SBL: AM64x: Updates for OSPI boot

OSPI parameter updates in the SBL to support OSPI boot at 133MHz.

Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>

diff --git a/packages/ti/boot/sbl/sbl_component.mk b/packages/ti/boot/sbl/sbl_component.mk
index dd28e3332fcfae0fe3a1d0b0ffc5d4d454c7ba55..597cca4519a33fcb92d78ab59a3700088ac8a9f2 100644 (file)
--- a/packages/ti/boot/sbl/sbl_component.mk
+++ b/packages/ti/boot/sbl/sbl_component.mk
@@ -1052,10 +1052,6 @@ export sbl_boot_xip_entry_SBL_APPIMAGEGEN
 # debugging and tuning performace knobs
 #SBL_CFLAGS += -DSBL_DISPLAY_PROFILE_INFO
 
-ifeq ($(SOC), am64x)
-SBL_CFLAGS += -DSBL_BYPASS_OSPI_DRIVER_FOR_SYSFW_DOWNLOAD
-endif
-
 ###### Use boot_perf_benchmark example#######
 ###### to fine tune the perf knobs  #########
 

diff --git a/packages/ti/boot/sbl/src/ospi/sbl_ospi.c b/packages/ti/boot/sbl/src/ospi/sbl_ospi.c
index 1df94aea065f84fbefa1d8a373c2f9d86e59d7ad..0e9dc80435eddcf8a589f69cf4cd90297e2e9ae9 100755 (executable)
--- a/packages/ti/boot/sbl/src/ospi/sbl_ospi.c
+++ b/packages/ti/boot/sbl/src/ospi/sbl_ospi.c
@@ -212,7 +212,7 @@ int32_t SBL_ReadSysfwImage(void **pBuffer, uint32_t num_bytes)
     /* Get default OSPI cfg */
     OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
 
-#if defined(SOC_J7200)
+#if defined(SOC_J7200) || defined(SOC_AM64X)
     ospi_cfg.funcClk = OSPI_MODULE_CLK_200M;
 #else
     ospi_cfg.funcClk = OSPI_MODULE_CLK_133M;
@@ -224,18 +224,18 @@ int32_t SBL_ReadSysfwImage(void **pBuffer, uint32_t num_bytes)
     /*        work with ROM, as ROM needs byte accesses       */
     ospi_cfg.dtrEnable = true;
 
-    /* OSPI clock is set to 200MHz by RBL on J7200 platform.
+    /* OSPI clock is set to 200MHz by RBL on J7200 & AM64X platforms.
      * PHY mode cannot be used until sysfw is loaded and OSPI clock is
      * configured to 133MHz.
      */
-#if defined(SIM_BUILD) || defined(SOC_J7200)
+#if defined(SIM_BUILD) || defined(SOC_J7200) || defined(SOC_AM64X)
     ospi_cfg.phyEnable = false;
 #endif
 
     /* Set the default SPI init configurations */
     OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
 
-#if defined(SOC_J7200)
+#if defined(SOC_J7200) || defined(SOC_AM64X)
     h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                         BOARD_OSPI_NOR_INSTANCE, NULL);
 #else
@@ -247,7 +247,7 @@ int32_t SBL_ReadSysfwImage(void **pBuffer, uint32_t num_bytes)
     {
         SBL_ADD_PROFILE_POINT;
 
-#if defined(SIM_BUILD) || defined(SOC_J7200)
+#if defined(SIM_BUILD) || defined(SOC_J7200) || defined(SOC_AM64X)
         /* Disable PHY pipeline mode */
         CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(ospi_cfg.baseAddr), FALSE);
 #else
@@ -255,7 +255,7 @@ int32_t SBL_ReadSysfwImage(void **pBuffer, uint32_t num_bytes)
         CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(ospi_cfg.baseAddr), TRUE);
 #endif
 
-#if defined(SOC_J7200)
+#if defined(SOC_J7200) || defined(SOC_AM64X)
         /* Until OSPI PHY + DMA is enabled at this early stage, the
          * ROM can more efficiently load the SYSFW directly from xSPI flash */
         if(pBuffer)
@@ -349,7 +349,7 @@ int32_t SBL_ospiInit(void *handle)
 
     ospi_cfg.dtrEnable = true;
 
-#if defined(SOC_J7200)
+#if defined(SOC_J7200) || defined(SOC_AM64X)
     ospi_cfg.funcClk = OSPI_MODULE_CLK_133M;
 #endif
 
@@ -368,7 +368,7 @@ int32_t SBL_ospiInit(void *handle)
     /* Set the default SPI init configurations */
     OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
 
-#if defined(SOC_J7200)
+#if defined(SOC_J7200) || defined(SOC_AM64X)
     h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                         BOARD_OSPI_NOR_INSTANCE, (void *)(enableTuning));
 #else
@@ -511,7 +511,7 @@ int32_t SBL_ospiLeaveConfigSPI()
 
     SBL_ADD_PROFILE_POINT;
 
-#if defined(SOC_J7200)
+#if defined(SOC_J7200) || defined(SOC_AM64X)
     h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                         BOARD_OSPI_NOR_INSTANCE, NULL);
 #else