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author | Sai Ramakurthi <s-ramakurthi@ti.com> | |
Wed, 25 Jan 2023 09:15:36 +0000 (14:45 +0530) | ||
committer | Sai Ramakurthi <s-ramakurthi@ti.com> | |
Wed, 25 Jan 2023 11:14:22 +0000 (16:44 +0530) |
j784s4
- Change OCMRAM_SBL_SYSFW memory to 0x41C83000 since 0x41C3E000 is used
by SBL
- Issue mentioned in the JIRA is a validation issue
Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
- Change OCMRAM_SBL_SYSFW memory to 0x41C83000 since 0x41C3E000 is used
by SBL
- Issue mentioned in the JIRA is a validation issue
Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/mcuXiplinker.lds
index cc5c674915455b3763aa81ff6b360226e583d6a6..fb5b8c3dacea6389623c9357eba3f812c56d8f8a 100644 (file)
/*----------------------------------------------------------------------------*/
-/* File: mcuXiplinker.cmd */
-/* Description: */
-/* Link command file for Maxwell Multicore Testcase */
+/* File: mcuXiplinker.cmd */
+/* Description: */
+/* Link command file to execute from OSPI flash memory */
/* */
-/* Platform: R5 Cores on AM65xx */
-/* (c) Texas Instruments 2019, All rights reserved. */
+/* Platform: R5 Cores on J7 */
+/* (c) Texas Instruments 2019-2023, All rights reserved. */
/*----------------------------------------------------------------------------*/
--entry_point=_sblTestResetVectors
MEMORY
{
OSPI_MCU1_CPU0_XIP_VEC (RIX) : origin=0x501c0000 length=0x40 /* 64B */
- OSPI_MCU1_CPU0_XIP_1 (RIX) : origin=0x501c0040 length=0x118
- OSPI_MCU1_CPU0_XIP_2 (RIX) : origin=0x501c0158 length=0x108
- OCMRAM_SBL_SYSFW (RWX) : origin=0x41C3E000 length=0x2000 - 0x800 /* 8KB */
+ OSPI_MCU1_CPU0_XIP_1 (RIX) : origin=0x501c0040 length=0x200
+ OSPI_MCU1_CPU0_XIP_2 (RIX) : origin=0x501c0240 length=0x200
+ OCMRAM_SBL_SYSFW (RWX) : origin=0x41C83000 length=0x2000 - 0x800 /* 8KB */
}
SECTIONS
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/mcuXiplinker.lds
index cc5c674915455b3763aa81ff6b360226e583d6a6..1cb17341f00488d731c02d5a5e8131160c94b3d4 100644 (file)
/*----------------------------------------------------------------------------*/
-/* File: mcuXiplinker.cmd */
-/* Description: */
-/* Link command file for Maxwell Multicore Testcase */
+/* File: mcuXiplinker.cmd */
+/* Description: */
+/* Link command file to execute from OSPI flash memory */
/* */
-/* Platform: R5 Cores on AM65xx */
-/* (c) Texas Instruments 2019, All rights reserved. */
+/* Platform: R5 Cores on J7 */
+/* (c) Texas Instruments 2019-2023, All rights reserved. */
/*----------------------------------------------------------------------------*/
--entry_point=_sblTestResetVectors
MEMORY
{
OSPI_MCU1_CPU0_XIP_VEC (RIX) : origin=0x501c0000 length=0x40 /* 64B */
- OSPI_MCU1_CPU0_XIP_1 (RIX) : origin=0x501c0040 length=0x118
- OSPI_MCU1_CPU0_XIP_2 (RIX) : origin=0x501c0158 length=0x108
- OCMRAM_SBL_SYSFW (RWX) : origin=0x41C3E000 length=0x2000 - 0x800 /* 8KB */
+ OSPI_MCU1_CPU0_XIP_1 (RIX) : origin=0x501c0040 length=0x200
+ OSPI_MCU1_CPU0_XIP_2 (RIX) : origin=0x501c0240 length=0x200
+ OCMRAM_SBL_SYSFW (RWX) : origin=0x41C83000 length=0x2000 - 0x800 /* 8KB */
}
SECTIONS
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j721s2/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j721s2/mcuXiplinker.lds
index 60c02da35ac86b532d2ce4096ab7ac04867abbba..7596d3d717478ee47ad00298506056975187d5a3 100644 (file)
/*----------------------------------------------------------------------------*/
-/* File: mcuXiplinker.cmd */
-/* Description: */
-/* Link command file for Maxwell Multicore Testcase */
+/* File: mcuXiplinker.cmd */
+/* Description: */
+/* Link command file to execute from OSPI flash memory */
/* */
-/* Platform: R5 Cores on AM65xx */
-/* (c) Texas Instruments 2019, All rights reserved. */
+/* Platform: R5 Cores on J7 */
+/* (c) Texas Instruments 2019-2023, All rights reserved. */
/*----------------------------------------------------------------------------*/
--entry_point=_sblTestResetVectors
MEMORY
{
- OSPI_MCU1_CPU0_XIP_VEC : origin=0x501c0000 length=0x40 /* 64B */
- OSPI_MCU1_CPU0_XIP : origin=0x501c0040 length=0x2000 - 0x40 /* 8KB - 64B*/
- OCMRAM_SBL_SYSFW : origin=0x41C3E000 length=0x2000 - 0x800 /* 8KB */
+ OSPI_MCU1_CPU0_XIP_VEC (RIX) : origin=0x501c0000 length=0x40 /* 64B */
+ OSPI_MCU1_CPU0_XIP_1 (RIX) : origin=0x501c0040 length=0x200
+ OSPI_MCU1_CPU0_XIP_2 (RIX) : origin=0x501c0240 length=0x200
+ OCMRAM_SBL_SYSFW (RWX) : origin=0x41C83000 length=0x2000 - 0x800 /* 8KB */
}
SECTIONS
{
- .rstvectors : {} palign(8) > OSPI_MCU1_CPU0_XIP_VEC
- .sbl_mcu_1_0_resetvector : {} palign(8) > OSPI_MCU1_CPU0_XIP
- .stack : {} palign(8) > OCMRAM_SBL_SYSFW
+ .rstvectors : {} palign(8) > OSPI_MCU1_CPU0_XIP_VEC
+ .text : {} palign(8) > OSPI_MCU1_CPU0_XIP_1
+ .rodata : {} palign(8) > OSPI_MCU1_CPU0_XIP_1
+ .sbl_mcu_1_0_resetvector : {} palign(8) > OSPI_MCU1_CPU0_XIP_2
+ .stack : {} palign(8) > OCMRAM_SBL_SYSFW
}
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j784s4/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j784s4/mcuXiplinker.lds
index 2e225402b50644dd12c3970938c3e5e3ea13d97d..a3fb9f68ae3d5a410932f13be6a24d114a011179 100644 (file)
/*----------------------------------------------------------------------------*/
-/* File: mcuXiplinker.cmd */
-/* Description: */
-/* Link command file for Maxwell Multicore Testcase */
+/* File: mcuXiplinker.cmd */
+/* Description: */
+/* Link command file to execute from OSPI flash memory */
/* */
-/* Platform: R5 Cores on AM65xx */
-/* (c) Texas Instruments 2022, All rights reserved. */
+/* Platform: R5 Cores on J7 */
+/* (c) Texas Instruments 2022-2023, All rights reserved. */
/*----------------------------------------------------------------------------*/
--entry_point=_sblTestResetVectors
MEMORY
{
- OSPI_MCU1_CPU0_XIP_VEC : origin=0x501c0000 length=0x40 /* 64B */
- OSPI_MCU1_CPU0_XIP : origin=0x501c0040 length=0x2000 - 0x40 /* 8KB - 64B*/
- OCMRAM_SBL_SYSFW : origin=0x41C3E000 length=0x2000 - 0x800 /* 8KB */
+ OSPI_MCU1_CPU0_XIP_VEC (RIX) : origin=0x501c0000 length=0x40 /* 64B */
+ OSPI_MCU1_CPU0_XIP_1 (RIX) : origin=0x501c0040 length=0x200
+ OSPI_MCU1_CPU0_XIP_2 (RIX) : origin=0x501c0240 length=0x200
+ OCMRAM_SBL_SYSFW (RWX) : origin=0x41C83000 length=0x2000 - 0x800 /* 8KB */
}
SECTIONS
{
.rstvectors : {} palign(8) > OSPI_MCU1_CPU0_XIP_VEC
- .sbl_mcu_1_0_resetvector : {} palign(8) > OSPI_MCU1_CPU0_XIP
+ .text : {} palign(8) > OSPI_MCU1_CPU0_XIP_1
+ .rodata : {} palign(8) > OSPI_MCU1_CPU0_XIP_1
+ .sbl_mcu_1_0_resetvector : {} palign(8) > OSPI_MCU1_CPU0_XIP_2
.stack : {} palign(8) > OCMRAM_SBL_SYSFW
}