Merge pull request #40 in PROCESSOR-SDK/pdk from PRSDK-7455 to master
authorMahesh Radhakrishnan <a0875154@ti.com>
Wed, 4 Dec 2019 17:49:55 +0000 (11:49 -0600)
committerMahesh Radhakrishnan <a0875154@ti.com>
Wed, 4 Dec 2019 17:49:55 +0000 (11:49 -0600)
* commit '13124fa6079d8b5cef83c123ddcb88c240ba4711':
  mcasp: PRSDK-7455: Example fix on j721e/c66x

115 files changed:
.gitignore [new file with mode: 0644]
packages/ti/board/board_cfg.h [changed mode: 0755->0644]
packages/ti/board/board_component.mk [changed mode: 0755->0644]
packages/ti/board/build/makefile.mk [changed mode: 0755->0644]
packages/ti/board/diag/pcie/build/am65xx_evm/armv8/makefile
packages/ti/board/src/idkAM437x/idkAM437x_info.c
packages/ti/board/src/j7200_evm/AM7xxx_pinmux.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data_gesi.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data_gesi_cpsw9g.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data_info.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_clock.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_control.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_ddr.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_ethernet_config.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_i2c_io_exp.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_info.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_init.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_lld_init.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_mmr.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_pinmux.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_pll.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_power.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_serdes_cfg.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/board_utils.c [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_cfg.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_clock.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_control.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_ddr.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_ethernet_config.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_i2c_io_exp.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_internal.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_pinmux.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_pll.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_power.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_serdes_cfg.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/board_utils.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/include/pinmux.h [new file with mode: 0644]
packages/ti/board/src/j7200_evm/src_files_j7200_evm.mk [new file with mode: 0644]
packages/ti/board/src/j721e_evm/board_clock.c
packages/ti/board/utils/uniflash/target/build/uart_make.mk
packages/ti/boot/sbl/src/ospi/sbl_ospi.c
packages/ti/build/makerules/component.mk
packages/ti/drv/cal/cal_component.mk
packages/ti/drv/emac/firmware/icss_dualmac/src/hd_helper.h
packages/ti/drv/emac/firmware/icss_dualmac/src/pru.cmd
packages/ti/drv/emac/firmware/icss_dualmac/src/rtu_v2.asm
packages/ti/drv/emac/firmware/icss_dualmac/src/rxl2_txl2.asm
packages/ti/drv/i2c/build/makefile.mk [changed mode: 0755->0644]
packages/ti/drv/i2c/build/makefile_profile.mk
packages/ti/drv/i2c/i2c_component.mk [changed mode: 0755->0644]
packages/ti/drv/i2c/package.xs [changed mode: 0755->0644]
packages/ti/drv/i2c/soc/I2C_soc.h
packages/ti/drv/i2c/soc/j7200/I2C_soc.c [new file with mode: 0644]
packages/ti/drv/i2c/src/src_files_common.mk
packages/ti/drv/ipc/soc/V0/ipc_soc.c
packages/ti/drv/ipc/soc/V1/ipc_soc.c
packages/ti/drv/ipc/soc/ipc_soc.h
packages/ti/drv/mcasp/example/j721e/src/mcasp_cfg.c
packages/ti/drv/mmcsd/soc/MMCSD_soc.h
packages/ti/drv/sciclient/include/sciclient_soc.h [changed mode: 0755->0644]
packages/ti/drv/sciclient/include/tisci/tisci_includes.h
packages/ti/drv/sciclient/package.xs
packages/ti/drv/sciclient/sciclient_component.mk [changed mode: 0755->0644]
packages/ti/drv/sciclient/soc/V1/sciclient_fmwMsgParams.h [changed mode: 0755->0644]
packages/ti/drv/sciclient/soc/V1/sciclient_fmwSecureProxyMap.c [changed mode: 0755->0644]
packages/ti/drv/sciclient/soc/sciclient_soc_priv.h
packages/ti/drv/sciclient/src/makefile [changed mode: 0755->0644]
packages/ti/drv/sciclient/src/sciclient.c [changed mode: 0755->0644]
packages/ti/drv/sciclient/src/sciclient_priv.h [changed mode: 0755->0644]
packages/ti/drv/sciclient/src/sciclient_rm_csl.c [changed mode: 0755->0644]
packages/ti/drv/uart/build/makefile.mk [changed mode: 0755->0644]
packages/ti/drv/uart/build/makefile_dma.mk
packages/ti/drv/uart/build/makefile_dma_profile.mk
packages/ti/drv/uart/build/makefile_profile.mk
packages/ti/drv/uart/package.xs
packages/ti/drv/uart/soc/j7200/UART_soc.c [new file with mode: 0644]
packages/ti/drv/uart/src/src_files_common.mk [changed mode: 0755->0644]
packages/ti/drv/uart/test/j7200/mpu.xs [new file with mode: 0644]
packages/ti/drv/uart/test/j7200/uartUnitTest_a72.cfg [new file with mode: 0644]
packages/ti/drv/uart/test/j7200/uartUnitTest_r5.cfg [new file with mode: 0644]
packages/ti/drv/uart/test/makefile [changed mode: 0755->0644]
packages/ti/drv/uart/test/src/UART_board.h
packages/ti/drv/uart/test/src/main_uart_test.c [changed mode: 0755->0644]
packages/ti/drv/uart/uart_component.mk [changed mode: 0755->0644]
packages/ti/drv/udma/include/udma_rm.h
packages/ti/drv/udma/package.xs
packages/ti/drv/udma/soc/V1/udma_soc.c [changed mode: 0755->0644]
packages/ti/drv/udma/soc/V2/udma_rmcfg.c [new file with mode: 0644]
packages/ti/drv/udma/soc/V2/udma_soc.c [new file with mode: 0644]
packages/ti/drv/udma/soc/V2/udma_soc.h [new file with mode: 0644]
packages/ti/drv/udma/soc/udma_soc.h
packages/ti/drv/udma/src/makefile
packages/ti/drv/udma/src/udma_ch.c
packages/ti/drv/udma/src/udma_rm.c
packages/ti/drv/udma/udma.h
packages/ti/drv/udma/udma_component.mk [changed mode: 0755->0644]
packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.c [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.h [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/src/udma_test.h
packages/ti/osal/build/makefile_nonos.mk
packages/ti/osal/osal_component.mk [changed mode: 0755->0644]
packages/ti/osal/soc/j7200/TimerP_default.c [new file with mode: 0644]
packages/ti/osal/soc/j7200/bios_mmu.c [new file with mode: 0644]
packages/ti/osal/soc/j7200/osal_soc.h [new file with mode: 0644]
packages/ti/osal/soc/osal_soc.h
packages/ti/osal/src/nonos/HwiP_nonos.c [changed mode: 0755->0644]
packages/ti/osal/src/nonos/Nonos_config.h [changed mode: 0755->0644]
packages/ti/osal/src/nonos/timer/v1/TimerP_nonos.c [changed mode: 0755->0644]
packages/ti/osal/src/src_common_nonos.mk
packages/ti/osal/src/src_common_tirtos.mk
packages/ti/osal/src/tirtos/TimerP_tirtos.c [changed mode: 0755->0644]
packages/ti/osal/test/baremetal/makefile [changed mode: 0755->0644]
packages/ti/osal/test/src/main_osal_test.c [changed mode: 0755->0644]
packages/ti/osal/test/sysbios_unit_test/makefile [changed mode: 0755->0644]

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..17a7c66
--- /dev/null
@@ -0,0 +1,9 @@
+docs/
+internal_docs/
+packages/ti/binary/
+packages/ti/csl/
+packages/ti/drv/cpsw/
+packages/ti/drv/csirx/
+packages/ti/drv/emac/firmware/icss_dualmac/src/version_file.h
+packages/ti/drv/pm/
+packages/ti/drv/vhwa/
old mode 100755 (executable)
new mode 100644 (file)
index 5e1614a..9701165
@@ -131,6 +131,9 @@ extern "C" {
 #elif defined (j721e_evm)
 #include <ti/board/src/j721e_evm/include/board_cfg.h>
 
+#elif defined (j7200_evm)
+#include <ti/board/src/j7200_evm/include/board_cfg.h>
+
 #endif
 
 #ifdef __cplusplus
old mode 100755 (executable)
new mode 100644 (file)
index 8dee265..74ff6f3
@@ -67,7 +67,7 @@
 ifeq ($(board_component_make_include), )
 
 board_lib_BOARDLIST       = evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G \
-                            evmC6678 evmC6657 tda2xx-evm evmDRA75x tda2ex-evm evmDRA72x tda3xx-evm evmDRA78x evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk j721e_sim j721e_qt j721e_evm
+                            evmC6678 evmC6657 tda2xx-evm evmDRA75x tda2ex-evm evmDRA72x tda3xx-evm evmDRA78x evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk j721e_sim j721e_qt j721e_evm j7200_evm
 board_lib_tda2xx_CORELIST = a15_0 ipu1_0 c66x
 board_lib_tda2ex_CORELIST = a15_0 ipu1_0 c66x
 board_lib_tda3xx_CORELIST = ipu1_0 c66x
@@ -90,6 +90,7 @@ board_lib_omapl137_CORELIST = arm9_0 c674x
 board_lib_omapl138_CORELIST = arm9_0 c674x
 board_lib_am65xx_CORELIST = mpu1_0 mcu1_0
 board_lib_j721e_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1
+board_lib_j7200_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
 
 
 ############################
old mode 100755 (executable)
new mode 100644 (file)
index b8abc12..60cbbf2
@@ -43,7 +43,7 @@ ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM
 SRCS_COMMON += board.c
 endif
 
-ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x evmDRA72x evmDRA75x evmDRA78x evmTDAxx j721e_sim j721e_qt))
+ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x evmDRA72x evmDRA75x evmDRA78x evmTDAxx j721e_sim j721e_qt j7200_evm))
 # Board stub function enabled for all the boards except evmK2G
 SRCS_COMMON += boardStub.c
 endif
@@ -79,6 +79,15 @@ PACKAGE_SRCS_COMMON += src/$(BOARD)
 PACKAGE_SRCS_COMMON += src/devices
 endif
  
+ifeq ($(BOARD),$(filter $(BOARD), j7200_evm))
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk
+include $(PDK_BOARD_COMP_PATH)/src/flash/src_files_flash.mk
+include $(PDK_BOARD_COMP_PATH)/src/devices/src_files_devices.mk
+PACKAGE_SRCS_COMMON += src/$(BOARD)
+PACKAGE_SRCS_COMMON += src/devices
+endif
+
 ifeq ($(BOARD),$(filter $(BOARD), evmAM572x idkAM571x idkAM572x idkAM574x))
 include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk
 include $(PDK_BOARD_COMP_PATH)/src/src_files_lld.mk
@@ -138,7 +147,7 @@ INCLUDE_INTERNAL_INTERFACES = csl
 
 PACKAGE_SRCS_COMMON += makefile board_component.mk board.h \
                        board_cfg.h build/makefile.mk
-ifeq ($(BOARD),$(filter $(BOARD), j721e_sim j721e_qt j721e_evm))
+ifeq ($(BOARD),$(filter $(BOARD), j721e_sim j721e_qt j721e_evm j7200_evm))
 PACKAGE_SRCS_COMMON += src/board.c src/boardStub.c src/Module.xs \
                        src/src_files_lld.mk src/src_files_starterware.mk
 else
index 5652fdd01bc6b983eec03d6ba5b078001d353fca..de3319527422f7206fce9febb7314d6038969184 100644 (file)
@@ -104,7 +104,7 @@ ENTRY_SRC = diag_entry.S
 DIAG_SRC = diag_common_cfg.c
 
 # FLAGS for the SourceFiles
-CFLAGS += -DDIAG_$(TESTMODE)-Wall -DDIAG_$(MODE)
+CFLAGS += -DDIAG_$(TESTMODE) -Wall -DDIAG_$(MODE)
 SRC_CFLAGS = -I. $(CFLAGS) -g -gdwarf-3 -gstrict-dwarf -Wall 
 
 # Make Rule for the SRC Files
index 4045b4e1192fba6e6eb57737f5546651950fa169..e7f162d9b8db109b8a11514dc215cf5c4123e61a 100644 (file)
@@ -134,7 +134,7 @@ Board_STATUS Board_writeIDInfo(Board_IDInfo *info) {
     I2C_Transaction i2cTransaction;
     I2C_Handle handle = NULL;
     char txBuf[2+BOARD_EEPROM_HEADER_LENGTH+BOARD_EEPROM_BOARD_NAME_LENGTH
-        +BOARD_EEPROM_VERSION_ADDR+BOARD_EEPROM_SERIAL_NO_LENGTH];
+        +BOARD_EEPROM_VERSION_LENGTH+BOARD_EEPROM_SERIAL_NO_LENGTH];
     bool status;
     int i, idx;
 
@@ -152,7 +152,7 @@ Board_STATUS Board_writeIDInfo(Board_IDInfo *info) {
 
     i2cTransaction.slaveAddress = BOARD_I2C_EEPROM_ADDR;
     i2cTransaction.writeBuf = (uint8_t *)&txBuf[0];
-    i2cTransaction.writeCount = 2;
+    i2cTransaction.writeCount = 2+BOARD_EEPROM_HEADER_LENGTH+BOARD_EEPROM_BOARD_NAME_LENGTH+BOARD_EEPROM_VERSION_LENGTH+BOARD_EEPROM_SERIAL_NO_LENGTH;
 
     /* write header info */
     txBuf[0] = (char)(((uint32_t) 0xFF00 & BOARD_EEPROM_HEADER_ADDR)>>8);
@@ -161,7 +161,7 @@ Board_STATUS Board_writeIDInfo(Board_IDInfo *info) {
     idx = 2;
     for (i = 0; i<BOARD_EEPROM_HEADER_LENGTH; i++) txBuf[idx++] = info->header[i];
     for (i = 0; i<BOARD_EEPROM_BOARD_NAME_LENGTH; i++) txBuf[idx++] = info->boardName[i];
-    for (i = 0; i<BOARD_EEPROM_VERSION_ADDR; i++) txBuf[idx++] = info->version[i];
+    for (i = 0; i<BOARD_EEPROM_VERSION_LENGTH; i++) txBuf[idx++] = info->version[i];
     for (i = 0; i<BOARD_EEPROM_SERIAL_NO_LENGTH; i++) txBuf[idx++] = info->serialNum[i];
     status = I2C_transfer(handle, &i2cTransaction);
     if (status == false)
diff --git a/packages/ti/board/src/j7200_evm/AM7xxx_pinmux.h b/packages/ti/board/src/j7200_evm/AM7xxx_pinmux.h
new file mode 100644 (file)
index 0000000..246c18e
--- /dev/null
@@ -0,0 +1,344 @@
+/**\r
+ * Note: This file was auto-generated by TI PinMux on 5/10/2019.\r
+ *\r
+ * \file   AM65xx_pinmux.h\r
+ *\r
+ * \brief  This file contains pad configure register offsets and bit-field \r
+ *         value macros for different configurations,\r
+ *\r
+ *           BIT[21]           TXDISABLE               disable the pin's output driver\r
+ *           BIT[18]           RXACTIVE                enable the pin's input buffer (typically kept enabled)\r
+ *           BIT[17]           PULLTYPESEL             set the iternal resistor pull direction high or low (if enabled)\r
+ *           BIT[16]           PULLUDEN                internal resistor disable (0 = enabled / 1 = disabled)\r
+ *           BIT[3:0]          MUXMODE                 select the desired function on the given pin\r
+ *\r
+ *  \copyright Copyright (CU) 2019 Texas Instruments Incorporated - \r
+ *             http://www.ti.com/\r
+ */\r
+\r
+#ifndef _AM7XXX_PIN_MUX_H_\r
+#define _AM7XXX_PIN_MUX_H_\r
+\r
+/* ========================================================================== */\r
+/*                             Include Files                                  */\r
+/* ========================================================================== */\r
+\r
+#include <ti/board/src/j7200_evm/include/pinmux.h>\r
+#include <ti/csl/csl_types.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* ========================================================================== */\r
+/*                           Macros & Typedefs                                */\r
+/* ========================================================================== */\r
+#define PIN_MODE(mode)                 (mode)\r
+#define PINMUX_END                      (-1)\r
+\r
+/** \brief Active mode configurations */\r
+/** \brief Resistor enable */\r
+#define PIN_PULL_DISABLE                (0x1U << 16U)\r
+/** \brief Pull direction */\r
+#define        PIN_PULL_DIRECTION              (0x1U << 17U)\r
+/** \brief Receiver enable */\r
+#define        PIN_INPUT_ENABLE                (0x1U << 18U)\r
+/** \brief Driver disable */\r
+#define        PIN_OUTPUT_DISABLE              (0x1U << 21U)\r
+/** \brief Wakeup enable */\r
+#define        PIN_WAKEUP_ENABLE               (0x1U << 29U)\r
+\r
+/** \brief Pad config register offset in control module */\r
+enum pinMainOffsets\r
+{\r
+    PIN_EXTINTN                = 0x0U,\r
+    PIN_PRG1_PRU0_GPO0         = 0x4U,\r
+    PIN_PRG1_PRU0_GPO1         = 0x8U,\r
+    PIN_PRG1_PRU0_GPO2         = 0xCU,\r
+    PIN_PRG1_PRU0_GPO3         = 0x10U,\r
+    PIN_PRG1_PRU0_GPO4         = 0x14U,\r
+    PIN_PRG1_PRU0_GPO5         = 0x18U,\r
+    PIN_PRG1_PRU0_GPO6         = 0x1CU,\r
+    PIN_PRG1_PRU0_GPO7         = 0x20U,\r
+    PIN_PRG1_PRU0_GPO8         = 0x24U,\r
+    PIN_PRG1_PRU0_GPO9         = 0x28U,\r
+    PIN_PRG1_PRU0_GPO10        = 0x2CU,\r
+    PIN_PRG1_PRU0_GPO11        = 0x30U,\r
+    PIN_PRG1_PRU0_GPO12        = 0x34U,\r
+    PIN_PRG1_PRU0_GPO13        = 0x38U,\r
+    PIN_PRG1_PRU0_GPO14        = 0x3CU,\r
+    PIN_PRG1_PRU0_GPO15        = 0x40U,\r
+    PIN_PRG1_PRU0_GPO16        = 0x44U,\r
+    PIN_PRG1_PRU0_GPO17        = 0x4CU,\r
+    PIN_PRG1_PRU0_GPO18        = 0x50U,\r
+    PIN_PRG1_PRU0_GPO19        = 0x54U,\r
+    PIN_PRG1_PRU1_GPO0         = 0x58U,\r
+    PIN_PRG1_PRU1_GPO1         = 0x5CU,\r
+    PIN_PRG1_PRU1_GPO2         = 0x60U,\r
+    PIN_PRG1_PRU1_GPO3         = 0x64U,\r
+    PIN_PRG1_PRU1_GPO4         = 0x68U,\r
+    PIN_PRG1_PRU1_GPO5         = 0x6CU,\r
+    PIN_PRG1_PRU1_GPO6         = 0x70U,\r
+    PIN_PRG1_PRU1_GPO7         = 0x74U,\r
+    PIN_PRG1_PRU1_GPO8         = 0x78U,\r
+    PIN_PRG1_PRU1_GPO9         = 0x7CU,\r
+    PIN_PRG1_PRU1_GPO10        = 0x80U,\r
+    PIN_PRG1_PRU1_GPO11        = 0x84U,\r
+    PIN_PRG1_PRU1_GPO12        = 0x88U,\r
+    PIN_PRG1_PRU1_GPO13        = 0x8CU,\r
+    PIN_PRG1_PRU1_GPO14        = 0x90U,\r
+    PIN_PRG1_PRU1_GPO15        = 0x94U,\r
+    PIN_PRG1_PRU1_GPO16        = 0x98U,\r
+    PIN_PRG1_PRU1_GPO17        = 0x9CU,\r
+    PIN_PRG1_PRU1_GPO18        = 0xA0U,\r
+    PIN_PRG1_PRU1_GPO19        = 0xA4U,\r
+    PIN_PRG1_MDIO0_MDIO        = 0xA8U,\r
+    PIN_PRG1_MDIO0_MDC         = 0xACU,\r
+    PIN_PRG0_PRU0_GPO0         = 0xB0U,\r
+    PIN_PRG0_PRU0_GPO1         = 0xB4U,\r
+    PIN_PRG0_PRU0_GPO2         = 0xB8U,\r
+    PIN_PRG0_PRU0_GPO3         = 0xBCU,\r
+    PIN_PRG0_PRU0_GPO4         = 0xC0U,\r
+    PIN_PRG0_PRU0_GPO5         = 0xC4U,\r
+    PIN_PRG0_PRU0_GPO6         = 0xC8U,\r
+    PIN_PRG0_PRU0_GPO7         = 0xCCU,\r
+    PIN_PRG0_PRU0_GPO8         = 0xD0U,\r
+    PIN_PRG0_PRU0_GPO9         = 0xD4U,\r
+    PIN_PRG0_PRU0_GPO10        = 0xD8U,\r
+    PIN_PRG0_PRU0_GPO11        = 0xDCU,\r
+    PIN_PRG0_PRU0_GPO12        = 0xE0U,\r
+    PIN_PRG0_PRU0_GPO13        = 0xE4U,\r
+    PIN_PRG0_PRU0_GPO14        = 0xE8U,\r
+    PIN_PRG0_PRU0_GPO15        = 0xECU,\r
+    PIN_PRG0_PRU0_GPO16        = 0xF0U,\r
+    PIN_PRG0_PRU0_GPO17        = 0xF4U,\r
+    PIN_PRG0_PRU0_GPO18        = 0xF8U,\r
+    PIN_PRG0_PRU0_GPO19        = 0xFCU,\r
+    PIN_PRG0_PRU1_GPO0         = 0x100U,\r
+    PIN_PRG0_PRU1_GPO1         = 0x104U,\r
+    PIN_PRG0_PRU1_GPO2         = 0x108U,\r
+    PIN_PRG0_PRU1_GPO3         = 0x10CU,\r
+    PIN_PRG0_PRU1_GPO4         = 0x110U,\r
+    PIN_PRG0_PRU1_GPO5         = 0x114U,\r
+    PIN_PRG0_PRU1_GPO6         = 0x118U,\r
+    PIN_PRG0_PRU1_GPO7         = 0x11CU,\r
+    PIN_PRG0_PRU1_GPO8         = 0x120U,\r
+    PIN_PRG0_PRU1_GPO9         = 0x124U,\r
+    PIN_PRG0_PRU1_GPO10        = 0x128U,\r
+    PIN_PRG0_PRU1_GPO11        = 0x12CU,\r
+    PIN_PRG0_PRU1_GPO12        = 0x130U,\r
+    PIN_PRG0_PRU1_GPO13        = 0x134U,\r
+    PIN_PRG0_PRU1_GPO14        = 0x138U,\r
+    PIN_PRG0_PRU1_GPO15        = 0x13CU,\r
+    PIN_PRG0_PRU1_GPO16        = 0x140U,\r
+    PIN_PRG0_PRU1_GPO17        = 0x144U,\r
+    PIN_PRG0_PRU1_GPO18        = 0x148U,\r
+    PIN_PRG0_PRU1_GPO19        = 0x14CU,\r
+    PIN_PRG0_MDIO0_MDIO        = 0x150U,\r
+    PIN_PRG0_MDIO0_MDC         = 0x154U,\r
+    PIN_RGMII5_TX_CTL          = 0x158U,\r
+    PIN_RGMII5_RX_CTL          = 0x15CU,\r
+    PIN_RGMII5_TD3             = 0x160U,\r
+    PIN_RGMII5_TD2             = 0x164U,\r
+    PIN_RGMII5_TD1             = 0x168U,\r
+    PIN_RGMII5_TD0             = 0x16CU,\r
+    PIN_RGMII5_TXC             = 0x170U,\r
+    PIN_RGMII5_RXC             = 0x174U,\r
+    PIN_RGMII5_RD3             = 0x178U,\r
+    PIN_RGMII5_RD2             = 0x17CU,\r
+    PIN_RGMII5_RD1             = 0x180U,\r
+    PIN_RGMII5_RD0             = 0x184U,\r
+    PIN_RGMII6_TX_CTL          = 0x188U,\r
+    PIN_RGMII6_RX_CTL          = 0x18CU,\r
+    PIN_RGMII6_TD3             = 0x190U,\r
+    PIN_RGMII6_TD2             = 0x194U,\r
+    PIN_RGMII6_TD1             = 0x198U,\r
+    PIN_RGMII6_TD0             = 0x19CU,\r
+    PIN_RGMII6_TXC             = 0x1A0U,\r
+    PIN_RGMII6_RXC             = 0x1A4U,\r
+    PIN_RGMII6_RD3             = 0x1A8U,\r
+    PIN_RGMII6_RD2             = 0x1ACU,\r
+    PIN_RGMII6_RD1             = 0x1B0U,\r
+    PIN_RGMII6_RD0             = 0x1B4U,\r
+    PIN_MDIO0_MDIO             = 0x1B8U,\r
+    PIN_MDIO0_MDC              = 0x1BCU,\r
+    PIN_SPI0_CS0               = 0x1C0U,\r
+    PIN_SPI0_CS1               = 0x1C4U,\r
+    PIN_SPI0_CLK               = 0x1C8U,\r
+    PIN_SPI0_D0                = 0x1CCU,\r
+    PIN_SPI0_D1                = 0x1D0U,\r
+    PIN_SPI1_CS0               = 0x1D4U,\r
+    PIN_SPI1_CS1               = 0x1D8U,\r
+    PIN_SPI1_CLK               = 0x1DCU,\r
+    PIN_SPI1_D0                = 0x1E0U,\r
+    PIN_SPI1_D1                = 0x1E4U,\r
+    PIN_UART0_RXD              = 0x1E8U,\r
+    PIN_UART0_TXD              = 0x1ECU,\r
+    PIN_UART0_CTSN             = 0x1F0U,\r
+    PIN_UART0_RTSN             = 0x1F4U,\r
+    PIN_UART1_RXD              = 0x1F8U,\r
+    PIN_UART1_TXD              = 0x1FCU,\r
+    PIN_UART1_CTSN             = 0x200U,\r
+    PIN_UART1_RTSN             = 0x204U,\r
+    PIN_MCAN0_RX               = 0x208U,\r
+    PIN_MCAN0_TX               = 0x20CU,\r
+    PIN_MCAN1_RX               = 0x210U,\r
+    PIN_MCAN1_TX               = 0x214U,\r
+    PIN_I3C0_SCL               = 0x218U,\r
+    PIN_I3C0_SDA               = 0x21CU,\r
+    PIN_I2C0_SCL               = 0x220U,\r
+    PIN_I2C0_SDA               = 0x224U,\r
+    PIN_I2C1_SCL               = 0x228U,\r
+    PIN_I2C1_SDA               = 0x22CU,\r
+    PIN_ECAP0_IN_APWM_OUT      = 0x230U,\r
+    PIN_EXT_REFCLK1            = 0x234U,\r
+    PIN_TIMER_IO0              = 0x238U,\r
+    PIN_TIMER_IO1              = 0x23CU,\r
+    PIN_MMC1_DAT3              = 0x240U,\r
+    PIN_MMC1_DAT2              = 0x244U,\r
+    PIN_MMC1_DAT1              = 0x248U,\r
+    PIN_MMC1_DAT0              = 0x24CU,\r
+    PIN_MMC1_CLK               = 0x250U,\r
+    PIN_MMC1_CMD               = 0x254U,\r
+    PIN_MMC1_SDCD              = 0x258U,\r
+    PIN_MMC1_SDWP              = 0x25CU,\r
+    PIN_MMC2_DAT3              = 0x260U,\r
+    PIN_MMC2_DAT2              = 0x264U,\r
+    PIN_MMC2_DAT1              = 0x268U,\r
+    PIN_MMC2_DAT0              = 0x26CU,\r
+    PIN_MMC2_CLK               = 0x270U,\r
+    PIN_MMC2_CMD               = 0x274U,\r
+    PIN_RESETSTATZ             = 0x278U,\r
+    PIN_PORZ_OUT               = 0x27CU,\r
+    PIN_SOC_SAFETY_ERRORN      = 0x280U,\r
+    PIN_TDI                    = 0x284U,\r
+    PIN_TDO                    = 0x288U,\r
+    PIN_TMS                    = 0x28CU,\r
+    PIN_USB0_DRVVBUS           = 0x290U,\r
+    PIN_MLB0_MLBSP             = 0x294U,\r
+    PIN_MLB0_MLBSN             = 0x298U,\r
+    PIN_MLB0_MLBDP             = 0x29CU,\r
+    PIN_MLB0_MLBDN             = 0x2A0U,\r
+    PIN_MLB0_MLBCP             = 0x2A4U,\r
+    PIN_MLB0_MLBCN             = 0x2A8U,\r
+    PIN_MMC1_CLKLB             = 0x2ACU,\r
+};\r
+\r
+enum pinWkupOffsets\r
+{\r
+    PIN_MCU_OSPI0_CLK          = 0x0U,\r
+    PIN_MCU_OSPI0_LBCLKO       = 0x4U,\r
+    PIN_MCU_OSPI0_DQS          = 0x8U,\r
+    PIN_MCU_OSPI0_D0           = 0xCU,\r
+    PIN_MCU_OSPI0_D1           = 0x10U,\r
+    PIN_MCU_OSPI0_D2           = 0x14U,\r
+    PIN_MCU_OSPI0_D3           = 0x18U,\r
+    PIN_MCU_OSPI0_D4           = 0x1CU,\r
+    PIN_MCU_OSPI0_D5           = 0x20U,\r
+    PIN_MCU_OSPI0_D6           = 0x24U,\r
+    PIN_MCU_OSPI0_D7           = 0x28U,\r
+    PIN_MCU_OSPI0_CSN0         = 0x2CU,\r
+    PIN_MCU_OSPI0_CSN1         = 0x30U,\r
+    PIN_MCU_OSPI1_CLK          = 0x34U,\r
+    PIN_MCU_OSPI1_LBCLKO       = 0x38U,\r
+    PIN_MCU_OSPI1_DQS          = 0x3CU,\r
+    PIN_MCU_OSPI1_D0           = 0x40U,\r
+    PIN_MCU_OSPI1_D1           = 0x44U,\r
+    PIN_MCU_OSPI1_D2           = 0x48U,\r
+    PIN_MCU_OSPI1_D3           = 0x4CU,\r
+    PIN_MCU_OSPI1_CSN0         = 0x50U,\r
+    PIN_MCU_OSPI1_CSN1         = 0x54U,\r
+    PIN_MCU_RGMII1_TX_CTL      = 0x58U,\r
+    PIN_MCU_RGMII1_RX_CTL      = 0x5CU,\r
+    PIN_MCU_RGMII1_TD3         = 0x60U,\r
+    PIN_MCU_RGMII1_TD2         = 0x64U,\r
+    PIN_MCU_RGMII1_TD1         = 0x68U,\r
+    PIN_MCU_RGMII1_TD0         = 0x6CU,\r
+    PIN_MCU_RGMII1_TXC         = 0x70U,\r
+    PIN_MCU_RGMII1_RXC         = 0x74U,\r
+    PIN_MCU_RGMII1_RD3         = 0x78U,\r
+    PIN_MCU_RGMII1_RD2         = 0x7CU,\r
+    PIN_MCU_RGMII1_RD1         = 0x80U,\r
+    PIN_MCU_RGMII1_RD0         = 0x84U,\r
+    PIN_MCU_MDIO0_MDIO         = 0x88U,\r
+    PIN_MCU_MDIO0_MDC          = 0x8CU,\r
+    PIN_MCU_SPI0_CLK           = 0x90U,\r
+    PIN_MCU_SPI0_D0            = 0x94U,\r
+    PIN_MCU_SPI0_D1            = 0x98U,\r
+    PIN_MCU_SPI0_CS0           = 0x9CU,\r
+    PIN_WKUP_UART0_RXD         = 0xA0U,\r
+    PIN_WKUP_UART0_TXD         = 0xA4U,\r
+    PIN_MCU_MCAN0_TX           = 0xA8U,\r
+    PIN_MCU_MCAN0_RX           = 0xACU,\r
+    PIN_WKUP_GPIO0_0           = 0xB0U,\r
+    PIN_WKUP_GPIO0_1           = 0xB4U,\r
+    PIN_WKUP_GPIO0_2           = 0xB8U,\r
+    PIN_WKUP_GPIO0_3           = 0xBCU,\r
+    PIN_WKUP_GPIO0_4           = 0xC0U,\r
+    PIN_WKUP_GPIO0_5           = 0xC4U,\r
+    PIN_WKUP_GPIO0_6           = 0xC8U,\r
+    PIN_WKUP_GPIO0_7           = 0xCCU,\r
+    PIN_WKUP_GPIO0_8           = 0xD0U,\r
+    PIN_WKUP_GPIO0_9           = 0xD4U,\r
+    PIN_WKUP_GPIO0_10          = 0xD8U,\r
+    PIN_WKUP_GPIO0_11          = 0xDCU,\r
+    PIN_WKUP_GPIO0_12          = 0xE0U,\r
+    PIN_WKUP_GPIO0_13          = 0xE4U,\r
+    PIN_WKUP_GPIO0_14          = 0xE8U,\r
+    PIN_WKUP_GPIO0_15          = 0xECU,\r
+    PIN_MCU_I3C0_SCL           = 0xF0U,\r
+    PIN_MCU_I3C0_SDA           = 0xF4U,\r
+    PIN_WKUP_I2C0_SCL          = 0xF8U,\r
+    PIN_WKUP_I2C0_SDA          = 0xFCU,\r
+    PIN_MCU_I2C0_SCL           = 0x100U,\r
+    PIN_MCU_I2C0_SDA           = 0x104U,\r
+    PIN_PMIC_POWER_EN0         = 0x108U,\r
+    PIN_PMIC_POWER_EN1         = 0x10CU,\r
+    PIN_MCU_SAFETY_ERRORN      = 0x110U,\r
+    PIN_MCU_RESETZ             = 0x114U,\r
+    PIN_MCU_RESETSTATZ         = 0x118U,\r
+    PIN_MCU_PORZ_OUT           = 0x11CU,\r
+    PIN_TCK                    = 0x120U,\r
+    PIN_TRSTN                  = 0x124U,\r
+    PIN_EMU0                   = 0x128U,\r
+    PIN_EMU1                   = 0x12CU,\r
+    PIN_MCU_ADC0_AIN0          = 0x130U,\r
+    PIN_MCU_ADC0_AIN1          = 0x134U,\r
+    PIN_MCU_ADC0_AIN2          = 0x138U,\r
+    PIN_MCU_ADC0_AIN3          = 0x13CU,\r
+    PIN_MCU_ADC0_AIN4          = 0x140U,\r
+    PIN_MCU_ADC0_AIN5          = 0x144U,\r
+    PIN_MCU_ADC0_AIN6          = 0x148U,\r
+    PIN_MCU_ADC0_AIN7          = 0x14CU,\r
+    PIN_MCU_ADC1_AIN0          = 0x150U,\r
+    PIN_MCU_ADC1_AIN1          = 0x154U,\r
+    PIN_MCU_ADC1_AIN2          = 0x158U,\r
+    PIN_MCU_ADC1_AIN3          = 0x15CU,\r
+    PIN_MCU_ADC1_AIN4          = 0x160U,\r
+    PIN_MCU_ADC1_AIN5          = 0x164U,\r
+    PIN_MCU_ADC1_AIN6          = 0x168U,\r
+    PIN_MCU_ADC1_AIN7          = 0x16CU,\r
+    PIN_RESET_REQZ             = 0x170U,\r
+    PIN_PORZ                   = 0x174U,\r
+};\r
+\r
+/* ========================================================================== */\r
+/*                            Global Variables                                */\r
+/* ========================================================================== */\r
+\r
+/** \brief Pinmux configuration data for the board. Auto-generated from \r
+           Pinmux tool. */\r
+extern pinmuxBoardCfg_t gAM7xMainPinmuxData[];\r
+extern pinmuxBoardCfg_t gAM7xWkupPinmuxData[];\r
+extern pinmuxBoardCfg_t gAM7xMainPinmuxDataGesiIcssg[];\r
+extern pinmuxBoardCfg_t gAM7xWkupPinmuxDataGesiIcssg[];\r
+extern pinmuxBoardCfg_t gAM7xMainPinmuxDataInfo[];\r
+extern pinmuxBoardCfg_t gAM7xWkupPinmuxDataInfo[];\r
+extern pinmuxBoardCfg_t gAM7xMainPinmuxDataGesiCpsw9g[];\r
+extern pinmuxBoardCfg_t gAM7xWkupPinmuxDataGesiCpsw9g[];\r
+extern pinmuxBoardCfg_t gAM7xWkupPinmuxDataHpb[];\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+#endif /* _AM7XXX_PIN_MUX_H_ */\r
diff --git a/packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data.c b/packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data.c
new file mode 100644 (file)
index 0000000..80b27f0
--- /dev/null
@@ -0,0 +1,1376 @@
+/**\r
+* Note: This file was auto-generated by TI PinMux on 5/10/2019 at 3:40:37 PM.\r
+*\r
+* \file  AM7xxx_pinmux_data.c\r
+*\r
+* \brief  This file contains the pin mux configurations for the boards.\r
+*         These are prepared based on how the peripherals are extended on\r
+*         the boards.\r
+*\r
+* \copyright Copyright (CU) 2019 Texas Instruments Incorporated -\r
+*             http://www.ti.com/\r
+*/\r
+\r
+/* ========================================================================== */\r
+/*                             Include Files                                  */\r
+/* ========================================================================== */\r
+\r
+#include "AM7xxx_pinmux.h"\r
+\r
+/** Peripheral Pin Configurations */\r
+\r
+\r
+static pinmuxPerCfg_t gDebugss0PinCfg[] =\r
+{\r
+    /* MyDEBUG1 -> TDI -> V1 */\r
+    {\r
+        PIN_TDI, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyDEBUG1 -> TDO -> V3 */\r
+    {\r
+        PIN_TDO, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyDEBUG1 -> TMS -> V2 */\r
+    {\r
+        PIN_TMS, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gDebugssPinCfg[] =\r
+{\r
+    {0, TRUE, gDebugss0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gDp0PinCfg[] =\r
+{\r
+    /* MyDP0 -> DP0_HPD -> Y4 */\r
+    {\r
+        PIN_SPI0_CS1, PIN_MODE(5) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gDpPinCfg[] =\r
+{\r
+    {0, TRUE, gDp0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gGpio0PinCfg[] =\r
+{\r
+    /* MySYSTEM1 -> GPIO0_0 -> AC18 */\r
+    {\r
+        PIN_EXTINTN, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_97 -> Y28 */\r
+    {\r
+        PIN_RGMII6_TX_CTL, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_98 -> V23 */\r
+    {\r
+        PIN_RGMII6_RX_CTL, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_117 -> W4 */\r
+    {\r
+        PIN_SPI1_CS1, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_127 -> AC4 */\r
+    {\r
+        PIN_UART1_CTSN, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gGpio1PinCfg[] =\r
+{\r
+    /* MyGPIO1 -> GPIO1_0 -> AD5 */\r
+    {\r
+        PIN_UART1_RTSN, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_3 -> W3 */\r
+    {\r
+        PIN_MCAN1_RX, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_5 -> W2 */\r
+    {\r
+        PIN_I3C0_SCL, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_6 -> W1 */\r
+    {\r
+        PIN_I3C0_SDA, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_11 -> U2 */\r
+    {\r
+        PIN_ECAP0_IN_APWM_OUT, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_12 -> U3 */\r
+    {\r
+        PIN_EXT_REFCLK1, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_22 -> R28 */\r
+    {\r
+        PIN_MMC1_SDWP, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_23 -> T28 */\r
+    {\r
+        PIN_MMC2_DAT3, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_24 -> T29 */\r
+    {\r
+        PIN_MMC2_DAT2, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_25 -> T27 */\r
+    {\r
+        PIN_MMC2_DAT1, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_26 -> T24 */\r
+    {\r
+        PIN_MMC2_DAT0, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gGpioPinCfg[] =\r
+{\r
+    {0, TRUE, gGpio0PinCfg},\r
+    {1, TRUE, gGpio1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gI2c2PinCfg[] =\r
+{\r
+    /* MyI2C2 -> I2C2_SCL -> AA1 */\r
+    {\r
+        PIN_SPI0_CLK, PIN_MODE(2) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyI2C2 -> I2C2_SDA -> AB5 */\r
+    {\r
+        PIN_SPI0_D0, PIN_MODE(2) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gI2c6PinCfg[] =\r
+{\r
+    /* MyI2C6 -> I2C6_SCL -> AA3 */\r
+    {\r
+        PIN_SPI0_D1, PIN_MODE(2) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyI2C6 -> I2C6_SDA -> Y2 */\r
+    {\r
+        PIN_SPI1_D1, PIN_MODE(2) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gI2c0PinCfg[] =\r
+{\r
+    /* MyI2C0 -> I2C0_SCL -> AC5 */\r
+    {\r
+        PIN_I2C0_SCL, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyI2C0 -> I2C0_SDA -> AA5 */\r
+    {\r
+        PIN_I2C0_SDA, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gI2c1PinCfg[] =\r
+{\r
+    /* MyI2C1 -> I2C1_SCL -> Y6 */\r
+    {\r
+        PIN_I2C1_SCL, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyI2C1 -> I2C1_SDA -> AA6 */\r
+    {\r
+        PIN_I2C1_SDA, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gI2c3PinCfg[] =\r
+{\r
+    /* MyI2C3 -> I2C3_SCL -> T26 */\r
+    {\r
+        PIN_MMC2_CLK, PIN_MODE(4) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyI2C3 -> I2C3_SDA -> T25 */\r
+    {\r
+        PIN_MMC2_CMD, PIN_MODE(4) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gI2cPinCfg[] =\r
+{\r
+    {2, TRUE, gI2c2PinCfg},\r
+    {6, TRUE, gI2c6PinCfg},\r
+    {0, TRUE, gI2c0PinCfg},\r
+    {1, TRUE, gI2c1PinCfg},\r
+    {3, TRUE, gI2c3PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcan2PinCfg[] =\r
+{\r
+    /* MyMCAN2 -> MCAN2_RX -> AC2 */\r
+    {\r
+        PIN_UART0_CTSN, PIN_MODE(3) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCAN2 -> MCAN2_TX -> AB1 */\r
+    {\r
+        PIN_UART0_RTSN, PIN_MODE(3) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcan0PinCfg[] =\r
+{\r
+    /* MyMCAN0 -> MCAN0_RX -> W5 */\r
+    {\r
+        PIN_MCAN0_RX, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCAN0 -> MCAN0_TX -> W6 */\r
+    {\r
+        PIN_MCAN0_TX, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcanPinCfg[] =\r
+{\r
+    {2, TRUE, gMcan2PinCfg},\r
+    {0, TRUE, gMcan0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcu_i2c0PinCfg[] =\r
+{\r
+    /* MyMCU_I2C0 -> MCU_I2C0_SCL -> J26 */\r
+    {\r
+        PIN_MCU_I2C0_SCL, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_I2C0 -> MCU_I2C0_SDA -> H25 */\r
+    {\r
+        PIN_MCU_I2C0_SDA, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_i2cPinCfg[] =\r
+{\r
+    {0, TRUE, gMcu_i2c0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcu_i3c0PinCfg[] =\r
+{\r
+    /* MyMCU_I3C0 -> MCU_I3C0_SCL -> D26 */\r
+    {\r
+        PIN_MCU_I3C0_SCL, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_I3C0 -> MCU_I3C0_SDA -> D25 */\r
+    {\r
+        PIN_MCU_I3C0_SDA, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_I3C0 -> MCU_I3C0_SDAPULLEN -> E26 */\r
+    {\r
+        PIN_PMIC_POWER_EN0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_i3cPinCfg[] =\r
+{\r
+    {0, TRUE, gMcu_i3c0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcu_mcan0PinCfg[] =\r
+{\r
+    /* MyMCU_MCAN0 -> MCU_MCAN0_RX -> C29 */\r
+    {\r
+        PIN_MCU_MCAN0_RX, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_MCAN0 -> MCU_MCAN0_TX -> D29 */\r
+    {\r
+        PIN_MCU_MCAN0_TX, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcu_mcan1PinCfg[] =\r
+{\r
+    /* MyMCU_MCAN1 -> MCU_MCAN1_RX -> G24 */\r
+    {\r
+        PIN_WKUP_GPIO0_5, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_MCAN1 -> MCU_MCAN1_TX -> G25 */\r
+    {\r
+        PIN_WKUP_GPIO0_4, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_mcanPinCfg[] =\r
+{\r
+    {0, TRUE, gMcu_mcan0PinCfg},\r
+    {1, TRUE, gMcu_mcan1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcu_mdio0PinCfg[] =\r
+{\r
+    /* MyMCU_MDIO1 -> MCU_MDIO0_MDC -> F23 */\r
+    {\r
+        PIN_MCU_MDIO0_MDC, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_MDIO1 -> MCU_MDIO0_MDIO -> E23 */\r
+    {\r
+        PIN_MCU_MDIO0_MDIO, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_mdioPinCfg[] =\r
+{\r
+    {0, TRUE, gMcu_mdio0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcu_fss0_ospi0PinCfg[] =\r
+{\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_CLK -> E20 */\r
+    {\r
+        PIN_MCU_OSPI0_CLK, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_CSn0 -> F19 */\r
+    {\r
+        PIN_MCU_OSPI0_CSN0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_D0 -> D20 */\r
+    {\r
+        PIN_MCU_OSPI0_D0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_D1 -> G19 */\r
+    {\r
+        PIN_MCU_OSPI0_D1, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_D2 -> G20 */\r
+    {\r
+        PIN_MCU_OSPI0_D2, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_D3 -> F20 */\r
+    {\r
+        PIN_MCU_OSPI0_D3, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_D4 -> F21 */\r
+    {\r
+        PIN_MCU_OSPI0_D4, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_D5 -> E21 */\r
+    {\r
+        PIN_MCU_OSPI0_D5, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_D6 -> B22 */\r
+    {\r
+        PIN_MCU_OSPI0_D6, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_D7 -> G21 */\r
+    {\r
+        PIN_MCU_OSPI0_D7, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI0 -> MCU_OSPI0_DQS -> D21 */\r
+    {\r
+        PIN_MCU_OSPI0_DQS, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcu_fss0_ospi1PinCfg[] =\r
+{\r
+    /* MyMCU_OSPI1 -> MCU_OSPI1_CLK -> F22 */\r
+    {\r
+        PIN_MCU_OSPI1_CLK, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_OSPI1 -> MCU_OSPI1_CSn0 -> C22 */\r
+    {\r
+        PIN_MCU_OSPI1_CSN0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_OSPI1 -> MCU_OSPI1_D0 -> D22 */\r
+    {\r
+        PIN_MCU_OSPI1_D0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI1 -> MCU_OSPI1_D1 -> G22 */\r
+    {\r
+        PIN_MCU_OSPI1_D1, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI1 -> MCU_OSPI1_D2 -> D23 */\r
+    {\r
+        PIN_MCU_OSPI1_D2, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI1 -> MCU_OSPI1_D3 -> C23 */\r
+    {\r
+        PIN_MCU_OSPI1_D3, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI1 -> MCU_OSPI1_DQS -> B23 */\r
+    {\r
+        PIN_MCU_OSPI1_DQS, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_OSPI1 -> MCU_OSPI1_LBCLKO -> A23 */\r
+    {\r
+        PIN_MCU_OSPI1_LBCLKO, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_fss0_ospiPinCfg[] =\r
+{\r
+    {0, TRUE, gMcu_fss0_ospi0PinCfg},\r
+    {1, TRUE, gMcu_fss0_ospi1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcu_fss0_hpb0PinCfg[] =\r
+{\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_CK -> E20 */\r
+    {\r
+        PIN_MCU_OSPI0_CLK, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_CSn0 -> F19 */\r
+    {\r
+        PIN_MCU_OSPI0_CSN0, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ0 -> D20 */\r
+    {\r
+        PIN_MCU_OSPI0_D0, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ1 -> G19 */\r
+    {\r
+        PIN_MCU_OSPI0_D1, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ2 -> G20 */\r
+    {\r
+        PIN_MCU_OSPI0_D2, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ3 -> F20 */\r
+    {\r
+        PIN_MCU_OSPI0_D3, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ4 -> F21 */\r
+    {\r
+        PIN_MCU_OSPI0_D4, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ5 -> E21 */\r
+    {\r
+        PIN_MCU_OSPI0_D5, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ6 -> B22 */\r
+    {\r
+        PIN_MCU_OSPI0_D6, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_HYPERBUS0_DQ7 -> G21 */\r
+    {\r
+        PIN_MCU_OSPI0_D7, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_OSPI0_DQS -> D21 */\r
+    {\r
+        PIN_MCU_OSPI0_DQS, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_FSS0_HPB1 -> MCU_OSPI0_LBCLKO -> C21 */\r
+    {\r
+        PIN_MCU_OSPI0_LBCLKO, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_fss0_hpbPinCfg[] =\r
+{\r
+    {0, TRUE, gMcu_fss0_hpb0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcu_rgmii1PinCfg[] =\r
+{\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_RD0 -> B24 */\r
+    {\r
+        PIN_MCU_RGMII1_RD0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_RD1 -> A24 */\r
+    {\r
+        PIN_MCU_RGMII1_RD1, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_RD2 -> D24 */\r
+    {\r
+        PIN_MCU_RGMII1_RD2, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_RD3 -> A25 */\r
+    {\r
+        PIN_MCU_RGMII1_RD3, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_RXC -> C24 */\r
+    {\r
+        PIN_MCU_RGMII1_RXC, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_RX_CTL -> C25 */\r
+    {\r
+        PIN_MCU_RGMII1_RX_CTL, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_TD0 -> B25 */\r
+    {\r
+        PIN_MCU_RGMII1_TD0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_TD1 -> A26 */\r
+    {\r
+        PIN_MCU_RGMII1_TD1, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_TD2 -> A27 */\r
+    {\r
+        PIN_MCU_RGMII1_TD2, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_TD3 -> A28 */\r
+    {\r
+        PIN_MCU_RGMII1_TD3, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_TXC -> B26 */\r
+    {\r
+        PIN_MCU_RGMII1_TXC, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_RGMII1 -> MCU_RGMII1_TX_CTL -> B27 */\r
+    {\r
+        PIN_MCU_RGMII1_TX_CTL, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_rgmiiPinCfg[] =\r
+{\r
+    {1, TRUE, gMcu_rgmii1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcu_uart0PinCfg[] =\r
+{\r
+    /* MyMCU_UART0 -> MCU_UART0_CTSn -> H29 */\r
+    {\r
+        PIN_WKUP_GPIO0_14, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_UART0 -> MCU_UART0_RTSn -> J27 */\r
+    {\r
+        PIN_WKUP_GPIO0_15, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMCU_UART0 -> MCU_UART0_RXD -> H28 */\r
+    {\r
+        PIN_WKUP_GPIO0_13, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_UART0 -> MCU_UART0_TXD -> G29 */\r
+    {\r
+        PIN_WKUP_GPIO0_12, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_uartPinCfg[] =\r
+{\r
+    {0, TRUE, gMcu_uart0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMdio0PinCfg[] =\r
+{\r
+    /* MyMDIO1 -> MDIO0_MDC -> V24 */\r
+    {\r
+        PIN_MDIO0_MDC, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMDIO1 -> MDIO0_MDIO -> V26 */\r
+    {\r
+        PIN_MDIO0_MDIO, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMdioPinCfg[] =\r
+{\r
+    {0, TRUE, gMdio0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMlb0PinCfg[] =\r
+{\r
+    /* MyMLB0 -> MLB0_MLBCN -> AE2 */\r
+    {\r
+        PIN_MLB0_MLBCN, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMLB0 -> MLB0_MLBCP -> AD2 */\r
+    {\r
+        PIN_MLB0_MLBCP, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMLB0 -> MLB0_MLBDN -> AD3 */\r
+    {\r
+        PIN_MLB0_MLBDN, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMLB0 -> MLB0_MLBDP -> AC3 */\r
+    {\r
+        PIN_MLB0_MLBDP, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMLB0 -> MLB0_MLBSN -> AC1 */\r
+    {\r
+        PIN_MLB0_MLBSN, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMLB0 -> MLB0_MLBSP -> AD1 */\r
+    {\r
+        PIN_MLB0_MLBSP, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMlbPinCfg[] =\r
+{\r
+    {0, TRUE, gMlb0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMmcsd1PinCfg[] =\r
+{\r
+    /* MyMMC1 -> MMC1_CLK -> P25 */\r
+    {\r
+        PIN_MMC1_CLK, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyMMC1 -> MMC1_CMD -> R29 */\r
+    {\r
+        PIN_MMC1_CMD, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyMMC1 -> MMC1_DAT0 -> R24 */\r
+    {\r
+        PIN_MMC1_DAT0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyMMC1 -> MMC1_DAT1 -> P24 */\r
+    {\r
+        PIN_MMC1_DAT1, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyMMC1 -> MMC1_DAT2 -> R25 */\r
+    {\r
+        PIN_MMC1_DAT2, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyMMC1 -> MMC1_DAT3 -> R26 */\r
+    {\r
+        PIN_MMC1_DAT3, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyMMC1 -> MMC1_SDCD -> P23 */\r
+    {\r
+        PIN_MMC1_SDCD, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyMMC1 -> MMC1_CLKLB */\r
+    {\r
+        PIN_MMC1_CLKLB, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMmcsdPinCfg[] =\r
+{\r
+    {1, TRUE, gMmcsd1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gSystem0PinCfg[] =\r
+{\r
+    /* MySYSTEM1 -> AUDIO_EXT_REFCLK2 -> W26 */\r
+    {\r
+        PIN_RGMII6_RXC, PIN_MODE(3) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySYSTEM1 -> OBSCLK0 -> V5 */\r
+    {\r
+        PIN_TIMER_IO1, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MySYSTEM1 -> PORz_OUT -> U1 */\r
+    {\r
+        PIN_PORZ_OUT, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MySYSTEM1 -> RESETSTATz -> T6 */\r
+    {\r
+        PIN_RESETSTATZ, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MySYSTEM1 -> SOC_SAFETY_ERRORn -> U4 */\r
+    {\r
+        PIN_SOC_SAFETY_ERRORN, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySYSTEM1 -> SYSCLKOUT0 -> V6 */\r
+    {\r
+        PIN_TIMER_IO0, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gSystemPinCfg[] =\r
+{\r
+    {0, TRUE, gSystem0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gUart4PinCfg[] =\r
+{\r
+    /* MyUART4 -> UART4_RXD -> W23 */\r
+    {\r
+        PIN_RGMII6_TD3, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyUART4 -> UART4_TXD -> W28 */\r
+    {\r
+        PIN_RGMII6_TD2, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gUart0PinCfg[] =\r
+{\r
+    /* MyUART0 -> UART0_CTSn -> Y3 */\r
+    {\r
+        PIN_SPI1_CS0, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyUART0 -> UART0_RTSn -> AA2 */\r
+    {\r
+        PIN_SPI0_CS0, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyUART0 -> UART0_RXD -> AB2 */\r
+    {\r
+        PIN_UART0_RXD, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyUART0 -> UART0_TXD -> AB3 */\r
+    {\r
+        PIN_UART0_TXD, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gUart2PinCfg[] =\r
+{\r
+    /* MyUART2 -> UART2_RXD -> Y1 */\r
+    {\r
+        PIN_SPI1_CLK, PIN_MODE(3) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyUART2 -> UART2_TXD -> Y5 */\r
+    {\r
+        PIN_SPI1_D0, PIN_MODE(3) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gUart1PinCfg[] =\r
+{\r
+    /* MyUART1 -> UART1_RXD -> AA4 */\r
+    {\r
+        PIN_UART1_RXD, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyUART1 -> UART1_TXD -> AB4 */\r
+    {\r
+        PIN_UART1_TXD, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gUartPinCfg[] =\r
+{\r
+    {4, TRUE, gUart4PinCfg},\r
+    {0, TRUE, gUart0PinCfg},\r
+    {2, TRUE, gUart2PinCfg},\r
+    {1, TRUE, gUart1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gUsb1PinCfg[] =\r
+{\r
+    /* MyUSB1 -> USB1_DRVVBUS -> V4 */\r
+    {\r
+        PIN_MCAN1_TX, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gUsb0PinCfg[] =\r
+{\r
+    /* MyUSB0 -> USB0_DRVVBUS -> U6 */\r
+    {\r
+        PIN_USB0_DRVVBUS, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gUsbPinCfg[] =\r
+{\r
+    {1, TRUE, gUsb1PinCfg},\r
+    {0, TRUE, gUsb0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gWkup_debugss0PinCfg[] =\r
+{\r
+    /* MyWKUP_DEBUG -> EMU0 -> C26 */\r
+    {\r
+        PIN_EMU0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_DEBUG -> EMU1 -> B29 */\r
+    {\r
+        PIN_EMU1, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_DEBUG -> TCK -> E29 */\r
+    {\r
+        PIN_TCK, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_DEBUG -> TRSTn -> F24 */\r
+    {\r
+        PIN_TRSTN, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gWkup_debugssPinCfg[] =\r
+{\r
+    {0, TRUE, gWkup_debugss0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gWkup_gpio0PinCfg[] =\r
+{\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_0 -> F26 */\r
+    {\r
+        PIN_WKUP_GPIO0_0, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_1 -> F25 */\r
+    {\r
+        PIN_WKUP_GPIO0_1, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_2 -> F28 */\r
+    {\r
+        PIN_WKUP_GPIO0_2, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_3 -> F27 */\r
+    {\r
+        PIN_WKUP_GPIO0_3, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_6 -> F29 */\r
+    {\r
+        PIN_WKUP_GPIO0_6, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_7 -> G28 */\r
+    {\r
+        PIN_WKUP_GPIO0_7, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_8 -> G27 */\r
+    {\r
+        PIN_WKUP_GPIO0_8, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_9 -> G26 */\r
+    {\r
+        PIN_WKUP_GPIO0_9, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_17 -> C21 */\r
+    {\r
+        PIN_MCU_OSPI0_LBCLKO, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_53 -> E24 */\r
+    {\r
+        PIN_MCU_SPI0_D0, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_54 -> E28 */\r
+    {\r
+        PIN_MCU_SPI0_D1, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_GPIO0 -> WKUP_GPIO0_55 -> E25 */\r
+    {\r
+        PIN_MCU_SPI0_CS0, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gWkup_gpioPinCfg[] =\r
+{\r
+    {0, TRUE, gWkup_gpio0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gWkup_i2c0PinCfg[] =\r
+{\r
+    /* MyWKUP_I2C0 -> WKUP_I2C0_SCL -> J25 */\r
+    {\r
+        PIN_WKUP_I2C0_SCL, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    /* MyWKUP_I2C0 -> WKUP_I2C0_SDA -> H24 */\r
+    {\r
+        PIN_WKUP_I2C0_SDA, PIN_MODE(0) | \\r
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gWkup_i2cPinCfg[] =\r
+{\r
+    {0, TRUE, gWkup_i2c0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gWkup_system0PinCfg[] =\r
+{\r
+    /* MyWKUP_SYSTEM -> MCU_PORz_OUT -> B28 */\r
+    {\r
+        PIN_MCU_PORZ_OUT, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyWKUP_SYSTEM -> MCU_RESETSTATz -> C27 */\r
+    {\r
+        PIN_MCU_RESETSTATZ, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyWKUP_SYSTEM -> MCU_RESETz -> D28 */\r
+    {\r
+        PIN_MCU_RESETZ, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_SYSTEM -> MCU_SAFETY_ERRORn -> D27 */\r
+    {\r
+        PIN_MCU_SAFETY_ERRORN, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_SYSTEM -> PMIC_POWER_EN1 -> G23 */\r
+    {\r
+        PIN_PMIC_POWER_EN1, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyWKUP_SYSTEM -> PORz -> J24 */\r
+    {\r
+        PIN_PORZ, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_SYSTEM -> RESET_REQz -> C28 */\r
+    {\r
+        PIN_RESET_REQZ, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gWkup_systemPinCfg[] =\r
+{\r
+    {0, TRUE, gWkup_system0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gWkup_uart0PinCfg[] =\r
+{\r
+    /* MyWKUP_UART0 -> WKUP_UART0_RXD -> J29 */\r
+    {\r
+        PIN_WKUP_UART0_RXD, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyWKUP_UART0 -> WKUP_UART0_TXD -> J28 */\r
+    {\r
+        PIN_WKUP_UART0_TXD, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gWkup_uartPinCfg[] =\r
+{\r
+    {0, TRUE, gWkup_uart0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcasp2PinCfg[] =\r
+{\r
+    /* MyMCASP2 -> MCASP2_ACLKX -> AA29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO19, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP2 -> MCASP2_AFSX -> AA26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO18, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP2 -> MCASP2_AXR3 -> Y25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO17, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcasp0PinCfg[] =\r
+{\r
+    /* MyMCASP10 -> MCASP10_ACLKX -> U23 */\r
+    {\r
+        PIN_RGMII5_TX_CTL, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP10 -> MCASP10_AFSX -> U26 */\r
+    {\r
+        PIN_RGMII5_RX_CTL, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP10 -> MCASP10_AXR0 -> V28 */\r
+    {\r
+        PIN_RGMII5_TD3, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP10 -> MCASP10_AXR1 -> V29 */\r
+    {\r
+        PIN_RGMII5_TD2, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP10 -> MCASP10_AXR2 -> U29 */\r
+    {\r
+        PIN_RGMII5_TXC, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP10 -> MCASP10_AXR3 -> U25 */\r
+    {\r
+        PIN_RGMII5_RXC, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP10 -> MCASP10_AXR4 -> V25 */\r
+    {\r
+        PIN_RGMII6_TD1, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP10 -> MCASP10_AXR5 -> W27 */\r
+    {\r
+        PIN_RGMII6_TD0, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP10 -> MCASP10_AXR6 -> W29 */\r
+    {\r
+        PIN_RGMII6_TXC, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* AUDIO_EXT_REFCLK2 (to PCM3168a) */\r
+    {\r
+        PIN_RGMII6_RXC, PIN_MODE(3) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcasp1PinCfg[] =\r
+{\r
+    /* MyMCASP11 -> MCASP11_ACLKX -> V27 */\r
+    {\r
+        PIN_RGMII5_TD1, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP11 -> MCASP11_AFSX -> U28 */\r
+    {\r
+        PIN_RGMII5_TD0, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP11 -> MCASP11_AXR0 -> U27 */\r
+    {\r
+        PIN_RGMII5_RD3, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP11 -> MCASP11_AXR1 -> U24 */\r
+    {\r
+        PIN_RGMII5_RD2, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP11 -> MCASP11_AXR2 -> R23 */\r
+    {\r
+        PIN_RGMII5_RD1, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP11 -> MCASP11_AXR3 -> T23 */\r
+    {\r
+        PIN_RGMII5_RD0, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP11 -> MCASP11_AXR4 -> Y29 */\r
+    {\r
+        PIN_RGMII6_RD3, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP11 -> MCASP11_AXR5 -> Y27 */\r
+    {\r
+        PIN_RGMII6_RD2, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP11 -> MCASP11_AXR6 -> W24 */\r
+    {\r
+        PIN_RGMII6_RD1, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP11 -> MCASP11_AXR7 -> W25 */\r
+    {\r
+        PIN_RGMII6_RD0, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcaspPinCfg[] =\r
+{\r
+    {2, TRUE, gMcasp2PinCfg},\r
+    {0, TRUE, gMcasp0PinCfg},\r
+    {1, TRUE, gMcasp1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcu_adc0PinCfg[] =\r
+{\r
+    /* MyMCU_ADC0 -> MCU_ADC0_AIN0 -> K25 */\r
+    {\r
+        PIN_MCU_ADC0_AIN0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC0 -> MCU_ADC0_AIN1 -> K26 */\r
+    {\r
+        PIN_MCU_ADC0_AIN1, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC0 -> MCU_ADC0_AIN2 -> K28 */\r
+    {\r
+        PIN_MCU_ADC0_AIN2, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC0 -> MCU_ADC0_AIN3 -> L28 */\r
+    {\r
+        PIN_MCU_ADC0_AIN3, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC0 -> MCU_ADC0_AIN4 -> K24 */\r
+    {\r
+        PIN_MCU_ADC0_AIN4, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC0 -> MCU_ADC0_AIN5 -> K27 */\r
+    {\r
+        PIN_MCU_ADC0_AIN5, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC0 -> MCU_ADC0_AIN6 -> K29 */\r
+    {\r
+        PIN_MCU_ADC0_AIN6, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC0 -> MCU_ADC0_AIN7 -> L29 */\r
+    {\r
+        PIN_MCU_ADC0_AIN7, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_adcPinCfg[] =\r
+{\r
+    {0, TRUE, gMcu_adc0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+pinmuxBoardCfg_t gAM7xMainPinmuxData[] =\r
+{\r
+    {0, gDebugssPinCfg},\r
+    {1, gDpPinCfg},\r
+    {2, gGpioPinCfg},\r
+    {3, gI2cPinCfg},\r
+    {4, gMcanPinCfg},\r
+    {5, gMdioPinCfg},\r
+    {6, gMlbPinCfg},\r
+    {7, gMmcsdPinCfg},\r
+    {8, gSystemPinCfg},\r
+    {9, gUartPinCfg},\r
+    {10, gUsbPinCfg},\r
+    {11, gMcaspPinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+pinmuxBoardCfg_t gAM7xWkupPinmuxData[] =\r
+{\r
+    {0, gMcu_i2cPinCfg},\r
+    {1, gMcu_i3cPinCfg},\r
+    {2, gMcu_mcanPinCfg},\r
+    {3, gMcu_mdioPinCfg},\r
+    {4, gMcu_fss0_ospiPinCfg},\r
+    {5, gMcu_rgmiiPinCfg},\r
+    {6, gMcu_uartPinCfg},\r
+    {7, gWkup_debugssPinCfg},\r
+    {8, gWkup_gpioPinCfg},\r
+    {9, gWkup_i2cPinCfg},\r
+    {10, gWkup_systemPinCfg},\r
+    {11, gWkup_uartPinCfg},\r
+    {12, gMcu_adcPinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+pinmuxBoardCfg_t gAM7xWkupPinmuxDataHpb[] =\r
+{\r
+    {0, gMcu_fss0_hpbPinCfg},\r
+    {PINMUX_END}\r
+};\r
diff --git a/packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data_gesi.c b/packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data_gesi.c
new file mode 100644 (file)
index 0000000..e878cf4
--- /dev/null
@@ -0,0 +1,872 @@
+/**\r
+* Note: This file was auto-generated by TI PinMux on 5/13/2019 at 5:17:56 PM.\r
+*\r
+* \file  AM7xxx_pinmux_data.c\r
+*\r
+* \brief  This file contains the pin mux configurations for the boards.\r
+*         These are prepared based on how the peripherals are extended on\r
+*         the boards.\r
+*\r
+* \copyright Copyright (CU) 2019 Texas Instruments Incorporated -\r
+*             http://www.ti.com/\r
+*/\r
+\r
+/* ========================================================================== */\r
+/*                             Include Files                                  */\r
+/* ========================================================================== */\r
+\r
+#include "AM7xxx_pinmux.h"\r
+\r
+/** Peripheral Pin Configurations */\r
+\r
+\r
+static pinmuxPerCfg_t gEhrpwm0PinCfg[] =\r
+{\r
+    /* MyEHRPWM0 -> EHRPWM0_A -> V29 */\r
+    {\r
+        PIN_RGMII5_TD2, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyEHRPWM0 -> EHRPWM0_B -> V27 */\r
+    {\r
+        PIN_RGMII5_TD1, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyEHRPWM0 -> EHRPWM0_SYNCI -> U23 */\r
+    {\r
+        PIN_RGMII5_TX_CTL, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyEHRPWM0 -> EHRPWM0_SYNCO -> U26 */\r
+    {\r
+        PIN_RGMII5_RX_CTL, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gEhrpwm1PinCfg[] =\r
+{\r
+    /* MyEHRPWM1 -> EHRPWM1_A -> U28 */\r
+    {\r
+        PIN_RGMII5_TD0, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyEHRPWM1 -> EHRPWM1_B -> U29 */\r
+    {\r
+        PIN_RGMII5_TXC, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gEhrpwm2PinCfg[] =\r
+{\r
+    /* MyEHRPWM2 -> EHRPWM2_A -> U27 */\r
+    {\r
+        PIN_RGMII5_RD3, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyEHRPWM2 -> EHRPWM2_B -> U24 */\r
+    {\r
+        PIN_RGMII5_RD2, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gEhrpwmPinCfg[] =\r
+{\r
+    {0, TRUE, gEhrpwm0PinCfg},\r
+    {1, TRUE, gEhrpwm1PinCfg},\r
+    {2, TRUE, gEhrpwm2PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gEqep0PinCfg[] =\r
+{\r
+    /* MyEQEP0 -> EQEP0_A -> AC2 */\r
+    {\r
+        PIN_UART0_CTSN, PIN_MODE(5) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyEQEP0 -> EQEP0_B -> AB1 */\r
+    {\r
+        PIN_UART0_RTSN, PIN_MODE(5) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyEQEP0 -> EQEP0_I -> AD5 */\r
+    {\r
+        PIN_UART1_RTSN, PIN_MODE(5) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyEQEP0 -> EQEP0_S -> AC4 */\r
+    {\r
+        PIN_UART1_CTSN, PIN_MODE(5) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gEqepPinCfg[] =\r
+{\r
+    {0, FALSE, gEqep0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gGpio0PinCfg[] =\r
+{\r
+    /* MyGPIO1 -> GPIO0_60 -> AB24 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO17, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO0_61 -> AB29 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO18, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO0_62 -> AB28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO19, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO0_68 -> AB27 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO5, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO0_96 -> T23 */\r
+    {\r
+        PIN_RGMII5_RD0, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gGpio1PinCfg[] =\r
+{\r
+    /* MyGPIO2 -> GPIO1_23 -> T28 */\r
+    {\r
+        PIN_MMC2_DAT3, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO2 -> GPIO1_24 -> T29 */\r
+    {\r
+        PIN_MMC2_DAT2, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gGpioPinCfg[] =\r
+{\r
+    {0, TRUE, gGpio0PinCfg},\r
+    {1, TRUE, gGpio1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcan6PinCfg[] =\r
+{\r
+    /* MyMCAN6 -> MCAN6_RX -> AG21 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO5, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCAN6 -> MCAN6_TX -> AH21 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO19, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcan7PinCfg[] =\r
+{\r
+    /* MyMCAN7 -> MCAN7_RX -> Y23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO8, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCAN7 -> MCAN7_TX -> AC21 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO7, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcan9PinCfg[] =\r
+{\r
+    /* MyMCAN9 -> MCAN9_RX -> AC27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO8, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCAN9 -> MCAN9_TX -> AC28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO7, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcan1PinCfg[] =\r
+{\r
+    /* MyMCAN11 -> MCAN11_RX -> AA28 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO8, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCAN11 -> MCAN11_TX -> AA24 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO7, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcan5PinCfg[] =\r
+{\r
+    /* MyMCAN5 -> MCAN5_RX -> AE21 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO18, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCAN5 -> MCAN5_TX -> AJ21 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO17, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcan4PinCfg[] =\r
+{\r
+    /* MyMCAN4 -> MCAN4_RX -> AJ20 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO8, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCAN4 -> MCAN4_TX -> AE20 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO7, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcanPinCfg[] =\r
+{\r
+    {6, TRUE, gMcan6PinCfg},\r
+    {7, TRUE, gMcan7PinCfg},\r
+    {9, TRUE, gMcan9PinCfg},\r
+    {1, TRUE, gMcan1PinCfg},\r
+    {5, TRUE, gMcan5PinCfg},\r
+    {4, TRUE, gMcan4PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcu_adc1PinCfg[] =\r
+{\r
+    /* MyMCU_ADC1 -> MCU_ADC1_AIN0 -> N23 */\r
+    {\r
+        PIN_MCU_ADC1_AIN0, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC1 -> MCU_ADC1_AIN1 -> M25 */\r
+    {\r
+        PIN_MCU_ADC1_AIN1, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC1 -> MCU_ADC1_AIN2 -> L24 */\r
+    {\r
+        PIN_MCU_ADC1_AIN2, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC1 -> MCU_ADC1_AIN3 -> L26 */\r
+    {\r
+        PIN_MCU_ADC1_AIN3, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC1 -> MCU_ADC1_AIN4 -> N24 */\r
+    {\r
+        PIN_MCU_ADC1_AIN4, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC1 -> MCU_ADC1_AIN5 -> M24 */\r
+    {\r
+        PIN_MCU_ADC1_AIN5, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC1 -> MCU_ADC1_AIN6 -> L25 */\r
+    {\r
+        PIN_MCU_ADC1_AIN6, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCU_ADC1 -> MCU_ADC1_AIN7 -> L27 */\r
+    {\r
+        PIN_MCU_ADC1_AIN7, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcu_adcPinCfg[] =\r
+{\r
+    {1, TRUE, gMcu_adc1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMdio0PinCfg[] =\r
+{\r
+    /* MyMDIO1 -> MDIO0_MDC -> V24 */\r
+    {\r
+        PIN_MDIO0_MDC, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMDIO1 -> MDIO0_MDIO -> V26 */\r
+    {\r
+        PIN_MDIO0_MDIO, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMdioPinCfg[] =\r
+{\r
+    {0, TRUE, gMdio0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gPru_icssg0_mdio0PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG0_MDIO1 -> PRG0_MDIO0_MDC -> AA27 */\r
+    {\r
+        PIN_PRG0_MDIO0_MDC, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG0_MDIO1 -> PRG0_MDIO0_MDIO -> Y26 */\r
+    {\r
+        PIN_PRG0_MDIO0_MDIO, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gPru_icssg0_mdioPinCfg[] =\r
+{\r
+    {0, TRUE, gPru_icssg0_mdio0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gPru_icssg0_rgmii1PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RD0 -> AF28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO0, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RD1 -> AE28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO1, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RD2 -> AE27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO2, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RD3 -> AD26 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO3, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RXC -> AE26 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO6, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_RX_CTL -> AD25 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO4, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TD0 -> AJ28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO11, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TD1 -> AH27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO12, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TD2 -> AH29 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO13, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TD3 -> AG28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO14, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TXC -> AH28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO16, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII1 -> PRG0_RGMII1_TX_CTL -> AG27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO15, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gPru_icssg0_rgmii2PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RD0 -> AE29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO0, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RD1 -> AD28 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO1, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RD2 -> AD27 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO2, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RD3 -> AC25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO3, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RXC -> AC26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO6, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_RX_CTL -> AD29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO4, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TD0 -> AG26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO11, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TD1 -> AF27 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO12, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TD2 -> AF26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO13, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TD3 -> AE25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO14, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TXC -> AG29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO16, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG0_RGMII2 -> PRG0_RGMII2_TX_CTL -> AF29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO15, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gPru_icssg0_rgmiiPinCfg[] =\r
+{\r
+    {1, TRUE, gPru_icssg0_rgmii1PinCfg},\r
+    {2, TRUE, gPru_icssg0_rgmii2PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gPru_icssg1_iep0PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG1_IEP1 -> PRG1_IEP0_EDIO_OUTVALID -> Y4 */\r
+    {\r
+        PIN_SPI0_CS1, PIN_MODE(6) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gPru_icssg1_iepPinCfg[] =\r
+{\r
+    {0, TRUE, gPru_icssg1_iep0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gPru_icssg1_mdio0PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG1_MDIO1 -> PRG1_MDIO0_MDC -> AD18 */\r
+    {\r
+        PIN_PRG1_MDIO0_MDC, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_MDIO1 -> PRG1_MDIO0_MDIO -> AD19 */\r
+    {\r
+        PIN_PRG1_MDIO0_MDIO, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gPru_icssg1_mdioPinCfg[] =\r
+{\r
+    {0, TRUE, gPru_icssg1_mdio0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gPru_icssg1_pru1PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG1_PRU1 -> PRG1_PRU1_GPO10 -> AB23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO10, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_PRU1 -> PRG1_PRU1_GPO9 -> AF21 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO9, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gPru_icssg1_pru0PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG1_PRU2 -> PRG1_PRU0_GPO10 -> AD21 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO10, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gPru_icssg1_pruPinCfg[] =\r
+{\r
+    {1, TRUE, gPru_icssg1_pru1PinCfg},\r
+    {0, TRUE, gPru_icssg1_pru0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gPru_icssg1_pwm3PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG1_PWM3 -> PRG1_PWM3_B2 -> AD20 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO5, PIN_MODE(3) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gPru_icssg1_pwmPinCfg[] =\r
+{\r
+    {3, TRUE, gPru_icssg1_pwm3PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gPru_icssg1_rgmii1PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD0 -> AC23 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO0, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD1 -> AG22 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO1, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD2 -> AF22 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO2, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD3 -> AJ23 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO3, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RXC -> AD22 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO6, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RX_CTL -> AH23 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO4, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD0 -> AF24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO11, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD1 -> AJ24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO12, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD2 -> AG24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO13, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD3 -> AD24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO14, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TXC -> AE24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO16, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TX_CTL -> AC24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO15, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gPru_icssg1_rgmii2PinCfg[] =\r
+{\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD0 -> AE22 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO0, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD1 -> AG23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO1, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD2 -> AF23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO2, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD3 -> AD23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO3, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RXC -> AE23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO6, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RX_CTL -> AH24 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO4, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD0 -> AJ25 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO11, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD1 -> AH25 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO12, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD2 -> AG25 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO13, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD3 -> AH26 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO14, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TXC -> AJ26 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO16, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TX_CTL -> AJ27 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO15, PIN_MODE(2) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gPru_icssg1_rgmiiPinCfg[] =\r
+{\r
+    {1, TRUE, gPru_icssg1_rgmii1PinCfg},\r
+    {2, TRUE, gPru_icssg1_rgmii2PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gSpi3PinCfg[] =\r
+{\r
+    /* MySPI3 -> SPI3_CLK -> Y25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO17, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySPI3 -> SPI3_CS1 -> AB26 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO9, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySPI3 -> SPI3_CS2 -> AB25 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO10, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySPI3 -> SPI3_D0 -> AA26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO18, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySPI3 -> SPI3_D1 -> AA29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO19, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gSpi6PinCfg[] =\r
+{\r
+    /* MySPI6 -> SPI6_CLK -> AC22 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO17, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySPI6 -> SPI6_D0 -> AJ22 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO18, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySPI6 -> SPI6_D1 -> AH22 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO19, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gSpiPinCfg[] =\r
+{\r
+    {3, TRUE, gSpi3PinCfg},\r
+    {6, TRUE, gSpi6PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gUart8PinCfg[] =\r
+{\r
+    /* MyUART1 -> UART8_RXD -> Y24 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO9, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyUART1 -> UART8_TXD -> AA25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO10, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gUart4PinCfg[] =\r
+{\r
+    /* MyUART4 -> UART4_RXD -> W23 */\r
+    {\r
+        PIN_RGMII6_TD3, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyUART4 -> UART4_TXD -> W28 */\r
+    {\r
+        PIN_RGMII6_TD2, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gUartPinCfg[] =\r
+{\r
+    {8, TRUE, gUart8PinCfg},\r
+    {4, TRUE, gUart4PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gWkup_gpio0PinCfg[] =\r
+{\r
+    /* MyWKUP_GPIO1 -> WKUP_GPIO0_11 -> H27 */\r
+    {\r
+        PIN_WKUP_GPIO0_11, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gWkup_gpioPinCfg[] =\r
+{\r
+    {0, TRUE, gWkup_gpio0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+pinmuxBoardCfg_t gAM7xMainPinmuxDataGesiIcssg[] =\r
+{\r
+    {0, gEhrpwmPinCfg},\r
+    {1, gEqepPinCfg},\r
+    {2, gGpioPinCfg},\r
+    {3, gMcanPinCfg},\r
+    {4, gMdioPinCfg},\r
+    {5, gPru_icssg0_mdioPinCfg},\r
+    {6, gPru_icssg0_rgmiiPinCfg},\r
+    {7, gPru_icssg1_iepPinCfg},\r
+    {8, gPru_icssg1_mdioPinCfg},\r
+    {9, gPru_icssg1_pruPinCfg},\r
+    {10, gPru_icssg1_pwmPinCfg},\r
+    {11, gPru_icssg1_rgmiiPinCfg},\r
+    {12, gSpiPinCfg},\r
+    {13, gUartPinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+pinmuxBoardCfg_t gAM7xWkupPinmuxDataGesiIcssg[] =\r
+{\r
+    {0, gMcu_adcPinCfg},\r
+    {1, gWkup_gpioPinCfg},\r
+    {PINMUX_END}\r
+};\r
diff --git a/packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data_gesi_cpsw9g.c b/packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data_gesi_cpsw9g.c
new file mode 100644 (file)
index 0000000..a2c7ca9
--- /dev/null
@@ -0,0 +1,425 @@
+/**\r
+* Note: This file was auto-generated by TI PinMux on 5/15/2019 at 8:07:17 AM.\r
+*\r
+* \file  AM7xxx_pinmux_data.c\r
+*\r
+* \brief  This file contains the pin mux configurations for the boards.\r
+*         These are prepared based on how the peripherals are extended on\r
+*         the boards.\r
+*\r
+* \copyright Copyright (CU) 2019 Texas Instruments Incorporated -\r
+*             http://www.ti.com/\r
+*/\r
+\r
+/* ========================================================================== */\r
+/*                             Include Files                                  */\r
+/* ========================================================================== */\r
+\r
+#include "AM7xxx_pinmux.h"\r
+\r
+/** Peripheral Pin Configurations */\r
+\r
+\r
+static pinmuxPerCfg_t gCpsw9g0PinCfg[] =\r
+{\r
+    /* MyCPSW9G3 -> CLKOUT -> AA25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO10, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gCpsw9gPinCfg[] =\r
+{\r
+    {0, TRUE, gCpsw9g0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gGpio0PinCfg[] =\r
+{\r
+    /* MyGPIO0 -> GPIO0_96 -> T23 */\r
+    {\r
+        PIN_RGMII5_RD0, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_104 -> W26 */\r
+    {\r
+        PIN_RGMII6_RXC, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gGpioPinCfg[] =\r
+{\r
+    {0, TRUE, gGpio0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMdio0PinCfg[] =\r
+{\r
+    /* MyMDIO1 -> MDIO0_MDC -> V24 */\r
+    {\r
+        PIN_MDIO0_MDC, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyMDIO1 -> MDIO0_MDIO -> V26 */\r
+    {\r
+        PIN_MDIO0_MDIO, PIN_MODE(0) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMdioPinCfg[] =\r
+{\r
+    {0, TRUE, gMdio0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gRgmii3PinCfg[] =\r
+{\r
+    /* MyRGMII3 -> RGMII3_RD0 -> AF28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO0, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_RD1 -> AE28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO1, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_RD2 -> AE27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO2, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_RD3 -> AD26 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO3, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_RXC -> AE26 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO6, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_RX_CTL -> AD25 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO4, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_TD0 -> AJ28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO11, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_TD1 -> AH27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO12, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_TD2 -> AH29 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO13, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_TD3 -> AG28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO14, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_TXC -> AH28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO16, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII3 -> RGMII3_TX_CTL -> AG27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO15, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gRgmii4PinCfg[] =\r
+{\r
+    /* MyRGMII4 -> RGMII4_RD0 -> AE29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO0, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_RD1 -> AD28 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO1, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_RD2 -> AD27 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO2, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_RD3 -> AC25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO3, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_RXC -> AC26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO6, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_RX_CTL -> AD29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO4, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_TD0 -> AG26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO11, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_TD1 -> AF27 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO12, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_TD2 -> AF26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO13, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_TD3 -> AE25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO14, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_TXC -> AG29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO16, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII4 -> RGMII4_TX_CTL -> AF29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO15, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gRgmii1PinCfg[] =\r
+{\r
+    /* MyRGMII1 -> RGMII1_RD0 -> AC23 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO0, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_RD1 -> AG22 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO1, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_RD2 -> AF22 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO2, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_RD3 -> AJ23 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO3, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_RXC -> AD22 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO6, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_RX_CTL -> AH23 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO4, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_TD0 -> AF24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO11, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_TD1 -> AJ24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO12, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_TD2 -> AG24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO13, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_TD3 -> AD24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO14, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_TXC -> AE24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO16, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII1 -> RGMII1_TX_CTL -> AC24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO15, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gRgmii2PinCfg[] =\r
+{\r
+    /* MyRGMII2 -> RGMII2_RD0 -> AE22 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO0, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_RD1 -> AG23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO1, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_RD2 -> AF23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO2, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_RD3 -> AD23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO3, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_RXC -> AE23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO6, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_RX_CTL -> AH24 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO4, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_TD0 -> AJ25 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO11, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_TD1 -> AH25 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO12, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_TD2 -> AG25 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO13, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_TD3 -> AH26 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO14, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_TXC -> AJ26 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO16, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRGMII2 -> RGMII2_TX_CTL -> AJ27 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO15, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gRgmiiPinCfg[] =\r
+{\r
+    {3, TRUE, gRgmii3PinCfg},\r
+    {4, TRUE, gRgmii4PinCfg},\r
+    {1, TRUE, gRgmii1PinCfg},\r
+    {2, TRUE, gRgmii2PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gRmii8PinCfg[] =\r
+{\r
+    /* MyRMII8 -> RMII8_CRS_DV -> Y28 */\r
+    {\r
+        PIN_RGMII6_TX_CTL, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRMII8 -> RMII8_RXD0 -> W25 */\r
+    {\r
+        PIN_RGMII6_RD0, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRMII8 -> RMII8_RXD1 -> W24 */\r
+    {\r
+        PIN_RGMII6_RD1, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRMII8 -> RMII8_RX_ER -> V23 */\r
+    {\r
+        PIN_RGMII6_RX_CTL, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyRMII8 -> RMII8_TXD0 -> W27 */\r
+    {\r
+        PIN_RGMII6_TD0, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRMII8 -> RMII8_TXD1 -> V25 */\r
+    {\r
+        PIN_RGMII6_TD1, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyRMII8 -> RMII8_TX_EN -> W29 */\r
+    {\r
+        PIN_RGMII6_TXC, PIN_MODE(1) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gRmii0PinCfg[] =\r
+{\r
+    /* MyRMII0 -> RMII_REF_CLK -> AD18 */\r
+    {\r
+        PIN_PRG1_MDIO0_MDC, PIN_MODE(5) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gRmiiPinCfg[] =\r
+{\r
+    {8, TRUE, gRmii8PinCfg},\r
+    {0, TRUE, gRmii0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+pinmuxBoardCfg_t gAM7xMainPinmuxDataGesiCpsw9g[] =\r
+{\r
+    {0, gCpsw9gPinCfg},\r
+    {1, gGpioPinCfg},\r
+    {2, gMdioPinCfg},\r
+    {3, gRgmiiPinCfg},\r
+    {4, gRmiiPinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+pinmuxBoardCfg_t gAM7xWkupPinmuxDataGesiCpsw9g[] =\r
+{\r
+    {PINMUX_END}\r
+};\r
diff --git a/packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data_info.c b/packages/ti/board/src/j7200_evm/AM7xxx_pinmux_data_info.c
new file mode 100644 (file)
index 0000000..3d977fa
--- /dev/null
@@ -0,0 +1,525 @@
+/**\r
+* Note: This file was auto-generated by TI PinMux on 5/26/2019 at 3:24:31 PM.\r
+*\r
+* \file  AM7xxx_pinmux_data.c\r
+*\r
+* \brief  This file contains the pin mux configurations for the boards.\r
+*         These are prepared based on how the peripherals are extended on\r
+*         the boards.\r
+*\r
+* \copyright Copyright (CU) 2019 Texas Instruments Incorporated -\r
+*             http://www.ti.com/\r
+*/\r
+\r
+/* ========================================================================== */\r
+/*                             Include Files                                  */\r
+/* ========================================================================== */\r
+\r
+#include "AM7xxx_pinmux.h"\r
+\r
+/** Peripheral Pin Configurations */\r
+\r
+\r
+static pinmuxPerCfg_t gGpio0PinCfg[] =\r
+{\r
+    /* MyGPIO0 -> GPIO0_11 -> AD21 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO10, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_45 -> AE27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO2, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_46 -> AD26 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO3, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_65 -> AD27 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO2, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_66 -> AC25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO3, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_76 -> AF26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO13, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_78 -> AF29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO15, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO0 -> GPIO0_79 -> AG29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO16, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gGpio1PinCfg[] =\r
+{\r
+    /* MyGPIO1 -> GPIO1_23 -> T28 */\r
+    {\r
+        PIN_MMC2_DAT3, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyGPIO1 -> GPIO1_24 -> T29 */\r
+    {\r
+        PIN_MMC2_DAT2, PIN_MODE(7) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gGpioPinCfg[] =\r
+{\r
+    {0, TRUE, gGpio0PinCfg},\r
+    {1, TRUE, gGpio1PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gMcasp1PinCfg[] =\r
+{\r
+    /* MyMCASP1 -> MCASP1_ACLKX -> AB27 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO5, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP1 -> MCASP1_AFSX -> AA28 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO8, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP1 -> MCASP1_AXR0 -> AE29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO0, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP1 -> MCASP1_AXR1 -> AD28 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO1, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP1 -> MCASP1_AXR2 -> AD29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO4, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP1 -> MCASP1_AXR3 -> AC26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO6, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP1 -> MCASP1_AXR5 -> Y24 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO9, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP1 -> MCASP1_AXR6 -> AA25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO10, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP1 -> MCASP1_AXR7 -> AG26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO11, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP1 -> MCASP1_AXR8 -> AF27 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO12, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcasp0PinCfg[] =\r
+{\r
+    /* MyMCASP0 -> MCASP0_ACLKX -> AB26 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO9, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AFSX -> AB25 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO10, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR0 -> AF28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO0, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR1 -> AE28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO1, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR10 -> AG28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO14, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR11 -> AG27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO15, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR12 -> AH28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO16, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR13 -> AB24 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO17, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR2 -> AD25 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO4, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR3 -> AC29 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO5, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR4 -> AE26 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO6, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR5 -> AC28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO7, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR6 -> AC27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO8, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR7 -> AJ28 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO11, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR8 -> AH27 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO12, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP0 -> MCASP0_AXR9 -> AH29 */\r
+    {\r
+        PIN_PRG0_PRU0_GPO13, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcasp2PinCfg[] =\r
+{\r
+    /* MyMCASP2 -> MCASP2_AXR0 -> AE25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO14, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxPerCfg_t gMcasp6PinCfg[] =\r
+{\r
+    /* MyMCASP6 -> MCASP6_ACLKR -> AH23 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO4, PIN_MODE(13) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP6 -> MCASP6_ACLKX -> AC23 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO0, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP6 -> MCASP6_AFSR -> AD22 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO6, PIN_MODE(13) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP6 -> MCASP6_AFSX -> AG22 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO1, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP6 -> MCASP6_AXR0 -> AF22 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO2, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP6 -> MCASP6_AXR1 -> AJ23 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO3, PIN_MODE(12) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyMCASP6 -> AUDIO_EXT_REFCLK1 -> AE20 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO7, PIN_MODE(5) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gMcaspPinCfg[] =\r
+{\r
+    {1, TRUE, gMcasp1PinCfg},\r
+    {0, TRUE, gMcasp0PinCfg},\r
+    {2, TRUE, gMcasp2PinCfg},\r
+    {6, TRUE, gMcasp6PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gSpi3PinCfg[] =\r
+{\r
+    /* MySPI3 -> SPI3_CLK -> Y25 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO17, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySPI3 -> SPI3_CS0 -> AA24 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO7, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySPI3 -> SPI3_D0 -> AA26 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO18, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MySPI3 -> SPI3_D1 -> AA29 */\r
+    {\r
+        PIN_PRG0_PRU1_GPO19, PIN_MODE(4) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gSpiPinCfg[] =\r
+{\r
+    {3, TRUE, gSpi3PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gVout0PinCfg[] =\r
+{\r
+    /* MyVOUT1 -> VOUT0_DATA0 -> AE22 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO0, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA1 -> AG23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO1, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA2 -> AF23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO2, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA3 -> AD23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO3, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA4 -> AH24 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO4, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA5 -> AG21 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO5, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA6 -> AE23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO6, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA7 -> AC21 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO7, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA8 -> Y23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO8, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA9 -> AF21 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO9, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA10 -> AB23 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO10, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA11 -> AJ25 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO11, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA12 -> AH25 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO12, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA13 -> AG25 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO13, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA14 -> AH26 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO14, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA15 -> AJ27 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO15, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA16 -> AF24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO11, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA17 -> AJ24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO12, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA18 -> AG24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO13, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA19 -> AD24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO14, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA20 -> AC24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO15, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA21 -> AE24 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO16, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA22 -> AJ20 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO8, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DATA23 -> AG20 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO9, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_DE -> AC22 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO17, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_EXTPCLKIN -> AH21 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO19, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_HSYNC -> AJ26 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO16, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_PCLK -> AH22 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO19, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    /* MyVOUT1 -> VOUT0_VSYNC -> AJ22 */\r
+    {\r
+        PIN_PRG1_PRU1_GPO18, PIN_MODE(10) | \\r
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gVoutPinCfg[] =\r
+{\r
+    {0, TRUE, gVout0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+static pinmuxPerCfg_t gVpfe0PinCfg[] =\r
+{\r
+    /* MyVPFE1 -> VPFE0_DATA6 -> AJ21 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO17, PIN_MODE(11) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyVPFE1 -> VPFE0_DATA7 -> AE21 */\r
+    {\r
+        PIN_PRG1_PRU0_GPO18, PIN_MODE(11) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyVPFE1 -> VPFE0_DATA11 -> AD19 */\r
+    {\r
+        PIN_PRG1_MDIO0_MDIO, PIN_MODE(11) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    /* MyVPFE1 -> VPFE0_DATA12 -> AD18 */\r
+    {\r
+        PIN_PRG1_MDIO0_MDC, PIN_MODE(11) | \\r
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
+    },\r
+    {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gVpfePinCfg[] =\r
+{\r
+    {0, TRUE, gVpfe0PinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+\r
+pinmuxBoardCfg_t gAM7xMainPinmuxDataInfo[] =\r
+{\r
+    {0, gGpioPinCfg},\r
+    {1, gMcaspPinCfg},\r
+    {2, gSpiPinCfg},\r
+    {3, gVoutPinCfg},\r
+    {4, gVpfePinCfg},\r
+    {PINMUX_END}\r
+};\r
+\r
+pinmuxBoardCfg_t gAM7xWkupPinmuxDataInfo[] =\r
+{\r
+    {PINMUX_END}\r
+};\r
diff --git a/packages/ti/board/src/j7200_evm/board_clock.c b/packages/ti/board/src/j7200_evm/board_clock.c
new file mode 100644 (file)
index 0000000..0f73964
--- /dev/null
@@ -0,0 +1,414 @@
+/******************************************************************************
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+ /** \file board_clock.c
+  *
+  *  \brief This file contains initialization of wakeup and main PSC
+  *  configuration structures and function definitions to get the number
+  *  of wakeup and main PSC config exists.
+  */
+
+#include "board_clock.h"
+#include "board_utils.h"
+#include <ti/drv/sciclient/sciclient.h>
+
+extern Board_initParams_t gBoardInitParams;
+
+uint32_t gBoardClkModuleMcuID[] = {
+    TISCI_DEV_MCU_ADC0,
+    TISCI_DEV_MCU_ADC1,
+    TISCI_DEV_MCU_CPSW0,
+    TISCI_DEV_MCU_TIMER0,
+    TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0,
+    TISCI_DEV_MCU_FSS0_OSPI_0,
+    TISCI_DEV_MCU_FSS0_OSPI_1,
+    TISCI_DEV_WKUP_GPIO0,
+    TISCI_DEV_WKUP_GPIO1,
+    TISCI_DEV_WKUP_GPIOMUX_INTRTR0,
+    TISCI_DEV_MCU_UART0,
+    TISCI_DEV_MCU_MCAN0,
+    TISCI_DEV_MCU_MCAN1,
+    TISCI_DEV_MCU_I2C0,
+    TISCI_DEV_MCU_I2C1,
+    TISCI_DEV_WKUP_I2C0,
+    TISCI_DEV_WKUP_UART0,
+    TISCI_DEV_SA2_UL0,
+};
+
+uint32_t gBoardClkModuleMainID[] = {
+    TISCI_DEV_DDR0,
+    TISCI_DEV_TIMER0,
+    TISCI_DEV_TIMER1,
+    TISCI_DEV_TIMER2,
+    TISCI_DEV_TIMER3,
+    TISCI_DEV_EMIF_DATA_0_VD,
+    TISCI_DEV_MMCSD0,
+    TISCI_DEV_MMCSD1,
+    TISCI_DEV_MMCSD2,
+    TISCI_DEV_GPIO0,
+    TISCI_DEV_GPIO1,
+    TISCI_DEV_GPIO2,
+    TISCI_DEV_GPIO3,
+    TISCI_DEV_GPIO4,
+    TISCI_DEV_GPIO5,
+    TISCI_DEV_GPIO6,
+    TISCI_DEV_GPIO7,
+    TISCI_DEV_PRU_ICSSG0,
+    TISCI_DEV_PRU_ICSSG1,
+    TISCI_DEV_UART0,
+    TISCI_DEV_MCAN0,
+    TISCI_DEV_MCAN1,
+    TISCI_DEV_MCAN2,
+    TISCI_DEV_MCAN3,
+    TISCI_DEV_MCAN4,
+    TISCI_DEV_MCAN5,
+    TISCI_DEV_MCAN6,
+    TISCI_DEV_MCAN7,
+    TISCI_DEV_MCAN8,
+    TISCI_DEV_MCAN9,
+    TISCI_DEV_MCAN10,
+    TISCI_DEV_MCAN11,
+    TISCI_DEV_MCAN12,
+    TISCI_DEV_MCAN13,
+    TISCI_DEV_MCASP0,
+    TISCI_DEV_MCASP1,
+    TISCI_DEV_MCASP2,
+    TISCI_DEV_MCASP3,
+    TISCI_DEV_MCASP4,
+    TISCI_DEV_MCASP5,
+    TISCI_DEV_MCASP6,
+    TISCI_DEV_MCASP7,
+    TISCI_DEV_MCASP8,
+    TISCI_DEV_MCASP9,
+    TISCI_DEV_MCASP10,
+    TISCI_DEV_MCASP11,
+    TISCI_DEV_I2C0,
+    TISCI_DEV_I2C1,
+    TISCI_DEV_I2C2,
+    TISCI_DEV_I2C3,
+    TISCI_DEV_I2C4,
+    TISCI_DEV_I2C5,
+    TISCI_DEV_I2C6,
+    TISCI_DEV_PCIE0,
+    TISCI_DEV_PCIE1,
+    TISCI_DEV_PCIE2,
+    TISCI_DEV_PCIE3,
+    TISCI_DEV_UFS0,
+    TISCI_DEV_UART1,
+    TISCI_DEV_UART2,
+    TISCI_DEV_UART3,
+    TISCI_DEV_UART4,
+    TISCI_DEV_UART5,
+    TISCI_DEV_UART6,
+    TISCI_DEV_UART7,
+    TISCI_DEV_UART8,
+    TISCI_DEV_UART9,
+    TISCI_DEV_USB0,
+    TISCI_DEV_USB1,
+    TISCI_DEV_VPFE0,
+    TISCI_DEV_SERDES_16G0,
+    TISCI_DEV_SERDES_16G1,
+    TISCI_DEV_SERDES_16G2,
+    TISCI_DEV_SERDES_16G3,
+    TISCI_DEV_SERDES_10G0,
+    TISCI_DEV_SA2_UL0,
+};
+
+/**
+ * \brief Disables module clock
+ *
+ * \return  BOARD_SOK   - Clock disable successful.
+ *          BOARD_FAIL  - Clock disable failed.
+ *
+ */
+Board_STATUS Board_moduleClockDisable(uint32_t moduleId)
+{
+    Board_STATUS retVal = BOARD_SOK;
+       int32_t      status = CSL_EFAIL;
+    uint32_t     moduleState = 0U;
+    uint32_t     resetState = 0U;
+    uint32_t     contextLossState = 0U;
+
+    /* Get the module state.
+       No need to change the module state if it
+       is already OFF 
+     */
+    status = Sciclient_pmGetModuleState(moduleId,
+                                        &moduleState,
+                                        &resetState,
+                                        &contextLossState,
+                                        SCICLIENT_SERVICE_WAIT_FOREVER);
+    if(moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_OFF)
+    {
+        status = Sciclient_pmSetModuleState(moduleId,
+                                            TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
+                                            (TISCI_MSG_FLAG_AOP |
+                                             TISCI_MSG_FLAG_DEVICE_RESET_ISO),
+                                             SCICLIENT_SERVICE_WAIT_FOREVER);
+        if (status == CSL_PASS)
+        {
+            status = Sciclient_pmSetModuleRst (moduleId,
+                                               0x1U,
+                                               SCICLIENT_SERVICE_WAIT_FOREVER);
+            if (status != CSL_PASS)
+            {
+                retVal = BOARD_FAIL;
+            }
+        }
+        else
+        {
+            retVal = BOARD_FAIL;
+        }
+    }
+
+    return retVal;
+}
+
+/**
+ * \brief Enables module clock
+ *
+ * \return  BOARD_SOK   - Clock enable sucessful. 
+ *          BOARD_FAIL  - Clock enable failed.
+ *
+ */
+Board_STATUS Board_moduleClockEnable(uint32_t moduleId)
+{
+    Board_STATUS retVal = BOARD_SOK;
+       int32_t      status = CSL_EFAIL;
+    uint32_t     moduleState = 0U;
+    uint32_t     resetState = 0U;
+    uint32_t     contextLossState = 0U;
+    
+    /* Get the module state. 
+       No need to change the module state if it
+       is already ON 
+     */
+    status = Sciclient_pmGetModuleState(moduleId,
+                                        &moduleState,
+                                        &resetState,
+                                        &contextLossState,
+                                        SCICLIENT_SERVICE_WAIT_FOREVER);
+    if(moduleState == TISCI_MSG_VALUE_DEVICE_HW_STATE_OFF)
+    {
+        if(gBoardInitParams.pscMode == BOARD_PSC_DEVICE_MODE_NONEXCLUSIVE)
+        {
+            status = Sciclient_pmSetModuleState(moduleId,
+                                                TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
+                                                (TISCI_MSG_FLAG_AOP |
+                                                 TISCI_MSG_FLAG_DEVICE_RESET_ISO),
+                                                 SCICLIENT_SERVICE_WAIT_FOREVER);
+        }
+        else
+        {
+            status = Sciclient_pmSetModuleState(moduleId,
+                                                TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
+                                                (TISCI_MSG_FLAG_AOP |
+                                                 TISCI_MSG_FLAG_DEVICE_EXCLUSIVE |
+                                                 TISCI_MSG_FLAG_DEVICE_RESET_ISO),
+                                                 SCICLIENT_SERVICE_WAIT_FOREVER);
+        }
+        if (status == CSL_PASS)
+        {
+            status = Sciclient_pmSetModuleRst (moduleId,
+                                               0x0U,
+                                               SCICLIENT_SERVICE_WAIT_FOREVER);
+            if (status != CSL_PASS)
+            {
+                retVal = BOARD_FAIL;
+            }
+        }
+        else
+        {
+            retVal = BOARD_FAIL;
+        }
+    }
+
+    return retVal;
+}
+
+/**
+ * \brief clock Initialization function for MCU domain
+ *
+ * Enables different power domains and peripheral clocks of the MCU.
+ * Some of the power domains and peripherals will be OFF by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * \return  BOARD_SOK              - Clock initialization sucessful.
+ *          BOARD_INIT_CLOCK_FAIL  - Clock initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockInitMcu(void)
+{
+       Board_STATUS  status = BOARD_SOK;
+    uint32_t index;
+    uint32_t loopCount;
+
+    loopCount = sizeof(gBoardClkModuleMcuID) / sizeof(uint32_t);
+
+    for(index = 0; index < loopCount; index++)
+    {
+        status = Board_moduleClockEnable(gBoardClkModuleMcuID[index]);
+        if(status != BOARD_SOK)
+        {
+            status = BOARD_INIT_CLOCK_FAIL;
+            break;
+        }
+    }
+
+#if defined(BUILD_MCU)
+    if(status == BOARD_SOK)
+    {
+        int32_t  ret;
+        uint64_t mcuClkFreq;
+
+        ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_R5FSS0_CORE0,
+                                           TISCI_DEV_MCU_R5FSS0_CORE0_CPU_CLK,
+                                           &mcuClkFreq,
+                                           SCICLIENT_SERVICE_WAIT_FOREVER);
+        if(ret == 0)
+        {
+            Osal_HwAttrs  hwAttrs;
+            uint32_t      ctrlBitmap;
+
+            ret = Osal_getHwAttrs(&hwAttrs);
+            if(ret == 0)
+            {
+                /*
+                 * Change the timer input clock frequency configuration
+                   based on R5 CPU clock configured
+                 */
+                hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);
+                ctrlBitmap         = OSAL_HWATTR_SET_CPU_FREQ;
+                ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
+            }
+        }
+        if(ret != 0)
+        {
+            status = BOARD_INIT_CLOCK_FAIL;
+        }
+    }
+#endif
+
+    return status;
+}
+
+/**
+ * \brief clock Initialization function for MAIN domain
+ *
+ * Enables different power domains and peripheral clocks of the SoC.
+ * Some of the power domains and peripherals will be OFF by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * \return  BOARD_SOK              - Clock initialization successful.
+ *          BOARD_INIT_CLOCK_FAIL  - Clock initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockInitMain(void)
+{
+       Board_STATUS  status = BOARD_SOK;
+    uint32_t index;
+    uint32_t loopCount;
+
+    loopCount = sizeof(gBoardClkModuleMainID) / sizeof(uint32_t);
+
+    for(index = 0; index < loopCount; index++)
+    {
+        status = Board_moduleClockEnable(gBoardClkModuleMainID[index]);
+        if(status != BOARD_SOK)
+        {
+            return BOARD_INIT_CLOCK_FAIL;
+        }
+    }
+
+    return status;
+}
+
+/**
+ * \brief clock de-initialization function for MCU domain
+ *
+ * Disables different power domains and peripheral clocks of the SoC.
+ *
+ * \return  BOARD_SOK              - Clock de-initialization successful. 
+ *          BOARD_INIT_CLOCK_FAIL  - Clock de-initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockDeinitMcu(void)
+{
+       Board_STATUS  status = BOARD_SOK;
+    uint32_t index;
+    uint32_t loopCount;
+
+    loopCount = sizeof(gBoardClkModuleMcuID) / sizeof(uint32_t);
+
+    for(index = 0; index < loopCount; index++)
+    {
+        status = Board_moduleClockDisable(gBoardClkModuleMcuID[index]);
+        if(status != BOARD_SOK)
+        {
+            return BOARD_INIT_CLOCK_FAIL;
+        }
+    }
+
+    return status;
+}
+
+/**
+ * \brief clock de-initialization function for MAIN domain
+ *
+ * Disables different power domains and peripheral clocks of the SoC.
+ *
+ * \return  BOARD_SOK              - Clock de-initialization successful.
+ *          BOARD_INIT_CLOCK_FAIL  - Clock de-initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockDeinitMain(void)
+{
+    Board_STATUS  status = BOARD_SOK;
+    uint32_t index;
+    uint32_t loopCount;
+
+    loopCount = sizeof(gBoardClkModuleMainID) / sizeof(uint32_t);
+
+    for(index = 0; index < loopCount; index++)
+    {
+        status = Board_moduleClockDisable(gBoardClkModuleMainID[index]);
+        if(status != BOARD_SOK)
+        {
+            return BOARD_INIT_CLOCK_FAIL;
+        }
+    }
+
+    return status;
+}
diff --git a/packages/ti/board/src/j7200_evm/board_control.c b/packages/ti/board/src/j7200_evm/board_control.c
new file mode 100644 (file)
index 0000000..68d0bd7
--- /dev/null
@@ -0,0 +1,319 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ *  \file   board_control.c\r
+ *\r
+ *  \brief  Implements multiple board control functions\r
+ *\r
+ */\r
+\r
+#include "board_control.h"\r
+\r
+/**\r
+ * \brief Configures HDMI PD pin to high\r
+ *\r
+ *  \return   Board_SOK in case of success or appropriate error code.\r
+ *\r
+ */\r
+static Board_STATUS Board_setIoExpPinOutput(Board_IoExpCfg_t *cfg)\r
+{\r
+    Board_I2cInitCfg_t i2cCfg;\r
+    Board_STATUS status;\r
+\r
+    i2cCfg.i2cInst    = cfg->i2cInst;\r
+    i2cCfg.socDomain  = cfg->socDomain;\r
+    i2cCfg.enableIntr = cfg->enableIntr;\r
+    Board_setI2cInitConfig(&i2cCfg);\r
+\r
+    status = Board_i2cIoExpInit();\r
+    if(status == BOARD_SOK)\r
+    {\r
+        /* Setting the pin direction as output */\r
+        status = Board_i2cIoExpSetPinDirection(cfg->slaveAddr,\r
+                                               cfg->ioExpType,\r
+                                               cfg->portNum,\r
+                                               cfg->pinNum,\r
+                                               PIN_DIRECTION_OUTPUT);\r
+        BOARD_delay(1000);\r
+        /* Pulling the hdmi power pin to low */\r
+        status |= Board_i2cIoExpPinLevelSet(cfg->slaveAddr,\r
+                                            cfg->ioExpType,\r
+                                            cfg->portNum,\r
+                                            cfg->pinNum,\r
+                                            cfg->signalLevel);\r
+        BOARD_delay(1000);\r
+\r
+        Board_i2cIoExpDeInit();\r
+    }\r
+\r
+    return status;\r
+}\r
+\r
+/**\r
+ * \brief Configures HDMI IO mux\r
+ *\r
+ *  \return   Board_SOK in case of success or appropriate error code.\r
+ *\r
+ */\r
+static Board_STATUS Board_setHDMIMux(void)\r
+{\r
+    Board_IoExpCfg_t ioExpCfg;\r
+    Board_STATUS status;\r
+\r
+    ioExpCfg.i2cInst     = BOARD_I2C_IOEXP_DEVICE1_INSTANCE;\r
+    ioExpCfg.socDomain   = BOARD_SOC_DOMAIN_MAIN;\r
+    ioExpCfg.slaveAddr   = BOARD_I2C_IOEXP_DEVICE1_ADDR;\r
+    ioExpCfg.enableIntr  = false;    \r
+    ioExpCfg.ioExpType   = TWO_PORT_IOEXP;\r
+    ioExpCfg.portNum     = PORTNUM_1;\r
+    ioExpCfg.pinNum      = PIN_NUM_4;\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;\r
+\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+    if(status != BOARD_SOK)\r
+    {\r
+        return status;\r
+    }\r
+\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;\r
+    ioExpCfg.pinNum = PIN_NUM_5;\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+\r
+    return status;\r
+}\r
+\r
+/**\r
+ * \brief Configures HDMI PD pin to high\r
+ *\r
+ *  \return   Board_SOK in case of success or appropriate error code.\r
+ *\r
+ */\r
+static Board_STATUS Board_setHDMIPdHigh(void)\r
+{\r
+    Board_IoExpCfg_t ioExpCfg;\r
+    Board_STATUS status;\r
+\r
+    ioExpCfg.i2cInst     = BOARD_HDMI_IO_EXP_INSTANCE;\r
+    ioExpCfg.socDomain   = BOARD_SOC_DOMAIN_MAIN;\r
+    ioExpCfg.slaveAddr   = BOARD_HDMI_IO_SLAVE_ADDR;\r
+    ioExpCfg.enableIntr  = false;\r
+    ioExpCfg.ioExpType   = TWO_PORT_IOEXP;\r
+    ioExpCfg.portNum     = PORTNUM_1;\r
+    ioExpCfg.pinNum      = PIN_NUM_0;\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;\r
+\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+\r
+    return status;\r
+}\r
+\r
+/**\r
+ * \brief   Configures ICSSG MDIO mux to low\r
+ *\r
+ * \return  Board_SOK in case of success or appropriate error code.\r
+ *\r
+ */\r
+static Board_STATUS Board_setIcssgMdioMux(void)\r
+{\r
+    Board_IoExpCfg_t ioExpCfg;\r
+    Board_STATUS status;\r
+\r
+    ioExpCfg.i2cInst     = BOARD_I2C_IOEXP_DEVICE1_INSTANCE;\r
+    ioExpCfg.socDomain   = BOARD_SOC_DOMAIN_MAIN;\r
+    ioExpCfg.slaveAddr   = BOARD_I2C_IOEXP_DEVICE1_ADDR;\r
+    ioExpCfg.enableIntr  = false;\r
+    ioExpCfg.ioExpType   = TWO_PORT_IOEXP;\r
+    ioExpCfg.portNum     = PORTNUM_1;\r
+    ioExpCfg.pinNum      = PIN_NUM_5;\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;\r
+\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+    if(status != BOARD_SOK)\r
+    {\r
+        return status;\r
+    }\r
+\r
+    ioExpCfg.pinNum = PIN_NUM_6;\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+\r
+    return status;\r
+}\r
+\r
+/**\r
+ * \brief   Configures CPSW9G mux to high\r
+ *\r
+ * \return  Board_SOK in case of success or appropriate error code.\r
+ *\r
+ */\r
+static Board_STATUS Board_setCpsw9GMdioMux(void)\r
+{\r
+    Board_IoExpCfg_t ioExpCfg;\r
+    Board_STATUS status;\r
+\r
+    ioExpCfg.i2cInst     = BOARD_I2C_IOEXP_DEVICE1_INSTANCE;\r
+    ioExpCfg.socDomain   = BOARD_SOC_DOMAIN_MAIN;\r
+    ioExpCfg.slaveAddr   = BOARD_I2C_IOEXP_DEVICE1_ADDR;\r
+    ioExpCfg.enableIntr  = false;\r
+    ioExpCfg.ioExpType   = TWO_PORT_IOEXP;\r
+    ioExpCfg.portNum     = PORTNUM_1;\r
+    ioExpCfg.pinNum      = PIN_NUM_5;\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;\r
+\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+    if(status != BOARD_SOK)\r
+    {\r
+        return status;\r
+    }\r
+\r
+    ioExpCfg.pinNum = PIN_NUM_6;\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+\r
+    return status;\r
+}\r
+\r
+/**\r
+ * \brief Configures PRG1 RGMII mux\r
+ *\r
+ *  \return   Board_SOK in case of success or appropriate error code.\r
+ *\r
+ */\r
+static Board_STATUS Board_setPRG1RGMIIMux(void)\r
+{\r
+    Board_IoExpCfg_t ioExpCfg;\r
+    Board_STATUS status;\r
+\r
+    ioExpCfg.i2cInst     = BOARD_I2C_IOEXP_DEVICE1_INSTANCE;\r
+    ioExpCfg.socDomain   = BOARD_SOC_DOMAIN_MAIN;\r
+    ioExpCfg.slaveAddr   = BOARD_I2C_IOEXP_DEVICE1_ADDR;\r
+    ioExpCfg.enableIntr  = false;\r
+    ioExpCfg.ioExpType   = TWO_PORT_IOEXP;\r
+    ioExpCfg.portNum     = PORTNUM_1;\r
+    ioExpCfg.pinNum      = PIN_NUM_4;\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;\r
+\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+\r
+    return status;\r
+}\r
+\r
+/**\r
+ * \brief   Configures data path for GPMC pins\r
+ *\r
+ * \return  Board_SOK in case of success or appropriate error code.\r
+ *\r
+ */\r
+static Board_STATUS Board_setGpmcDataMux(void)\r
+{\r
+    Board_IoExpCfg_t ioExpCfg;\r
+    Board_STATUS status;\r
+\r
+    ioExpCfg.i2cInst     = BOARD_I2C_IOEXP_DEVICE2_INSTANCE;\r
+    ioExpCfg.socDomain   = BOARD_SOC_DOMAIN_MAIN;\r
+    ioExpCfg.slaveAddr   = BOARD_I2C_IOEXP_DEVICE2_ADDR;\r
+    ioExpCfg.enableIntr  = false;\r
+    ioExpCfg.ioExpType   = THREE_PORT_IOEXP;\r
+    ioExpCfg.portNum     = PORTNUM_1;\r
+    ioExpCfg.pinNum      = PIN_NUM_1;\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;\r
+\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+    if(status != BOARD_SOK)\r
+    {\r
+        return status;\r
+    }\r
+\r
+    ioExpCfg.pinNum = PIN_NUM_2;\r
+    ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;\r
+    status = Board_setIoExpPinOutput(&ioExpCfg);\r
+\r
+    return status;\r
+}\r
+\r
+/**\r
+ * \brief Board control function\r
+ *\r
+ * \param   cmd  [IN]  Board control command\r
+ * \param   arg  [IN]  Control command argument. \r
+ *                     Changes based on the command\r
+ *\r
+ * \return   TRUE if the given board is detected else 0.\r
+ *           SoM board will be always connected to the base board.\r
+ *           For SoM boardID return value TRUE indicates dual PMIC\r
+ *           SoM and FALSE indicates alternate PMIC SoM\r
+ *\r
+ */\r
+Board_STATUS Board_control(uint32_t cmd, void *arg)\r
+{\r
+    Board_STATUS status;\r
+\r
+    switch (cmd)\r
+    {\r
+        case BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT:\r
+            status = Board_setIoExpPinOutput((Board_IoExpCfg_t *)arg);\r
+            break;\r
+        case BOARD_CTRL_CMD_SET_HDMI_MUX:\r
+            status = Board_setHDMIMux();\r
+            break;\r
+\r
+        case BOARD_CTRL_CMD_SET_HDMI_PD_HIGH:\r
+            status = Board_setHDMIPdHigh();\r
+            break;\r
+\r
+        case BOARD_CTRL_CMD_SET_ICSSG_MDIO_MUX:\r
+            status = Board_setIcssgMdioMux();\r
+            break;\r
+\r
+        case BOARD_CTRL_CMD_SET_CPSW9G_MDIO_MUX:\r
+            status = Board_setCpsw9GMdioMux();\r
+            break;\r
+\r
+        case BOARD_CTRL_CMD_SET_PRG1_RGMII_MDIO_MUX:\r
+            status = Board_setPRG1RGMIIMux();\r
+            break;\r
+\r
+        case BOARD_CTRL_CMD_SET_RS485_UART4_EN_MUX:\r
+        case BOARD_CTRL_CMD_SET_RMII_DATA_MUX:\r
+            status = Board_setGpmcDataMux();\r
+            break;\r
+\r
+        default:\r
+            status = BOARD_INVALID_PARAM;\r
+            break;\r
+    }\r
+\r
+    return status;\r
+}\r
+\r
diff --git a/packages/ti/board/src/j7200_evm/board_ddr.c b/packages/ti/board/src/j7200_evm/board_ddr.c
new file mode 100644 (file)
index 0000000..659af4d
--- /dev/null
@@ -0,0 +1,1836 @@
+/******************************************************************************
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/** \file board_ddr.c
+ *
+ *  \brief This file used to configure the DDR timing parameters.
+ *
+ */
+
+#include "board_ddr.h"
+#include "board_utils.h"
+#include <ti/drv/sciclient/sciclient.h>
+
+/* ************************************************************************* */
+/* Global Helper Functions */
+/* ************************************************************************* */
+
+/* Write to a specific field in an MMR. */
+static void Board_DDRWriteMMRField(uint32_t mmrAddr,
+                                   uint32_t fieldVal,
+                                   uint32_t width,
+                                   uint32_t leftshift)
+{
+    uint32_t pMMR;
+    uint32_t mask;
+    pMMR = HW_RD_REG32(mmrAddr);   //Grab the MMR value
+    mask = (((1 << width) - 1) << leftshift); //Build a mask of 1s for the field.
+    mask = ~(mask); //Invert the mask so that the field will be zero'd out with the AND operation.
+    pMMR &= mask; //Zero out the field in the register.
+    pMMR |= (fieldVal << leftshift); //Assign the value to that specific field.
+    HW_WR_REG32(mmrAddr, pMMR);
+}
+
+/**
+ * \brief   Write the unlocking keys to the locking registers.
+ *
+ * \param   kick0                              The first lock register.
+ *
+ * \param   kick1                              The second lock register.
+ *
+ * \return  status                             This should return 0 on a successful unlock.
+ */
+static uint32_t Board_DDRMMRUnlockOne(uint32_t kick0, uint32_t kick1)
+{
+    // initialize the status variable
+    uint32_t status = 1;
+
+    // if either of the kick lock registers are locked
+    if (!(kick0 & 0x1) | !(kick1 & 0x1)){
+        // unlock the partition by writing the unlock values to the kick lock registers
+        kick0 = KICK0_UNLOCK;
+        kick1 = KICK1_UNLOCK;
+    }
+
+    // check to see if either of the kick registers are unlocked.
+    if (!(kick0 & 0x1)){
+        status = 0;
+    }
+
+    // return the status to the calling program
+    return status;
+
+}
+
+/**
+ * \brief   Unlock the partition for a specific PLL.
+ *
+ * \param   BaseAddr                   The base address of the PLL MMR instance.
+ * \param   addrOffset          MMR register offset.
+ * \param   PLLIndex                   The index of the PLL (one PLL per partition).
+ *
+ * \return  none
+ */
+static void Board_DDRUnlockPLLMMR(uint32_t BaseAddr, 
+                                  uint32_t addrOffset, 
+                                  uint32_t PLLIndex)
+{
+       uint32_t firstMMR; 
+    uint32_t secondMMR;
+
+       //Calculate the first lock register address based on the PLL index.
+       firstMMR = 0x10 + (PLLIndex * 0x1000) + BaseAddr + addrOffset;
+       //Calculate tthe second lock register address based on the PLL index.
+       secondMMR = 0x14 + (PLLIndex * 0x1000) + BaseAddr + addrOffset;
+       //Unlock the MMR region with those addresses.
+       Board_DDRMMRUnlockOne(HW_RD_REG32(firstMMR), HW_RD_REG32(secondMMR));
+}
+
+/**
+ * \brief   Set DDR PLL to bypass, efectively 20MHz or 19.2MHz (on silicon).
+ *
+ * \param   none
+ *
+ * \return  none
+ */
+static void Board_DDRSetPLLExtBypass(void)
+{
+
+       uint32_t addrOffset = 0x00000000;
+       uint32_t BaseAddr = CSL_PLL0_CFG_BASE;
+       uint32_t PLLIndex = DDR_PLL_INDEX;
+
+    Board_DDRUnlockPLLMMR(CSL_PLL0_CFG_BASE, addrOffset, PLLIndex);
+       //BOARD_DEBUG_LOG("Setting DDR PLL to 20MHz/19.2MHz on silicon (bypass)\n");
+               //Put the PLL in external bypass first. Write "1" to bit #31 in the control register.
+       Board_DDRWriteMMRField((BaseAddr + addrOffset + (PLLIndex * 0x1000) + CONTROL), 1, 1, 31);
+       //BOARD_DEBUG_LOG("Set PLL to external bypass\n");
+}
+
+/**
+ * \brief   Set DDR PLL clock value
+ *
+ * \param   none
+ *
+ * \return  none
+ */
+static void Board_DDRSetPLLClock(void)
+{
+    Board_STATUS  status = BOARD_SOK;
+    status = Board_PLLInit(TISCI_DEV_DDR0,
+                           TISCI_DEV_DDR0_DDRSS_DDR_PLL_CLK,
+                           DDRSS_PLL_FREQUENCY);
+    if(status != BOARD_SOK)
+    {
+        BOARD_DEBUG_LOG("Failed to set the PLL clock freq\n");
+    }
+}
+
+static void Board_DDRChangeFreqAck(void)
+{
+      uint32_t reqType, regVal;
+      volatile uint32_t counter, counter2;
+      volatile uint32_t temp = 0;
+
+      temp = temp;  /* To suppress compiler warning */
+      BOARD_DEBUG_LOG("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
+
+      for(counter = 0; counter < DDRSS_PLL_FHS_CNT; counter++)
+      {
+          //wait for freq change request
+          regVal = HW_RD_REG32(0x00114080) & 0x80;
+          BOARD_DEBUG_LOG("Reg Value: %d \n",,,,, regVal);
+          while(regVal == 0x0){
+              regVal = HW_RD_REG32(0x00114080) & 0x80;
+              BOARD_DEBUG_LOG("Reg Value: %d \n",,,,, regVal);
+          }
+
+              reqType = HW_RD_REG32(0x00114080) & 0x03;
+              BOARD_DEBUG_LOG("Frequency Change type %d request from Controller \n",,,,, reqType);
+
+              if(reqType == 1){
+                  Board_DDRSetPLLClock();
+              }else if(reqType == 2){
+                  Board_DDRSetPLLClock(); //Set_DDR_PLL_933MHz
+              }else if(reqType == 0){
+                  Board_DDRSetPLLExtBypass();
+              }else{
+                  //BOARD_DEBUG_LOG("error\n",,,,,);
+              }
+
+              counter2 = 0;
+              while(counter2 < 200){
+                  temp = HW_RD_REG32(0x00114080);
+                  counter2++;
+              }
+
+              HW_WR_REG32(0x001140C0, 0x1); //set the ack bit
+
+              counter2 = 0;
+              while(counter2 < 10){
+                  temp = HW_RD_REG32(0x00114080);
+                  counter2++;
+              }
+
+              while((HW_RD_REG32(0x00114080) & 0x80) == 0x80);
+
+              counter2 = 0;
+              while(counter2 < 10){
+                  temp = HW_RD_REG32(0x00114080);
+                  counter2++;
+              }
+
+              HW_WR_REG32(0x001140C0, 0x0); //clear the ack bit
+
+              counter2 = 0;
+              while(counter2 < 10){
+                  temp= HW_RD_REG32(0x00114080);
+                  counter2++;
+              }
+      }
+       
+    BOARD_DEBUG_LOG("--->>> Frequency Change request handshake is completed... <<<---\n");
+}
+
+/**
+ * \brief DDR4 Initialization function
+ *
+ * Initializes the DDR timing parameters. Sets the DDR timing parameters
+ * based in the DDR PLL controller configuration done by the board library.
+ * Any changes to DDR PLL requires change to DDR timing.
+ *
+ * \param   void
+ *
+ * \return  BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_DDRInit(void)
+{
+    Board_unlockMMR();
+
+    Board_DDRSetPLLExtBypass();
+
+    //Program the DDR Controller
+    BOARD_DEBUG_LOG("--->>> DDR controller programming in progress.. <<<---\n");
+    BOARD_delay(100000);
+
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_0_OFFSET,   DDRSS_CTL_00_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_1_OFFSET,   DDRSS_CTL_01_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_2_OFFSET,   DDRSS_CTL_02_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_3_OFFSET,   DDRSS_CTL_03_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_4_OFFSET,   DDRSS_CTL_04_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_5_OFFSET,   DDRSS_CTL_05_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_6_OFFSET,   DDRSS_CTL_06_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_7_OFFSET,   DDRSS_CTL_07_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_8_OFFSET,   DDRSS_CTL_08_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_9_OFFSET,   DDRSS_CTL_09_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_10_OFFSET,  DDRSS_CTL_10_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_11_OFFSET,  DDRSS_CTL_11_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_12_OFFSET,  DDRSS_CTL_12_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_13_OFFSET,  DDRSS_CTL_13_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_14_OFFSET,  DDRSS_CTL_14_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_15_OFFSET,  DDRSS_CTL_15_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_16_OFFSET,  DDRSS_CTL_16_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_17_OFFSET,  DDRSS_CTL_17_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_18_OFFSET,  DDRSS_CTL_18_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_19_OFFSET,  DDRSS_CTL_19_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_20_OFFSET,  DDRSS_CTL_20_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_21_OFFSET,  DDRSS_CTL_21_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_22_OFFSET,  DDRSS_CTL_22_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_23_OFFSET,  DDRSS_CTL_23_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_24_OFFSET,  DDRSS_CTL_24_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_25_OFFSET,  DDRSS_CTL_25_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_26_OFFSET,  DDRSS_CTL_26_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_27_OFFSET,  DDRSS_CTL_27_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_28_OFFSET,  DDRSS_CTL_28_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_29_OFFSET,  DDRSS_CTL_29_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_30_OFFSET,  DDRSS_CTL_30_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_31_OFFSET,  DDRSS_CTL_31_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_32_OFFSET,  DDRSS_CTL_32_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_33_OFFSET,  DDRSS_CTL_33_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_34_OFFSET,  DDRSS_CTL_34_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_35_OFFSET,  DDRSS_CTL_35_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_36_OFFSET,  DDRSS_CTL_36_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_37_OFFSET,  DDRSS_CTL_37_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_38_OFFSET,  DDRSS_CTL_38_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_39_OFFSET,  DDRSS_CTL_39_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_40_OFFSET,  DDRSS_CTL_40_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_41_OFFSET,  DDRSS_CTL_41_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_42_OFFSET,  DDRSS_CTL_42_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_43_OFFSET,  DDRSS_CTL_43_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_44_OFFSET,  DDRSS_CTL_44_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_45_OFFSET,  DDRSS_CTL_45_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_46_OFFSET,  DDRSS_CTL_46_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_47_OFFSET,  DDRSS_CTL_47_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_48_OFFSET,  DDRSS_CTL_48_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_49_OFFSET,  DDRSS_CTL_49_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_50_OFFSET,  DDRSS_CTL_50_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_51_OFFSET,  DDRSS_CTL_51_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_52_OFFSET,  DDRSS_CTL_52_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_53_OFFSET,  DDRSS_CTL_53_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_54_OFFSET,  DDRSS_CTL_54_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_55_OFFSET,  DDRSS_CTL_55_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_56_OFFSET,  DDRSS_CTL_56_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_57_OFFSET,  DDRSS_CTL_57_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_58_OFFSET,  DDRSS_CTL_58_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_59_OFFSET,  DDRSS_CTL_59_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_60_OFFSET,  DDRSS_CTL_60_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_61_OFFSET,  DDRSS_CTL_61_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_62_OFFSET,  DDRSS_CTL_62_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_63_OFFSET,  DDRSS_CTL_63_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_64_OFFSET,  DDRSS_CTL_64_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_65_OFFSET,  DDRSS_CTL_65_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_66_OFFSET,  DDRSS_CTL_66_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_67_OFFSET,  DDRSS_CTL_67_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_68_OFFSET,  DDRSS_CTL_68_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_69_OFFSET,  DDRSS_CTL_69_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_70_OFFSET,  DDRSS_CTL_70_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_71_OFFSET,  DDRSS_CTL_71_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_72_OFFSET,  DDRSS_CTL_72_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_73_OFFSET,  DDRSS_CTL_73_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_74_OFFSET,  DDRSS_CTL_74_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_75_OFFSET,  DDRSS_CTL_75_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_76_OFFSET,  DDRSS_CTL_76_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_77_OFFSET,  DDRSS_CTL_77_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_78_OFFSET,  DDRSS_CTL_78_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_79_OFFSET,  DDRSS_CTL_79_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_80_OFFSET,  DDRSS_CTL_80_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_81_OFFSET,  DDRSS_CTL_81_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_82_OFFSET,  DDRSS_CTL_82_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_83_OFFSET,  DDRSS_CTL_83_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_84_OFFSET,  DDRSS_CTL_84_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_85_OFFSET,  DDRSS_CTL_85_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_86_OFFSET,  DDRSS_CTL_86_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_87_OFFSET,  DDRSS_CTL_87_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_88_OFFSET,  DDRSS_CTL_88_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_89_OFFSET,  DDRSS_CTL_89_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_90_OFFSET,  DDRSS_CTL_90_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_91_OFFSET,  DDRSS_CTL_91_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_92_OFFSET,  DDRSS_CTL_92_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_93_OFFSET,  DDRSS_CTL_93_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_94_OFFSET,  DDRSS_CTL_94_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_95_OFFSET,  DDRSS_CTL_95_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_96_OFFSET,  DDRSS_CTL_96_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_97_OFFSET,  DDRSS_CTL_97_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_98_OFFSET,  DDRSS_CTL_98_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_99_OFFSET,  DDRSS_CTL_99_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_100_OFFSET, DDRSS_CTL_100_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_101_OFFSET, DDRSS_CTL_101_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_102_OFFSET, DDRSS_CTL_102_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_103_OFFSET, DDRSS_CTL_103_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_104_OFFSET, DDRSS_CTL_104_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_105_OFFSET, DDRSS_CTL_105_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_106_OFFSET, DDRSS_CTL_106_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_107_OFFSET, DDRSS_CTL_107_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_108_OFFSET, DDRSS_CTL_108_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_109_OFFSET, DDRSS_CTL_109_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_110_OFFSET, DDRSS_CTL_110_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_111_OFFSET, DDRSS_CTL_111_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_112_OFFSET, DDRSS_CTL_112_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_113_OFFSET, DDRSS_CTL_113_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_114_OFFSET, DDRSS_CTL_114_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_115_OFFSET, DDRSS_CTL_115_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_116_OFFSET, DDRSS_CTL_116_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_117_OFFSET, DDRSS_CTL_117_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_118_OFFSET, DDRSS_CTL_118_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_119_OFFSET, DDRSS_CTL_119_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_120_OFFSET, DDRSS_CTL_120_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_121_OFFSET, DDRSS_CTL_121_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_122_OFFSET, DDRSS_CTL_122_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_123_OFFSET, DDRSS_CTL_123_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_124_OFFSET, DDRSS_CTL_124_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_125_OFFSET, DDRSS_CTL_125_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_126_OFFSET, DDRSS_CTL_126_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_127_OFFSET, DDRSS_CTL_127_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_128_OFFSET, DDRSS_CTL_128_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_129_OFFSET, DDRSS_CTL_129_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_130_OFFSET, DDRSS_CTL_130_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_131_OFFSET, DDRSS_CTL_131_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_132_OFFSET, DDRSS_CTL_132_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_133_OFFSET, DDRSS_CTL_133_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_134_OFFSET, DDRSS_CTL_134_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_135_OFFSET, DDRSS_CTL_135_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_136_OFFSET, DDRSS_CTL_136_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_137_OFFSET, DDRSS_CTL_137_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_138_OFFSET, DDRSS_CTL_138_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_139_OFFSET, DDRSS_CTL_139_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_140_OFFSET, DDRSS_CTL_140_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_141_OFFSET, DDRSS_CTL_141_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_142_OFFSET, DDRSS_CTL_142_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_143_OFFSET, DDRSS_CTL_143_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_144_OFFSET, DDRSS_CTL_144_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_145_OFFSET, DDRSS_CTL_145_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_146_OFFSET, DDRSS_CTL_146_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_147_OFFSET, DDRSS_CTL_147_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_148_OFFSET, DDRSS_CTL_148_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_149_OFFSET, DDRSS_CTL_149_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_150_OFFSET, DDRSS_CTL_150_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_151_OFFSET, DDRSS_CTL_151_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_152_OFFSET, DDRSS_CTL_152_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_153_OFFSET, DDRSS_CTL_153_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_154_OFFSET, DDRSS_CTL_154_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_155_OFFSET, DDRSS_CTL_155_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_156_OFFSET, DDRSS_CTL_156_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_157_OFFSET, DDRSS_CTL_157_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_158_OFFSET, DDRSS_CTL_158_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_159_OFFSET, DDRSS_CTL_159_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_160_OFFSET, DDRSS_CTL_160_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_161_OFFSET, DDRSS_CTL_161_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_162_OFFSET, DDRSS_CTL_162_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_163_OFFSET, DDRSS_CTL_163_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_164_OFFSET, DDRSS_CTL_164_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_165_OFFSET, DDRSS_CTL_165_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_166_OFFSET, DDRSS_CTL_166_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_167_OFFSET, DDRSS_CTL_167_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_168_OFFSET, DDRSS_CTL_168_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_169_OFFSET, DDRSS_CTL_169_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_170_OFFSET, DDRSS_CTL_170_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_171_OFFSET, DDRSS_CTL_171_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_172_OFFSET, DDRSS_CTL_172_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_173_OFFSET, DDRSS_CTL_173_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_174_OFFSET, DDRSS_CTL_174_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_175_OFFSET, DDRSS_CTL_175_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_176_OFFSET, DDRSS_CTL_176_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_177_OFFSET, DDRSS_CTL_177_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_178_OFFSET, DDRSS_CTL_178_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_179_OFFSET, DDRSS_CTL_179_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_180_OFFSET, DDRSS_CTL_180_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_181_OFFSET, DDRSS_CTL_181_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_182_OFFSET, DDRSS_CTL_182_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_183_OFFSET, DDRSS_CTL_183_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_184_OFFSET, DDRSS_CTL_184_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_185_OFFSET, DDRSS_CTL_185_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_186_OFFSET, DDRSS_CTL_186_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_187_OFFSET, DDRSS_CTL_187_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_188_OFFSET, DDRSS_CTL_188_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_189_OFFSET, DDRSS_CTL_189_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_190_OFFSET, DDRSS_CTL_190_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_191_OFFSET, DDRSS_CTL_191_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_192_OFFSET, DDRSS_CTL_192_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_193_OFFSET, DDRSS_CTL_193_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_194_OFFSET, DDRSS_CTL_194_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_195_OFFSET, DDRSS_CTL_195_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_196_OFFSET, DDRSS_CTL_196_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_197_OFFSET, DDRSS_CTL_197_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_198_OFFSET, DDRSS_CTL_198_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_199_OFFSET, DDRSS_CTL_199_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_200_OFFSET, DDRSS_CTL_200_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_201_OFFSET, DDRSS_CTL_201_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_202_OFFSET, DDRSS_CTL_202_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_203_OFFSET, DDRSS_CTL_203_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_204_OFFSET, DDRSS_CTL_204_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_205_OFFSET, DDRSS_CTL_205_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_206_OFFSET, DDRSS_CTL_206_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_207_OFFSET, DDRSS_CTL_207_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_208_OFFSET, DDRSS_CTL_208_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_209_OFFSET, DDRSS_CTL_209_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_210_OFFSET, DDRSS_CTL_210_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_211_OFFSET, DDRSS_CTL_211_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_212_OFFSET, DDRSS_CTL_212_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_213_OFFSET, DDRSS_CTL_213_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_214_OFFSET, DDRSS_CTL_214_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_215_OFFSET, DDRSS_CTL_215_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_216_OFFSET, DDRSS_CTL_216_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_217_OFFSET, DDRSS_CTL_217_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_218_OFFSET, DDRSS_CTL_218_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_219_OFFSET, DDRSS_CTL_219_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_220_OFFSET, DDRSS_CTL_220_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_221_OFFSET, DDRSS_CTL_221_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_222_OFFSET, DDRSS_CTL_222_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_223_OFFSET, DDRSS_CTL_223_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_224_OFFSET, DDRSS_CTL_224_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_225_OFFSET, DDRSS_CTL_225_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_226_OFFSET, DDRSS_CTL_226_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_227_OFFSET, DDRSS_CTL_227_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_228_OFFSET, DDRSS_CTL_228_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_229_OFFSET, DDRSS_CTL_229_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_230_OFFSET, DDRSS_CTL_230_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_231_OFFSET, DDRSS_CTL_231_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_232_OFFSET, DDRSS_CTL_232_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_233_OFFSET, DDRSS_CTL_233_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_234_OFFSET, DDRSS_CTL_234_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_235_OFFSET, DDRSS_CTL_235_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_236_OFFSET, DDRSS_CTL_236_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_237_OFFSET, DDRSS_CTL_237_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_238_OFFSET, DDRSS_CTL_238_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_239_OFFSET, DDRSS_CTL_239_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_240_OFFSET, DDRSS_CTL_240_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_241_OFFSET, DDRSS_CTL_241_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_242_OFFSET, DDRSS_CTL_242_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_243_OFFSET, DDRSS_CTL_243_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_244_OFFSET, DDRSS_CTL_244_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_245_OFFSET, DDRSS_CTL_245_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_246_OFFSET, DDRSS_CTL_246_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_247_OFFSET, DDRSS_CTL_247_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_248_OFFSET, DDRSS_CTL_248_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_249_OFFSET, DDRSS_CTL_249_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_250_OFFSET, DDRSS_CTL_250_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_251_OFFSET, DDRSS_CTL_251_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_252_OFFSET, DDRSS_CTL_252_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_253_OFFSET, DDRSS_CTL_253_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_254_OFFSET, DDRSS_CTL_254_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_255_OFFSET, DDRSS_CTL_255_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_256_OFFSET, DDRSS_CTL_256_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_257_OFFSET, DDRSS_CTL_257_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_258_OFFSET, DDRSS_CTL_258_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_259_OFFSET, DDRSS_CTL_259_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_260_OFFSET, DDRSS_CTL_260_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_261_OFFSET, DDRSS_CTL_261_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_262_OFFSET, DDRSS_CTL_262_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_263_OFFSET, DDRSS_CTL_263_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_264_OFFSET, DDRSS_CTL_264_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_265_OFFSET, DDRSS_CTL_265_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_266_OFFSET, DDRSS_CTL_266_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_267_OFFSET, DDRSS_CTL_267_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_268_OFFSET, DDRSS_CTL_268_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_269_OFFSET, DDRSS_CTL_269_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_270_OFFSET, DDRSS_CTL_270_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_271_OFFSET, DDRSS_CTL_271_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_272_OFFSET, DDRSS_CTL_272_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_273_OFFSET, DDRSS_CTL_273_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_274_OFFSET, DDRSS_CTL_274_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_275_OFFSET, DDRSS_CTL_275_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_276_OFFSET, DDRSS_CTL_276_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_277_OFFSET, DDRSS_CTL_277_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_278_OFFSET, DDRSS_CTL_278_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_279_OFFSET, DDRSS_CTL_279_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_280_OFFSET, DDRSS_CTL_280_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_281_OFFSET, DDRSS_CTL_281_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_282_OFFSET, DDRSS_CTL_282_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_283_OFFSET, DDRSS_CTL_283_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_284_OFFSET, DDRSS_CTL_284_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_285_OFFSET, DDRSS_CTL_285_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_286_OFFSET, DDRSS_CTL_286_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_287_OFFSET, DDRSS_CTL_287_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_288_OFFSET, DDRSS_CTL_288_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_289_OFFSET, DDRSS_CTL_289_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_290_OFFSET, DDRSS_CTL_290_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_291_OFFSET, DDRSS_CTL_291_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_292_OFFSET, DDRSS_CTL_292_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_293_OFFSET, DDRSS_CTL_293_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_294_OFFSET, DDRSS_CTL_294_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_295_OFFSET, DDRSS_CTL_295_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_296_OFFSET, DDRSS_CTL_296_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_297_OFFSET, DDRSS_CTL_297_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_298_OFFSET, DDRSS_CTL_298_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_299_OFFSET, DDRSS_CTL_299_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_300_OFFSET, DDRSS_CTL_300_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_301_OFFSET, DDRSS_CTL_301_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_302_OFFSET, DDRSS_CTL_302_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_303_OFFSET, DDRSS_CTL_303_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_304_OFFSET, DDRSS_CTL_304_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_305_OFFSET, DDRSS_CTL_305_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_306_OFFSET, DDRSS_CTL_306_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_307_OFFSET, DDRSS_CTL_307_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_308_OFFSET, DDRSS_CTL_308_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_309_OFFSET, DDRSS_CTL_309_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_310_OFFSET, DDRSS_CTL_310_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_311_OFFSET, DDRSS_CTL_311_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_312_OFFSET, DDRSS_CTL_312_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_313_OFFSET, DDRSS_CTL_313_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_314_OFFSET, DDRSS_CTL_314_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_315_OFFSET, DDRSS_CTL_315_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_316_OFFSET, DDRSS_CTL_316_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_317_OFFSET, DDRSS_CTL_317_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_318_OFFSET, DDRSS_CTL_318_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_319_OFFSET, DDRSS_CTL_319_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_320_OFFSET, DDRSS_CTL_320_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_321_OFFSET, DDRSS_CTL_321_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_322_OFFSET, DDRSS_CTL_322_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_323_OFFSET, DDRSS_CTL_323_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_324_OFFSET, DDRSS_CTL_324_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_325_OFFSET, DDRSS_CTL_325_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_326_OFFSET, DDRSS_CTL_326_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_327_OFFSET, DDRSS_CTL_327_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_328_OFFSET, DDRSS_CTL_328_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_329_OFFSET, DDRSS_CTL_329_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_330_OFFSET, DDRSS_CTL_330_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_331_OFFSET, DDRSS_CTL_331_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_332_OFFSET, DDRSS_CTL_332_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_333_OFFSET, DDRSS_CTL_333_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_334_OFFSET, DDRSS_CTL_334_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_335_OFFSET, DDRSS_CTL_335_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_336_OFFSET, DDRSS_CTL_336_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_337_OFFSET, DDRSS_CTL_337_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_338_OFFSET, DDRSS_CTL_338_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_339_OFFSET, DDRSS_CTL_339_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_340_OFFSET, DDRSS_CTL_340_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_341_OFFSET, DDRSS_CTL_341_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_342_OFFSET, DDRSS_CTL_342_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_343_OFFSET, DDRSS_CTL_343_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_344_OFFSET, DDRSS_CTL_344_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_345_OFFSET, DDRSS_CTL_345_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_346_OFFSET, DDRSS_CTL_346_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_347_OFFSET, DDRSS_CTL_347_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_348_OFFSET, DDRSS_CTL_348_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_349_OFFSET, DDRSS_CTL_349_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_350_OFFSET, DDRSS_CTL_350_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_351_OFFSET, DDRSS_CTL_351_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_352_OFFSET, DDRSS_CTL_352_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_353_OFFSET, DDRSS_CTL_353_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_354_OFFSET, DDRSS_CTL_354_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_355_OFFSET, DDRSS_CTL_355_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_356_OFFSET, DDRSS_CTL_356_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_357_OFFSET, DDRSS_CTL_357_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_358_OFFSET, DDRSS_CTL_358_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_359_OFFSET, DDRSS_CTL_359_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_360_OFFSET, DDRSS_CTL_360_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_361_OFFSET, DDRSS_CTL_361_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_362_OFFSET, DDRSS_CTL_362_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_363_OFFSET, DDRSS_CTL_363_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_364_OFFSET, DDRSS_CTL_364_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_365_OFFSET, DDRSS_CTL_365_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_366_OFFSET, DDRSS_CTL_366_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_367_OFFSET, DDRSS_CTL_367_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_368_OFFSET, DDRSS_CTL_368_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_369_OFFSET, DDRSS_CTL_369_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_370_OFFSET, DDRSS_CTL_370_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_371_OFFSET, DDRSS_CTL_371_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_372_OFFSET, DDRSS_CTL_372_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_373_OFFSET, DDRSS_CTL_373_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_374_OFFSET, DDRSS_CTL_374_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_375_OFFSET, DDRSS_CTL_375_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_376_OFFSET, DDRSS_CTL_376_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_377_OFFSET, DDRSS_CTL_377_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_378_OFFSET, DDRSS_CTL_378_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_379_OFFSET, DDRSS_CTL_379_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_380_OFFSET, DDRSS_CTL_380_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_381_OFFSET, DDRSS_CTL_381_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_382_OFFSET, DDRSS_CTL_382_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_383_OFFSET, DDRSS_CTL_383_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_384_OFFSET, DDRSS_CTL_384_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_385_OFFSET, DDRSS_CTL_385_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_386_OFFSET, DDRSS_CTL_386_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_387_OFFSET, DDRSS_CTL_387_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_388_OFFSET, DDRSS_CTL_388_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_389_OFFSET, DDRSS_CTL_389_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_390_OFFSET, DDRSS_CTL_390_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_391_OFFSET, DDRSS_CTL_391_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_392_OFFSET, DDRSS_CTL_392_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_393_OFFSET, DDRSS_CTL_393_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_394_OFFSET, DDRSS_CTL_394_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_395_OFFSET, DDRSS_CTL_395_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_396_OFFSET, DDRSS_CTL_396_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_397_OFFSET, DDRSS_CTL_397_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_398_OFFSET, DDRSS_CTL_398_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_399_OFFSET, DDRSS_CTL_399_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_400_OFFSET, DDRSS_CTL_400_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_401_OFFSET, DDRSS_CTL_401_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_402_OFFSET, DDRSS_CTL_402_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_403_OFFSET, DDRSS_CTL_403_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_404_OFFSET, DDRSS_CTL_404_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_405_OFFSET, DDRSS_CTL_405_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_406_OFFSET, DDRSS_CTL_406_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_407_OFFSET, DDRSS_CTL_407_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_408_OFFSET, DDRSS_CTL_408_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_409_OFFSET, DDRSS_CTL_409_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_410_OFFSET, DDRSS_CTL_410_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_411_OFFSET, DDRSS_CTL_411_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_412_OFFSET, DDRSS_CTL_412_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_413_OFFSET, DDRSS_CTL_413_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_414_OFFSET, DDRSS_CTL_414_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_415_OFFSET, DDRSS_CTL_415_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_416_OFFSET, DDRSS_CTL_416_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_417_OFFSET, DDRSS_CTL_417_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_418_OFFSET, DDRSS_CTL_418_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_419_OFFSET, DDRSS_CTL_419_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_420_OFFSET, DDRSS_CTL_420_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_421_OFFSET, DDRSS_CTL_421_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_422_OFFSET, DDRSS_CTL_422_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_423_OFFSET, DDRSS_CTL_423_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_424_OFFSET, DDRSS_CTL_424_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_425_OFFSET, DDRSS_CTL_425_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_426_OFFSET, DDRSS_CTL_426_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_427_OFFSET, DDRSS_CTL_427_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_428_OFFSET, DDRSS_CTL_428_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_429_OFFSET, DDRSS_CTL_429_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_430_OFFSET, DDRSS_CTL_430_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_431_OFFSET, DDRSS_CTL_431_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_432_OFFSET, DDRSS_CTL_432_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_433_OFFSET, DDRSS_CTL_433_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_434_OFFSET, DDRSS_CTL_434_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_435_OFFSET, DDRSS_CTL_435_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_436_OFFSET, DDRSS_CTL_436_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_437_OFFSET, DDRSS_CTL_437_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_438_OFFSET, DDRSS_CTL_438_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_439_OFFSET, DDRSS_CTL_439_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_440_OFFSET, DDRSS_CTL_440_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_441_OFFSET, DDRSS_CTL_441_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_442_OFFSET, DDRSS_CTL_442_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_443_OFFSET, DDRSS_CTL_443_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_444_OFFSET, DDRSS_CTL_444_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_445_OFFSET, DDRSS_CTL_445_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_446_OFFSET, DDRSS_CTL_446_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_447_OFFSET, DDRSS_CTL_447_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_448_OFFSET, DDRSS_CTL_448_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_449_OFFSET, DDRSS_CTL_449_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_450_OFFSET, DDRSS_CTL_450_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_451_OFFSET, DDRSS_CTL_451_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_452_OFFSET, DDRSS_CTL_452_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_453_OFFSET, DDRSS_CTL_453_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_454_OFFSET, DDRSS_CTL_454_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_455_OFFSET, DDRSS_CTL_455_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_456_OFFSET, DDRSS_CTL_456_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_457_OFFSET, DDRSS_CTL_457_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_458_OFFSET, DDRSS_CTL_458_DATA );
+
+       BOARD_DEBUG_LOG("--->>> DDR controller programming completed... <<<---\n");
+
+    //Program the PI module
+    BOARD_DEBUG_LOG("--->>> DDR PI programming in progress.. <<<---\n");
+
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_0_OFFSET,   DDRSS_PI_00_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_1_OFFSET,   DDRSS_PI_01_DATA    );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_2_OFFSET,       DDRSS_PI_02_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_3_OFFSET,       DDRSS_PI_03_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_4_OFFSET,       DDRSS_PI_04_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_5_OFFSET,       DDRSS_PI_05_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_6_OFFSET,       DDRSS_PI_06_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_7_OFFSET,       DDRSS_PI_07_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_8_OFFSET,       DDRSS_PI_08_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_9_OFFSET,       DDRSS_PI_09_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_10_OFFSET,      DDRSS_PI_10_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_11_OFFSET,      DDRSS_PI_11_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_12_OFFSET,      DDRSS_PI_12_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_13_OFFSET,      DDRSS_PI_13_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_14_OFFSET,      DDRSS_PI_14_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_15_OFFSET,      DDRSS_PI_15_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_16_OFFSET,      DDRSS_PI_16_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_17_OFFSET,      DDRSS_PI_17_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_18_OFFSET,      DDRSS_PI_18_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_19_OFFSET,      DDRSS_PI_19_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_20_OFFSET,      DDRSS_PI_20_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_21_OFFSET,      DDRSS_PI_21_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_22_OFFSET,      DDRSS_PI_22_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_23_OFFSET,      DDRSS_PI_23_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_24_OFFSET,      DDRSS_PI_24_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_25_OFFSET,      DDRSS_PI_25_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_26_OFFSET,      DDRSS_PI_26_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_27_OFFSET,      DDRSS_PI_27_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_28_OFFSET,      DDRSS_PI_28_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_29_OFFSET,      DDRSS_PI_29_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_30_OFFSET,      DDRSS_PI_30_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_31_OFFSET,      DDRSS_PI_31_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_32_OFFSET,      DDRSS_PI_32_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_33_OFFSET,      DDRSS_PI_33_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_34_OFFSET,      DDRSS_PI_34_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_35_OFFSET,      DDRSS_PI_35_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_36_OFFSET,      DDRSS_PI_36_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_37_OFFSET,      DDRSS_PI_37_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_38_OFFSET,      DDRSS_PI_38_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_39_OFFSET,      DDRSS_PI_39_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_40_OFFSET,      DDRSS_PI_40_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_41_OFFSET,      DDRSS_PI_41_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_42_OFFSET,      DDRSS_PI_42_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_43_OFFSET,      DDRSS_PI_43_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_44_OFFSET,      DDRSS_PI_44_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_45_OFFSET,      DDRSS_PI_45_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_46_OFFSET,      DDRSS_PI_46_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_47_OFFSET,      DDRSS_PI_47_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_48_OFFSET,      DDRSS_PI_48_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_49_OFFSET,      DDRSS_PI_49_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_50_OFFSET,      DDRSS_PI_50_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_51_OFFSET,      DDRSS_PI_51_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_52_OFFSET,      DDRSS_PI_52_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_53_OFFSET,      DDRSS_PI_53_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_54_OFFSET,      DDRSS_PI_54_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_55_OFFSET,      DDRSS_PI_55_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_56_OFFSET,      DDRSS_PI_56_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_57_OFFSET,      DDRSS_PI_57_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_58_OFFSET,      DDRSS_PI_58_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_59_OFFSET,      DDRSS_PI_59_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_60_OFFSET,      DDRSS_PI_60_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_61_OFFSET,      DDRSS_PI_61_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_62_OFFSET,      DDRSS_PI_62_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_63_OFFSET,      DDRSS_PI_63_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_64_OFFSET,      DDRSS_PI_64_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_65_OFFSET,      DDRSS_PI_65_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_66_OFFSET,      DDRSS_PI_66_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_67_OFFSET,      DDRSS_PI_67_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_68_OFFSET,      DDRSS_PI_68_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_69_OFFSET,      DDRSS_PI_69_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_70_OFFSET,      DDRSS_PI_70_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_71_OFFSET,      DDRSS_PI_71_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_72_OFFSET,      DDRSS_PI_72_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_73_OFFSET,      DDRSS_PI_73_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_74_OFFSET,      DDRSS_PI_74_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_75_OFFSET,      DDRSS_PI_75_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_76_OFFSET,      DDRSS_PI_76_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_77_OFFSET,      DDRSS_PI_77_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_78_OFFSET,      DDRSS_PI_78_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_79_OFFSET,      DDRSS_PI_79_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_80_OFFSET,      DDRSS_PI_80_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_81_OFFSET,      DDRSS_PI_81_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_82_OFFSET,      DDRSS_PI_82_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_83_OFFSET,      DDRSS_PI_83_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_84_OFFSET,      DDRSS_PI_84_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_85_OFFSET,      DDRSS_PI_85_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_86_OFFSET,      DDRSS_PI_86_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_87_OFFSET,      DDRSS_PI_87_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_88_OFFSET,      DDRSS_PI_88_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_89_OFFSET,      DDRSS_PI_89_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_90_OFFSET,      DDRSS_PI_90_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_91_OFFSET,      DDRSS_PI_91_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_92_OFFSET,      DDRSS_PI_92_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_93_OFFSET,      DDRSS_PI_93_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_94_OFFSET,      DDRSS_PI_94_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_95_OFFSET,      DDRSS_PI_95_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_96_OFFSET,      DDRSS_PI_96_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_97_OFFSET,      DDRSS_PI_97_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_98_OFFSET,      DDRSS_PI_98_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_99_OFFSET,      DDRSS_PI_99_DATA   );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_100_OFFSET,     DDRSS_PI_100_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_101_OFFSET,     DDRSS_PI_101_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_102_OFFSET,     DDRSS_PI_102_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_103_OFFSET,     DDRSS_PI_103_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_104_OFFSET,     DDRSS_PI_104_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_105_OFFSET,     DDRSS_PI_105_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_106_OFFSET,     DDRSS_PI_106_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_107_OFFSET,     DDRSS_PI_107_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_108_OFFSET,     DDRSS_PI_108_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_109_OFFSET,     DDRSS_PI_109_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_110_OFFSET,     DDRSS_PI_110_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_111_OFFSET,     DDRSS_PI_111_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_112_OFFSET,     DDRSS_PI_112_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_113_OFFSET,     DDRSS_PI_113_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_114_OFFSET,     DDRSS_PI_114_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_115_OFFSET,     DDRSS_PI_115_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_116_OFFSET,     DDRSS_PI_116_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_117_OFFSET,     DDRSS_PI_117_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_118_OFFSET,     DDRSS_PI_118_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_119_OFFSET,     DDRSS_PI_119_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_120_OFFSET,     DDRSS_PI_120_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_121_OFFSET,     DDRSS_PI_121_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_122_OFFSET,     DDRSS_PI_122_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_123_OFFSET,     DDRSS_PI_123_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_124_OFFSET,     DDRSS_PI_124_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_125_OFFSET,     DDRSS_PI_125_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_126_OFFSET,     DDRSS_PI_126_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_127_OFFSET,     DDRSS_PI_127_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_128_OFFSET,     DDRSS_PI_128_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_129_OFFSET,     DDRSS_PI_129_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_130_OFFSET,     DDRSS_PI_130_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_131_OFFSET,     DDRSS_PI_131_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_132_OFFSET,     DDRSS_PI_132_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_133_OFFSET,     DDRSS_PI_133_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_134_OFFSET,     DDRSS_PI_134_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_135_OFFSET,     DDRSS_PI_135_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_136_OFFSET,     DDRSS_PI_136_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_137_OFFSET,     DDRSS_PI_137_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_138_OFFSET,     DDRSS_PI_138_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_139_OFFSET,     DDRSS_PI_139_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_140_OFFSET,     DDRSS_PI_140_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_141_OFFSET,     DDRSS_PI_141_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_142_OFFSET,     DDRSS_PI_142_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_143_OFFSET,     DDRSS_PI_143_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_144_OFFSET,     DDRSS_PI_144_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_145_OFFSET,     DDRSS_PI_145_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_146_OFFSET,     DDRSS_PI_146_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_147_OFFSET,     DDRSS_PI_147_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_148_OFFSET,     DDRSS_PI_148_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_149_OFFSET,     DDRSS_PI_149_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_150_OFFSET,     DDRSS_PI_150_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_151_OFFSET,     DDRSS_PI_151_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_152_OFFSET,     DDRSS_PI_152_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_153_OFFSET,     DDRSS_PI_153_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_154_OFFSET,     DDRSS_PI_154_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_155_OFFSET,     DDRSS_PI_155_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_156_OFFSET,     DDRSS_PI_156_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_157_OFFSET,     DDRSS_PI_157_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_158_OFFSET,     DDRSS_PI_158_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_159_OFFSET,     DDRSS_PI_159_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_160_OFFSET,     DDRSS_PI_160_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_161_OFFSET,     DDRSS_PI_161_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_162_OFFSET,     DDRSS_PI_162_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_163_OFFSET,     DDRSS_PI_163_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_164_OFFSET,     DDRSS_PI_164_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_165_OFFSET,     DDRSS_PI_165_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_166_OFFSET,     DDRSS_PI_166_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_167_OFFSET,     DDRSS_PI_167_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_168_OFFSET,     DDRSS_PI_168_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_169_OFFSET,     DDRSS_PI_169_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_170_OFFSET,     DDRSS_PI_170_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_171_OFFSET,     DDRSS_PI_171_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_172_OFFSET,     DDRSS_PI_172_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_173_OFFSET,     DDRSS_PI_173_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_174_OFFSET,     DDRSS_PI_174_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_175_OFFSET,     DDRSS_PI_175_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_176_OFFSET,     DDRSS_PI_176_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_177_OFFSET,     DDRSS_PI_177_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_178_OFFSET,     DDRSS_PI_178_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_179_OFFSET,     DDRSS_PI_179_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_180_OFFSET,     DDRSS_PI_180_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_181_OFFSET,     DDRSS_PI_181_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_182_OFFSET,     DDRSS_PI_182_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_183_OFFSET,     DDRSS_PI_183_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_184_OFFSET,     DDRSS_PI_184_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_185_OFFSET,     DDRSS_PI_185_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_186_OFFSET,     DDRSS_PI_186_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_187_OFFSET,     DDRSS_PI_187_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_188_OFFSET,     DDRSS_PI_188_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_189_OFFSET,     DDRSS_PI_189_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_190_OFFSET,     DDRSS_PI_190_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_191_OFFSET,     DDRSS_PI_191_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_192_OFFSET,     DDRSS_PI_192_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_193_OFFSET,     DDRSS_PI_193_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_194_OFFSET,     DDRSS_PI_194_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_195_OFFSET,     DDRSS_PI_195_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_196_OFFSET,     DDRSS_PI_196_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_197_OFFSET,     DDRSS_PI_197_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_198_OFFSET,     DDRSS_PI_198_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_199_OFFSET,     DDRSS_PI_199_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_200_OFFSET,     DDRSS_PI_200_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_201_OFFSET,     DDRSS_PI_201_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_202_OFFSET,     DDRSS_PI_202_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_203_OFFSET,     DDRSS_PI_203_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_204_OFFSET,     DDRSS_PI_204_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_205_OFFSET,     DDRSS_PI_205_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_206_OFFSET,     DDRSS_PI_206_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_207_OFFSET,     DDRSS_PI_207_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_208_OFFSET,     DDRSS_PI_208_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_209_OFFSET,     DDRSS_PI_209_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_210_OFFSET,     DDRSS_PI_210_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_211_OFFSET,     DDRSS_PI_211_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_212_OFFSET,     DDRSS_PI_212_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_213_OFFSET,     DDRSS_PI_213_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_214_OFFSET,     DDRSS_PI_214_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_215_OFFSET,     DDRSS_PI_215_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_216_OFFSET,     DDRSS_PI_216_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_217_OFFSET,     DDRSS_PI_217_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_218_OFFSET,     DDRSS_PI_218_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_219_OFFSET,     DDRSS_PI_219_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_220_OFFSET,     DDRSS_PI_220_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_221_OFFSET,     DDRSS_PI_221_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_222_OFFSET,     DDRSS_PI_222_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_223_OFFSET,     DDRSS_PI_223_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_224_OFFSET,     DDRSS_PI_224_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_225_OFFSET,     DDRSS_PI_225_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_226_OFFSET,     DDRSS_PI_226_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_227_OFFSET,     DDRSS_PI_227_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_228_OFFSET,     DDRSS_PI_228_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_229_OFFSET,     DDRSS_PI_229_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_230_OFFSET,     DDRSS_PI_230_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_231_OFFSET,     DDRSS_PI_231_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_232_OFFSET,     DDRSS_PI_232_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_233_OFFSET,     DDRSS_PI_233_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_234_OFFSET,     DDRSS_PI_234_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_235_OFFSET,     DDRSS_PI_235_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_236_OFFSET,     DDRSS_PI_236_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_237_OFFSET,     DDRSS_PI_237_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_238_OFFSET,     DDRSS_PI_238_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_239_OFFSET,     DDRSS_PI_239_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_240_OFFSET,     DDRSS_PI_240_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_241_OFFSET,     DDRSS_PI_241_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_242_OFFSET,     DDRSS_PI_242_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_243_OFFSET,     DDRSS_PI_243_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_244_OFFSET,     DDRSS_PI_244_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_245_OFFSET,     DDRSS_PI_245_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_246_OFFSET,     DDRSS_PI_246_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_247_OFFSET,     DDRSS_PI_247_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_248_OFFSET,     DDRSS_PI_248_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_249_OFFSET,     DDRSS_PI_249_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_250_OFFSET,     DDRSS_PI_250_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_251_OFFSET,     DDRSS_PI_251_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_252_OFFSET,     DDRSS_PI_252_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_253_OFFSET,     DDRSS_PI_253_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_254_OFFSET,     DDRSS_PI_254_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_255_OFFSET,     DDRSS_PI_255_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_256_OFFSET,     DDRSS_PI_256_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_257_OFFSET,     DDRSS_PI_257_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_258_OFFSET,     DDRSS_PI_258_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_259_OFFSET,     DDRSS_PI_259_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_260_OFFSET,     DDRSS_PI_260_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_261_OFFSET,     DDRSS_PI_261_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_262_OFFSET,     DDRSS_PI_262_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_263_OFFSET,     DDRSS_PI_263_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_264_OFFSET,     DDRSS_PI_264_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_265_OFFSET,     DDRSS_PI_265_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_266_OFFSET,     DDRSS_PI_266_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_267_OFFSET,     DDRSS_PI_267_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_268_OFFSET,     DDRSS_PI_268_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_269_OFFSET,     DDRSS_PI_269_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_270_OFFSET,     DDRSS_PI_270_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_271_OFFSET,     DDRSS_PI_271_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_272_OFFSET,     DDRSS_PI_272_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_273_OFFSET,     DDRSS_PI_273_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_274_OFFSET,     DDRSS_PI_274_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_275_OFFSET,     DDRSS_PI_275_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_276_OFFSET,     DDRSS_PI_276_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_277_OFFSET,     DDRSS_PI_277_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_278_OFFSET,     DDRSS_PI_278_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_279_OFFSET,     DDRSS_PI_279_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_280_OFFSET,     DDRSS_PI_280_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_281_OFFSET,     DDRSS_PI_281_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_282_OFFSET,     DDRSS_PI_282_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_283_OFFSET,     DDRSS_PI_283_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_284_OFFSET,     DDRSS_PI_284_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_285_OFFSET,     DDRSS_PI_285_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_286_OFFSET,     DDRSS_PI_286_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_287_OFFSET,     DDRSS_PI_287_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_288_OFFSET,     DDRSS_PI_288_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_289_OFFSET,     DDRSS_PI_289_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_290_OFFSET,     DDRSS_PI_290_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_291_OFFSET,     DDRSS_PI_291_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_292_OFFSET,     DDRSS_PI_292_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_293_OFFSET,     DDRSS_PI_293_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_294_OFFSET,     DDRSS_PI_294_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_295_OFFSET,     DDRSS_PI_295_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_296_OFFSET,     DDRSS_PI_296_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_297_OFFSET,     DDRSS_PI_297_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_298_OFFSET,     DDRSS_PI_298_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_299_OFFSET,     DDRSS_PI_299_DATA  );
+
+    BOARD_DEBUG_LOG("--->>> DDR PI programming completed... <<<---\n");
+
+    //Program the data slice 0
+       BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 0 programming in progress.. <<<---\n");
+
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_0_OFFSET,    DDRSS_PHY_00_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1_OFFSET,    DDRSS_PHY_01_DATA       );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_2_OFFSET,    DDRSS_PHY_02_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_3_OFFSET,    DDRSS_PHY_03_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_4_OFFSET,    DDRSS_PHY_04_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_5_OFFSET,    DDRSS_PHY_05_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_6_OFFSET,    DDRSS_PHY_06_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_7_OFFSET,    DDRSS_PHY_07_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_8_OFFSET,    DDRSS_PHY_08_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_9_OFFSET,    DDRSS_PHY_09_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_10_OFFSET,   DDRSS_PHY_10_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_11_OFFSET,   DDRSS_PHY_11_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_12_OFFSET,   DDRSS_PHY_12_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_13_OFFSET,   DDRSS_PHY_13_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_14_OFFSET,   DDRSS_PHY_14_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_15_OFFSET,   DDRSS_PHY_15_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_16_OFFSET,   DDRSS_PHY_16_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_17_OFFSET,   DDRSS_PHY_17_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_18_OFFSET,   DDRSS_PHY_18_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_19_OFFSET,   DDRSS_PHY_19_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_20_OFFSET,   DDRSS_PHY_20_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_21_OFFSET,   DDRSS_PHY_21_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_22_OFFSET,   DDRSS_PHY_22_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_23_OFFSET,   DDRSS_PHY_23_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_24_OFFSET,   DDRSS_PHY_24_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_25_OFFSET,   DDRSS_PHY_25_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_26_OFFSET,   DDRSS_PHY_26_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_27_OFFSET,   DDRSS_PHY_27_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_28_OFFSET,   DDRSS_PHY_28_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_29_OFFSET,   DDRSS_PHY_29_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_30_OFFSET,   DDRSS_PHY_30_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_31_OFFSET,   DDRSS_PHY_31_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_32_OFFSET,   DDRSS_PHY_32_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_33_OFFSET,   DDRSS_PHY_33_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_34_OFFSET,   DDRSS_PHY_34_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_35_OFFSET,   DDRSS_PHY_35_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_36_OFFSET,   DDRSS_PHY_36_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_37_OFFSET,   DDRSS_PHY_37_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_38_OFFSET,   DDRSS_PHY_38_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_39_OFFSET,   DDRSS_PHY_39_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_40_OFFSET,   DDRSS_PHY_40_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_41_OFFSET,   DDRSS_PHY_41_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_42_OFFSET,   DDRSS_PHY_42_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_43_OFFSET,   DDRSS_PHY_43_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_44_OFFSET,   DDRSS_PHY_44_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_45_OFFSET,   DDRSS_PHY_45_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_46_OFFSET,   DDRSS_PHY_46_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_47_OFFSET,   DDRSS_PHY_47_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_48_OFFSET,   DDRSS_PHY_48_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_49_OFFSET,   DDRSS_PHY_49_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_50_OFFSET,   DDRSS_PHY_50_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_51_OFFSET,   DDRSS_PHY_51_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_52_OFFSET,   DDRSS_PHY_52_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_53_OFFSET,   DDRSS_PHY_53_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_54_OFFSET,   DDRSS_PHY_54_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_55_OFFSET,   DDRSS_PHY_55_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_56_OFFSET,   DDRSS_PHY_56_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_57_OFFSET,   DDRSS_PHY_57_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_58_OFFSET,   DDRSS_PHY_58_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_59_OFFSET,   DDRSS_PHY_59_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_60_OFFSET,   DDRSS_PHY_60_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_61_OFFSET,   DDRSS_PHY_61_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_62_OFFSET,   DDRSS_PHY_62_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_63_OFFSET,   DDRSS_PHY_63_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_64_OFFSET,   DDRSS_PHY_64_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_65_OFFSET,   DDRSS_PHY_65_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_66_OFFSET,   DDRSS_PHY_66_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_67_OFFSET,   DDRSS_PHY_67_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_68_OFFSET,   DDRSS_PHY_68_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_69_OFFSET,   DDRSS_PHY_69_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_70_OFFSET,   DDRSS_PHY_70_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_71_OFFSET,   DDRSS_PHY_71_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_72_OFFSET,   DDRSS_PHY_72_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_73_OFFSET,   DDRSS_PHY_73_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_74_OFFSET,   DDRSS_PHY_74_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_75_OFFSET,   DDRSS_PHY_75_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_76_OFFSET,   DDRSS_PHY_76_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_77_OFFSET,   DDRSS_PHY_77_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_78_OFFSET,   DDRSS_PHY_78_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_79_OFFSET,   DDRSS_PHY_79_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_80_OFFSET,   DDRSS_PHY_80_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_81_OFFSET,   DDRSS_PHY_81_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_82_OFFSET,   DDRSS_PHY_82_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_83_OFFSET,   DDRSS_PHY_83_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_84_OFFSET,   DDRSS_PHY_84_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_85_OFFSET,   DDRSS_PHY_85_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_86_OFFSET,   DDRSS_PHY_86_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_87_OFFSET,   DDRSS_PHY_87_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_88_OFFSET,   DDRSS_PHY_88_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_89_OFFSET,   DDRSS_PHY_89_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_90_OFFSET,   DDRSS_PHY_90_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_91_OFFSET,   DDRSS_PHY_91_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_92_OFFSET,   DDRSS_PHY_92_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_93_OFFSET,   DDRSS_PHY_93_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_94_OFFSET,   DDRSS_PHY_94_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_95_OFFSET,   DDRSS_PHY_95_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_96_OFFSET,   DDRSS_PHY_96_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_97_OFFSET,   DDRSS_PHY_97_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_98_OFFSET,   DDRSS_PHY_98_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_99_OFFSET,   DDRSS_PHY_99_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_100_OFFSET,  DDRSS_PHY_100_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_101_OFFSET,  DDRSS_PHY_101_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_102_OFFSET,  DDRSS_PHY_102_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_103_OFFSET,  DDRSS_PHY_103_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_104_OFFSET,  DDRSS_PHY_104_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_105_OFFSET,  DDRSS_PHY_105_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_106_OFFSET,  DDRSS_PHY_106_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_107_OFFSET,  DDRSS_PHY_107_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_108_OFFSET,  DDRSS_PHY_108_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_109_OFFSET,  DDRSS_PHY_109_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_110_OFFSET,  DDRSS_PHY_110_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_111_OFFSET,  DDRSS_PHY_111_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_112_OFFSET,  DDRSS_PHY_112_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_113_OFFSET,  DDRSS_PHY_113_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_114_OFFSET,  DDRSS_PHY_114_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_115_OFFSET,  DDRSS_PHY_115_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_116_OFFSET,  DDRSS_PHY_116_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_117_OFFSET,  DDRSS_PHY_117_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_118_OFFSET,  DDRSS_PHY_118_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_119_OFFSET,  DDRSS_PHY_119_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_120_OFFSET,  DDRSS_PHY_120_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_121_OFFSET,  DDRSS_PHY_121_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_122_OFFSET,  DDRSS_PHY_122_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_123_OFFSET,  DDRSS_PHY_123_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_124_OFFSET,  DDRSS_PHY_124_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_125_OFFSET,  DDRSS_PHY_125_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_126_OFFSET,  DDRSS_PHY_126_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_127_OFFSET,  DDRSS_PHY_127_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_128_OFFSET,  DDRSS_PHY_128_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_129_OFFSET,  DDRSS_PHY_129_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_130_OFFSET,  DDRSS_PHY_130_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_131_OFFSET,  DDRSS_PHY_131_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_132_OFFSET,  DDRSS_PHY_132_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_133_OFFSET,  DDRSS_PHY_133_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_134_OFFSET,  DDRSS_PHY_134_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_135_OFFSET,  DDRSS_PHY_135_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_136_OFFSET,  DDRSS_PHY_136_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_137_OFFSET,  DDRSS_PHY_137_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_138_OFFSET,  DDRSS_PHY_138_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_139_OFFSET,  DDRSS_PHY_139_DATA );
+    BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 0 programming completed... <<<---\n");
+
+       BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 1 programming in progress.. <<<---\n");
+
+     //Program the data slice 1
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_256_OFFSET,  DDRSS_PHY_256_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_257_OFFSET,  DDRSS_PHY_257_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_258_OFFSET,  DDRSS_PHY_258_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_259_OFFSET,  DDRSS_PHY_259_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_260_OFFSET,  DDRSS_PHY_260_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_261_OFFSET,  DDRSS_PHY_261_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_262_OFFSET,  DDRSS_PHY_262_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_263_OFFSET,  DDRSS_PHY_263_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_264_OFFSET,  DDRSS_PHY_264_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_265_OFFSET,  DDRSS_PHY_265_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_266_OFFSET,  DDRSS_PHY_266_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_267_OFFSET,  DDRSS_PHY_267_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_268_OFFSET,  DDRSS_PHY_268_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_269_OFFSET,  DDRSS_PHY_269_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_270_OFFSET,  DDRSS_PHY_270_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_271_OFFSET,  DDRSS_PHY_271_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_272_OFFSET,  DDRSS_PHY_272_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_273_OFFSET,  DDRSS_PHY_273_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_274_OFFSET,  DDRSS_PHY_274_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_275_OFFSET,  DDRSS_PHY_275_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_276_OFFSET,  DDRSS_PHY_276_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_277_OFFSET,  DDRSS_PHY_277_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_278_OFFSET,  DDRSS_PHY_278_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_279_OFFSET,  DDRSS_PHY_279_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_280_OFFSET,  DDRSS_PHY_280_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_281_OFFSET,  DDRSS_PHY_281_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_282_OFFSET,  DDRSS_PHY_282_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_283_OFFSET,  DDRSS_PHY_283_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_284_OFFSET,  DDRSS_PHY_284_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_285_OFFSET,  DDRSS_PHY_285_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_286_OFFSET,  DDRSS_PHY_286_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_287_OFFSET,  DDRSS_PHY_287_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_288_OFFSET,  DDRSS_PHY_288_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_289_OFFSET,  DDRSS_PHY_289_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_290_OFFSET,  DDRSS_PHY_290_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_291_OFFSET,  DDRSS_PHY_291_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_292_OFFSET,  DDRSS_PHY_292_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_293_OFFSET,  DDRSS_PHY_293_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_294_OFFSET,  DDRSS_PHY_294_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_295_OFFSET,  DDRSS_PHY_295_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_296_OFFSET,  DDRSS_PHY_296_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_297_OFFSET,  DDRSS_PHY_297_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_298_OFFSET,  DDRSS_PHY_298_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_299_OFFSET,  DDRSS_PHY_299_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_300_OFFSET,  DDRSS_PHY_300_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_301_OFFSET,  DDRSS_PHY_301_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_302_OFFSET,  DDRSS_PHY_302_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_303_OFFSET,  DDRSS_PHY_303_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_304_OFFSET,  DDRSS_PHY_304_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_305_OFFSET,  DDRSS_PHY_305_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_306_OFFSET,  DDRSS_PHY_306_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_307_OFFSET,  DDRSS_PHY_307_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_308_OFFSET,  DDRSS_PHY_308_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_309_OFFSET,  DDRSS_PHY_309_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_310_OFFSET,  DDRSS_PHY_310_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_311_OFFSET,  DDRSS_PHY_311_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_312_OFFSET,  DDRSS_PHY_312_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_313_OFFSET,  DDRSS_PHY_313_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_314_OFFSET,  DDRSS_PHY_314_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_315_OFFSET,  DDRSS_PHY_315_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_316_OFFSET,  DDRSS_PHY_316_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_317_OFFSET,  DDRSS_PHY_317_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_318_OFFSET,  DDRSS_PHY_318_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_319_OFFSET,  DDRSS_PHY_319_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_320_OFFSET,  DDRSS_PHY_320_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_321_OFFSET,  DDRSS_PHY_321_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_322_OFFSET,  DDRSS_PHY_322_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_323_OFFSET,  DDRSS_PHY_323_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_324_OFFSET,  DDRSS_PHY_324_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_325_OFFSET,  DDRSS_PHY_325_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_326_OFFSET,  DDRSS_PHY_326_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_327_OFFSET,  DDRSS_PHY_327_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_328_OFFSET,  DDRSS_PHY_328_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_329_OFFSET,  DDRSS_PHY_329_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_330_OFFSET,  DDRSS_PHY_330_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_331_OFFSET,  DDRSS_PHY_331_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_332_OFFSET,  DDRSS_PHY_332_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_333_OFFSET,  DDRSS_PHY_333_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_334_OFFSET,  DDRSS_PHY_334_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_335_OFFSET,  DDRSS_PHY_335_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_336_OFFSET,  DDRSS_PHY_336_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_337_OFFSET,  DDRSS_PHY_337_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_338_OFFSET,  DDRSS_PHY_338_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_339_OFFSET,  DDRSS_PHY_339_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_340_OFFSET,  DDRSS_PHY_340_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_341_OFFSET,  DDRSS_PHY_341_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_342_OFFSET,  DDRSS_PHY_342_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_343_OFFSET,  DDRSS_PHY_343_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_344_OFFSET,  DDRSS_PHY_344_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_345_OFFSET,  DDRSS_PHY_345_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_346_OFFSET,  DDRSS_PHY_346_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_347_OFFSET,  DDRSS_PHY_347_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_348_OFFSET,  DDRSS_PHY_348_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_349_OFFSET,  DDRSS_PHY_349_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_350_OFFSET,  DDRSS_PHY_350_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_351_OFFSET,  DDRSS_PHY_351_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_352_OFFSET,  DDRSS_PHY_352_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_353_OFFSET,  DDRSS_PHY_353_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_354_OFFSET,  DDRSS_PHY_354_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_355_OFFSET,  DDRSS_PHY_355_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_356_OFFSET,  DDRSS_PHY_356_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_357_OFFSET,  DDRSS_PHY_357_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_358_OFFSET,  DDRSS_PHY_358_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_359_OFFSET,  DDRSS_PHY_359_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_360_OFFSET,  DDRSS_PHY_360_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_361_OFFSET,  DDRSS_PHY_361_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_362_OFFSET,  DDRSS_PHY_362_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_363_OFFSET,  DDRSS_PHY_363_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_364_OFFSET,  DDRSS_PHY_364_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_365_OFFSET,  DDRSS_PHY_365_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_366_OFFSET,  DDRSS_PHY_366_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_367_OFFSET,  DDRSS_PHY_367_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_368_OFFSET,  DDRSS_PHY_368_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_369_OFFSET,  DDRSS_PHY_369_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_370_OFFSET,  DDRSS_PHY_370_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_371_OFFSET,  DDRSS_PHY_371_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_372_OFFSET,  DDRSS_PHY_372_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_373_OFFSET,  DDRSS_PHY_373_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_374_OFFSET,  DDRSS_PHY_374_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_375_OFFSET,  DDRSS_PHY_375_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_376_OFFSET,  DDRSS_PHY_376_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_377_OFFSET,  DDRSS_PHY_377_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_378_OFFSET,  DDRSS_PHY_378_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_379_OFFSET,  DDRSS_PHY_379_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_380_OFFSET,  DDRSS_PHY_380_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_381_OFFSET,  DDRSS_PHY_381_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_382_OFFSET,  DDRSS_PHY_382_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_383_OFFSET,  DDRSS_PHY_383_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_384_OFFSET,  DDRSS_PHY_384_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_385_OFFSET,  DDRSS_PHY_385_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_386_OFFSET,  DDRSS_PHY_386_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_387_OFFSET,  DDRSS_PHY_387_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_388_OFFSET,  DDRSS_PHY_388_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_389_OFFSET,  DDRSS_PHY_389_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_390_OFFSET,  DDRSS_PHY_390_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_391_OFFSET,  DDRSS_PHY_391_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_392_OFFSET,  DDRSS_PHY_392_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_393_OFFSET,  DDRSS_PHY_393_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_394_OFFSET,  DDRSS_PHY_394_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_395_OFFSET,  DDRSS_PHY_395_DATA );
+
+    BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 1 programming completed... <<<---\n");
+       BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 2 programming in progress.. <<<---\n");
+
+     //Program the data slice 2);
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_512_OFFSET,  DDRSS_PHY_512_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_513_OFFSET,  DDRSS_PHY_513_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_514_OFFSET,  DDRSS_PHY_514_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_515_OFFSET,  DDRSS_PHY_515_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_516_OFFSET,  DDRSS_PHY_516_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_517_OFFSET,  DDRSS_PHY_517_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_518_OFFSET,  DDRSS_PHY_518_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_519_OFFSET,  DDRSS_PHY_519_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_520_OFFSET,  DDRSS_PHY_520_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_521_OFFSET,  DDRSS_PHY_521_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_522_OFFSET,  DDRSS_PHY_522_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_523_OFFSET,  DDRSS_PHY_523_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_524_OFFSET,  DDRSS_PHY_524_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_525_OFFSET,  DDRSS_PHY_525_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_526_OFFSET,  DDRSS_PHY_526_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_527_OFFSET,  DDRSS_PHY_527_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_528_OFFSET,  DDRSS_PHY_528_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_529_OFFSET,  DDRSS_PHY_529_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_530_OFFSET,  DDRSS_PHY_530_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_531_OFFSET,  DDRSS_PHY_531_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_532_OFFSET,  DDRSS_PHY_532_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_533_OFFSET,  DDRSS_PHY_533_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_534_OFFSET,  DDRSS_PHY_534_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_535_OFFSET,  DDRSS_PHY_535_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_536_OFFSET,  DDRSS_PHY_536_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_537_OFFSET,  DDRSS_PHY_537_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_538_OFFSET,  DDRSS_PHY_538_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_539_OFFSET,  DDRSS_PHY_539_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_540_OFFSET,  DDRSS_PHY_540_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_541_OFFSET,  DDRSS_PHY_541_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_542_OFFSET,  DDRSS_PHY_542_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_543_OFFSET,  DDRSS_PHY_543_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_544_OFFSET,  DDRSS_PHY_544_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_545_OFFSET,  DDRSS_PHY_545_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_546_OFFSET,  DDRSS_PHY_546_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_547_OFFSET,  DDRSS_PHY_547_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_548_OFFSET,  DDRSS_PHY_548_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_549_OFFSET,  DDRSS_PHY_549_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_550_OFFSET,  DDRSS_PHY_550_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_551_OFFSET,  DDRSS_PHY_551_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_552_OFFSET,  DDRSS_PHY_552_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_553_OFFSET,  DDRSS_PHY_553_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_554_OFFSET,  DDRSS_PHY_554_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_555_OFFSET,  DDRSS_PHY_555_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_556_OFFSET,  DDRSS_PHY_556_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_557_OFFSET,  DDRSS_PHY_557_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_558_OFFSET,  DDRSS_PHY_558_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_559_OFFSET,  DDRSS_PHY_559_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_560_OFFSET,  DDRSS_PHY_560_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_561_OFFSET,  DDRSS_PHY_561_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_562_OFFSET,  DDRSS_PHY_562_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_563_OFFSET,  DDRSS_PHY_563_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_564_OFFSET,  DDRSS_PHY_564_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_565_OFFSET,  DDRSS_PHY_565_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_566_OFFSET,  DDRSS_PHY_566_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_567_OFFSET,  DDRSS_PHY_567_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_568_OFFSET,  DDRSS_PHY_568_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_569_OFFSET,  DDRSS_PHY_569_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_570_OFFSET,  DDRSS_PHY_570_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_571_OFFSET,  DDRSS_PHY_571_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_572_OFFSET,  DDRSS_PHY_572_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_573_OFFSET,  DDRSS_PHY_573_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_574_OFFSET,  DDRSS_PHY_574_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_575_OFFSET,  DDRSS_PHY_575_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_576_OFFSET,  DDRSS_PHY_576_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_577_OFFSET,  DDRSS_PHY_577_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_578_OFFSET,  DDRSS_PHY_578_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_579_OFFSET,  DDRSS_PHY_579_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_580_OFFSET,  DDRSS_PHY_580_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_581_OFFSET,  DDRSS_PHY_581_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_582_OFFSET,  DDRSS_PHY_582_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_583_OFFSET,  DDRSS_PHY_583_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_584_OFFSET,  DDRSS_PHY_584_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_585_OFFSET,  DDRSS_PHY_585_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_586_OFFSET,  DDRSS_PHY_586_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_587_OFFSET,  DDRSS_PHY_587_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_588_OFFSET,  DDRSS_PHY_588_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_589_OFFSET,  DDRSS_PHY_589_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_590_OFFSET,  DDRSS_PHY_590_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_591_OFFSET,  DDRSS_PHY_591_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_592_OFFSET,  DDRSS_PHY_592_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_593_OFFSET,  DDRSS_PHY_593_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_594_OFFSET,  DDRSS_PHY_594_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_595_OFFSET,  DDRSS_PHY_595_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_596_OFFSET,  DDRSS_PHY_596_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_597_OFFSET,  DDRSS_PHY_597_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_598_OFFSET,  DDRSS_PHY_598_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_599_OFFSET,  DDRSS_PHY_599_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_600_OFFSET,  DDRSS_PHY_600_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_601_OFFSET,  DDRSS_PHY_601_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_602_OFFSET,  DDRSS_PHY_602_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_603_OFFSET,  DDRSS_PHY_603_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_604_OFFSET,  DDRSS_PHY_604_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_605_OFFSET,  DDRSS_PHY_605_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_606_OFFSET,  DDRSS_PHY_606_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_607_OFFSET,  DDRSS_PHY_607_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_608_OFFSET,  DDRSS_PHY_608_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_609_OFFSET,  DDRSS_PHY_609_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_610_OFFSET,  DDRSS_PHY_610_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_611_OFFSET,  DDRSS_PHY_611_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_612_OFFSET,  DDRSS_PHY_612_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_613_OFFSET,  DDRSS_PHY_613_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_614_OFFSET,  DDRSS_PHY_614_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_615_OFFSET,  DDRSS_PHY_615_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_616_OFFSET,  DDRSS_PHY_616_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_617_OFFSET,  DDRSS_PHY_617_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_618_OFFSET,  DDRSS_PHY_618_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_619_OFFSET,  DDRSS_PHY_619_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_620_OFFSET,  DDRSS_PHY_620_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_621_OFFSET,  DDRSS_PHY_621_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_622_OFFSET,  DDRSS_PHY_622_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_623_OFFSET,  DDRSS_PHY_623_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_624_OFFSET,  DDRSS_PHY_624_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_625_OFFSET,  DDRSS_PHY_625_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_626_OFFSET,  DDRSS_PHY_626_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_627_OFFSET,  DDRSS_PHY_627_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_628_OFFSET,  DDRSS_PHY_628_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_629_OFFSET,  DDRSS_PHY_629_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_630_OFFSET,  DDRSS_PHY_630_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_631_OFFSET,  DDRSS_PHY_631_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_632_OFFSET,  DDRSS_PHY_632_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_633_OFFSET,  DDRSS_PHY_633_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_634_OFFSET,  DDRSS_PHY_634_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_635_OFFSET,  DDRSS_PHY_635_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_636_OFFSET,  DDRSS_PHY_636_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_637_OFFSET,  DDRSS_PHY_637_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_638_OFFSET,  DDRSS_PHY_638_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_639_OFFSET,  DDRSS_PHY_639_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_640_OFFSET,  DDRSS_PHY_640_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_641_OFFSET,  DDRSS_PHY_641_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_642_OFFSET,  DDRSS_PHY_642_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_643_OFFSET,  DDRSS_PHY_643_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_644_OFFSET,  DDRSS_PHY_644_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_645_OFFSET,  DDRSS_PHY_645_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_646_OFFSET,  DDRSS_PHY_646_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_647_OFFSET,  DDRSS_PHY_647_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_648_OFFSET,  DDRSS_PHY_648_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_649_OFFSET,  DDRSS_PHY_649_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_650_OFFSET,  DDRSS_PHY_650_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_651_OFFSET,  DDRSS_PHY_651_DATA );
+
+    BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 2 programming completed... <<<---\n");
+       BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 3 programming in progress.. <<<---\n");
+
+    //Program the data slice 3
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_768_OFFSET,  DDRSS_PHY_768_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_769_OFFSET,  DDRSS_PHY_769_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_770_OFFSET,  DDRSS_PHY_770_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_771_OFFSET,  DDRSS_PHY_771_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_772_OFFSET,  DDRSS_PHY_772_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_773_OFFSET,  DDRSS_PHY_773_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_774_OFFSET,  DDRSS_PHY_774_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_775_OFFSET,  DDRSS_PHY_775_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_776_OFFSET,  DDRSS_PHY_776_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_777_OFFSET,  DDRSS_PHY_777_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_778_OFFSET,  DDRSS_PHY_778_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_779_OFFSET,  DDRSS_PHY_779_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_780_OFFSET,  DDRSS_PHY_780_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_781_OFFSET,  DDRSS_PHY_781_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_782_OFFSET,  DDRSS_PHY_782_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_783_OFFSET,  DDRSS_PHY_783_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_784_OFFSET,  DDRSS_PHY_784_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_785_OFFSET,  DDRSS_PHY_785_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_786_OFFSET,  DDRSS_PHY_786_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_787_OFFSET,  DDRSS_PHY_787_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_788_OFFSET,  DDRSS_PHY_788_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_789_OFFSET,  DDRSS_PHY_789_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_790_OFFSET,  DDRSS_PHY_790_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_791_OFFSET,  DDRSS_PHY_791_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_792_OFFSET,  DDRSS_PHY_792_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_793_OFFSET,  DDRSS_PHY_793_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_794_OFFSET,  DDRSS_PHY_794_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_795_OFFSET,  DDRSS_PHY_795_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_796_OFFSET,  DDRSS_PHY_796_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_797_OFFSET,  DDRSS_PHY_797_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_798_OFFSET,  DDRSS_PHY_798_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_799_OFFSET,  DDRSS_PHY_799_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_800_OFFSET,  DDRSS_PHY_800_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_801_OFFSET,  DDRSS_PHY_801_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_802_OFFSET,  DDRSS_PHY_802_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_803_OFFSET,  DDRSS_PHY_803_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_804_OFFSET,  DDRSS_PHY_804_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_805_OFFSET,  DDRSS_PHY_805_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_806_OFFSET,  DDRSS_PHY_806_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_807_OFFSET,  DDRSS_PHY_807_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_808_OFFSET,  DDRSS_PHY_808_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_809_OFFSET,  DDRSS_PHY_809_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_810_OFFSET,  DDRSS_PHY_810_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_811_OFFSET,  DDRSS_PHY_811_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_812_OFFSET,  DDRSS_PHY_812_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_813_OFFSET,  DDRSS_PHY_813_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_814_OFFSET,  DDRSS_PHY_814_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_815_OFFSET,  DDRSS_PHY_815_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_816_OFFSET,  DDRSS_PHY_816_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_817_OFFSET,  DDRSS_PHY_817_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_818_OFFSET,  DDRSS_PHY_818_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_819_OFFSET,  DDRSS_PHY_819_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_820_OFFSET,  DDRSS_PHY_820_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_821_OFFSET,  DDRSS_PHY_821_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_822_OFFSET,  DDRSS_PHY_822_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_823_OFFSET,  DDRSS_PHY_823_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_824_OFFSET,  DDRSS_PHY_824_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_825_OFFSET,  DDRSS_PHY_825_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_826_OFFSET,  DDRSS_PHY_826_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_827_OFFSET,  DDRSS_PHY_827_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_828_OFFSET,  DDRSS_PHY_828_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_829_OFFSET,  DDRSS_PHY_829_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_830_OFFSET,  DDRSS_PHY_830_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_831_OFFSET,  DDRSS_PHY_831_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_832_OFFSET,  DDRSS_PHY_832_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_833_OFFSET,  DDRSS_PHY_833_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_834_OFFSET,  DDRSS_PHY_834_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_835_OFFSET,  DDRSS_PHY_835_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_836_OFFSET,  DDRSS_PHY_836_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_837_OFFSET,  DDRSS_PHY_837_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_838_OFFSET,  DDRSS_PHY_838_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_839_OFFSET,  DDRSS_PHY_839_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_840_OFFSET,  DDRSS_PHY_840_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_841_OFFSET,  DDRSS_PHY_841_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_842_OFFSET,  DDRSS_PHY_842_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_843_OFFSET,  DDRSS_PHY_843_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_844_OFFSET,  DDRSS_PHY_844_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_845_OFFSET,  DDRSS_PHY_845_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_846_OFFSET,  DDRSS_PHY_846_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_847_OFFSET,  DDRSS_PHY_847_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_848_OFFSET,  DDRSS_PHY_848_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_849_OFFSET,  DDRSS_PHY_849_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_850_OFFSET,  DDRSS_PHY_850_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_851_OFFSET,  DDRSS_PHY_851_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_852_OFFSET,  DDRSS_PHY_852_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_853_OFFSET,  DDRSS_PHY_853_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_854_OFFSET,  DDRSS_PHY_854_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_855_OFFSET,  DDRSS_PHY_855_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_856_OFFSET,  DDRSS_PHY_856_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_857_OFFSET,  DDRSS_PHY_857_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_858_OFFSET,  DDRSS_PHY_858_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_859_OFFSET,  DDRSS_PHY_859_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_860_OFFSET,  DDRSS_PHY_860_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_861_OFFSET,  DDRSS_PHY_861_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_862_OFFSET,  DDRSS_PHY_862_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_863_OFFSET,  DDRSS_PHY_863_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_864_OFFSET,  DDRSS_PHY_864_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_865_OFFSET,  DDRSS_PHY_865_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_866_OFFSET,  DDRSS_PHY_866_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_867_OFFSET,  DDRSS_PHY_867_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_868_OFFSET,  DDRSS_PHY_868_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_869_OFFSET,  DDRSS_PHY_869_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_870_OFFSET,  DDRSS_PHY_870_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_871_OFFSET,  DDRSS_PHY_871_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_872_OFFSET,  DDRSS_PHY_872_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_873_OFFSET,  DDRSS_PHY_873_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_874_OFFSET,  DDRSS_PHY_874_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_875_OFFSET,  DDRSS_PHY_875_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_876_OFFSET,  DDRSS_PHY_876_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_877_OFFSET,  DDRSS_PHY_877_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_878_OFFSET,  DDRSS_PHY_878_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_879_OFFSET,  DDRSS_PHY_879_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_880_OFFSET,  DDRSS_PHY_880_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_881_OFFSET,  DDRSS_PHY_881_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_882_OFFSET,  DDRSS_PHY_882_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_883_OFFSET,  DDRSS_PHY_883_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_884_OFFSET,  DDRSS_PHY_884_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_885_OFFSET,  DDRSS_PHY_885_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_886_OFFSET,  DDRSS_PHY_886_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_887_OFFSET,  DDRSS_PHY_887_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_888_OFFSET,  DDRSS_PHY_888_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_889_OFFSET,  DDRSS_PHY_889_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_890_OFFSET,  DDRSS_PHY_890_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_891_OFFSET,  DDRSS_PHY_891_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_892_OFFSET,  DDRSS_PHY_892_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_893_OFFSET,  DDRSS_PHY_893_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_894_OFFSET,  DDRSS_PHY_894_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_895_OFFSET,  DDRSS_PHY_895_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_896_OFFSET,  DDRSS_PHY_896_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_897_OFFSET,  DDRSS_PHY_897_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_898_OFFSET,  DDRSS_PHY_898_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_899_OFFSET,  DDRSS_PHY_899_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_900_OFFSET,  DDRSS_PHY_900_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_901_OFFSET,  DDRSS_PHY_901_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_902_OFFSET,  DDRSS_PHY_902_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_903_OFFSET,  DDRSS_PHY_903_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_904_OFFSET,  DDRSS_PHY_904_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_905_OFFSET,  DDRSS_PHY_905_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_906_OFFSET,  DDRSS_PHY_906_DATA );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_907_OFFSET,  DDRSS_PHY_907_DATA );
+
+    BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 3 programming completed... <<<---\n");
+
+       BOARD_DEBUG_LOG("--->>> DDR PHY Address slice 0 programming in progress.. <<<---\n");
+       //Program the Addres slice 0
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1024_OFFSET, DDRSS_PHY_1024_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1025_OFFSET, DDRSS_PHY_1025_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1026_OFFSET, DDRSS_PHY_1026_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1027_OFFSET, DDRSS_PHY_1027_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1028_OFFSET, DDRSS_PHY_1028_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1029_OFFSET, DDRSS_PHY_1029_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1030_OFFSET, DDRSS_PHY_1030_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1031_OFFSET, DDRSS_PHY_1031_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1032_OFFSET, DDRSS_PHY_1032_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1033_OFFSET, DDRSS_PHY_1033_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1034_OFFSET, DDRSS_PHY_1034_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1035_OFFSET, DDRSS_PHY_1035_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1036_OFFSET, DDRSS_PHY_1036_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1037_OFFSET, DDRSS_PHY_1037_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1038_OFFSET, DDRSS_PHY_1038_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1039_OFFSET, DDRSS_PHY_1039_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1040_OFFSET, DDRSS_PHY_1040_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1041_OFFSET, DDRSS_PHY_1041_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1042_OFFSET, DDRSS_PHY_1042_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1043_OFFSET, DDRSS_PHY_1043_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1044_OFFSET, DDRSS_PHY_1044_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1045_OFFSET, DDRSS_PHY_1045_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1046_OFFSET, DDRSS_PHY_1046_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1047_OFFSET, DDRSS_PHY_1047_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1048_OFFSET, DDRSS_PHY_1048_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1049_OFFSET, DDRSS_PHY_1049_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1050_OFFSET, DDRSS_PHY_1050_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1051_OFFSET, DDRSS_PHY_1051_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1052_OFFSET, DDRSS_PHY_1052_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1053_OFFSET, DDRSS_PHY_1053_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1054_OFFSET, DDRSS_PHY_1054_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1055_OFFSET, DDRSS_PHY_1055_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1056_OFFSET, DDRSS_PHY_1056_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1057_OFFSET, DDRSS_PHY_1057_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1058_OFFSET, DDRSS_PHY_1058_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1059_OFFSET, DDRSS_PHY_1059_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1060_OFFSET, DDRSS_PHY_1060_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1061_OFFSET, DDRSS_PHY_1061_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1062_OFFSET, DDRSS_PHY_1062_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1063_OFFSET, DDRSS_PHY_1063_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1064_OFFSET, DDRSS_PHY_1064_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1065_OFFSET, DDRSS_PHY_1065_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1066_OFFSET, DDRSS_PHY_1066_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1067_OFFSET, DDRSS_PHY_1067_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1068_OFFSET, DDRSS_PHY_1068_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1069_OFFSET, DDRSS_PHY_1069_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1070_OFFSET, DDRSS_PHY_1070_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1071_OFFSET, DDRSS_PHY_1071_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1072_OFFSET, DDRSS_PHY_1072_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1073_OFFSET, DDRSS_PHY_1073_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1074_OFFSET, DDRSS_PHY_1074_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1075_OFFSET, DDRSS_PHY_1075_DATA  );
+
+    BOARD_DEBUG_LOG("--->>> DDR PHY Address Slice 0 programming completed... <<<---\n");
+       BOARD_DEBUG_LOG("--->>> DDR PHY programming in progress.. <<<---\n");
+
+       BOARD_DEBUG_LOG("--->>> Set PHY registers for F1 freq... <<<---\n");
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1281_OFFSET, 0x00000100  );
+
+    //Program the PHY
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1280_OFFSET, DDRSS_PHY_1280_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1281_OFFSET, DDRSS_PHY_1281_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1282_OFFSET, DDRSS_PHY_1282_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1283_OFFSET, DDRSS_PHY_1283_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1284_OFFSET, DDRSS_PHY_1284_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1285_OFFSET, DDRSS_PHY_1285_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1286_OFFSET, DDRSS_PHY_1286_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1287_OFFSET, DDRSS_PHY_1287_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1288_OFFSET, DDRSS_PHY_1288_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1289_OFFSET, DDRSS_PHY_1289_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1290_OFFSET, DDRSS_PHY_1290_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1291_OFFSET, DDRSS_PHY_1291_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1292_OFFSET, DDRSS_PHY_1292_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1293_OFFSET, DDRSS_PHY_1293_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1294_OFFSET, DDRSS_PHY_1294_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1295_OFFSET, DDRSS_PHY_1295_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1296_OFFSET, DDRSS_PHY_1296_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1297_OFFSET, DDRSS_PHY_1297_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1298_OFFSET, DDRSS_PHY_1298_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1299_OFFSET, DDRSS_PHY_1299_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1300_OFFSET, DDRSS_PHY_1300_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1301_OFFSET, DDRSS_PHY_1301_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1302_OFFSET, DDRSS_PHY_1302_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1303_OFFSET, DDRSS_PHY_1303_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1304_OFFSET, DDRSS_PHY_1304_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1305_OFFSET, DDRSS_PHY_1305_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1306_OFFSET, DDRSS_PHY_1306_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1307_OFFSET, DDRSS_PHY_1307_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1308_OFFSET, DDRSS_PHY_1308_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1309_OFFSET, DDRSS_PHY_1309_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1310_OFFSET, DDRSS_PHY_1310_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1311_OFFSET, DDRSS_PHY_1311_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1312_OFFSET, DDRSS_PHY_1312_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1313_OFFSET, DDRSS_PHY_1313_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1314_OFFSET, DDRSS_PHY_1314_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1315_OFFSET, DDRSS_PHY_1315_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1316_OFFSET, DDRSS_PHY_1316_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1317_OFFSET, DDRSS_PHY_1317_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1318_OFFSET, DDRSS_PHY_1318_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1319_OFFSET, DDRSS_PHY_1319_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1320_OFFSET, DDRSS_PHY_1320_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1321_OFFSET, DDRSS_PHY_1321_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1322_OFFSET, DDRSS_PHY_1322_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1323_OFFSET, DDRSS_PHY_1323_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1324_OFFSET, DDRSS_PHY_1324_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1325_OFFSET, DDRSS_PHY_1325_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1326_OFFSET, DDRSS_PHY_1326_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1327_OFFSET, DDRSS_PHY_1327_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1328_OFFSET, DDRSS_PHY_1328_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1329_OFFSET, DDRSS_PHY_1329_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1330_OFFSET, DDRSS_PHY_1330_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1331_OFFSET, DDRSS_PHY_1331_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1332_OFFSET, DDRSS_PHY_1332_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1333_OFFSET, DDRSS_PHY_1333_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1334_OFFSET, DDRSS_PHY_1334_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1335_OFFSET, DDRSS_PHY_1335_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1336_OFFSET, DDRSS_PHY_1336_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1337_OFFSET, DDRSS_PHY_1337_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1338_OFFSET, DDRSS_PHY_1338_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1339_OFFSET, DDRSS_PHY_1339_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1340_OFFSET, DDRSS_PHY_1340_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1341_OFFSET, DDRSS_PHY_1341_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1342_OFFSET, DDRSS_PHY_1342_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1343_OFFSET, DDRSS_PHY_1343_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1344_OFFSET, DDRSS_PHY_1344_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1345_OFFSET, DDRSS_PHY_1345_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1346_OFFSET, DDRSS_PHY_1346_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1347_OFFSET, DDRSS_PHY_1347_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1348_OFFSET, DDRSS_PHY_1348_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1349_OFFSET, DDRSS_PHY_1349_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1350_OFFSET, DDRSS_PHY_1350_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1351_OFFSET, DDRSS_PHY_1351_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1352_OFFSET, DDRSS_PHY_1352_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1353_OFFSET, DDRSS_PHY_1353_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1354_OFFSET, DDRSS_PHY_1354_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1355_OFFSET, DDRSS_PHY_1355_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1356_OFFSET, DDRSS_PHY_1356_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1357_OFFSET, DDRSS_PHY_1357_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1358_OFFSET, DDRSS_PHY_1358_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1359_OFFSET, DDRSS_PHY_1359_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1360_OFFSET, DDRSS_PHY_1360_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1361_OFFSET, DDRSS_PHY_1361_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1362_OFFSET, DDRSS_PHY_1362_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1363_OFFSET, DDRSS_PHY_1363_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1364_OFFSET, DDRSS_PHY_1364_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1365_OFFSET, DDRSS_PHY_1365_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1366_OFFSET, DDRSS_PHY_1366_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1367_OFFSET, DDRSS_PHY_1367_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1368_OFFSET, DDRSS_PHY_1368_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1369_OFFSET, DDRSS_PHY_1369_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1370_OFFSET, DDRSS_PHY_1370_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1371_OFFSET, DDRSS_PHY_1371_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1372_OFFSET, DDRSS_PHY_1372_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1373_OFFSET, DDRSS_PHY_1373_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1374_OFFSET, DDRSS_PHY_1374_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1375_OFFSET, DDRSS_PHY_1375_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1376_OFFSET, DDRSS_PHY_1376_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1377_OFFSET, DDRSS_PHY_1377_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1378_OFFSET, DDRSS_PHY_1378_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1379_OFFSET, DDRSS_PHY_1379_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1380_OFFSET, DDRSS_PHY_1380_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1381_OFFSET, DDRSS_PHY_1381_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1382_OFFSET, DDRSS_PHY_1382_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1383_OFFSET, DDRSS_PHY_1383_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1384_OFFSET, DDRSS_PHY_1384_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1385_OFFSET, DDRSS_PHY_1385_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1386_OFFSET, DDRSS_PHY_1386_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1387_OFFSET, DDRSS_PHY_1387_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1388_OFFSET, DDRSS_PHY_1388_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1389_OFFSET, DDRSS_PHY_1389_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1390_OFFSET, DDRSS_PHY_1390_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1391_OFFSET, DDRSS_PHY_1391_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1392_OFFSET, DDRSS_PHY_1392_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1393_OFFSET, DDRSS_PHY_1393_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1394_OFFSET, DDRSS_PHY_1394_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1395_OFFSET, DDRSS_PHY_1395_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1396_OFFSET, DDRSS_PHY_1396_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1397_OFFSET, DDRSS_PHY_1397_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1398_OFFSET, DDRSS_PHY_1398_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1399_OFFSET, DDRSS_PHY_1399_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1400_OFFSET, DDRSS_PHY_1400_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1401_OFFSET, DDRSS_PHY_1401_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1402_OFFSET, DDRSS_PHY_1402_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1403_OFFSET, DDRSS_PHY_1403_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1404_OFFSET, DDRSS_PHY_1404_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1405_OFFSET, DDRSS_PHY_1405_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1406_OFFSET, DDRSS_PHY_1406_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1407_OFFSET, DDRSS_PHY_1407_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1408_OFFSET, DDRSS_PHY_1408_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1409_OFFSET, DDRSS_PHY_1409_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1410_OFFSET, DDRSS_PHY_1410_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1411_OFFSET, DDRSS_PHY_1411_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1412_OFFSET, DDRSS_PHY_1412_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1413_OFFSET, DDRSS_PHY_1413_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1414_OFFSET, DDRSS_PHY_1414_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1415_OFFSET, DDRSS_PHY_1415_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1416_OFFSET, DDRSS_PHY_1416_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1417_OFFSET, DDRSS_PHY_1417_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1418_OFFSET, DDRSS_PHY_1418_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1419_OFFSET, DDRSS_PHY_1419_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1420_OFFSET, DDRSS_PHY_1420_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1421_OFFSET, DDRSS_PHY_1421_DATA  );
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1422_OFFSET, DDRSS_PHY_1422_DATA  );
+    
+    BOARD_DEBUG_LOG("--->>> DDR PHY programming completed... <<<---\n");
+
+    BOARD_DEBUG_LOG("--->>> Set PHY registers for F2 freq... <<<---\n");
+
+       //trigger the start bit
+
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_0_OFFSET,   0x00000B01   );
+
+       //BOARD_DEBUG_LOG("--->>> DDR PI initialization started... <<<---\n");
+    BOARD_delay(100000);
+
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_0_OFFSET,   0x00000B01  );
+
+       //Partition5 lockkey0
+       HW_WR_REG32((M3_RAT_OFFSET + 0x115008), 0x68EF3490);
+       //Partition5 lockkey1
+       HW_WR_REG32((M3_RAT_OFFSET + 0x11500C), 0xD172BC5A);
+       Board_DDRChangeFreqAck();
+
+    BOARD_DEBUG_LOG("--->>> Waiting..CP1 <<<---\n");
+
+       while(((HW_RD_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_79_OFFSET)) & 0x1) != 0x1);
+
+    BOARD_DEBUG_LOG("--->>> Waiting..CP2 <<<---\n");
+
+    while((HW_RD_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_293_OFFSET)!= 0x200)); //181108 rls - change to 293
+
+       HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_80_OFFSET, 0x1 );
+
+    HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_295_OFFSET, 0x200 );
+
+       BOARD_DEBUG_LOG("--->>> DDR 3733MTs Initialization completed... <<<---\n");
+
+    return BOARD_SOK;
+}
diff --git a/packages/ti/board/src/j7200_evm/board_ethernet_config.c b/packages/ti/board/src/j7200_evm/board_ethernet_config.c
new file mode 100644 (file)
index 0000000..e889662
--- /dev/null
@@ -0,0 +1,590 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ *   \file  board_ethernet_config.c\r
+ *\r
+ *   \brief\r
+ *      This file contains the boards specific Ethernet PHY configurations.\r
+ *\r
+ */\r
+\r
+#include "board_ethernet_config.h"\r
+#include "board_internal.h"\r
+#include <ti/csl/soc.h>\r
+#include <ti/csl/cslr_mdio.h>\r
+\r
+\r
+\r
+Board_pruicssMdioInfo  Board_cpswMdioInfo[BOARD_CPSW9G_EMAC_PORT_MAX] =\r
+                       {{(CSL_CPSW0_NUSS_BASE + BOARD_CPSW_MDIO_REG_OFFSET), BOARD_ICSS0_EMAC_PHY0_ADDR},\r
+                        {(CSL_CPSW0_NUSS_BASE + BOARD_CPSW_MDIO_REG_OFFSET), BOARD_ICSS0_EMAC_PHY1_ADDR},\r
+                        {(CSL_CPSW0_NUSS_BASE + BOARD_CPSW_MDIO_REG_OFFSET), BOARD_ICSS1_EMAC_PHY0_ADDR},\r
+                        {(CSL_CPSW0_NUSS_BASE + BOARD_CPSW_MDIO_REG_OFFSET), BOARD_ICSS1_EMAC_PHY1_ADDR},\r
+                       };\r
+/**\r
+ * \brief  Function to initialize MDIO\r
+ *\r
+ * \param   baseAddr [IN]   MDIO base address\r
+ *\r
+ * \return  uint32_t\r
+            TRUE     Read is successful.\r
+ *          FALSE    Read is not acknowledged properly.\r
+ */\r
+static void Board_mdioInit(uint32_t baseAddr)\r
+{\r
+    HW_WR_REG32((baseAddr + BOARD_MDIO_CTRL_REG_OFFSET),\r
+                (CSL_FMKT(MDIO_CONTROL_REG_ENABLE, YES) |\r
+                CSL_FMK(MDIO_CONTROL_REG_CLKDIV,\r
+                BOARD_MDIO_CLK_DIV_CFG)));\r
+}\r
+\r
+/**\r
+ * \brief  PHY register write function\r
+ *\r
+ * This function is used to writes a PHY register using MDIO.\r
+ *\r
+ * \param   baseAddr [IN]   MDIO base address\r
+ *          phyAddr  [IN]   PHY Address\r
+ *          regAddr  [IN]   Register offset to be written\r
+ *          data     [IN]   Value to be written\r
+ *\r
+ */\r
+static void Board_ethPhyRegWrite(uint32_t baseAddr, uint32_t phyAddr,\r
+                                 uint32_t regAddr, uint16_t data)\r
+{\r
+    uint32_t regVal = 0U;\r
+\r
+    /* Wait till transaction completion if any */\r
+    while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
+          CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)\r
+    {}\r
+\r
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO, 1);\r
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_WRITE, 1);\r
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_PHYADR, phyAddr);\r
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_REGADR, regAddr);\r
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_DATA, data);\r
+    HW_WR_REG32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U), regVal);\r
+\r
+    /* wait for command completion */\r
+    while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
+          CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)\r
+    {}\r
+}\r
+\r
+/**\r
+ * \brief  PHY register read function\r
+ *\r
+ * This function is used to Read a PHY register using MDIO.\r
+ *\r
+ * \param   baseAddr [IN]   MDIO base address\r
+ *          phyAddr  [IN]   PHY Address\r
+ *          regAddr  [IN]   Register offset to be written\r
+ *          regData  [OUT]  Pointer where the read value shall be written\r
+ *\r
+ * \return  uint32_t\r
+            TRUE     Read is successful.\r
+ *          FALSE    Read is not acknowledged properly.\r
+ */\r
+static uint32_t BoardDiag_ethPhyRegRead(uint32_t baseAddr, uint32_t phyAddr,\r
+                                        uint32_t regAddr, uint16_t *regData)\r
+{\r
+    uint32_t regVal = 0U;\r
+    uint32_t retVal = 0U;\r
+\r
+    /* Wait till transaction completion if any */\r
+    while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
+        CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)\r
+    {}\r
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO,1);\r
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_WRITE, 0);\r
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_PHYADR, phyAddr);\r
+    HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_REGADR, regAddr);\r
+    HW_WR_REG32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U), regVal);\r
+\r
+    /* wait for command completion */\r
+    while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
+          CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)\r
+    {}\r
+\r
+    /* Store the data if the read is acknowledged */\r
+    if(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
+        CSL_MDIO_USER_GROUP_USER_ACCESS_REG_ACK) == 1)\r
+    {\r
+        *regData = (uint16_t)(HW_RD_FIELD32(baseAddr + \\r
+                    CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
+                    CSL_MDIO_USER_GROUP_USER_ACCESS_REG_DATA));\r
+        retVal = (uint32_t)TRUE;\r
+    }\r
+    else\r
+    {\r
+        retVal = (uint32_t)FALSE;\r
+    }\r
+\r
+    return(retVal);\r
+}\r
+\r
+/**\r
+ * \brief  Function to write extended address registers of Ethernet PHY\r
+ *\r
+ * \param   baseAddr [IN]    MDIO base address\r
+ *          phyAddr  [IN]    Ethernet PHY address\r
+ *          regNum   [IN]    PHY Register address\r
+ *          pData    [OUT]   Values read from register\r
+ *\r
+ */\r
+static void Board_ethPhyExtendedRegRead (uint32_t baseAddr,\r
+                                         uint32_t phyAddr,\r
+                                         uint32_t regNum,\r
+                                         uint16_t *pData)\r
+{\r
+    Board_ethPhyRegWrite(baseAddr, phyAddr,\r
+                         BOARD_ETHPHY_REGCR_REG_ADDR,\r
+                         BOARD_ETHPHY_REGCR_ADDR_EN);\r
+    Board_ethPhyRegWrite(baseAddr, phyAddr,\r
+                         BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);\r
+    Board_ethPhyRegWrite(baseAddr, phyAddr,\r
+                         BOARD_ETHPHY_REGCR_REG_ADDR,\r
+                         BOARD_ETHPHY_REGCR_DATA_EN);\r
+    BoardDiag_ethPhyRegRead(baseAddr, phyAddr,\r
+                            BOARD_ETHPHY_ADDAR_REG_ADDR, pData);\r
+}\r
+\r
+/**\r
+ * \brief  Function to write extended address registers of Ethernet PHY\r
+ *\r
+ * \param   baseAddr [IN]    MDIO base address\r
+ * \param   phyAddr  [IN]    Ethernet PHY address\r
+ * \param   regNum   [IN]    PHY Register address\r
+ * \param   regVal   [IN]    Register value to be written\r
+ *\r
+ * \return  none\r
+ */\r
+static void Board_ethPhyExtendedRegWrite(uint32_t baseAddr,\r
+                                         uint32_t phyAddr,\r
+                                         uint32_t regNum,\r
+                                         uint16_t regVal)\r
+{\r
+    Board_ethPhyRegWrite(baseAddr, phyAddr,\r
+                         BOARD_ETHPHY_REGCR_REG_ADDR,\r
+                         BOARD_ETHPHY_REGCR_ADDR_EN);\r
+    Board_ethPhyRegWrite(baseAddr, phyAddr,\r
+                         BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);\r
+    Board_ethPhyRegWrite(baseAddr, phyAddr,\r
+                         BOARD_ETHPHY_REGCR_REG_ADDR,\r
+                         BOARD_ETHPHY_REGCR_DATA_EN);\r
+    Board_ethPhyRegWrite(baseAddr, phyAddr,\r
+                         BOARD_ETHPHY_ADDAR_REG_ADDR, regVal);\r
+}\r
+\r
+/**\r
+ * \brief  Power down the ENET PHYs\r
+ *\r
+ * \return  BOARD_SOK in case of success or appropriate error code\r
+ */\r
+static Board_STATUS Board_enetPhyPwrDwn(void)\r
+{\r
+    Board_IoExpCfg_t ioExpCfg;\r
+    Board_STATUS status = BOARD_SOK;\r
+    bool isAlpha = 0;\r
+\r
+    /*\r
+     * MDIO stability issue due to ENET card is resolved in Beta HW revision.\r
+     * Disabling ENET card is needed only for Alpha CP boards.\r
+     */\r
+    isAlpha = Board_isAlpha(BOARD_ID_CP);\r
+\r
+    if((isAlpha == TRUE) && (Board_detectBoard(BOARD_ID_ENET) == TRUE))\r
+    {\r
+        ioExpCfg.i2cInst     = BOARD_I2C_IOEXP_DEVICE2_INSTANCE;\r
+        ioExpCfg.socDomain