[WIP][PDK-8726] Separate OSPI tests keeping memory cached/non-cached

- added new tests that export cache as enabled
- separate mpu.xs files for cache enabled/disabled
- RTOS implemented, baremetal pending

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>

diff --git a/packages/ti/drv/spi/spi_component.mk b/packages/ti/drv/spi/spi_component.mk
index 8722a2fd049788e97ec782ca90a6e4724b4745d8..edc200add8fe0e27baa00ba2c9d880e1a4cd93ed 100644 (file)
--- a/packages/ti/drv/spi/spi_component.mk
+++ b/packages/ti/drv/spi/spi_component.mk
@@ -126,7 +126,7 @@ spi_EXAMPLE_LIST += MCSPI_Baremetal_Master_TestApp MCSPI_Baremetal_Slave_TestApp
 spi_EXAMPLE_LIST += MCSPI_Master_TestApp MCSPI_Slave_TestApp
 spi_EXAMPLE_LIST += MCSPI_Baremetal_Master_Dma_TestApp MCSPI_Baremetal_Slave_Dma_TestApp
 spi_EXAMPLE_LIST += MCSPI_Master_Dma_TestApp MCSPI_Slave_Dma_TestApp
 spi_EXAMPLE_LIST += MCSPI_Master_TestApp MCSPI_Slave_TestApp
 spi_EXAMPLE_LIST += MCSPI_Baremetal_Master_Dma_TestApp MCSPI_Baremetal_Slave_Dma_TestApp
 spi_EXAMPLE_LIST += MCSPI_Master_Dma_TestApp MCSPI_Slave_Dma_TestApp

-spi_EXAMPLE_LIST += OSPI_Baremetal_Flash_TestApp  OSPI_Baremetal_Flash_Dma_TestApp OSPI_Flash_TestApp OSPI_Flash_SMP_TestApp OSPI_Flash_Dma_TestApp OSPI_Flash_Dma_SMP_TestApp QSPI_Baremetal_Flash_TestApp QSPI_Flash_TestApp QSPI_Baremetal_Flash_Dma_TestApp QSPI_Flash_Dma_TestApp QSPI_FileFlashWrite_Dma_TestApp
+spi_EXAMPLE_LIST += OSPI_Baremetal_Flash_TestApp  OSPI_Baremetal_Flash_Dma_TestApp OSPI_Flash_TestApp OSPI_Flash_Dma_TestApp OSPI_Baremetal_Flash_Cache_TestApp  OSPI_Baremetal_Flash_Dma_Cache_TestApp OSPI_Flash_Cache_TestApp OSPI_Flash_Dma_Cache_TestApp OSPI_Flash_SMP_TestApp OSPI_Flash_Dma_SMP_TestApp QSPI_Baremetal_Flash_TestApp QSPI_Flash_TestApp QSPI_Baremetal_Flash_Dma_TestApp QSPI_Flash_Dma_TestApp QSPI_FileFlashWrite_Dma_TestApp

 drvspi_EXAMPLE_LIST = $(spi_EXAMPLE_LIST)
 
 #
 drvspi_EXAMPLE_LIST = $(spi_EXAMPLE_LIST)
 
 #


@@ -622,31 +622,6 @@ OSPI_Flash_TestApp_SBL_APPIMAGEGEN = yes
 export OSPI_Flash_TestApp_SBL_APPIMAGEGEN
 endif
 
 export OSPI_Flash_TestApp_SBL_APPIMAGEGEN
 endif
 

-# OSPI rtos Flash Test app with SMP enabled
-OSPI_Flash_SMP_TestApp_COMP_LIST = OSPI_Flash_SMP_TestApp
-OSPI_Flash_SMP_TestApp_RELPATH = ti/drv/spi/test/ospi_flash
-OSPI_Flash_SMP_TestApp_PATH = $(PDK_SPI_COMP_PATH)/test/ospi_flash
-OSPI_Flash_SMP_TestApp_BOARD_DEPENDENCY = yes
-OSPI_Flash_SMP_TestApp_CORE_DEPENDENCY = no
-OSPI_Flash_SMP_TestApp_XDC_CONFIGURO = yes
-OSPI_Flash_SMP_TestApp_MAKEFILE = -f makefile SMP=enable
-export OSPI_Flash_SMP_TestApp_COMP_LIST
-export OSPI_Flash_SMP_TestApp_BOARD_DEPENDENCY
-export OSPI_Flash_SMP_TestApp_CORE_DEPENDENCY
-export OSPI_Flash_SMP_TestApp_XDC_CONFIGURO
-export OSPI_Flash_SMP_TestApp_MAKEFILE
-OSPI_Flash_SMP_TestApp_PKG_LIST = OSPI_Flash_SMP_TestApp
-OSPI_Flash_SMP_TestApp_INCLUDE = $(OSPI_Flash_SMP_TestApp_PATH)
-OSPI_Flash_SMP_TestApp_BOARDLIST = am65xx_idk
-export OSPI_Flash_SMP_TestApp_BOARDLIST
-OSPI_Flash_SMP_TestApp_$(SOC)_CORELIST = mpu1_0
-export OSPI_Flash_SMP_TestApp_$(SOC)_CORELIST
-
-ifeq ($(SOC),$(filter $(SOC), j721e am65xx))
-OSPI_Flash_SMP_TestApp_SBL_APPIMAGEGEN = yes
-export OSPI_Flash_SMP_TestApp_SBL_APPIMAGEGEN
-endif
-

 # OSPI rtos DMA Flash Test app
 OSPI_Flash_Dma_TestApp_COMP_LIST = OSPI_Flash_Dma_TestApp
 OSPI_Flash_Dma_TestApp_RELPATH = ti/drv/spi/test/ospi_flash
 # OSPI rtos DMA Flash Test app
 OSPI_Flash_Dma_TestApp_COMP_LIST = OSPI_Flash_Dma_TestApp
 OSPI_Flash_Dma_TestApp_RELPATH = ti/drv/spi/test/ospi_flash


@@ -676,6 +651,143 @@ OSPI_Flash_Dma_TestApp_SBL_APPIMAGEGEN = yes
 export OSPI_Flash_Dma_TestApp_SBL_APPIMAGEGEN
 endif
 
 export OSPI_Flash_Dma_TestApp_SBL_APPIMAGEGEN
 endif
 

+# OSPI baremetal Flash Test app with cacheable OSPI memory
+OSPI_Baremetal_Flash_Cache_TestApp_COMP_LIST = OSPI_Baremetal_Flash_Cache_TestApp
+OSPI_Baremetal_Flash_Cache_TestApp_RELPATH = ti/drv/spi/test/ospi_flash
+OSPI_Baremetal_Flash_Cache_TestApp_PATH = $(PDK_SPI_COMP_PATH)/test/ospi_flash
+OSPI_Baremetal_Flash_Cache_TestApp_BOARD_DEPENDENCY = yes
+OSPI_Baremetal_Flash_Cache_TestApp_CORE_DEPENDENCY = no
+OSPI_Baremetal_Flash_Cache_TestApp_MAKEFILE = -f makefile IS_BAREMETAL=yes CACHE=enable
+export OSPI_Baremetal_Flash_Cache_TestApp_COMP_LIST
+export OSPI_Baremetal_Flash_Cache_TestApp_BOARD_DEPENDENCY
+export OSPI_Baremetal_Flash_Cache_TestApp_CORE_DEPENDENCY
+export OSPI_Baremetal_Flash_Cache_TestApp_MAKEFILE
+OSPI_Baremetal_Flash_Cache_TestApp_PKG_LIST = OSPI_Baremetal_Flash_Cache_TestApp
+OSPI_Baremetal_Flash_Cache_TestApp_INCLUDE = $(OSPI_Baremetal_Flash_Cache_TestApp_PATH)
+OSPI_Baremetal_Flash_Cache_TestApp_BOARDLIST = $(drvspi_BOARDLIST)
+export OSPI_Baremetal_Flash_Cache_TestApp_BOARDLIST
+ifeq ($(SOC),$(filter $(SOC), j721e am64x))
+OSPI_Baremetal_Flash_Cache_TestApp_$(SOC)_CORELIST = $(drvspi_$(SOC)_CORELISTARM)
+else
+OSPI_Baremetal_Flash_Cache_TestApp_$(SOC)_CORELIST = $(drvspi_$(SOC)_CORELIST)
+endif
+export OSPI_Baremetal_Flash_Cache_TestApp_$(SOC)_CORELIST
+
+ifeq ($(SOC),$(filter $(SOC), j721e am65xx j7200 am64x))
+OSPI_Baremetal_Flash_Cache_TestApp_SBL_APPIMAGEGEN = yes
+export OSPI_Baremetal_Flash_Cache_TestApp_SBL_APPIMAGEGEN
+endif
+
+# OSPI baremetal dma Flash Test app with cacheable OSPI memory
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_COMP_LIST = OSPI_Baremetal_Flash_Dma_Cache_TestApp
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_RELPATH = ti/drv/spi/test/ospi_flash
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_PATH = $(PDK_SPI_COMP_PATH)/test/ospi_flash
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_BOARD_DEPENDENCY = yes
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_CORE_DEPENDENCY = no
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_MAKEFILE = -f makefile IS_BAREMETAL=yes DMA=enable CACHE=enable
+export OSPI_Baremetal_Flash_Dma_Cache_TestApp_COMP_LIST
+export OSPI_Baremetal_Flash_Dma_Cache_TestApp_BOARD_DEPENDENCY
+export OSPI_Baremetal_Flash_Dma_Cache_TestApp_CORE_DEPENDENCY
+export OSPI_Baremetal_Flash_Dma_Cache_TestApp_MAKEFILE
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_PKG_LIST = OSPI_Baremetal_Flash_Dma_Cache_TestApp
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_INCLUDE = $(OSPI_Baremetal_Flash_Dma_Cache_TestApp_PATH)
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_BOARDLIST = $(drvspi_BOARDLIST)
+export OSPI_Baremetal_Flash_Dma_Cache_TestApp_BOARDLIST
+ifeq ($(SOC),$(filter $(SOC), j721e am64x))
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_$(SOC)_CORELIST = $(drvspi_$(SOC)_CORELISTARM)
+else
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_$(SOC)_CORELIST = $(drvspi_$(SOC)_CORELIST)
+endif
+export OSPI_Baremetal_Flash_Dma_Cache_TestApp_$(SOC)_CORELIST
+
+ifeq ($(SOC),$(filter $(SOC), j721e am65xx j7200 am64x))
+OSPI_Baremetal_Flash_Dma_Cache_TestApp_SBL_APPIMAGEGEN = yes
+export OSPI_Baremetal_Flash_Dma_Cache_TestApp_SBL_APPIMAGEGEN
+endif
+
+# OSPI rtos Flash Test app with cacheable OSPI memory
+OSPI_Flash_Cache_TestApp_COMP_LIST = OSPI_Flash_Cache_TestApp
+OSPI_Flash_Cache_TestApp_RELPATH = ti/drv/spi/test/ospi_flash
+OSPI_Flash_Cache_TestApp_PATH = $(PDK_SPI_COMP_PATH)/test/ospi_flash
+OSPI_Flash_Cache_TestApp_BOARD_DEPENDENCY = yes
+OSPI_Flash_Cache_TestApp_CORE_DEPENDENCY = no
+OSPI_Flash_Cache_TestApp_XDC_CONFIGURO = yes
+OSPI_Flash_Cache_TestApp_MAKEFILE = -f makefile CACHE=enable
+export OSPI_Flash_Cache_TestApp_COMP_LIST
+export OSPI_Flash_Cache_TestApp_BOARD_DEPENDENCY
+export OSPI_Flash_Cache_TestApp_CORE_DEPENDENCY
+export OSPI_Flash_Cache_TestApp_XDC_CONFIGURO
+export OSPI_Flash_Cache_TestApp_MAKEFILE
+OSPI_Flash_Cache_TestApp_PKG_LIST = OSPI_Flash_Cache_TestApp
+OSPI_Flash_Cache_TestApp_INCLUDE = $(OSPI_Flash_Cache_TestApp_PATH)
+OSPI_Flash_Cache_TestApp_BOARDLIST = $(drvspi_BOARDLIST)
+export OSPI_Flash_Cache_TestApp_BOARDLIST
+ifeq ($(SOC),$(filter $(SOC), j721e am64x))
+OSPI_Flash_Cache_TestApp_$(SOC)_CORELIST = $(drvspi_$(SOC)_CORELISTARM)
+else
+OSPI_Flash_Cache_TestApp_$(SOC)_CORELIST = $(drvspi_$(SOC)_CORELIST)
+endif
+export OSPI_Flash_Cache_TestApp_$(SOC)_CORELIST
+
+ifeq ($(SOC),$(filter $(SOC), j721e am65xx j7200 am64x))
+OSPI_Flash_Cache_TestApp_SBL_APPIMAGEGEN = yes
+export OSPI_Flash_Cache_TestApp_SBL_APPIMAGEGEN
+endif
+
+# OSPI rtos DMA Flash Test app with cacheable OSPI memory
+OSPI_Flash_Dma_Cache_TestApp_COMP_LIST = OSPI_Flash_Dma_Cache_TestApp
+OSPI_Flash_Dma_Cache_TestApp_RELPATH = ti/drv/spi/test/ospi_flash
+OSPI_Flash_Dma_Cache_TestApp_PATH = $(PDK_SPI_COMP_PATH)/test/ospi_flash
+OSPI_Flash_Dma_Cache_TestApp_BOARD_DEPENDENCY = yes
+OSPI_Flash_Dma_Cache_TestApp_CORE_DEPENDENCY = no
+OSPI_Flash_Dma_Cache_TestApp_XDC_CONFIGURO = yes
+OSPI_Flash_Dma_Cache_TestApp_MAKEFILE = -f makefile DMA=enable CACHE=enable
+export OSPI_Flash_Dma_Cache_TestApp_COMP_LIST
+export OSPI_Flash_Dma_Cache_TestApp_BOARD_DEPENDENCY
+export OSPI_Flash_Dma_Cache_TestApp_CORE_DEPENDENCY
+export OSPI_Flash_Dma_Cache_TestApp_XDC_CONFIGURO
+export OSPI_Flash_Dma_Cache_TestApp_MAKEFILE
+OSPI_Flash_Dma_Cache_TestApp_PKG_LIST = OSPI_Flash_Dma_Cache_TestApp
+OSPI_Flash_Dma_Cache_TestApp_INCLUDE = $(OSPI_Flash_Dma_Cache_TestApp_PATH)
+OSPI_Flash_Dma_Cache_TestApp_BOARDLIST = $(drvspi_BOARDLIST)
+export OSPI_Flash_Dma_Cache_TestApp_BOARDLIST
+ifeq ($(SOC),$(filter $(SOC), j721e am64x))
+OSPI_Flash_Dma_Cache_TestApp_$(SOC)_CORELIST = $(drvspi_$(SOC)_CORELISTARM)
+else
+OSPI_Flash_Dma_Cache_TestApp_$(SOC)_CORELIST = $(drvspi_$(SOC)_CORELIST)
+endif
+export OSPI_Flash_Dma_Cache_TestApp_$(SOC)_CORELIST
+
+ifeq ($(SOC),$(filter $(SOC), j721e am65xx j7200 am64x))
+OSPI_Flash_Dma_Cache_TestApp_SBL_APPIMAGEGEN = yes
+export OSPI_Flash_Dma_Cache_TestApp_SBL_APPIMAGEGEN
+endif
+
+# OSPI rtos Flash Test app with SMP enabled
+OSPI_Flash_SMP_TestApp_COMP_LIST = OSPI_Flash_SMP_TestApp
+OSPI_Flash_SMP_TestApp_RELPATH = ti/drv/spi/test/ospi_flash
+OSPI_Flash_SMP_TestApp_PATH = $(PDK_SPI_COMP_PATH)/test/ospi_flash
+OSPI_Flash_SMP_TestApp_BOARD_DEPENDENCY = yes
+OSPI_Flash_SMP_TestApp_CORE_DEPENDENCY = no
+OSPI_Flash_SMP_TestApp_XDC_CONFIGURO = yes
+OSPI_Flash_SMP_TestApp_MAKEFILE = -f makefile SMP=enable
+export OSPI_Flash_SMP_TestApp_COMP_LIST
+export OSPI_Flash_SMP_TestApp_BOARD_DEPENDENCY
+export OSPI_Flash_SMP_TestApp_CORE_DEPENDENCY
+export OSPI_Flash_SMP_TestApp_XDC_CONFIGURO
+export OSPI_Flash_SMP_TestApp_MAKEFILE
+OSPI_Flash_SMP_TestApp_PKG_LIST = OSPI_Flash_SMP_TestApp
+OSPI_Flash_SMP_TestApp_INCLUDE = $(OSPI_Flash_SMP_TestApp_PATH)
+OSPI_Flash_SMP_TestApp_BOARDLIST = am65xx_idk
+export OSPI_Flash_SMP_TestApp_BOARDLIST
+OSPI_Flash_SMP_TestApp_$(SOC)_CORELIST = mpu1_0
+export OSPI_Flash_SMP_TestApp_$(SOC)_CORELIST
+
+ifeq ($(SOC),$(filter $(SOC), j721e am65xx))
+OSPI_Flash_SMP_TestApp_SBL_APPIMAGEGEN = yes
+export OSPI_Flash_SMP_TestApp_SBL_APPIMAGEGEN
+endif
+

 # OSPI rtos DMA Flash Test app with SMP enabled
 OSPI_Flash_Dma_SMP_TestApp_COMP_LIST = OSPI_Flash_Dma_SMP_TestApp
 OSPI_Flash_Dma_SMP_TestApp_RELPATH = ti/drv/spi/test/ospi_flash
 # OSPI rtos DMA Flash Test app with SMP enabled
 OSPI_Flash_Dma_SMP_TestApp_COMP_LIST = OSPI_Flash_Dma_SMP_TestApp
 OSPI_Flash_Dma_SMP_TestApp_RELPATH = ti/drv/spi/test/ospi_flash

diff --git a/packages/ti/drv/spi/test/ospi_flash/am64x/cached/r5_mpu.xs b/packages/ti/drv/spi/test/ospi_flash/am64x/cached/r5_mpu.xs
new file mode 100755 (executable)
index 0000000..0a60db4
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am64x/cached/r5_mpu.xs
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  ======== event_MPU.xs ========
+ *  MPU Settings for am64x device's Cortex-R5F
+ */
+
+/*
+ *  -------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable                                 | XN | AccPerm             | Mask |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 0  | 0x00000000   | 4GB  | T  | uncacheable, Shareable                    | F  | RW at PL 1 & PL 2   | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 1  | 0 (local TCM)| 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 2  | 0x41000000   | 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 3  | 0x41010000   | 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 4  | 0x41C00000   | 1MB  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ *  -------------------------------------------------------------------------------------------------------------
+ * | 5  | 0x70000000   | 8MB  | T  | MSMC Ram - Cachable                       | F  | RW at PL 1          | 0x0  |
+ *  -------------------------------------------------------------------------------------------------------------
+ * | 6  | 0x80000000   | 2GB  | T  | DDR - Strongly Ordered, Shareable         | F  | RW at PL 1 & PL 3   | 0x0  |
+ *  -------------------------------------------------------------------------------------------------------------
+ * | 7  | 0xA5000000   | 8MB  | T  | DDR (VRing Buffer) - Uncacheble           | F  | RW at PL 1 & PL 3   | 0x0  |
+ * |-------------------------------------------------------------------------------------------------------------|
+ * | 8  | 0x50000000   | 64MB | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1          | 0x0  |
+ *  --------------------------------------------------------------------------------------------------------------------
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ *       no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ *       regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+/* This entry covers the whole 32 bit memory range
+   Address: 0x00000000-0xffffffff */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* This entry covers the ATCM mapped to 0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = true;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers ATCM if mapped to 0x41000000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers BTCM if mapped to 0x41010000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers RAM0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers MSMC SRAM */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_8M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 0x3;          /* RW at PL1 & PL2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
+
+/* Ring Buffer uncached.... */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 3;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0xA5000000, MPU.RegionSize_8M, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(8, 0x50000000, MPU.RegionSize_64M, attrs);

diff --git a/packages/ti/drv/spi/test/ospi_flash/am64x/cached/sysbios_a53.cfg b/packages/ti/drv/spi/test/ospi_flash/am64x/cached/sysbios_a53.cfg
new file mode 100755 (executable)
index 0000000..d8fac07
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am64x/cached/sysbios_a53.cfg
@@ -0,0 +1,173 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2019
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*5;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 1000000000;
+BIOS.cpuFreq.hi = 0;
+
+var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
+Timer.intFreq.lo = 250000000;
+Timer.intFreq.hi = 0;
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/am64x/cached/sysbios_r5f.cfg b/packages/ti/drv/spi/test/ospi_flash/am64x/cached/sysbios_r5f.cfg
new file mode 100755 (executable)
index 0000000..9a5071b
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am64x/cached/sysbios_r5f.cfg
@@ -0,0 +1,215 @@
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2019
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x2000;
+
+/* Place vector table in separate section - by default this goes to 0x0 which
+ * is reserved by SBL */
+Program.sectMap[".vecs"] = "RESET_VECTORS";
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 0x4000;
+Task.common$.namedInstance = true;
+Task.common$.namedModule = true;
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*4;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 800000000;
+BIOS.cpuFreq.hi = 0;
+
+var coreId = java.lang.System.getenv("CORE");
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+if(coreId=="mcu1_0")
+{
+    Core.id = 0;
+    /* DM timer cfg */
+    Clock.timerId = 0;
+}
+if(coreId=="mcu1_1")
+{
+    Core.id = 1;
+    /* DM timer cfg */
+    Clock.timerId = 1;
+}
+if(coreId=="mcu2_0")
+{
+    Core.id = 0;
+    Clock.timerId = 2;
+}
+if(coreId=="mcu2_1")
+{
+    Core.id = 1;
+    Clock.timerId = 3;
+}
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#179 as per cslr_intr_r5fss0.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+Hwi.dummyIRQ                   = 179;
+
+var Reset = xdc.useModule("xdc.runtime.Reset");
+Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/am64x/non_cached/r5_mpu.xs b/packages/ti/drv/spi/test/ospi_flash/am64x/non_cached/r5_mpu.xs
new file mode 100755 (executable)
index 0000000..c6c9afd
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am64x/non_cached/r5_mpu.xs
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  ======== event_MPU.xs ========
+ *  MPU Settings for am64x device's Cortex-R5F
+ */
+
+/*
+ *  -------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable                                 | XN | AccPerm             | Mask |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 0  | 0x00000000   | 4GB  | T  | uncacheable, Shareable                    | F  | RW at PL 1 & PL 2   | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 1  | 0 (local TCM)| 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 2  | 0x41000000   | 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 3  | 0x41010000   | 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 4  | 0x41C00000   | 1MB  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ *  -------------------------------------------------------------------------------------------------------------
+ * | 5  | 0x70000000   | 8MB  | T  | MSMC Ram - Cachable                       | F  | RW at PL 1          | 0x0  |
+ *  -------------------------------------------------------------------------------------------------------------
+ * | 6  | 0x80000000   | 2GB  | T  | DDR - Strongly Ordered, Shareable         | F  | RW at PL 1 & PL 3   | 0x0  |
+ *  -------------------------------------------------------------------------------------------------------------
+ * | 7  | 0xA5000000   | 8MB  | T  | DDR (VRing Buffer) - Uncacheble           | F  | RW at PL 1 & PL 3   | 0x0  |
+ * |-------------------------------------------------------------------------------------------------------------|
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ *       no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ *       regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+/* This entry covers the whole 32 bit memory range
+   Address: 0x00000000-0xffffffff */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* This entry covers the ATCM mapped to 0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = true;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers ATCM if mapped to 0x41000000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers BTCM if mapped to 0x41010000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers RAM0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers MSMC SRAM */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_8M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 0x3;          /* RW at PL1 & PL2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
+
+/* Ring Buffer uncached.... */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 3;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0xA5000000, MPU.RegionSize_8M, attrs);

diff --git a/packages/ti/drv/spi/test/ospi_flash/am64x/non_cached/sysbios_a53.cfg b/packages/ti/drv/spi/test/ospi_flash/am64x/non_cached/sysbios_a53.cfg
new file mode 100755 (executable)
index 0000000..d8fac07
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am64x/non_cached/sysbios_a53.cfg
@@ -0,0 +1,173 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2019
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*5;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 1000000000;
+BIOS.cpuFreq.hi = 0;
+
+var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
+Timer.intFreq.lo = 250000000;
+Timer.intFreq.hi = 0;
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/am64x/non_cached/sysbios_r5f.cfg b/packages/ti/drv/spi/test/ospi_flash/am64x/non_cached/sysbios_r5f.cfg
new file mode 100755 (executable)
index 0000000..9a5071b
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am64x/non_cached/sysbios_r5f.cfg
@@ -0,0 +1,215 @@
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2019
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x2000;
+
+/* Place vector table in separate section - by default this goes to 0x0 which
+ * is reserved by SBL */
+Program.sectMap[".vecs"] = "RESET_VECTORS";
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 0x4000;
+Task.common$.namedInstance = true;
+Task.common$.namedModule = true;
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*4;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 800000000;
+BIOS.cpuFreq.hi = 0;
+
+var coreId = java.lang.System.getenv("CORE");
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+if(coreId=="mcu1_0")
+{
+    Core.id = 0;
+    /* DM timer cfg */
+    Clock.timerId = 0;
+}
+if(coreId=="mcu1_1")
+{
+    Core.id = 1;
+    /* DM timer cfg */
+    Clock.timerId = 1;
+}
+if(coreId=="mcu2_0")
+{
+    Core.id = 0;
+    Clock.timerId = 2;
+}
+if(coreId=="mcu2_1")
+{
+    Core.id = 1;
+    Clock.timerId = 3;
+}
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#179 as per cslr_intr_r5fss0.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+Hwi.dummyIRQ                   = 179;
+
+var Reset = xdc.useModule("xdc.runtime.Reset");
+Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/j7200/cached/r5_mpu.xs b/packages/ti/drv/spi/test/ospi_flash/j7200/cached/r5_mpu.xs
new file mode 100755 (executable)
index 0000000..ffbe804
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/j7200/cached/r5_mpu.xs
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  ======== event_MPU.xs ========
+ *  MPU Settings for J7200 device's Cortex-R5F
+ */
+
+/*
+ *  --------------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable                                        | XN | AccPerm             | Mask |
+ * |--------------------------------------------------------------------------------------------------------------------|
+ * | 0  | 0x00000000   | 4GB  | T  | uncacheable, Shareable                           | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 1  | 0 (local TCM)| 32K  | T  | Non-cacheable, Non-Shareable                     | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 2  | 0x41000000   | 32K  | T  | Non-cacheable, Non-Shareable                     | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 3  | 0x41010000   | 32K  | T  | Non-cacheable, Non-Shareable                     | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 4  | 0x41C00000   | 1MB  | T  | Write-Back, Write-Allocate, Non-Shareable        | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 5  | 0x70000000   | 8MB  | T  | MSMC - Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 6  | 0x80000000   | 2GB  | T  | DDR -  Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1 & PL 2   | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 7  | 0xA4000000   | 8MB  | T  | DDR (VRing Buffer) - Uncacheable, Shareable      | F  | RW at PL 1 & PL 2   | 0x0  |
+ * |----|---------------------|----|--------------------------------------------------|----|---------------------|------|
+ * | 8  | 0x50000000   | 64MB | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1          | 0x0  |
+ *  --------------------------------------------------------------------------------------------------------------------
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ *       no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ *       regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+/* This entry covers the whole 32 bit memory range
+   Address: 0x00000000-0xffffffff */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* This entry covers the ATCM mapped to 0 */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers ATCM if mapped to 0x41000000 */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers BTCM if mapped to 0x41010000 */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers RAM0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers MSMC SRAM */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 0x3;          /* RW at PL1 & PL2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
+
+/* Ring Buffer uncached.... */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 3;          /* RW at PL1 & PL2 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0xA4000000, MPU.RegionSize_8M, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(8, 0x50000000, MPU.RegionSize_64M, attrs);

diff --git a/packages/ti/drv/spi/test/ospi_flash/j7200/cached/sysbios_a72.cfg b/packages/ti/drv/spi/test/ospi_flash/j7200/cached/sysbios_a72.cfg
new file mode 100755 (executable)
index 0000000..1d721ce
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/j7200/cached/sysbios_a72.cfg
@@ -0,0 +1,173 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples do not use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*5;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 2000000000;
+BIOS.cpuFreq.hi = 0;
+
+var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
+Timer.intFreq.lo = 250000000;
+Timer.intFreq.hi = 0;
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/j7200/cached/sysbios_r5f.cfg b/packages/ti/drv/spi/test/ospi_flash/j7200/cached/sysbios_r5f.cfg
new file mode 100755 (executable)
index 0000000..3142138
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/j7200/cached/sysbios_r5f.cfg
@@ -0,0 +1,240 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x2000;
+
+/* Place vector table in separate section - by default this goes to 0x0 which
+ * is reserved by SBL */
+Program.sectMap[".vecs"] = "RESET_VECTORS";
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 0x4000;
+Task.common$.namedInstance = true;
+Task.common$.namedModule = true;
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples do not use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*4;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 1000000000;
+BIOS.cpuFreq.hi = 0;
+
+var coreId = java.lang.System.getenv("CORE");
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+if(coreId=="mcu1_0")
+{
+    Core.id = 0;
+    /* DM timer cfg */
+    Clock.timerId = 1;
+}
+if(coreId=="mcu1_1")
+{
+    Core.id = 1;
+    /* DM timer cfg */
+    Clock.timerId = 2;
+}
+
+/*  Using the main domain timer, instance 6 & 7. */
+/*  main domain instance 0 base address is 0x02400000 */
+if(coreId=="mcu2_0")
+{
+    Core.id = 0;
+    Clock.timerId = 0;
+    /* DMTimer #6 - in general, address is 0x024x0000 where x is timer # */
+    DMTimer.timerSettings[0].baseAddr = 0x02460000;
+    DMTimer.timerSettings[0].intNum = 295;
+}
+if(coreId=="mcu2_1")
+{
+    Core.id = 1;
+    Clock.timerId = 1;
+    /* DMTimer #7 - in general, address is 0x024x0000 where x is timer # */
+    DMTimer.timerSettings[1].baseAddr = 0x02470000;
+    DMTimer.timerSettings[1].intNum = 296;
+}
+
+/* Set base address of Vector Interrupt Manager */
+if((coreId=="mcu2_0") || (coreId=="mcu2_1"))
+{
+    var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+    Hwi.vimBaseAddress = 0x0ff80000;
+}
+
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#383 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+if((coreId=="mcu1_0") || (coreId=="mcu1_1"))
+{
+    Hwi.dummyIRQ                   = 383;
+}
+if((coreId=="mcu2_0") || (coreId=="mcu2_1"))
+{
+    Hwi.dummyIRQ                   = 511;
+}
+
+var Reset = xdc.useModule("xdc.runtime.Reset");
+Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/j7200/non_cached/r5_mpu.xs b/packages/ti/drv/spi/test/ospi_flash/j7200/non_cached/r5_mpu.xs
new file mode 100755 (executable)
index 0000000..946e865
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/j7200/non_cached/r5_mpu.xs
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  ======== event_MPU.xs ========
+ *  MPU Settings for J7200 device's Cortex-R5F
+ */
+
+/*
+ *  --------------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable                                        | XN | AccPerm             | Mask |
+ * |--------------------------------------------------------------------------------------------------------------------|
+ * | 0  | 0x00000000   | 4GB  | T  | uncacheable, Shareable                           | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 1  | 0 (local TCM)| 32K  | T  | Non-cacheable, Non-Shareable                     | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 2  | 0x41000000   | 32K  | T  | Non-cacheable, Non-Shareable                     | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 3  | 0x41010000   | 32K  | T  | Non-cacheable, Non-Shareable                     | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 4  | 0x41C00000   | 1MB  | T  | Write-Back, Write-Allocate, Non-Shareable        | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 5  | 0x70000000   | 8MB  | T  | MSMC - Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 6  | 0x80000000   | 2GB  | T  | DDR -  Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1 & PL 2   | 0x0  |
+ * |----|--------------|------|----|--------------------------------------------------|----|---------------------|------|
+ * | 7  | 0xA4000000   | 8MB  | T  | DDR (VRing Buffer) - Uncacheable, Shareable      | F  | RW at PL 1 & PL 2   | 0x0  |
+ *  --------------------------------------------------------------------------------------------------------------------
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ *       no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ *       regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+/* This entry covers the whole 32 bit memory range
+   Address: 0x00000000-0xffffffff */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* This entry covers the ATCM mapped to 0 */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers ATCM if mapped to 0x41000000 */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers BTCM if mapped to 0x41010000 */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers RAM0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers MSMC SRAM */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 0x3;          /* RW at PL1 & PL2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
+
+/* Ring Buffer uncached.... */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 3;          /* RW at PL1 & PL2 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0xA4000000, MPU.RegionSize_8M, attrs);

diff --git a/packages/ti/drv/spi/test/ospi_flash/j7200/non_cached/sysbios_a72.cfg b/packages/ti/drv/spi/test/ospi_flash/j7200/non_cached/sysbios_a72.cfg
new file mode 100755 (executable)
index 0000000..1d721ce
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/j7200/non_cached/sysbios_a72.cfg
@@ -0,0 +1,173 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples do not use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*5;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 2000000000;
+BIOS.cpuFreq.hi = 0;
+
+var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
+Timer.intFreq.lo = 250000000;
+Timer.intFreq.hi = 0;
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/j7200/non_cached/sysbios_r5f.cfg b/packages/ti/drv/spi/test/ospi_flash/j7200/non_cached/sysbios_r5f.cfg
new file mode 100755 (executable)
index 0000000..3142138
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/j7200/non_cached/sysbios_r5f.cfg
@@ -0,0 +1,240 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x2000;
+
+/* Place vector table in separate section - by default this goes to 0x0 which
+ * is reserved by SBL */
+Program.sectMap[".vecs"] = "RESET_VECTORS";
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 0x4000;
+Task.common$.namedInstance = true;
+Task.common$.namedModule = true;
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples do not use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*4;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 1000000000;
+BIOS.cpuFreq.hi = 0;
+
+var coreId = java.lang.System.getenv("CORE");
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+if(coreId=="mcu1_0")
+{
+    Core.id = 0;
+    /* DM timer cfg */
+    Clock.timerId = 1;
+}
+if(coreId=="mcu1_1")
+{
+    Core.id = 1;
+    /* DM timer cfg */
+    Clock.timerId = 2;
+}
+
+/*  Using the main domain timer, instance 6 & 7. */
+/*  main domain instance 0 base address is 0x02400000 */
+if(coreId=="mcu2_0")
+{
+    Core.id = 0;
+    Clock.timerId = 0;
+    /* DMTimer #6 - in general, address is 0x024x0000 where x is timer # */
+    DMTimer.timerSettings[0].baseAddr = 0x02460000;
+    DMTimer.timerSettings[0].intNum = 295;
+}
+if(coreId=="mcu2_1")
+{
+    Core.id = 1;
+    Clock.timerId = 1;
+    /* DMTimer #7 - in general, address is 0x024x0000 where x is timer # */
+    DMTimer.timerSettings[1].baseAddr = 0x02470000;
+    DMTimer.timerSettings[1].intNum = 296;
+}
+
+/* Set base address of Vector Interrupt Manager */
+if((coreId=="mcu2_0") || (coreId=="mcu2_1"))
+{
+    var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+    Hwi.vimBaseAddress = 0x0ff80000;
+}
+
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#383 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+if((coreId=="mcu1_0") || (coreId=="mcu1_1"))
+{
+    Hwi.dummyIRQ                   = 383;
+}
+if((coreId=="mcu2_0") || (coreId=="mcu2_1"))
+{
+    Hwi.dummyIRQ                   = 511;
+}
+
+var Reset = xdc.useModule("xdc.runtime.Reset");
+Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/j721e/cached/r5_mpu.xs b/packages/ti/drv/spi/test/ospi_flash/j721e/cached/r5_mpu.xs
new file mode 100755 (executable)
index 0000000..fef9e8b
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/j721e/cached/r5_mpu.xs
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  ======== event_MPU.xs ========
+ *  MPU Settings for J721E device's Cortex-R5F
+ */
+
+/*
+ *  ----------------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable                                          | XN | AccPerm             | Mask |
+ * |----------------------------------------------------------------------------------------------------------------------|
+ * | 0  | 0x00000000   | 4GB  | T  | uncacheable, Shareable                             | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|----------------------------------------------------|----|---------------------|------|
+ * | 1  | 0 (local TCM)| 32K  | T  | Non-cacheable, Non-Shareable                       | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|----------------------------------------------------|----|---------------------|------|
+ * | 2  | 0x41000000   | 32K  | T  | Non-cacheable, Non-shareable                       | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|----------------------------------------------------|----|---------------------|------|
+ * | 3  | 0x41010000   | 32K  | T  | Non-cacheable, Non-Shareable                       | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|----------------------------------------------------|----|---------------------|------|
+ * | 4  | 0x41C00000   | 1MB  | T  | Write-Back, Write-Allocate, Non-Shareable          | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|----------------------------------------------------|----|---------------------|------|
+ * | 5  | 0x70000000   | 8MB  | T  | MSMC - Write-Back, Write-Allocate, Non-Shareable   | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|----------------------------------------------------|----|---------------------|------|
+ * | 6  | 0x80000000   | 2GB  | T  | DDR - Write-Back, Write-Allocate, Non-Shareable    | F  | RW at PL 1 & PL 2   | 0x0  |
+ * |----|--------------|------|----|----------------------------------------------------|----|---------------------|------|
+ * | 7  | 0xAA000000   | 32MB | T  | DDR (VRing Buffer) - Uncacheable, Shareable        | F  | RW at PL 1 & PL 2   | 0x0  |
+ * |----|---------------------|----|----------------------------------------------------|----|---------------------|------|
+ * | 8  | 0x50000000   | 64MB | T  | OSPI flash memory - Cacheable                    | F  | RW at PL 1          | 0x0  |
+ *  --------------------------------------------------------------------------------------------------------------------
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ *       no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ *       regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+/* This entry covers the whole 32 bit memory range
+   Address: 0x00000000-0xffffffff */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* This entry covers the ATCM mapped to 0 */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers ATCM if mapped to 0x41000000 */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers BTCM if mapped to 0x41010000 */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers RAM0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers MSMC SRAM */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_8M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 0x3;          /* RW at PL1 & PL2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
+
+/* Ring Buffer uncached.... */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 3;          /* RW at PL1 & PL2 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0xAA000000, MPU.RegionSize_32M, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(8, 0x50000000, MPU.RegionSize_64M, attrs);

diff --git a/packages/ti/drv/spi/test/ospi_flash/j721e/sysbios_a72.cfg b/packages/ti/drv/spi/test/ospi_flash/j721e/cached/sysbios_a72.cfg
old mode 100644 (file)
new mode 100755 (executable)
similarity index 100%
rename from packages/ti/drv/spi/test/ospi_flash/j721e/sysbios_a72.cfg
rename to packages/ti/drv/spi/test/ospi_flash/j721e/cached/sysbios_a72.cfg

diff --git a/packages/ti/drv/spi/test/ospi_flash/j721e/sysbios_r5f.cfg b/packages/ti/drv/spi/test/ospi_flash/j721e/cached/sysbios_r5f.cfg
old mode 100644 (file)
new mode 100755 (executable)
similarity index 100%
rename from packages/ti/drv/spi/test/ospi_flash/j721e/sysbios_r5f.cfg
rename to packages/ti/drv/spi/test/ospi_flash/j721e/cached/sysbios_r5f.cfg

diff --git a/packages/ti/drv/spi/test/ospi_flash/j721e/r5_mpu.xs b/packages/ti/drv/spi/test/ospi_flash/j721e/non_cached/r5_mpu.xs
old mode 100644 (file)
new mode 100755 (executable)
similarity index 100%
rename from packages/ti/drv/spi/test/ospi_flash/j721e/r5_mpu.xs
rename to packages/ti/drv/spi/test/ospi_flash/j721e/non_cached/r5_mpu.xs

diff --git a/packages/ti/drv/spi/test/ospi_flash/j721e/non_cached/sysbios_a72.cfg b/packages/ti/drv/spi/test/ospi_flash/j721e/non_cached/sysbios_a72.cfg
new file mode 100755 (executable)
index 0000000..ffbfb0a
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/j721e/non_cached/sysbios_a72.cfg
@@ -0,0 +1,173 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*5;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 2000000000;
+BIOS.cpuFreq.hi = 0;
+
+var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
+Timer.intFreq.lo = 250000000;
+Timer.intFreq.hi = 0;
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/j721e/non_cached/sysbios_r5f.cfg b/packages/ti/drv/spi/test/ospi_flash/j721e/non_cached/sysbios_r5f.cfg
new file mode 100755 (executable)
index 0000000..76fcaf0
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/j721e/non_cached/sysbios_r5f.cfg
@@ -0,0 +1,253 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x2000;
+
+/* Place vector table in separate section - by default this goes to 0x0 which
+ * is reserved by SBL */
+Program.sectMap[".vecs"] = "RESET_VECTORS";
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 0x4000;
+Task.common$.namedInstance = true;
+Task.common$.namedModule = true;
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*4;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 1000000000;
+BIOS.cpuFreq.hi = 0;
+
+var coreId = java.lang.System.getenv("CORE");
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+if(coreId=="mcu1_0")
+{
+    Core.id = 0;
+    /* DM timer cfg */
+    Clock.timerId = 1;
+}
+if(coreId=="mcu1_1")
+{
+    Core.id = 1;
+    /* DM timer cfg */
+    Clock.timerId = 2;
+}
+if(coreId=="mcu2_0")
+{
+    Core.id = 0;
+    Clock.timerId = 0;
+    /* DMTimer #12 - in general, address is 0x024x0000 where x is timer # */
+    DMTimer.timerSettings[0].baseAddr = 0x024c0000;
+    DMTimer.timerSettings[0].intNum = 168;
+}
+if(coreId=="mcu2_1")
+{
+    Core.id = 1;
+    Clock.timerId = 1;
+    /* DMTimer #13 - in general, address is 0x024x0000 where x is timer # */
+    DMTimer.timerSettings[1].baseAddr = 0x024d0000;
+    DMTimer.timerSettings[1].intNum = 169;
+}
+if(coreId=="mcu3_0")
+{
+    Core.id = 0;
+    Clock.timerId = 2;
+    /* DMTimer #14 - in general, address is 0x024x0000 where x is timer # */
+    DMTimer.timerSettings[2].baseAddr = 0x024e0000;
+    DMTimer.timerSettings[2].intNum = 170;
+}
+if(coreId=="mcu3_1")
+{
+    Core.id = 1;
+    Clock.timerId = 3;
+    /* DMTimer #15 - in general, address is 0x024x0000 where x is timer # */
+    DMTimer.timerSettings[3].baseAddr = 0x024f0000;
+    DMTimer.timerSettings[3].intNum = 171;
+}
+
+/* Set base address of Vector Interrupt Manager */
+if((coreId=="mcu2_0") || (coreId=="mcu2_1") || (coreId=="mcu3_0") || (coreId=="mcu3_1"))
+{
+    var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+    Hwi.vimBaseAddress = 0x0ff80000;
+}
+
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#383 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+if((coreId=="mcu1_0") || (coreId=="mcu1_1"))
+{
+    Hwi.dummyIRQ                   = 383;
+}
+if((coreId=="mcu2_0") || (coreId=="mcu2_1") || (coreId=="mcu3_0") || (coreId=="mcu3_1"))
+{
+    Hwi.dummyIRQ                   = 511;
+}
+
+var Reset = xdc.useModule("xdc.runtime.Reset");
+Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+    xdc.print("Loading configuration update " + cfgUpdate);
+    xdc.loadCapsule(cfgUpdate);
+}

diff --git a/packages/ti/drv/spi/test/ospi_flash/makefile b/packages/ti/drv/spi/test/ospi_flash/makefile
old mode 100644 (file)
new mode 100755 (executable)
index aa5c616..470edd1
--- a/packages/ti/drv/spi/test/ospi_flash/makefile
+++ b/packages/ti/drv/spi/test/ospi_flash/makefile
@@ -23,11 +23,12 @@ ifeq ($(SOC),$(filter $(SOC), am65xx))
 XDC_CFG_FILE_mpu1_0 = ./$(SOC)/ospiFlashTest_a53.cfg
 XDC_CFG_FILE_mcu1_0 = ./$(SOC)/ospiFlashTest_r5.cfg
 endif
 XDC_CFG_FILE_mpu1_0 = ./$(SOC)/ospiFlashTest_a53.cfg
 XDC_CFG_FILE_mcu1_0 = ./$(SOC)/ospiFlashTest_r5.cfg
 endif

-ifeq ($(SOC),$(filter $(SOC), j7200 am64x))
-XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
-endif
-ifeq ($(SOC),$(filter $(SOC), j721e))
-XDC_CFG_FILE_$(CORE) = ./$(SOC)/sysbios_$(ISA).cfg
+ifeq ($(SOC),$(filter $(SOC), j7200 j721e am64x))
+    ifeq ($(CACHE), enable)
+        XDC_CFG_FILE_$(CORE) = ./$(SOC)/cached/sysbios_$(ISA).cfg
+    else
+        XDC_CFG_FILE_$(CORE) = ./$(SOC)/non_cached/sysbios_$(ISA).cfg
+    endif

 endif
 
 endif
 endif
 
 endif


@@ -48,43 +49,85 @@ endif
 # need to be included for this component
 INCLUDE_EXTERNAL_INTERFACES = pdk $(EXTERNAL_INTERFACES)
 
 # need to be included for this component
 INCLUDE_EXTERNAL_INTERFACES = pdk $(EXTERNAL_INTERFACES)
 

-ifeq ($(DMA), enable)
-    ifeq ($(SMP), enable)
-        #Name of the directory created under packages/ti/binary/
-        APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_SMP_TestApp
-        # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
-        LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_$(BOARD)_$(CORE)_SMP_TestApp
-        ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200))
-            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_SMP_TestApp_$(CORE)
+ifeq ($(CACHE), enable)
+    ifeq ($(DMA), enable)
+        ifeq ($(SMP), enable)
+            #Name of the directory created under packages/ti/binary/
+            APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_SMP_Cache_TestApp
+            # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_$(BOARD)_$(CORE)_SMP_Cache_TestApp
+            ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200))
+                LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_SMP_Cache_TestApp_$(CORE)
+            endif
+
+        else
+            #Name of the directory created under packages/ti/binary/
+            APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_Cache_TestApp
+            # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_Cache_$(BOARD)_$(CORE)TestApp
+            ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200))
+                LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_Cache_TestApp_$(CORE)
+            endif

         endif
 
         endif
 

+    COMP_LIST_COMMON += spi_dma
+    #COMP_LIST_COMMON += spi_dma_profile
+    CFLAGS_SPI_DMA    = -DSPI_DMA_ENABLE 

     else
     else

-        #Name of the directory created under packages/ti/binary/
-        APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_TestApp
-        # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
-        LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_$(BOARD)_$(CORE)TestApp
-        ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200))
-            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_TestApp_$(CORE)
+        ifeq ($(SMP), enable)
+            APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_SMP_Cache_TestApp
+            # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_$(BOARD)_$(CORE)_SMP_Cache_TestApp
+        else
+            APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_Cache_TestApp
+            # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Cache_$(BOARD)_$(CORE)TestApp

         endif
         endif

+
+    COMP_LIST_COMMON += spi 
+    #COMP_LIST_COMMON += spi_profile
+    CFLAGS_SPI_DMA    =

     endif
 
     endif
 

-COMP_LIST_COMMON += spi_dma
-#COMP_LIST_COMMON += spi_dma_profile
-CFLAGS_SPI_DMA    = -DSPI_DMA_ENABLE 

 else
 else

-    ifeq ($(SMP), enable)
-        APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_SMP_TestApp
-        # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
-        LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_$(BOARD)_$(CORE)_SMP_TestApp
+    ifeq ($(DMA), enable)
+        ifeq ($(SMP), enable)
+            #Name of the directory created under packages/ti/binary/
+            APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_SMP_TestApp
+            # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_$(BOARD)_$(CORE)_SMP_TestApp
+            ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200))
+                LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_SMP_TestApp_$(CORE)
+            endif
+
+        else
+            #Name of the directory created under packages/ti/binary/
+            APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_TestApp
+            # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_$(BOARD)_$(CORE)TestApp
+            ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200))
+                LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_Dma_TestApp_$(CORE)
+            endif
+        endif
+
+    COMP_LIST_COMMON += spi_dma
+    #COMP_LIST_COMMON += spi_dma_profile
+    CFLAGS_SPI_DMA    = -DSPI_DMA_ENABLE 

     else
     else

-        APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_TestApp
-        # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
-        LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_$(BOARD)_$(CORE)TestApp
-    endif
+        ifeq ($(SMP), enable)
+            APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_SMP_TestApp
+            # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_$(BOARD)_$(CORE)_SMP_TestApp
+        else
+            APP_NAME = OSPI$(OSPI_OS_TESTPREFIX)_Flash_TestApp
+            # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+            LOCAL_APP_NAME =  OSPI$(OSPI_OS_TESTPREFIX)_Flash_$(BOARD)_$(CORE)TestApp
+        endif

 
 

-COMP_LIST_COMMON += spi 
-#COMP_LIST_COMMON += spi_profile
-CFLAGS_SPI_DMA    =
+    COMP_LIST_COMMON += spi 
+    #COMP_LIST_COMMON += spi_profile
+    CFLAGS_SPI_DMA    =
+    endif

 endif
 
 PACKAGE_SRCS_COMMON = .
 endif
 
 PACKAGE_SRCS_COMMON = .