PDK-5115: Board: Updated gpio mapping for am64x expansion header test
PDK-6940: Board: Updated gpio mapping for am64x evm boot switch test
PDK-6953: Board: Updated automation header boot values for am64x evm
PDK-6951: Board: Updated current monitor calibration values for am64x evm
PDK-5151: Board: Updated the oled display test for am64x evm
- OLED display test validated on EVM HW
- Updated the file names to be platform independent
- OLED display test validated on EVM HW
- Updated the file names to be platform independent
PDK-6952: Board: Updated led diagnostic test for am64x evm
- User LED and industrial LED diag tests are validated on EVM HW
- User LED and industrial LED diag tests are validated on EVM HW
mcspi: am64x: add RAT offset for M4F
Add RAT offset to baseaddress of MCSPI registers.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Add RAT offset to baseaddress of MCSPI registers.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
SPI : Add check for return value of MCSPI_dmaConfig in MCSPI_open_v1
- Check for return value of MCSPI_dmaConfig was missing
- Any error in UDMA config was missed
Signed-off-by: Don Dominic <a0486429@ti.com>
- Check for return value of MCSPI_dmaConfig was missing
- Any error in UDMA config was missed
Signed-off-by: Don Dominic <a0486429@ti.com>
uart: test: use main uart0 for am64x tests
Uart test does not have support for MCU UART0, this is a problem
when running on M4 core as MCU UART0 gets assigned as the default instance.
For now use the main uart0 for all cores of am64x tests.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Uart test does not have support for MCU UART0, this is a problem
when running on M4 core as MCU UART0 gets assigned as the default instance.
For now use the main uart0 for all cores of am64x tests.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
PDK-6948: Board: Updated am64x evm pinmux
- Enabled Rx active for FSI-Rx lines
- Corrected Board_pinmuxSetReg for proper register offset access
- Enabled Rx active for FSI-Rx lines
- Corrected Board_pinmuxSetReg for proper register offset access
Sciclient: AM64x: support M4F in launch.js
Initialize M4F in the launch.js script.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Initialize M4F in the launch.js script.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
SPI : AM64x Bringup : Fix Issues with MCSPI multi-channel test on mpu1_0
- On mpu1_0, Multi-channel tests was faling during opening the second channel
- In mcspi inti only the default channel (ch0) object was reset
- Updated 'MCSPI_init_v1' to reset all 4 mcspi channels
- Non-DMA multichannel test are working fine on AM64x mpu1_0 with this fix
Signed-off-by: Don Dominic <a0486429@ti.com>
- On mpu1_0, Multi-channel tests was faling during opening the second channel
- In mcspi inti only the default channel (ch0) object was reset
- Updated 'MCSPI_init_v1' to reset all 4 mcspi channels
- Non-DMA multichannel test are working fine on AM64x mpu1_0 with this fix
Signed-off-by: Don Dominic <a0486429@ti.com>
AM64x OSPI Bringup
Removed SIM_BUILD.
Semantic corrections.
WAs added for PDK-8724 and PDK-8607.
Order of tests changed to 166MHz then 133MHz.
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Removed SIM_BUILD.
Semantic corrections.
WAs added for PDK-8724 and PDK-8607.
Order of tests changed to 166MHz then 133MHz.
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
osal: return correct test result from hwi test
OSAL_hwi_test unconditionally returns true, fix it by returning
actual result.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
OSAL_hwi_test unconditionally returns true, fix it by returning
actual result.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
[PDK-8761] AM64x UART UT : Workaround for issues with DMA mode tests on R5F
- Reordered the testcases such that the following tests runs before UART timeout test(UT4/5)
- UART simultaneous read write test (BIOS only test)
- UART TX/RX FIFO trigger level test
- Else the above testcases (UT10/12) was hanging
- Also intermittent hang was seen in the following testcases
- UART DMA RX error test, enter a break (UT6)
- UART DMA read write cancel test, enter less than 16 chars (UT8)
- This commit is a workaround for the above issues.
- PDK-8761 to track, root-cause and fix this issue
Signed-off-by: Don Dominic <a0486429@ti.com>
- Reordered the testcases such that the following tests runs before UART timeout test(UT4/5)
- UART simultaneous read write test (BIOS only test)
- UART TX/RX FIFO trigger level test
- Else the above testcases (UT10/12) was hanging
- Also intermittent hang was seen in the following testcases
- UART DMA RX error test, enter a break (UT6)
- UART DMA read write cancel test, enter less than 16 chars (UT8)
- This commit is a workaround for the above issues.
- PDK-8761 to track, root-cause and fix this issue
Signed-off-by: Don Dominic <a0486429@ti.com>
board: am64x_evm: add pinmux support for M4F
Add RAT configuration offset for doing pinmux from M4F.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Add RAT configuration offset for doing pinmux from M4F.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
PDK-8760: IPC: Examples: AM64X: Use default RAT config for M4F
The default RAT config for M4F (located in csl/arch/m4/startup/startup.c)
already contains the mapping for the mailbox registers, as well
as other needed mappings. Update the IPC M4F test apps to
use the default RAT config instead of a custom RAT config.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
The default RAT config for M4F (located in csl/arch/m4/startup/startup.c)
already contains the mapping for the mailbox registers, as well
as other needed mappings. Update the IPC M4F test apps to
use the default RAT config instead of a custom RAT config.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
enable appimage gen for pcie tests
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
AM64x: UDMA UT: Build Fix
- Add utilsCopyVecsToAtcm SECTION to linker file
- This fixes the linking error with udma_unit_testapp om AM64x nmcu1_0/mcu1_1/mcu2_0/mcu2_1
Signed-off-by: Don Dominic <a0486429@ti.com>
- Add utilsCopyVecsToAtcm SECTION to linker file
- This fixes the linking error with udma_unit_testapp om AM64x nmcu1_0/mcu1_1/mcu2_0/mcu2_1
Signed-off-by: Don Dominic <a0486429@ti.com>
SBL: Handle different size R5 ATCM/BTCM on different SoCs
Updates SBL to check for reported ATCM/BTCM memory sizes
for the R5 for each device, instead of using hard-coded
sizes with compile tokens.
Initialization of ATCM/BTCM memories can then take place
with the proper size, for each situation.
Tested-by: Jonathan Bergsagel <jbergsagel@ti.com>
Updates SBL to check for reported ATCM/BTCM memory sizes
for the R5 for each device, instead of using hard-coded
sizes with compile tokens.
Initialization of ATCM/BTCM memories can then take place
with the proper size, for each situation.
Tested-by: Jonathan Bergsagel <jbergsagel@ti.com>
fixed am64x linker cmd file for sysbios
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
PDK-6948: Board: Fix for OSPI PHY tuning failure on AM64x EVM
AM64x: Sciclient: Update non-Secure host for A53
- BoardCfg is using TISCI_HOST_ID_A53_2 (12U)
- Hence, to allign using SCICLIENT_CONTEXT_A53_NONSEC_1
Signed-off-by: Don Dominic <a0486429@ti.com>
- BoardCfg is using TISCI_HOST_ID_A53_2 (12U)
- Hence, to allign using SCICLIENT_CONTEXT_A53_NONSEC_1
Signed-off-by: Don Dominic <a0486429@ti.com>
sciclient: update AM64x launch.js
Mask the boot mode check with 0x78. No-boot mode needs bit[6-3]=1. Bit7 is
don't care.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Mask the boot mode check with 0x78. No-boot mode needs bit[6-3]=1. Bit7 is
don't care.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Revert "Board: Disabled sciclient init in am64x evm board library"
This reverts commit 1db8ad0569960c7370bbe8c96af6f52f40201152.
launch.js is functional now for AM64x.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
This reverts commit 1db8ad0569960c7370bbe8c96af6f52f40201152.
launch.js is functional now for AM64x.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Enabling launch.js and DDR init
Enabling AM64x luanch.js and DDR init
Should be used with GEL updates
Signed-off-by: Goswami <piyali_g@ti.com>
Enabling AM64x luanch.js and DDR init
Should be used with GEL updates
Signed-off-by: Goswami <piyali_g@ti.com>
PDK-6948: Board: Added mmc1 loopback clock config for am64x evm pinmux
- Communication with SD card is failing without enabling the pinmux for
MMC1_CLKLB pin
- Communication with SD card is failing without enabling the pinmux for
MMC1_CLKLB pin
AM64x launch.js updates
Updates to run SYSFW on AM64 silicon
Signed-off-by: Goswami <piyali_g@ti.com>
Updates to run SYSFW on AM64 silicon
Signed-off-by: Goswami <piyali_g@ti.com>
SBL: AM64x: UART clock updates for silicon
Update UART input clock values for actual silicon.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Update UART input clock values for actual silicon.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
[PDK-8728] UDMA: Update UDMA Resource Allocation for c7x-host-emu
- For c7x-host-emu:
- Reserve 16 DRU channels &
- 32 Free Rings(in allignment with current BoardCfg for C7x) - Since there is Indirect TR usecase with dmautils
- DMSC/SCICLIENT is NA for host emu
- Hence querying from the BoardCfg is not supported.
- Therefore updating the sciclient_dummy.c file to return these ranges for c7x-host-emu
Signed-off-by: Don Dominic <a0486429@ti.com>
- For c7x-host-emu:
- Reserve 16 DRU channels &
- 32 Free Rings(in allignment with current BoardCfg for C7x) - Since there is Indirect TR usecase with dmautils
- DMSC/SCICLIENT is NA for host emu
- Hence querying from the BoardCfg is not supported.
- Therefore updating the sciclient_dummy.c file to return these ranges for c7x-host-emu
Signed-off-by: Don Dominic <a0486429@ti.com>
PDK-6948: Board: Added mmr unlock after pinmux config in am64x evm board
lib
lib
PDK-6948: Board: Updated am64x evm board uart init
- Updaed board UART init to control the UART instance
through board init params.
- Updaed board UART init to control the UART instance
through board init params.
PDK-6948: Board: Added mmr unlock for am64x evm pinmux
Sciclient: AM64x silicon updates
AM64x Silicon bringup updates
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
AM64x Silicon bringup updates
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Board: Disabled sciclient init in am64x evm board library
- sciclient init is disabled in am64x board init function to make the
board init execution independent of sciclient.
This will be enabled after sciclient is validated and stable
with SoC.
- sciclient init is disabled in am64x board init function to make the
board init execution independent of sciclient.
This will be enabled after sciclient is validated and stable
with SoC.
Board: Remoaved SIM_BUILD configurations in am64x board
- Conifgurations enabled using SIM_BUILD macro are used for QT/Zebu
testing. Need to disable these configs for testing on EVM.
- Conifgurations enabled using SIM_BUILD macro are used for QT/Zebu
testing. Need to disable these configs for testing on EVM.
PDK-8458: sciclient: update AM64x RAT macro name
Since the secure proxy config is used by all cores in AM64x, the RAT
macro name should not be limited to M4F. The RAT offset should be
applied only for M4F applications.
Just renaming macros. No functional change.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Since the secure proxy config is used by all cores in AM64x, the RAT
macro name should not be limited to M4F. The RAT offset should be
applied only for M4F applications.
Just renaming macros. No functional change.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Revert "BOARD: Enabling Board_moduleClock() only for mpu & mcu cores (not m4f)"
This reverts commit 5d48db09b6a9c6b2280c3da95fab924228a2906f.
Board_moduleClockEnable was previously disabled for M4F since it was crashing.
The crash is fixed after RAT configuration was enabled for sec proxy register
regions.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
This reverts commit 5d48db09b6a9c6b2280c3da95fab924228a2906f.
Board_moduleClockEnable was previously disabled for M4F since it was crashing.
The crash is fixed after RAT configuration was enabled for sec proxy register
regions.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
PDK-8458: sciclient: update secure proxy config for AM64x
The M4F core on AM64x needs RAT to access the secure proxy registers.
The offset of 0x60000000 is used to convert from MAIN domain memory
map to M4FSS memory map.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
The M4F core on AM64x needs RAT to access the secure proxy registers.
The offset of 0x60000000 is used to convert from MAIN domain memory
map to M4FSS memory map.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
am64x: align BIOS and XDC version with other devices
Changing to below versions
BIOS_VERSION=6_83_00_18
XDC_VERSION=3_61_03_29_core
Important fix related to A53 interrupts is included in 6_83 version.
More info in SYSBIOS-1409.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Changing to below versions
BIOS_VERSION=6_83_00_18
XDC_VERSION=3_61_03_29_core
Important fix related to A53 interrupts is included in 6_83 version.
More info in SYSBIOS-1409.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Static Analysis fixes for Sciclient
Static Analysis fixes for Sciclient
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Static Analysis fixes for Sciclient
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 years agoBoard: Removed compile error based on core check in am64x evm board cfg REL.CORESDK.07.01.00.40
Board: Removed compile error based on core check in am64x evm board cfg
3 years agoPDK-8305: Updated am64x evm board uart config to map to proper SoC instance REL.CORESDK.07.01.00.39
PDK-8305: Updated am64x evm board uart config to map to proper SoC instance
- Removed the additional configurations done for UART and I2C for
SoC domain switch which are not needed on AM64x
- Removed the additional configurations done for UART and I2C for
SoC domain switch which are not needed on AM64x
Sciclient: Fixes for the firmware boot applications
Fixes to add support firmware boot for J721e
Fixes: PDK-8579
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fixes to add support firmware boot for J721e
Fixes: PDK-8579
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Sciclient_firmware_boot: Update for the test case for the firmware boot
Update for the Firmware boot test app to run on AM65x and J7200
Fixes: PDK-8602
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Update for the Firmware boot test app to run on AM65x and J7200
Fixes: PDK-8602
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
PDK-8578: Fix for sciclient_fw_test example
Fix for the example to run on J721e, J7200 and AM65xx
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fix for the example to run on J721e, J7200 and AM65xx
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 years agoPDK-8155: IPC examples: Call Sciclient_init before Sciserver_tirtosInit REL.CORESDK.07.01.00.36 REL.CORESDK.07.01.00.37 REL.CORESDK.07.01.00.38
PDK-8155: IPC examples: Call Sciclient_init before Sciserver_tirtosInit
Sciclient_init should be called before Sciserver_tirtosInit in
the init sequence.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Sciclient_init should be called before Sciserver_tirtosInit in
the init sequence.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
mcspi example fix for release mode
- after adding sync between the master and slave delay required in
master app for the release binary to make sure the slave is ready before
master initiates the transfer.
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- after adding sync between the master and slave delay required in
master app for the release binary to make sure the slave is ready before
master initiates the transfer.
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
[BugFix] PDK-7945: OSPI Flash Application failing on J721E
fixed ospi rtos example for j721e
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
fixed ospi rtos example for j721e
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
build fixed for baremetal build
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Sciclient: documentation and header update
Update for the documentation and header
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Update for the documentation and header
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
sdr_test: Update j721e linker file to not load to ATCM
This fixes issue observed when performing sbl mmcsd booting
of the sdr_test appimage.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
This fixes issue observed when performing sbl mmcsd booting
of the sdr_test appimage.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
fixed mcspi example for j721e and j7200
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
PDK-8495: QoS settings disabled for SBL boot
- Enabled the QoS settings for Non-HS
- For HS issue, we can track this seperately
- Also used CSLR register write macro instead of
writel which was not using the volatile keyward for
reg access - but not sure if this caused any issues
- The R5F QOS is still disabled as this is causing the
DRU testcases to hang
Signed-off-by: Sivaraj R <sivaraj@ti.com>
- Enabled the QoS settings for Non-HS
- For HS issue, we can track this seperately
- Also used CSLR register write macro instead of
writel which was not using the volatile keyward for
reg access - but not sure if this caused any issues
- The R5F QOS is still disabled as this is causing the
DRU testcases to hang
Signed-off-by: Sivaraj R <sivaraj@ti.com>
PDK-8569: Board: Updated Uniflash host tool to avoid platform dependency for sysfw load
- Uniflash host tool depends on the platform name in the Uniflash flash programmer
binary file name to decide whether system firmware autoload is needed.
This is causing the Uniflash host tool update for every new platform with system firmware dependency.
Updated the host tool to load system firmware if the file exists in flash programmer folder
instead of depending on the platform name.
- Uniflash host tool depends on the platform name in the Uniflash flash programmer
binary file name to decide whether system firmware autoload is needed.
This is causing the Uniflash host tool update for every new platform with system firmware dependency.
Updated the host tool to load system firmware if the file exists in flash programmer folder
instead of depending on the platform name.
Board: Added ospi phy tuning data binary file
PDK-8567: Board: Fix for board flash open performance issue on j7200
- Board flash open function is taking more CPU cycles which is caused
by flash register write to configure hybrid sector configuration.
Updated the code to check for the default setting and write only
if hybrid sector config needs a change.
- Board flash open function is taking more CPU cycles which is caused
by flash register write to configure hybrid sector configuration.
Updated the code to check for the default setting and write only
if hybrid sector config needs a change.
Sysfw Public doc updates
Public docs update based on review feedback
Fixes: SYSFW-4215
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Public docs update based on review feedback
Fixes: SYSFW-4215
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 years agoPDK-8305: Board: Updated am64x diag tests to map with proper driver instances REL.CORESDK.07.01.02.03 REL.CORESDK.07.01.02.04
PDK-8305: Board: Updated am64x diag tests to map with proper driver instances
PDK-5118: Board: Enabled I2C init functions in am64x board library
Added wwdt multicore back to build with lastcore change
PDK-8511: sciserver: set GTC to 200MHz
This is a temporary hack. The SPL expects the GTC to be configured at
200MHz. Since the default GTC frequency is 250MHz, it needs to be
reconfigured to 200MHz to align with SPL.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
This is a temporary hack. The SPL expects the GTC to be configured at
200MHz. Since the default GTC frequency is 250MHz, it needs to be
reconfigured to 200MHz to align with SPL.
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
[PDK-8391] UDMA UT : Fix issues with unit_testapp on J7200 mcu2_1 and mcu2_0
- Update Linker File
- Else Test was stuck in Sciclient_Service in Sciclient_init
Signed-off-by: Don Dominic <a0486429@ti.com>
- Update Linker File
- Else Test was stuck in Sciclient_Service in Sciclient_init
Signed-off-by: Don Dominic <a0486429@ti.com>
PDK-8502: Board: Fix for Uniflash flash programmer failure in UART load mode
- Uniflash flash programmer is hanging in board init with latest sciclient
driver due to dependency on system firmware.
Updated the flash programmer init sequence to call board init after
loading system firmware.
DMA mode is not functional which is disabled in this update.
- Uniflash flash programmer is hanging in board init with latest sciclient
driver due to dependency on system firmware.
Updated the flash programmer init sequence to call board init after
loading system firmware.
DMA mode is not functional which is disabled in this update.
[PDK-8515] UDMA UT : Enable MCU NAVSS HC Block Copy Testcases on J7200 mcu1_0
- This change somehow got missed from 9b50f64b1208c54c7de3105f7027815bf77d120a
Signed-off-by: Don Dominic <a0486429@ti.com>
- This change somehow got missed from 9b50f64b1208c54c7de3105f7027815bf77d120a
Signed-off-by: Don Dominic <a0486429@ti.com>
fixed mmcsd tests
- removed the mcu1_1 build for the mmcsd
- fixed the mmcsd tests for mcu2_1 and mcu3_1 cores
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- removed the mcu1_1 build for the mmcsd
- fixed the mmcsd tests for mcu2_1 and mcu3_1 cores
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
[PDK-8515] UDMA UT : Enable HC Block Copy Testcases
- As per BoardCfg, there no HC Block Copy Channel assigned for any core.
- In this case, use the resource assigned for HC RX/TX channels
- to test various HC Block Copy testcases.
- This is with the assumption that, the range of this resources are same
- for both RX and TX High Capacity channels
- Also remove macors for START of resource, since its no longer used to override rm prms.
Signed-off-by: Don Dominic <a0486429@ti.com>
- As per BoardCfg, there no HC Block Copy Channel assigned for any core.
- In this case, use the resource assigned for HC RX/TX channels
- to test various HC Block Copy testcases.
- This is with the assumption that, the range of this resources are same
- for both RX and TX High Capacity channels
- Also remove macors for START of resource, since its no longer used to override rm prms.
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-8492] RM : Regenerate boardCfg and Sciclient_ccs_init
- Was not on tip of rm_pal_hal while generated the binaries last time in commit 47856c4a40c531039165d8da2c292a725d579ba1
- Hence regenerating after rebasing to tip of rm_pm_hal
Signed-off-by: Don Dominic <a0486429@ti.com>
- Was not on tip of rm_pal_hal while generated the binaries last time in commit 47856c4a40c531039165d8da2c292a725d579ba1
- Hence regenerating after rebasing to tip of rm_pm_hal
Signed-off-by: Don Dominic <a0486429@ti.com>
Sciclient debug build enabling
Sciclient debug linker file changes to enable build
Fixes: PDK-8440
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Sciclient debug linker file changes to enable build
Fixes: PDK-8440
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
[Bug Fix]Fixed issue with I2C tests failing on Main Domain R5 Cores
- Issue:
- Tests fails on Main Domain MCU2_1 and MCU3_1 cores
- Root-cause:
- Due to recent RM changes, interrupts reserved from Interrupt Routers for these core are changed
- This was making TC time-out as no interrupts were triggered
- Resolution:
- Assign interrupts as per new RM i.e. +128 for MCUx_1 cores from Main Domain
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Issue:
- Tests fails on Main Domain MCU2_1 and MCU3_1 cores
- Root-cause:
- Due to recent RM changes, interrupts reserved from Interrupt Routers for these core are changed
- This was making TC time-out as no interrupts were triggered
- Resolution:
- Assign interrupts as per new RM i.e. +128 for MCUx_1 cores from Main Domain
Signed-off-by: Vivek Dhande <a0132295@ti.com>
UDMA UT: Enable Ring Monitor Testcases
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-8492] RM : Fix UDMA Ring Monitor Issues with mcu1_0
- Removed MCU NAVSS Ring monitor resource entry for mcu1_0 Non Secure context
- Updated for both J721E and J7200
- The fixes the issues with Ring Monitor Config on mcu1_0
- SYSFW do not support multiple overlapping ranges in the RA monitor
due to the limitation to support both the DM and DMSC to need to have access to the registers.
So only one host can have exclusive access to the range of ring monitors.
- sysfw force the MCU1_0 to secure in the re-arch, so removing the non-secure and keep the secure.
Signed-off-by: Don Dominic <a0486429@ti.com>
- Removed MCU NAVSS Ring monitor resource entry for mcu1_0 Non Secure context
- Updated for both J721E and J7200
- The fixes the issues with Ring Monitor Config on mcu1_0
- SYSFW do not support multiple overlapping ranges in the RA monitor
due to the limitation to support both the DM and DMSC to need to have access to the registers.
So only one host can have exclusive access to the range of ring monitors.
- sysfw force the MCU1_0 to secure in the re-arch, so removing the non-secure and keep the secure.
Signed-off-by: Don Dominic <a0486429@ti.com>
Board: Diagnostic stress test update to resolve build issues
Board: Disabled the macro PDK_RAW_BOOT for tpr12 evm diag release profile
- PDK_RAW_BOOT is enabled for tpr12 during inital testing. Reverting it
to default and release mode diag binaries should be tested with sbl boot flow.
- PDK_RAW_BOOT is enabled for tpr12 during inital testing. Reverting it
to default and release mode diag binaries should be tested with sbl boot flow.
Sciclient: CCS_Init application added cache options
Sciclient ccs init application updated with cache operations for writing the board config data
Fixes: PDK-8496
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Sciclient ccs init application updated with cache operations for writing the board config data
Fixes: PDK-8496
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
edma: use CSL cache line size definitions and macros
Replace local cache line size definitions and macros with the CSL ones
Signed-off-by: Eric Ruei <e-ruei1@ti.com>
Replace local cache line size definitions and macros with the CSL ones
Signed-off-by: Eric Ruei <e-ruei1@ti.com>
PDK-5002: Board: Updated the name for csirx diagnostic test
[Bug Fix] PDK-8469: mcspi master test crashes in interrupt mode
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Migrating to SYSFW version v2020.08b
Migrating to v2020.08b
Migrating to v2020.08b
sciserver: add sync semaphore to user message tasks
A semaphore is added inside the high and low priority user message task.
It prevents the low priority task processing stale message response from
high priority task during message forwarding.
Both the high and low priority tasks can forward message to TIFS. But
DM2DMSC response path is shared. The reading of the RX thread in
Sciclient_serviceSecureProxy() is not protected by the critical section.
The DM's high priority task could forward a message to TIFS before low
priority reads the response. Then the high priority task processes the
response in the DM2DMSC rxThread. The issue occurs when the low priority
thread would process the same stale response message from high priority
task.
The sync semaphore serializes incoming messages to DM and prevents the
above scenario from occurring.
Fixes: PDK-8312 #integrate-and-build
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
A semaphore is added inside the high and low priority user message task.
It prevents the low priority task processing stale message response from
high priority task during message forwarding.
Both the high and low priority tasks can forward message to TIFS. But
DM2DMSC response path is shared. The reading of the RX thread in
Sciclient_serviceSecureProxy() is not protected by the critical section.
The DM's high priority task could forward a message to TIFS before low
priority reads the response. Then the high priority task processes the
response in the DM2DMSC rxThread. The issue occurs when the low priority
thread would process the same stale response message from high priority
task.
The sync semaphore serializes incoming messages to DM and prevents the
above scenario from occurring.
Fixes: PDK-8312 #integrate-and-build
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
PDK-7718: Board: Fix for hyperflash stability issue at higher clock
- Hyperflash operations are not stable at higher frequency on j7200 evm.
Hyperbus datasheet recommends to enable the controller after clocks are stable.
But hyperbus controller will be active while PLLs are being configured which is
causing wrong MDLL code some times resulting data write failure.
Resetting the hyperbus controller in board flash open to resync with PLL
clocks configured.
- Hyperflash operations are not stable at higher frequency on j7200 evm.
Hyperbus datasheet recommends to enable the controller after clocks are stable.
But hyperbus controller will be active while PLLs are being configured which is
causing wrong MDLL code some times resulting data write failure.
Resetting the hyperbus controller in board flash open to resync with PLL
clocks configured.
Revert "PDK-8311: Revert "[PDK-8145] Board: J721E DDR: Check-in Latest DDR Configuration Revision: 0.5.0""
This reverts commit c7b7ae53965394168e68cf0e1726ff3326d93074.
- 4266 configuration is the tested and recommended settings for production sample
- RTOS and Linux DDR configuration should be in sync, and both will be using the 4266 settings
- The failures in some boards could be due to earlier engineering sample issues.
Signed-off-by: Don Dominic <a0486429@ti.com>
This reverts commit c7b7ae53965394168e68cf0e1726ff3326d93074.
- 4266 configuration is the tested and recommended settings for production sample
- RTOS and Linux DDR configuration should be in sync, and both will be using the 4266 settings
- The failures in some boards could be due to earlier engineering sample issues.
Signed-off-by: Don Dominic <a0486429@ti.com>
Fix for print for automation
Fix for print for automation test to pass.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fix for print for automation test to pass.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
PDK-8480: Sciserver: Fix linker cmd file for testapp
Solves problem of Sciserver starting properly on MCU1_0
by putting all key boot code & vectors into BTCM memory.
This allows test cases on remote cores to be paired with
the included sciserver_testapp RPRC images and provide a
working sciserver on MCU1_0 when booting apps from OSPI.
NOTE: solves multiple test case issues on J7200 & J721E.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Solves problem of Sciserver starting properly on MCU1_0
by putting all key boot code & vectors into BTCM memory.
This allows test cases on remote cores to be paired with
the included sciserver_testapp RPRC images and provide a
working sciserver on MCU1_0 when booting apps from OSPI.
NOTE: solves multiple test case issues on J7200 & J721E.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
fixed mmcsd test for am65xx mcu core
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Fixing OSPI issues on J7200
Added necessary task params to fix BIOS start failure.
Disabled DAC DMA write and verify for J7200 since this is not supported.
Disabled interrupt mode in cases that are facing hangs.
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Added necessary task params to fix BIOS start failure.
Disabled DAC DMA write and verify for J7200 since this is not supported.
Disabled interrupt mode in cases that are facing hangs.
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Updates to TIFS binaries with fix from IA MAP in TIFS
Fix for IA MAP in TIFS during secure proxy setup
Fixes: SYSFW-4212
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fix for IA MAP in TIFS during secure proxy setup
Fixes: SYSFW-4212
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
diag: fix memory map to work with SBL
fixed memory map of MIBSPI/HWA/Diag to
work with SBL as they were using custom
linker cmd file.Also SBL updated for
case where app image only loaded on DSP
and not R5
Signed-off-by: Badri S <badri@ti.com>
fixed memory map of MIBSPI/HWA/Diag to
work with SBL as they were using custom
linker cmd file.Also SBL updated for
case where app image only loaded on DSP
and not R5
Signed-off-by: Badri S <badri@ti.com>
PDK-8453: SBL: Boot performance app fix
Fixes "sbl_boot_perf_test" for both J721E & J7200.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Fixes "sbl_boot_perf_test" for both J721E & J7200.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Revert "Fix SBL build fix for J721E"
This reverts commit 8334df9f4cc5fa826da3677e26572859e869602a.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
This reverts commit 8334df9f4cc5fa826da3677e26572859e869602a.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
gpio/tpr12: Update GPIO example to work on TPR12 EVM
Updated the GPIO example to work on TPR12 EVM
Signed-off-by: Badri S <badri@ti.com>
Updated the GPIO example to work on TPR12 EVM
Signed-off-by: Badri S <badri@ti.com>
diag_csirx/tpr12: added frontend cfg binaries to packaging list
Added frontend cfg binaries to PKG_SRCS so that it packaged
Signed-off-by: Badri S <badri@ti.com>
Added frontend cfg binaries to PKG_SRCS so that it packaged
Signed-off-by: Badri S <badri@ti.com>
sbl/tpr12: ROM certificate generation script ignore tmpfile not present
Modified the ROM certificate signing script to ignore rm of temp file
if not present
Signed-off-by: Badri S <badri@ti.com>
Modified the ROM certificate signing script to ignore rm of temp file
if not present
Signed-off-by: Badri S <badri@ti.com>
board/tpr12: pinmux data for AWR2243 front end control from DSP
Modified pnmux data so that default support is for AWR2243 front
end cfg from DSP instead of R5 which is the common usecase
This allows mmWaveSDK to run out of box with PDK without any
changes
Signed-off-by: Badri S <badri@ti.com>
Modified pnmux data so that default support is for AWR2243 front
end cfg from DSP instead of R5 which is the common usecase
This allows mmWaveSDK to run out of box with PDK without any
changes
Signed-off-by: Badri S <badri@ti.com>
[PDK-8394] Bug fix for wrong delay value in edma ut
Osal_delay takes delay in ms in ti_rtos configuration
but in CPU cycles in baremetal configuration.The test
case was invoking Osal_delay with large values assuming
CPU cycles but results in huge delay in execution as it
is interpreted as ms delay.Setting delay value to min 1
which is sufficient. Osal_delay API has to be fixed so that
API behaviour is same for both baremetal and ti_rtos
Signed-off-by: Badri S <badri@ti.com>
Osal_delay takes delay in ms in ti_rtos configuration
but in CPU cycles in baremetal configuration.The test
case was invoking Osal_delay with large values assuming
CPU cycles but results in huge delay in execution as it
is interpreted as ms delay.Setting delay value to min 1
which is sufficient. Osal_delay API has to be fixed so that
API behaviour is same for both baremetal and ti_rtos
Signed-off-by: Badri S <badri@ti.com>
diag_csirx/tpr12: support for csirx diag on c66x and ti_rtos config
added frontend cfg for AWR2243 and added support for c66x build
and sysbios config. CSIRX on c66x works only in sysbios config
and not in baremetal config presently due to PDK-8403
Signed-off-by: Badri S <badri@ti.com>
added frontend cfg for AWR2243 and added support for c66x build
and sysbios config. CSIRX on c66x works only in sysbios config
and not in baremetal config presently due to PDK-8403
Signed-off-by: Badri S <badri@ti.com>
3 years agoPDK-8437: Create Board init with limited module initializations for tpr12 REL.CORESDK.07.01.00.30
PDK-8437: Create Board init with limited module initializations for tpr12
- This is for usage in the Radar applications which cannot integrate
drivers like uart due to memory constraints.
- This is for usage in the Radar applications which cannot integrate
drivers like uart due to memory constraints.
Migrating to SYSFW version v2020.08b
Migrating to SYSFW 2020.08b
Migrating to SYSFW 2020.08b
Fixes for IRQ_RELEASE failing on the 2020.08a release
Fixed IRQ_RELEASE to use the forwarding of messages for VINT clearning.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fixed IRQ_RELEASE to use the forwarding of messages for VINT clearning.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
sbl: swap order of boardcfg
Send security boardcfg prior to RM boardcfg. This is required for the
specified devgrp to ensure firewalls are in proper state for rm_pm_hal
to access the resources.
Signed-off-by: Stephen Molfetta <sjmolfetta@ti.com>
Send security boardcfg prior to RM boardcfg. This is required for the
specified devgrp to ensure firewalls are in proper state for rm_pm_hal
to access the resources.
Signed-off-by: Stephen Molfetta <sjmolfetta@ti.com>