osal: Fixing OSAL VRING size for MMU settings for J784S4
[IPC] Fixed CLEC programming for J7AHP
- For NAVSS INTR, the output destination should be queried separately for both base event num and current event num
- Made corresponding changes in CLEC registration
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- For NAVSS INTR, the output destination should be queried separately for both base event num and current event num
- Made corresponding changes in CLEC registration
Signed-off-by: Rishabh Garg <rishabh@ti.com>
J7AHP: Adding mcu40/mcu41 to makefile
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Fixed IPC Issues
- Updated MPU to use 64 MB page
- Fixed typos for MCU4_0
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Updated MPU to use 64 MB page
- Fixed typos for MCU4_0
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Sciclient: Fix for sciclient ROM Alternate SPROXY for J784S4
Adds MSG_M4_ROM_USE_ALTERNATE_SPROXY config for J784S4 that
was causing problems with SBL boot for legacy boot mode.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Adds MSG_M4_ROM_USE_ALTERNATE_SPROXY config for J784S4 that
was causing problems with SBL boot for legacy boot mode.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
J7AHP: Update RM IRQ tree
Signed-off-by: l-kumar <a0492259@ti.com>
Signed-off-by: l-kumar <a0492259@ti.com>
Board: Fix for j784s4 board library build error on C7x core
Board: Updated Board MMR unlock call sequence for j784s4 evm
- Board MMR unlock function is called at the start of Board_init based
on the flag passed by applications. Board functions like pinmux and
eth config will also does the mmr unlock and lock which will
overwrite the unlock done by Board init MMR unlock flag.
Applications will face issues in MMR unlock when then combine the MMR
unlock flag with other board init flags which does MMR writes.
Moved the MMR unlock to end of Board_init to fix the issue.
- Board MMR unlock function is called at the start of Board_init based
on the flag passed by applications. Board functions like pinmux and
eth config will also does the mmr unlock and lock which will
overwrite the unlock done by Board init MMR unlock flag.
Applications will face issues in MMR unlock when then combine the MMR
unlock flag with other board init flags which does MMR writes.
Moved the MMR unlock to end of Board_init to fix the issue.
Board: Updated j784s4 evm Ethernet config functions
- Updated the CPSW2G Main ENET control and PHY config board init flag
values not to conflict with CPSW9G
- Added MMR unlock/lock in ENET config APIs
- Updated the CPSW2G Main ENET control and PHY config board init flag
values not to conflict with CPSW9G
- Added MMR unlock/lock in ENET config APIs
Board: Updated j784s4 evm wakeup gpio pinmux
- Added wakeup gpio pin mapping used by bootswitch test
- Added wakeup gpio pin mapping used by bootswitch test
Migrating to SYSFW version j7ahp-presil-0.9-rc3
Fixed IPC interrupts for C7x
- RT mapping was not done correctly for C7x_3/C7x_4
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- RT mapping was not done correctly for C7x_3/C7x_4
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Fixed VRING buffer size for J7AHP IPC
- One processor communication needs 0x40000 memory
- J7AHP needs 14*13* 0x40000 = ~46 MB memory
- Rounded off to 48 MB
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- One processor communication needs 0x40000 memory
- J7AHP needs 14*13* 0x40000 = ~46 MB memory
- Rounded off to 48 MB
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Fixed IPC RTOS example
- Added missing remote procs for C7x_1 and C7x_2
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Added missing remote procs for C7x_1 and C7x_2
Signed-off-by: Rishabh Garg <rishabh@ti.com>
J7AHP: Fix: UDMA channel allocation fails for local DRUs
Signed-off-by: l-kumar <a0492259@ti.com>
Signed-off-by: l-kumar <a0492259@ti.com>
J784S4: UDMA: Fixing host emulation mode build
Signed-off-by: Lucas Weaver <l-weaver@ti.com>
Signed-off-by: Lucas Weaver <l-weaver@ti.com>
J784S4: Sciclient: Removing hacks
Removing Board and UART related hacks
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Removing Board and UART related hacks
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
J7AHP: Fix: UDMA shared resources rm_boardcfg for C7X cores.
- The default sharing policy for VINT/INTR resources are incorrect and causing failure in UdmaInitPrms_init API.
- Update sharing policy for C7X cores, such that required resources not exceeds available range recieved from sciclient RM boardcfg.
Signed-off-by: l-kumar <a0492259@ti.com>
- The default sharing policy for VINT/INTR resources are incorrect and causing failure in UdmaInitPrms_init API.
- Update sharing policy for C7X cores, such that required resources not exceeds available range recieved from sciclient RM boardcfg.
Signed-off-by: l-kumar <a0492259@ti.com>
J784S4: Further updates for SYSFW Migration to j7ahp-presil-0.9-rc2
Adding tifs bin
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Adding tifs bin
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Migrating to SYSFW version j7ahp-presil-0.9-rc2
Fix PLL27 and PLL28 flags in rm_pm_hal
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Fix PLL27 and PLL28 flags in rm_pm_hal
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Board: Added SD loopback clock pinmux for j784s4 evm
Migrating to SYSFW version j7ahp-presil-0.9-rc1
J784S4: SYSFW script update
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
J784S4: Further updates for SYSFW Migration to j7ahp-presil-0.7
Adding files missed in previous migration commit
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
Adding files missed in previous migration commit
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
6 days agoJ784S4: SBL: Macro names update REL.CORESDK.08.02.01.04 REL.CORESDK.08.02.01.06 REL.CORESDK.08.02.01.07
J784S4: SBL: Macro names update
Compute cluster macro names update required
after j7ahp-resil-0.7 SYSFW release migration
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
Compute cluster macro names update required
after j7ahp-resil-0.7 SYSFW release migration
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
Migrating to SYSFW version j7ahp-presil-0.7
scripts: sysfw migrate script update
sysfw migrate script now accepts a list of SOCs
for which the migration needs to be performed
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
sysfw migrate script now accepts a list of SOCs
for which the migration needs to be performed
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
J7AHP: Sysfw updates
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
PDK-11540: Board: Updated j784s4 USXGMII configurations to use ENET2 port
PDK-11773: Board: Updated j784s4 QSGMII and QSGMII_sub port allocation
PDK-11772: Board: Updated board control APIs for j784s4 evm
PDK-11773: Board: Added board Ethernet APIs for j784s4 evm
PDK-11540: Board: Enabled Ethernet SerDes configurations for j784s4 evm
j784s4: Port driver for newly added UTCs
- Create local boardcfg for newly added DRUs.
- Modify UDMA RM to pick resource ranges for these DRUs locally
- Add support for newly added VPAC
Signed-off-by: l-kumar <a0492259@ti.com>
- Create local boardcfg for newly added DRUs.
- Modify UDMA RM to pick resource ranges for these DRUs locally
- Add support for newly added VPAC
Signed-off-by: l-kumar <a0492259@ti.com>
Revert "J7AHP: UDMA: Add support to additional DRUs"
This reverts commit 448d04379017c6e2569be5ceae91d2c69ca40ff8.
This reverts commit 448d04379017c6e2569be5ceae91d2c69ca40ff8.
[GPIO][J7200]: Disabling Baremetal LedBlink example on main cores
- There is no interrupt allocation for wakeup GPIO to main domain.
- The LedBlink app uses the wakeup GPIO.
Signed-off-by: Mriganka Chakravarty <m-chakravarty@ti.com>
- There is no interrupt allocation for wakeup GPIO to main domain.
- The LedBlink app uses the wakeup GPIO.
Signed-off-by: Mriganka Chakravarty <m-chakravarty@ti.com>
Fix: UDMA: DRU direct TR Example failure
Fixes: PDK-11133
Signed-off-by: l-kumar <a0492259@ti.com>
Fixes: PDK-11133
Signed-off-by: l-kumar <a0492259@ti.com>
[GPIO][J721E]: Fix and Updated gpio interrupt config implementation
Existing Issues:-
- GPIO driver is core independendent.
- But Core specific build flags are used in soc specific files for setting various params like TISCI host Id etc.
- Interrupt Numbers are hardcoded.
- This should be derived from allocated interrupt router # for each core in the BoardCfg.
Fixes:-
j721e/GPIO_soc.c
- Added API to query from BoardCfg the valid interrupt router # /Core Interrupt #.
- Use CSL APIs to identify and set TISCI Dev id fo the current core.
- CLEC Cfg RTMAP update to use id based on C7x core, using CSL API.
Signed-off-by: Mriganka Chakravarty <m-chakravarty@ti.com>
Existing Issues:-
- GPIO driver is core independendent.
- But Core specific build flags are used in soc specific files for setting various params like TISCI host Id etc.
- Interrupt Numbers are hardcoded.
- This should be derived from allocated interrupt router # for each core in the BoardCfg.
Fixes:-
j721e/GPIO_soc.c
- Added API to query from BoardCfg the valid interrupt router # /Core Interrupt #.
- Use CSL APIs to identify and set TISCI Dev id fo the current core.
- CLEC Cfg RTMAP update to use id based on C7x core, using CSL API.
Signed-off-by: Mriganka Chakravarty <m-chakravarty@ti.com>
[GPIO][J7200]: Fix and Updated gpio interrupt config implementation
Existing Issues:-
- GPIO driver is core independendent.
- But Core specific build flags are used in soc specific files for setting various params like TISCI host Id etc.
- Interrupt Numbers are hardcoded.
- This should be derived from allocated interrupt router # for each core in the BoardCfg.
Fixes:-
j7200/GPIO_soc.c
- Added API to query from BoardCfg the valid interrupt router # /Core Interrupt #.
- Use CSL APIs to identify and set TISCI Dev id fo the current core.
- CLEC Cfg RTMAP update to use id based on C7x core, using CSL API.
Signed-off-by: Mriganka Chakravarty <m-chakravarty@ti.com>
Existing Issues:-
- GPIO driver is core independendent.
- But Core specific build flags are used in soc specific files for setting various params like TISCI host Id etc.
- Interrupt Numbers are hardcoded.
- This should be derived from allocated interrupt router # for each core in the BoardCfg.
Fixes:-
j7200/GPIO_soc.c
- Added API to query from BoardCfg the valid interrupt router # /Core Interrupt #.
- Use CSL APIs to identify and set TISCI Dev id fo the current core.
- CLEC Cfg RTMAP update to use id based on C7x core, using CSL API.
Signed-off-by: Mriganka Chakravarty <m-chakravarty@ti.com>
Freertos: j7aep: Enable UT on all C7x cores
Signed-off-by: l-kumar <a0492259@ti.com>
Signed-off-by: l-kumar <a0492259@ti.com>
J7AHP updates due to IPC
- Fixed packaging issue
- Updated OSAL for DDR shared region mapping
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Fixed packaging issue
- Updated OSAL for DDR shared region mapping
Signed-off-by: Rishabh Garg <rishabh@ti.com>
[j784s4][IPC] Enabling IPC example for j784s4
- Enable IPC echo_test and perf_test for j784s4
Signed-off-by: Chandru Dhavamani <a0497642@ti.com>
- Enable IPC echo_test and perf_test for j784s4
Signed-off-by: Chandru Dhavamani <a0497642@ti.com>
Migrating to SYSFW version v08.04.01
Scripts: Updated sysfw migrate script for hs devices
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
J721S2: Update rm board config file
SA3SS resources have been removed
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
SA3SS resources have been removed
Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>
Fix for j784s4 evm board build error
PDK-11771: Board: Added board utils functions for j784s4 evm
- Removed sd voltage switch board dummy function in mmcsd example
- Removed sd voltage switch board dummy function in mmcsd example
PDK-11775: Board: Added mmr lock/unlock configurations for j784s4 evm
Board: Enabled board lld init APIs for j784s4 evm
PDK-11768: Added I2C init functions
PDK-11767: Added UART init functions
PDK-11768: Added I2C init functions
PDK-11767: Added UART init functions
PDK-11351: Board: Added PLL clock configurations for j784s4 evm
PDK-11769: Board: Added board info APIs for j784s4 evm
PDK-11770: Board: Added i2c IO expander library for j784s4 evm
PDK-11776: Board: Added psc configurations for j784s4 evm
PDK-11772: Board: Added board control API for j784s4 evm
PDK-11766: Board: Added pinmux configurations for j784s4 evm
PDK-11354: Board: Added board DDR configurations for j784s4 evm
lwip: Add support for J784S4
Enable lwIP stack, contrib and port for J748S4.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Enable lwIP stack, contrib and port for J748S4.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Removed NDK sections from PDK linker command files
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Bug Fix: PDK-10925, PDK-10350, PDK-10346
- IPC performance tests included MPU1_0 as TI-RTOS supported MPU cores but same are not supported by Freertos
- Hence removed MPU1_0 from performance tests for J7200 as part of cleanup:
* https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/pull-requests/2681/diff#packages/ti/drv/ipc/examples/ipc_perf_test/ipc_perf_test.c
* https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/pull-requests/2681/diff#packages/ti/drv/ipc/examples/ipc_perf_test/ipc_test_defs.c
- Prints have also moved to MCU1_0
- Similar changes have been done for J721e and J721S2
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- IPC performance tests included MPU1_0 as TI-RTOS supported MPU cores but same are not supported by Freertos
- Hence removed MPU1_0 from performance tests for J7200 as part of cleanup:
* https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/pull-requests/2681/diff#packages/ti/drv/ipc/examples/ipc_perf_test/ipc_perf_test.c
* https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/pull-requests/2681/diff#packages/ti/drv/ipc/examples/ipc_perf_test/ipc_test_defs.c
- Prints have also moved to MCU1_0
- Similar changes have been done for J721e and J721S2
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Fix: j721s2: Sciclient: unit test hanging on c7x cores.
- Sciclient was not able to program interrupt response lines(clec input event) for multiple c7x cores.
- The interrupt response lines used for j721s2 c7x cores are incorrect.
- Defining interrupt response lines used for c7x cores in sciclient_fmwMsgParams.h
- Modifying sciliclient core context structure to add clec input event(interrupt response line coming to clec) in sciclient_priv.h
- Update C7x cores context to add respective clec input event number in sciclient_fmwSecureProxyMap.c
- Update driver to take clec input event from it's context in sclient.c
Fixes: PDK-10829
Signed-off-by: l-kumar <a0492259@ti.com>
- Sciclient was not able to program interrupt response lines(clec input event) for multiple c7x cores.
- The interrupt response lines used for j721s2 c7x cores are incorrect.
- Defining interrupt response lines used for c7x cores in sciclient_fmwMsgParams.h
- Modifying sciliclient core context structure to add clec input event(interrupt response line coming to clec) in sciclient_priv.h
- Update C7x cores context to add respective clec input event number in sciclient_fmwSecureProxyMap.c
- Update driver to take clec input event from it's context in sclient.c
Fixes: PDK-10829
Signed-off-by: l-kumar <a0492259@ti.com>
[DSS]: Disabling HPD support for j721e.
Signed-off-by: Mriganka Chakravarty <m-chakravarty@ti.com>
Signed-off-by: Mriganka Chakravarty <m-chakravarty@ti.com>
j784s4: Add DRU base register macros for host_emu
Signed-off-by: l-kumar <a0492259@ti.com>
Signed-off-by: l-kumar <a0492259@ti.com>
[SPI] : creating Multicore image for MCSPI MasterSlave TestApp
- MCSPI slavemode used to communicate between two cores
- Common makefile is used to create multicore appimage for MCSPI_Baremetal_TestApp
MCSPI_Baremetal_Dma_TestApp MCSPI_MasterSlave_TestApp_freertos MCSPI_MasterSlave_Dma_TestApp_freertos
Signed-off-by: chandru dhavamani <chandru@ti.com>
- MCSPI slavemode used to communicate between two cores
- Common makefile is used to create multicore appimage for MCSPI_Baremetal_TestApp
MCSPI_Baremetal_Dma_TestApp MCSPI_MasterSlave_TestApp_freertos MCSPI_MasterSlave_Dma_TestApp_freertos
Signed-off-by: chandru dhavamani <chandru@ti.com>
Updated IPC driver for J7AHP
- Added default interrupt mapping for sciclient disable
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Added default interrupt mapping for sciclient disable
Signed-off-by: Rishabh Garg <rishabh@ti.com>
j784s4: Add missing SerDes and ENET expansion board related APIs
Added follwing SerDes and ENET expansion board related APIs:
Board_cpswEnetExpPhyReset()
Board_cpswEnetExpComaModeCfg()
Board_serdesCfgSgmii()
Board_serdesCfgQsgmii()
Board_serdesCfgUsxgmii()
Board_serdesCfgStatus()
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Added follwing SerDes and ENET expansion board related APIs:
Board_cpswEnetExpPhyReset()
Board_cpswEnetExpComaModeCfg()
Board_serdesCfgSgmii()
Board_serdesCfgQsgmii()
Board_serdesCfgUsxgmii()
Board_serdesCfgStatus()
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Fixed PDK build for SBL
- Multicore apps fail for J784S4 as soc info is not in sync with sbl_component.mk
- Last core in sbl_component.mk is mpu2_3 whereas it is specified in middle of soc_info.mk
- Updated soc_info.mk to make mpu2_3 as last core
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Multicore apps fail for J784S4 as soc info is not in sync with sbl_component.mk
- Last core in sbl_component.mk is mpu2_3 whereas it is specified in middle of soc_info.mk
- Updated soc_info.mk to make mpu2_3 as last core
Signed-off-by: Rishabh Garg <rishabh@ti.com>
[PDK-11976][FREERTOS] C66X IR Configuration for OS Timer Interrupts for FREERTOS
- In os_init() C66X IR for OS Timer Interrupts has been configured.
- In application Timer interrupts have been removed since it has been configured in os_init()
Signed-off-by: chandru dhavamani <chandru@ti.com>
- In os_init() C66X IR for OS Timer Interrupts has been configured.
- In application Timer interrupts have been removed since it has been configured in os_init()
Signed-off-by: chandru dhavamani <chandru@ti.com>
[PDK-11976][FREERTOS] C66X IR Configuration for OS Timer Interrupts for FREERTOS
- In os_init() C66X IR for OS Timer Interrupts has been configured.
- In application Timer interrupts have been removed since it has been configured in os_init()
Signed-off-by: chandru dhavamani <chandru@ti.com>
- In os_init() C66X IR for OS Timer Interrupts has been configured.
- In application Timer interrupts have been removed since it has been configured in os_init()
Signed-off-by: chandru dhavamani <chandru@ti.com>
[PDK-11976][FREERTOS] C66X IR Configuration for OS Timer Interrupts for FREERTOS
- In os_init() C66X IR for OS Timer Interrupts has been configured.
- In application Timer interrupts have been removed since it has been configured in os_init()
Signed-off-by: chandru dhavamani <chandru@ti.com>
- In os_init() C66X IR for OS Timer Interrupts has been configured.
- In application Timer interrupts have been removed since it has been configured in os_init()
Signed-off-by: chandru dhavamani <chandru@ti.com>
J784S4: SBL: Add sbl support for j784s4
Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Fixed ipc_component.mk
- Baremetal does not have a default board list so used driver SOC list
- Fixed copy paste error perf test
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Baremetal does not have a default board list so used driver SOC list
- Fixed copy paste error perf test
Signed-off-by: Rishabh Garg <rishabh@ti.com>
J7AHP: UDMA: Add support to additional DRUs
Fixes: PDK-12045
Signed-off-by: l-kumar <a0492259@ti.com>
Fixes: PDK-12045
Signed-off-by: l-kumar <a0492259@ti.com>
J784S4: Add CFLAGS, LNKFLAGS for newly added mpu cores
Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Fix: Freertos: UT fails on newly added c7x cores.
- Add support for newly added c7x cores for j7ahp
Signed-off-by: l-kumar <a0492259@ti.com>
- Add support for newly added c7x cores for j7ahp
Signed-off-by: l-kumar <a0492259@ti.com>
[QNX] board: sciclient: Add build support for j784s4
Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Praveen Rao <prao@ti.com>
Updated IPC example structure
- Added separate folders for baremetal, linux and qnx
- Added qnx example which was missed last time
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Added separate folders for baremetal, linux and qnx
- Added qnx example which was missed last time
Signed-off-by: Rishabh Garg <rishabh@ti.com>
[J7AHP] Enable host emulation builds for osal, udma and sciclient. Enable dmautils build for both host emulation and target
[DIAG] Disable diag examples for j721e
- SDR is descoped from PDK and DIAG examples have dependency on the same
- Hence diasble diag examples
Signed-off-by: Don Dominic <a0486429@ti.com>
- SDR is descoped from PDK and DIAG examples have dependency on the same
- Hence diasble diag examples
Signed-off-by: Don Dominic <a0486429@ti.com>
Disabled SDR for J721e
- SDR is now SDL and a different package
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- SDR is now SDL and a different package
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Bug Fix: PDK-11388
- SBL Image package build was wrongly copying all files in build directoy to board folder
- Fixed packaging and included board files in SBL Lib package build
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- SBL Image package build was wrongly copying all files in build directoy to board folder
- Fixed packaging and included board files in SBL Lib package build
Signed-off-by: Rishabh Garg <rishabh@ti.com>
[SBL] Removed files for legacy SOCs
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Signed-off-by: Rishabh Garg <rishabh@ti.com>
J721E : J7200 : OSPI boot bug fix
- Fix the OSPI boot bug fix for j721e and j7200
- Change the app_img_version to 1 in rprc to control the change to the
new SDK due to new core IDs
Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
- Fix the OSPI boot bug fix for j721e and j7200
- Change the app_img_version to 1 in rprc to control the change to the
new SDK due to new core IDs
Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Fixed IPC build issues
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Fixed PDK build
- Wrongly used C style comments in makefile
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Wrongly used C style comments in makefile
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Fixed IPC packaging and makefile
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Enabled IPC driver build for J7AHP
Signed-off-by: Rishabh Garg <rishabh@ti.com>
Signed-off-by: Rishabh Garg <rishabh@ti.com>
J7AHP: UDMA: Remove HACK for Bord_init
Fixes:PDK-12017
Signed-off-by: l-kumar <a0492259@ti.com>
Fixes:PDK-12017
Signed-off-by: l-kumar <a0492259@ti.com>
osal: cleanup: Remove source files and makefile refernces related to legacy devices
- Remove all source files and makefile related to legacy devices
- Cleanup osal_component.mk
- Remove all unsupported rules
- Remove all files that are no longer used
Signed-off-by: Don Dominic <a0486429@ti.com>
- Remove all source files and makefile related to legacy devices
- Cleanup osal_component.mk
- Remove all unsupported rules
- Remove all files that are no longer used
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-12013] sciserver: safertos: Fix OCMC RAM SCISERVER memory overlap
- OCMC_RAM_SCISERVER in sciserver_testapp linker file
was encroaching into OCMC_RAM used by other linker files
- Fix this by reducing the length of OCMC_RAM_SCISERVER in sciserver_testapp linker file
- Also relocate various sections in sciserver_testapp linker file TCMB and TCMA
to fit all sections in available memories
- update checked-in sciserver binaries
- This fixes UDMA UT failure in R5F non-mcu1_0 cores
Signed-off-by: Don Dominic <a0486429@ti.com>
- OCMC_RAM_SCISERVER in sciserver_testapp linker file
was encroaching into OCMC_RAM used by other linker files
- Fix this by reducing the length of OCMC_RAM_SCISERVER in sciserver_testapp linker file
- Also relocate various sections in sciserver_testapp linker file TCMB and TCMA
to fit all sections in available memories
- update checked-in sciserver binaries
- This fixes UDMA UT failure in R5F non-mcu1_0 cores
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-12012] sciclient: safertos: launch.js updates to load sciserver safertos binary
- Add new isSafertos flag
- Load safeRTOS version of sciserver_testapp binary when above flag is set
Signed-off-by: Don Dominic <a0486429@ti.com>
- Add new isSafertos flag
- Load safeRTOS version of sciserver_testapp binary when above flag is set
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-12011] build: safertos: Updates to set custom SafeRTOS Package path
- Add new safertos_package_path.mk
- SAFERTOS_<SOC>_<ISA>_INSTALL_PATH variable can be set here
- If not set, it will use the default development location
- i.e, $(SDK_INSTALL_PATH)/safertos_<SOC>_<ISA>_<SAFERTOS_VERSION>
- Add Utility script to setup SDK for SafeRTOS Builds
- This script can be used to custom SafeRTOS WHIS Package Installation path
- Also rebuilds required libraries like safertos, osal_safertos
check-in sciserver_testapp_safertos .xer5f and .rprx to sciclient tools folder
- This is required since the above libs/binaries won't be included in the public SDK
- Only enabled for j721e r5f/c66/c7x
- Can be enhanced in future to support other SOC's
Signed-off-by: Don Dominic <a0486429@ti.com>
- Add new safertos_package_path.mk
- SAFERTOS_<SOC>_<ISA>_INSTALL_PATH variable can be set here
- If not set, it will use the default development location
- i.e, $(SDK_INSTALL_PATH)/safertos_<SOC>_<ISA>_<SAFERTOS_VERSION>
- Add Utility script to setup SDK for SafeRTOS Builds
- This script can be used to custom SafeRTOS WHIS Package Installation path
- Also rebuilds required libraries like safertos, osal_safertos
check-in sciserver_testapp_safertos .xer5f and .rprx to sciclient tools folder
- This is required since the above libs/binaries won't be included in the public SDK
- Only enabled for j721e r5f/c66/c7x
- Can be enhanced in future to support other SOC's
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-12010] osal: safertos: Critical Sections Fix
- Use SafeRTOS portable layer APIs to disable/enable Interrupts in critical sections
when scheduler is already started and not in ISR
- This is to avoid breakage of critical sections when CSL/OSAL_Arch APIs are also used
in conjunction
Signed-off-by: Don Dominic <a0486429@ti.com>
- Use SafeRTOS portable layer APIs to disable/enable Interrupts in critical sections
when scheduler is already started and not in ISR
- This is to avoid breakage of critical sections when CSL/OSAL_Arch APIs are also used
in conjunction
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-12009] safertos: test: osal: Updates to use osal_safertos lib for task switch example and safertos demo
- Since osal_safertos lib is now available for all ISA's, task switch example and safertos_demo can use the same
- task switch example and safertos_demo makefile updates to use PDK_COMMON_SAFERTOS_COMP
- OSAL updates to make vApplicationErrorHook and vApplicationSetupTickInterruptHook
definition as weak so that application can have overridden definition.
- Remove custom linker files for task switch example and use default one in ti/build
- Also enable SBL appimage generation for task switch example
- Validated SafeRTOS Task SW Example and OSAL UT on all cores (R5F/C66x/C7x)
Signed-off-by: Don Dominic <a0486429@ti.com>
- Since osal_safertos lib is now available for all ISA's, task switch example and safertos_demo can use the same
- task switch example and safertos_demo makefile updates to use PDK_COMMON_SAFERTOS_COMP
- OSAL updates to make vApplicationErrorHook and vApplicationSetupTickInterruptHook
definition as weak so that application can have overridden definition.
- Remove custom linker files for task switch example and use default one in ti/build
- Also enable SBL appimage generation for task switch example
- Validated SafeRTOS Task SW Example and OSAL UT on all cores (R5F/C66x/C7x)
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-11091] safertos: c7x: drv: IPC SafeRTOS C7x Driver Integration
- Add Linker file for IPC C7x SafeRTOS examples
- example common makefile updates to include c7x_mmu.c for safertos builds
- Also update Mmu.h header file for C7x in main_rtos.c/c7_mmu.c
Signed-off-by: Don Dominic <a0486429@ti.com>
- Add Linker file for IPC C7x SafeRTOS examples
- example common makefile updates to include c7x_mmu.c for safertos builds
- Also update Mmu.h header file for C7x in main_rtos.c/c7_mmu.c
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-11091] safertos: c7x: osal: Enable OSAL lib for SafeRTOS C7x
- General Updates to enable C7x for osal_safertos
- Add HwiP_safertos_c7x.c
- Add osalArch_TimeStampGetFreqKHz and osalArch_TimestampGet64 implementations
in arch/core/c7x to enable TimerP_getTimeInUsecs
- Related makefile updates
- Update OSAL_CPU_FREQ_KHZ_DEFAULT in osal/soc/j721e/osal_soc.h based on ISA flags
- Updates to make SafeROS C7x Integration with Drivers similar to FreeRTOS
so that no custom updates are required in the application
- Define Osal_initMmuDefault and OsalCfgClecAccessCtrl
which will be referred in applications
- Invoke application defined InitMmu in the SafeRTOS C7x startup function vInitMmu
- Enable OSAL SafeRTOS UT for C7x
- OSAL UT Source file updates
- OSAL_board.h cleanup
Signed-off-by: Don Dominic <a0486429@ti.com>
- General Updates to enable C7x for osal_safertos
- Add HwiP_safertos_c7x.c
- Add osalArch_TimeStampGetFreqKHz and osalArch_TimestampGet64 implementations
in arch/core/c7x to enable TimerP_getTimeInUsecs
- Related makefile updates
- Update OSAL_CPU_FREQ_KHZ_DEFAULT in osal/soc/j721e/osal_soc.h based on ISA flags
- Updates to make SafeROS C7x Integration with Drivers similar to FreeRTOS
so that no custom updates are required in the application
- Define Osal_initMmuDefault and OsalCfgClecAccessCtrl
which will be referred in applications
- Invoke application defined InitMmu in the SafeRTOS C7x startup function vInitMmu
- Enable OSAL SafeRTOS UT for C7x
- OSAL UT Source file updates
- OSAL_board.h cleanup
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-9547] c7x: build: Update --symdebug compiler option for SafeRTOS C7x Build
- SafeRTOS package uses .asmfunc and .endasmfunc directives
- This will work only with --symdebug:dwarf compiler option
- Hence set --symdebug:dwarf for both release and debug safertos build
Signed-off-by: Don Dominic <a0486429@ti.com>
- SafeRTOS package uses .asmfunc and .endasmfunc directives
- This will work only with --symdebug:dwarf compiler option
- Hence set --symdebug:dwarf for both release and debug safertos build
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-9547] safertos: c7x: Check-in SafeRTOS C7x
- Check-in SafeRTOS C7x Release from WHIS
- makefile updates for SafeRTOS C7x package, enables safertos lib for C7x
- makefile updates for safertos_demo app build for C7x
- Enable safertos task switch example for C7x
- Add default linker file for safeRTOS C7x
- Enable C7x SafeRTOS apps build for j721e from ti/build/component.mk
- Remove c7x_1 from SafeRTOS default exclude CORELIST
Signed-off-by: Don Dominic <a0486429@ti.com>
- Check-in SafeRTOS C7x Release from WHIS
- makefile updates for SafeRTOS C7x package, enables safertos lib for C7x
- makefile updates for safertos_demo app build for C7x
- Enable safertos task switch example for C7x
- Add default linker file for safeRTOS C7x
- Enable C7x SafeRTOS apps build for j721e from ti/build/component.mk
- Remove c7x_1 from SafeRTOS default exclude CORELIST
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-9535] safertos: c66: IPC/UDMA/UART/McASP/Sciclient SafeRTOS C66x Integration Updates
- Add IPC C66x SafeRTOS Linker files
- Driver Example source file updates to
- restrict R5F FFI limitation - stack to be aligned to stack size only for MCU cores
- bypass IR Configuration for Timer Interrupt
- For SafeRTOS this is already done as part of OS_Init()
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: chandru dhavamani <chandru@ti.com>
- Add IPC C66x SafeRTOS Linker files
- Driver Example source file updates to
- restrict R5F FFI limitation - stack to be aligned to stack size only for MCU cores
- bypass IR Configuration for Timer Interrupt
- For SafeRTOS this is already done as part of OS_Init()
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: chandru dhavamani <chandru@ti.com>
[PDK-9535] safertos: c66: osal: Enable OSAL lib for SafeRTOS C66x
- General Updates to enable C66x for osal_safertos
- Enable OSAL SafeRTOS UT for C66x
- OSAL UT Source file updates
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: chandru dhavamani <chandru@ti.com>
- General Updates to enable C66x for osal_safertos
- Enable OSAL SafeRTOS UT for C66x
- OSAL UT Source file updates
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: chandru dhavamani <chandru@ti.com>
[PDK-10707] safertos: c66: Check-in SafeRTOS C66
- Check-in SafeRTOS C66x Release from WHIS
- makefile updates for safertos c66x package, enables safertos lib for C66x
- makefile updates for safertos_demo app build for C66x
- Enable safertos task switch example for C66x
- Add default linker file for SafeRTOS C66x
- Enable C66x SafeRTOS apps build for j721e from ti/build/component.mk
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: chandru dhavamani <chandru@ti.com>
- Check-in SafeRTOS C66x Release from WHIS
- makefile updates for safertos c66x package, enables safertos lib for C66x
- makefile updates for safertos_demo app build for C66x
- Enable safertos task switch example for C66x
- Add default linker file for SafeRTOS C66x
- Enable C66x SafeRTOS apps build for j721e from ti/build/component.mk
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: chandru dhavamani <chandru@ti.com>