[WIP][PDK-8726] OSPI: Separate OPSI tests keeping memory cached/non-cached
- Added support for baremetal apps
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- Added support for baremetal apps
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[WIP][PDK-8726] Separate OSPI tests keeping memory cached/non-cached
- added new tests that export cache as enabled
- separate mpu.xs files for cache enabled/disabled
- RTOS implemented, baremetal pending
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- added new tests that export cache as enabled
- separate mpu.xs files for cache enabled/disabled
- RTOS implemented, baremetal pending
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Hyperflash : Tested with board diag on j721e es 1.1
Works fine in 166 MHz (333 MHz device clock)
Require to clean up code
Signed-off-by: sujith <sujith.s@ti.com>
Works fine in 166 MHz (333 MHz device clock)
Require to clean up code
Signed-off-by: sujith <sujith.s@ti.com>
PDK-6706 : SPI Master example is not functional
The Master example would perform, couple of transactions with
slave app and stall/timeout with an error.
The "loopback" tests would always fail
Root Cause : The driver do not support operating McSPI in
digital loopback mode. As the IP did not support the same.
Fix: Disabled the loopback mode of operation for j721e & j7200
Test : Tested on j721e evm
Signed-off-by: sujith <sujith.s@ti.com>
The Master example would perform, couple of transactions with
slave app and stall/timeout with an error.
The "loopback" tests would always fail
Root Cause : The driver do not support operating McSPI in
digital loopback mode. As the IP did not support the same.
Fix: Disabled the loopback mode of operation for j721e & j7200
Test : Tested on j721e evm
Signed-off-by: sujith <sujith.s@ti.com>
[PDK-9435] Board: DDR: Enable DDR Thermal Testapp for J7200
- enabled board_ddr_thermal_test_app for j7200 mcu1_0/mcu1_1/mcu2_0/mcu2_1
- Updates in board lib 'board/src/j7200_evm/board_ddrtempmonitor.c'
- to enable all r5 cores
- no interrupt routers b/w DDR controller and Main Domain R5
- so skip Sciclient IRQ Routing
- for MCU Domain R5 cores
- query the IR Range from BoardCfg
- translate to Core Interrupt Idx and configure path
Signed-off-by: Don Dominic <a0486429@ti.com>
- enabled board_ddr_thermal_test_app for j7200 mcu1_0/mcu1_1/mcu2_0/mcu2_1
- Updates in board lib 'board/src/j7200_evm/board_ddrtempmonitor.c'
- to enable all r5 cores
- no interrupt routers b/w DDR controller and Main Domain R5
- so skip Sciclient IRQ Routing
- for MCU Domain R5 cores
- query the IR Range from BoardCfg
- translate to Core Interrupt Idx and configure path
Signed-off-by: Don Dominic <a0486429@ti.com>
Firmware gen.sh update for ES1.1 HS testing
Firmware Gen.sh update for ES1.1 HS testing
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Firmware Gen.sh update for ES1.1 HS testing
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fix for proper sending and parsing of RM board config in HS
Ignoring of the certificate is handled correctly by adjusting the size at source when the certificate is not passed and at sink when the certificate is passed.
Fixes: PDK-9427
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Ignoring of the certificate is handled correctly by adjusting the size at source when the certificate is not passed and at sink when the certificate is passed.
Fixes: PDK-9427
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
[DSS M2M APP]Added sample application for DSS M2M Driver
Signed-off-by: Vivek Dhande <a0132295@ti.com>
Signed-off-by: Vivek Dhande <a0132295@ti.com>
freertos: Add FreeRTOS kernel folders to gitignore
- Add the following folders in ti/kernel/freertos to gitignore
- FreeRTOS-Labs/
- FreeRTOS-LTS/
- These are cloned from https://github.com/FreeRTOS/ as defined in psdk.xml
Signed-off-by: Don Dominic <a0486429@ti.com>
- Add the following folders in ti/kernel/freertos to gitignore
- FreeRTOS-Labs/
- FreeRTOS-LTS/
- These are cloned from https://github.com/FreeRTOS/ as defined in psdk.xml
Signed-off-by: Don Dominic <a0486429@ti.com>
PDK-9285: IPC: Fix KW issues
Fix KW issues for AM64X IPC and MB build.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Fix KW issues for AM64X IPC and MB build.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
[DSS M2M Driver]Addressed review comments
Signed-off-by: Vivek Dhande <a0132295@ti.com>
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M Driver]Fixed Doxygen API Guide Warnings
Signed-off-by: Vivek Dhande <a0132295@ti.com>
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M Driver]Driver implementation: Patch-2
- Added implementation for 'Fvid2_processRequest()' and 'Fvid2_getProcessedRequest()'
- Implemented 'IOCTL_DSS_DCTRL_SET_PATH' and 'IOCTL_DSS_DCTRL_CLEAR_PATH' IOCTLs
- Implemented DMA completion Events
- Implemented internal functions needed for above
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Added implementation for 'Fvid2_processRequest()' and 'Fvid2_getProcessedRequest()'
- Implemented 'IOCTL_DSS_DCTRL_SET_PATH' and 'IOCTL_DSS_DCTRL_CLEAR_PATH' IOCTLs
- Implemented DMA completion Events
- Implemented internal functions needed for above
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M Driver]Driver implementation: Patch-1
- Added 'dss_m2mPriv.h'
- This files contains following
- internal structures required for maintaining driver and HW Module states
- Added support for multiple open/create to support multiple channel support
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Added 'dss_m2mPriv.h'
- This files contains following
- internal structures required for maintaining driver and HW Module states
- Added support for multiple open/create to support multiple channel support
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M DRV][PDK-5179]DSS FVID2 Writeback M2M Driver
- [PDK-5184]DSS Writeback Pipeline Support
- Added interface for DSS M2M driver
- Added nodes & edges for WB pipeline
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- [PDK-5184]DSS Writeback Pipeline Support
- Added interface for DSS M2M driver
- Added nodes & edges for WB pipeline
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[PDK-9432] Sciclient : Rebased and Regenerated Sciclient Binaries
- Regenerated sclient binaries after rebasing
- Validated memcpy with latest binaries on j721e/j7200 mcu1_0 and mcu2_0 with noboot and uart boot.
Signed-off-by: Don Dominic <a0486429@ti.com>
- Regenerated sclient binaries after rebasing
- Validated memcpy with latest binaries on j721e/j7200 mcu1_0 and mcu2_0 with noboot and uart boot.
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-9432] J7200 BoardCfg: Update to the latest auto-generated from SysConfig/k3-resource-partitioning
- This includes the updates in the following:
- Remove shared allocation for MCU R5
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview
- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc
- This includes the updates in the following:
- Remove shared allocation for MCU R5
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview
- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc
[PDK-9432] J721E BoardCfg: Update to the latest auto-generated from SysConfig/k3-resource-partitioning
- This includes the updates in the following:
- Remove shared allocation for MCU R5
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview
- Increase virt id range for A72_2
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/12/overview
- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc
- This includes the updates in the following:
- Remove shared allocation for MCU R5
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview
- Increase virt id range for A72_2
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/12/overview
- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc
[PDK-9432] Sciclient : Updates to support BoardCfg with mcu1_0 non-secure host id entries
- Do not force mcu1_0 to be in secure mode for all cases
- Set to secure mode in case the message is to be forwarded
- Also The MCU1_0 will always be secure when trying to send the message to the TIFS directly to avoid self blocking.
Signed-off-by: Don Dominic <a0486429@ti.com>
- Do not force mcu1_0 to be in secure mode for all cases
- Set to secure mode in case the message is to be forwarded
- Also The MCU1_0 will always be secure when trying to send the message to the TIFS directly to avoid self blocking.
Signed-off-by: Don Dominic <a0486429@ti.com>
udma_event.c: Do not pass a NULL resp payload for the Sciclient_rmUdmapGcfgCfg function
Response payload should not be NULL. The API fails in that case
Fixes: PDK-9431
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Response payload should not be NULL. The API fails in that case
Fixes: PDK-9431
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
copied binary and built firmware header .h file
PDK-6534 : un-expected ISR if the timer were running, before creation
If the timer was running before the timer was created, on creation
especially in user start mode, an ISR would be triggered before
the timer was started.
Root cause : The timer module is not reset before the ISR registration
so, if the timer count lapses after creation but before starting the
the timer, an FALSE isr would be triggered.
Fix: Reset the timer peripheral at create time. This ensures that
counter is disabled and interrupt notification is disabled
Testing: Tested both baremetal & ti rtos unit test of the timer, it
works as expected. OSAL_Baremetal_TestApp and OSAL_TestApp works as
expected
Signed-off-by: Sujith S <sujith.s@ti.com>
If the timer was running before the timer was created, on creation
especially in user start mode, an ISR would be triggered before
the timer was started.
Root cause : The timer module is not reset before the ISR registration
so, if the timer count lapses after creation but before starting the
the timer, an FALSE isr would be triggered.
Fix: Reset the timer peripheral at create time. This ensures that
counter is disabled and interrupt notification is disabled
Testing: Tested both baremetal & ti rtos unit test of the timer, it
works as expected. OSAL_Baremetal_TestApp and OSAL_TestApp works as
expected
Signed-off-by: Sujith S <sujith.s@ti.com>
3 years agoMMC: Build break fix REL.CORESDK.07.01.06.03 REL.CORESDK.07.01.06.04 REL.CORESDK.07.03.00.18 REL.CORESDK.07.03.00.19
MMC: Build break fix
Signed-off-by: Sujith S <sujith.s@ti.com>
Signed-off-by: Sujith S <sujith.s@ti.com>
freertos: posix support only in git and not in rel pkg
remove support for freertos posix in release package
support only in development git folder
Signed-off-by: Badri S <badri@ti.com>
remove support for freertos posix in release package
support only in development git folder
Signed-off-by: Badri S <badri@ti.com>
PDK-7484 : Disabled HS400 from the supported modes list
As per j721e errata (i2024) HS 400 is not supported
on mmc-sd instance 0
Tested MMCSD Regressions on j721e ES 1.0 EVM
ΓΌ01000000011a00006a3765730000000000000000475020200200010002000100CCSBL Revision: 01.00.10.00 (Mar 6 2021 - 01:34:19)
Waiting for tifs.bin ...
CCTIFS ver: 21.1.0--v2021.01 (Terrific Llam
Waiting for multicore app ...
CCCCalibration Start
Calibration: Ticks per ms is 999994
Calibration Completed
:
:
MMCSD Regression Test Menu
--------------------------
Test ID: Description Powercycle Required?
0 DS Mode 1-bit Test No
1 DS Mode Test No
2 HS Mode Test No
8 SDR12 Mode Test Yes
9 SDR25 Mode Test Yes
10 SDR50 Mode Test Yes
11 DDR50 Mode Test Yes
13 Default Unit Test (Max speed) Yes
-1 All non powercycle tests No
-2 Exit the regression test No
Please enter a test ID from the above list: -2
Test ID Entered = -2
Exiting the regression test
All tests have PASSED
3/3 tests passed
Signed-off-by: Sujith S <sujith.s@ti.com>
As per j721e errata (i2024) HS 400 is not supported
on mmc-sd instance 0
Tested MMCSD Regressions on j721e ES 1.0 EVM
ΓΌ01000000011a00006a3765730000000000000000475020200200010002000100CCSBL Revision: 01.00.10.00 (Mar 6 2021 - 01:34:19)
Waiting for tifs.bin ...
CCTIFS ver: 21.1.0--v2021.01 (Terrific Llam
Waiting for multicore app ...
CCCCalibration Start
Calibration: Ticks per ms is 999994
Calibration Completed
:
:
MMCSD Regression Test Menu
--------------------------
Test ID: Description Powercycle Required?
0 DS Mode 1-bit Test No
1 DS Mode Test No
2 HS Mode Test No
8 SDR12 Mode Test Yes
9 SDR25 Mode Test Yes
10 SDR50 Mode Test Yes
11 DDR50 Mode Test Yes
13 Default Unit Test (Max speed) Yes
-1 All non powercycle tests No
-2 Exit the regression test No
Please enter a test ID from the above list: -2
Test ID Entered = -2
Exiting the regression test
All tests have PASSED
3/3 tests passed
Signed-off-by: Sujith S <sujith.s@ti.com>
Build Fix: Fix build issues with Board DDR Temp Monitor
- Not applicable for mpu1_0
- Removed #ifdef for BUILD_MCU1_0 when added support for main R5 cores
https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/commits/8e4f1ae9e303b3627fbe71b81bde75b6dd601a07#packages/ti/board/src/j721e_evm/board_ddrtempmonitor.c
- But should have protected with MCU ifdef
- Fixed by adding #ifdef for BUILD_MCU
Signed-off-by: Don Dominic <a0486429@ti.com>
- Not applicable for mpu1_0
- Removed #ifdef for BUILD_MCU1_0 when added support for main R5 cores
https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/commits/8e4f1ae9e303b3627fbe71b81bde75b6dd601a07#packages/ti/board/src/j721e_evm/board_ddrtempmonitor.c
- But should have protected with MCU ifdef
- Fixed by adding #ifdef for BUILD_MCU
Signed-off-by: Don Dominic <a0486429@ti.com>
3 years ago[PDK-9317][PDK-9316] Board: DDR: Updates in Board DDR thermal monitoring REL.CORESDK.07.01.06.02
[PDK-9317][PDK-9316] Board: DDR: Updates in Board DDR thermal monitoring
- Query from BoardCfg to get the allowed core interrupt IRQ idx
- Add support for other R5F cores
Signed-off-by: Don Dominic <a0486429@ti.com>
- Query from BoardCfg to get the allowed core interrupt IRQ idx
- Add support for other R5F cores
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-9312] FreeeRTOS: Addressed review comments
- Updated linker file to use OCMC/DDR instead of MSMC
- Many times apps/customer copy our linker and struggled due to use of MSMC for MCU R5 apps
Signed-off-by: Don Dominic <a0486429@ti.com>
- Updated linker file to use OCMC/DDR instead of MSMC
- Many times apps/customer copy our linker and struggled due to use of MSMC for MCU R5 apps
Signed-off-by: Don Dominic <a0486429@ti.com>
Build Fix: sciclient_firmware_boot_TestApp linker updates to enable debug build
- '.cinit' program will not fit into available memory in OCMRAM
- Moved bss to TCMB from OCMRAM
Signed-off-by: Don Dominic <a0486429@ti.com>
- '.cinit' program will not fit into available memory in OCMRAM
- Moved bss to TCMB from OCMRAM
Signed-off-by: Don Dominic <a0486429@ti.com>
FreeRTOS: UT Build Fix
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: Don Dominic <a0486429@ti.com>
freertos: jenkins build fixes
jenkins build fixes
Signed-off-by: Badri S <badri@ti.com>
jenkins build fixes
Signed-off-by: Badri S <badri@ti.com>
[PDK-9312] OSAL: FreeRTOS: Added osal_freertos support for J7ES/J7VCL/AM65xx
- osal_freertos library added for j721e/j7200/am65xx
Signed-off-by: Don Dominic <a0486429@ti.com>
- osal_freertos library added for j721e/j7200/am65xx
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-9312] FreeeRTOS: Added support for freertos on all R5F cores in J7ES/J7VCL/AM65xx
- Enable all R5F cores in am65xx/j7200/j721e
- Added config files for each core with unique DMTimer id
- Add support to copy freertos reset vectors to atcm
- implemented inside 'xPortStartScheduler' before calling 'vPortRestoreTaskContext()'
- Update config file to add define to enable/disable copy of freertos reset vectors to atcm
- By default Enabled for AM65xx since vectors are placed in OCMRAM in the linker file since core reset will clear the atcm
- Updated freertos kernel paths
- Minor cleanups
Signed-off-by: Don Dominic <a0486429@ti.com>
- Enable all R5F cores in am65xx/j7200/j721e
- Added config files for each core with unique DMTimer id
- Add support to copy freertos reset vectors to atcm
- implemented inside 'xPortStartScheduler' before calling 'vPortRestoreTaskContext()'
- Update config file to add define to enable/disable copy of freertos reset vectors to atcm
- By default Enabled for AM65xx since vectors are placed in OCMRAM in the linker file since core reset will clear the atcm
- Updated freertos kernel paths
- Minor cleanups
Signed-off-by: Don Dominic <a0486429@ti.com>
added osal lib for free rtos
- added osal lib
- added semephore osal implementation
- other components of osal use the nonos implementation
- added taskp in freertos
- added memoryP in freertos
- added memoryP test in osal testapp
- added delay implementation using TaskP_sleep
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- added osal lib
- added semephore osal implementation
- other components of osal use the nonos implementation
- added taskp in freertos
- added memoryP in freertos
- added memoryP test in osal testapp
- added delay implementation using TaskP_sleep
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
freertos: fix r5f pmu counter overflow
ensure we periodically check for PMU cycle
counter overflow so that we dont miss incrementing
overflow counter.
Signed-off-by: Badri S <badri@ti.com>
ensure we periodically check for PMU cycle
counter overflow so that we dont miss incrementing
overflow counter.
Signed-off-by: Badri S <badri@ti.com>
freertos: disable interrupt preemption for r5
Disable interrupt preemption for r5 until correct
interrupt preemption support
Signed-off-by: Badri S <badri@ti.com>
Disable interrupt preemption for r5 until correct
interrupt preemption support
Signed-off-by: Badri S <badri@ti.com>
freertos:c66x fixes to ensure csl_vect is not linked in
ensure csl_vect is not wrongly linked in resulting in
interrupts not being serviced by freertos vecs
Signed-off-by: Badri S <badri@ti.com>
ensure csl_vect is not wrongly linked in resulting in
interrupts not being serviced by freertos vecs
Signed-off-by: Badri S <badri@ti.com>
freertos: remove dpl folder and move to port folder
remove dpl folder and move files under port folder
also make test folder freertos specific
Signed-off-by: Badri S <badri@ti.com>
remove dpl folder and move files under port folder
also make test folder freertos specific
Signed-off-by: Badri S <badri@ti.com>
freertos: support for j721e,j7200,am65xx SoCs
Support added for am65xx,j721e,am65xx SoCs
freertos lib made core specific instead of isa
so that freeRTOS config can include core specific
header file
Signed-off-by: Badri S <badri@ti.com>
Support added for am65xx,j721e,am65xx SoCs
freertos lib made core specific instead of isa
so that freeRTOS config can include core specific
header file
Signed-off-by: Badri S <badri@ti.com>
freertos: support for r5f core
freertos support for r5f core ported from mcu_plus_sdk
Signed-off-by: Badri S <badri@ti.com>
freertos support for r5f core ported from mcu_plus_sdk
Signed-off-by: Badri S <badri@ti.com>
freertos: support for c66x core for freertos
freertos c66x port support
Signed-off-by: Badri S <badri@ti.com>
freertos c66x port support
Signed-off-by: Badri S <badri@ti.com>
PDK-7013: Removes VTM workaround for J7ES PG1.1
Removes default workaround flag for J7ES VTM.
Signed-off-by: Erick Narvaez <e-narvaez@ti.com>
Removes default workaround flag for J7ES VTM.
Signed-off-by: Erick Narvaez <e-narvaez@ti.com>
added adcbuf driver for AWR294x SOC
OSPI: PHY tuning benchmarking
- added a macro which can be enabled to get the logs of how much time the PHY tuning elapsed
- switched to UART prints
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- added a macro which can be enabled to get the logs of how much time the PHY tuning elapsed
- switched to UART prints
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
timeSync: v2: Explicitly set no traffic class
The newly added txPktTc field of the Enet DMA packet structure is used
for ICSSG but it's not applicable for CPSW. Hence, it's explicitly set
to indicate that no traffic class is to be used.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
The newly added txPktTc field of the Enet DMA packet structure is used
for ICSSG but it's not applicable for CPSW. Hence, it's explicitly set
to indicate that no traffic class is to be used.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
PDK-9240:Board: Fix for DDR init hang issue on j721e evm during warm reset
- DDR initialization is hanging during the warm reset which is caused
by PLL bypass function. Need to unlock the PLL registers for access
during the warm reset.
- DDR initialization is hanging during the warm reset which is caused
by PLL bypass function. Need to unlock the PLL registers for access
during the warm reset.
PRSDK-8813: Board/USB: Updated AM65xx SerDes configurations
- CSL SerDes USB configurations are updated to fix enumeration failures.
Updated the board library and USB driver to align with updated SerDes
configurations.
- CSL SerDes USB configurations are updated to fix enumeration failures.
Updated the board library and USB driver to align with updated SerDes
configurations.
board - Missing enum and fix include path
Signed-off-by: Prasad Jondhale <prasad.jondhale@ti.com>
Signed-off-by: Prasad Jondhale <prasad.jondhale@ti.com>
[PDK-9404] OSAL: Fix TIMERP_TIMER_FREQ_LO for J7200
- TIMERP_TIMER_FREQ_LO defined in osal_soc.h for J7200 is wrong.(25MHz)
- Input Crystal Frequency for j7200 is 19.2MHz and default Timer clk_sel 0(HFOSC0_CLKOUT) will be 19.2MHz
Signed-off-by: Don Dominic <a0486429@ti.com>
- TIMERP_TIMER_FREQ_LO defined in osal_soc.h for J7200 is wrong.(25MHz)
- Input Crystal Frequency for j7200 is 19.2MHz and default Timer clk_sel 0(HFOSC0_CLKOUT) will be 19.2MHz
Signed-off-by: Don Dominic <a0486429@ti.com>
3 years ago[PDK-9315] Updating BIOS and XDC REL.CORESDK.07.03.00.13 REL.CORESDK.07.03.00.14 REL.CORESDK.07.03.00.15 REL.CORESDK.07.03.00.16 REL.CORESDK.07.03.01.03 REL.CORESDK.07.03.01.04 REL.CORESDK.07.03.01.05 REL.CORESDK.07.03.01.06
[PDK-9315] Updating BIOS and XDC
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
[BugFix] PDK-8886: pdk_examples build fails on Windows
- armstrip or strip6x on windows is not able to delete the strip file
if it already present.
- $(RM) is set to rm -f so will not generate error if the file is not
present.
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- armstrip or strip6x on windows is not able to delete the strip file
if it already present.
- $(RM) is set to rm -f so will not generate error if the file is not
present.
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
added build support for awr294x
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
3 years agoPDK-9337: Fix for Clocking on J7VCL to use fracf pll calibration REL.CORESDK.07.03.00.10 REL.CORESDK.07.03.00.11 REL.CORESDK.07.03.00.12 REL.CORESDK.07.03.01.02
PDK-9337: Fix for Clocking on J7VCL to use fracf pll calibration
Fix for clocking on J7VCL to use fracf pll calibration
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fix for clocking on J7VCL to use fracf pll calibration
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
osal: baremetal build fix for mcu1_1
OSAL baremetal build fix for mcu1_1
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
OSAL baremetal build fix for mcu1_1
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Build Fix
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
3 years ago[PDK-9328] OSPI: Binary search instead of linear search for PHY tuning window REL.CORESDK.07.03.00.08
[PDK-9328] OSPI: Binary search instead of linear search for PHY tuning window
- Previous implementation was a linear search algorithm
- Occassional failures observed
- Replaced by a binary search algorithm
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- Previous implementation was a linear search algorithm
- Occassional failures observed
- Replaced by a binary search algorithm
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
SPI packaging error fix
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
CGT update for C7x
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
Revert "[PDK-9315] Updating the BIOS version to 06.83.02.07"
This reverts commit dca947d3294daa19d842386afa038ef797e35e1b.
This reverts commit dca947d3294daa19d842386afa038ef797e35e1b.
Revert "updating XDC and C7x CGT tool version"
This reverts commit e738709d0f9e45ac20b3092009ed41a49c2b2aea.
This reverts commit e738709d0f9e45ac20b3092009ed41a49c2b2aea.
3 years agosciclient: docs: design: Update to add Domain reset information REL.CORESDK.07.03.00.02 REL.CORESDK.07.03.00.03 REL.CORESDK.07.03.00.04
sciclient: docs: design: Update to add Domain reset information
Doc update to add domain groups reset API information
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Doc update to add domain groups reset API information
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for Domain resets in Sciclient PM
Support for Domain Resets in Sciclient PM
Fixes: PDK-9326
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for Domain Resets in Sciclient PM
Fixes: PDK-9326
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
updating XDC and C7x CGT tool version
Signed-off-by: ankur <ankurbaranwal@ti.com>
Signed-off-by: ankur <ankurbaranwal@ti.com>
[PDK-9315] Updating the BIOS version to 06.83.02.07
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
Migrating to SYSFW version v2021.01
v2021.01 migration
v2021.01 migration
ETHFW-607: j7200_evm: Bypass SerDes config for Eth if already configured
Don't configure SerDes if it has already been configured, i.e. by
u-boot. This enables EthFw to transparently work in Linux boot and
CCS boot.
In Linux boot, u-boot will configure SerDes (i.e. for PCIe and Ethernet
sharing) and at a later point load EthFw, EthFw will not attempt to
reconfigure SerDes.
In CCS boot, EthFw will configure SerDes.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Don't configure SerDes if it has already been configured, i.e. by
u-boot. This enables EthFw to transparently work in Linux boot and
CCS boot.
In Linux boot, u-boot will configure SerDes (i.e. for PCIe and Ethernet
sharing) and at a later point load EthFw, EthFw will not attempt to
reconfigure SerDes.
In CCS boot, EthFw will configure SerDes.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
3 years agoPDK-9050: Board: Fix for board PLL clock configuration failure on j721e REL.CORESDK.07.03.00.01
PDK-9050: Board: Fix for board PLL clock configuration failure on j721e
- Removed the redundant clock configurations for McASP & ADC
- Removed the core PLL configurations as they are done by default
- Updated the clock IDs for some of the modules to fix the errors
- Removed the redundant clock configurations for McASP & ADC
- Removed the core PLL configurations as they are done by default
- Updated the clock IDs for some of the modules to fix the errors
Migrating to SYSFW version v2020.08d
Migrating to SYSFW v2020.08d
Migrating to SYSFW v2020.08d
sysfw_migrate.sh: Update to have support for generation of ES1.1 images
Support for generation of ES1.1 HS tifs images
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for generation of ES1.1 HS tifs images
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Firmware Header Gen updates for ES1.1
Support for ES1.1 hs binary generation
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for ES1.1 hs binary generation
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
PDK-9050 : Compute core clock config is removed
The A72, R5F, functional clock should not be reconfigured
disabled the same.
Skipped clock config for McASP and Adc
Will be addressed in subsequent commits
Signed-off-by: sujith <sujith.s@ti.com>
The A72, R5F, functional clock should not be reconfigured
disabled the same.
Skipped clock config for McASP and Adc
Will be addressed in subsequent commits
Signed-off-by: sujith <sujith.s@ti.com>
Add build support for awr294x
- Added basic build support
- build for csl added with tpr12 soc files
- build enabled for board lib with tpr12 files. build not enabled for
board Examples / utils.
- build for few drivers enabled like edma, uart which are used by
common examples
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- Added basic build support
- build for csl added with tpr12 soc files
- build enabled for board lib with tpr12 files. build not enabled for
board Examples / utils.
- build for few drivers enabled like edma, uart which are used by
common examples
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
UDMA: OSPI Example: Fix Porting for Cypress Flash(J7200/AM64x)
- Added new test to write PHY tuning data to flash memory
- Writes phy tuning data to last 128B of Flash memory
- This region should be made non-cacheable
- Include new phy tuning algo source file from CSL OSPI Common
- Support for new phy tuning(phyConfig) for devices with Cypress flash(AM64x/J7200)
- Enable phyPiplene mode for DAC DMA Read
- Proper switching from INDAC to DAC mode, after Write operation
- For devices with Cypress Flash in which DAC write is not supported
The test writes in INDAC mode and reads in DAC DMA mode
Here the switch to DAC mode was not Proper.
- Just calling CSL_ospiDacEnable was not enough
- Added flag to Disable CacheOps in Real-time loop
- To enable performance measurement without including CacheInv
- Disabled by default
- Clear the interrupt after breaking from the TR Reload Perpetual loop.
- During channel forced tear-down to break from the TR Reload Perpetual loop,
DMA will complete the already reloaded TR.
- This results in setting the interrupt status register after this transfer completion.
- Hence clear the interrupt after this.
- Else it will result in odd behavior with successive UDMA transfers
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- Added new test to write PHY tuning data to flash memory
- Writes phy tuning data to last 128B of Flash memory
- This region should be made non-cacheable
- Include new phy tuning algo source file from CSL OSPI Common
- Support for new phy tuning(phyConfig) for devices with Cypress flash(AM64x/J7200)
- Enable phyPiplene mode for DAC DMA Read
- Proper switching from INDAC to DAC mode, after Write operation
- For devices with Cypress Flash in which DAC write is not supported
The test writes in INDAC mode and reads in DAC DMA mode
Here the switch to DAC mode was not Proper.
- Just calling CSL_ospiDacEnable was not enough
- Added flag to Disable CacheOps in Real-time loop
- To enable performance measurement without including CacheInv
- Disabled by default
- Clear the interrupt after breaking from the TR Reload Perpetual loop.
- During channel forced tear-down to break from the TR Reload Perpetual loop,
DMA will complete the already reloaded TR.
- This results in setting the interrupt status register after this transfer completion.
- Hence clear the interrupt after this.
- Else it will result in odd behavior with successive UDMA transfers
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[DSS APP][PDK-9214]DSS Display Examples is not working on eDP
- Issue:
- Display does not recognize the incoming stream and fps seems to be too high ~200
- Root Cause:
- DSS clock selection was wrong along with wrong frequency
- Earlier default clock selection was working for DSS which got changed over time, making EDP TC to fail
- DSS application shall do this configuration rather than relying on default configuration
- Resolution:
- Select proper clock for DPI
- Configure following clocks
- TISCI_DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK to 148.5 MHz
- TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK to 148.5 MHz
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Issue:
- Display does not recognize the incoming stream and fps seems to be too high ~200
- Root Cause:
- DSS clock selection was wrong along with wrong frequency
- Earlier default clock selection was working for DSS which got changed over time, making EDP TC to fail
- DSS application shall do this configuration rather than relying on default configuration
- Resolution:
- Select proper clock for DPI
- Configure following clocks
- TISCI_DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK to 148.5 MHz
- TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK to 148.5 MHz
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[PDK-9074]OSPI: Adding a summary of OSPI modes supported by each EVM
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
OSPI: J721e: Fix for large appimage size
- marked the txBuf and rxBuf as a benchmark buffer section
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- marked the txBuf and rxBuf as a benchmark buffer section
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Revert "Revert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain""
This reverts commit 9ac60cdd6d46fd7162a07f1f3a3351884eb9439f.
The fix was reverted due to code freeze. Applying the fix now that the release tag has been created.
This reverts commit 9ac60cdd6d46fd7162a07f1f3a3351884eb9439f.
The fix was reverted due to code freeze. Applying the fix now that the release tag has been created.
Mailbox: Example: Fix debug build failure in daily build
Increase the section size in liner file.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Increase the section size in liner file.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Fix for UDMA tests failing after fix for PDK-9013
Fixes in Sciclient.c where the respHdr is not populated in the respPayload.
The Sciserver logic looks for the payload to have the flags set correctly and because the flags were never copied in the case when the message was forwarded to the TIFS, the response is falsely reported to the calling function.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fixes in Sciclient.c where the respHdr is not populated in the respPayload.
The Sciserver logic looks for the payload to have the flags set correctly and because the flags were never copied in the case when the message was forwarded to the TIFS, the response is falsely reported to the calling function.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 years agoRevert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain" REL.CORESDK.07.02.01.11
Revert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain"
This reverts commit 9540772ac3c2b1ff082447675b23c4bfe75842e7.
Temporarily reverting it as this patch came in middle of AM64x RC.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
This reverts commit 9540772ac3c2b1ff082447675b23c4bfe75842e7.
Temporarily reverting it as this patch came in middle of AM64x RC.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain
- added a soc init function to update interrupt number at run time
- added a config soc interrupt path function to set interrupt path
- fixes interrupt hang issue on j721e and j7200
- removed WA of using polling mode in UT
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- added a soc init function to update interrupt number at run time
- added a config soc interrupt path function to set interrupt path
- fixes interrupt hang issue on j721e and j7200
- removed WA of using polling mode in UT
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 years agoBoard: Added GTC frequency ID config in am64x board library REL.CORESDK.07.02.01.09 REL.CORESDK.07.02.01.10
Board: Added GTC frequency ID config in am64x board library
Board: AM64x: Update GTC clk freq to 200 MHz
Changes GTC input functional clock from the default freq,
of 225 MHz, to the HLOS expected value of 200 MHz.
Solves an issue with SBL booting Linux on AM64x.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Changes GTC input functional clock from the default freq,
of 225 MHz, to the HLOS expected value of 200 MHz.
Solves an issue with SBL booting Linux on AM64x.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Board: Removed unused code in am64x board library
- Updated copyright banners
- Updated copyright banners
SBL: AM64x: Change sbl_ospi_img_hlos to use Non-DMA option
Builds the HLOS variant of SBL for OSPI boot mode to use
memcpy for OSPI transfers, instead of using BCDMA. This also
causes OSPI interface to be used without PHY pipelining.
Workaround for possible resource contention with Linux.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Builds the HLOS variant of SBL for OSPI boot mode to use
memcpy for OSPI transfers, instead of using BCDMA. This also
causes OSPI interface to be used without PHY pipelining.
Workaround for possible resource contention with Linux.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
PDK-9257: SBL: AM64x: Fix M4F mem section loading for OSPI boot
Fixes a problem with using the BCDMA (in OSPI boot mode) to load
memory sections of the Cortex-M4F.
Works around this issue by checking for M4F memory section addresses
and using memcpy (from OSPI flash to M4 mem), instead of doing DMA.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Fixes a problem with using the BCDMA (in OSPI boot mode) to load
memory sections of the Cortex-M4F.
Works around this issue by checking for M4F memory section addresses
and using memcpy (from OSPI flash to M4 mem), instead of doing DMA.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
PDK-9257: SBL: AM64x: Fix OSPI boot w/ DMA when using MCU1_0 TCMs
Need to use SoC-level addresses for R5F0_0 local TCM memories
as well on OSPI boot mode with DMA.
Changes SBL to use SoC-level address for all loading to local
TCM memories of MCU1_0.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Need to use SoC-level addresses for R5F0_0 local TCM memories
as well on OSPI boot mode with DMA.
Changes SBL to use SoC-level address for all loading to local
TCM memories of MCU1_0.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
PDK-8885: Board: Created different init/deinit clock groups for am64x evm board library
- Board library for am64x evm is updated to provide the flexibility of
choosing clock modules which will be enabled/disabled during the boot process.
Two different clock groups are created to choose between RTOS normal boot flow
and RTOS+HLOS boot flow.
Clock resources which are used during RTOS boot can be released using
Board_releaseResource function before switching to HLOS
- Board library for am64x evm is updated to provide the flexibility of
choosing clock modules which will be enabled/disabled during the boot process.
Two different clock groups are created to choose between RTOS normal boot flow
and RTOS+HLOS boot flow.
Clock resources which are used during RTOS boot can be released using
Board_releaseResource function before switching to HLOS
Board: Fix for am64x evm stress test build errors
AM64x: launch.js update for latest CSP
Updates to launch.js based on latest CSP package made for public consumption.
When R5 is connected, the DDR will not be configured automatically.
After the sciclient_ccs_init runs, the launch.js explicitly calls
AM64_DDR_Initialization_ECC_Disabled() to configure the DDR.
CSP commit:
https://bitbucket.itg.ti.com/projects/CPHWA/repos/k3_ccs/commits/662bc078f8ccee26024a80bd648803872a31b5e6
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Updates to launch.js based on latest CSP package made for public consumption.
When R5 is connected, the DDR will not be configured automatically.
After the sciclient_ccs_init runs, the launch.js explicitly calls
AM64_DDR_Initialization_ECC_Disabled() to configure the DDR.
CSP commit:
https://bitbucket.itg.ti.com/projects/CPHWA/repos/k3_ccs/commits/662bc078f8ccee26024a80bd648803872a31b5e6
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
AM64x Build Fix: Use CORELISTARM for UART baremetal app
- Use drvuart_am64x_CORELISTARM for UART_Baremetal_TestApp
- All other UART apps for am64x was already using drvuart_am64x_CORELISTARM
Signed-off-by: Don Dominic <a0486429@ti.com>
- Use drvuart_am64x_CORELISTARM for UART_Baremetal_TestApp
- All other UART apps for am64x was already using drvuart_am64x_CORELISTARM
Signed-off-by: Don Dominic <a0486429@ti.com>
BUILD: AM64x: Add missing mpu1_1 in the am64x core list
Update core lists in both BUILD and SBL to match the cores
that are used for building various test cases.
Fixes build issue for the sbl_multicore_amp boot test case
for am64x_evm by including the last "mpu1_1" core that was
previously missing.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Update core lists in both BUILD and SBL to match the cores
that are used for building various test cases.
Fixes build issue for the sbl_multicore_amp boot test case
for am64x_evm by including the last "mpu1_1" core that was
previously missing.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
[PDK-9033] UDMA Example : Fix UDMA ADC example on AM64x mpu1_0
- Clear destination buffer and cache writeback
Signed-off-by: Don Dominic <a0486429@ti.com>
- Clear destination buffer and cache writeback
Signed-off-by: Don Dominic <a0486429@ti.com>
am64x: Enable appimage generation for mcspi tests
Enable appimage generation for test cases that apply to am64x.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Enable appimage generation for test cases that apply to am64x.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
PDK-9175: SBL: AM64x: Fix MMCSD boot when using MCU1_0 TCMs
Adds address translation to SoC level addresses of MCU1_0
local TCMs when using MMCSD ADMA to copy appimage sections
to MCU1_0 ATCM / BTCM.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Adds address translation to SoC level addresses of MCU1_0
local TCMs when using MMCSD ADMA to copy appimage sections
to MCU1_0 ATCM / BTCM.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
[PDK-9033] UDMA Example : Fix UDMA ADC example on AM64x
- Moved PDMA Config and chEnable to App_create
- Moved chDiable to App_delete
- Added VirtToPhy/PhyToVirt conversion before submitting to/after receiving from DMA Controller
- Basic Porting for LCDMA
- Added RA Type macro for Teardown Completion Queue, Teardown Event and Completion Ring Mem
Signed-off-by: Don Dominic <a0486429@ti.com>
- Moved PDMA Config and chEnable to App_create
- Moved chDiable to App_delete
- Added VirtToPhy/PhyToVirt conversion before submitting to/after receiving from DMA Controller
- Basic Porting for LCDMA
- Added RA Type macro for Teardown Completion Queue, Teardown Event and Completion Ring Mem
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-7995] UDMA: Simplify UDMA RM Configuration for AM64x
- Simplify RM Configuration by querying from defaultBoardCfg
- Using #Sciclient_rmGetResourceRange to populate #Udma_RmInitPrms
- Removes all hard-codings in udma_rmcfg.c
- Splits shared resources like GlobalEvents/VINTR across BCDMA/PKTDMA Instances
based on the prms in #Udma_RmSharedResPrms (UDMA RM Shared Resource parameters)
- User can override default UDMA RM Shared Resource parameters, using Udma_rmGetSharedResPrms API
- Moved UdmaRmInitPrms_init to 'udma_rmcfg_common.c' in 'soc' folder.
This API will return error, if it fails to init #Udma_RmInitPrms
- New API to to retun TISCI Core Dev ID 'Udma_getCoreSciDevId'
- To be reused in 'UdmaRmInitPrms_init'
- For devices like AM64x (LCDMA), One to one mapping exists from Virtual Interrupts to Core Interrupts
So translate to corresponding range using 'Sciclient_rmIrqTranslateIaOutput'.
Since there are no Interrupt Routers, startIrIntr/numIrIntr refers to core interrupt itslef.
Signed-off-by: Don Dominic <a0486429@ti.com>
- Simplify RM Configuration by querying from defaultBoardCfg
- Using #Sciclient_rmGetResourceRange to populate #Udma_RmInitPrms
- Removes all hard-codings in udma_rmcfg.c
- Splits shared resources like GlobalEvents/VINTR across BCDMA/PKTDMA Instances
based on the prms in #Udma_RmSharedResPrms (UDMA RM Shared Resource parameters)
- User can override default UDMA RM Shared Resource parameters, using Udma_rmGetSharedResPrms API
- Moved UdmaRmInitPrms_init to 'udma_rmcfg_common.c' in 'soc' folder.
This API will return error, if it fails to init #Udma_RmInitPrms
- New API to to retun TISCI Core Dev ID 'Udma_getCoreSciDevId'
- To be reused in 'UdmaRmInitPrms_init'
- For devices like AM64x (LCDMA), One to one mapping exists from Virtual Interrupts to Core Interrupts
So translate to corresponding range using 'Sciclient_rmIrqTranslateIaOutput'.
Since there are no Interrupt Routers, startIrIntr/numIrIntr refers to core interrupt itslef.
Signed-off-by: Don Dominic <a0486429@ti.com>
PDK-5153: Board: Updated stress tests for am64x evm to fix the failures
PDK-8367: Board: Updated SPI EEPROM diag test for AM64x EVM
PDK-5115: Board: Corrected gpio pin mapping for am64x evm exp header test