freertos: disable interrupt preemption for r5
Disable interrupt preemption for r5 until correct
interrupt preemption support
Signed-off-by: Badri S <badri@ti.com>
Disable interrupt preemption for r5 until correct
interrupt preemption support
Signed-off-by: Badri S <badri@ti.com>
freertos:c66x fixes to ensure csl_vect is not linked in
ensure csl_vect is not wrongly linked in resulting in
interrupts not being serviced by freertos vecs
Signed-off-by: Badri S <badri@ti.com>
ensure csl_vect is not wrongly linked in resulting in
interrupts not being serviced by freertos vecs
Signed-off-by: Badri S <badri@ti.com>
freertos: remove dpl folder and move to port folder
remove dpl folder and move files under port folder
also make test folder freertos specific
Signed-off-by: Badri S <badri@ti.com>
remove dpl folder and move files under port folder
also make test folder freertos specific
Signed-off-by: Badri S <badri@ti.com>
freertos: support for j721e,j7200,am65xx SoCs
Support added for am65xx,j721e,am65xx SoCs
freertos lib made core specific instead of isa
so that freeRTOS config can include core specific
header file
Signed-off-by: Badri S <badri@ti.com>
Support added for am65xx,j721e,am65xx SoCs
freertos lib made core specific instead of isa
so that freeRTOS config can include core specific
header file
Signed-off-by: Badri S <badri@ti.com>
freertos: support for r5f core
freertos support for r5f core ported from mcu_plus_sdk
Signed-off-by: Badri S <badri@ti.com>
freertos support for r5f core ported from mcu_plus_sdk
Signed-off-by: Badri S <badri@ti.com>
freertos: support for c66x core for freertos
freertos c66x port support
Signed-off-by: Badri S <badri@ti.com>
freertos c66x port support
Signed-off-by: Badri S <badri@ti.com>
PDK-7013: Removes VTM workaround for J7ES PG1.1
Removes default workaround flag for J7ES VTM.
Signed-off-by: Erick Narvaez <e-narvaez@ti.com>
Removes default workaround flag for J7ES VTM.
Signed-off-by: Erick Narvaez <e-narvaez@ti.com>
added adcbuf driver for AWR294x SOC
OSPI: PHY tuning benchmarking
- added a macro which can be enabled to get the logs of how much time the PHY tuning elapsed
- switched to UART prints
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- added a macro which can be enabled to get the logs of how much time the PHY tuning elapsed
- switched to UART prints
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
timeSync: v2: Explicitly set no traffic class
The newly added txPktTc field of the Enet DMA packet structure is used
for ICSSG but it's not applicable for CPSW. Hence, it's explicitly set
to indicate that no traffic class is to be used.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
The newly added txPktTc field of the Enet DMA packet structure is used
for ICSSG but it's not applicable for CPSW. Hence, it's explicitly set
to indicate that no traffic class is to be used.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
PDK-9240:Board: Fix for DDR init hang issue on j721e evm during warm reset
- DDR initialization is hanging during the warm reset which is caused
by PLL bypass function. Need to unlock the PLL registers for access
during the warm reset.
- DDR initialization is hanging during the warm reset which is caused
by PLL bypass function. Need to unlock the PLL registers for access
during the warm reset.
PRSDK-8813: Board/USB: Updated AM65xx SerDes configurations
- CSL SerDes USB configurations are updated to fix enumeration failures.
Updated the board library and USB driver to align with updated SerDes
configurations.
- CSL SerDes USB configurations are updated to fix enumeration failures.
Updated the board library and USB driver to align with updated SerDes
configurations.
board - Missing enum and fix include path
Signed-off-by: Prasad Jondhale <prasad.jondhale@ti.com>
Signed-off-by: Prasad Jondhale <prasad.jondhale@ti.com>
[PDK-9404] OSAL: Fix TIMERP_TIMER_FREQ_LO for J7200
- TIMERP_TIMER_FREQ_LO defined in osal_soc.h for J7200 is wrong.(25MHz)
- Input Crystal Frequency for j7200 is 19.2MHz and default Timer clk_sel 0(HFOSC0_CLKOUT) will be 19.2MHz
Signed-off-by: Don Dominic <a0486429@ti.com>
- TIMERP_TIMER_FREQ_LO defined in osal_soc.h for J7200 is wrong.(25MHz)
- Input Crystal Frequency for j7200 is 19.2MHz and default Timer clk_sel 0(HFOSC0_CLKOUT) will be 19.2MHz
Signed-off-by: Don Dominic <a0486429@ti.com>
3 years ago[PDK-9315] Updating BIOS and XDC REL.CORESDK.07.03.00.13 REL.CORESDK.07.03.00.14 REL.CORESDK.07.03.00.15 REL.CORESDK.07.03.00.16 REL.CORESDK.07.03.01.03 REL.CORESDK.07.03.01.04 REL.CORESDK.07.03.01.05 REL.CORESDK.07.03.01.06
[PDK-9315] Updating BIOS and XDC
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
[BugFix] PDK-8886: pdk_examples build fails on Windows
- armstrip or strip6x on windows is not able to delete the strip file
if it already present.
- $(RM) is set to rm -f so will not generate error if the file is not
present.
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- armstrip or strip6x on windows is not able to delete the strip file
if it already present.
- $(RM) is set to rm -f so will not generate error if the file is not
present.
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
added build support for awr294x
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
3 years agoPDK-9337: Fix for Clocking on J7VCL to use fracf pll calibration REL.CORESDK.07.03.00.10 REL.CORESDK.07.03.00.11 REL.CORESDK.07.03.00.12 REL.CORESDK.07.03.01.02
PDK-9337: Fix for Clocking on J7VCL to use fracf pll calibration
Fix for clocking on J7VCL to use fracf pll calibration
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fix for clocking on J7VCL to use fracf pll calibration
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
osal: baremetal build fix for mcu1_1
OSAL baremetal build fix for mcu1_1
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
OSAL baremetal build fix for mcu1_1
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Build Fix
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
3 years ago[PDK-9328] OSPI: Binary search instead of linear search for PHY tuning window REL.CORESDK.07.03.00.08
[PDK-9328] OSPI: Binary search instead of linear search for PHY tuning window
- Previous implementation was a linear search algorithm
- Occassional failures observed
- Replaced by a binary search algorithm
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- Previous implementation was a linear search algorithm
- Occassional failures observed
- Replaced by a binary search algorithm
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
SPI packaging error fix
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
CGT update for C7x
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
Revert "[PDK-9315] Updating the BIOS version to 06.83.02.07"
This reverts commit dca947d3294daa19d842386afa038ef797e35e1b.
This reverts commit dca947d3294daa19d842386afa038ef797e35e1b.
Revert "updating XDC and C7x CGT tool version"
This reverts commit e738709d0f9e45ac20b3092009ed41a49c2b2aea.
This reverts commit e738709d0f9e45ac20b3092009ed41a49c2b2aea.
3 years agosciclient: docs: design: Update to add Domain reset information REL.CORESDK.07.03.00.02 REL.CORESDK.07.03.00.03 REL.CORESDK.07.03.00.04
sciclient: docs: design: Update to add Domain reset information
Doc update to add domain groups reset API information
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Doc update to add domain groups reset API information
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for Domain resets in Sciclient PM
Support for Domain Resets in Sciclient PM
Fixes: PDK-9326
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for Domain Resets in Sciclient PM
Fixes: PDK-9326
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
updating XDC and C7x CGT tool version
Signed-off-by: ankur <ankurbaranwal@ti.com>
Signed-off-by: ankur <ankurbaranwal@ti.com>
[PDK-9315] Updating the BIOS version to 06.83.02.07
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
Migrating to SYSFW version v2021.01
v2021.01 migration
v2021.01 migration
ETHFW-607: j7200_evm: Bypass SerDes config for Eth if already configured
Don't configure SerDes if it has already been configured, i.e. by
u-boot. This enables EthFw to transparently work in Linux boot and
CCS boot.
In Linux boot, u-boot will configure SerDes (i.e. for PCIe and Ethernet
sharing) and at a later point load EthFw, EthFw will not attempt to
reconfigure SerDes.
In CCS boot, EthFw will configure SerDes.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Don't configure SerDes if it has already been configured, i.e. by
u-boot. This enables EthFw to transparently work in Linux boot and
CCS boot.
In Linux boot, u-boot will configure SerDes (i.e. for PCIe and Ethernet
sharing) and at a later point load EthFw, EthFw will not attempt to
reconfigure SerDes.
In CCS boot, EthFw will configure SerDes.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
3 years agoPDK-9050: Board: Fix for board PLL clock configuration failure on j721e REL.CORESDK.07.03.00.01
PDK-9050: Board: Fix for board PLL clock configuration failure on j721e
- Removed the redundant clock configurations for McASP & ADC
- Removed the core PLL configurations as they are done by default
- Updated the clock IDs for some of the modules to fix the errors
- Removed the redundant clock configurations for McASP & ADC
- Removed the core PLL configurations as they are done by default
- Updated the clock IDs for some of the modules to fix the errors
Migrating to SYSFW version v2020.08d
Migrating to SYSFW v2020.08d
Migrating to SYSFW v2020.08d
sysfw_migrate.sh: Update to have support for generation of ES1.1 images
Support for generation of ES1.1 HS tifs images
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for generation of ES1.1 HS tifs images
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Firmware Header Gen updates for ES1.1
Support for ES1.1 hs binary generation
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for ES1.1 hs binary generation
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
PDK-9050 : Compute core clock config is removed
The A72, R5F, functional clock should not be reconfigured
disabled the same.
Skipped clock config for McASP and Adc
Will be addressed in subsequent commits
Signed-off-by: sujith <sujith.s@ti.com>
The A72, R5F, functional clock should not be reconfigured
disabled the same.
Skipped clock config for McASP and Adc
Will be addressed in subsequent commits
Signed-off-by: sujith <sujith.s@ti.com>
Add build support for awr294x
- Added basic build support
- build for csl added with tpr12 soc files
- build enabled for board lib with tpr12 files. build not enabled for
board Examples / utils.
- build for few drivers enabled like edma, uart which are used by
common examples
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- Added basic build support
- build for csl added with tpr12 soc files
- build enabled for board lib with tpr12 files. build not enabled for
board Examples / utils.
- build for few drivers enabled like edma, uart which are used by
common examples
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
UDMA: OSPI Example: Fix Porting for Cypress Flash(J7200/AM64x)
- Added new test to write PHY tuning data to flash memory
- Writes phy tuning data to last 128B of Flash memory
- This region should be made non-cacheable
- Include new phy tuning algo source file from CSL OSPI Common
- Support for new phy tuning(phyConfig) for devices with Cypress flash(AM64x/J7200)
- Enable phyPiplene mode for DAC DMA Read
- Proper switching from INDAC to DAC mode, after Write operation
- For devices with Cypress Flash in which DAC write is not supported
The test writes in INDAC mode and reads in DAC DMA mode
Here the switch to DAC mode was not Proper.
- Just calling CSL_ospiDacEnable was not enough
- Added flag to Disable CacheOps in Real-time loop
- To enable performance measurement without including CacheInv
- Disabled by default
- Clear the interrupt after breaking from the TR Reload Perpetual loop.
- During channel forced tear-down to break from the TR Reload Perpetual loop,
DMA will complete the already reloaded TR.
- This results in setting the interrupt status register after this transfer completion.
- Hence clear the interrupt after this.
- Else it will result in odd behavior with successive UDMA transfers
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- Added new test to write PHY tuning data to flash memory
- Writes phy tuning data to last 128B of Flash memory
- This region should be made non-cacheable
- Include new phy tuning algo source file from CSL OSPI Common
- Support for new phy tuning(phyConfig) for devices with Cypress flash(AM64x/J7200)
- Enable phyPiplene mode for DAC DMA Read
- Proper switching from INDAC to DAC mode, after Write operation
- For devices with Cypress Flash in which DAC write is not supported
The test writes in INDAC mode and reads in DAC DMA mode
Here the switch to DAC mode was not Proper.
- Just calling CSL_ospiDacEnable was not enough
- Added flag to Disable CacheOps in Real-time loop
- To enable performance measurement without including CacheInv
- Disabled by default
- Clear the interrupt after breaking from the TR Reload Perpetual loop.
- During channel forced tear-down to break from the TR Reload Perpetual loop,
DMA will complete the already reloaded TR.
- This results in setting the interrupt status register after this transfer completion.
- Hence clear the interrupt after this.
- Else it will result in odd behavior with successive UDMA transfers
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[DSS APP][PDK-9214]DSS Display Examples is not working on eDP
- Issue:
- Display does not recognize the incoming stream and fps seems to be too high ~200
- Root Cause:
- DSS clock selection was wrong along with wrong frequency
- Earlier default clock selection was working for DSS which got changed over time, making EDP TC to fail
- DSS application shall do this configuration rather than relying on default configuration
- Resolution:
- Select proper clock for DPI
- Configure following clocks
- TISCI_DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK to 148.5 MHz
- TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK to 148.5 MHz
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Issue:
- Display does not recognize the incoming stream and fps seems to be too high ~200
- Root Cause:
- DSS clock selection was wrong along with wrong frequency
- Earlier default clock selection was working for DSS which got changed over time, making EDP TC to fail
- DSS application shall do this configuration rather than relying on default configuration
- Resolution:
- Select proper clock for DPI
- Configure following clocks
- TISCI_DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK to 148.5 MHz
- TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK to 148.5 MHz
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[PDK-9074]OSPI: Adding a summary of OSPI modes supported by each EVM
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
OSPI: J721e: Fix for large appimage size
- marked the txBuf and rxBuf as a benchmark buffer section
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- marked the txBuf and rxBuf as a benchmark buffer section
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Revert "Revert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain""
This reverts commit 9ac60cdd6d46fd7162a07f1f3a3351884eb9439f.
The fix was reverted due to code freeze. Applying the fix now that the release tag has been created.
This reverts commit 9ac60cdd6d46fd7162a07f1f3a3351884eb9439f.
The fix was reverted due to code freeze. Applying the fix now that the release tag has been created.
Mailbox: Example: Fix debug build failure in daily build
Increase the section size in liner file.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Increase the section size in liner file.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Fix for UDMA tests failing after fix for PDK-9013
Fixes in Sciclient.c where the respHdr is not populated in the respPayload.
The Sciserver logic looks for the payload to have the flags set correctly and because the flags were never copied in the case when the message was forwarded to the TIFS, the response is falsely reported to the calling function.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fixes in Sciclient.c where the respHdr is not populated in the respPayload.
The Sciserver logic looks for the payload to have the flags set correctly and because the flags were never copied in the case when the message was forwarded to the TIFS, the response is falsely reported to the calling function.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 years agoRevert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain" REL.CORESDK.07.02.01.11
Revert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain"
This reverts commit 9540772ac3c2b1ff082447675b23c4bfe75842e7.
Temporarily reverting it as this patch came in middle of AM64x RC.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
This reverts commit 9540772ac3c2b1ff082447675b23c4bfe75842e7.
Temporarily reverting it as this patch came in middle of AM64x RC.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain
- added a soc init function to update interrupt number at run time
- added a config soc interrupt path function to set interrupt path
- fixes interrupt hang issue on j721e and j7200
- removed WA of using polling mode in UT
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- added a soc init function to update interrupt number at run time
- added a config soc interrupt path function to set interrupt path
- fixes interrupt hang issue on j721e and j7200
- removed WA of using polling mode in UT
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 years agoBoard: Added GTC frequency ID config in am64x board library REL.CORESDK.07.02.01.09 REL.CORESDK.07.02.01.10
Board: Added GTC frequency ID config in am64x board library
Board: AM64x: Update GTC clk freq to 200 MHz
Changes GTC input functional clock from the default freq,
of 225 MHz, to the HLOS expected value of 200 MHz.
Solves an issue with SBL booting Linux on AM64x.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Changes GTC input functional clock from the default freq,
of 225 MHz, to the HLOS expected value of 200 MHz.
Solves an issue with SBL booting Linux on AM64x.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Board: Removed unused code in am64x board library
- Updated copyright banners
- Updated copyright banners
SBL: AM64x: Change sbl_ospi_img_hlos to use Non-DMA option
Builds the HLOS variant of SBL for OSPI boot mode to use
memcpy for OSPI transfers, instead of using BCDMA. This also
causes OSPI interface to be used without PHY pipelining.
Workaround for possible resource contention with Linux.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Builds the HLOS variant of SBL for OSPI boot mode to use
memcpy for OSPI transfers, instead of using BCDMA. This also
causes OSPI interface to be used without PHY pipelining.
Workaround for possible resource contention with Linux.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
PDK-9257: SBL: AM64x: Fix M4F mem section loading for OSPI boot
Fixes a problem with using the BCDMA (in OSPI boot mode) to load
memory sections of the Cortex-M4F.
Works around this issue by checking for M4F memory section addresses
and using memcpy (from OSPI flash to M4 mem), instead of doing DMA.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Fixes a problem with using the BCDMA (in OSPI boot mode) to load
memory sections of the Cortex-M4F.
Works around this issue by checking for M4F memory section addresses
and using memcpy (from OSPI flash to M4 mem), instead of doing DMA.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
PDK-9257: SBL: AM64x: Fix OSPI boot w/ DMA when using MCU1_0 TCMs
Need to use SoC-level addresses for R5F0_0 local TCM memories
as well on OSPI boot mode with DMA.
Changes SBL to use SoC-level address for all loading to local
TCM memories of MCU1_0.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Need to use SoC-level addresses for R5F0_0 local TCM memories
as well on OSPI boot mode with DMA.
Changes SBL to use SoC-level address for all loading to local
TCM memories of MCU1_0.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
PDK-8885: Board: Created different init/deinit clock groups for am64x evm board library
- Board library for am64x evm is updated to provide the flexibility of
choosing clock modules which will be enabled/disabled during the boot process.
Two different clock groups are created to choose between RTOS normal boot flow
and RTOS+HLOS boot flow.
Clock resources which are used during RTOS boot can be released using
Board_releaseResource function before switching to HLOS
- Board library for am64x evm is updated to provide the flexibility of
choosing clock modules which will be enabled/disabled during the boot process.
Two different clock groups are created to choose between RTOS normal boot flow
and RTOS+HLOS boot flow.
Clock resources which are used during RTOS boot can be released using
Board_releaseResource function before switching to HLOS
Board: Fix for am64x evm stress test build errors
AM64x: launch.js update for latest CSP
Updates to launch.js based on latest CSP package made for public consumption.
When R5 is connected, the DDR will not be configured automatically.
After the sciclient_ccs_init runs, the launch.js explicitly calls
AM64_DDR_Initialization_ECC_Disabled() to configure the DDR.
CSP commit:
https://bitbucket.itg.ti.com/projects/CPHWA/repos/k3_ccs/commits/662bc078f8ccee26024a80bd648803872a31b5e6
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Updates to launch.js based on latest CSP package made for public consumption.
When R5 is connected, the DDR will not be configured automatically.
After the sciclient_ccs_init runs, the launch.js explicitly calls
AM64_DDR_Initialization_ECC_Disabled() to configure the DDR.
CSP commit:
https://bitbucket.itg.ti.com/projects/CPHWA/repos/k3_ccs/commits/662bc078f8ccee26024a80bd648803872a31b5e6
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
AM64x Build Fix: Use CORELISTARM for UART baremetal app
- Use drvuart_am64x_CORELISTARM for UART_Baremetal_TestApp
- All other UART apps for am64x was already using drvuart_am64x_CORELISTARM
Signed-off-by: Don Dominic <a0486429@ti.com>
- Use drvuart_am64x_CORELISTARM for UART_Baremetal_TestApp
- All other UART apps for am64x was already using drvuart_am64x_CORELISTARM
Signed-off-by: Don Dominic <a0486429@ti.com>
BUILD: AM64x: Add missing mpu1_1 in the am64x core list
Update core lists in both BUILD and SBL to match the cores
that are used for building various test cases.
Fixes build issue for the sbl_multicore_amp boot test case
for am64x_evm by including the last "mpu1_1" core that was
previously missing.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Update core lists in both BUILD and SBL to match the cores
that are used for building various test cases.
Fixes build issue for the sbl_multicore_amp boot test case
for am64x_evm by including the last "mpu1_1" core that was
previously missing.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
[PDK-9033] UDMA Example : Fix UDMA ADC example on AM64x mpu1_0
- Clear destination buffer and cache writeback
Signed-off-by: Don Dominic <a0486429@ti.com>
- Clear destination buffer and cache writeback
Signed-off-by: Don Dominic <a0486429@ti.com>
am64x: Enable appimage generation for mcspi tests
Enable appimage generation for test cases that apply to am64x.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Enable appimage generation for test cases that apply to am64x.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
PDK-9175: SBL: AM64x: Fix MMCSD boot when using MCU1_0 TCMs
Adds address translation to SoC level addresses of MCU1_0
local TCMs when using MMCSD ADMA to copy appimage sections
to MCU1_0 ATCM / BTCM.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Adds address translation to SoC level addresses of MCU1_0
local TCMs when using MMCSD ADMA to copy appimage sections
to MCU1_0 ATCM / BTCM.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
[PDK-9033] UDMA Example : Fix UDMA ADC example on AM64x
- Moved PDMA Config and chEnable to App_create
- Moved chDiable to App_delete
- Added VirtToPhy/PhyToVirt conversion before submitting to/after receiving from DMA Controller
- Basic Porting for LCDMA
- Added RA Type macro for Teardown Completion Queue, Teardown Event and Completion Ring Mem
Signed-off-by: Don Dominic <a0486429@ti.com>
- Moved PDMA Config and chEnable to App_create
- Moved chDiable to App_delete
- Added VirtToPhy/PhyToVirt conversion before submitting to/after receiving from DMA Controller
- Basic Porting for LCDMA
- Added RA Type macro for Teardown Completion Queue, Teardown Event and Completion Ring Mem
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-7995] UDMA: Simplify UDMA RM Configuration for AM64x
- Simplify RM Configuration by querying from defaultBoardCfg
- Using #Sciclient_rmGetResourceRange to populate #Udma_RmInitPrms
- Removes all hard-codings in udma_rmcfg.c
- Splits shared resources like GlobalEvents/VINTR across BCDMA/PKTDMA Instances
based on the prms in #Udma_RmSharedResPrms (UDMA RM Shared Resource parameters)
- User can override default UDMA RM Shared Resource parameters, using Udma_rmGetSharedResPrms API
- Moved UdmaRmInitPrms_init to 'udma_rmcfg_common.c' in 'soc' folder.
This API will return error, if it fails to init #Udma_RmInitPrms
- New API to to retun TISCI Core Dev ID 'Udma_getCoreSciDevId'
- To be reused in 'UdmaRmInitPrms_init'
- For devices like AM64x (LCDMA), One to one mapping exists from Virtual Interrupts to Core Interrupts
So translate to corresponding range using 'Sciclient_rmIrqTranslateIaOutput'.
Since there are no Interrupt Routers, startIrIntr/numIrIntr refers to core interrupt itslef.
Signed-off-by: Don Dominic <a0486429@ti.com>
- Simplify RM Configuration by querying from defaultBoardCfg
- Using #Sciclient_rmGetResourceRange to populate #Udma_RmInitPrms
- Removes all hard-codings in udma_rmcfg.c
- Splits shared resources like GlobalEvents/VINTR across BCDMA/PKTDMA Instances
based on the prms in #Udma_RmSharedResPrms (UDMA RM Shared Resource parameters)
- User can override default UDMA RM Shared Resource parameters, using Udma_rmGetSharedResPrms API
- Moved UdmaRmInitPrms_init to 'udma_rmcfg_common.c' in 'soc' folder.
This API will return error, if it fails to init #Udma_RmInitPrms
- New API to to retun TISCI Core Dev ID 'Udma_getCoreSciDevId'
- To be reused in 'UdmaRmInitPrms_init'
- For devices like AM64x (LCDMA), One to one mapping exists from Virtual Interrupts to Core Interrupts
So translate to corresponding range using 'Sciclient_rmIrqTranslateIaOutput'.
Since there are no Interrupt Routers, startIrIntr/numIrIntr refers to core interrupt itslef.
Signed-off-by: Don Dominic <a0486429@ti.com>
PDK-5153: Board: Updated stress tests for am64x evm to fix the failures
PDK-8367: Board: Updated SPI EEPROM diag test for AM64x EVM
PDK-5115: Board: Corrected gpio pin mapping for am64x evm exp header test
[dmautils] Update hostemu to support 8 to 16 bit conversion
Signed-off-by: Anshu Jain <anshu.jain@ti.com>
Signed-off-by: Anshu Jain <anshu.jain@ti.com>
PDK-9013: Fixes for Sciserver logic
Sciserver_UserProcessMsg has 2 flows:
1. Non-secure host --> Sciserver_UserProcessMsg (MCU1_0)
RM Process / PM Process
[RM forward to DMSC]
2. Secure Host --> DMSC --> Sciserver_UserProcessMsg (MCU1_0)
RM Process/ PM Process
Earlier logic was performing the following steps:
1. Check message type - based on that set RM, PM or forward flag.
2. If RM flag and forward flag is set the Process RM is called and the Forward message is called.
3. The effect is the local RM is called 2 times
4. If the local RM fails, we still end up calling the API 2 times.
5. If there is a fail in the Forward response function, the response is not sent back to the non-secure host.
So the logic has to be corrected to have only local RM processing when getting forwarded from a secure host and have non-secure processing call the Sciclient_service function which identifies the forward or non-forward message calls.
The earlier logic also has another issue where the value of return is checked for the setting of the ACK and NACK flag after the override finished for the ret value based on the fact that the ACK and NACK flag is already set in the response. So the net effect is the ACK / NACK flag is falsely set to ACK based on the ret value giving an incorrect response to the user.
The current logic does the following:
1. Checks if the message is from DMSC (forwarded) or not. Based on this it calls the full message processing or only the local to MCU1_0 RM message processing.
2. The Sciserver and the local RM message processing sets the ACK/NACK flag and the API does not overwrite this after the processing is complete.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Sciserver_UserProcessMsg has 2 flows:
1. Non-secure host --> Sciserver_UserProcessMsg (MCU1_0)
RM Process / PM Process
[RM forward to DMSC]
2. Secure Host --> DMSC --> Sciserver_UserProcessMsg (MCU1_0)
RM Process/ PM Process
Earlier logic was performing the following steps:
1. Check message type - based on that set RM, PM or forward flag.
2. If RM flag and forward flag is set the Process RM is called and the Forward message is called.
3. The effect is the local RM is called 2 times
4. If the local RM fails, we still end up calling the API 2 times.
5. If there is a fail in the Forward response function, the response is not sent back to the non-secure host.
So the logic has to be corrected to have only local RM processing when getting forwarded from a secure host and have non-secure processing call the Sciclient_service function which identifies the forward or non-forward message calls.
The earlier logic also has another issue where the value of return is checked for the setting of the ACK and NACK flag after the override finished for the ret value based on the fact that the ACK and NACK flag is already set in the response. So the net effect is the ACK / NACK flag is falsely set to ACK based on the ret value giving an incorrect response to the user.
The current logic does the following:
1. Checks if the message is from DMSC (forwarded) or not. Based on this it calls the full message processing or only the local to MCU1_0 RM message processing.
2. The Sciserver and the local RM message processing sets the ACK/NACK flag and the API does not overwrite this after the processing is complete.
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 years agoBoard: Fix for am64x evm ospi diagnostic test build error REL.CORESDK.07.02.00.10 REL.CORESDK.07.02.01.06
Board: Fix for am64x evm ospi diagnostic test build error
- Disabled sbl cust image build for am64x svb
- Disabled sbl cust image build for am64x svb
PDK-8969: Board: Fix for am64x svb ospi diagnostic test build failure
PDK-8977: Board: Enabled temperature sensor diagnostic test for am64x svb
PDK-8978: Board: Enabled current monitor diagnostic test for am64x svb
PDK-8981: Board: Enabled MCAN diagnostic test for am64x svb
Board: Enabled memory diagnostic tests for am64x svb
- PDK-8985: Enabled I2C Board ID EEPROM test
- PDK-8983: Enabled DDR memory diagnostic test
- PDK-8984: Enabled SD card diagnostic test
- PDK-8982: Enabled eMMC diagnostic test
- PDK-8969: Enabled OSPI diagnostic test
- PDK-8988: Enabled QSPI flash diagnostic test
- PDK-8985: Enabled I2C Board ID EEPROM test
- PDK-8983: Enabled DDR memory diagnostic test
- PDK-8984: Enabled SD card diagnostic test
- PDK-8982: Enabled eMMC diagnostic test
- PDK-8969: Enabled OSPI diagnostic test
- PDK-8988: Enabled QSPI flash diagnostic test
PDK-8968: Board: Added gpmc diagnostic test
PDK-8967: Board: Updated board flash library for am64x svb
PDK-8967: Board: Updated am64x svb board library for SVB HW
am64x main pll 0 HSDIV setting for 200 MHz for ICSS
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Migrating to SYSFW version v2020.12a
Migrating to SYSFW version v2020.12a
Migrating to SYSFW version v2020.12a
Board: Uniflash host tool update for Uniflash release 6.2
- PDK-9019: Enabled flow control to support higher baudrate on AM64 EVM
- PDK-9179: Added support for auto-detecting tifs.bin
- PDK-9180: Added raw mode support to fix Linux failure with TPR12 EVM
- PDK-9019: Enabled flow control to support higher baudrate on AM64 EVM
- PDK-9179: Added support for auto-detecting tifs.bin
- PDK-9180: Added raw mode support to fix Linux failure with TPR12 EVM
[PDK-8573] UDMA: Expose Udma_chGetTriggerEvent API
- Expose Udma_chGetTriggerEvent API
- Added Error Checks
- Removed i/p param 'drvHandle' (Derive from passed 'chHandle')
- API will return the global 0/1 trigger event for the channel
- Trigger is not supported for external channels and the function will return #UDMA_EVENT_INVALID.
Signed-off-by: Don Dominic <a0486429@ti.com>
- Expose Udma_chGetTriggerEvent API
- Added Error Checks
- Removed i/p param 'drvHandle' (Derive from passed 'chHandle')
- API will return the global 0/1 trigger event for the channel
- Trigger is not supported for external channels and the function will return #UDMA_EVENT_INVALID.
Signed-off-by: Don Dominic <a0486429@ti.com>
Mailbox: Test: Update mailbox_perf_test for automation
Update the mailbox_perf_test for baremetal and rtos to
print to UART and to print the correct pass string for
test automation.
Also update the linker files to be compatible with SBL
loading and create the multicore appimage.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Update the mailbox_perf_test for baremetal and rtos to
print to UART and to print the correct pass string for
test automation.
Also update the linker files to be compatible with SBL
loading and create the multicore appimage.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Mailbox: Add missing documentation
Add the missing documentation for the read modes and
update documentation for functions that are not supported for
every device to indicate the support.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Add the missing documentation for the read modes and
update documentation for functions that are not supported for
every device to indicate the support.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
mmcsd: v2: fix build with logs enabled
Fix build errors seen when trying to enable LOG_EN flag. Also add missing
new lines in log statements to make the log easier to read.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Fix build errors seen when trying to enable LOG_EN flag. Also add missing
new lines in log statements to make the log easier to read.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
PDK-9098: Board: am64x_evm add ICSSG0 IEP SYNC/LATCH pins and GPIO outputs for sitara-apps/timesync_example
PDK-9098: Board: am64x_evm add MCU GPIO for sitara-apps/servo_drive_demo
3 years agoSBL: AM64x: Fix example XIP flash boot test REL.CORESDK.07.02.00.06 REL.CORESDK.07.02.00.07
SBL: AM64x: Fix example XIP flash boot test
Fixes SBL XIP boot test for AM64x by using the latest aligned
flash address offset for the XIP test binary (0x1c0000).
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Fixes SBL XIP boot test for AM64x by using the latest aligned
flash address offset for the XIP test binary (0x1c0000).
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Correct portNum parameter used by emac_poll_pkt and emac_poll_ctrl for ICSSG switch
Signed-off-by: Pratheesh Gangadhar <pratheesh@ti.com>
Signed-off-by: Pratheesh Gangadhar <pratheesh@ti.com>
Fix for issues seen with port call backs
EMAC_FREE_PKT needs to be invoked on Port/Slice used to transmit the packet as packet will be scheduled by ICSSG firmware irrespective of the port in which application is polling for TX completion
Signed-off-by: Pratheesh Gangadhar <pratheesh@ti.com>
EMAC_FREE_PKT needs to be invoked on Port/Slice used to transmit the packet as packet will be scheduled by ICSSG firmware irrespective of the port in which application is polling for TX completion
Signed-off-by: Pratheesh Gangadhar <pratheesh@ti.com>
Add ingress rate limiter support in emac lld
Signed-off-by: Pratheesh Gangadhar <pratheesh@ti.com>
Signed-off-by: Pratheesh Gangadhar <pratheesh@ti.com>
SBL: AM64x: Enable OSPI PHY with DMA for OSPI build
Enables the OSPI PHY (using PHY tuning) and DMA transfers
for faster application booting, when using "sbl_ospi_img".
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Enables the OSPI PHY (using PHY tuning) and DMA transfers
for faster application booting, when using "sbl_ospi_img".
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
SBL: AM64x: Enable CUST build for OSPI boot with custom flags
Enables building "sbl_cust_img" for an alternate OSPI boot method
where special SBL "CUST" build flags can be used (sbl_component.mk)
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Enables building "sbl_cust_img" for an alternate OSPI boot method
where special SBL "CUST" build flags can be used (sbl_component.mk)
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
3 years agoSBL: AM64x: Add OSPI 166 MHz operation and update caching for xSPI REL.CORESDK.07.02.01.05
SBL: AM64x: Add OSPI 166 MHz operation and update caching for xSPI
OSPI parameter updates in the SBL to support using OSPI interface
at 166 MHz for booting images.
Added R5 cache exclusion region for the xSPI flash PHY tuning data
area.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
OSPI parameter updates in the SBL to support using OSPI interface
at 166 MHz for booting images.
Added R5 cache exclusion region for the xSPI flash PHY tuning data
area.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
3 years ago[PDK-9060] UDMA: Apputils: Add support of AM64x TCMA Address Translations REL.CORESDK.07.02.00.04 REL.CORESDK.07.02.00.05
[PDK-9060] UDMA: Apputils: Add support of AM64x TCMA Address Translations
- Convert local R5 TCMA address to global space in Udma_appVirtToPhyFxn
- Convert global R5 TCMA address to local space in Udma_appPhyToVirtFxn
- Fix typo for macro in udma_ospi_flash example
- This fixes PDK-9060 : UDMA OSPI example not working on AM64x
Signed-off-by: Don Dominic <a0486429@ti.com>
- Convert local R5 TCMA address to global space in Udma_appVirtToPhyFxn
- Convert global R5 TCMA address to local space in Udma_appPhyToVirtFxn
- Fix typo for macro in udma_ospi_flash example
- This fixes PDK-9060 : UDMA OSPI example not working on AM64x
Signed-off-by: Don Dominic <a0486429@ti.com>
KEYWRITER: fixes main.c build issue
[Bug Fix] PDK-8849: UART UT: few unit tests are failing on M4F core
- Interrupts are enabled for mcu uart instances on M4f core
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- Interrupts are enabled for mcu uart instances on M4f core
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
3 years agoAM64x RM: Update defaulBoardCfg_rm to assign CMPEVNT INTR outputs for local events... REL.CORESDK.07.02.00.01 REL.CORESDK.07.02.00.02 REL.CORESDK.07.02.00.03
AM64x RM: Update defaulBoardCfg_rm to assign CMPEVNT INTR outputs for local events to HOST_ID_ALL
- Updates in allignment with https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/13/overview
- Regenrate scilcient_boardcfg and sciclient_ccs_init
Signed-off-by: Don Dominic <a0486429@ti.com>
- Updates in allignment with https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/13/overview
- Regenrate scilcient_boardcfg and sciclient_ccs_init
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-8918] udma ospi example for j7200/am64x
- perform writes in INDAC mode and reads in DAC DMA mode
- moved the OSPI INDAC Write API to common csl file
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- perform writes in INDAC mode and reads in DAC DMA mode
- moved the OSPI INDAC Write API to common csl file
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[Bug Fix] PDK-8761: UART UT Dma tests hangs after timeout
- After timeout Flush any pending request from the free queue
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- After timeout Flush any pending request from the free queue
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
SBL: AM64x: Change SCRATCH RAM location to DDR memory
Moves the SCRATCH RAM for the SBL (used for temp location
for appimage loads) back to the same DDR address & size
as used for other similar SoCs.
Enables loading larger appimages via UART boot mode (and
larger signed appimages via any boot mode). Also avoids
conflicts with other possible usage of the OC SRAM.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Moves the SCRATCH RAM for the SBL (used for temp location
for appimage loads) back to the same DDR address & size
as used for other similar SoCs.
Enables loading larger appimages via UART boot mode (and
larger signed appimages via any boot mode). Also avoids
conflicts with other possible usage of the OC SRAM.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
[PDK-8724] Fixed PHY causing failure of next test
- Some fields in RD_DATA_CAPTURE_REG are modified by the Nor_spiPhyTune API
- Resting these fields in the Nor_xspiClose API
- Removed the WA of disabling PHY done in PDK-8725
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- Some fields in RD_DATA_CAPTURE_REG are modified by the Nor_spiPhyTune API
- Resting these fields in the Nor_xspiClose API
- Removed the WA of disabling PHY done in PDK-8725
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>