processor-sdk/pdk.git
3 months ago[PDK-6649] OSAL: nonos: Fix TimerP_delete to update gTimerAnyMask
Don Dominic [Tue, 16 Mar 2021 10:31:07 +0000 (16:01 +0530)]
[PDK-6649] OSAL: nonos: Fix TimerP_delete to update gTimerAnyMask

- TimerP_delete was not resetting the the timer's bit field in the gTimerAnyMask
  - Hence the mask was getting exhausted after log2(TIMERP_AVAILABLE_MASK+1) no.of TimerP_create
  - This resulted in TimerP_create failures even when there are unused timers
- Update the timer's bit field in the mask while deleting the timer to resolve this
- For v0/v1, Global Timer Structure's used flag was cleared only when Timer ISR is non-NULL
  - Fixed this to clear irrespective of Timer ISR

- Also updated the UT with a test to catch this failure
 - This tests TimerP_create and TimerP_delete repeatedly for more no.of times than that in the mask,
   to make sure freeing up of resources was successful
 - The test which was failing earlier, now works fine with the updates in source

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months ago[PDK-8586] SBL: OSPI: Early CAN response optimization
Aditya Wadhwa [Thu, 4 Mar 2021 18:51:55 +0000 (00:21 +0530)]
[PDK-8586] SBL: OSPI: Early CAN response optimization

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months ago[PDK-6848] OSAL: SYSBIOS: TaskP_delete to delete task only when deleteTerminatedTasks...
Don Dominic [Mon, 15 Mar 2021 15:34:44 +0000 (21:04 +0530)]
[PDK-6848] OSAL: SYSBIOS: TaskP_delete to delete task only when deleteTerminatedTasks flag is disabled

- In case of apps with the BIOS cfg 'Task.deleteTerminatedTasks' enabled,
  cleanup happens in BIOS idle task.
- Deleting terminated task will results in BIOS error.
- Hence to make BIOS config independent, TaskP_delete will check for the flag before deleting any task.

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months ago[DSS DRV][Bug Fix][PDK-5040]Display stops working if two pipelines are started back... REL.CORESDK.07.03.00.22
Vivek Dhande [Sun, 14 Mar 2021 14:00:01 +0000 (19:30 +0530)]
[DSS DRV][Bug Fix][PDK-5040]Display stops working if two pipelines are started back to back

- Issue:
    - When two display pipelines (connected to the same overlay) are started back to back by calling FVID2_Start() twice, pipelines do not start and does not display anything.
    - Same is observed for 2 LCDs
- Resolution:
    - Second start has to wait for a VSYNC to come from first pipeline before starting
- Fix:
    - We should not allow pipelines to be started back to back until the first vsync callback of pipeline comes.
    - Wait for semaphore before starting second pipeline

Signed-off-by: Vivek Dhande <a0132295@ti.com>
3 months ago[DSS M2M DRV]Doxygen build fix
Vivek Dhande [Mon, 15 Mar 2021 06:53:10 +0000 (12:23 +0530)]
[DSS M2M DRV]Doxygen build fix

- This patch also contains small driver and app update

Signed-off-by: Vivek Dhande <a0132295@ti.com>
3 months agoOSPI: Build Fix REL.CORESDK.07.03.00.21
Aditya Wadhwa [Fri, 12 Mar 2021 09:24:39 +0000 (14:54 +0530)]
OSPI: Build Fix

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months agoMigrating to SYSFW version v2021.01a
Piyali Goswami [Fri, 12 Mar 2021 05:43:01 +0000 (11:13 +0530)]
Migrating to SYSFW version v2021.01a

Migrating to v2021.01a

3 months agoFixes for Sciclient to not globally disable interrupts
Piyali Goswami [Fri, 12 Mar 2021 05:00:33 +0000 (10:30 +0530)]
Fixes for Sciclient to not globally disable interrupts

Added a software mechanism to not have to disable interrupts when trying polling mode of operation and still allow secure proxy to not be overwritten by multiple threads.

Fixes: PDK-8945

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 months ago[PDK-9436] UDMA : Update offset of C7x events associated to CLEC
Don Dominic [Thu, 11 Mar 2021 18:27:56 +0000 (23:57 +0530)]
[PDK-9436] UDMA : Update offset of C7x events associated to CLEC

Update offset of C7x events associated to CLEC
which will be used for various UDMA events
such that it won't overlap with that for
DRU Local Events(configured by vision apps/TIDL usecases)
or other drivers.

- Currently vision apps configures CLEC DRU Local events to C7x events starting from 32.
  - Configures for 16 DRU channels allocated for C7x
- Hence to avoid resource conflict UDMA driver will manage C7x events starting from an offset

- Statically partition 64 C7x events into different sets.
  - 0 -31 left for other driver
  - 32-47 for routing DRU Local events
  - 48-63 to be managed by UDMA for various udma events

- This fixes ADASVISION-2344

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months ago[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
Aditya Wadhwa [Thu, 11 Mar 2021 12:09:30 +0000 (17:39 +0530)]
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached

- added a cacheEnable field to the hwAttrs

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months ago[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
Aditya Wadhwa [Thu, 11 Mar 2021 07:44:31 +0000 (13:14 +0530)]
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached

- added copyright comments
- deleted extra file

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months ago[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
Aditya Wadhwa [Wed, 10 Mar 2021 17:59:57 +0000 (23:29 +0530)]
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached

- switched to macro instead of hard-coded values
- flag not working

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months ago[PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
Aditya Wadhwa [Fri, 26 Feb 2021 14:15:02 +0000 (19:45 +0530)]
[PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached

- enabled interrupt for INDAC tests

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months ago[PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
Aditya Wadhwa [Fri, 26 Feb 2021 14:00:12 +0000 (19:30 +0530)]
[PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached

- all tests passing

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months ago[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
Aditya Wadhwa [Thu, 25 Feb 2021 18:17:23 +0000 (23:47 +0530)]
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached

- DAC+DMA, Legacy SPI working
- DAC has data mismatch
- INDAC failure

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months ago[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
Aditya Wadhwa [Fri, 15 Jan 2021 18:56:29 +0000 (00:26 +0530)]
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached

- OPSI FSS DAT0 memory cached/non-cached
- PHY memory always non-cached
- Build failures

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months ago[WIP][PDK-8726] OSPI: Separate OPSI tests keeping memory cached/non-cached
Aditya Wadhwa [Wed, 13 Jan 2021 10:36:01 +0000 (16:06 +0530)]
[WIP][PDK-8726] OSPI: Separate OPSI tests keeping memory cached/non-cached

- Added support for baremetal apps

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months ago[WIP][PDK-8726] Separate OSPI tests keeping memory cached/non-cached
Aditya Wadhwa [Wed, 6 Jan 2021 18:28:07 +0000 (23:58 +0530)]
[WIP][PDK-8726] Separate OSPI tests keeping memory cached/non-cached

- added new tests that export cache as enabled
- separate mpu.xs files for cache enabled/disabled
- RTOS implemented, baremetal pending

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months agoHyperflash : Tested with board diag on j721e es 1.1 REL.CORESDK.07.03.00.20
sujith [Tue, 12 Jan 2021 10:17:35 +0000 (15:47 +0530)]
Hyperflash : Tested with board diag on j721e es 1.1

Works fine in 166 MHz (333 MHz device clock)

Require to clean up code

Signed-off-by: sujith <sujith.s@ti.com>
3 months agoPDK-6706 : SPI Master example is not functional
sujith [Thu, 11 Mar 2021 16:10:42 +0000 (21:40 +0530)]
PDK-6706 : SPI Master example is not functional

The Master example would perform, couple of transactions with
slave app and stall/timeout with an error.

The "loopback" tests would always fail

Root Cause : The driver do not support operating McSPI in
digital loopback mode. As the IP did not support the same.

Fix: Disabled the loopback mode of operation for j721e & j7200

Test : Tested on j721e evm

Signed-off-by: sujith <sujith.s@ti.com>
3 months ago[PDK-9435] Board: DDR: Enable DDR Thermal Testapp for J7200
Don Dominic [Thu, 11 Mar 2021 14:45:36 +0000 (20:15 +0530)]
[PDK-9435] Board: DDR: Enable DDR Thermal Testapp for J7200

- enabled board_ddr_thermal_test_app for j7200 mcu1_0/mcu1_1/mcu2_0/mcu2_1
- Updates in board lib 'board/src/j7200_evm/board_ddrtempmonitor.c'
  - to enable all r5 cores
  - no interrupt routers b/w DDR controller and Main Domain R5
- so skip Sciclient IRQ Routing
  - for MCU Domain R5 cores
- query the IR Range from BoardCfg
  - translate to Core Interrupt Idx and configure path

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months agoFirmware gen.sh update for ES1.1 HS testing
Piyali Goswami [Thu, 11 Mar 2021 10:26:37 +0000 (15:56 +0530)]
Firmware gen.sh update for ES1.1 HS testing

Firmware Gen.sh update for ES1.1 HS testing

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 months agoFix for proper sending and parsing of RM board config in HS
Piyali Goswami [Thu, 11 Mar 2021 05:59:57 +0000 (11:29 +0530)]
Fix for proper sending and parsing of RM board config in HS

Ignoring of the certificate is handled correctly by adjusting the size at source when the certificate is not passed and at sink when the certificate is passed.

Fixes: PDK-9427

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 months ago[DSS M2M APP]Added sample application for DSS M2M Driver
Vivek Dhande [Wed, 10 Mar 2021 13:26:23 +0000 (18:56 +0530)]
[DSS M2M APP]Added sample application for DSS M2M Driver

Signed-off-by: Vivek Dhande <a0132295@ti.com>
3 months agofreertos: Add FreeRTOS kernel folders to gitignore
Don Dominic [Mon, 8 Mar 2021 04:26:45 +0000 (09:56 +0530)]
freertos: Add FreeRTOS kernel folders to gitignore

- Add the following folders in ti/kernel/freertos to gitignore
  - FreeRTOS-Labs/
  - FreeRTOS-LTS/
- These are cloned from https://github.com/FreeRTOS/ as defined in psdk.xml

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months agoPDK-9285: IPC: Fix KW issues
Angela Stegmaier [Fri, 29 Jan 2021 23:52:34 +0000 (17:52 -0600)]
PDK-9285: IPC: Fix KW issues

Fix KW issues for AM64X IPC and MB build.

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
3 months ago[DSS M2M Driver]Addressed review comments
Vivek Dhande [Tue, 9 Mar 2021 18:48:01 +0000 (00:18 +0530)]
[DSS M2M Driver]Addressed review comments

Signed-off-by: Vivek Dhande <a0132295@ti.com>
3 months ago[DSS M2M Driver]Fixed Doxygen API Guide Warnings
Vivek Dhande [Tue, 9 Mar 2021 09:55:11 +0000 (15:25 +0530)]
[DSS M2M Driver]Fixed Doxygen API Guide Warnings

Signed-off-by: Vivek Dhande <a0132295@ti.com>
3 months ago[DSS M2M Driver]Driver implementation: Patch-2
Vivek Dhande [Fri, 5 Mar 2021 10:02:23 +0000 (15:32 +0530)]
[DSS M2M Driver]Driver implementation: Patch-2

- Added implementation for 'Fvid2_processRequest()' and 'Fvid2_getProcessedRequest()'
- Implemented 'IOCTL_DSS_DCTRL_SET_PATH' and 'IOCTL_DSS_DCTRL_CLEAR_PATH' IOCTLs
- Implemented DMA completion Events
- Implemented internal functions needed for above

Signed-off-by: Vivek Dhande <a0132295@ti.com>
3 months ago[DSS M2M Driver]Driver implementation: Patch-1
Vivek Dhande [Sat, 27 Feb 2021 07:40:51 +0000 (13:10 +0530)]
[DSS M2M Driver]Driver implementation: Patch-1

- Added 'dss_m2mPriv.h'
- This files contains following
    - internal structures required for maintaining driver and HW Module states
    - Added support for multiple open/create to support multiple channel support

Signed-off-by: Vivek Dhande <a0132295@ti.com>
3 months ago[DSS M2M DRV][PDK-5179]DSS FVID2 Writeback M2M Driver
Vivek Dhande [Fri, 19 Feb 2021 17:12:18 +0000 (22:42 +0530)]
[DSS M2M DRV][PDK-5179]DSS FVID2 Writeback M2M Driver

- [PDK-5184]DSS Writeback Pipeline Support
- Added interface for DSS M2M driver
- Added nodes & edges for WB pipeline

Signed-off-by: Vivek Dhande <a0132295@ti.com>
3 months ago[PDK-9432] Sciclient : Rebased and Regenerated Sciclient Binaries
Don Dominic [Wed, 10 Mar 2021 18:30:18 +0000 (00:00 +0530)]
[PDK-9432] Sciclient : Rebased and Regenerated Sciclient Binaries

- Regenerated sclient binaries after rebasing
- Validated memcpy with latest binaries on j721e/j7200 mcu1_0 and mcu2_0 with noboot and uart boot.

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months ago[PDK-9432] J7200 BoardCfg: Update to the latest auto-generated from SysConfig/k3...
Don Dominic [Wed, 10 Mar 2021 17:24:58 +0000 (22:54 +0530)]
[PDK-9432] J7200 BoardCfg: Update to the latest auto-generated from SysConfig/k3-resource-partitioning

- This includes the updates in the following:
   - Remove shared allocation for MCU R5
       https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview

- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc

3 months ago[PDK-9432] J721E BoardCfg: Update to the latest auto-generated from SysConfig/k3...
Don Dominic [Wed, 10 Mar 2021 16:03:33 +0000 (21:33 +0530)]
[PDK-9432] J721E BoardCfg: Update to the latest auto-generated from SysConfig/k3-resource-partitioning

- This includes the updates in the following:
   - Remove shared allocation for MCU R5
       https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview
   - Increase virt id range for A72_2
       https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/12/overview

- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc

3 months ago[PDK-9432] Sciclient : Updates to support BoardCfg with mcu1_0 non-secure host id...
Don Dominic [Wed, 10 Mar 2021 14:49:36 +0000 (20:19 +0530)]
[PDK-9432] Sciclient : Updates to support BoardCfg with mcu1_0 non-secure host id entries

-  Do not force mcu1_0 to be in secure mode for all cases
-  Set to secure mode in case the message is to be forwarded
-  Also The MCU1_0 will always be secure when trying to send the message to the TIFS directly to avoid self blocking.

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months agoudma_event.c: Do not pass a NULL resp payload for the Sciclient_rmUdmapGcfgCfg function
Piyali Goswami [Thu, 11 Mar 2021 03:04:13 +0000 (08:34 +0530)]
udma_event.c: Do not pass a NULL resp payload for the Sciclient_rmUdmapGcfgCfg function

Response payload should not be NULL. The API fails in that case

Fixes: PDK-9431

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
3 months agocopied binary and built firmware header .h file
Anuraag Tummanapally [Wed, 10 Mar 2021 15:55:49 +0000 (15:55 +0000)]
copied binary and built firmware header .h file

3 months agoPDK-6534 : un-expected ISR if the timer were running, before creation
Sujith S [Wed, 10 Mar 2021 09:00:27 +0000 (14:30 +0530)]
PDK-6534 : un-expected ISR if the timer were running, before creation

If the timer was running before the timer was created, on creation
especially in user start mode, an ISR would be triggered before
the timer was started.

Root cause : The timer module is not reset before the ISR registration
so, if the timer count lapses after creation but before starting the
the timer, an FALSE isr would be triggered.

Fix: Reset the timer peripheral at create time. This ensures that
counter is disabled and interrupt notification is disabled

Testing: Tested both baremetal & ti rtos unit test of the timer, it
works as expected. OSAL_Baremetal_TestApp and OSAL_TestApp works as
expected

Signed-off-by: Sujith S <sujith.s@ti.com>
3 months agoMMC: Build break fix REL.CORESDK.07.01.06.03 REL.CORESDK.07.01.06.04 REL.CORESDK.07.03.00.18 REL.CORESDK.07.03.00.19
Sujith S [Sat, 6 Mar 2021 16:28:48 +0000 (21:58 +0530)]
MMC: Build break fix

Signed-off-by: Sujith S <sujith.s@ti.com>
3 months agofreertos: posix support only in git and not in rel pkg REL.CORESDK.07.03.00.17
Badri S [Sat, 6 Mar 2021 04:07:00 +0000 (09:37 +0530)]
freertos: posix support only in git and not in rel pkg

remove support for freertos posix in release package
support only in development git folder

Signed-off-by: Badri S <badri@ti.com>
3 months agoPDK-7484 : Disabled HS400 from the supported modes list
Sujith S [Fri, 5 Mar 2021 20:38:47 +0000 (02:08 +0530)]
PDK-7484 : Disabled HS400 from the supported modes list

As per j721e errata (i2024) HS 400 is not supported
on mmc-sd instance 0

Tested MMCSD Regressions on j721e ES 1.0 EVM

ΓΌ01000000011a00006a3765730000000000000000475020200200010002000100CCSBL Revision: 01.00.10.00 (Mar  6 2021 - 01:34:19)
Waiting for tifs.bin ...
CCTIFS  ver: 21.1.0--v2021.01 (Terrific Llam
Waiting for multicore app ...
CCCCalibration Start
Calibration: Ticks per ms is 999994
Calibration Completed
:
:
MMCSD Regression Test Menu
--------------------------
 Test ID:   Description    Powercycle Required?
    0          DS Mode 1-bit Test            No
    1          DS Mode Test                  No
    2          HS Mode Test                  No
    8          SDR12 Mode Test               Yes
    9          SDR25 Mode Test               Yes
   10          SDR50 Mode Test               Yes
   11          DDR50 Mode Test               Yes
   13         Default Unit Test (Max speed)           Yes
   -1          All non powercycle tests           No
   -2          Exit the regression test           No

Please enter a test ID from the above list: -2
 Test ID Entered = -2

Exiting the regression test

All tests have PASSED
3/3 tests passed

Signed-off-by: Sujith S <sujith.s@ti.com>
3 months agoBuild Fix: Fix build issues with Board DDR Temp Monitor
Don Dominic [Fri, 5 Mar 2021 15:29:56 +0000 (20:59 +0530)]
Build Fix: Fix build issues with Board DDR Temp Monitor

- Not applicable for mpu1_0
- Removed #ifdef for BUILD_MCU1_0 when added support for main R5 cores
https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/commits/8e4f1ae9e303b3627fbe71b81bde75b6dd601a07#packages/ti/board/src/j721e_evm/board_ddrtempmonitor.c
- But should have protected with MCU ifdef
- Fixed by adding #ifdef for BUILD_MCU

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months ago[PDK-9317][PDK-9316] Board: DDR: Updates in Board DDR thermal monitoring REL.CORESDK.07.01.06.02
Don Dominic [Mon, 8 Feb 2021 16:00:09 +0000 (21:30 +0530)]
[PDK-9317][PDK-9316] Board: DDR: Updates in Board DDR thermal monitoring

- Query from BoardCfg to get the  allowed core interrupt IRQ idx
- Add support for other R5F cores

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months ago[PDK-9312] FreeeRTOS: Addressed review comments
Don Dominic [Fri, 5 Mar 2021 09:24:52 +0000 (14:54 +0530)]
[PDK-9312] FreeeRTOS: Addressed review comments

- Updated linker file to use OCMC/DDR instead of MSMC
- Many times apps/customer copy our linker and struggled due to use of MSMC for MCU R5 apps

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months agoBuild Fix: sciclient_firmware_boot_TestApp linker updates to enable debug build
Don Dominic [Fri, 5 Mar 2021 05:42:50 +0000 (11:12 +0530)]
Build Fix: sciclient_firmware_boot_TestApp linker updates to enable debug build

- '.cinit' program will not fit into available memory in OCMRAM
- Moved bss to TCMB from OCMRAM

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months agoFreeRTOS: UT Build Fix
Don Dominic [Fri, 5 Mar 2021 04:03:02 +0000 (09:33 +0530)]
FreeRTOS: UT Build Fix

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months agofreertos: jenkins build fixes
Badri S [Thu, 4 Mar 2021 10:51:13 +0000 (16:21 +0530)]
freertos: jenkins build fixes

jenkins build fixes

Signed-off-by: Badri S <badri@ti.com>
3 months ago[PDK-9312] OSAL: FreeRTOS: Added osal_freertos support for J7ES/J7VCL/AM65xx
Don Dominic [Wed, 3 Mar 2021 19:46:19 +0000 (01:16 +0530)]
[PDK-9312] OSAL: FreeRTOS: Added osal_freertos support for J7ES/J7VCL/AM65xx

- osal_freertos library added for j721e/j7200/am65xx

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months ago[PDK-9312] FreeeRTOS: Added support for freertos on all R5F cores in J7ES/J7VCL/AM65xx
Don Dominic [Wed, 3 Mar 2021 14:49:18 +0000 (20:19 +0530)]
[PDK-9312] FreeeRTOS: Added support for freertos on all R5F cores in J7ES/J7VCL/AM65xx

- Enable all R5F cores in am65xx/j7200/j721e
  - Added config files for each core with unique DMTimer id
- Add support to copy freertos reset vectors to atcm
  - implemented inside 'xPortStartScheduler' before calling 'vPortRestoreTaskContext()'
- Update config file to add define to enable/disable copy of freertos reset vectors to atcm
  - By default Enabled for AM65xx since vectors are placed in OCMRAM in the linker file since core reset will clear the atcm
- Updated freertos kernel paths
- Minor cleanups

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months agoadded osal lib for free rtos
Prasad Konnur [Tue, 23 Feb 2021 14:20:11 +0000 (19:50 +0530)]
added osal lib for free rtos

 - added osal lib
 - added semephore osal implementation
 - other components of osal use the nonos implementation
 - added taskp in freertos
 - added memoryP in freertos
 - added memoryP test in osal testapp
 - added delay implementation using TaskP_sleep

Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
3 months agofreertos: fix r5f pmu counter overflow
Badri S [Wed, 3 Mar 2021 09:01:24 +0000 (14:31 +0530)]
freertos: fix r5f pmu counter overflow

ensure we periodically check for PMU cycle
counter overflow so that we dont miss incrementing
overflow counter.

Signed-off-by: Badri S <badri@ti.com>
3 months agofreertos: disable interrupt preemption for r5
Badri S [Tue, 2 Mar 2021 11:50:19 +0000 (17:20 +0530)]
freertos: disable interrupt preemption for r5

Disable interrupt preemption for r5 until correct
interrupt preemption support

Signed-off-by: Badri S <badri@ti.com>
3 months agofreertos:c66x fixes to ensure csl_vect is not linked in
Badri S [Sun, 28 Feb 2021 03:37:51 +0000 (09:07 +0530)]
freertos:c66x fixes to ensure csl_vect is not linked in

ensure csl_vect is not wrongly linked in resulting in
interrupts not being serviced by freertos vecs

Signed-off-by: Badri S <badri@ti.com>
3 months agofreertos: remove dpl folder and move to port folder
Badri S [Sat, 27 Feb 2021 14:31:09 +0000 (20:01 +0530)]
freertos: remove dpl folder and move to port folder

remove dpl folder and move files under port folder
also make test folder freertos specific

Signed-off-by: Badri S <badri@ti.com>
3 months agofreertos: support for j721e,j7200,am65xx SoCs
Badri S [Sat, 27 Feb 2021 07:37:16 +0000 (13:07 +0530)]
freertos: support for j721e,j7200,am65xx SoCs

Support added for am65xx,j721e,am65xx SoCs
freertos lib made core specific instead of isa
so that freeRTOS config can include core specific
header file

Signed-off-by: Badri S <badri@ti.com>
3 months agofreertos: support for r5f core
Badri S [Sat, 27 Feb 2021 02:50:09 +0000 (08:20 +0530)]
freertos: support for r5f core

freertos support for r5f core ported from mcu_plus_sdk

Signed-off-by: Badri S <badri@ti.com>
3 months agofreertos: support for c66x core for freertos
Badri S [Tue, 16 Feb 2021 07:31:34 +0000 (13:01 +0530)]
freertos: support for c66x core for freertos

freertos c66x port support

Signed-off-by: Badri S <badri@ti.com>
3 months agoPDK-7013: Removes VTM workaround for J7ES PG1.1
Erick Narvaez [Tue, 23 Feb 2021 03:04:31 +0000 (21:04 -0600)]
PDK-7013: Removes VTM workaround for J7ES PG1.1

Removes default workaround flag for J7ES VTM.

Signed-off-by: Erick Narvaez <e-narvaez@ti.com>
3 months agoadded adcbuf driver for AWR294x SOC
KALYAN VAGVALA [Thu, 11 Feb 2021 16:48:42 +0000 (22:18 +0530)]
added adcbuf driver for AWR294x SOC

3 months agoOSPI: PHY tuning benchmarking
Aditya Wadhwa [Tue, 2 Mar 2021 19:13:40 +0000 (00:43 +0530)]
OSPI: PHY tuning benchmarking

- added a macro which can be enabled to get the logs of how much time the PHY tuning elapsed
- switched to UART prints

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
3 months agotimeSync: v2: Explicitly set no traffic class
Misael Lopez Cruz [Wed, 3 Mar 2021 08:21:51 +0000 (02:21 -0600)]
timeSync: v2: Explicitly set no traffic class

The newly added txPktTc field of the Enet DMA packet structure is used
for ICSSG but it's not applicable for CPSW.  Hence, it's explicitly set
to indicate that no traffic class is to be used.

Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
3 months agoPDK-9240:Board: Fix for DDR init hang issue on j721e evm during warm reset
M V Pratap Reddy [Thu, 4 Mar 2021 14:53:30 +0000 (20:23 +0530)]
PDK-9240:Board: Fix for DDR init hang issue on j721e evm during warm reset

 - DDR initialization is hanging during the warm reset which is caused
   by PLL bypass function. Need to unlock the PLL registers for access
   during the warm reset.

3 months agoPRSDK-8813: Board/USB: Updated AM65xx SerDes configurations
M V Pratap Reddy [Wed, 3 Mar 2021 05:15:30 +0000 (10:45 +0530)]
PRSDK-8813: Board/USB: Updated AM65xx SerDes configurations

 - CSL SerDes USB configurations are updated to fix enumeration failures.
   Updated the board library and USB driver to align with updated SerDes
   configurations.

3 months agoboard - Missing enum and fix include path
Prasad Jondhale [Sat, 27 Feb 2021 16:43:57 +0000 (22:13 +0530)]
board - Missing enum and fix include path

Signed-off-by: Prasad Jondhale <prasad.jondhale@ti.com>
3 months ago[PDK-9404] OSAL: Fix TIMERP_TIMER_FREQ_LO for J7200
Don Dominic [Tue, 2 Mar 2021 17:53:32 +0000 (23:23 +0530)]
[PDK-9404] OSAL: Fix TIMERP_TIMER_FREQ_LO  for J7200

- TIMERP_TIMER_FREQ_LO defined in osal_soc.h for J7200 is wrong.(25MHz)
- Input Crystal Frequency for j7200 is 19.2MHz and default Timer clk_sel 0(HFOSC0_CLKOUT) will be 19.2MHz

Signed-off-by: Don Dominic <a0486429@ti.com>
3 months ago[PDK-9315] Updating BIOS and XDC REL.CORESDK.07.03.00.13 REL.CORESDK.07.03.00.14 REL.CORESDK.07.03.00.15 REL.CORESDK.07.03.00.16 REL.CORESDK.07.03.01.03 REL.CORESDK.07.03.01.04 REL.CORESDK.07.03.01.05 REL.CORESDK.07.03.01.06
Ankur [Tue, 23 Feb 2021 17:58:13 +0000 (23:28 +0530)]
[PDK-9315] Updating BIOS and XDC

Signed-off-by: Ankur <a0132173@ti.com>
3 months ago[BugFix] PDK-8886: pdk_examples build fails on Windows
Prasad Konnur [Fri, 19 Feb 2021 13:45:02 +0000 (19:15 +0530)]
[BugFix] PDK-8886: pdk_examples build fails on Windows

 - armstrip or strip6x on windows is not able to delete the strip file
 if it already present.
 - $(RM) is set to rm -f so will not generate error if the file is not
 present.

Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
3 months agoadded build support for awr294x
Prasad Konnur [Thu, 18 Feb 2021 13:25:51 +0000 (18:55 +0530)]
added build support for awr294x

Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
4 months agoPDK-9337: Fix for Clocking on J7VCL to use fracf pll calibration REL.CORESDK.07.03.00.10 REL.CORESDK.07.03.00.11 REL.CORESDK.07.03.00.12 REL.CORESDK.07.03.01.02
Piyali Goswami [Thu, 18 Feb 2021 13:14:11 +0000 (18:44 +0530)]
PDK-9337: Fix for Clocking on J7VCL to use fracf pll calibration

Fix for clocking on J7VCL to use fracf pll calibration

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
4 months agoosal: baremetal build fix for mcu1_1
Piyali Goswami [Thu, 18 Feb 2021 10:28:08 +0000 (15:58 +0530)]
osal: baremetal build fix for mcu1_1

OSAL baremetal build fix for mcu1_1

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
4 months agoBuild Fix REL.CORESDK.07.03.00.09 REL.CORESDK.07.03.01.01
Ankur [Thu, 18 Feb 2021 09:01:14 +0000 (14:31 +0530)]
Build Fix

Signed-off-by: Ankur <a0132173@ti.com>
4 months ago[PDK-9328] OSPI: Binary search instead of linear search for PHY tuning window REL.CORESDK.07.03.00.08
Aditya Wadhwa [Mon, 15 Feb 2021 19:28:34 +0000 (00:58 +0530)]
[PDK-9328] OSPI: Binary search instead of linear search for PHY tuning window

- Previous implementation was a linear search algorithm
- Occassional failures observed
- Replaced by a binary search algorithm

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
4 months agoSPI packaging error fix REL.CORESDK.07.03.00.06 REL.CORESDK.07.03.00.07
Ankur [Tue, 16 Feb 2021 19:54:21 +0000 (01:24 +0530)]
SPI packaging error fix

Signed-off-by: Ankur <a0132173@ti.com>
4 months agoCGT update for C7x REL.CORESDK.07.03.00.05
Ankur [Tue, 16 Feb 2021 15:19:19 +0000 (20:49 +0530)]
CGT update for C7x

Signed-off-by: Ankur <a0132173@ti.com>
4 months agoRevert "[PDK-9315] Updating the BIOS version to 06.83.02.07"
Ankur [Tue, 16 Feb 2021 15:16:51 +0000 (20:46 +0530)]
Revert "[PDK-9315] Updating the BIOS version to 06.83.02.07"

This reverts commit dca947d3294daa19d842386afa038ef797e35e1b.

4 months agoRevert "updating XDC and C7x CGT tool version"
Ankur [Tue, 16 Feb 2021 15:16:45 +0000 (20:46 +0530)]
Revert "updating XDC and C7x CGT tool version"

This reverts commit e738709d0f9e45ac20b3092009ed41a49c2b2aea.

4 months agosciclient: docs: design: Update to add Domain reset information REL.CORESDK.07.03.00.02 REL.CORESDK.07.03.00.03 REL.CORESDK.07.03.00.04
Piyali Goswami [Fri, 12 Feb 2021 04:01:46 +0000 (09:31 +0530)]
sciclient: docs: design: Update to add Domain reset information

Doc update to add domain groups reset API information

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
4 months agoSupport for Domain resets in Sciclient PM
Piyali Goswami [Thu, 11 Feb 2021 06:22:41 +0000 (11:52 +0530)]
Support for Domain resets in Sciclient PM

Support for Domain Resets in Sciclient PM

Fixes: PDK-9326

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
4 months agoupdating XDC and C7x CGT tool version
ankur [Mon, 15 Feb 2021 09:20:19 +0000 (14:50 +0530)]
updating XDC and C7x CGT tool version

Signed-off-by: ankur <ankurbaranwal@ti.com>
4 months ago[PDK-9315] Updating the BIOS version to 06.83.02.07
Ankur [Sun, 14 Feb 2021 06:05:01 +0000 (11:35 +0530)]
[PDK-9315] Updating the BIOS version to 06.83.02.07

Signed-off-by: Ankur <a0132173@ti.com>
4 months agoMigrating to SYSFW version v2021.01
Piyali Goswami [Sun, 14 Feb 2021 15:11:31 +0000 (20:41 +0530)]
Migrating to SYSFW version v2021.01

v2021.01 migration

4 months agoETHFW-607: j7200_evm: Bypass SerDes config for Eth if already configured
Misael Lopez Cruz [Fri, 12 Feb 2021 03:14:33 +0000 (21:14 -0600)]
ETHFW-607: j7200_evm: Bypass SerDes config for Eth if already configured

Don't configure SerDes if it has already been configured, i.e. by
u-boot. This enables EthFw to transparently work in Linux boot and
CCS boot.

In Linux boot, u-boot will configure SerDes (i.e. for PCIe and Ethernet
sharing) and at a later point load EthFw, EthFw will not attempt to
reconfigure SerDes.

In CCS boot, EthFw will configure SerDes.

Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
4 months agoPDK-9050: Board: Fix for board PLL clock configuration failure on j721e REL.CORESDK.07.03.00.01
M V Pratap Reddy [Thu, 4 Feb 2021 07:52:44 +0000 (13:22 +0530)]
PDK-9050: Board: Fix for board PLL clock configuration failure on j721e

 - Removed the redundant clock configurations for McASP & ADC
 - Removed the core PLL configurations as they are done by default
 - Updated the clock IDs for some of the modules to fix the errors

4 months agoMigrating to SYSFW version v2020.08d
Piyali Goswami [Tue, 2 Feb 2021 05:23:48 +0000 (10:53 +0530)]
Migrating to SYSFW version v2020.08d

Migrating to SYSFW v2020.08d

4 months agosysfw_migrate.sh: Update to have support for generation of ES1.1 images
Piyali Goswami [Tue, 2 Feb 2021 04:55:28 +0000 (10:25 +0530)]
sysfw_migrate.sh: Update to have support for generation of ES1.1 images

Support for generation of ES1.1 HS tifs images

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
4 months agoFirmware Header Gen updates for ES1.1
Piyali Goswami [Tue, 2 Feb 2021 04:54:36 +0000 (10:24 +0530)]
Firmware Header Gen updates for ES1.1

Support for ES1.1 hs binary generation

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
4 months agoPDK-9050 : Compute core clock config is removed
sujith [Mon, 1 Feb 2021 13:07:07 +0000 (18:37 +0530)]
PDK-9050 : Compute core clock config is removed

The A72, R5F, functional clock should not be reconfigured
disabled the same.

Skipped clock config for McASP and Adc
Will be addressed in subsequent commits

Signed-off-by: sujith <sujith.s@ti.com>
4 months agoAdd build support for awr294x
Prasad Konnur [Sun, 7 Feb 2021 10:40:50 +0000 (16:10 +0530)]
Add build support for awr294x

 - Added basic build support
 - build for csl added with tpr12 soc files
 - build enabled for board lib with tpr12 files. build not enabled for
board Examples / utils.
 - build for few drivers enabled like edma, uart which are used by
common examples

Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
4 months agoUDMA: OSPI Example: Fix Porting for Cypress Flash(J7200/AM64x)
Don Dominic [Tue, 9 Feb 2021 09:41:48 +0000 (15:11 +0530)]
UDMA: OSPI Example: Fix Porting for Cypress Flash(J7200/AM64x)

- Added new test to write PHY tuning data to flash memory
    - Writes phy tuning data to last 128B of Flash memory
    - This region should be made non-cacheable
- Include new phy tuning algo source file from CSL OSPI Common
- Support for new phy tuning(phyConfig) for devices with Cypress flash(AM64x/J7200)
    - Enable phyPiplene mode for DAC DMA Read
- Proper switching from INDAC to DAC mode, after Write operation
    - For devices with Cypress Flash in which DAC write is not supported
      The test writes in INDAC mode and reads in DAC DMA mode
      Here the switch to DAC mode was not Proper.
    - Just calling CSL_ospiDacEnable was not enough
- Added flag to Disable CacheOps in Real-time loop
    - To enable performance measurement without including CacheInv
    - Disabled by default
- Clear the interrupt after breaking from the TR Reload Perpetual loop.
    - During channel forced tear-down to break from the TR Reload Perpetual loop,
      DMA will complete the already reloaded TR.
    - This results in setting the interrupt status register after this transfer completion.
    - Hence clear the interrupt after this.
    - Else it will result in odd behavior with successive UDMA transfers

Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
4 months ago[DSS APP][PDK-9214]DSS Display Examples is not working on eDP
Vivek Dhande [Wed, 3 Feb 2021 12:47:14 +0000 (18:17 +0530)]
[DSS APP][PDK-9214]DSS Display Examples is not working on eDP

- Issue:
    - Display does not recognize the incoming stream and fps seems to be too high ~200

- Root Cause:
    - DSS clock selection was wrong along with wrong frequency
    - Earlier default clock selection was working for DSS which got changed over time, making EDP TC to fail
    - DSS application shall do this configuration rather than relying on default configuration

- Resolution:
    - Select proper clock for DPI
    - Configure following clocks
        - TISCI_DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK to 148.5 MHz
        - TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK to 148.5 MHz

Signed-off-by: Vivek Dhande <a0132295@ti.com>
4 months ago[PDK-9074]OSPI: Adding a summary of OSPI modes supported by each EVM
Aditya Wadhwa [Mon, 1 Feb 2021 13:04:32 +0000 (18:34 +0530)]
[PDK-9074]OSPI: Adding a summary of OSPI modes supported by each EVM

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
4 months agoOSPI: J721e: Fix for large appimage size
Aditya Wadhwa [Fri, 5 Feb 2021 11:41:33 +0000 (17:11 +0530)]
OSPI: J721e: Fix for large appimage size

- marked the txBuf and rxBuf as a benchmark buffer section

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
4 months agoRevert "Revert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain""
Aditya Wadhwa [Fri, 5 Feb 2021 14:30:29 +0000 (20:00 +0530)]
Revert "Revert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain""

This reverts commit 9ac60cdd6d46fd7162a07f1f3a3351884eb9439f.

The fix was reverted due to code freeze. Applying the fix now that the release tag has been created.

4 months agoMailbox: Example: Fix debug build failure in daily build
Angela Stegmaier [Fri, 5 Feb 2021 19:38:30 +0000 (13:38 -0600)]
Mailbox: Example: Fix debug build failure in daily build

Increase the section size in liner file.

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
4 months agoFix for UDMA tests failing after fix for PDK-9013
Piyali Goswami [Sun, 31 Jan 2021 03:21:07 +0000 (08:51 +0530)]
Fix for UDMA tests failing after fix for PDK-9013

Fixes in Sciclient.c where the respHdr is not populated in the respPayload.
The Sciserver logic looks for the payload to have the flags set correctly and because the flags were never copied in the case when the message was forwarded to the TIFS, the response is falsely reported to the calling function.

Signed-off-by: Piyali Goswami <piyali_g@ti.com>
4 months agoRevert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain" REL.CORESDK.07.02.01.11
Vishal Mahaveer [Wed, 27 Jan 2021 19:33:03 +0000 (13:33 -0600)]
Revert "[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain"

This reverts commit 9540772ac3c2b1ff082447675b23c4bfe75842e7.

Temporarily reverting it as this patch came in middle of AM64x RC.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
4 months ago[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain
Aditya Wadhwa [Wed, 23 Dec 2020 16:40:12 +0000 (22:10 +0530)]
[PDK-8607] Fix for interrupt hang on MCU cores in MAIN domain

- added a soc init function to update interrupt number at run time
- added a config soc interrupt path function to set interrupt path
- fixes interrupt hang issue on j721e and j7200
- removed WA of using polling mode in UT

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
4 months agoBoard: Added GTC frequency ID config in am64x board library REL.CORESDK.07.02.01.09 REL.CORESDK.07.02.01.10
M V Pratap Reddy [Sat, 23 Jan 2021 07:00:01 +0000 (12:30 +0530)]
Board: Added GTC frequency ID config in am64x board library

4 months agoBoard: AM64x: Update GTC clk freq to 200 MHz REL.CORESDK.07.02.01.08
Jonathan Bergsagel [Sat, 23 Jan 2021 02:40:04 +0000 (20:40 -0600)]
Board: AM64x: Update GTC clk freq to 200 MHz

Changes GTC input functional clock from the default freq,
of 225 MHz, to the HLOS expected value of 200 MHz.
Solves an issue with SBL booting Linux on AM64x.

Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
4 months agoBoard: Removed unused code in am64x board library
M V Pratap Reddy [Fri, 22 Jan 2021 20:41:26 +0000 (02:11 +0530)]
Board: Removed unused code in am64x board library

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