2 years ago[DSS M2M DRV]KW Fixes : Patch-2 release/CORESDK_07.03.00 REL.CORESDK.07.03.00.28 REL.CORESDK.07.03.00.29 REL.CORESDK.07.03.00.30 REL.CORESDK.07.03.00.31 REL.CORESDK.07.03.00.32 REL.CORESDK.07.03.00.33 REL.CORESDK.07.03.00.34 REL.CORESDK.07.03.00.35
[DSS M2M DRV]KW Fixes : Patch-2
Signed-off-by: Vivek Dhande <a0132295@ti.com>
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M DRV and APP][BUG FIX: Patch - 2]DSS M2M sample application is crashing and failing inturn
- Issue:
- Outputting same color
- In case of RGB format, only 720 line were outputted
- In case of YUV format, outputted Y component is '0'
- For YUV420, WB pipeline was hung after outputting few pixels
- Root-cause:
- Outputted same color was from background, this was happening due to WB pipeline DMA was enabled before VID pipeline
- In case of unsupported format, DSS WB CSL-FL does not return error and programs default value
- CSL was not programming WB scaler unit properly, it was checking inFmt instead of outFmt
- Resolution:
- Updated driver to enable WB Pipeline after enabling VID pipeline
- Updated CSL-FL to use outFmt in checks and programming
- Additional Changes:
- Updated application to for YUV422 to YUV420 CSC
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Issue:
- Outputting same color
- In case of RGB format, only 720 line were outputted
- In case of YUV format, outputted Y component is '0'
- For YUV420, WB pipeline was hung after outputting few pixels
- Root-cause:
- Outputted same color was from background, this was happening due to WB pipeline DMA was enabled before VID pipeline
- In case of unsupported format, DSS WB CSL-FL does not return error and programs default value
- CSL was not programming WB scaler unit properly, it was checking inFmt instead of outFmt
- Resolution:
- Updated driver to enable WB Pipeline after enabling VID pipeline
- Updated CSL-FL to use outFmt in checks and programming
- Additional Changes:
- Updated application to for YUV422 to YUV420 CSC
Signed-off-by: Vivek Dhande <a0132295@ti.com>
UDMA: AM65xx Build Fix
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: Don Dominic <a0486429@ti.com>
SBL: Fix Issues with OSPI DMA boot
- Init Sciclient with mcu1_0 core context as non-secure (default)
- default board cfg is for non-secure mode
- Update in allignment with BoardCfg updates to remove shared allocation for mcu1_0
and entries only for non-secure host
- BoardCfg Update Commits: 770ca7fdd4d and 07897868126
- Without this update Udma_init for OSPI DMA boot would fail
- Since,‘Sciclient_rmGetResourceRange’ is returning ‘start’ and ‘num’ as zero for all resources.
- Verified sbl_baremetal_boot_test_all_cores with OSPI DMA boot on J721E and J7200
Signed-off-by: Don Dominic <a0486429@ti.com>
- Init Sciclient with mcu1_0 core context as non-secure (default)
- default board cfg is for non-secure mode
- Update in allignment with BoardCfg updates to remove shared allocation for mcu1_0
and entries only for non-secure host
- BoardCfg Update Commits: 770ca7fdd4d and 07897868126
- Without this update Udma_init for OSPI DMA boot would fail
- Since,‘Sciclient_rmGetResourceRange’ is returning ‘start’ and ‘num’ as zero for all resources.
- Verified sbl_baremetal_boot_test_all_cores with OSPI DMA boot on J721E and J7200
Signed-off-by: Don Dominic <a0486429@ti.com>
Update ESM test app to call Sciclient_init
ESM test app was calling Sciclient APIs without first calling
Sciclient_init. This led to a failure being returned from
Sciclient_rmGetModuleClkFreq and incorrectly calculated minimum
time interval for the error pin.
This patch fixes the error checking around the Sciclient_* calls
in the test app, and also adds the call to Sciclient_init.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
ESM test app was calling Sciclient APIs without first calling
Sciclient_init. This led to a failure being returned from
Sciclient_rmGetModuleClkFreq and incorrectly calculated minimum
time interval for the error pin.
This patch fixes the error checking around the Sciclient_* calls
in the test app, and also adds the call to Sciclient_init.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
KW Critical and Error Fix
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
OSPI: Static analysis critical issue fix
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
UDMA: KW Fixes
Verified udma_memcpy
Signed-off-by: Don Dominic <a0486429@ti.com>
Verified udma_memcpy
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-6649] OSAL: nonos: Fix issues in TimerP_delte reset mask
- Convert/Reverse map the Timer ID to corresponding timer bit id.
- 'TimerP_mapId' was called during TimerP_create to map the id to respective ID for that core for timer
- the reverse operation is required to clear/reset the appropriate bit in the gTimerAnyMask
- Hence added 'TimerP_reverseMapId' to do the reverse translation
- The above fxn is called before clearing the mask's bit filed to find the correct bit
- Issues was observed in J721E MAIN Domain mcu cores in which the 'TimerP_mapId' translation was active
- Verified OSAL UT
Signed-off-by: Don Dominic <a0486429@ti.com>
- Convert/Reverse map the Timer ID to corresponding timer bit id.
- 'TimerP_mapId' was called during TimerP_create to map the id to respective ID for that core for timer
- the reverse operation is required to clear/reset the appropriate bit in the gTimerAnyMask
- Hence added 'TimerP_reverseMapId' to do the reverse translation
- The above fxn is called before clearing the mask's bit filed to find the correct bit
- Issues was observed in J721E MAIN Domain mcu cores in which the 'TimerP_mapId' translation was active
- Verified OSAL UT
Signed-off-by: Don Dominic <a0486429@ti.com>
[DSS M2M DRV]KW Fixes
Signed-off-by: Vivek Dhande <a0132295@ti.com>
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M DRV APP][Bug Fix][PDK-9479]DSS M2M sample application is crashing and failing inturn
- Issue:
- On running, application crashes and fails
- Root-cause:
- Event configuration and internal mux for pipeline input was wrongly configured
- Fix:
- Updated mux configuration of DSS module
- Fixed few issues with wrong assert conditions
- Additional changes in the Patch
- Updated driver Queue handling in case of driver is stopped i.e. after calling 'FVID2_stop()'
- Added additional check conditions for driver robustness
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Issue:
- On running, application crashes and fails
- Root-cause:
- Event configuration and internal mux for pipeline input was wrongly configured
- Fix:
- Updated mux configuration of DSS module
- Fixed few issues with wrong assert conditions
- Additional changes in the Patch
- Updated driver Queue handling in case of driver is stopped i.e. after calling 'FVID2_stop()'
- Added additional check conditions for driver robustness
Signed-off-by: Vivek Dhande <a0132295@ti.com>
ccs lauch script : Reset MCU 11 to ensure tcm config take effect
Tested with mcspi master/slave example application
Signed-off-by: sujith <sujith.s@ti.com>
Tested with mcspi master/slave example application
Signed-off-by: sujith <sujith.s@ti.com>
PDK-9454 : McSPI : Baremetal master slave not functional
Root Cause : The slave on MPU 10, relies on SCI client APIs
to route interrupts. But MCU 10 hosts baremetal master
and cannot hosrt sci server
Fix : Moved the master to MCU 11 and hosted sci server on mcu 10
Test : Tested on j7200 and j721e
Works as expected on j7200 but DMA fails on j721e
Signed-off-by: sujith <sujith.s@ti.com>
Root Cause : The slave on MPU 10, relies on SCI client APIs
to route interrupts. But MCU 10 hosts baremetal master
and cannot hosrt sci server
Fix : Moved the master to MCU 11 and hosted sci server on mcu 10
Test : Tested on j7200 and j721e
Works as expected on j7200 but DMA fails on j721e
Signed-off-by: sujith <sujith.s@ti.com>
[PDK-9471] J7ES SBL: Fix Issues with sending and parsing of RM board config on HS device
- BUILD_HS flag was missing in SBL IMG build for HS devices
- only SBL_BUILD_HS was passed, which will include correct headers for SBL library build
- But others will include wrong sciclient header files (defaultBoardCfg for GP)
- Hence, SCICLIENT_BOARDCFG_RM_SIZE_IN_BYTES macro for GP was getting passed (instead of that defined for HS)
- And this corrupts/truncates the actual BoardCfg
- Fix by including BUILD_HS flag
Signed-off-by: Don Dominic <a0486429@ti.com>
- BUILD_HS flag was missing in SBL IMG build for HS devices
- only SBL_BUILD_HS was passed, which will include correct headers for SBL library build
- But others will include wrong sciclient header files (defaultBoardCfg for GP)
- Hence, SCICLIENT_BOARDCFG_RM_SIZE_IN_BYTES macro for GP was getting passed (instead of that defined for HS)
- And this corrupts/truncates the actual BoardCfg
- Fix by including BUILD_HS flag
Signed-off-by: Don Dominic <a0486429@ti.com>
OSAL: C++ Build Fix: Resolve J7200 TimerP_getPreferredDefInst Build Errors
- Move extern inline Fxn definition of 'TimerP_getPreferredDefInst'
from 'osal/soc/j7200/TimerP_default_r5f.c' to header file 'osal/soc/j7200/osal_soc.h'
- Fxn is refernced in Arch_utils.c,
which will break C++ build if extern "inline" fxn defined in different source file
- Issue introduced by "b431aefd763ff2f15468e87f67038ed5db55f50f#packages/ti/osal/soc/j7200/osal_soc.h"
Signed-off-by: Don Dominic <a0486429@ti.com>
- Move extern inline Fxn definition of 'TimerP_getPreferredDefInst'
from 'osal/soc/j7200/TimerP_default_r5f.c' to header file 'osal/soc/j7200/osal_soc.h'
- Fxn is refernced in Arch_utils.c,
which will break C++ build if extern "inline" fxn defined in different source file
- Issue introduced by "b431aefd763ff2f15468e87f67038ed5db55f50f#packages/ti/osal/soc/j7200/osal_soc.h"
Signed-off-by: Don Dominic <a0486429@ti.com>
C++ Build fix
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
3 years agoSciclient UT: Fix app failure for C7x/C66x cores REL.CORESDK.07.03.00.23 REL.CORESDK.07.03.00.24
Sciclient UT: Fix app failure for C7x/C66x cores
- Board_unlockMMR() was failing from C7x/C66x
- hence UART_STUDIO , PINMUX was not getting initialized
- This results in UART print issues in the app
- BOARD_INIT_UNLOCK_MMR was added for AM64x
Ref: https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/commits/924bc3e7347515cf69ef89ac71845942ef9576f7#packages/ti/drv/sciclient/examples/common/sciclient_appCommon.c
- Hence protect with #ifdef for AM64x to unblock issues on C66x/C7x on J7
- Verified UT on C7x/C66x/R5/A72 on J7
Signed-off-by: Don Dominic <a0486429@ti.com>
- Board_unlockMMR() was failing from C7x/C66x
- hence UART_STUDIO , PINMUX was not getting initialized
- This results in UART print issues in the app
- BOARD_INIT_UNLOCK_MMR was added for AM64x
Ref: https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/commits/924bc3e7347515cf69ef89ac71845942ef9576f7#packages/ti/drv/sciclient/examples/common/sciclient_appCommon.c
- Hence protect with #ifdef for AM64x to unblock issues on C66x/C7x on J7
- Verified UT on C7x/C66x/R5/A72 on J7
Signed-off-by: Don Dominic <a0486429@ti.com>
OSPI: Build fixes for cached applications
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
PDK-9464 : J7200 : I2C Demo not functional on mcu 21
Root cause : Wrong interrupt number is used for mcu 21.
The commit 0d59f6540b introduced this issue
Fix : Limited the interrupt offset to j721e alone
Test : tested on j7200 mcu 21
Signed-off-by: sujith <sujith.s@ti.com>
Root cause : Wrong interrupt number is used for mcu 21.
The commit 0d59f6540b introduced this issue
Fix : Limited the interrupt offset to j721e alone
Test : tested on j7200 mcu 21
Signed-off-by: sujith <sujith.s@ti.com>
Updating C7x CGT to 1.4.2
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
PTEST-2548: Add SBL combined.appimage build for AM65xx
Adds base-board.dtb file for AM65xx combined.appimage
builds.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Adds base-board.dtb file for AM65xx combined.appimage
builds.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
[PDK-6649] OSAL: nonos: Fix TimerP_delete to update gTimerAnyMask
- TimerP_delete was not resetting the the timer's bit field in the gTimerAnyMask
- Hence the mask was getting exhausted after log2(TIMERP_AVAILABLE_MASK+1) no.of TimerP_create
- This resulted in TimerP_create failures even when there are unused timers
- Update the timer's bit field in the mask while deleting the timer to resolve this
- For v0/v1, Global Timer Structure's used flag was cleared only when Timer ISR is non-NULL
- Fixed this to clear irrespective of Timer ISR
- Also updated the UT with a test to catch this failure
- This tests TimerP_create and TimerP_delete repeatedly for more no.of times than that in the mask,
to make sure freeing up of resources was successful
- The test which was failing earlier, now works fine with the updates in source
Signed-off-by: Don Dominic <a0486429@ti.com>
- TimerP_delete was not resetting the the timer's bit field in the gTimerAnyMask
- Hence the mask was getting exhausted after log2(TIMERP_AVAILABLE_MASK+1) no.of TimerP_create
- This resulted in TimerP_create failures even when there are unused timers
- Update the timer's bit field in the mask while deleting the timer to resolve this
- For v0/v1, Global Timer Structure's used flag was cleared only when Timer ISR is non-NULL
- Fixed this to clear irrespective of Timer ISR
- Also updated the UT with a test to catch this failure
- This tests TimerP_create and TimerP_delete repeatedly for more no.of times than that in the mask,
to make sure freeing up of resources was successful
- The test which was failing earlier, now works fine with the updates in source
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-8586] SBL: OSPI: Early CAN response optimization
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[PDK-6848] OSAL: SYSBIOS: TaskP_delete to delete task only when deleteTerminatedTasks flag is disabled
- In case of apps with the BIOS cfg 'Task.deleteTerminatedTasks' enabled,
cleanup happens in BIOS idle task.
- Deleting terminated task will results in BIOS error.
- Hence to make BIOS config independent, TaskP_delete will check for the flag before deleting any task.
Signed-off-by: Don Dominic <a0486429@ti.com>
- In case of apps with the BIOS cfg 'Task.deleteTerminatedTasks' enabled,
cleanup happens in BIOS idle task.
- Deleting terminated task will results in BIOS error.
- Hence to make BIOS config independent, TaskP_delete will check for the flag before deleting any task.
Signed-off-by: Don Dominic <a0486429@ti.com>
3 years ago[DSS DRV][Bug Fix][PDK-5040]Display stops working if two pipelines are started back... REL.CORESDK.07.03.00.22
[DSS DRV][Bug Fix][PDK-5040]Display stops working if two pipelines are started back to back
- Issue:
- When two display pipelines (connected to the same overlay) are started back to back by calling FVID2_Start() twice, pipelines do not start and does not display anything.
- Same is observed for 2 LCDs
- Resolution:
- Second start has to wait for a VSYNC to come from first pipeline before starting
- Fix:
- We should not allow pipelines to be started back to back until the first vsync callback of pipeline comes.
- Wait for semaphore before starting second pipeline
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Issue:
- When two display pipelines (connected to the same overlay) are started back to back by calling FVID2_Start() twice, pipelines do not start and does not display anything.
- Same is observed for 2 LCDs
- Resolution:
- Second start has to wait for a VSYNC to come from first pipeline before starting
- Fix:
- We should not allow pipelines to be started back to back until the first vsync callback of pipeline comes.
- Wait for semaphore before starting second pipeline
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M DRV]Doxygen build fix
- This patch also contains small driver and app update
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- This patch also contains small driver and app update
Signed-off-by: Vivek Dhande <a0132295@ti.com>
OSPI: Build Fix
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Migrating to SYSFW version v2021.01a
Migrating to v2021.01a
Migrating to v2021.01a
Fixes for Sciclient to not globally disable interrupts
Added a software mechanism to not have to disable interrupts when trying polling mode of operation and still allow secure proxy to not be overwritten by multiple threads.
Fixes: PDK-8945
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Added a software mechanism to not have to disable interrupts when trying polling mode of operation and still allow secure proxy to not be overwritten by multiple threads.
Fixes: PDK-8945
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
[PDK-9436] UDMA : Update offset of C7x events associated to CLEC
Update offset of C7x events associated to CLEC
which will be used for various UDMA events
such that it won't overlap with that for
DRU Local Events(configured by vision apps/TIDL usecases)
or other drivers.
- Currently vision apps configures CLEC DRU Local events to C7x events starting from 32.
- Configures for 16 DRU channels allocated for C7x
- Hence to avoid resource conflict UDMA driver will manage C7x events starting from an offset
- Statically partition 64 C7x events into different sets.
- 0 -31 left for other driver
- 32-47 for routing DRU Local events
- 48-63 to be managed by UDMA for various udma events
- This fixes ADASVISION-2344
Signed-off-by: Don Dominic <a0486429@ti.com>
Update offset of C7x events associated to CLEC
which will be used for various UDMA events
such that it won't overlap with that for
DRU Local Events(configured by vision apps/TIDL usecases)
or other drivers.
- Currently vision apps configures CLEC DRU Local events to C7x events starting from 32.
- Configures for 16 DRU channels allocated for C7x
- Hence to avoid resource conflict UDMA driver will manage C7x events starting from an offset
- Statically partition 64 C7x events into different sets.
- 0 -31 left for other driver
- 32-47 for routing DRU Local events
- 48-63 to be managed by UDMA for various udma events
- This fixes ADASVISION-2344
Signed-off-by: Don Dominic <a0486429@ti.com>
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
- added a cacheEnable field to the hwAttrs
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- added a cacheEnable field to the hwAttrs
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
- added copyright comments
- deleted extra file
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- added copyright comments
- deleted extra file
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
- switched to macro instead of hard-coded values
- flag not working
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- switched to macro instead of hard-coded values
- flag not working
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
- enabled interrupt for INDAC tests
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- enabled interrupt for INDAC tests
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
- all tests passing
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- all tests passing
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
- DAC+DMA, Legacy SPI working
- DAC has data mismatch
- INDAC failure
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- DAC+DMA, Legacy SPI working
- DAC has data mismatch
- INDAC failure
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[WIP][PDK-8726]OSPI: Separate OSPI tests keeping memory cached/non-cached
- OPSI FSS DAT0 memory cached/non-cached
- PHY memory always non-cached
- Build failures
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- OPSI FSS DAT0 memory cached/non-cached
- PHY memory always non-cached
- Build failures
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[WIP][PDK-8726] OSPI: Separate OPSI tests keeping memory cached/non-cached
- Added support for baremetal apps
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- Added support for baremetal apps
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
[WIP][PDK-8726] Separate OSPI tests keeping memory cached/non-cached
- added new tests that export cache as enabled
- separate mpu.xs files for cache enabled/disabled
- RTOS implemented, baremetal pending
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- added new tests that export cache as enabled
- separate mpu.xs files for cache enabled/disabled
- RTOS implemented, baremetal pending
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
Hyperflash : Tested with board diag on j721e es 1.1
Works fine in 166 MHz (333 MHz device clock)
Require to clean up code
Signed-off-by: sujith <sujith.s@ti.com>
Works fine in 166 MHz (333 MHz device clock)
Require to clean up code
Signed-off-by: sujith <sujith.s@ti.com>
PDK-6706 : SPI Master example is not functional
The Master example would perform, couple of transactions with
slave app and stall/timeout with an error.
The "loopback" tests would always fail
Root Cause : The driver do not support operating McSPI in
digital loopback mode. As the IP did not support the same.
Fix: Disabled the loopback mode of operation for j721e & j7200
Test : Tested on j721e evm
Signed-off-by: sujith <sujith.s@ti.com>
The Master example would perform, couple of transactions with
slave app and stall/timeout with an error.
The "loopback" tests would always fail
Root Cause : The driver do not support operating McSPI in
digital loopback mode. As the IP did not support the same.
Fix: Disabled the loopback mode of operation for j721e & j7200
Test : Tested on j721e evm
Signed-off-by: sujith <sujith.s@ti.com>
[PDK-9435] Board: DDR: Enable DDR Thermal Testapp for J7200
- enabled board_ddr_thermal_test_app for j7200 mcu1_0/mcu1_1/mcu2_0/mcu2_1
- Updates in board lib 'board/src/j7200_evm/board_ddrtempmonitor.c'
- to enable all r5 cores
- no interrupt routers b/w DDR controller and Main Domain R5
- so skip Sciclient IRQ Routing
- for MCU Domain R5 cores
- query the IR Range from BoardCfg
- translate to Core Interrupt Idx and configure path
Signed-off-by: Don Dominic <a0486429@ti.com>
- enabled board_ddr_thermal_test_app for j7200 mcu1_0/mcu1_1/mcu2_0/mcu2_1
- Updates in board lib 'board/src/j7200_evm/board_ddrtempmonitor.c'
- to enable all r5 cores
- no interrupt routers b/w DDR controller and Main Domain R5
- so skip Sciclient IRQ Routing
- for MCU Domain R5 cores
- query the IR Range from BoardCfg
- translate to Core Interrupt Idx and configure path
Signed-off-by: Don Dominic <a0486429@ti.com>
Firmware gen.sh update for ES1.1 HS testing
Firmware Gen.sh update for ES1.1 HS testing
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Firmware Gen.sh update for ES1.1 HS testing
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fix for proper sending and parsing of RM board config in HS
Ignoring of the certificate is handled correctly by adjusting the size at source when the certificate is not passed and at sink when the certificate is passed.
Fixes: PDK-9427
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Ignoring of the certificate is handled correctly by adjusting the size at source when the certificate is not passed and at sink when the certificate is passed.
Fixes: PDK-9427
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
[DSS M2M APP]Added sample application for DSS M2M Driver
Signed-off-by: Vivek Dhande <a0132295@ti.com>
Signed-off-by: Vivek Dhande <a0132295@ti.com>
freertos: Add FreeRTOS kernel folders to gitignore
- Add the following folders in ti/kernel/freertos to gitignore
- FreeRTOS-Labs/
- FreeRTOS-LTS/
- These are cloned from https://github.com/FreeRTOS/ as defined in psdk.xml
Signed-off-by: Don Dominic <a0486429@ti.com>
- Add the following folders in ti/kernel/freertos to gitignore
- FreeRTOS-Labs/
- FreeRTOS-LTS/
- These are cloned from https://github.com/FreeRTOS/ as defined in psdk.xml
Signed-off-by: Don Dominic <a0486429@ti.com>
PDK-9285: IPC: Fix KW issues
Fix KW issues for AM64X IPC and MB build.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Fix KW issues for AM64X IPC and MB build.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
[DSS M2M Driver]Addressed review comments
Signed-off-by: Vivek Dhande <a0132295@ti.com>
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M Driver]Fixed Doxygen API Guide Warnings
Signed-off-by: Vivek Dhande <a0132295@ti.com>
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M Driver]Driver implementation: Patch-2
- Added implementation for 'Fvid2_processRequest()' and 'Fvid2_getProcessedRequest()'
- Implemented 'IOCTL_DSS_DCTRL_SET_PATH' and 'IOCTL_DSS_DCTRL_CLEAR_PATH' IOCTLs
- Implemented DMA completion Events
- Implemented internal functions needed for above
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Added implementation for 'Fvid2_processRequest()' and 'Fvid2_getProcessedRequest()'
- Implemented 'IOCTL_DSS_DCTRL_SET_PATH' and 'IOCTL_DSS_DCTRL_CLEAR_PATH' IOCTLs
- Implemented DMA completion Events
- Implemented internal functions needed for above
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M Driver]Driver implementation: Patch-1
- Added 'dss_m2mPriv.h'
- This files contains following
- internal structures required for maintaining driver and HW Module states
- Added support for multiple open/create to support multiple channel support
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Added 'dss_m2mPriv.h'
- This files contains following
- internal structures required for maintaining driver and HW Module states
- Added support for multiple open/create to support multiple channel support
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[DSS M2M DRV][PDK-5179]DSS FVID2 Writeback M2M Driver
- [PDK-5184]DSS Writeback Pipeline Support
- Added interface for DSS M2M driver
- Added nodes & edges for WB pipeline
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- [PDK-5184]DSS Writeback Pipeline Support
- Added interface for DSS M2M driver
- Added nodes & edges for WB pipeline
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[PDK-9432] Sciclient : Rebased and Regenerated Sciclient Binaries
- Regenerated sclient binaries after rebasing
- Validated memcpy with latest binaries on j721e/j7200 mcu1_0 and mcu2_0 with noboot and uart boot.
Signed-off-by: Don Dominic <a0486429@ti.com>
- Regenerated sclient binaries after rebasing
- Validated memcpy with latest binaries on j721e/j7200 mcu1_0 and mcu2_0 with noboot and uart boot.
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-9432] J7200 BoardCfg: Update to the latest auto-generated from SysConfig/k3-resource-partitioning
- This includes the updates in the following:
- Remove shared allocation for MCU R5
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview
- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc
- This includes the updates in the following:
- Remove shared allocation for MCU R5
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview
- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc
[PDK-9432] J721E BoardCfg: Update to the latest auto-generated from SysConfig/k3-resource-partitioning
- This includes the updates in the following:
- Remove shared allocation for MCU R5
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview
- Increase virt id range for A72_2
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/12/overview
- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc
- This includes the updates in the following:
- Remove shared allocation for MCU R5
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/10/overview
- Increase virt id range for A72_2
https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/12/overview
- Rebuilt sciclient_boardcfg; sciclient_boardcfg for HS; sciclient_ccs_init; sciserver_testapp and copied to tools/ccsLoadDmsc
[PDK-9432] Sciclient : Updates to support BoardCfg with mcu1_0 non-secure host id entries
- Do not force mcu1_0 to be in secure mode for all cases
- Set to secure mode in case the message is to be forwarded
- Also The MCU1_0 will always be secure when trying to send the message to the TIFS directly to avoid self blocking.
Signed-off-by: Don Dominic <a0486429@ti.com>
- Do not force mcu1_0 to be in secure mode for all cases
- Set to secure mode in case the message is to be forwarded
- Also The MCU1_0 will always be secure when trying to send the message to the TIFS directly to avoid self blocking.
Signed-off-by: Don Dominic <a0486429@ti.com>
udma_event.c: Do not pass a NULL resp payload for the Sciclient_rmUdmapGcfgCfg function
Response payload should not be NULL. The API fails in that case
Fixes: PDK-9431
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Response payload should not be NULL. The API fails in that case
Fixes: PDK-9431
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
copied binary and built firmware header .h file
PDK-6534 : un-expected ISR if the timer were running, before creation
If the timer was running before the timer was created, on creation
especially in user start mode, an ISR would be triggered before
the timer was started.
Root cause : The timer module is not reset before the ISR registration
so, if the timer count lapses after creation but before starting the
the timer, an FALSE isr would be triggered.
Fix: Reset the timer peripheral at create time. This ensures that
counter is disabled and interrupt notification is disabled
Testing: Tested both baremetal & ti rtos unit test of the timer, it
works as expected. OSAL_Baremetal_TestApp and OSAL_TestApp works as
expected
Signed-off-by: Sujith S <sujith.s@ti.com>
If the timer was running before the timer was created, on creation
especially in user start mode, an ISR would be triggered before
the timer was started.
Root cause : The timer module is not reset before the ISR registration
so, if the timer count lapses after creation but before starting the
the timer, an FALSE isr would be triggered.
Fix: Reset the timer peripheral at create time. This ensures that
counter is disabled and interrupt notification is disabled
Testing: Tested both baremetal & ti rtos unit test of the timer, it
works as expected. OSAL_Baremetal_TestApp and OSAL_TestApp works as
expected
Signed-off-by: Sujith S <sujith.s@ti.com>
3 years agoMMC: Build break fix REL.CORESDK.07.01.06.03 REL.CORESDK.07.01.06.04 REL.CORESDK.07.03.00.18 REL.CORESDK.07.03.00.19
MMC: Build break fix
Signed-off-by: Sujith S <sujith.s@ti.com>
Signed-off-by: Sujith S <sujith.s@ti.com>
freertos: posix support only in git and not in rel pkg
remove support for freertos posix in release package
support only in development git folder
Signed-off-by: Badri S <badri@ti.com>
remove support for freertos posix in release package
support only in development git folder
Signed-off-by: Badri S <badri@ti.com>
PDK-7484 : Disabled HS400 from the supported modes list
As per j721e errata (i2024) HS 400 is not supported
on mmc-sd instance 0
Tested MMCSD Regressions on j721e ES 1.0 EVM
ü01000000011a00006a3765730000000000000000475020200200010002000100CCSBL Revision: 01.00.10.00 (Mar 6 2021 - 01:34:19)
Waiting for tifs.bin ...
CCTIFS ver: 21.1.0--v2021.01 (Terrific Llam
Waiting for multicore app ...
CCCCalibration Start
Calibration: Ticks per ms is 999994
Calibration Completed
:
:
MMCSD Regression Test Menu
--------------------------
Test ID: Description Powercycle Required?
0 DS Mode 1-bit Test No
1 DS Mode Test No
2 HS Mode Test No
8 SDR12 Mode Test Yes
9 SDR25 Mode Test Yes
10 SDR50 Mode Test Yes
11 DDR50 Mode Test Yes
13 Default Unit Test (Max speed) Yes
-1 All non powercycle tests No
-2 Exit the regression test No
Please enter a test ID from the above list: -2
Test ID Entered = -2
Exiting the regression test
All tests have PASSED
3/3 tests passed
Signed-off-by: Sujith S <sujith.s@ti.com>
As per j721e errata (i2024) HS 400 is not supported
on mmc-sd instance 0
Tested MMCSD Regressions on j721e ES 1.0 EVM
ü01000000011a00006a3765730000000000000000475020200200010002000100CCSBL Revision: 01.00.10.00 (Mar 6 2021 - 01:34:19)
Waiting for tifs.bin ...
CCTIFS ver: 21.1.0--v2021.01 (Terrific Llam
Waiting for multicore app ...
CCCCalibration Start
Calibration: Ticks per ms is 999994
Calibration Completed
:
:
MMCSD Regression Test Menu
--------------------------
Test ID: Description Powercycle Required?
0 DS Mode 1-bit Test No
1 DS Mode Test No
2 HS Mode Test No
8 SDR12 Mode Test Yes
9 SDR25 Mode Test Yes
10 SDR50 Mode Test Yes
11 DDR50 Mode Test Yes
13 Default Unit Test (Max speed) Yes
-1 All non powercycle tests No
-2 Exit the regression test No
Please enter a test ID from the above list: -2
Test ID Entered = -2
Exiting the regression test
All tests have PASSED
3/3 tests passed
Signed-off-by: Sujith S <sujith.s@ti.com>
Build Fix: Fix build issues with Board DDR Temp Monitor
- Not applicable for mpu1_0
- Removed #ifdef for BUILD_MCU1_0 when added support for main R5 cores
https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/commits/8e4f1ae9e303b3627fbe71b81bde75b6dd601a07#packages/ti/board/src/j721e_evm/board_ddrtempmonitor.c
- But should have protected with MCU ifdef
- Fixed by adding #ifdef for BUILD_MCU
Signed-off-by: Don Dominic <a0486429@ti.com>
- Not applicable for mpu1_0
- Removed #ifdef for BUILD_MCU1_0 when added support for main R5 cores
https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/pdk/commits/8e4f1ae9e303b3627fbe71b81bde75b6dd601a07#packages/ti/board/src/j721e_evm/board_ddrtempmonitor.c
- But should have protected with MCU ifdef
- Fixed by adding #ifdef for BUILD_MCU
Signed-off-by: Don Dominic <a0486429@ti.com>
3 years ago[PDK-9317][PDK-9316] Board: DDR: Updates in Board DDR thermal monitoring REL.CORESDK.07.01.06.02
[PDK-9317][PDK-9316] Board: DDR: Updates in Board DDR thermal monitoring
- Query from BoardCfg to get the allowed core interrupt IRQ idx
- Add support for other R5F cores
Signed-off-by: Don Dominic <a0486429@ti.com>
- Query from BoardCfg to get the allowed core interrupt IRQ idx
- Add support for other R5F cores
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-9312] FreeeRTOS: Addressed review comments
- Updated linker file to use OCMC/DDR instead of MSMC
- Many times apps/customer copy our linker and struggled due to use of MSMC for MCU R5 apps
Signed-off-by: Don Dominic <a0486429@ti.com>
- Updated linker file to use OCMC/DDR instead of MSMC
- Many times apps/customer copy our linker and struggled due to use of MSMC for MCU R5 apps
Signed-off-by: Don Dominic <a0486429@ti.com>
Build Fix: sciclient_firmware_boot_TestApp linker updates to enable debug build
- '.cinit' program will not fit into available memory in OCMRAM
- Moved bss to TCMB from OCMRAM
Signed-off-by: Don Dominic <a0486429@ti.com>
- '.cinit' program will not fit into available memory in OCMRAM
- Moved bss to TCMB from OCMRAM
Signed-off-by: Don Dominic <a0486429@ti.com>
FreeRTOS: UT Build Fix
Signed-off-by: Don Dominic <a0486429@ti.com>
Signed-off-by: Don Dominic <a0486429@ti.com>
freertos: jenkins build fixes
jenkins build fixes
Signed-off-by: Badri S <badri@ti.com>
jenkins build fixes
Signed-off-by: Badri S <badri@ti.com>
[PDK-9312] OSAL: FreeRTOS: Added osal_freertos support for J7ES/J7VCL/AM65xx
- osal_freertos library added for j721e/j7200/am65xx
Signed-off-by: Don Dominic <a0486429@ti.com>
- osal_freertos library added for j721e/j7200/am65xx
Signed-off-by: Don Dominic <a0486429@ti.com>
[PDK-9312] FreeeRTOS: Added support for freertos on all R5F cores in J7ES/J7VCL/AM65xx
- Enable all R5F cores in am65xx/j7200/j721e
- Added config files for each core with unique DMTimer id
- Add support to copy freertos reset vectors to atcm
- implemented inside 'xPortStartScheduler' before calling 'vPortRestoreTaskContext()'
- Update config file to add define to enable/disable copy of freertos reset vectors to atcm
- By default Enabled for AM65xx since vectors are placed in OCMRAM in the linker file since core reset will clear the atcm
- Updated freertos kernel paths
- Minor cleanups
Signed-off-by: Don Dominic <a0486429@ti.com>
- Enable all R5F cores in am65xx/j7200/j721e
- Added config files for each core with unique DMTimer id
- Add support to copy freertos reset vectors to atcm
- implemented inside 'xPortStartScheduler' before calling 'vPortRestoreTaskContext()'
- Update config file to add define to enable/disable copy of freertos reset vectors to atcm
- By default Enabled for AM65xx since vectors are placed in OCMRAM in the linker file since core reset will clear the atcm
- Updated freertos kernel paths
- Minor cleanups
Signed-off-by: Don Dominic <a0486429@ti.com>
added osal lib for free rtos
- added osal lib
- added semephore osal implementation
- other components of osal use the nonos implementation
- added taskp in freertos
- added memoryP in freertos
- added memoryP test in osal testapp
- added delay implementation using TaskP_sleep
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- added osal lib
- added semephore osal implementation
- other components of osal use the nonos implementation
- added taskp in freertos
- added memoryP in freertos
- added memoryP test in osal testapp
- added delay implementation using TaskP_sleep
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
freertos: fix r5f pmu counter overflow
ensure we periodically check for PMU cycle
counter overflow so that we dont miss incrementing
overflow counter.
Signed-off-by: Badri S <badri@ti.com>
ensure we periodically check for PMU cycle
counter overflow so that we dont miss incrementing
overflow counter.
Signed-off-by: Badri S <badri@ti.com>
freertos: disable interrupt preemption for r5
Disable interrupt preemption for r5 until correct
interrupt preemption support
Signed-off-by: Badri S <badri@ti.com>
Disable interrupt preemption for r5 until correct
interrupt preemption support
Signed-off-by: Badri S <badri@ti.com>
freertos:c66x fixes to ensure csl_vect is not linked in
ensure csl_vect is not wrongly linked in resulting in
interrupts not being serviced by freertos vecs
Signed-off-by: Badri S <badri@ti.com>
ensure csl_vect is not wrongly linked in resulting in
interrupts not being serviced by freertos vecs
Signed-off-by: Badri S <badri@ti.com>
freertos: remove dpl folder and move to port folder
remove dpl folder and move files under port folder
also make test folder freertos specific
Signed-off-by: Badri S <badri@ti.com>
remove dpl folder and move files under port folder
also make test folder freertos specific
Signed-off-by: Badri S <badri@ti.com>
freertos: support for j721e,j7200,am65xx SoCs
Support added for am65xx,j721e,am65xx SoCs
freertos lib made core specific instead of isa
so that freeRTOS config can include core specific
header file
Signed-off-by: Badri S <badri@ti.com>
Support added for am65xx,j721e,am65xx SoCs
freertos lib made core specific instead of isa
so that freeRTOS config can include core specific
header file
Signed-off-by: Badri S <badri@ti.com>
freertos: support for r5f core
freertos support for r5f core ported from mcu_plus_sdk
Signed-off-by: Badri S <badri@ti.com>
freertos support for r5f core ported from mcu_plus_sdk
Signed-off-by: Badri S <badri@ti.com>
freertos: support for c66x core for freertos
freertos c66x port support
Signed-off-by: Badri S <badri@ti.com>
freertos c66x port support
Signed-off-by: Badri S <badri@ti.com>
PDK-7013: Removes VTM workaround for J7ES PG1.1
Removes default workaround flag for J7ES VTM.
Signed-off-by: Erick Narvaez <e-narvaez@ti.com>
Removes default workaround flag for J7ES VTM.
Signed-off-by: Erick Narvaez <e-narvaez@ti.com>
added adcbuf driver for AWR294x SOC
OSPI: PHY tuning benchmarking
- added a macro which can be enabled to get the logs of how much time the PHY tuning elapsed
- switched to UART prints
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- added a macro which can be enabled to get the logs of how much time the PHY tuning elapsed
- switched to UART prints
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
timeSync: v2: Explicitly set no traffic class
The newly added txPktTc field of the Enet DMA packet structure is used
for ICSSG but it's not applicable for CPSW. Hence, it's explicitly set
to indicate that no traffic class is to be used.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
The newly added txPktTc field of the Enet DMA packet structure is used
for ICSSG but it's not applicable for CPSW. Hence, it's explicitly set
to indicate that no traffic class is to be used.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
PDK-9240:Board: Fix for DDR init hang issue on j721e evm during warm reset
- DDR initialization is hanging during the warm reset which is caused
by PLL bypass function. Need to unlock the PLL registers for access
during the warm reset.
- DDR initialization is hanging during the warm reset which is caused
by PLL bypass function. Need to unlock the PLL registers for access
during the warm reset.
PRSDK-8813: Board/USB: Updated AM65xx SerDes configurations
- CSL SerDes USB configurations are updated to fix enumeration failures.
Updated the board library and USB driver to align with updated SerDes
configurations.
- CSL SerDes USB configurations are updated to fix enumeration failures.
Updated the board library and USB driver to align with updated SerDes
configurations.
board - Missing enum and fix include path
Signed-off-by: Prasad Jondhale <prasad.jondhale@ti.com>
Signed-off-by: Prasad Jondhale <prasad.jondhale@ti.com>
[PDK-9404] OSAL: Fix TIMERP_TIMER_FREQ_LO for J7200
- TIMERP_TIMER_FREQ_LO defined in osal_soc.h for J7200 is wrong.(25MHz)
- Input Crystal Frequency for j7200 is 19.2MHz and default Timer clk_sel 0(HFOSC0_CLKOUT) will be 19.2MHz
Signed-off-by: Don Dominic <a0486429@ti.com>
- TIMERP_TIMER_FREQ_LO defined in osal_soc.h for J7200 is wrong.(25MHz)
- Input Crystal Frequency for j7200 is 19.2MHz and default Timer clk_sel 0(HFOSC0_CLKOUT) will be 19.2MHz
Signed-off-by: Don Dominic <a0486429@ti.com>
3 years ago[PDK-9315] Updating BIOS and XDC REL.CORESDK.07.03.00.13 REL.CORESDK.07.03.00.14 REL.CORESDK.07.03.00.15 REL.CORESDK.07.03.00.16 REL.CORESDK.07.03.01.03 REL.CORESDK.07.03.01.04 REL.CORESDK.07.03.01.05 REL.CORESDK.07.03.01.06
[PDK-9315] Updating BIOS and XDC
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
[BugFix] PDK-8886: pdk_examples build fails on Windows
- armstrip or strip6x on windows is not able to delete the strip file
if it already present.
- $(RM) is set to rm -f so will not generate error if the file is not
present.
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
- armstrip or strip6x on windows is not able to delete the strip file
if it already present.
- $(RM) is set to rm -f so will not generate error if the file is not
present.
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
added build support for awr294x
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
3 years agoPDK-9337: Fix for Clocking on J7VCL to use fracf pll calibration REL.CORESDK.07.03.00.10 REL.CORESDK.07.03.00.11 REL.CORESDK.07.03.00.12 REL.CORESDK.07.03.01.02
PDK-9337: Fix for Clocking on J7VCL to use fracf pll calibration
Fix for clocking on J7VCL to use fracf pll calibration
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Fix for clocking on J7VCL to use fracf pll calibration
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
osal: baremetal build fix for mcu1_1
OSAL baremetal build fix for mcu1_1
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
OSAL baremetal build fix for mcu1_1
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Build Fix
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
3 years ago[PDK-9328] OSPI: Binary search instead of linear search for PHY tuning window REL.CORESDK.07.03.00.08
[PDK-9328] OSPI: Binary search instead of linear search for PHY tuning window
- Previous implementation was a linear search algorithm
- Occassional failures observed
- Replaced by a binary search algorithm
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- Previous implementation was a linear search algorithm
- Occassional failures observed
- Replaced by a binary search algorithm
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
SPI packaging error fix
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
CGT update for C7x
Signed-off-by: Ankur <a0132173@ti.com>
Signed-off-by: Ankur <a0132173@ti.com>
Revert "[PDK-9315] Updating the BIOS version to 06.83.02.07"
This reverts commit dca947d3294daa19d842386afa038ef797e35e1b.
This reverts commit dca947d3294daa19d842386afa038ef797e35e1b.
Revert "updating XDC and C7x CGT tool version"
This reverts commit e738709d0f9e45ac20b3092009ed41a49c2b2aea.
This reverts commit e738709d0f9e45ac20b3092009ed41a49c2b2aea.
3 years agosciclient: docs: design: Update to add Domain reset information REL.CORESDK.07.03.00.02 REL.CORESDK.07.03.00.03 REL.CORESDK.07.03.00.04
sciclient: docs: design: Update to add Domain reset information
Doc update to add domain groups reset API information
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Doc update to add domain groups reset API information
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for Domain resets in Sciclient PM
Support for Domain Resets in Sciclient PM
Fixes: PDK-9326
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
Support for Domain Resets in Sciclient PM
Fixes: PDK-9326
Signed-off-by: Piyali Goswami <piyali_g@ti.com>
updating XDC and C7x CGT tool version
Signed-off-by: ankur <ankurbaranwal@ti.com>
Signed-off-by: ankur <ankurbaranwal@ti.com>