From 08b394eb6e72f357e7905e0f1b3ec6f88a68b966 Mon Sep 17 00:00:00 2001 From: Badri S Date: Fri, 30 Oct 2020 06:18:42 +0530 Subject: [PATCH] uniflash/tpr12: Add support for ROM flow Uniflash target binary support for load by TPR12 ROM Signed-off-by: Badri S --- .../ti/board/utils/board_utils_component.mk | 2 ++ .../uniflash/target/soc/tpr12/linker.cmd | 34 +++++++++++++++---- packages/ti/drv/spi/soc/dma/v3/QSPI_dma.c | 11 ++++-- 3 files changed, 38 insertions(+), 9 deletions(-) mode change 100755 => 100644 packages/ti/board/utils/board_utils_component.mk diff --git a/packages/ti/board/utils/board_utils_component.mk b/packages/ti/board/utils/board_utils_component.mk old mode 100755 new mode 100644 index 3b39faac1..5d2077f9e --- a/packages/ti/board/utils/board_utils_component.mk +++ b/packages/ti/board/utils/board_utils_component.mk @@ -164,7 +164,9 @@ export board_utils_uart_flash_programmer_hs_SBL_IMAGEGEN # Uniflash utils is not supported for any profile # other than release due to memory constraint ifneq ($(BUILD_PROFILE), release) +ifneq ($(SOC), tpr12) board_utils_EXAMPLE_LIST = +endif # TPR12 Debug Uniflash build supported endif # ifneq ($(BUILD_PROFILE), release) export board_utils_EXAMPLE_LIST diff --git a/packages/ti/board/utils/uniflash/target/soc/tpr12/linker.cmd b/packages/ti/board/utils/uniflash/target/soc/tpr12/linker.cmd index 47a1bba47..3acc9b947 100755 --- a/packages/ti/board/utils/uniflash/target/soc/tpr12/linker.cmd +++ b/packages/ti/board/utils/uniflash/target/soc/tpr12/linker.cmd @@ -31,16 +31,25 @@ __ABORT_STACK_SIZE = 0x800; __UND_STACK_SIZE = 0x800; __SVC_STACK_SIZE = 0x2000; +/*********************************************************************************** + * This is reserved for the initialization code which is a part of the TCMA. The + * code should setup the MPU to allow L2 execution permissions + ***********************************************************************************/ +#define SBL_INIT_CODE_SIZE 640 +#define SBL_TEST_CCS_LOAD 1 + /*----------------------------------------------------------------------------*/ /* Memory Map */ MEMORY { - /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */ - RESET_VECTORS (X) : origin=0x00000000 length=0x100 - /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */ - TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00 + /* IVT Table for the R5 SBL is always placed at the beginning of the TCM Memory */ + /* Initialization code which executes in the TCM memory and sets up the MPU. */ + INIT_CODE : origin = 0x00000000, length = SBL_INIT_CODE_SIZE + TCMA_RAM (RX) : origin=SBL_INIT_CODE_SIZE length=(0x00008000 - SBL_INIT_CODE_SIZE) TCMB_RAM (RW) : origin=0x00080000 length=0x00008000 - L2_RAM (RW) : origin=0x10200000 length=0x00060000 + /* L2 MEMORY reserved for IVT+Initialization code: */ + L2_RESVD : ORIGIN = 0x10200000, LENGTH = SBL_INIT_CODE_SIZE, fill = 0xBDBDBDBD + L2_RAM (RW) : origin = (0x10200000 + SBL_INIT_CODE_SIZE) length=(0x00060000 - SBL_INIT_CODE_SIZE) L3_RAM (RW) : origin=0x88000000 length=0x00390000 HWA_RAM (RW) : origin=0x82000000 length=0x00020000 } /* end of MEMORY */ @@ -50,8 +59,19 @@ MEMORY SECTIONS { - .rstvectors : {} palign(8) > RESET_VECTORS - .bootCode : {} palign(8) > L2_RAM + /* SBL Initialization Code: This needs to be relocated from the L2 to the TCMA + * The code is executed initially and this will setup the MPU permissions. */ + .sbl_init_code: palign(8), fill=0xabcdabcd + { + *(.rstvectors) /* IVT is put at the beginning of the section */ + . = align(8); + *(.bootCode) + . = align(8); +#if (SBL_TEST_CCS_LOAD == 1) + } > INIT_CODE +#else + } load=L2_RESVD, run=INIT_CODE +#endif .startupCode : {} palign(8) > L2_RAM .startupData : {} palign(8) > L2_RAM, type = NOINIT .text : {} palign(8) > L2_RAM diff --git a/packages/ti/drv/spi/soc/dma/v3/QSPI_dma.c b/packages/ti/drv/spi/soc/dma/v3/QSPI_dma.c index ae7d77cfb..2158d6464 100644 --- a/packages/ti/drv/spi/soc/dma/v3/QSPI_dma.c +++ b/packages/ti/drv/spi/soc/dma/v3/QSPI_dma.c @@ -43,6 +43,7 @@ #include #define QSPI_EVENTQUE (0U) +#define QSPI_DMA_XFER_SIZE_ALIGN (4U) /* DMA functions */ static void QSPI_dmaIsrHandler (uintptr_t appData, uint8_t tcc); @@ -67,8 +68,10 @@ int32_t QSPI_dmaConfig(SPI_Handle handle) QSPI_HwAttrs *hwAttrs; int32_t status = SPI_STATUS_SUCCESS; int32_t edmaStatus = EDMA_NO_ERROR; + QSPI_v1_Object *object; /* Get the pointer to the object and hwAttrs */ + object = (QSPI_v1_Object *)handle->object; hwAttrs = (QSPI_HwAttrs*)handle->hwAttrs; /* Check EDMA handle is not NULL */ @@ -88,7 +91,7 @@ int32_t QSPI_dmaConfig(SPI_Handle handle) status = SPI_STATUS_ERROR; } } - + object->intermediateDmaXferInitiated = false; return status; } @@ -108,13 +111,15 @@ int32_t QSPI_dmaTransfer(SPI_Handle handle, dataPtr = ((uintptr_t)hwAttrs->memMappedBaseAddr + (uintptr_t)transaction->txBuf); + object->intermediateDmaXferInitiated = false; if(SPI_TRANSACTION_TYPE_READ == object->transactionType) { uint32_t i; for (i = 0; i < transaction->count; i += QSPI_DMA_MAX_XFER_SIZE) { - uint32_t xferLen = CSL_NEXT_MULTIPLE_OF(CSL_MIN((transaction->count - i), QSPI_DMA_MAX_XFER_SIZE), 4); + /* QSPI EDMA read transfer should be 4 byte aligned else will result in corrupted tranfer */ + uint32_t xferLen = CSL_NEXT_MULTIPLE_OF(CSL_MIN((transaction->count - i), QSPI_DMA_MAX_XFER_SIZE), QSPI_DMA_XFER_SIZE_ALIGN); if (transaction->count > (i + xferLen)) { @@ -125,6 +130,8 @@ int32_t QSPI_dmaTransfer(SPI_Handle handle, ((uintptr_t)transaction->rxBuf + i), ((uintptr_t)dataPtr + i), xferLen); + //TODO: This reprogramming of intermidiate xfers shoud be done in + //intermediate xfer complete ISR and not in loop here. while (object->intermediateDmaXferInitiated == true); } } -- 2.39.2