From 61b6a4f7d32ef7de036740c7af65f302452e7e4e Mon Sep 17 00:00:00 2001 From: Jacob Stiffler Date: Fri, 1 Nov 2019 14:55:08 -0400 Subject: [PATCH] mcbsp-lld: add to PDK Development of mcbsp-lld has been relocated here from: * Repo: https://git.ti.com/keystone-rtos/mcbsp-lld * Branch: master * Commit ID: cd201419a8b4e4aefee6b9323d9a84f4ea467d6a Signed-off-by: Jacob Stiffler --- packages/ti/drv/mcbsp/.gitignore | 28 + packages/ti/drv/mcbsp/Settings.xdc.xdt | 51 + packages/ti/drv/mcbsp/build/buildlib.xs | 614 +++ packages/ti/drv/mcbsp/build/makefile.mk | 67 + packages/ti/drv/mcbsp/config.bld | 232 + packages/ti/drv/mcbsp/config_mk.bld | 43 + packages/ti/drv/mcbsp/device/Module.xs | 33 + .../device/c6657/src/device_mcbsp_loopback.c | 180 + .../device/c674x/src/device_mcbsp_loopback.c | 184 + .../device/k2g/src/device_mcbsp_loopback.c | 187 + .../omapl138/src/device_mcbsp_loopback.c | 182 + packages/ti/drv/mcbsp/docs/Doxyfile | 293 ++ packages/ti/drv/mcbsp/docs/MCBSP_LLD_SDS.pdf | 4504 +++++++++++++++++ .../mcbsp/docs/MCBSP_LLD_SoftwareManifest.doc | Bin 0 -> 56320 bytes .../mcbsp/docs/MCBSP_LLD_SoftwareManifest.pdf | Bin 0 -> 89727 bytes packages/ti/drv/mcbsp/docs/McBSP_LLD_SDS.doc | Bin 0 -> 438272 bytes packages/ti/drv/mcbsp/docs/Module.xs | 54 + .../drv/mcbsp/docs/ReleaseNotes_MCBSP_LLD.doc | Bin 0 -> 137216 bytes .../drv/mcbsp/docs/ReleaseNotes_MCBSP_LLD.pdf | Bin 0 -> 285734 bytes packages/ti/drv/mcbsp/docs/Thumbs.db | Bin 0 -> 23552 bytes packages/ti/drv/mcbsp/docs/doxyfile.xdt | 302 ++ .../mcbsp/docs/mpbu mcbsp lld aug 2012 .doc | Bin 0 -> 267776 bytes .../docs/mpbumcbsp_C6657July2012Report.html | 1048 ++++ packages/ti/drv/mcbsp/docs/tifooter.htm | 4 + packages/ti/drv/mcbsp/docs/tiheader.htm | 12 + packages/ti/drv/mcbsp/docs/tilogo.gif | Bin 0 -> 1137 bytes packages/ti/drv/mcbsp/docs/titagline.gif | Bin 0 -> 653 bytes packages/ti/drv/mcbsp/eclipseDocs/sample.xml | 20 + .../drv/mcbsp/eclipseDocs/toc_cdoc_sample.xml | 21 + packages/ti/drv/mcbsp/example/Module.xs | 58 + ...CBSP_evmc6657_C66DigLpbkExampleProject.txt | 7 + .../MCBSPDigLpbk/bios6_edma3_drv_sample.h | 186 + .../example/c6657/MCBSPDigLpbk/config.bld | 82 + .../c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.c | 993 ++++ .../c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg | 80 + .../c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd | 9 + .../MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c | 641 +++ .../c6657/MCBSPDigLpbk/sample_c6657_cfg.c | 701 +++ .../c6657/MCBSPDigLpbk/sample_c6657_int_reg.c | 153 + .../example/c6657/MCBSPDigLpbk/sample_cs.c | 419 ++ .../example/c6657/MCBSPDigLpbk/sample_init.c | 226 + .../MCBSP_DigLpbkC66ExampleProject.txt | 11 + .../MCBSPDigLpbk/bios6_edma3_drv_sample.h | 186 + .../c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.c | 978 ++++ .../c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg | 78 + .../c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd | 9 + .../MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c | 639 +++ .../c674x/MCBSPDigLpbk/sample_c6657_cfg.c | 692 +++ .../c674x/MCBSPDigLpbk/sample_c6657_int_reg.c | 228 + .../example/c674x/MCBSPDigLpbk/sample_cs.c | 420 ++ .../example/c674x/MCBSPDigLpbk/sample_init.c | 223 + .../c674x/MCBSPDigLpbk/sample_omapl138_cfg.c | 1391 +++++ .../MCBSPDigLpbk/sample_omapl138_int_reg.c | 152 + .../ti/drv/mcbsp/example/include/MCBSP_log.h | 77 + .../MCBSP_DigLpbkevmK2Gc66ExampleProject.txt | 8 + .../k2g/MCBSPDigLpbk/bios6_edma3_drv_sample.h | 186 + .../mcbsp/example/k2g/MCBSPDigLpbk/config.bld | 82 + .../k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.c | 979 ++++ .../k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg | 80 + .../k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd | 9 + .../MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c | 641 +++ .../example/k2g/MCBSPDigLpbk/sample_k2g_cfg.c | 1217 +++++ ...gLpbk_lcdkOMAPL138_c674xExampleProject.txt | 11 + .../MCBSPDigLpbk/bios6_edma3_drv_sample.h | 186 + .../MCBSPDigLpbk/mcbspMasterDigLpbk.c | 978 ++++ .../MCBSPDigLpbk/mcbspMasterDigLpbk.cfg | 78 + .../MCBSPDigLpbk/mcbspMasterDigLpbk.cmd | 9 + .../MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c | 639 +++ .../example/omapl138/MCBSPDigLpbk/sample_cs.c | 420 ++ .../omapl138/MCBSPDigLpbk/sample_init.c | 223 + .../MCBSPDigLpbk/sample_omapl138_cfg.c | 1391 +++++ .../MCBSPDigLpbk/sample_omapl138_int_reg.c | 152 + packages/ti/drv/mcbsp/include/Module.xs | 33 + packages/ti/drv/mcbsp/include/mcbsp_pvt.h | 448 ++ packages/ti/drv/mcbsp/install/mcbsplld.mpi | 1839 +++++++ packages/ti/drv/mcbsp/makefile | 46 + packages/ti/drv/mcbsp/mcbsp_component.mk | 129 + packages/ti/drv/mcbsp/mcbsp_drv.h | 1245 +++++ packages/ti/drv/mcbsp/mcbsp_osal.h | 515 ++ packages/ti/drv/mcbsp/mcbsp_types.h | 49 + packages/ti/drv/mcbsp/mcbspver.h | 68 + packages/ti/drv/mcbsp/mcbspver.h.xdt | 100 + packages/ti/drv/mcbsp/package.bld | 122 + packages/ti/drv/mcbsp/package.xdc | 15 + packages/ti/drv/mcbsp/package.xs | 86 + packages/ti/drv/mcbsp/setupenv.bat | 84 + packages/ti/drv/mcbsp/setupenv.sh | 4 + packages/ti/drv/mcbsp/src/Module.xs | 87 + packages/ti/drv/mcbsp/src/mcbsp_drv.c | 2724 ++++++++++ packages/ti/drv/mcbsp/src/mcbsp_edma.c | 1952 +++++++ packages/ti/drv/mcbsp/src/mcbsp_ioctl.c | 630 +++ packages/ti/drv/mcbsp/src/src_files_common.mk | 12 + 92 files changed, 34175 insertions(+) create mode 100644 packages/ti/drv/mcbsp/.gitignore create mode 100644 packages/ti/drv/mcbsp/Settings.xdc.xdt create mode 100755 packages/ti/drv/mcbsp/build/buildlib.xs create mode 100644 packages/ti/drv/mcbsp/build/makefile.mk create mode 100644 packages/ti/drv/mcbsp/config.bld create mode 100644 packages/ti/drv/mcbsp/config_mk.bld create mode 100755 packages/ti/drv/mcbsp/device/Module.xs create mode 100644 packages/ti/drv/mcbsp/device/c6657/src/device_mcbsp_loopback.c create mode 100644 packages/ti/drv/mcbsp/device/c674x/src/device_mcbsp_loopback.c create mode 100644 packages/ti/drv/mcbsp/device/k2g/src/device_mcbsp_loopback.c create mode 100644 packages/ti/drv/mcbsp/device/omapl138/src/device_mcbsp_loopback.c create mode 100644 packages/ti/drv/mcbsp/docs/Doxyfile create mode 100644 packages/ti/drv/mcbsp/docs/MCBSP_LLD_SDS.pdf create mode 100644 packages/ti/drv/mcbsp/docs/MCBSP_LLD_SoftwareManifest.doc create mode 100644 packages/ti/drv/mcbsp/docs/MCBSP_LLD_SoftwareManifest.pdf create mode 100644 packages/ti/drv/mcbsp/docs/McBSP_LLD_SDS.doc create mode 100644 packages/ti/drv/mcbsp/docs/Module.xs create mode 100644 packages/ti/drv/mcbsp/docs/ReleaseNotes_MCBSP_LLD.doc create mode 100644 packages/ti/drv/mcbsp/docs/ReleaseNotes_MCBSP_LLD.pdf create mode 100644 packages/ti/drv/mcbsp/docs/Thumbs.db create mode 100644 packages/ti/drv/mcbsp/docs/doxyfile.xdt create mode 100644 packages/ti/drv/mcbsp/docs/mpbu mcbsp lld aug 2012 .doc create mode 100644 packages/ti/drv/mcbsp/docs/mpbumcbsp_C6657July2012Report.html create mode 100644 packages/ti/drv/mcbsp/docs/tifooter.htm create mode 100644 packages/ti/drv/mcbsp/docs/tiheader.htm create mode 100644 packages/ti/drv/mcbsp/docs/tilogo.gif create mode 100644 packages/ti/drv/mcbsp/docs/titagline.gif create mode 100644 packages/ti/drv/mcbsp/eclipseDocs/sample.xml create mode 100644 packages/ti/drv/mcbsp/eclipseDocs/toc_cdoc_sample.xml create mode 100644 packages/ti/drv/mcbsp/example/Module.xs create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/MCBSP_evmc6657_C66DigLpbkExampleProject.txt create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/bios6_edma3_drv_sample.h create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/config.bld create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.c create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_int_reg.c create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_cs.c create mode 100644 packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_init.c create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/MCBSP_DigLpbkC66ExampleProject.txt create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/bios6_edma3_drv_sample.h create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.c create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_c6657_cfg.c create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_c6657_int_reg.c create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_cs.c create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_init.c create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_cfg.c create mode 100644 packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_int_reg.c create mode 100644 packages/ti/drv/mcbsp/example/include/MCBSP_log.h create mode 100644 packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/MCBSP_DigLpbkevmK2Gc66ExampleProject.txt create mode 100644 packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/bios6_edma3_drv_sample.h create mode 100644 packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/config.bld create mode 100644 packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.c create mode 100644 packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg create mode 100644 packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd create mode 100644 packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c create mode 100644 packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/sample_k2g_cfg.c create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/MCBSP_DigLpbk_lcdkOMAPL138_c674xExampleProject.txt create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/bios6_edma3_drv_sample.h create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.c create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_cs.c create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_init.c create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_cfg.c create mode 100644 packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_int_reg.c create mode 100644 packages/ti/drv/mcbsp/include/Module.xs create mode 100644 packages/ti/drv/mcbsp/include/mcbsp_pvt.h create mode 100644 packages/ti/drv/mcbsp/install/mcbsplld.mpi create mode 100644 packages/ti/drv/mcbsp/makefile create mode 100644 packages/ti/drv/mcbsp/mcbsp_component.mk create mode 100644 packages/ti/drv/mcbsp/mcbsp_drv.h create mode 100644 packages/ti/drv/mcbsp/mcbsp_osal.h create mode 100644 packages/ti/drv/mcbsp/mcbsp_types.h create mode 100644 packages/ti/drv/mcbsp/mcbspver.h create mode 100644 packages/ti/drv/mcbsp/mcbspver.h.xdt create mode 100644 packages/ti/drv/mcbsp/package.bld create mode 100644 packages/ti/drv/mcbsp/package.xdc create mode 100644 packages/ti/drv/mcbsp/package.xs create mode 100644 packages/ti/drv/mcbsp/setupenv.bat create mode 100644 packages/ti/drv/mcbsp/setupenv.sh create mode 100644 packages/ti/drv/mcbsp/src/Module.xs create mode 100644 packages/ti/drv/mcbsp/src/mcbsp_drv.c create mode 100644 packages/ti/drv/mcbsp/src/mcbsp_edma.c create mode 100644 packages/ti/drv/mcbsp/src/mcbsp_ioctl.c create mode 100644 packages/ti/drv/mcbsp/src/src_files_common.mk diff --git a/packages/ti/drv/mcbsp/.gitignore b/packages/ti/drv/mcbsp/.gitignore new file mode 100644 index 000000000..36f8dd104 --- /dev/null +++ b/packages/ti/drv/mcbsp/.gitignore @@ -0,0 +1,28 @@ +*.sw? +*~ +*.bak +*.orig +.dlls +.executables +.interfaces +.libraries +.xdcenv.mak +Settings.h +Settings.xdc +build/c674?/ +build/c66/ +build/k2?/ +build/c6657/ +docs/Doxyfile +docs/doxygen/ +docs/mcbsplldDocs.chm +lib/ +/makefile +package.mak +package/ +packages/ +analysis/ +test/*/c66/bios/src +example/*/MCBSPDigLpbk/src/ +Debug/ +Release/ diff --git a/packages/ti/drv/mcbsp/Settings.xdc.xdt b/packages/ti/drv/mcbsp/Settings.xdc.xdt new file mode 100644 index 000000000..e422bfbe2 --- /dev/null +++ b/packages/ti/drv/mcbsp/Settings.xdc.xdt @@ -0,0 +1,51 @@ + +%%{ +/*! + * This template implements the Settings.xdc + */ + /* Versioning */ + var ver = this; + for each(i=0;i 1; i--) { + pkgroot+="/.."; + } + + makefile.writeLine("\n# ROOT Directory"); + makefile.writeLine("export ROOTDIR := "+pkgroot); + + makefile.writeLine("\n# INCLUDE Directory"); + makefile.writeLine("export INCDIR := "+getxdcpath+";$(ROOTDIR)"); + + makefile.writeLine("\n# Common Macros used in make"); + makefile.writeLine("\nifndef RM"); + makefile.writeLine("export RM = rm -f"); + makefile.writeLine("endif"); + + makefile.writeLine("\nifndef CP"); + makefile.writeLine("export CP = cp -p"); + makefile.writeLine("endif"); + + makefile.writeLine("\nexport MKDIR = mkdir -p"); + + makefile.writeLine("\nifndef RMDIR"); + makefile.writeLine("export RMDIR = rm -rf"); + makefile.writeLine("endif"); + + makefile.writeLine("\nifndef SED"); + makefile.writeLine("export SED = sed"); + makefile.writeLine("endif"); + + makefile.writeLine("\nifndef MAKE"); + makefile.writeLine("export MAKE = make"); + makefile.writeLine("endif"); + + makefile.writeLine("\n# PHONY Targets"); + makefile.writeLine(".PHONY: all clean cleanall "); + + makefile.writeLine("\n# FORCE Targets"); + makefile.writeLine("FORCE: "); + + makefile.writeLine("\n# all rule"); + makefile.writeLine("all: .executables"); + makefile.writeLine(".executables: .libraries"); + makefile.writeLine(".libraries:"); + + makefile.writeLine("\n# Clean Rule"); + makefile.writeLine("clean:: clean_package"); + makefile.writeLine("# Clean Top Level Object Directory "); + makefile.writeLine("clean_package :\n\t$(RMDIR) $(LIBDIR)/*/"); + makefile.writeLine("\t$(RMDIR) package/cfg"); + } + else + { + try{ + makefile = fileModule.open("makefile", "a"); + } catch (ex) + { + print("makefile cannot be written to. Please check Writing Permissions."); + java.lang.System.exit(1); + } + + } + + return makefile; +} + +function createLibMake(device, makelibname,targetname, objectPath) +{ + var tooldir; + var cmdprefix; + var targetDir; + var stringname=String(targetname).replace("(xdc.bld.ITarget.Module)",""); + + switch(stringname) + { + case String(C66LE): + tooldir="C6X_GEN_INSTALL_PATH"; + cmdprefix=""; + targetDir="c66/release"; + targetname=C66LE; + break; + case String(C66BE): + tooldir="C6X_GEN_INSTALL_PATH"; + cmdprefix=""; + targetDir="c66/release"; + targetname=C66BE; + break; + case String(A15LE): + tooldir="TOOLCHAIN_PATH_A15"; + cmdprefix="CROSS_TOOL_PRFX"; + targetDir="a15/release"; + targetname=A15LE; + break; + case String(A9LE): + tooldir="TOOLCHAIN_PATH_A9"; + cmdprefix="CROSS_TOOL_PRFX"; + targetDir="a9/release"; + targetname=A9LE; + break; + case String(A8LE): + tooldir="TOOLCHAIN_PATH_A8"; + cmdprefix="CROSS_TOOL_PRFX"; + targetDir="a8/release"; + targetname=A8LE; + break; + case String(M4LE): + tooldir="TOOLCHAIN_PATH_M4"; + cmdprefix=""; + targetDir="m4/release"; + targetname=M4LE; + break; + case String(C674LE): + tooldir="C6X_GEN_INSTALL_PATH"; + cmdprefix=""; + targetDir="c674/release"; + targetname=C674LE; + break; + + } + var fileModule = xdc.module('xdc.services.io.File'); + try{ + var dstFile = new java.io.File(makelibname); + dstFile.getParentFile().mkdirs(); + libmakefile = fileModule.open(makelibname, "w"); + /* Add to Archive list */ + } catch (ex) + { + print(makelibname+" cannot be written to. Please check Writing Permissions."); + java.lang.System.exit(1); + } + libmakefile.writeLine("#*******************************************************************************"); + libmakefile.writeLine("#* FILE PURPOSE: Lower level makefile for Creating Component Libraries"); + libmakefile.writeLine("#*******************************************************************************"); + libmakefile.writeLine("#* FILE NAME: "+makelibname); + libmakefile.writeLine("#*"); + libmakefile.writeLine("#* DESCRIPTION: Defines Source Files, Compilers flags and build rules"); + libmakefile.writeLine("#*"); + libmakefile.writeLine("#*"); + libmakefile.writeLine("#*******************************************************************************"); + libmakefile.writeLine("#"); + libmakefile.writeLine(""); + libmakefile.writeLine("#"); + libmakefile.writeLine("# Macro definitions referenced below"); + libmakefile.writeLine("#"); + libmakefile.writeLine("empty ="); + libmakefile.writeLine("space =$(empty) $(empty)"); + + if ((targetname.name == "A15F") || (targetname.name == "A9F") || (targetname.name == "A8F")) + { + + if(stringname.match("gnu.targets")) + { + libmakefile.writeLine("CC = $("+tooldir+")/bin/$("+cmdprefix+")gcc"); + libmakefile.writeLine("AC = $("+tooldir+")/bin/$("+cmdprefix+")as"); + libmakefile.writeLine("ARIN = $("+tooldir+")/bin/$("+cmdprefix+")ar"); + libmakefile.writeLine("LD = $("+tooldir+")/bin/$("+cmdprefix+")gcc"); + } + else + { + print("Error: Non-GNU targets are not currently supported "); + java.lang.System.exit(1); + + } + + libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include"); + libmakefile.writeLine("OBJEXT = o"+targetname.suffix); + libmakefile.writeLine("AOBJEXT = s"+targetname.suffix); + libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts); + libmakefile.writeLine("ASFLAGS_INTERNAL = " +targetname.asmOpts.prefix+" "+targetname.asm.opts); + libmakefile.writeLine("ARFLAGS_INTERNAL = " +targetname.ar.opts); + libmakefile.writeLine("LNKFLAGS_INTERNAL = " +targetname.lnk.opts); + libmakefile.writeLine("INTERNALDEFS = -MD -MF $@.dep"); + libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map"); /* TBD */ + libmakefile.writeLine("OBJDIR = ./obj/obj_" +targetname.suffix +"/" + device.toString() + "/" + targetDir +"/obj" + "/" + objExtDir); + + } + else + { + + if(stringname.match("ti.targets")) + { + + var rtslibtemp = targetname.lnkOpts.suffix.toString().split("/"); + var rtslib; + for(n=0;n> $@.dep; \\"); + makefilename.writeLine(" $(RM) $@.pp "); + } + } + else if(fileExt == "asm") + { + makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fa $< "); + } + else if(fileExt == "sa") + { + makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< "); + } + + makefilename.writeLine("\n#Create Empty rule for dependency"); + makefilename.writeLine("$("+objectliststring+"):"+makefilename.$private.fd); + makefilename.writeLine(makefilename.$private.fd+":"); + makefilename.writeLine("\n#Include Depedency for "+srcString+" Files"); + makefilename.writeLine("ifneq (clean,$(MAKECMDGOALS))"); + makefilename.writeLine(" -include $("+objectliststring+":%.$(OBJEXT)=%.$(OBJEXT).dep)"); + makefilename.writeLine("endif"); + +} + +/************************************************************************** + * FUNCTION NAME : buildLibrary + ************************************************************************** + * DESCRIPTION : + * Utility function which will build a specific library + **************************************************************************/ +var makefilelocal; +function buildLibrary (socName, isSoc, libOptions, libName, target, libFiles) +{ + var targetDir; + var objExtDir; + + if (target.name == "A15F") + { + targetDir = "a15/release"; + } + else if (target.name == "A9F") + { + targetDir = "a9/release"; + } + else if (target.name == "A8F") + { + targetDir = "a8/release"; + } + else if (target.name == "M4") + { + targetDir = "m4/release"; + } + else if (target.name == "C674") + { + targetDir = "c674"; + } + else + { + targetDir = "c66"; + } + + /* Derive the operating system and soc names */ + if (isSoc == "true") { + var libNameExp = libName+"."+socName; + targetDir = socName+"/"+targetDir; + objExtDir = "soc"; + } + else { + var libNameExp = libName; + objExtDir = "all"; + } + + var lldFullLibraryPath = "./lib/" + targetDir +"/" + libNameExp; + var lldFullBuildPath = "./build/" + targetDir +"/" + libNameExp; + var lldFullLibraryPathMake = "$(LIBDIR)/" + targetDir +"/" + libNameExp; + + /* Create Main make file in the root of package folder */ + makefilelocal = createMake(makefilelocal); + + /* Write the rule to make library in main makefile */ + lib = lldFullBuildPath+".a"+target.suffix; + libMake = lldFullLibraryPathMake+".a"+target.suffix; + var objectPath= "./package/"+lldFullBuildPath; + makefilelocal.writeLine("\n\n# Make rule to create "+libMake+" library"); + makefilelocal.writeLine(".libraries: "+ libMake); + makefilelocal.writeLine(libMake+": FORCE\n\t$(MAKE) -f "+lib+".mk $@"); + + /* Create Library make file in the lib folder */ + var makefilelib= createLibMake(socName, lib+".mk",target,objectPath); + + /* Rule to clean library in main makefile */ + makefilelocal.writeLine("# Rule to clean "+libMake+" library"); + makefilelocal.writeLine("clean ::\n\t$(RM) "+ libMake); + librule="\n\n"+libMake+" :"; + + /* Add files to be compiled */ + /* Separate out the C and assembly files */ + var cfiles= new Array(); + var afiles= new Array(); + var safiles= new Array(); + for each(var srcFile in libFiles) + { + var srcFile=String(srcFile); + var dot = srcFile.lastIndexOf("."); + var extension = srcFile.substr(dot,srcFile.length); + if(extension == ".c") + { + cfiles.push(srcFile); + } + else if(extension == ".sa") + { + safiles.push(srcFile); + } + else if(extension == ".asm") + { + afiles.push(srcFile); + } + else + { + print("ERROR: Unsupported file extension"); + java.lang.System.exit(1); + } + } + if(cfiles.length > 0) + { + makeAddObjects("COMMONSRC",makefilelib,cfiles,libOptions,"c",target, "$(OBJDIR)"); + librule += " $(COMMONSRCCOBJS)"; + } + if(afiles.length > 0) + { + makeAddObjects("COMMONSRC",makefilelib,afiles,libOptions,"asm",target, "$(OBJDIR)"); + librule += " $(COMMONSRCASMOBJS)"; + } + if(safiles.length > 0) + { + makeAddObjects("COMMONSRC",makefilelib,safiles,libOptions,"sa",target, "$(OBJDIR)"); + librule += " $(COMMONSRCSAOBJS)"; + } + + makefilelib.writeLine(librule); + makefilelib.writeLine("\t@echo archiving $? into $@ ..."); + makefilelib.writeLine("\tif [ ! -d $(LIBDIR)/"+targetDir+" ]; then $(MKDIR) $(LIBDIR)/"+targetDir+" ; fi;"); + makefilelib.writeLine("\t$(ARIN) $(ARFLAGS_INTERNAL) $@ $?"); + makefilelib.close(); + + /* Create the Epilogue; which executes after all the builds are completed. + * This is used to generate the benchmark information for the built library. + * Also add the benchmarking information file to the package. */ + + /* Put the temp file in object directory since javascript doesn't have a built in tmpname, + * and don't want --jobs=# with # > 1 to result in collisions */ + var libFullName = lldFullLibraryPath + ".a" + target.suffix; + var tempFile = libFullName + ".xml"; + Pkg.makeEpilogue += ".libraries: " + libFullName + "_size.txt\n"; + Pkg.makeEpilogue += libFullName + "_size.txt: " + libFullName + "\n"; + if ( java.lang.String(target.name).contains('66') ) + { + Pkg.makeEpilogue += "\n\t $(C6X_GEN_INSTALL_PATH)/bin/ofd6x -x " + libFullName + " > " + tempFile; + Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt"; + Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n"; + } + else if (target.name == "M4") + { + Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_M4)/bin/armofd -x " + libFullName + " > " + tempFile; + Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt"; + Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n"; + } + else + { + Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_A15)/bin/$(CROSS_TOOL_PRFX)size " + libFullName + " > " + libFullName + "_size.txt"; + } + Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix + "_size.txt"; + Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullBuildPath + ".a" + target.suffix + ".mk"; + Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix; + + /* We need to clean after ourselves; extend the 'clean' target to take care of this. */ + Pkg.makeEpilogue += "\nclean::\n"; + Pkg.makeEpilogue += "\t$(RM) " + lldFullBuildPath + ".a" + target.suffix + "_size.txt\n"; + Pkg.makeEpilogue += "\t$(RMDIR) " + "$(LIBDIR)/" + targetDir + "/ \n\n"; + + return lib; +} + diff --git a/packages/ti/drv/mcbsp/build/makefile.mk b/packages/ti/drv/mcbsp/build/makefile.mk new file mode 100644 index 000000000..84c936062 --- /dev/null +++ b/packages/ti/drv/mcbsp/build/makefile.mk @@ -0,0 +1,67 @@ +# +# Copyright (c) 2018, Texas Instruments Incorporated +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Texas Instruments Incorporated nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +include $(PDK_INSTALL_PATH)/ti/build/Rules.make +include $(PDK_MCBSP_COMP_PATH)/src/src_files_common.mk + +MODULE_NAME = mcbsp + +ifeq ($(SOC),$(filter $(SOC), k2g c6657 omapl138)) +SRCDIR += device/$(SOC)/src +INCDIR += device +# Common source files across all platforms and cores + SRCS_COMMON += device_mcbsp_loopback.c +endif + +# List all the external components/interfaces, whose interface header files +# need to be included for this component +INCLUDE_EXTERNAL_INTERFACES = pdk edma + + +ifeq ($(SOC),$(filter $(SOC), k2g c6657 omapl138)) +PACKAGE_SRCS_COMMON += device/$(SOC)/src +endif + +CFLAGS_LOCAL_COMMON += $(PDK_CFLAGS) +ifeq ($(CORE),$(filter $(CORE), c66x c674x)) +CFLAGS_LOCAL_COMMON += -DBUILD_DSP +endif + +# Include common make files +ifeq ($(MAKERULEDIR), ) +#Makerule path not defined, define this and assume relative path from ROOTDIR + MAKERULEDIR := $(ROOTDIR)/ti/build/makerules + export MAKERULEDIR +endif +include $(MAKERULEDIR)/common.mk + +# Nothing beyond this point diff --git a/packages/ti/drv/mcbsp/config.bld b/packages/ti/drv/mcbsp/config.bld new file mode 100644 index 000000000..4e07c8072 --- /dev/null +++ b/packages/ti/drv/mcbsp/config.bld @@ -0,0 +1,232 @@ +/****************************************************************************** + * FILE PURPOSE: Build configuration Script for the MCBSP Driver + ****************************************************************************** + * FILE NAME: config.bld + * + * DESCRIPTION: + * This file contains the build configuration script for the MCBSP driver + * and is responsible for configuration of the paths for the various + * tools required to build the driver. + * + * Copyright (C) 2012-2013, Texas Instruments, Inc. + *****************************************************************************/ + +/* Get the Tools Base directory from the Environment Variable. */ +var toolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH"); +var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4"); +var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15"); +var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9"); +var arm9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_ARM9"); +var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8"); + +/* Get the extended debug flags */ +var extDbgFlags = java.lang.System.getenv("EXTDBGFLAGS"); + +/* Get the extended debug flags for A15 */ +var extDbgFlags_a15 = java.lang.System.getenv("EXTDBGFLAGS_A15"); + +/* Get the extended debug flags for A8 */ +var extDbgFlags_a8 = java.lang.System.getenv("EXTDBGFLAGS_A8"); + +/* Get the extended debug flags for A9 */ +var extDbgFlags_a9 = java.lang.System.getenv("EXTDBGFLAGS_A9"); + +/* Get the extended debug flags for ARM9 */ +var extDbgFlags_arm9 = java.lang.System.getenv("EXTDBGFLAGS_ARM9"); +/* Get the extended debug flags for M4 */ +var extDbgFlags_m4 = java.lang.System.getenv("EXTDBGFLAGS_M4"); + +/* Get the base directory for the MCBSP Driver Package */ +var mcbspDriverPath = new java.io.File(".//").getPath(); + +/* Read the part number from the environment variable. */ +var mcbspLLDPartNumber = java.lang.System.getenv("PARTNO"); + +/* Get the base directory for the hyplnk LLD Package */ +var mcbsplldPath = new java.io.File(".//").getPath(); +/* Include Path */ +var mcbsplldIncPath = " -i" + mcbsplldPath; +/* Configure the MCBSP Release Version Information */ +var mcbspDriverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(','); + +/* C66 ELF compiler configuration for Little Endian Mode. */ +var C66LE = xdc.useModule('ti.targets.elf.C66'); +C66LE.rootDir = toolsBaseDir; +C66LE.ccOpts.prefix = "-mo -o3 -q -k -eo.o"; +if(extDbgFlags) + C66LE.ccOpts.prefix = C66LE.ccOpts.prefix + " " + extDbgFlags; + +/* C6740 elf compiler configuration for Little Endian Mode. */ +var C674LE = xdc.useModule('ti.targets.elf.C674'); +C674LE.rootDir = toolsBaseDir; +C674LE.ccOpts.prefix = "-mo -o3 -q -k -eo.o"; +if(extDbgFlags) + C674LE.ccOpts.prefix = C674LE.ccOpts.prefix + " " + extDbgFlags; + +/* C66 ELF compiler configuration for Big Endian Mode. */ +var C66BE = xdc.useModule('ti.targets.elf.C66_big_endian'); +C66BE.rootDir = toolsBaseDir; +C66BE.ccOpts.prefix = "-mo -o3 -q -k -eo.o -DBIGENDIAN"; +if(extDbgFlags) + C66BE.ccOpts.prefix = C66BE.ccOpts.prefix + " " + extDbgFlags; + +/* C674 ELF compiler configuration for Big Endian Mode. */ +var C674BE = xdc.useModule('ti.targets.elf.C674_big_endian'); +C674BE.rootDir = toolsBaseDir; +C674BE.ccOpts.prefix = "-mo -o3 -q -k -eo.o -DBIGENDIAN"; +if(extDbgFlags) + C674BE.ccOpts.prefix = C674BE.ccOpts.prefix + " " + extDbgFlags; + +/* ARMv7 A15 compiler configuration */ +var A15LE = xdc.useModule('gnu.targets.arm.A15F'); +A15LE.rootDir = a15ToolsBaseDir; +A15LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a15 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1"; +if(extDbgFlags_a15) + A15LE.ccOpts.prefix = A15LE.ccOpts.prefix + " " + extDbgFlags_a15; + +/* ARMv7 A9 compiler configuration */ +var A9LE = xdc.useModule('gnu.targets.arm.A9F'); +A9LE.rootDir = a9ToolsBaseDir; +A9LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a9 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1"; +if(extDbgFlags_a9) + A9LE.ccOpts.prefix = A9LE.ccOpts.prefix + " " + extDbgFlags_a9; + +/* ARMv5 ARM9 compiler configuration */ +var ARM9LE = xdc.useModule('ti.targets.arm.elf.Arm9'); +ARM9LE.rootDir = arm9ToolsBaseDir; +ARM9LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=arm926ej-s -msoft-float -mfloat-abi=soft -march=armv5te -marm -DDRA7xx -Dxdc_target_types__=gnu/targets/arm/std.h -Dxdc_target_name__=Arm9 -gstrict-dwarf -Wall -D__ARMv5 -D_LITTLE_ENDIAN=1"; +if(extDbgFlags_arm9) + ARM9LE.ccOpts.prefix = ARM9LE.ccOpts.prefix + " " + extDbgFlags_arm9; + +/* ARMv7 A8 compiler configuration */ +var A8LE = xdc.useModule('gnu.targets.arm.A8F'); +A8LE.rootDir = a8ToolsBaseDir; +A8LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a8 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1"; +if(extDbgFlags_a8) + A8LE.ccOpts.prefix = A8LE.ccOpts.prefix + " " + extDbgFlags_a8; + +/* M4 ELF compiler configuration for Little Endian Mode. */ +var M4LE = xdc.useModule('ti.targets.arm.elf.M4'); +M4LE.rootDir = m4ToolsBaseDir; +M4LE.ccOpts.prefix = "-o4 -qq -pdsw255 -DMAKEFILE_BUILD"; +if(extDbgFlags_m4) + M4LE.ccOpts.prefix = M4LE.ccOpts.prefix + " " + extDbgFlags_m4; + +/* device name (k2?) is inserted between first an second element of this + list to construct device file name for each device */ +var deviceConstruct = [ "device/", "/src/device_mcbsp_loopback.c" ]; + +/* Create the SoC List */ +var socs = { + /* device independent libraries */ + all : + { + /* Build this library */ + build: "true", + /* SoC lib disabled as this is device independent lib */ + socDevLib: "false", + /* Library options */ + copts: "", + /* target lists, kept blank now, would be updated based on argument lists */ + targets: [] + }, + k2g : + { + /* this variable would be reinitialized to true, if XDCARGS contains k2g */ + build: "false", + /* SoC lib enabled */ + socDevLib: "true", + /* Library options */ + copts: " -DDEVICE_K2G -DSOC_K2G", + /* target list */ + targets: [ C66LE, C66BE ] + }, + omapl138 : + { + /* this variable would be reinitialized to true, if XDCARGS contains omapl138 */ + build: "false", + /* SoC lib enabled */ + socDevLib: "true", + /* Library options */ + copts: " -DSOC_OMAPL138", + /* target list */ + targets: [ C674LE ] + }, + c6657 : + { + /* this variable would be reinitialized to true, if XDCARGS contains c6657 */ + build: "false", + /* SoC lib enabled */ + socDevLib: "true", + /* Library options */ + copts: " -DSOC_C6657", + /* target list */ + targets: [ C66LE, C66BE ] + }, +}; + +/************************************************************************** + * FUNCTION NAME : merge + ************************************************************************** + * DESCRIPTION : + * The function is used to merge two arrarys + **************************************************************************/ +function merge() { + var args = arguments; + var hash = {}; + var arr = []; + for (var i = 0; i < args.length; i++) { + for (var j = 0; j < args[i].length; j++) { + if (hash[args[i][j]] !== true) { + arr[arr.length] = args[i][j]; + hash[args[i][j]] = true; + } + } + } + return arr; +} + +/* Grab input from XDCARGS */ +var buildArguments = []; + +/* Construct the build arguments */ +for (var tmp=0; arguments[tmp] != undefined; tmp++) +{ + + /* If no arguments are provided, override for building all */ + if ( ( arguments.length == 1) && (arguments[tmp].equals("./config.bld")) ) + buildArguments[buildArguments.length++] = "all"; + else + buildArguments[buildArguments.length++] = arguments[tmp]; +} + +/* Build targets on this build */ +var build_targets = []; +var soc_names = Object.keys(socs); + +for (var i=0; i < buildArguments.length; i++ ) { + /* Build it for all targets */ + if (buildArguments[i] == "all") { + for (var j = 0; j < soc_names.length; j++) { + build_targets = merge (build_targets.slice(0), socs[soc_names[j]].targets.slice(0)); + /* Set build to "true" for that SoC */ + socs[soc_names[j]].build = "true"; + } + } + else { + /* Skip the first argument, which is ./config.bld to get to next SoCs */ + if (i == 0) continue; + /* Set that build to true if it is found in supported build socs */ + for (j = 0; j < soc_names.length; j++) { + if (buildArguments[i] == soc_names[j]) { + socs[buildArguments[i]].build = "true"; + build_targets = merge (build_targets.slice(0), socs[buildArguments[i]].targets.slice(0)); + break; + } + } + } +} + +/* Update the Build target generated list */ +socs["all"].targets = build_targets; +Build.targets = build_targets; diff --git a/packages/ti/drv/mcbsp/config_mk.bld b/packages/ti/drv/mcbsp/config_mk.bld new file mode 100644 index 000000000..9f16994cf --- /dev/null +++ b/packages/ti/drv/mcbsp/config_mk.bld @@ -0,0 +1,43 @@ +/****************************************************************************** + * FILE PURPOSE: Build configuration Script for the MCBSP LLD + ****************************************************************************** + * FILE NAME: config.bld + * + * DESCRIPTION: + * This file contains the build configuration script for the MCBSP LLD + * and is responsible for configuration of the paths for the various + * tools required to build the LLD. + * + * Copyright (C) 2018, Texas Instruments, Inc. + *****************************************************************************/ + +/* Get the Tools Base directory from the Environment Variable. */ +var toolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH"); +var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4"); +var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15"); +var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9"); +var arm9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_ARM9"); +var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8"); + +/* Get the base directory for the McBSP LLD Driver Package */ +var driverPath = new java.io.File(".//").getPath(); + +/* Include Path */ +var lldIncludePath = " -I" + driverPath + "/src" + " -I" + driverPath + " -I" + driverPath + "/include"; + +/* Configure the McBSP Release Version Information */ +/* 3 steps: remove SPACE and TAB, convert to string and split to make array */ +var mcbspDriverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(','); + +/* Do not Print the Compiler Options */ +var pOpts = 0; + +/* List of all devices that needs to be build via XDC + * As the build happens through makefile, there is nothing to build via XDC + * using the below for packaging infrastructure + */ +var socs = []; +var devices = []; +var build_devices = []; +Build.targets = [] + diff --git a/packages/ti/drv/mcbsp/device/Module.xs b/packages/ti/drv/mcbsp/device/Module.xs new file mode 100755 index 000000000..71a646e79 --- /dev/null +++ b/packages/ti/drv/mcbsp/device/Module.xs @@ -0,0 +1,33 @@ +/****************************************************************************** + * FILE PURPOSE: MCBSP LLD device files. + ****************************************************************************** + * FILE NAME: Module.xs + * + * DESCRIPTION: + * This file contains the module specification for MCBSP LLD device files. + * + * Copyright (C) 2012, Texas Instruments, Inc. + *****************************************************************************/ + +/* Load the library utility. */ +var libUtility = xdc.loadCapsule ("../build/buildlib.xs"); + +/************************************************************************** + * FUNCTION NAME : modBuild + ************************************************************************** + * DESCRIPTION : + * The function is used to add all the source files in the device + * directory into the package. + **************************************************************************/ +function modBuild() +{ + /* Add all the .c files to the release package. */ + var configFiles = libUtility.listAllFiles (".c", "device", true); + for (var k = 0 ; k < configFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k]; + + /* Add all the .h files to the release package. */ + var configFiles = libUtility.listAllFiles (".h", "device", true); + for (var k = 0 ; k < configFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k]; +} diff --git a/packages/ti/drv/mcbsp/device/c6657/src/device_mcbsp_loopback.c b/packages/ti/drv/mcbsp/device/c6657/src/device_mcbsp_loopback.c new file mode 100644 index 000000000..334dcaa97 --- /dev/null +++ b/packages/ti/drv/mcbsp/device/c6657/src/device_mcbsp_loopback.c @@ -0,0 +1,180 @@ +/* + * mcbsp_device.c + * + * This file contains MCBSP IP related EVM (platform) specific routines + * implementation. This file contains the board specific code for enabling + * the use of mcbsp driver, and may contain related device pre-driver + * initialization routines. The file is provided as a sample configuration + * and should be modified by customers for their own platforms and + * configurations. + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/* MCBSP Driver Includes. */ +#include +#include +#include + +/* CSL MCBSP Register Layer */ +#include + +/* CSL Chip Functional Layer */ +#include + + +/*============================================================================*/ +/* IMPORTED VARIABLES */ +/*============================================================================*/ + +extern Mcbsp_HwInfo Mcbsp_deviceInstInfo[CSL_MCBSP_PER_CNT]; +extern Mcbsp_TempBuffer Mcbsp_muteBuf[CSL_MCBSP_PER_CNT]; + +#ifdef MCBSP_LOOPJOB_ENABLE +extern Mcbsp_TempBuffer Mcbsp_loopDstBuf[CSL_MCBSP_PER_CNT]; +extern Mcbsp_TempBuffer Mcbsp_loopSrcBuf[CSL_MCBSP_PER_CNT]; +#endif /* MCBSP_LOOPJOB_ENABLE */ + +/* ========================================================================== */ +/* MODULE FUNCTIONS */ +/* ========================================================================== */ +/** + * \brief Initializes McBSP driver's data structures + * + * This function initializes the McBSP driver's data structures + * including instance objects and channel objects. This is the + * MCBSP Driver Initialization API which needs to be invoked by + * the users to initialize the MCBSP peripheral. This call is + * *mandatory* and should be called before calling any of the + * other driver API's. This can be modified by customers for + * their application and configuration. + * + * \return None + */ +void McbspDevice_init(void) +{ + int32_t devId = 0; + void *key; + + /* Begin Critical Section before accessing shared resources. */ + key = Mcbsp_osalEnterMultipleCoreCriticalSection (); + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* initialize the loop job buffers and the mute buffers for all instances */ +#ifdef MCBSP_LOOPJOB_ENABLE + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf)); + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf)); + memset((void *)Mcbsp_loopDstBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_PER_CNT); + memset((void *)Mcbsp_loopSrcBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_PER_CNT); +#endif /* MCBSP_LOOPJOB_ENABLE */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf)); + memset((void *)Mcbsp_muteBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_PER_CNT); + + /* initialize the information for all the device instances */ + for (devId = 0; devId < CSL_MCBSP_PER_CNT; devId++) + { + if (0 == devId) + { + /* instance 0 initialisation */ + Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId; + Mcbsp_deviceInstInfo[devId].obj.regs = + (CSL_McbspRegsOvly)CSL_Mcbsp0_CFG_DATA_REGS; + Mcbsp_deviceInstInfo[devId].obj.fifoRegs = + (CSL_BfifoRegsOvly)CSL_Mcbsp0_FIFO_CFG_REGS; + Mcbsp_deviceInstInfo[devId].obj.dataAddress = + (CSL_BdataRegsOvly)CSL_Mcbsp0_FIFO_DATA_REGS; + Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum = + (uint32_t)CSL_EDMA3CC2_XEVT0_MCBSP_A; + Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum = + (uint32_t)CSL_EDMA3CC2_REVT0_MCBSP_A; + Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum = + (uint32_t)CSL_INTC0_XEVT0; + Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum = + (uint32_t)CSL_INTC0_REVT0; + } + else if (1 == devId) + { + /* instance 1 initialisation */ + Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId; + Mcbsp_deviceInstInfo[devId].obj.regs = + (CSL_McbspRegsOvly)CSL_Mcbsp1_CFG_DATA_REGS; + Mcbsp_deviceInstInfo[devId].obj.fifoRegs = + (CSL_BfifoRegsOvly)CSL_Mcbsp1_FIFO_CFG_REGS; + Mcbsp_deviceInstInfo[devId].obj.dataAddress = + (CSL_BdataRegsOvly)CSL_Mcbsp1_FIFO_DATA_REGS; + Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum = + (uint32_t)CSL_EDMA3CC2_XEVT1_MCBSP_B; + Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum = + (uint32_t)CSL_EDMA3CC2_REVT1_MCBSP_B; + Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum = + (uint32_t)CSL_INTC0_XEVT1; + Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum = + (uint32_t)CSL_INTC0_REVT1; + } + else + { + /* do nothing */ + } +#ifdef MCBSP_LOOPJOB_ENABLE + /* align the buffers to the cache line size */ + Mcbsp_loopSrcBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_loopSrcBuf[devId].scratchBuf + 0x7F) & ~0x7F); + + Mcbsp_loopDstBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_loopDstBuf[devId].scratchBuf + 0x7F) & ~0x7F); + + Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf)); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf)); +#endif /* MCBSP_LOOPJOB_ENABLE */ + Mcbsp_muteBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_muteBuf[devId].scratchBuf + 0x7F) & ~0x7F); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf)); + } + + /* Writeback Global Objects */ + Mcbsp_osalEndMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (key); + + return; +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ diff --git a/packages/ti/drv/mcbsp/device/c674x/src/device_mcbsp_loopback.c b/packages/ti/drv/mcbsp/device/c674x/src/device_mcbsp_loopback.c new file mode 100644 index 000000000..bb047f8ec --- /dev/null +++ b/packages/ti/drv/mcbsp/device/c674x/src/device_mcbsp_loopback.c @@ -0,0 +1,184 @@ +/* + * mcbsp_device.c + * + * This file contains MCBSP IP related EVM (platform) specific routines + * implementation. This file contains the board specific code for enabling + * the use of mcbsp driver, and may contain related device pre-driver + * initialization routines. The file is provided as a sample configuration + * and should be modified by customers for their own platforms and + * configurations. + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/* MCBSP Driver Includes. */ +#include +#include +#include + +/* CSL MCBSP Register Layer */ +#include + +/* CSL Chip Functional Layer */ +// #include // no functional CSL for Freon + +#include + + +/*============================================================================*/ +/* IMPORTED VARIABLES */ +/*============================================================================*/ + +extern Mcbsp_HwInfo Mcbsp_deviceInstInfo[CSL_MCBSP_PER_CNT]; +extern Mcbsp_TempBuffer Mcbsp_muteBuf[CSL_MCBSP_PER_CNT]; + +#ifdef MCBSP_LOOPJOB_ENABLE +extern Mcbsp_TempBuffer Mcbsp_loopDstBuf[CSL_MCBSP_PER_CNT]; +extern Mcbsp_TempBuffer Mcbsp_loopSrcBuf[CSL_MCBSP_PER_CNT]; +#endif /* MCBSP_LOOPJOB_ENABLE */ + +/* ========================================================================== */ +/* MODULE FUNCTIONS */ +/* ========================================================================== */ +/** + * \brief Initializes McBSP driver's data structures + * + * This function initializes the McBSP driver's data structures + * including instance objects and channel objects. This is the + * MCBSP Driver Initialization API which needs to be invoked by + * the users to initialize the MCBSP peripheral. This call is + * *mandatory* and should be called before calling any of the + * other driver API's. This can be modified by customers for + * their application and configuration. + * + * \return None + */ +void McbspDevice_init(void) +{ + int32_t devId = 0; + void *key; + + /* Begin Critical Section before accessing shared resources. */ + key = Mcbsp_osalEnterMultipleCoreCriticalSection (); + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* initialize the loop job buffers and the mute buffers for all instances */ +#ifdef MCBSP_LOOPJOB_ENABLE + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf)); + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf)); + memset((void *)Mcbsp_loopDstBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_PER_CNT); + memset((void *)Mcbsp_loopSrcBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_PER_CNT); +#endif /* MCBSP_LOOPJOB_ENABLE */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf)); + memset((void *)Mcbsp_muteBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_PER_CNT); + + /* initialize the information for all the device instances */ + for (devId = 0; devId < CSL_MCBSP_PER_CNT; devId++) + { + if (0 == devId) + { + /* instance 0 initialisation */ + /* instance 0 initialisation */ + Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId; + Mcbsp_deviceInstInfo[devId].obj.regs = + (CSL_McbspRegsOvly)CSL_MCBSP_0_CTRL_REGS; + Mcbsp_deviceInstInfo[devId].obj.fifoRegs = + (CSL_BfifoRegsOvly)CSL_MCBSP_0_FIFO_REGS; + Mcbsp_deviceInstInfo[devId].obj.dataAddress = + (CSL_BdataRegsOvly)CSL_MCBSP_0_DATA_REGS; + Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP0_TX; + Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP0_RX; + Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP0_TXINT ; + Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP0_RXINT ; + } + else if (1 == devId) + { + /* instance 1 initialisation */ + Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId; + Mcbsp_deviceInstInfo[devId].obj.regs = + (CSL_McbspRegsOvly)CSL_MCBSP_1_CTRL_REGS; + Mcbsp_deviceInstInfo[devId].obj.fifoRegs = + (CSL_BfifoRegsOvly)CSL_MCBSP_1_FIFO_REGS; + Mcbsp_deviceInstInfo[devId].obj.dataAddress = + (CSL_BdataRegsOvly)CSL_MCBSP_1_DATA_REGS; + Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP1_TX; + Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP1_RX; + Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP1_TXINT ; + Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP1_RXINT ; + } + else + { + /* do nothing */ + } + +#ifdef MCBSP_LOOPJOB_ENABLE + /* align the buffers to the cache line size */ + Mcbsp_loopSrcBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_loopSrcBuf[devId].scratchBuf + 0x7F) & ~0x7F); + + Mcbsp_loopDstBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_loopDstBuf[devId].scratchBuf + 0x7F) & ~0x7F); + + Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf)); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf)); +#endif /* MCBSP_LOOPJOB_ENABLE */ + Mcbsp_muteBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_muteBuf[devId].scratchBuf + 0x7F) & ~0x7F); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf)); + } + + /* Writeback Global Objects */ + Mcbsp_osalEndMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (key); + + return; +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ diff --git a/packages/ti/drv/mcbsp/device/k2g/src/device_mcbsp_loopback.c b/packages/ti/drv/mcbsp/device/k2g/src/device_mcbsp_loopback.c new file mode 100644 index 000000000..eb37b96a1 --- /dev/null +++ b/packages/ti/drv/mcbsp/device/k2g/src/device_mcbsp_loopback.c @@ -0,0 +1,187 @@ +/* + * mcbsp_device.c + * + * This file contains MCBSP IP related EVM (platform) specific routines + * implementation. This file contains the board specific code for enabling + * the use of mcbsp driver, and may contain related device pre-driver + * initialization routines. The file is provided as a sample configuration + * and should be modified by customers for their own platforms and + * configurations. + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/* MCBSP Driver Includes. */ +#include +#include +#include + +/* CSL MCBSP Register Layer */ +#include + +#include +/* CSL Chip Functional Layer */ +// #include // no functional CSL for Freon + +//#include + + +/*============================================================================*/ +/* IMPORTED VARIABLES */ +/*============================================================================*/ + +extern Mcbsp_HwInfo Mcbsp_deviceInstInfo[CSL_MCBSP_CNT]; +extern Mcbsp_TempBuffer Mcbsp_muteBuf[CSL_MCBSP_CNT]; + +#ifdef MCBSP_LOOPJOB_ENABLE +extern Mcbsp_TempBuffer Mcbsp_loopDstBuf[CSL_MCBSP_CNT]; +extern Mcbsp_TempBuffer Mcbsp_loopSrcBuf[CSL_MCBSP_CNT]; +#endif /* MCBSP_LOOPJOB_ENABLE */ + +/* ========================================================================== */ +/* MODULE FUNCTIONS */ +/* ========================================================================== */ +/** + * \brief Initializes McBSP driver's data structures + * + * This function initializes the McBSP driver's data structures + * including instance objects and channel objects. This is the + * MCBSP Driver Initialization API which needs to be invoked by + * the users to initialize the MCBSP peripheral. This call is + * *mandatory* and should be called before calling any of the + * other driver API's. This can be modified by customers for + * their application and configuration. + * + * \return None + */ +void McbspDevice_init(void) +{ + int32_t devId = 0; + void *key; + + /* Begin Critical Section before accessing shared resources. */ + key = Mcbsp_osalEnterMultipleCoreCriticalSection (); + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* initialize the loop job buffers and the mute buffers for all instances */ +#ifdef MCBSP_LOOPJOB_ENABLE + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf)); + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf)); + memset((void *)Mcbsp_loopDstBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_CNT); + memset((void *)Mcbsp_loopSrcBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_CNT); +#endif /* MCBSP_LOOPJOB_ENABLE */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf)); + memset((void *)Mcbsp_muteBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_CNT); + + /* initialize the information for all the device instances */ + for (devId = 0; devId < CSL_MCBSP_CNT; devId++) + { + if (0 == devId) + { + /* instance 0 initialisation */ + /* instance 0 initialisation */ + Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId; + Mcbsp_deviceInstInfo[devId].obj.regs = + (CSL_McbspRegsOvly)CSL_MCBSP_0_CFG_REGS; + Mcbsp_deviceInstInfo[devId].obj.fifoRegs = + (CSL_BfifoRegsOvly)CSL_MCBSP_0_FIFO_CFG_REGS; + Mcbsp_deviceInstInfo[devId].obj.dataAddress = + (CSL_BdataRegsOvly)CSL_MCBSP_0_SLV_REGS; + Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum = + (uint32_t)CSL_EDMACC_0_McBSP_XEVT; + Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum = + (uint32_t)CSL_EDMACC_0_McBSP_REVT; + Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum = + (uint32_t)CSL_CIC_McBSP_XINT ; + Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum = + (uint32_t)CSL_CIC_McBSP_RINT ; + } +#if 0 + else if (1 == devId) + { + /* instance 1 initialisation */ + Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId; + Mcbsp_deviceInstInfo[devId].obj.regs = + (CSL_McbspRegsOvly)CSL_MCBSP_1_CTRL_REGS; + Mcbsp_deviceInstInfo[devId].obj.fifoRegs = + (CSL_BfifoRegsOvly)CSL_MCBSP_1_FIFO_REGS; + Mcbsp_deviceInstInfo[devId].obj.dataAddress = + (CSL_BdataRegsOvly)CSL_MCBSP_1_DATA_REGS; + Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP1_TX; + Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP1_RX; + Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP1_TXINT ; + Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP1_RXINT ; + } +#endif + else + { + /* do nothing */ + } + +#ifdef MCBSP_LOOPJOB_ENABLE + /* align the buffers to the cache line size */ + Mcbsp_loopSrcBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_loopSrcBuf[devId].scratchBuf + 0x7F) & ~0x7F); + + Mcbsp_loopDstBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_loopDstBuf[devId].scratchBuf + 0x7F) & ~0x7F); + + Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf)); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf)); +#endif /* MCBSP_LOOPJOB_ENABLE */ + Mcbsp_muteBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_muteBuf[devId].scratchBuf + 0x7F) & ~0x7F); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf)); + } + + /* Writeback Global Objects */ + Mcbsp_osalEndMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (key); + + return; +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ diff --git a/packages/ti/drv/mcbsp/device/omapl138/src/device_mcbsp_loopback.c b/packages/ti/drv/mcbsp/device/omapl138/src/device_mcbsp_loopback.c new file mode 100644 index 000000000..6cc3bceaf --- /dev/null +++ b/packages/ti/drv/mcbsp/device/omapl138/src/device_mcbsp_loopback.c @@ -0,0 +1,182 @@ +/* + * mcbsp_device.c + * + * This file contains MCBSP IP related EVM (platform) specific routines + * implementation. This file contains the board specific code for enabling + * the use of mcbsp driver, and may contain related device pre-driver + * initialization routines. The file is provided as a sample configuration + * and should be modified by customers for their own platforms and + * configurations. + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/* MCBSP Driver Includes. */ +#include +#include +#include + +/* CSL MCBSP Register Layer */ +#include + +#include + +#include + +/*============================================================================*/ +/* IMPORTED VARIABLES */ +/*============================================================================*/ + +extern Mcbsp_HwInfo Mcbsp_deviceInstInfo[CSL_MCBSP_CNT]; +extern Mcbsp_TempBuffer Mcbsp_muteBuf[CSL_MCBSP_CNT]; + +#ifdef MCBSP_LOOPJOB_ENABLE +extern Mcbsp_TempBuffer Mcbsp_loopDstBuf[CSL_MCBSP_CNT]; +extern Mcbsp_TempBuffer Mcbsp_loopSrcBuf[CSL_MCBSP_CNT]; +#endif /* MCBSP_LOOPJOB_ENABLE */ + +/* ========================================================================== */ +/* MODULE FUNCTIONS */ +/* ========================================================================== */ +/** + * \brief Initializes McBSP driver's data structures + * + * This function initializes the McBSP driver's data structures + * including instance objects and channel objects. This is the + * MCBSP Driver Initialization API which needs to be invoked by + * the users to initialize the MCBSP peripheral. This call is + * *mandatory* and should be called before calling any of the + * other driver API's. This can be modified by customers for + * their application and configuration. + * + * \return None + */ +void McbspDevice_init(void) +{ + int32_t devId = 0; + void *key; + + /* Begin Critical Section before accessing shared resources. */ + key = Mcbsp_osalEnterMultipleCoreCriticalSection (); + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* initialize the loop job buffers and the mute buffers for all instances */ +#ifdef MCBSP_LOOPJOB_ENABLE + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf)); + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf)); + memset((void *)Mcbsp_loopDstBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_CNT); + memset((void *)Mcbsp_loopSrcBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_CNT); +#endif /* MCBSP_LOOPJOB_ENABLE */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf)); + memset((void *)Mcbsp_muteBuf,0x0, + sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_CNT); + + /* initialize the information for all the device instances */ + for (devId = 0; devId < CSL_MCBSP_CNT; devId++) + { + if (0 == devId) + { + /* instance 0 initialisation */ + /* instance 0 initialisation */ + Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId; + Mcbsp_deviceInstInfo[devId].obj.regs = + (CSL_McbspRegsOvly)CSL_MCBSP_0_CTRL_REGS; + Mcbsp_deviceInstInfo[devId].obj.fifoRegs = + (CSL_BfifoRegsOvly)CSL_MCBSP_0_FIFO_REGS; + Mcbsp_deviceInstInfo[devId].obj.dataAddress = + (CSL_BdataRegsOvly)CSL_MCBSP_0_DATA_REGS; + Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP0_TX; + Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP0_RX; + Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP0_TXINT ; + Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP0_RXINT ; + } + else if (1 == devId) + { + /* instance 1 initialisation */ + Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId; + Mcbsp_deviceInstInfo[devId].obj.regs = + (CSL_McbspRegsOvly)CSL_MCBSP_1_CTRL_REGS; + Mcbsp_deviceInstInfo[devId].obj.fifoRegs = + (CSL_BfifoRegsOvly)CSL_MCBSP_1_FIFO_REGS; + Mcbsp_deviceInstInfo[devId].obj.dataAddress = + (CSL_BdataRegsOvly)CSL_MCBSP_1_DATA_REGS; + Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP1_TX; + Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum = + (uint32_t)CSL_EDMA3_CHA_MCBSP1_RX; + Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP1_TXINT ; + Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum = + (uint32_t)CSL_INTC_EVENTID_MCBSP1_RXINT ; + } + else + { + /* do nothing */ + } + +#ifdef MCBSP_LOOPJOB_ENABLE + /* align the buffers to the cache line size */ + Mcbsp_loopSrcBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_loopSrcBuf[devId].scratchBuf + 0x7F) & ~0x7F); + + Mcbsp_loopDstBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_loopDstBuf[devId].scratchBuf + 0x7F) & ~0x7F); + + Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf)); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf)); +#endif /* MCBSP_LOOPJOB_ENABLE */ + Mcbsp_muteBuf[devId].scratchBuffer = (uint32_t *) + (((uint32_t)Mcbsp_muteBuf[devId].scratchBuf + 0x7F) & ~0x7F); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf)); + } + + /* Writeback Global Objects */ + Mcbsp_osalEndMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (key); + + return; +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ diff --git a/packages/ti/drv/mcbsp/docs/Doxyfile b/packages/ti/drv/mcbsp/docs/Doxyfile new file mode 100644 index 000000000..e30432f35 --- /dev/null +++ b/packages/ti/drv/mcbsp/docs/Doxyfile @@ -0,0 +1,293 @@ + +# Doxyfile 1.5.6 + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- +DOXYFILE_ENCODING = UTF-8 +PROJECT_NAME = "MCBSP Low Level Driver" +PROJECT_NUMBER = 1.0.0.2 +OUTPUT_DIRECTORY = ./docs/doxygen +CREATE_SUBDIRS = NO +OUTPUT_LANGUAGE = English +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = "The $name class" \ + "The $name widget" \ + "The $name file" \ + is \ + provides \ + specifies \ + contains \ + represents \ + a \ + an \ + the +ALWAYS_DETAILED_SEC = NO +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = NO +STRIP_FROM_PATH = +STRIP_FROM_INC_PATH = +SHORT_NAMES = NO +JAVADOC_AUTOBRIEF = NO +QT_AUTOBRIEF = NO +MULTILINE_CPP_IS_BRIEF = NO +DETAILS_AT_TOP = NO +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 8 +ALIASES = +OPTIMIZE_OUTPUT_FOR_C = YES +OPTIMIZE_OUTPUT_JAVA = NO +OPTIMIZE_FOR_FORTRAN = NO +OPTIMIZE_OUTPUT_VHDL = NO +BUILTIN_STL_SUPPORT = NO +CPP_CLI_SUPPORT = NO +SIP_SUPPORT = NO +IDL_PROPERTY_SUPPORT = YES +DISTRIBUTE_GROUP_DOC = NO +SUBGROUPING = YES +TYPEDEF_HIDES_STRUCT = NO +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- +EXTRACT_ALL = NO +EXTRACT_PRIVATE = NO +EXTRACT_STATIC = YES +EXTRACT_LOCAL_CLASSES = YES +EXTRACT_LOCAL_METHODS = NO +EXTRACT_ANON_NSPACES = NO +HIDE_UNDOC_MEMBERS = YES +HIDE_UNDOC_CLASSES = YES +HIDE_FRIEND_COMPOUNDS = NO +HIDE_IN_BODY_DOCS = NO +INTERNAL_DOCS = NO +CASE_SENSE_NAMES = NO +HIDE_SCOPE_NAMES = NO +SHOW_INCLUDE_FILES = YES +INLINE_INFO = YES +SORT_MEMBER_DOCS = YES +SORT_BRIEF_DOCS = NO +SORT_GROUP_NAMES = NO +SORT_BY_SCOPE_NAME = NO +GENERATE_TODOLIST = YES +GENERATE_TESTLIST = YES +GENERATE_BUGLIST = YES +GENERATE_DEPRECATEDLIST= YES +ENABLED_SECTIONS = +MAX_INITIALIZER_LINES = 30 +SHOW_USED_FILES = YES +SHOW_DIRECTORIES = NO +SHOW_FILES = YES +SHOW_NAMESPACES = YES +FILE_VERSION_FILTER = +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- +QUIET = NO +WARNINGS = YES +WARN_IF_UNDOCUMENTED = YES +WARN_IF_DOC_ERROR = YES +WARN_NO_PARAMDOC = NO +WARN_FORMAT = "$file:$line: $text" +WARN_LOGFILE = +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- +INPUT = +INPUT_ENCODING = UTF-8 +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.d \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.idl \ + *.odl \ + *.cs \ + *.php \ + *.php3 \ + *.inc \ + *.m \ + *.mm \ + *.dox \ + *.py \ + *.f90 \ + *.f \ + *.vhd \ + *.vhdl +RECURSIVE = YES +EXCLUDE = YES \ + ./example \ + ./test \ + ./package \ + ./packages +EXCLUDE_SYMLINKS = NO +EXCLUDE_PATTERNS = cslr_*.h +EXCLUDE_SYMBOLS = +EXAMPLE_PATH = +EXAMPLE_PATTERNS = * +EXAMPLE_RECURSIVE = NO +IMAGE_PATH = +INPUT_FILTER = +FILTER_PATTERNS = +FILTER_SOURCE_FILES = NO +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- +SOURCE_BROWSER = NO +INLINE_SOURCES = NO +STRIP_CODE_COMMENTS = YES +REFERENCED_BY_RELATION = NO +REFERENCES_RELATION = NO +REFERENCES_LINK_SOURCE = YES +USE_HTAGS = NO +VERBATIM_HEADERS = NO +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- +ALPHABETICAL_INDEX = NO +COLS_IN_ALPHA_INDEX = 5 +IGNORE_PREFIX = +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- +GENERATE_HTML = YES +HTML_OUTPUT = html +HTML_FILE_EXTENSION = .html +HTML_HEADER = ./docs/tiheader.htm +HTML_FOOTER = ./docs/tifooter.htm +HTML_STYLESHEET = +HTML_ALIGN_MEMBERS = YES +GENERATE_HTMLHELP = YES +GENERATE_DOCSET = NO +DOCSET_FEEDNAME = "Doxygen generated docs" +DOCSET_BUNDLE_ID = org.doxygen.Project +HTML_DYNAMIC_SECTIONS = NO +CHM_FILE = ..\..\mcbsplldDocs.chm +HHC_LOCATION = hhc.exe +GENERATE_CHI = NO +CHM_INDEX_ENCODING = +BINARY_TOC = NO +TOC_EXPAND = NO +DISABLE_INDEX = NO +ENUM_VALUES_PER_LINE = 4 +GENERATE_TREEVIEW = NONE +TREEVIEW_WIDTH = 250 +FORMULA_FONTSIZE = 10 +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- +GENERATE_LATEX = NO +LATEX_OUTPUT = latex +LATEX_CMD_NAME = latex +MAKEINDEX_CMD_NAME = makeindex +COMPACT_LATEX = NO +PAPER_TYPE = a4wide +EXTRA_PACKAGES = +LATEX_HEADER = +PDF_HYPERLINKS = YES +USE_PDFLATEX = YES +LATEX_BATCHMODE = NO +LATEX_HIDE_INDICES = NO +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- +GENERATE_RTF = NO +RTF_OUTPUT = rtf +COMPACT_RTF = NO +RTF_HYPERLINKS = NO +RTF_STYLESHEET_FILE = +RTF_EXTENSIONS_FILE = +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- +GENERATE_MAN = NO +MAN_OUTPUT = man +MAN_EXTENSION = .3 +MAN_LINKS = NO +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- +GENERATE_XML = NO +XML_OUTPUT = xml +XML_SCHEMA = +XML_DTD = +XML_PROGRAMLISTING = YES +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- +GENERATE_AUTOGEN_DEF = NO +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- +GENERATE_PERLMOD = NO +PERLMOD_LATEX = NO +PERLMOD_PRETTY = YES +PERLMOD_MAKEVAR_PREFIX = +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = NO +EXPAND_ONLY_PREDEF = NO +SEARCH_INCLUDES = YES +INCLUDE_PATH = +INCLUDE_FILE_PATTERNS = +PREDEFINED = +EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +PERL_PATH = /usr/bin/perl +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- +CLASS_DIAGRAMS = NO +MSCGEN_PATH = +HIDE_UNDOC_RELATIONS = YES +HAVE_DOT = NO +DOT_FONTNAME = FreeSans +DOT_FONTPATH = +CLASS_GRAPH = YES +COLLABORATION_GRAPH = YES +GROUP_GRAPHS = YES +UML_LOOK = NO +TEMPLATE_RELATIONS = NO +INCLUDE_GRAPH = YES +INCLUDED_BY_GRAPH = YES +CALL_GRAPH = NO +CALLER_GRAPH = NO +GRAPHICAL_HIERARCHY = YES +DIRECTORY_GRAPH = YES +DOT_IMAGE_FORMAT = png +DOT_PATH = +DOTFILE_DIRS = +DOT_GRAPH_MAX_NODES = 50 +MAX_DOT_GRAPH_DEPTH = 1000 +DOT_TRANSPARENT = YES +DOT_MULTI_TARGETS = NO +GENERATE_LEGEND = YES +DOT_CLEANUP = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- +SEARCHENGINE = NO + + diff --git a/packages/ti/drv/mcbsp/docs/MCBSP_LLD_SDS.pdf b/packages/ti/drv/mcbsp/docs/MCBSP_LLD_SDS.pdf new file mode 100644 index 000000000..6a38abfe4 --- /dev/null +++ b/packages/ti/drv/mcbsp/docs/MCBSP_LLD_SDS.pdf @@ -0,0 +1,4504 @@ +%PDF-1.4 +%âãÏÓ +1 0 obj +<< +/Title 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mode 100644 index 000000000..88dc645b9 --- /dev/null +++ b/packages/ti/drv/mcbsp/docs/Module.xs @@ -0,0 +1,54 @@ +/****************************************************************************** + * FILE PURPOSE: MCBSP LLD DOCS Module specification file. + ****************************************************************************** + * FILE NAME: Module.xs + * + * DESCRIPTION: + * This file contains the module specification for the MCBSP LLD Documentation. + * + * Copyright (C) 2012, Texas Instruments, Inc. + *****************************************************************************/ + +/* Load the library utility. */ +var libUtility = xdc.loadCapsule ("../build/buildlib.xs"); + +/************************************************************************** + * FUNCTION NAME : modBuild + ************************************************************************** + * DESCRIPTION : + * The function is used to build all the components of the documentation + **************************************************************************/ +function modBuild() +{ + /* Create the actual PROLOGUE Section for the Documentation.*/ + Pkg.makePrologue += "release: mcbsp_lld_document_generation\n"; + Pkg.makePrologue += "mcbsp_lld_document_generation:\n"; + Pkg.makePrologue += "\t @echo -------------------------------------------------------\n"; + Pkg.makePrologue += "\t @echo Generating MCBSP LLD Documentation\n"; + Pkg.makePrologue += "\t doxygen docs/Doxyfile\n"; + Pkg.makePrologue += "\t @echo MCBSP LLD Documentation Generated \n"; + Pkg.makePrologue += "\t @echo -------------------------------------------------------\n"; + + /* Add the documentation file to the package. */ + Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tifooter.htm"; + Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tiheader.htm"; + Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tilogo.gif"; + Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/titagline.gif"; + Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxygen"; + Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/MCBSP_LLD_SDS.pdf"; + Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/MCBSP_LLD_SoftwareManifest.pdf"; + Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/ReleaseNotes_MCBSP_LLD.pdf"; + + if (mcbspDriverInstallType == "SETUP") + { + /* Generate the ECLIPSE Plugin Generation */ + Pkg.makePrologue += "all: eclipse_plugin_generation\n"; + Pkg.makePrologue += "eclipse_plugin_generation:\n"; + Pkg.makePrologue += "\t @echo -------------------------------------------------------\n"; + Pkg.makePrologue += "\t @echo MCBSP LLD Eclipse Plugin Generation\n"; + Pkg.makePrologue += "\t xs xdc.tools.eclipsePluginGen -o . -x ./eclipseDocs/sample.xml -c ./eclipseDocs/toc_cdoc_sample.xml\n"; + Pkg.makePrologue += "\t @echo MCBSP LLD Eclipse Plugin Generated \n"; + Pkg.makePrologue += "\t @echo -------------------------------------------------------\n"; + } +} + diff --git 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ConfidentialFor Internal Use Only
DISCLAIMER:This report was created using Black Duck(TM) Protex software compliance management products and services. The results contained in the report reflect the user's analysis and decision making. Recipient of the results bears all of the risks relating to use of, or reliance upon, such results or any other content contained in this report. Black Duck Software makes no representation or warranty to any party regarding the contents of this report, its accuracy, completeness or correctness, and Black Duck Software hereby disclaims any and all warranties (both express and implied) with respect thereto.
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mpbu mcbsp_C6657 July 2012 Report

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July 31, 2012 03:42 PM

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Table Of Contents
 
Summary
Analysis Summary
Bill of Materials
File Name Patterns Flagged as Pending Id
Code Matches - Precision
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+Summary +
Name:mpbu mcbsp_C6657 July 2012
Project Creator:Jack Manbeck
License:[template] Basic Proprietary Commercial License
Description:
Number of Files:96
Files Pending Identification:3 (3.12%)
Files with Violations:6 (6.25%)
Server:blackduck01.dal.design.ti.com
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Analysis Summary +
Last Updated:July 31, 2012 03:39 PM
Scan Started:July 31, 2012 03:19 PM
Scan Finished:July 31, 2012 03:20 PM
Files analyzed:96 Files
Bytes analyzed:2.53 MiB (2,650,509 bytes)
Files skipped: 0 Files
Bytes skipped: 0 Bytes
Analysis Release Description:Product version 6.0.4 KB update 70, custom codeprints modified June 04, 2012 10:22 AM
Analyzed From Host:GTLA0850427.gt.design.ti.com
Analyzed By:a0850427 (j-manbeck2@ti.com)
Analyzed With OS:Windows XP
Analyzed With Locale:en-US
Analyzed With Options:File Matches -Yes
Snippet Matches -Yes
Java Import Statements -Yes
Java Package Statements -Yes
Binary Dependencies -Yes
String Searches -Yes
Allow wild cards (*) in string search queries -Yes
Allow regular expression search queries -No
Decompress Compressed Files -Yes
Expand Archive Files -Yes
Enable Multi-User File Comparison -No
Store non-precision matches -Yes
Enable Auto Identification -No
+
+


+ + + + +
+ Top + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Bill of Materials +
Approval StatusLicense ConflictComponentVersionHome PageComponent CommentLicenseUsageShip Status# Manual Code Match# Rapid ID Code Match# Manual Depends# Manual SearchUsed By
Pending ApprovalDeclared License Conflict and Component License ConflictDoxygenUnspecifiedhttp://www.stack.nl/~dimitri/doxygenGPL 2.0FileShip6000
N/AN/Ampbu mcbsp_C6657 July 2012Unspecified[template] Basic Proprietary Commercial LicenseOriginal CodeShip68000
Pending ApprovalNo Conflictsmsp430-Breathe-with-GraceUnspecifiedhttp://github.com/GWDeveloper/msp430-Breathe-with-Grace/UnspecifiedSnippetShip1000
+
+


+ + + + +
+ Top + +
+ + + + + + + + + + + + + + + + +
+File Name Patterns Flagged as Pending Id +
Full PathTypeFile/Folder Comment
This project does not have any file name patterns flagged as pending id.
+
+


+ + + + +
+ Top + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Code Matches - Precision +
FileSizeFile LineTotal LinesComponentVersionLicenseUsageStatus%Matched FileMatched File LineFile CommentComponent Comment
ti/drv/mcbsp/docs/doxygen/html/doxygen.css8077Doxygen1.5.0GPL 2.0FileIdentified by Generic Version100%doxygen-1.5.0.linux.bin.tar.gz/doxygen-1.5.0/html/doxygen.css
ti/drv/mcbsp/docs/doxygen/html/doxygen.png1281Doxygen1.3.9GPL 2.0FileIdentified by Generic Version100%doxygen-1.3.9.linux.bin.tar.gz/doxygen-1.3.9/examples/afterdoc/html/doxygen.png
ti/drv/mcbsp/docs/doxygen/html/tab_b.gif35Doxygen1.4.5GPL 2.0FileIdentified by Generic Version100%doxygen-1.4.5.linux.bin.tar.gz/doxygen-1.4.5/html/tab_b.gif
ti/drv/mcbsp/docs/doxygen/html/tab_l.gif706Doxygen1.4.5GPL 2.0FileIdentified by Generic Version100%doxygen-1.4.5.linux.bin.tar.gz/doxygen-1.4.5/html/tab_l.gif
ti/drv/mcbsp/docs/doxygen/html/tab_r.gif2585Doxygen1.4.5GPL 2.0FileIdentified by Generic Version100%doxygen-1.4.5.linux.bin.tar.gz/doxygen-1.4.5/html/tab_r.gif
ti/drv/mcbsp/docs/doxygen/html/tabs.css1758Doxygen1.4.5GPL 2.0FileIdentified by Generic Version100%doxygen-1.4.5.linux.bin.tar.gz/doxygen-1.4.5/examples/tag/html/tabs.css
ti/drv/mcbsp/docs/tifooter.htm98EonosMIT License V2FilePrecision Match100%Eonos-master-20101115.tgz/Martix-Eonos-cedf664/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98OpenEmbeddedtesting_2010-09-07MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-09-07.tar.gz/openembedded-git-tag-testing_2010-09-07/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98OpenEmbeddedtesting_2010-08-30MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-08-30.tar.gz/openembedded-git-tag-testing_2010-08-30/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98OpenEmbeddedtesting_2010-09-13MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-09-13.tar.gz/openembedded-git-tag-testing_2010-09-13/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98OpenEmbeddedtesting_2010-09-20MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-09-20.tar.gz/openembedded-git-tag-testing_2010-09-20/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98OpenEmbeddedtesting_2010-08-23MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-08-23.tar.gz/openembedded-git-tag-testing_2010-08-23/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98OpenEmbedded2011.3MIT License V2FilePrecision Match100%release-2011.03.tar.gz/release-2011.03/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98OpenEmbedded2010.12MIT License V2FilePrecision Match100%release-2010.12.tar.gz/release-2010.12/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98openembedded-androidMIT License V2FilePrecision Match100%openembedded-android-android-20101206.tgz/anguslees-openembedded-android-a608b5f/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98openembedded-rascalMIT License V2FilePrecision Match100%openembedded-rascal-master-20101212.tgz/rascalmicro-openembedded-rascal-effc276/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tifooter.htm98overo-oeMIT License V2FilePrecision Match100%overo-oe-min_image-20110417.tgz/yyli-overo-oe-b470aae/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tifooter.htm
ti/drv/mcbsp/docs/tilogo.gif1137EonosMIT License V2FilePrecision Match100%Eonos-master-20101115.tgz/Martix-Eonos-cedf664/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
ti/drv/mcbsp/docs/tilogo.gif1137OpenEmbeddedtesting_2010-09-20MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-09-20.tar.gz/openembedded-git-tag-testing_2010-09-20/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
ti/drv/mcbsp/docs/tilogo.gif1137OpenEmbeddedtesting_2010-09-13MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-09-13.tar.gz/openembedded-git-tag-testing_2010-09-13/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
ti/drv/mcbsp/docs/tilogo.gif1137OpenEmbeddedtesting_2010-09-07MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-09-07.tar.gz/openembedded-git-tag-testing_2010-09-07/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
ti/drv/mcbsp/docs/tilogo.gif1137OpenEmbeddedtesting_2010-08-23MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-08-23.tar.gz/openembedded-git-tag-testing_2010-08-23/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
ti/drv/mcbsp/docs/tilogo.gif1137OpenEmbeddedtesting_2010-08-30MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-08-30.tar.gz/openembedded-git-tag-testing_2010-08-30/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
ti/drv/mcbsp/docs/tilogo.gif1137OpenEmbedded2011.3MIT License V2FilePrecision Match100%release-2011.03.tar.gz/release-2011.03/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
ti/drv/mcbsp/docs/tilogo.gif1137OpenEmbedded2010.12MIT License V2FilePrecision Match100%release-2010.12.tar.gz/release-2010.12/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
ti/drv/mcbsp/docs/tilogo.gif1137openembedded-androidMIT License V2FilePrecision Match100%openembedded-android-android-20101206.tgz/anguslees-openembedded-android-a608b5f/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
ti/drv/mcbsp/docs/tilogo.gif1137openembedded-rascalMIT License V2FilePrecision Match100%openembedded-rascal-master-20101212.tgz/rascalmicro-openembedded-rascal-effc276/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/tilogo.gif
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ti/drv/mcbsp/docs/titagline.gif653OpenEmbeddedtesting_2010-09-13MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-09-13.tar.gz/openembedded-git-tag-testing_2010-09-13/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/titagline.gif
ti/drv/mcbsp/docs/titagline.gif653OpenEmbeddedtesting_2010-08-23MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-08-23.tar.gz/openembedded-git-tag-testing_2010-08-23/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/titagline.gif
ti/drv/mcbsp/docs/titagline.gif653OpenEmbeddedtesting_2010-09-07MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-09-07.tar.gz/openembedded-git-tag-testing_2010-09-07/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/titagline.gif
ti/drv/mcbsp/docs/titagline.gif653OpenEmbeddedtesting_2010-09-20MIT License V2FilePrecision Match100%openembedded-git-tag-testing_2010-09-20.tar.gz/openembedded-git-tag-testing_2010-09-20/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/titagline.gif
ti/drv/mcbsp/docs/titagline.gif653OpenEmbedded2011.3MIT License V2FilePrecision Match100%release-2011.03.tar.gz/release-2011.03/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/titagline.gif
ti/drv/mcbsp/docs/titagline.gif653OpenEmbedded2010.12MIT License V2FilePrecision Match100%release-2010.12.tar.gz/release-2010.12/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/titagline.gif
ti/drv/mcbsp/docs/titagline.gif653openembedded-androidMIT License V2FilePrecision Match100%openembedded-android-android-20101206.tgz/anguslees-openembedded-android-a608b5f/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/titagline.gif
ti/drv/mcbsp/docs/titagline.gif653openembedded-rascalMIT License V2FilePrecision Match100%openembedded-rascal-master-20101212.tgz/rascalmicro-openembedded-rascal-effc276/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/titagline.gif
ti/drv/mcbsp/docs/titagline.gif653overo-oeMIT License V2FilePrecision Match100%overo-oe-min_image-20110417.tgz/yyli-overo-oe-b470aae/recipes/ti/ti-dmai/doxygen_templates.tar.gz.---/doxygen_templates/titagline.gif
ti/drv/mcbsp/package/ti_drv_mcbsp.java11018161msp430-Breathe-with-GraceUnspecifiedSnippetIdentified41%msp430-Breathe-with-Grace-master-20110401.tgz/GWDeveloper-msp430-Breathe-with-Grace-1d8bd9a/Debug/configPkg/package/configPkg.java1TI Code matching TI code
+
+ + + + + + + + + +
ConfidentialFor Internal Use Only
DISCLAIMER:This report was created using Black Duck(TM) Protex software compliance management products and services. The results contained in the report reflect the user's analysis and decision making. Recipient of the results bears all of the risks relating to use of, or reliance upon, such results or any other content contained in this report. Black Duck Software makes no representation or warranty to any party regarding the contents of this report, its accuracy, completeness or correctness, and Black Duck Software hereby disclaims any and all warranties (both express and implied) with respect thereto.
+ + diff --git a/packages/ti/drv/mcbsp/docs/tifooter.htm b/packages/ti/drv/mcbsp/docs/tifooter.htm new file mode 100644 index 000000000..4bdf9c9f5 --- /dev/null +++ b/packages/ti/drv/mcbsp/docs/tifooter.htm @@ -0,0 +1,4 @@ +
+Copyright $year, Texas Instruments Incorporated + + diff --git a/packages/ti/drv/mcbsp/docs/tiheader.htm b/packages/ti/drv/mcbsp/docs/tiheader.htm new file mode 100644 index 000000000..3c61efe15 --- /dev/null +++ b/packages/ti/drv/mcbsp/docs/tiheader.htm @@ -0,0 +1,12 @@ + + +$title + + + + + + + + +
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+ +/************************************************************************** + * FUNCTION NAME : modBuild + ************************************************************************** + * DESCRIPTION : + * The function is used to add all the source files in the example + * directory into the package. + **************************************************************************/ +function modBuild() +{ + /* Add all the .c files to the release package. */ + var exampleFiles = libUtility.listAllFiles (".c", "example", true); + for (var k = 0 ; k < exampleFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k]; + + /* Add all the .h files to the release package. */ + var exampleFiles = libUtility.listAllFiles (".h", "example", true); + for (var k = 0 ; k < exampleFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k]; + + /* Add all the .cmd files to the release package. */ + var exampleFiles = libUtility.listAllFiles (".cmd", "example", true); + for (var k = 0 ; k < exampleFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k]; + + /* Add all the .cfg files to the release package. */ + var exampleFiles = libUtility.listAllFiles (".cfg", "example", true); + for (var k = 0 ; k < exampleFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k]; + + /* Add all the make files to the release package. */ + var exampleFiles = libUtility.listAllFiles ("makefile", "example", true); + for (var k = 0 ; k < exampleFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k]; + + /* Add the .txt to the package */ + var exampleFiles = libUtility.listAllFiles (".txt", "example", true); + for (var k = 0 ; k < exampleFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k]; + + /* Add all the .mk files to the release package. */ + var mkFiles = libUtility.listAllFiles (".mk", "example", true); + for (var k = 0 ; k < mkFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k]; +} diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/MCBSP_evmc6657_C66DigLpbkExampleProject.txt b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/MCBSP_evmc6657_C66DigLpbkExampleProject.txt new file mode 100644 index 000000000..1c429a481 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/MCBSP_evmc6657_C66DigLpbkExampleProject.txt @@ -0,0 +1,7 @@ +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/device/c6657/src/device_mcbsp_loopback.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c" + +-ccs.setCompilerOptions "-DSOC_C6657 -DMCBSP_DEBUG_TEMP -g --diag_warning=225 -I${PDK_INSTALL_PATH} -I${BIOS_INSTALL_PATH}/packages -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/include -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/include -I${PDK_INSTALL_PATH}/ti/drv/mcbsp -I${PDK_INSTALL_PATH}/ti/board" -rtsc.enableRtsc diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/bios6_edma3_drv_sample.h b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/bios6_edma3_drv_sample.h new file mode 100644 index 000000000..5fad8a74a --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/bios6_edma3_drv_sample.h @@ -0,0 +1,186 @@ +/* + * bios6_edma3_drv_sample.h + * + * Header file for the sample application for the EDMA3 Driver. + * + * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef _BIOS6_EDMA3_DRV_SAMPLE_H_ +#define _BIOS6_EDMA3_DRV_SAMPLE_H_ + +#include +#include + +/* Include EDMA3 Driver */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Cache line size on the underlying SoC. It needs to be modified + * for different cache line sizes, if the Cache is Enabled. + */ +#define EDMA3_CACHE_LINE_SIZE_IN_BYTES (128u) + +/* Error returned in case of buffers are not aligned on the cache boundary */ +#define EDMA3_NON_ALIGNED_BUFFERS_ERROR (-1) + +/* Error returned in case of data mismatch */ +#define EDMA3_DATA_MISMATCH_ERROR (-2) + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 Driver for the given EDMA3 controller + * and opens a EDMA3 driver instance. It internally calls EDMA3_DRV_create() and + * EDMA3_DRV_open(), in that order. + * + * It also registers interrupt handlers for various EDMA3 interrupts like + * transfer completion or error interrupts. + * + * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0) + * \param errorCode [IN/OUT] Error code while opening DRV instance + * \return EDMA3_DRV_Handle: If successfully opened, the API will return the + * associated driver's instance handle. + */ +EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode); + +/** + * \brief EDMA3 De-initialization + * + * This function de-initializes the EDMA3 Driver for the given EDMA3 controller + * and closes the previously opened EDMA3 driver instance. It internally calls + * EDMA3_DRV_close and EDMA3_DRV_delete(), in that order. + * + * It also un-registers the previously registered interrupt handlers for various + * EDMA3 interrupts. + * + * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0) + * \param hEdma [IN] EDMA3 Driver handle, returned while using + * edma3init(). + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma); + + +/** + * \brief EDMA3 Cache Invalidate + * + * This function invalidates the D cache. + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * \brief EDMA3 Cache Flush + * + * This function flushes (cleans) the Cache + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 driver/RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to receive the handle to just created + * semaphore. + * \return EDMA3_DRV_SOK if successful, else a suitable error code. + */ +EDMA3_DRV_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem); + + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_DRV_SOK if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _BIOS6_EDMA3_DRV_SAMPLE_H_ */ + diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/config.bld b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/config.bld new file mode 100644 index 000000000..cb4905e5a --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/config.bld @@ -0,0 +1,82 @@ +/* + * + * $Source: /cvsstl/ti/pa/f/s19/config.bld,v $ + * $Revision: 1.6 $ + * + * XDC/BIOS configuration file for I12 Topo/Feature Set + * + * Copyright 2008, Texas Instruments, Inc. All rights reserved. + * + * $Log: config.bld,v $ + * Revision 1.6 2009/06/10 07:51:13 mkamat + * MID 2487 Replace references to PA17 with PA + * + * Revision 1.5 2009/03/02 04:36:58 uparikh + * Add segment SDRAM_LINK_SHARED for dhared LINK memory + * + * Revision 1.4 2009/02/18 14:29:12 uparikh + * Partition SDRAM and re-order memory segments in ascending order + * + * Revision 1.3 2009/02/14 09:05:55 uparikh + * Update IRAM and SDRAM base / len + * + * Revision 1.2 2009/01/28 12:37:59 mkamat + * Made cache 64k and moved o/p buffer to L3 - MID 2144 + * + * Revision 1.1 2008/10/21 04:45:09 mkamat + * Code cleanup in s19 area - MID 1923 + * + * Revision 1.6 2008/10/13 05:22:54 uparikh + * Define section for uboot + * + * Revision 1.5 2008/09/29 11:20:53 uparikh + * Increase size of SDRAM for pa.out to build + * + * Revision 1.4 2008/09/09 23:35:52 lester + * (MID 1820) Revised to use deviceName: 'TMS320DA830', + * instead of deviceName: 'Primus' (deprecated). + * + * Revision 1.3 2008/09/05 17:18:42 martin + * Renumber array elements. Element 1 was missing in last commit + * + * Revision 1.2 2008/09/05 16:00:43 martin + * Move DSP image to upper SDRAM to cooperate with Linux images. + * + * Revision 1.1 2008/08/20 09:54:35 lester + * (MID 1820) Generated via (from latest this date): + * [/cygdrive/t/pa/f/s17/pai1] delog -f"t:/pa/f/s19/i12" .... + * + */ + +/* ......................................................................... */ + +var memory = []; + + +memory[0] = ["IRAM", + { + name : "IRAM", + base : 0x10800000, + len : 0x00080000, + space : "code/data" + }]; + +memory[1] = ["L3RAM", + { + name : "DDR3", + base : 0x80000000, + len : 0x10000000, + space : "data" + }]; + + +Build.platformTable['ti.platforms.generic:plat'] = +{ +clockRate: 600, +catalogName: 'ti.catalog.c6000', +deviceName: 'TMS320TCI6616', +regs: {l1DMode: "32k"}, +regs: {l1PMode: "32k"}, +regs: {l2Mode: "64k"}, +customMemoryMap: memory +}; diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.c b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.c new file mode 100644 index 000000000..22a7fa967 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.c @@ -0,0 +1,993 @@ +/* + * mcbspMasterDigLpbk.c + * + * This file contains the test / demo code to demonstrate the McBSP driver + * master functionality using Digital Loopback setup. The file configures + * the EVM in master mode. + * + * Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/* ========================================================================== */ +/* INCLUDE FILES */ +/* ========================================================================== */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Include EDMA3 Driver */ +#include + +/* CSL Chip Functional Layer */ +//#include + +/* CSL Cache Functional Layer */ +//#include + +/* CSL CPINTC Include Files. */ +//#include + +/* MCBSP Driver Include File. */ +#include +#include + +/* PlatformLib Include File */ +//#include + + +extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[]; +extern EDMA3_RM_InstanceInitConfig sampleInstInitConfig[2][8]; +/* ========================================================================== */ +/* EXTERNAL FUNCTIONS */ +/* ========================================================================== */ + +extern EDMA3_DRV_Handle edma3init(unsigned int edma3Id, EDMA3_DRV_Result *); + +extern void McbspDevice_init(void); + +extern int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize); + +extern void McbspXmtInterrupt_init(void *mcbspTxChan); +extern void McbspRcvInterrupt_init(void *mcbspRxChan); + +extern Board_STATUS Board_init(Board_initCfg); + +/* FPGA Configuration Misc-1 Register offset */ +#define MCBSP_FPGA_MISC_REG_OFFSET (0x0C) + +/* ========================================================================== */ +/* MACRO DEFINTIONS */ +/* ========================================================================== */ + +#define NUM_BUFS 2 /* Max of buffers used in each direction */ +#define FRAMESIZE 40 /* e.g 5 ms 8 KHz samples */ +#define NUM_OF_ENABLED_CHANNELS 8 /* Number of slots to be used */ +#define NUM_OF_MAX_CHANNELS 128 /* Maximum number of time slots available based on clock settings */ +#define BUFSIZE (NUM_OF_ENABLED_CHANNELS * FRAMESIZE) /* Total buffer size per frame */ + +/* Defines the core number responsible for system initialization. */ +#define CORE_SYS_INIT 0 +/* Number of iterations to execute test: Only applicable to INTERNAL CLOCK Loopback test */ +#define NUM_OF_ITERATIONS 10 + +/* Number of MCBSP Frame structures used for submit channel */ +#define NUM_OF_MCBSP_FRAMES 2 + +/* Number of buffers initially submitted to Mcbsp lld: Only applicable to + External clock test ; Note: This should be set to 2*/ +#define INIT_SUBMIT_Q_CNT 2 + +/*============================================================================*/ +/* GLOBAL VARIABLES */ +/*============================================================================*/ + +/* Shared Memory Variable to ensure synchronizing MCBSP initialization + * with all the other cores. */ +/* Created an array to pad the cache line with MCBSP_CACHE_LENGTH size */ +#pragma DATA_ALIGN (isMCBSPInitialized, MCBSP_MAX_CACHE_ALIGN) +#pragma DATA_SECTION (isMCBSPInitialized, ".mcbspSharedMem"); +volatile Uint32 isMCBSPInitialized[(MCBSP_CACHE_LENGTH / sizeof(Uint32))] = { 0 }; + +/* Handle to the EDMA driver instance */ +#pragma DATA_ALIGN (hEdma, MCBSP_MAX_CACHE_ALIGN) +EDMA3_DRV_Handle hEdma[(MCBSP_CACHE_LENGTH / sizeof(EDMA3_DRV_Handle))] = { NULL }; + +/* Handle to MCBSP driver instance */ +typedef void* Mcbsp_DevHandle; +Mcbsp_DevHandle hMcbspDev; + +/* Handle to MCBSP driver channel instance */ +typedef void* Mcbsp_ChanHandle; +Mcbsp_ChanHandle hMcbspTxChan; +Mcbsp_ChanHandle hMcbspRxChan; + +/* Core Number Identifier */ +UInt32 coreNum = 0xFFFF; + +/* Array to hold the pointer to the allocated buffers */ +void* bufRx[NUM_BUFS]; +void* bufTx[NUM_BUFS]; + +#ifdef MCBSP_LOOP_PING_PONG +/* Ping pong buffers used to submit to Mcbsp lld, which will be used in a loop */ +void* bufRxPingPong[INIT_SUBMIT_Q_CNT]; +void* bufTxPingPong[INIT_SUBMIT_Q_CNT]; +#endif +/* Global Error call back function prototype */ +void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3); + +/* Variables to indicate status of EDMA TX and RX requests */ +volatile uint32_t edmaTxDone = 0; +volatile uint32_t edmaRxDone = 0; +/* Global variables to track number of buffers submitted, number of iterations, error counts etc */ +int rxSubmitCount=0, txSubmitCount=0; +uint32_t num_iterations=0; +uint32_t num_rx_Call_backs=0, num_tx_Call_backs=0, dummy_call_backs=0; +uint32_t rxunderflowcnt=0, txunderflowcnt=0; +uint32_t errBuffCount=0; +/* Debug variables */ +volatile int debugVar=1; /* This can be used to maintain a while loop, If set to 0 will exit loop */ +volatile int debugCommand=1; /* This can be used to set to value below to send command to restart channel */ + +#define DEBUG_COMMAND_RESTART_CHANNELS 1 +/** + * \brief Mcbsp Sample rate generator default parameters. + * + */ +Mcbsp_srgConfig mcbspSrgCfg = +{ + FALSE, /* No gsync to be used as input is not CLKS */ + Mcbsp_ClkSPol_RISING_EDGE, /* Dont care as input clock is not clks */ + Mcbsp_SrgClk_CLKCPU, /* McBSP internal clock to be used */ + //166666667, /* Mcbsp internal clock frequency(PLL-SYSCLK6) */ + 333333333, //sys_oscclk or cpu_clk/3 + 0 /* frame sync pulse width (val+1) is used */ +}; + +/** + * \brief Mcbsp device creation default parameters. + * + */ +const Mcbsp_Params Mcbsp_PARAMS = +{ + Mcbsp_DevMode_McBSP, /* Use the device as MCBSP */ + Mcbsp_OpMode_DMAINTERRUPT, /* Use DMA mode of operation */ + TRUE, /* cache coherency taken care of by driver */ + Mcbsp_EmuMode_FREE, /* Emulation mode free is to be enabled */ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_Loopback_DISABLE, /* Loop back mode disabled */ +#else + Mcbsp_Loopback_ENABLE, /* Loop back mode enabled */ +#endif + &mcbspSrgCfg, /* sample rate generator configuration */ + NULL, /* TX pending buffer queue from application */ + NULL, /* TX floating buffer queue in DMA */ + NULL, /* RX pending buffer queue from application */ + NULL /* RX floating buffer queue in DMA */ +}; + +#pragma DATA_ALIGN(loopTxJob, MCBSP_MAX_CACHE_ALIGN) +static Int32 loopTxJob[16] = { + /* Filling with Mu law silence pattern : Can be any user defined pattern */ + 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, + 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f +}; +#pragma DATA_ALIGN(loopRxJob, MCBSP_MAX_CACHE_ALIGN) +static Int32 loopRxJob[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/**< settings to configure the TX or RX hardware sections */ +Mcbsp_DataConfig mcbspChanConfigTx = +{ + Mcbsp_Phase_SINGLE, + Mcbsp_WordLength_8, + Mcbsp_WordLength_8, /* Dont care for single phase*/ + NUM_OF_MAX_CHANNELS, + NUM_OF_MAX_CHANNELS, // Only used with dual phase + Mcbsp_FrmSync_DETECT, +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_DataDelay_0_BIT, +#else + Mcbsp_DataDelay_1_BIT, +#endif + Mcbsp_Compand_OFF_MSB_FIRST, + Mcbsp_BitReversal_DISABLE, + Mcbsp_IntMode_ON_SYNCERR, + Mcbsp_RxJust_RZF, /* Dont care for TX */ + Mcbsp_DxEna_OFF +}; + +/**< settings to configure the TX or RX hardware sections */ +Mcbsp_DataConfig mcbspChanConfigRx = +{ + Mcbsp_Phase_SINGLE, + Mcbsp_WordLength_8, + Mcbsp_WordLength_8, /* Dont care for single phase*/ + NUM_OF_MAX_CHANNELS, + NUM_OF_MAX_CHANNELS, // Only used with dual phase + Mcbsp_FrmSync_DETECT, +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_DataDelay_0_BIT, +#else + Mcbsp_DataDelay_1_BIT, +#endif + Mcbsp_Compand_OFF_MSB_FIRST, + Mcbsp_BitReversal_DISABLE, + Mcbsp_IntMode_ON_SYNCERR, + Mcbsp_RxJust_RZF, /* Dont care for TX */ + Mcbsp_DxEna_OFF +}; +/**< clock setup for the TX section */ +Mcbsp_ClkSetup mcbspClkConfigTx = +{ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_FsClkMode_EXTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_EXTERNAL, +#else + Mcbsp_FsClkMode_INTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_INTERNAL, +#endif + Mcbsp_FsPol_ACTIVE_HIGH, + Mcbsp_ClkPol_RISING_EDGE +}; + +/**< clock setup for the RX section */ +Mcbsp_ClkSetup mcbspClkConfigRx = +{ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_FsClkMode_EXTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_EXTERNAL, +#else + Mcbsp_FsClkMode_INTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_INTERNAL, +#endif + Mcbsp_FsPol_ACTIVE_HIGH, + Mcbsp_ClkPol_FALLING_EDGE +}; + +/**< Multi channel setup */ +Mcbsp_McrSetup mcbspMultiChanCtrl = +{ + Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED, + Mcbsp_PartitionMode_CHAN_0_15, + Mcbsp_PartitionMode_CHAN_16_31, + Mcbsp_PartitionMode_2 +}; + + +Mcbsp_ChanParams mcbspChanparamTx = +{ + Mcbsp_WordLength_8, /* wordlength configured */ + &loopTxJob[0], /* loop job buffer internal */ + 8, /* user loopjob length */ + mcbsp_GblErrCallback, /* global error callback */ + NULL, /* edma Handle */ + 1, /* EDMA event queue */ + 8, /* hwi number */ + Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED, + TRUE, /* FIFO mode enabled */ + &mcbspChanConfigTx, /* channel configuration */ + &mcbspClkConfigTx, /* clock configuration */ + &mcbspMultiChanCtrl, /* multi channel control */ + 0x7531, /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */ + 0x00, + 0x00, + 0x00, + NUM_OF_ENABLED_CHANNELS /* Total number of channels enabled*/ +}; + +Mcbsp_ChanParams mcbspChanparamRx = +{ + Mcbsp_WordLength_8, /* wordlength configured */ + &loopRxJob[0], /* loop job buffer internal */ + 8, /* user loopjob length */ + mcbsp_GblErrCallback, /* global error callback */ + NULL, /* edma Handle */ + 1, /* EDMA event queue */ + 8, /* hwi number */ + Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED, + TRUE, /* FIFO mode enabled */ + &mcbspChanConfigRx, /* channel configuration */ + &mcbspClkConfigRx, /* clock configuration */ + &mcbspMultiChanCtrl, /* multi channel control */ + 0x7531, /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */ + 0x00, + 0x00, + 0x00, + NUM_OF_ENABLED_CHANNELS /* Total number of channels enabled*/ +}; + + +/* ========================================================================== */ +/* FUNCTION DEFINITIONS */ +/* ========================================================================== */ + +/* + * This is the application's callback function. The driver will + * call this function whenever an EDMA I/O operation is over. + * + */ +void mcbspAppCallback(void* arg, Mcbsp_IOBuf *ioBuf) +{ + int32_t mode; + int32_t *pmode = (int32_t *)arg; + + mode = *pmode; + if (mode == MCBSP_MODE_OUTPUT) + { + if(ioBuf) { + num_tx_Call_backs++; + edmaTxDone = 1; + }else + txunderflowcnt++; + } + else if (mode == MCBSP_MODE_INPUT) + { + if(ioBuf) { + num_rx_Call_backs++; + edmaRxDone = 1; + }else + rxunderflowcnt++; + }else + dummy_call_backs++; + return; +} + +/* + * This is the application's Global error callback function + */ +void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3) +{ + MCBSP_log ("Debug(Core %d): ERROR callback called SPCR: %x", coreNum, spcr_read); +} + +/* + * \brief This function demostrates the use of Mcbsp using digital loopback + * communication setup. + * + * \param None + * + * \return None + */ +void mcbspDigLpbkApp(UArg arg0, UArg arg1) +{ + /**< Mcbsp device params */ + Mcbsp_Params mcbspParams; + + /**< Queue to hold the pending packets received from the application */ + Queue_Struct txQueuePendingList, rxQueuePendingList; + /**< Queue to manage floating packets in DMA */ + Queue_Struct txQueueFloatingList, rxQueueFloatingList; + + uint32_t count = 0, tempCount = 0; + int32_t status = 0, retval = 0; + int32_t txChanMode = MCBSP_MODE_OUTPUT; + int32_t rxChanMode = MCBSP_MODE_INPUT; + uint32_t mcbspTxDone = 0, mcbspRxDone = 0; + Mcbsp_IOBuf txFrame[NUM_OF_MCBSP_FRAMES], rxFrame[NUM_OF_MCBSP_FRAMES]; + int txFrameIndex=0, rxFrameIndex=0; + int init_count=0; +#ifdef MCBSP_LOOP_PING_PONG + int pingPongIndex=0; +#endif + + /* Initialize the OSAL */ + if (Osal_dataBufferInitMemory(BUFSIZE) < 0) + { + MCBSP_log ("Debug(Core %d): Error: Unable to initialize the OSAL. \n", coreNum); + return; + } + + /* update EDMA3 handle to channel parameters */ + mcbspChanparamTx.edmaHandle = hEdma[0]; + mcbspChanparamRx.edmaHandle = hEdma[0]; + + /* create the pending and floating queue for the TX channel */ + Queue_construct(&txQueuePendingList, NULL); + Queue_construct(&txQueueFloatingList, NULL); + + /* create the pending and floating queue for the RX channel */ + Queue_construct(&rxQueuePendingList, NULL); + Queue_construct(&rxQueueFloatingList, NULL); + + + mcbspParams = Mcbsp_PARAMS; + mcbspParams.txQPendingList = &txQueuePendingList; + mcbspParams.txQFloatingList = &txQueueFloatingList; + mcbspParams.rxQPendingList = &rxQueuePendingList; + mcbspParams.rxQFloatingList = &rxQueueFloatingList; + + + /* Bind the driver instance with device instance */ + status = mcbspBindDev(&hMcbspDev, coreNum, &mcbspParams); + + if (status != MCBSP_STATUS_COMPLETED) + { + MCBSP_log ("Debug(Core %d): MCBSP LLD Bind Device Failed\n", coreNum); + return; + } + + /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */ + if(mcbspChanparamRx.userLoopJobBuffer) + mcbspChanparamRx.userLoopJobBuffer = (void *)Mcbsp_osalLocal2Global(mcbspChanparamRx.userLoopJobBuffer); + + /* Create a RX channel for receiving */ + status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum); + return; + } + + /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */ + if(mcbspChanparamTx.userLoopJobBuffer) + mcbspChanparamTx.userLoopJobBuffer = Mcbsp_osalLocal2Global(mcbspChanparamTx.userLoopJobBuffer); + + /* Create a TX channel for the transmission */ + status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum); + return; + } + + /* Register mcbsp interrupts */ + //McbspRcvInterrupt_init(hMcbspRxChan); + //McbspXmtInterrupt_init(hMcbspTxChan); + + /* create the buffers required for the TX and RX operations */ + for (count = 0; count < (NUM_BUFS); count++) + { + bufTx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + bufRx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + + if (bufTx[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Tx Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + if (bufRx[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Rx Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* create the ping pong buffers required for the TX and RX operations */ + for (count = 0; count < (NUM_BUFS); count++) + { + bufRxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + bufTxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + + if (bufTxPingPong[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Tx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + if (bufRxPingPong[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Rx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + } +#endif + /* Fill the buffers with known data and transmit the same and + check if the same pattern is received */ + for (count = 0; count < (NUM_BUFS); count++) + { + memset((uint8_t *)bufTx[count], 0, BUFSIZE); + for (tempCount = 0; tempCount < BUFSIZE; tempCount++) + { + ((uint8_t *)bufTx[count])[tempCount] = (tempCount % 0x100); + } + } + MCBSP_log ("Debug(Core %d): If required to restart set debugCommand variable to %d\n", coreNum, DEBUG_COMMAND_RESTART_CHANNELS); + +restart_mcbsp_point: + txFrameIndex=0; + rxFrameIndex=0; + init_count=0; +#ifdef MCBSP_EXTERNAL_CLOCK + /* Initial loading of ping ping buffers */ + for(init_count =0 ; init_count < INIT_SUBMIT_Q_CNT; init_count++) + { +#ifdef MCBSP_LOOP_PING_PONG + memset((uint8_t *)bufRxPingPong[init_count], 0, BUFSIZE); + + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRxPingPong[init_count]; +#else + memset((uint8_t *)bufRx[init_count], 0, BUFSIZE); + + + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRx[init_count]; +#endif + + rxFrame[rxFrameIndex].size = BUFSIZE; + rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan; + rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED; + rxFrame[rxFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, init_count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, init_count); +#endif + } + rxFrameIndex++; + rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex; + + rxSubmitCount++; + + /* TX frame processing */ + txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE; +#ifdef MCBSP_LOOP_PING_PONG + txFrame[txFrameIndex].addr = (void*)bufTxPingPong[init_count]; +#else + txFrame[txFrameIndex].addr = (void*)bufTx[init_count]; +#endif + txFrame[txFrameIndex].size = BUFSIZE; + txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan; + txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED; + txFrame[txFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: TX buffer #%d submission FAILED\n", coreNum, init_count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): TX buffer #%d submission is submitted to MCBSP driver\n", coreNum, init_count); +#endif + } + txFrameIndex++; + txFrameIndex = (txFrameIndex >=(NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex; + + txSubmitCount++; + } + + /* Wait for TX and RX processing to complete */ + while (1) + { + if (edmaTxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Iteration-%d frames are transmitted to TX path\n", coreNum, count); +#endif + edmaTxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 1; + } + if (edmaRxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Iteration-%d frames are received from RX path\n", coreNum, count); +#endif + edmaRxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 1; + } + if ((mcbspTxDone == 1) && (mcbspRxDone == 1)) + { + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + break; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* Change ping Pong Index */ + init_count=0; +#endif +#endif /* MCBSP_EXTERNAL_CLOCK */ + + /* Start main loop to iterate through frames */ + while(debugVar) + { + /* submit frames to the driver */ + for (count = init_count; count < NUM_BUFS; count++) + { +#ifdef MCBSP_EXTERNAL_CLOCK +/* With External clock the data coming from the RX side is copied to loop back to the Tx side */ + memcpy((uint8_t *)bufTx[count], (uint8_t *)bufRx[count], BUFSIZE); +#endif +#ifdef MCBSP_LOOP_PING_PONG + memset((uint8_t *)bufRxPingPong[pingPongIndex], 0, BUFSIZE); +#else + memset((uint8_t *)bufRx[count], 0, BUFSIZE); + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)getGlobalAddr(bufRx[count]); + rxFrame[rxFrameIndex].size = BUFSIZE; + rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan; + rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED; + rxFrame[rxFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, count); +#endif + } + rxFrameIndex++; + rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex; +#endif + rxSubmitCount++; +#ifdef MCBSP_LOOP_PING_PONG + /* Copy buffer from buffer to ping pong buffer*/ + memcpy((uint8_t *)bufTxPingPong[pingPongIndex], (uint8_t *)bufTx[count],BUFSIZE); +#else + /* TX frame processing */ + txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE; + txFrame[txFrameIndex].addr = (void*)getGlobalAddr(bufTx[count]); + txFrame[txFrameIndex].size = BUFSIZE; + txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan; + txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED; + txFrame[txFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: TX buffer #%d submission FAILED\n", coreNum, count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): TX buffer #%d is submitted to MCBSP driver\n", coreNum, count); +#endif + } + txFrameIndex++; + txFrameIndex = (txFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex; +#endif + txSubmitCount++; + + /* Wait for TX and RX processing to complete */ + while (1) + { + if (edmaTxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Buffer #-%d is transmitted to TX path\n", coreNum, count); +#endif + edmaTxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 1; + } + if (edmaRxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Buffer #-%d is received from RX path\n", coreNum, count); +#endif + edmaRxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 1; + } + if ((mcbspTxDone == 1) && (mcbspRxDone == 1)) + { + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + break; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* Change ping Pong Index */ + pingPongIndex=(pingPongIndex)?0:1; + + /* Copy buffer from buffer to other buffer*/ + memcpy((void*)bufRx[count], (uint8_t *)bufRxPingPong[pingPongIndex],BUFSIZE); +#endif + /* compare buffer contents */ + for (tempCount = 0; tempCount < BUFSIZE; tempCount++) + { + if (((char *)bufTx[count])[tempCount] != ((char *)bufRx[count])[tempCount]) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log("Debug(Core %d): Error: TX and RX frame data DOES NOT match in Buffer #-%d\n", + coreNum, count); + MCBSP_log("Debug(Core %d): Error: Buffer index = %d, Tx data = %d, Rx data = %d\n", coreNum, + tempCount, ((char *)bufTx[count])[tempCount], ((char *)bufRx[count])[tempCount]); +#endif + errBuffCount++; + break; + } + } + if (tempCount >= BUFSIZE) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log("Debug(Core %d): TX and RX frames data match in iteration-%d !!!\n", coreNum, count); +#endif + } + } + init_count=0; + num_iterations++; +#ifndef MCBSP_EXTERNAL_CLOCK + if(num_iterations >= NUM_OF_ITERATIONS) + break; +#endif + switch(debugCommand) + { + case DEBUG_COMMAND_RESTART_CHANNELS: + debugCommand=0; + /* Close channel and reopen */ + /* Delete RX channel */ + status = mcbspDeleteChan(hMcbspRxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum); + return; + } + + /* Delete TX channel*/ + status = mcbspDeleteChan(hMcbspTxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum); + return; + } + /* Create a RX channel for receiving */ + status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum); + return; + } + + /* Create a TX channel for the transmission */ + status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum); + return; + } + edmaTxDone = 0; /* Reset for next iteration */ + edmaRxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + goto restart_mcbsp_point; + + default: + debugCommand=0; + break; + + } + + } + + if ((errBuffCount == 0 ) & (retval ==0)) + { + MCBSP_log("Debug(Core %d): MCBSP Digital Loopback Application completed successfully : "\ + "Num iterations %d Num buffers per iteration %d!!!\n", + coreNum, num_iterations, NUM_BUFS); + MCBSP_log("\n All tests have passed \n"); + } + else + { + MCBSP_log("Debug(Core %d): MCBSP Digital Loopback application FAILED : "\ + "Num iterations %d Num buffers per iteration %d Failed buffers %d!!!\n", + coreNum, num_iterations, NUM_BUFS, errBuffCount); + } + + /* Delete RX channel */ + status = mcbspDeleteChan(hMcbspRxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum); + return; + } + + /* Delete TX channel*/ + status = mcbspDeleteChan(hMcbspTxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum); + return; + } + return; +} + +/* + * \brief Void main(Void) + * + * Main function of the sample application. This function calls the + * function to configure the mcbsp instance. + * + * \param None + * + * \return None + */ +#include "ti/sysbios/hal/Cache.h" + +Void main(Void) +{ + Task_Params taskParams; + EDMA3_DRV_Result edmaResult = 0; +#ifdef SIMULATOR_SUPPORT + uint8_t uchValue, uchReadValue; +#endif + + Board_initCfg arg = BOARD_INIT_MODULE_CLOCK | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_UART_STDIO; + Board_init(arg); + + uint32_t temp; + /* Get the core number. */ + coreNum = 0; //CSL_chipReadReg (CSL_CHIP_DNUM); + +#ifdef SIMULATOR_SUPPORT +#warn MCBSP Digital Loopback example is not supported on SIMULATOR !!! + MCBSP_log ("MCBSP Digital Loopback example is not supported on SIMULATOR. Exiting!\n"); + return; +#else + MCBSP_log ("Debug(Core %d): Running MCBSP Digital Loopback example on the DEVICE\n", coreNum); +#endif + + /* Initialize the system only if the core was configured to do so. */ + if (coreNum == CORE_SYS_INIT) + { +#if 0 + MCBSP_log ("Debug(Core %d): System Initialization for MCBSP\n", coreNum); + /* Read FPGA register */ + if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum); + return; + } + /* Clear field for configuration */ + uchValue = (uchReadValue & (~0x3)); +#ifndef PLATFORM_FPGA_MCBSP_AMC_EN + uchValue |= 0x3; +#endif + /* Drive McBSP_AMC_EN# high. Output SLCLKs, TxCLKs, RxCLKs, FSTs, FSRs as Hi-Z. + * These clocks and syncs are tri-stated and McBSP is accessed over 80-pin header */ + if (0 != (platform_fpgaWriteConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, (uchValue)))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register WRITE failed \n", coreNum); + return; + } + + /* DEBUG: Verify if FPGA register is configured correctly */ + if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum); + return; + } + + if (uchValue != uchReadValue) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register setting failed \n", coreNum); + return; + } + else + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register is set to %d \n", coreNum, uchValue); + } +#endif + /* MCBSP Driver Initialization: This should always be called before + * invoking the MCBSP Driver. */ + mcbspInit(); + + /* Device Specific MCBSP Initializations */ + McbspDevice_init(); + + /* MCBSP Driver is operational at this time. */ + MCBSP_log ("Debug(Core %d): MCBSP Driver Initialization Done\n", coreNum); + + /* Write to the SHARED memory location at this point in time. The other cores cannot execute + * till the MCBSP Driver is up and running. */ + isMCBSPInitialized[0] = 1; + + /* The MCBSP IP block has been initialized. We need to writeback the cache here because it will + * ensure that the rest of the cores which are waiting for MCBSP to be initialized would now be + * woken up. */ + //CACHE_wbL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT); + Cache_wb ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH,0x7fff, 1); + } + else + { + /* All other cores need to wait for the MCBSP to be initialized before they proceed with the test. */ + MCBSP_log ("Debug(Core %d): Waiting for MCBSP to be initialized.\n", coreNum); + + /* All other cores loop around forever till the MCBSP is up and running. + * We need to invalidate the cache so that we always read this from the memory. */ + while (isMCBSPInitialized[0] == 0) + //CACHE_invL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT); + Cache_inv ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH, 0x7fff, 1); + + + MCBSP_log ("Debug(Core %d): MCBSP can now be used.\n", coreNum); + } + /* Enabling the dmaChannel MCBSP Events to EDMA (36-40) */ + temp=sampleEdma3GblCfgParams[0].dmaChannelHwEvtMap[1]; + sampleEdma3GblCfgParams[0].dmaChannelHwEvtMap[1]= temp | 0x000000F0; + + /* Let RM Own the dmaChannels (36-40) */ + temp=sampleInstInitConfig[0][0].ownDmaChannels[1]; + sampleInstInitConfig[0][0].ownDmaChannels[1]=temp | 0x000000F0; + + /* Let RM Own the TCCs (36-40) */ + temp=sampleInstInitConfig[0][0].ownTccs[1]; + sampleInstInitConfig[0][0].ownTccs[1]= temp | 0x000000F0; + + /* Initialize EDMA3 library */ + hEdma[0] = edma3init(0, &edmaResult); + + if (edmaResult != EDMA3_DRV_SOK) + { + /* Report EDMA Error */ + MCBSP_log("Debug(Core %d): EDMA Driver Initialization FAILED\n", coreNum); + } + else + { + MCBSP_log("Debug(Core %d): EDMA Driver Initialization Done\n", coreNum); + } + + /* Create the Digital Loopback Application Task */ + Task_Params_init(&taskParams); + Task_create(mcbspDigLpbkApp, &taskParams, NULL); + + /* Start BIOS */ + BIOS_start(); + + return; +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg new file mode 100644 index 000000000..7377088a4 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg @@ -0,0 +1,80 @@ +/* + * Copyright 2012-2018 by Texas Instruments Incorporated. + * + * All rights reserved. Property of Texas Instruments Incorporated. + * Restricted rights to use, duplicate or disclose this code are + * granted through contract. + * + */ + +/* THIS FILE WAS GENERATED BY ti.sysbios.genx */ + +/* + * ======== mcbspMasterDigLpbk.cfg ======== + * + */ + +/* Load and use the required BIOS packages */ +var BIOS = xdc.useModule('ti.sysbios.BIOS'); +var Task = xdc.useModule('ti.sysbios.knl.Task'); +var cache = xdc.useModule('ti.sysbios.hal.Cache'); +var Idle = xdc.useModule('ti.sysbios.knl.Idle'); +var Queue = xdc.useModule('ti.sysbios.knl.Queue'); +var ECM = xdc.useModule('ti.sysbios.family.c64p.EventCombiner'); +var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc'); +var Memory = xdc.useModule('xdc.runtime.Memory'); +var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); + +/* Load and use the System Package */ +var System = xdc.useModule('xdc.runtime.System'); +var SysStd = xdc.useModule('xdc.runtime.SysStd'); + +/* Create a default system heap using ti.bios.HeapMem. */ +var heapMemParams1 = new HeapMem.Params; +heapMemParams1.size = 32768; +heapMemParams1.sectionName = "systemHeap"; +Program.global.heap0 = HeapMem.create(heapMemParams1); + +/* This is the default memory heap. */ +Memory.defaultHeapInstance = Program.global.heap0; + +/* + * Create and install logger for the whole system. + * Enable Event Groups here and registering of ISR for specific GEM INTC is done + * using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs + */ +ECM.eventGroupHwiNum[0] = 7; +ECM.eventGroupHwiNum[1] = 8; +ECM.eventGroupHwiNum[2] = 9; +ECM.eventGroupHwiNum[3] = 10; + +/* Load and use the mcbsp, EDMA, PlatformLib etc. packages */ +var Edma = xdc.loadPackage ("ti.sdo.edma3.drv.sample"); +var drv = xdc.loadPackage ("ti.sdo.edma3.drv"); +var rm = xdc.loadPackage ("ti.sdo.edma3.rm"); + +var devType = "c6657" +var mcbsp = xdc.useModule('ti.drv.mcbsp.Settings'); +mcbsp.deviceType = devType; + +/* Load the uart package */ +var Uart = xdc.loadPackage('ti.drv.uart'); +Uart.Settings.socType = devType; + +var Csl = xdc.useModule('ti.csl.Settings'); +Csl.deviceType = devType; +Csl.libProfile = "release"; + +/* Load the OSAL package */ +var osType = "tirtos" +var Osal = xdc.useModule('ti.osal.Settings'); +Osal.osType = osType; +Osal.socType = devType; + +/* Load the Board package and set the board name */ +var Board = xdc.loadPackage('ti.board'); +Board.Settings.boardName = "evmC6657"; + +/* Circular buffer size for System_printf() */ +System.SupportProxy = SysStd; + diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd new file mode 100644 index 000000000..207553081 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd @@ -0,0 +1,9 @@ +SECTIONS +{ + .init_array: load >> L2SRAM + .mcbsp: load >> L2SRAM + .mcbspSharedMem: load >> L2SRAM + platform_lib: load >> L2SRAM + systemHeap: load >> L2SRAM +} + diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c new file mode 100644 index 000000000..888513df5 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c @@ -0,0 +1,641 @@ +/** + * @file mcbspMasterDigLpbk_osal.c + * + * @brief + * This is the OS abstraction layer and is used by the MCBSP + * driver for the MCBSP Example Digital Loopback Application. + * + * \par + * ============================================================================ + * @n (C) Copyright 2012, Texas Instruments, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * \par +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if 0 +/* CSL Include Files */ +#include +#include +#include +#include +#endif +/* IPC includes */ +/* #include +#include +#include +#include */ + +/********************************************************************** + ************************** Local Definitions ************************* + **********************************************************************/ + +#define MCBSP_HW_SEM 1 +#define PLATFORM_SPI_HW_SEM 2 /**< SPI BUS arbitration - Used by platform library */ + +#ifdef MCBSP_LOOP_PING_PONG +#define MAX_MEM_MGR_ENTRIES 8 +#else +#define MAX_MEM_MGR_ENTRIES 4 +#endif + +typedef struct MEM_MGMT_ENTRY +{ + uint8_t* ptrMemory; + uint32_t isFree; +}MEM_MGMT_ENTRY; + +MEM_MGMT_ENTRY gDataBufferMemMgr[MAX_MEM_MGR_ENTRIES]; +int32_t gDataBufferMemMgrMaxSize = 0; + +/********************************************************************** + ************************** Global Variables ************************** + **********************************************************************/ +UInt32 malloc_counter = 0; +UInt32 free_counter = 0; + +/********************************************************************** + ************************** Extern Definitions ************************ + **********************************************************************/ + + +/********************************************************************** + **************************** OSAL Functions ************************** + **********************************************************************/ + +/** + * @b Description + * @n + * Utility function which converts a local address to global. + * + * @param[in] addr + * Local address to be converted + * + * @retval + * Global Address + */ +void *Osal_local2Global (void *addr) +{ + UInt32 corenum; + + /* Get the core number. */ + corenum = 0;//CSL_chipReadReg(CSL_CHIP_DNUM); + return addr; + + if(((UInt32)addr & 0xff000000) == 0) { + /* Compute the global address. */ + return ((void *)((UInt32)(addr) + (0x10000000 + (corenum*0x1000000)))); + } + else + return(addr); +} + +/** + * @b Description + * @n + * The function is used to allocate a memory block of the specified size. + * + * @param[in] numBytes + * Number of bytes to be allocated. + * + * @retval + * Allocated block address + */ +Void* Osal_mcbspMalloc(UInt32 numBytes) +{ + Error_Block errorBlock; + Void* ptr; + + /* Increment the allocation counter. */ + malloc_counter++; + + /* Allocate the memory. */ + ptr = Memory_alloc(NULL, numBytes, 0, &errorBlock); + + /* Return the allocated memory block. */ + return ptr; +} + +/** + * @b Description + * @n + * The function is used to clean up a specific memory block and is called + * from the MCBSP Driver. + * + * @param[in] ptr + * Pointer to the memory block to be cleaned up. + * @param[in] size + * Size of the memory block being cleaned up. + * + * @retval + * Not Applicable + */ +Void Osal_mcbspFree (Void* ptr, UInt32 size) +{ + /* Increment the free counter. */ + free_counter++; + Memory_free(NULL, ptr, size); +} + +/** + * @b Description + * @n + * The function is used to allocate a block of memory for all the data buffer + * operations. This function is called by the application. + * + * @param[in] numBuffers + * Number of data buffers + * @param[in] dataBufferSize + * Size of each data buffer + * + * @retval + * Success - 0 + * @retval + * Error - <0 + */ +int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize) +{ + Error_Block errorBlock; + uint8_t* ptrMemory; + uint32_t index; + + /* Allocate memory for all the data buffers */ + ptrMemory = (uint8_t*)Memory_alloc(NULL, MAX_MEM_MGR_ENTRIES*dataBufferSize, 128, &errorBlock); + if (ptrMemory == NULL) + return -1; + + /* Convert to a global address */ + ptrMemory = Osal_local2Global(ptrMemory); + + /* Now we chop up the memory and add it to the memory manager. */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Populate the data memory management entry. */ + gDataBufferMemMgr[index].isFree = 1; + gDataBufferMemMgr[index].ptrMemory = ptrMemory; + + /* Increment the memory to the next address */ + ptrMemory = ptrMemory + dataBufferSize; + } + + /* Remember the memory buffer size */ + gDataBufferMemMgrMaxSize = dataBufferSize; + + /* Memory Manager has been created. */ + return 0; +} + +/** + * @b Description + * @n + * The function is used to allocate a data buffer of the specified + * size. Data buffers should always be allocated from the global + * address space. + * + * @param[in] numBytes + * Number of bytes to be allocated. + * + * @retval + * Allocated block address + */ +Void* Osal_mcbspDataBufferMalloc(UInt32 numBytes) +{ + uint32_t index; + void* ptrMemory = NULL; + + /* Basic Validation: Ensure that the memory size requested is within range. */ + if (numBytes > gDataBufferMemMgrMaxSize) + return NULL; + + /* Increment the allocation counter. */ + malloc_counter++; + + /* Lock out interrupts */ + Hwi_disable(); + + /* Cycle through for a free entry. */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Check if the entry is free or not? */ + if (gDataBufferMemMgr[index].isFree == 1) + { + /* Entry was free. We can use it. */ + ptrMemory = gDataBufferMemMgr[index].ptrMemory; + + /* Mark the entry as used. */ + gDataBufferMemMgr[index].isFree = 0; + + /* We have found a match. */ + break; + } + } + + /* Unlock interrupts. */ + Hwi_enable(); + + /* Return the allocated memory. */ + return ptrMemory; +} + +/** + * @b Description + * @n + * The function is used to clean up a previously allocated data buffer + * block. All data buffers are in the global address space + * + * @param[in] ptr + * Pointer to the data buffer block to be cleaned up + * @param[in] size + * Size of the data buffer + * + * @retval + * Not Applicable + */ +void Osal_mcbspDataBufferFree(void* ptr, uint32_t numBytes) +{ + uint32_t index; + + /* Increment the free counter. */ + free_counter++; + + /* Lock out interrupts */ + Hwi_disable(); + + /* Cycle through and clean up */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Check if the entry is free or not? */ + if (gDataBufferMemMgr[index].ptrMemory == (uint8_t*)ptr) + { + /* Mark the entry as free. */ + gDataBufferMemMgr[index].isFree = 1; + + /* We have found a match. */ + break; + } + } + + /* Unlock interrupts. */ + Hwi_enable(); + return; +} + +/** + * @b Description + * @n + * The function is the MCBSP OSAL Logging API which logs + * the messages on the console. + * + * @param[in] fmt + * Formatted String. + * + * @retval + * Not Applicable + */ +Void Osal_mcbspLog( String fmt, ... ) +{ +} + +/** + * @b Description + * @n + * The function is used to create a critical section. + * + * @retval + * Semaphore Handle created + */ +Void* Osal_mcbspCreateSem(Void) +{ + return (Void*)Semaphore_create(0, NULL, NULL); +} + +/** + * @b Description + * @n + * The function is used to delete a critical section. + * + * @param[in] semHandle + * Semaphore handle to be deleted + * + * @retval + * Not Applicable + */ +Void Osal_mcbspDeleteSem(Void* semHandle) +{ + Semaphore_delete(semHandle); +} + +/** + * @b Description + * @n + * The function is used to pend on a semaphore + * + * @param[in] semHandle + * Semaphore handle on which the API will pend + * + * @retval + * Not Applicable + */ +Void Osal_mcbspPendSem(Void* semHandle) +{ + Semaphore_pend(semHandle, BIOS_WAIT_FOREVER); +} + +/** + * @b Description + * @n + * The function is used to post a semaphore + * + * @param[in] semHandle + * Semaphore handle which will be posted + * + * @retval + * Not Applicable + */ +Void Osal_mcbspPostSem(Void* semHandle) +{ + Semaphore_post(semHandle); +} + +/** + * @b Description + * @n + * This is the Multicore OSAL Implementation to protect the driver shared + * resources across multiple cores. + * + * @retval + * Semaphore Opaque Handle + */ +void* Osal_mcbspEnterMultipleCoreCriticalSection(void) +{ + /* Get the hardware semaphore */ + // while ((CSL_semAcquireDirect (MCBSP_HW_SEM)) == 0); + return NULL; +} + +/** + * @b Description + * @n + * The function is called to end the critical section which was protecting + * shared resources from access across multiple cores. + * + * @param[in] critSectHandle + * Semaphore opaque handle. + * + * @retval + * None + */ +Void Osal_mcbspExitMultipleCoreCriticalSection(Void* critSectHandle) +{ + //CSL_semReleaseSemaphore (MCBSP_HW_SEM); +} + +/** + * @b Description + * @n + * The function is used to provide critical section to prevent access of shared + * resources from single core and multiple threads. + * + * @param[in] drvHandle + * Driver Handle which needs critical section to protect its resources. + * + * @retval + * Opaque handle + */ +Void* Osal_mcbspEnterSingleCoreCriticalSection() +{ + /* Disable interrupts */ + return (Void*)Hwi_disable(); +} + +/** + * @b Description + * @n + * The function is called to end the critical section access of shared resources + * from single cores. + * + * @param[in] drvHandle + * Driver Handle which needed critical section to protect its resources. + * @param[in] critSectHandle + * Opaque handle retreived when the Single Core Protection Enter API was called + * + * @retval + * Not Applicable. + */ +Void Osal_mcbspExitSingleCoreCriticalSection(Void* critSectHandle) +{ + /* Driver Managed Configuration: We need to enable interrupts. */ + Hwi_enable(); +} + +/** + * @b Description + * @n + * The function is used by the MCBSP driver to indicate that + * its about to access a block of memory and we need to ensure + * that the cache contents for this block are invalidated before + * we try and use it. + * + * @param[in] ptr + * Pointer to the buffer which is being accessed + * @param[in] size + * Size of the buffer which is to be accessed. + * + * @retval + * None + */ +#include "ti/sysbios/hal/Cache.h" +void Osal_mcbspBeginMemAccess(void* ptr, uint32_t size) +{ + UInt key; + + /* Disable Interrupts */ + key = Hwi_disable(); + + /* Cleanup the prefetch buffer also. */ + //CSL_XMC_invalidatePrefetchBuffer(); + + /* Invalidate the cache. */ + //CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT); + + Cache_inv ((void *) ptr,size, 0x7fff, 1); + + /* Reenable Interrupts. */ + Hwi_restore(key); +} + +/** + * @b Description + * @n + * The function is used by the MCBSP driver to indicate that its + * ending access to a block of memory. We need to ensure that the + * contents of the cache are written back to the actual memory. + * + * @param[in] ptr + * Pointer to the buffer + * @param[in] size + * Size of the buffer + * + * @retval + * None + */ +void Osal_mcbspEndMemAccess(void* ptr, uint32_t size) +{ + UInt key; + + /* Disable Interrupts */ + key = Hwi_disable(); + + /* Writeback the cache. */ + //CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT); + Cache_wb ((void *) ptr,size, 0x7fff, 1); + /* Reenable Interrupts. */ + Hwi_restore(key); +} + +/** + * @brief The function is used by the MCBSP driver to test for an + * empty queue. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n TRUE - If the queue is empty + */ +Bool Osal_mcbspQueueEmpty(void* handle) +{ + return Queue_empty(handle); +} + +/** + * @brief The macro is used by the MCBSP driver to get an + * element from the front of queue. The function + * removes the element from the front of queue and + * returns a pointer to it. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n Handle (pointer) to former first element + */ +void* Osal_mcbspQueueGet(void* handle) +{ + return Queue_get(handle); +} + +/** + * @brief The macro is used by the MCBSP driver to put an + * element at the end of queue. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * @n elem - Pointer to new queue element + * + * Return Value + * @n None + */ +void Osal_mcbspQueuePut(void* handle, Mcbsp_QueueElem* elem) +{ + Queue_put(handle, (Queue_Elem *)elem); + return; +} + +/** + * @brief The macro is used by the MCBSP driver to wait 'n' + * bit clocks to ensure proper synchronization internally. + * + * Parameter + * @n nticks - Number of bit clocks to wait + * + * Return Value + * @n None + */ +void Osal_mcbspWaitNBitClocks(uint32_t nticks) +{ + //Task_sleep(nticks); + int i=0; + for (i=0; i<100; i++); + return; +} + +/* OSAL functions for Platform Library */ +uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment) +{ + return malloc(num_bytes); +} + +void Osal_platformFree (uint8_t *dataPtr, uint32_t num_bytes) +{ + /* Free up the memory */ + if (dataPtr) + { + free(dataPtr); + } +} + +void Osal_platformSpiCsEnter(void) +{ + /* Get the hardware semaphore. + * + * Acquire Multi core CPPI synchronization lock + */ + //while ((CSL_semAcquireDirect (PLATFORM_SPI_HW_SEM)) == 0); + + return; +} + +void Osal_platformSpiCsExit (void) +{ + /* Release the hardware semaphore + * + * Release multi-core lock. + */ + //CSL_semReleaseSemaphore (PLATFORM_SPI_HW_SEM); + + return; +} diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c new file mode 100644 index 000000000..b698e98d2 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c @@ -0,0 +1,701 @@ +/* + * sample_c6657_cfg.c + * + * Platform specific EDMA3 hardware related information like number of transfer + * controllers, various interrupt ids etc. It is used while interrupts + * enabling / disabling. It needs to be ported for different SoCs. + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include + +/* Number of EDMA3 controllers present in the system */ +#define NUM_EDMA3_INSTANCES 1u +const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES; + +/* Number of DSPs present in the system */ +#define NUM_DSPS 2u +//const unsigned int numDsps = NUM_DSPS; + +#define CGEM_REG_START (0x01800000) + + +extern cregister volatile unsigned int DNUM; + +#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff)) + + +/* Determine the processor id by reading DNUM register. */ +unsigned short determineProcId() + { + volatile unsigned int *addr; + unsigned int core_no; + + /* Identify the core number */ + addr = (unsigned int *)(CGEM_REG_START+0x40000); + core_no = ((*addr) & 0x000F0000)>>16; + + return core_no; + } + +signed char* getGlobalAddr(signed char* addr) +{ + if (((unsigned int)addr & (unsigned int)0xFF000000) != 0) + { + return (addr); /* The address is already a global address */ + } + + return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr))); +} +/** Whether global configuration required for EDMA3 or not. + * This configuration should be done only once for the EDMA3 hardware by + * any one of the masters (i.e. DSPs). + * It can be changed depending on the use-case. + */ +unsigned int gblCfgReqdArray [NUM_DSPS] = { + 0, /* DSP#0 is Master, will do the global init */ + 1, /* DSP#1 is Slave, will not do the global init */ + }; + +unsigned short isGblConfigRequired(unsigned int dspNum) + { + return gblCfgReqdArray[dspNum]; + } + +/* Semaphore handles */ +EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; + + +/* Variable which will be used internally for referring number of Event Queues. */ +unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {4u}; + +/* Variable which will be used internally for referring number of TCs. */ +unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {4u}; + +/** + * Variable which will be used internally for referring transfer completion + * interrupt. Completion interrupts for all the shadow regions and all the + * EDMA3 controllers are captured since it is a multi-DSP platform. + */ +unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { + { + 24u, 25u, 26u, 27u, + 28u, 29u, 30u, 31u, + }, + }; + +/** + * Variable which will be used internally for referring channel controller's + * error interrupt. + */ +unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {16u}; + +/** + * Variable which will be used internally for referring transfer controllers' + * error interrupts. + */ +unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = { + { + 18u, 19u, 20u, 21u, + 0u, 0u, 0u, 0u, + }, + }; + +/* Driver Object Initialization Configuration */ +EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = + { + { + /* EDMA3 INSTANCE# 0 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 64u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 64u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 512u, + /** Total number of Event Queues in the EDMA3 Controller */ + 4u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ + 4u, + /** Number of Regions on this EDMA3 controller */ + 8u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 1u, + + /** Existence of memory protection feature */ + 1u, + + /** Global Register Region of CC Registers */ + (void *)0x02740000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x02790000u, + (void *)0x02798000u, + (void *)0x027A0000u, + (void *)0x027A8000u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + 24u, + /** Interrupt no. for CC Error */ + 16u, + /** Interrupt no. for TCs Error */ + { + 18u, + 19u, + 20u, + 21u, + 0u, + 0u, + 0u, + 0u, + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 2u, + 3u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 16u, + 16u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 64u, + 64u, + 64u, + 64u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + 0xFFFFFFFFu, + 0xFF0000FFu + } + }, + }; + +EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = + { + /* EDMA3 INSTANCE# 0 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 287 256 319 288 351 320 383 352 */ + 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x0000FF00u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x0000000Fu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x0000FFF0u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFF0000FFu}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFF0000FFu}, + }, + + /* Resources owned/reserved by region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 415 384 447 416 479 448 511 480 */ + 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00FF0000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000F0u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00FF0000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFF0000FFu}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFF0000FFu}, + }, + + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + }, + }; + +/* End of File */ diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_int_reg.c b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_int_reg.c new file mode 100644 index 000000000..a727019c7 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_int_reg.c @@ -0,0 +1,153 @@ +/* + * sample_c6657_int_reg.c + * + * Platform specific interrupt registration and un-registration routines. + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include +#include + +#include + +extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS]; +extern unsigned int ccErrorInt[]; +extern unsigned int tcErrorInt[][EDMA3_MAX_TC]; +extern unsigned int numEdma3Tc[]; + +void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) = + { + &lisrEdma3TC0ErrHandler0, + &lisrEdma3TC1ErrHandler0, + &lisrEdma3TC2ErrHandler0, + &lisrEdma3TC3ErrHandler0, + &lisrEdma3TC4ErrHandler0, + &lisrEdma3TC5ErrHandler0, + &lisrEdma3TC6ErrHandler0, + &lisrEdma3TC7ErrHandler0, + }; + +unsigned int hwiInterrupt = 8; + +/* Host interrupts for transfer completion */ +//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = { +unsigned int ccXferHostInt[1][2] = { + {0u, 20u}, + }; +unsigned int edma3ErrHostInt[1][2] = { + {1u, 21u}, + }; + + +extern unsigned int dsp_num; + +/** To Register the ISRs with the underlying OS, if required */ +void registerEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + Int eventId = 0; /* GEM event id */ + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Transfer completion ISR */ + CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num], + lisrEdma3ComplHandler0, + edma3Id, + TRUE); + CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num], + ccXferHostInt[edma3Id][dsp_num]); + CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]); + eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]); + EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, + ccXferHostInt[edma3Id][dsp_num], TRUE); + EventCombiner_enableEvent(eventId); + + /* CC Error ISR */ + CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0, + edma3Id, TRUE); + CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id], + edma3ErrHostInt[edma3Id][dsp_num]); + /* TC Error ISR */ + while (numTc < numEdma3Tc[edma3Id]) + { + CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc], + (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]), + edma3Id, TRUE); + CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc], + edma3ErrHostInt[edma3Id][dsp_num]); + numTc++; + } + /* Enable the host interrupt which is common for both CC and TC error */ + CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]); + eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]); + EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, + edma3ErrHostInt[edma3Id][dsp_num], TRUE); + EventCombiner_enableEvent(eventId); + + Hwi_enableInterrupt(hwiInterrupt); + + /* enable the 'global' switch */ + CpIntc_enableAllHostInts(0); + + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +void unregisterEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + Int eventId = 0; /* GEM event id */ + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Transfer completion ISR */ + CpIntc_disableHostInt(0, ccXferHostInt[edma3Id][dsp_num]); + eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]); + EventCombiner_disableEvent(eventId); + + /* CC/TC Error ISR */ + CpIntc_disableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]); + eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]); + EventCombiner_disableEvent(eventId); + + /* Restore interrupts */ + Hwi_restore(cookie); + } + diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_cs.c b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_cs.c new file mode 100644 index 000000000..2cfcc4ca8 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_cs.c @@ -0,0 +1,419 @@ +/* + * sample_cs.c + * + * Sample functions showing the implementation of critical section entry/exit + * routines and various semaphore related routines (all BIOS6 depenedent). + * These implementations MUST be provided by the user / application, using the + * EDMA3 driver, for its correct functioning. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include +#include +#include + +#include + +extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]; +extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES]; +extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC]; + +/** + * Shadow Region on which the executable is running. Its value is + * populated with the DSP Instance Number here in this case. + */ +extern uint32_t region_id; + +/** + * \brief EDMA3 OS Protect Entry + * + * This function saves the current state of protection in 'intState' + * variable passed by caller, if the protection level is + * EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of + * protection. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is disabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the + * Transfer Controller number whose interrupt needs to be disabled. + * + * \param level is numeric identifier of the desired degree of protection. + * \param intState is memory location where current state of protection is + * saved for future use while restoring it via edma3OsProtectExit() (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectEntry (uint32_t edma3InstanceId, + int32_t level, uint32_t *intState) + { + if (((level == EDMA3_OS_PROTECT_INTERRUPT) + || (level == EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR)) + && (intState == NULL)) + { + /* Nothing to be done here */ + } + else + { + switch (level) + { + /* Disable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + *intState = Hwi_disable(); + break; + + /* Disable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_disable(); + break; + + /* Disable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_disableEvent(ccXferCompInt[edma3InstanceId][region_id]); + break; + + /* Disable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_disableEvent(ccErrorInt[edma3InstanceId]); + break; + + /* Disable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch (*intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Disable the corresponding interrupt */ + EventCombiner_disableEvent(tcErrorInt[edma3InstanceId][*intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + return; + } + + +/** + * \brief EDMA3 OS Protect Exit + * + * This function undoes the protection enforced to original state + * as is specified by the variable 'intState' passed, if the protection + * level is EDMA3_OS_PROTECT_INTERRUPT. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is enabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the + * Transfer Controller number whose interrupt needs to be enabled. + * \param level is numeric identifier of the desired degree of protection. + * \param intState is original state of protection at time when the + * corresponding edma3OsProtectEntry() was called (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectExit (uint32_t edma3InstanceId, + int32_t level, uint32_t intState) + { + switch (level) + { + /* Enable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + Hwi_restore(intState); + break; + + /* Enable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_enable(); + break; + + /* Enable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_enableEvent(ccXferCompInt[edma3InstanceId][region_id]); + break; + + /* Enable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_enableEvent(ccErrorInt[edma3InstanceId]); + break; + + /* Enable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch ((int32_t)intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Enable the corresponding interrupt */ + EventCombiner_enableEvent(tcErrorInt[edma3InstanceId][intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + + +/** + * \brief EDMA3 Cache Invalidate + * + * This function invalidates the D cache. + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheInvalidate(uint32_t mem_start_ptr, + uint32_t num_bytes) + { + EDMA3_DRV_Result cacheInvResult = EDMA3_DRV_SOK; + + /* Verify whether the start address is cache aligned or not */ + if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1U)) != 0) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n", + EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif + cacheInvResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR; + } + else + { + Cache_inv((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, (Bool)TRUE); + } + + return cacheInvResult; +} + + + +/** + * \brief EDMA3 Cache Flush + * + * This function flushes (cleans) the Cache + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheFlush(uint32_t mem_start_ptr, + uint32_t num_bytes) + { + EDMA3_DRV_Result cacheFlushResult = EDMA3_DRV_SOK; + + /* Verify whether the start address is cache aligned or not */ + if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1U)) != 0) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n", + EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif + cacheFlushResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR; + } + else + { + Cache_wb((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, (Bool)TRUE); + } + + return cacheFlushResult; +} + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 driver/RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to recieve the handle to just created + * semaphore + * \return EDMA3_DRV_SOK if succesful, else a suitable error code. + */ +EDMA3_DRV_Result edma3OsSemCreate(int32_t initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem) + { + EDMA3_DRV_Result semCreateResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semCreateResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + *hSem = (EDMA3_OS_Sem_Handle)Semaphore_create(initVal, semParams, NULL); + if ( (*hSem) == NULL ) + { + semCreateResult = EDMA3_DRV_E_SEMAPHORE; + } + } + + return semCreateResult; + } + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_DRV_SOK if succesful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_DRV_Result semDeleteResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semDeleteResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + Semaphore_delete((Semaphore_Handle *)&hSem); + } + + return semDeleteResult; + } + + +/** + * \brief EDMA3 OS Semaphore Take + * + * This function takes a semaphore token if available. + * If a semaphore is unavailable, it blocks currently + * running thread in wait (for specified duration) for + * a free semaphore. + * \param hSem [IN] is the handle of the specified semaphore + * \param mSecTimeout [IN] is wait time in milliseconds + * \return EDMA3_Result if successful else a suitable error code + */ +EDMA3_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int32_t mSecTimeout) + { + EDMA3_Result semTakeResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semTakeResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + if((Semaphore_pend(hSem, (uint32_t)mSecTimeout)) == FALSE) + { + semTakeResult = EDMA3_DRV_E_SEMAPHORE; + } + } + + return semTakeResult; + } + + +/** + * \brief EDMA3 OS Semaphore Give + * + * This function gives or relinquishes an already + * acquired semaphore token + * \param hSem [IN] is the handle of the specified semaphore + * \return EDMA3_Result if successful else a suitable error code + */ +EDMA3_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_Result semGiveResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semGiveResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + Semaphore_post(hSem); + } + + return semGiveResult; + } + +/* End of File */ + diff --git a/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_init.c b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_init.c new file mode 100644 index 000000000..b8f0b6295 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_init.c @@ -0,0 +1,226 @@ +/* + * sample_init.c + * + * Sample Initialization for the EDMA3 Driver for BIOS 6 based applications. + * It should be MANDATORILY done once before EDMA3 usage. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include + +#include + +/** @brief EDMA3 Driver Instance specific Semaphore handle */ +extern EDMA3_OS_Sem_Handle semHandle[EDMA3_MAX_EDMA3_INSTANCES]; + +/** To Register the ISRs with the underlying OS, if required. */ +extern void registerEdma3Interrupts (uint32_t edma3Id); +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +extern void unregisterEdma3Interrupts (uint32_t edma3Id); + +/* To find out the DSP# */ +extern uint16_t determineProcId(void); + +/** + * To check whether the global EDMA3 configuration is required or not. + * It should be done ONCE by any of the masters present in the system. + * This function checks whether the global configuration is required by the + * current master or not. In case of many masters, it should be done only + * by one of the masters. Hence this function will return TRUE only once + * and FALSE for all other masters. + */ +extern uint16_t isGblConfigRequired(uint32_t dspNum); + +/** + * DSP instance number on which the executable is running. Its value is + * determined by reading the processor specific register DNUM. + */ +uint32_t dsp_num; + +/** + * Shadow Region on which the executable is runnig. Its value is populated + * with the DSP Instance Number here in this case. + */ +uint32_t region_id; + +/* Number of EDMA3 controllers present in the system */ +extern const uint32_t numEdma3Instances; + +/* External Global Configuration Structure */ +extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[EDMA3_MAX_EDMA3_INSTANCES]; + +/* External Instance Specific Configuration Structure */ +extern EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]; + +#ifdef DMA_XBAR_AVAILABLE +extern EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, uint32_t edma3Id); +#endif + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 Driver and registers the + * interrupt handlers. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Handle edma3init (uint32_t edma3Id, EDMA3_DRV_Result *errorCode) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM; + Semaphore_Params semParams; + EDMA3_DRV_GblConfigParams *globalConfig = NULL; + EDMA3_DRV_InitConfig initCfg; + EDMA3_RM_MiscParam miscParam; + EDMA3_DRV_Handle hEdma = NULL; + + if ((edma3Id >= numEdma3Instances) || (errorCode == NULL)) + { + hEdma = NULL; + } + else + { + /* DSP instance number */ + dsp_num = determineProcId(); + + globalConfig = &sampleEdma3GblCfgParams[edma3Id]; + + /* Configure it as master, if required */ + miscParam.isSlave = isGblConfigRequired(dsp_num); + edma3Result = EDMA3_DRV_create (edma3Id, globalConfig , + (void *)&miscParam); + + if (edma3Result == EDMA3_DRV_SOK) + { + /** + * Driver Object created successfully. + * Create a semaphore now for driver instance. + */ + Semaphore_Params_init(&semParams); + + initCfg.drvSemHandle = NULL; + edma3Result = edma3OsSemCreate((int32_t)1, &semParams, &initCfg.drvSemHandle); + } + + if (edma3Result == EDMA3_DRV_SOK) + { + /* Save the semaphore handle for future use */ + semHandle[edma3Id] = initCfg.drvSemHandle; + + /* Driver instance specific config NULL */ + initCfg.drvInstInitConfig = NULL; + +#ifndef EDMA3_DRV_USE_DEF_RM_CFG + /* Hook for running examples with default RM config */ + /* configuration structure for the Driver */ + initCfg.drvInstInitConfig = &sampleInstInitConfig[edma3Id][dsp_num]; +#endif + + initCfg.isMaster = TRUE; + /* Choose shadow region according to the DSP# */ + initCfg.regionId = (EDMA3_RM_RegionId)dsp_num; + /*Saving the regionId for using it in the sample_cs.c file */ + region_id = (EDMA3_RM_RegionId)dsp_num; + /* Driver instance specific config NULL */ + + initCfg.gblerrCb = NULL; + initCfg.gblerrData = NULL; + + /* Open the Driver Instance */ + hEdma = EDMA3_DRV_open (edma3Id, (void *) &initCfg, &edma3Result); + } + +#ifdef DMA_XBAR_AVAILABLE + { + if((hEdma != NULL) && (edma3Result == EDMA3_DRV_SOK)) + { + edma3Result = sampleInitXbarEvt(hEdma, edma3Id); + } + } +#endif + if((hEdma != NULL) && (edma3Result == EDMA3_DRV_SOK)) + { + /** + * Register Interrupt Handlers for various interrupts + * like transfer completion interrupt, CC error + * interrupt, TC error interrupts etc, if required. + */ + registerEdma3Interrupts(edma3Id); + } + + *errorCode = edma3Result; + } + return hEdma; + } + + +/** + * \brief EDMA3 De-initialization + * + * This function removes the EDMA3 Driver instance and unregisters the + * interrupt handlers. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result edma3deinit (uint32_t edma3Id, EDMA3_DRV_Handle hEdma) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM; + + /* Unregister Interrupt Handlers first */ + unregisterEdma3Interrupts(edma3Id); + + /* Delete the semaphore */ + edma3Result = edma3OsSemDelete(semHandle[edma3Id]); + + if (EDMA3_DRV_SOK == edma3Result ) + { + /* Make the semaphore handle as NULL. */ + semHandle[edma3Id] = NULL; + + /* Now, close the EDMA3 Driver Instance */ + edma3Result = EDMA3_DRV_close (hEdma, NULL); + } + + if (EDMA3_DRV_SOK == edma3Result ) + { + /* Now, delete the EDMA3 Driver Object */ + edma3Result = EDMA3_DRV_delete (edma3Id, NULL); + } + + return edma3Result; + } + +/* End of File */ + diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/MCBSP_DigLpbkC66ExampleProject.txt b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/MCBSP_DigLpbkC66ExampleProject.txt new file mode 100644 index 000000000..2565bf5e5 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/MCBSP_DigLpbkC66ExampleProject.txt @@ -0,0 +1,11 @@ +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/device/c674x/device_mcbsp_loopback.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_cfg.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_int_reg.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_cs.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_init.c" + +-ccs.setCompilerOptions "-Domapl138 -DMCBSP_DEBUG_TEMP -mv6740 -g --diag_warning=225 -I${PDK_INSTALL_PATH} -I${BIOS_INSTALL_PATH}/packages -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/MCBSPDigLpbk -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/include -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/include -I${PDK_INSTALL_PATH}/ti/drv/mcbsp -I${PDK_INSTALL_PATH}/ti/board" -rtsc.enableRtsc diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/bios6_edma3_drv_sample.h b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/bios6_edma3_drv_sample.h new file mode 100644 index 000000000..5fad8a74a --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/bios6_edma3_drv_sample.h @@ -0,0 +1,186 @@ +/* + * bios6_edma3_drv_sample.h + * + * Header file for the sample application for the EDMA3 Driver. + * + * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef _BIOS6_EDMA3_DRV_SAMPLE_H_ +#define _BIOS6_EDMA3_DRV_SAMPLE_H_ + +#include +#include + +/* Include EDMA3 Driver */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Cache line size on the underlying SoC. It needs to be modified + * for different cache line sizes, if the Cache is Enabled. + */ +#define EDMA3_CACHE_LINE_SIZE_IN_BYTES (128u) + +/* Error returned in case of buffers are not aligned on the cache boundary */ +#define EDMA3_NON_ALIGNED_BUFFERS_ERROR (-1) + +/* Error returned in case of data mismatch */ +#define EDMA3_DATA_MISMATCH_ERROR (-2) + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 Driver for the given EDMA3 controller + * and opens a EDMA3 driver instance. It internally calls EDMA3_DRV_create() and + * EDMA3_DRV_open(), in that order. + * + * It also registers interrupt handlers for various EDMA3 interrupts like + * transfer completion or error interrupts. + * + * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0) + * \param errorCode [IN/OUT] Error code while opening DRV instance + * \return EDMA3_DRV_Handle: If successfully opened, the API will return the + * associated driver's instance handle. + */ +EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode); + +/** + * \brief EDMA3 De-initialization + * + * This function de-initializes the EDMA3 Driver for the given EDMA3 controller + * and closes the previously opened EDMA3 driver instance. It internally calls + * EDMA3_DRV_close and EDMA3_DRV_delete(), in that order. + * + * It also un-registers the previously registered interrupt handlers for various + * EDMA3 interrupts. + * + * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0) + * \param hEdma [IN] EDMA3 Driver handle, returned while using + * edma3init(). + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma); + + +/** + * \brief EDMA3 Cache Invalidate + * + * This function invalidates the D cache. + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * \brief EDMA3 Cache Flush + * + * This function flushes (cleans) the Cache + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 driver/RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to receive the handle to just created + * semaphore. + * \return EDMA3_DRV_SOK if successful, else a suitable error code. + */ +EDMA3_DRV_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem); + + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_DRV_SOK if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _BIOS6_EDMA3_DRV_SAMPLE_H_ */ + diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.c b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.c new file mode 100644 index 000000000..005508e24 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.c @@ -0,0 +1,978 @@ +/* + * mcbspMasterDigLpbk.c + * + * This file contains the test / demo code to demonstrate the McBSP driver + * master functionality using Digital Loopback setup. The file configures + * the EVM in master mode. + * + * Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/* ========================================================================== */ +/* INCLUDE FILES */ +/* ========================================================================== */ + +#include +#include +#include +#include +#include +#include + +#include + +/* Include EDMA3 Driver */ +#include + +/* CSL Chip Functional Layer */ +//#include + +/* CSL Cache Functional Layer */ +//#include + +/* CSL CPINTC Include Files. */ +//#include + +/* MCBSP Driver Include File. */ +#include +#include +#include +#include + +/* PlatformLib Include File */ +//#include + + +/* ========================================================================== */ +/* EXTERNAL FUNCTIONS */ +/* ========================================================================== */ + +extern EDMA3_DRV_Handle edma3init(unsigned int edma3Id, EDMA3_DRV_Result *); + +extern void McbspDevice_init(void); + +extern int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize); + +extern void McbspXmtInterrupt_init(void *mcbspTxChan); +extern void McbspRcvInterrupt_init(void *mcbspRxChan); + +extern Board_STATUS Board_init(Board_initCfg); + +/* FPGA Configuration Misc-1 Register offset */ +#define MCBSP_FPGA_MISC_REG_OFFSET (0x0C) + +/* ========================================================================== */ +/* MACRO DEFINTIONS */ +/* ========================================================================== */ + +#define NUM_BUFS 2 /* Max of buffers used in each direction */ +#define FRAMESIZE 40 /* e.g 5 ms 8 KHz samples */ +#define NUM_OF_ENABLED_CHANNELS 8 /* Number of slots to be used */ +#define NUM_OF_MAX_CHANNELS 128 /* Maximum number of time slots available based on clock settings */ +#define BUFSIZE (NUM_OF_ENABLED_CHANNELS * FRAMESIZE) /* Total buffer size per frame */ + +/* Defines the core number responsible for system initialization. */ +#define CORE_SYS_INIT 0 +/* Number of iterations to execute test: Only applicable to INTERNAL CLOCK Loopback test */ +#define NUM_OF_ITERATIONS 10 + +/* Number of MCBSP Frame structures used for submit channel */ +#define NUM_OF_MCBSP_FRAMES 2 + +/* Number of buffers initially submitted to Mcbsp lld: Only applicable to + External clock test ; Note: This should be set to 2*/ +#define INIT_SUBMIT_Q_CNT 2 + +/*============================================================================*/ +/* GLOBAL VARIABLES */ +/*============================================================================*/ + +/* Shared Memory Variable to ensure synchronizing MCBSP initialization + * with all the other cores. */ +/* Created an array to pad the cache line with MCBSP_CACHE_LENGTH size */ +#pragma DATA_ALIGN (isMCBSPInitialized, MCBSP_MAX_CACHE_ALIGN) +#pragma DATA_SECTION (isMCBSPInitialized, ".mcbspSharedMem"); +volatile Uint32 isMCBSPInitialized[(MCBSP_CACHE_LENGTH / sizeof(Uint32))] = { 0 }; + +/* Handle to the EDMA driver instance */ +#pragma DATA_ALIGN (hEdma, MCBSP_MAX_CACHE_ALIGN) +EDMA3_DRV_Handle hEdma[(MCBSP_CACHE_LENGTH / sizeof(EDMA3_DRV_Handle))] = { NULL }; + +/* Handle to MCBSP driver instance */ +typedef void* Mcbsp_DevHandle; +Mcbsp_DevHandle hMcbspDev; + +/* Handle to MCBSP driver channel instance */ +typedef void* Mcbsp_ChanHandle; +Mcbsp_ChanHandle hMcbspTxChan; +Mcbsp_ChanHandle hMcbspRxChan; + +/* Core Number Identifier */ +UInt32 coreNum = 0xFFFF; + +/* Array to hold the pointer to the allocated buffers */ +void* bufRx[NUM_BUFS]; +void* bufTx[NUM_BUFS]; + +#ifdef MCBSP_LOOP_PING_PONG +/* Ping pong buffers used to submit to Mcbsp lld, which will be used in a loop */ +void* bufRxPingPong[INIT_SUBMIT_Q_CNT]; +void* bufTxPingPong[INIT_SUBMIT_Q_CNT]; +#endif +/* Global Error call back function prototype */ +void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3); + +/* Variables to indicate status of EDMA TX and RX requests */ +volatile uint32_t edmaTxDone = 0; +volatile uint32_t edmaRxDone = 0; +/* Global variables to track number of buffers submitted, number of iterations, error counts etc */ +int rxSubmitCount=0, txSubmitCount=0; +uint32_t num_iterations=0; +uint32_t num_rx_Call_backs=0, num_tx_Call_backs=0, dummy_call_backs=0; +uint32_t rxunderflowcnt=0, txunderflowcnt=0; +uint32_t errBuffCount=0; +/* Debug variables */ +volatile int debugVar=1; /* This can be used to maintain a while loop, If set to 0 will exit loop */ +volatile int debugCommand=1; /* This can be used to set to value below to send command to restart channel */ + +#define DEBUG_COMMAND_RESTART_CHANNELS 1 +/** + * \brief Mcbsp Sample rate generator default parameters. + * + */ +Mcbsp_srgConfig mcbspSrgCfg = +{ + FALSE, /* No gsync to be used as input is not CLKS */ + Mcbsp_ClkSPol_RISING_EDGE, /* Dont care as input clock is not clks */ + Mcbsp_SrgClk_CLKCPU, /* McBSP internal clock to be used */ + 166666667, /* Mcbsp internal clock frequency(PLL-SYSCLK6) */ + 0 /* frame sync pulse width (val+1) is used */ +}; + +/** + * \brief Mcbsp device creation default parameters. + * + */ +const Mcbsp_Params Mcbsp_PARAMS = +{ + Mcbsp_DevMode_McBSP, /* Use the device as MCBSP */ + Mcbsp_OpMode_DMAINTERRUPT, /* Use DMA mode of operation */ + TRUE, /* cache coherency taken care of by driver */ + Mcbsp_EmuMode_FREE, /* Emulation mode free is to be enabled */ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_Loopback_DISABLE, /* Loop back mode disabled */ +#else + Mcbsp_Loopback_ENABLE, /* Loop back mode enabled */ +#endif + &mcbspSrgCfg, /* sample rate generator configuration */ + NULL, /* TX pending buffer queue from application */ + NULL, /* TX floating buffer queue in DMA */ + NULL, /* RX pending buffer queue from application */ + NULL /* RX floating buffer queue in DMA */ +}; + +#pragma DATA_ALIGN(loopTxJob, MCBSP_MAX_CACHE_ALIGN) +static Int32 loopTxJob[16] = { + /* Filling with Mu law silence pattern : Can be any user defined pattern */ + 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, + 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f +}; +#pragma DATA_ALIGN(loopRxJob, MCBSP_MAX_CACHE_ALIGN) +static Int32 loopRxJob[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/**< settings to configure the TX or RX hardware sections */ +Mcbsp_DataConfig mcbspChanConfigTx = +{ + Mcbsp_Phase_SINGLE, + Mcbsp_WordLength_8, + Mcbsp_WordLength_8, /* Dont care for single phase*/ + NUM_OF_MAX_CHANNELS, + NUM_OF_MAX_CHANNELS, // Only used with dual phase + Mcbsp_FrmSync_DETECT, +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_DataDelay_0_BIT, +#else + Mcbsp_DataDelay_1_BIT, +#endif + Mcbsp_Compand_OFF_MSB_FIRST, + Mcbsp_BitReversal_DISABLE, + Mcbsp_IntMode_ON_SYNCERR, + Mcbsp_RxJust_RZF, /* Dont care for TX */ + Mcbsp_DxEna_OFF +}; + +/**< settings to configure the TX or RX hardware sections */ +Mcbsp_DataConfig mcbspChanConfigRx = +{ + Mcbsp_Phase_SINGLE, + Mcbsp_WordLength_8, + Mcbsp_WordLength_8, /* Dont care for single phase*/ + NUM_OF_MAX_CHANNELS, + NUM_OF_MAX_CHANNELS, // Only used with dual phase + Mcbsp_FrmSync_DETECT, +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_DataDelay_0_BIT, +#else + Mcbsp_DataDelay_1_BIT, +#endif + Mcbsp_Compand_OFF_MSB_FIRST, + Mcbsp_BitReversal_DISABLE, + Mcbsp_IntMode_ON_SYNCERR, + Mcbsp_RxJust_RZF, /* Dont care for TX */ + Mcbsp_DxEna_OFF +}; +/**< clock setup for the TX section */ +Mcbsp_ClkSetup mcbspClkConfigTx = +{ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_FsClkMode_EXTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_EXTERNAL, +#else + Mcbsp_FsClkMode_INTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_INTERNAL, +#endif + Mcbsp_FsPol_ACTIVE_HIGH, + Mcbsp_ClkPol_RISING_EDGE +}; + +/**< clock setup for the RX section */ +Mcbsp_ClkSetup mcbspClkConfigRx = +{ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_FsClkMode_EXTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_EXTERNAL, +#else + Mcbsp_FsClkMode_INTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_INTERNAL, +#endif + Mcbsp_FsPol_ACTIVE_HIGH, + Mcbsp_ClkPol_FALLING_EDGE +}; + +/**< Multi channel setup */ +Mcbsp_McrSetup mcbspMultiChanCtrl = +{ + Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED, + Mcbsp_PartitionMode_CHAN_0_15, + Mcbsp_PartitionMode_CHAN_16_31, + Mcbsp_PartitionMode_2 +}; + + +Mcbsp_ChanParams mcbspChanparamTx = +{ + Mcbsp_WordLength_8, /* wordlength configured */ + &loopTxJob[0], /* loop job buffer internal */ + 8, /* user loopjob length */ + mcbsp_GblErrCallback, /* global error callback */ + NULL, /* edma Handle */ + 1, /* EDMA event queue */ + 8, /* hwi number */ + Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED, + TRUE, /* FIFO mode enabled */ + &mcbspChanConfigTx, /* channel configuration */ + &mcbspClkConfigTx, /* clock configuration */ + &mcbspMultiChanCtrl, /* multi channel control */ + 0x7531, /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */ + 0x00, + 0x00, + 0x00, + NUM_OF_ENABLED_CHANNELS /* Total number of channels enabled*/ +}; + +Mcbsp_ChanParams mcbspChanparamRx = +{ + Mcbsp_WordLength_8, /* wordlength configured */ + &loopRxJob[0], /* loop job buffer internal */ + 8, /* user loopjob length */ + mcbsp_GblErrCallback, /* global error callback */ + NULL, /* edma Handle */ + 1, /* EDMA event queue */ + 8, /* hwi number */ + Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED, + TRUE, /* FIFO mode enabled */ + &mcbspChanConfigRx, /* channel configuration */ + &mcbspClkConfigRx, /* clock configuration */ + &mcbspMultiChanCtrl, /* multi channel control */ + 0x7531, /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */ + 0x00, + 0x00, + 0x00, + NUM_OF_ENABLED_CHANNELS /* Total number of channels enabled*/ +}; + + +/* ========================================================================== */ +/* FUNCTION DEFINITIONS */ +/* ========================================================================== */ + +/* + * This is the application's callback function. The driver will + * call this function whenever an EDMA I/O operation is over. + * + */ +void mcbspAppCallback(void* arg, Mcbsp_IOBuf *ioBuf) +{ + int32_t mode; + int32_t *pmode = (int32_t *)arg; + + mode = *pmode; + if (mode == MCBSP_MODE_OUTPUT) + { + if(ioBuf) { + num_tx_Call_backs++; + edmaTxDone = 1; + }else + txunderflowcnt++; + } + else if (mode == MCBSP_MODE_INPUT) + { + if(ioBuf) { + num_rx_Call_backs++; + edmaRxDone = 1; + }else + rxunderflowcnt++; + }else + dummy_call_backs++; + return; +} + +/* + * This is the application's Global error callback function + */ +void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3) +{ + MCBSP_log ("Debug(Core %d): ERROR callback called SPCR: %x", coreNum, spcr_read); +} + +/* + * \brief This function demostrates the use of Mcbsp using digital loopback + * communication setup. + * + * \param None + * + * \return None + */ +void mcbspDigLpbkApp(UArg arg0, UArg arg1) +{ + /**< Mcbsp device params */ + Mcbsp_Params mcbspParams; + + /**< Queue to hold the pending packets received from the application */ + Queue_Struct txQueuePendingList, rxQueuePendingList; + /**< Queue to manage floating packets in DMA */ + Queue_Struct txQueueFloatingList, rxQueueFloatingList; + + uint32_t count = 0, tempCount = 0; + int32_t status = 0, retval = 0; + int32_t txChanMode = MCBSP_MODE_OUTPUT; + int32_t rxChanMode = MCBSP_MODE_INPUT; + uint32_t mcbspTxDone = 0, mcbspRxDone = 0; + Mcbsp_IOBuf txFrame[NUM_OF_MCBSP_FRAMES], rxFrame[NUM_OF_MCBSP_FRAMES]; + int txFrameIndex=0, rxFrameIndex=0; + int init_count=0; +#ifdef MCBSP_LOOP_PING_PONG + int pingPongIndex=0; +#endif + + /* Initialize the OSAL */ + if (Osal_dataBufferInitMemory(BUFSIZE) < 0) + { + MCBSP_log ("Debug(Core %d): Error: Unable to initialize the OSAL. \n", coreNum); + return; + } + + /* update EDMA3 handle to channel parameters */ + mcbspChanparamTx.edmaHandle = hEdma[0]; + mcbspChanparamRx.edmaHandle = hEdma[0]; + + /* create the pending and floating queue for the TX channel */ + Queue_construct(&txQueuePendingList, NULL); + Queue_construct(&txQueueFloatingList, NULL); + + /* create the pending and floating queue for the RX channel */ + Queue_construct(&rxQueuePendingList, NULL); + Queue_construct(&rxQueueFloatingList, NULL); + + + mcbspParams = Mcbsp_PARAMS; + mcbspParams.txQPendingList = &txQueuePendingList; + mcbspParams.txQFloatingList = &txQueueFloatingList; + mcbspParams.rxQPendingList = &rxQueuePendingList; + mcbspParams.rxQFloatingList = &rxQueueFloatingList; + + + /* Bind the driver instance with device instance */ + status = mcbspBindDev(&hMcbspDev, coreNum, &mcbspParams); + + if (status != MCBSP_STATUS_COMPLETED) + { + MCBSP_log ("Debug(Core %d): MCBSP LLD Bind Device Failed\n", coreNum); + return; + } + + /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */ + if(mcbspChanparamRx.userLoopJobBuffer) + mcbspChanparamRx.userLoopJobBuffer = (void *)Mcbsp_osalLocal2Global(mcbspChanparamRx.userLoopJobBuffer); + + /* Create a RX channel for receiving */ + status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum); + return; + } + + /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */ + if(mcbspChanparamTx.userLoopJobBuffer) + mcbspChanparamTx.userLoopJobBuffer = Mcbsp_osalLocal2Global(mcbspChanparamTx.userLoopJobBuffer); + + /* Create a TX channel for the transmission */ + status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum); + return; + } + + /* Register mcbsp interrupts */ + //McbspRcvInterrupt_init(hMcbspRxChan); + //McbspXmtInterrupt_init(hMcbspTxChan); + + /* create the buffers required for the TX and RX operations */ + for (count = 0; count < (NUM_BUFS); count++) + { + bufTx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + bufRx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + + if (bufTx[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Tx Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + if (bufRx[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Rx Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* create the ping pong buffers required for the TX and RX operations */ + for (count = 0; count < (NUM_BUFS); count++) + { + bufRxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + bufTxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + + if (bufTxPingPong[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Tx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + if (bufRxPingPong[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Rx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + } +#endif + /* Fill the buffers with known data and transmit the same and + check if the same pattern is received */ + for (count = 0; count < (NUM_BUFS); count++) + { + memset((uint8_t *)bufTx[count], 0, BUFSIZE); + for (tempCount = 0; tempCount < BUFSIZE; tempCount++) + { + ((uint8_t *)bufTx[count])[tempCount] = (tempCount % 0x100); + } + } + MCBSP_log ("Debug(Core %d): If required to restart set debugCommand variable to %d\n", coreNum, DEBUG_COMMAND_RESTART_CHANNELS); + +restart_mcbsp_point: + txFrameIndex=0; + rxFrameIndex=0; + init_count=0; +#ifdef MCBSP_EXTERNAL_CLOCK + /* Initial loading of ping ping buffers */ + for(init_count =0 ; init_count < INIT_SUBMIT_Q_CNT; init_count++) + { +#ifdef MCBSP_LOOP_PING_PONG + memset((uint8_t *)bufRxPingPong[init_count], 0, BUFSIZE); + + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRxPingPong[init_count]; +#else + memset((uint8_t *)bufRx[init_count], 0, BUFSIZE); + + + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRx[init_count]; +#endif + + rxFrame[rxFrameIndex].size = BUFSIZE; + rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan; + rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED; + rxFrame[rxFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, init_count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, init_count); +#endif + } + rxFrameIndex++; + rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex; + + rxSubmitCount++; + + /* TX frame processing */ + txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE; +#ifdef MCBSP_LOOP_PING_PONG + txFrame[txFrameIndex].addr = (void*)bufTxPingPong[init_count]; +#else + txFrame[txFrameIndex].addr = (void*)bufTx[init_count]; +#endif + txFrame[txFrameIndex].size = BUFSIZE; + txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan; + txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED; + txFrame[txFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: TX buffer #%d submission FAILED\n", coreNum, init_count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): TX buffer #%d submission is submitted to MCBSP driver\n", coreNum, init_count); +#endif + } + txFrameIndex++; + txFrameIndex = (txFrameIndex >=(NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex; + + txSubmitCount++; + } + + /* Wait for TX and RX processing to complete */ + while (1) + { + if (edmaTxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Iteration-%d frames are transmitted to TX path\n", coreNum, count); +#endif + edmaTxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 1; + } + if (edmaRxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Iteration-%d frames are received from RX path\n", coreNum, count); +#endif + edmaRxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 1; + } + if ((mcbspTxDone == 1) && (mcbspRxDone == 1)) + { + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + break; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* Change ping Pong Index */ + init_count=0; +#endif +#endif /* MCBSP_EXTERNAL_CLOCK */ + + /* Start main loop to iterate through frames */ + while(debugVar) + { + /* submit frames to the driver */ + for (count = init_count; count < NUM_BUFS; count++) + { +#ifdef MCBSP_EXTERNAL_CLOCK +/* With External clock the data coming from the RX side is copied to loop back to the Tx side */ + memcpy((uint8_t *)bufTx[count], (uint8_t *)bufRx[count], BUFSIZE); +#endif +#ifdef MCBSP_LOOP_PING_PONG + memset((uint8_t *)bufRxPingPong[pingPongIndex], 0, BUFSIZE); +#else + memset((uint8_t *)bufRx[count], 0, BUFSIZE); + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRx[count]; + rxFrame[rxFrameIndex].size = BUFSIZE; + rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan; + rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED; + rxFrame[rxFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, count); +#endif + } + rxFrameIndex++; + rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex; +#endif + rxSubmitCount++; +#ifdef MCBSP_LOOP_PING_PONG + /* Copy buffer from buffer to ping pong buffer*/ + memcpy((uint8_t *)bufTxPingPong[pingPongIndex], (uint8_t *)bufTx[count],BUFSIZE); +#else + /* TX frame processing */ + txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE; + txFrame[txFrameIndex].addr = (void*)bufTx[count]; + txFrame[txFrameIndex].size = BUFSIZE; + txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan; + txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED; + txFrame[txFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: TX buffer #%d submission FAILED\n", coreNum, count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): TX buffer #%d is submitted to MCBSP driver\n", coreNum, count); +#endif + } + txFrameIndex++; + txFrameIndex = (txFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex; +#endif + txSubmitCount++; + + /* Wait for TX and RX processing to complete */ + while (1) + { + if (edmaTxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Buffer #-%d is transmitted to TX path\n", coreNum, count); +#endif + edmaTxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 1; + } + if (edmaRxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Buffer #-%d is received from RX path\n", coreNum, count); +#endif + edmaRxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 1; + } + if ((mcbspTxDone == 1) && (mcbspRxDone == 1)) + { + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + break; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* Change ping Pong Index */ + pingPongIndex=(pingPongIndex)?0:1; + + /* Copy buffer from buffer to other buffer*/ + memcpy((void*)bufRx[count], (uint8_t *)bufRxPingPong[pingPongIndex],BUFSIZE); +#endif + /* compare buffer contents */ + for (tempCount = 0; tempCount < BUFSIZE; tempCount++) + { + if (((char *)bufTx[count])[tempCount] != ((char *)bufRx[count])[tempCount]) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log("Debug(Core %d): Error: TX and RX frame data DOES NOT match in Buffer #-%d\n", + coreNum, count); + MCBSP_log("Debug(Core %d): Error: Buffer index = %d, Tx data = %d, Rx data = %d\n", coreNum, + tempCount, ((char *)bufTx[count])[tempCount], ((char *)bufRx[count])[tempCount]); +#endif + errBuffCount++; + break; + } + } + if (tempCount >= BUFSIZE) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log("Debug(Core %d): TX and RX frames data match in iteration-%d !!!\n", coreNum, count); +#endif + } + } + init_count=0; + num_iterations++; +#ifndef MCBSP_EXTERNAL_CLOCK + if(num_iterations >= NUM_OF_ITERATIONS) + break; +#endif + switch(debugCommand) + { + case DEBUG_COMMAND_RESTART_CHANNELS: + debugCommand=0; + /* Close channel and reopen */ + /* Delete RX channel */ + status = mcbspDeleteChan(hMcbspRxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum); + return; + } + + /* Delete TX channel*/ + status = mcbspDeleteChan(hMcbspTxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum); + return; + } + /* Create a RX channel for receiving */ + status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum); + return; + } + + /* Create a TX channel for the transmission */ + status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum); + return; + } + edmaTxDone = 0; /* Reset for next iteration */ + edmaRxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + goto restart_mcbsp_point; + + default: + debugCommand=0; + break; + + } + + } + + if ((errBuffCount == 0 ) & (retval ==0)) + { + MCBSP_log("Debug(Core %d): MCBSP Digital Loopback Application completed successfully : "\ + "Num iterations %d Num buffers per iteration %d!!!\n", + coreNum, num_iterations, NUM_BUFS); + MCBSP_log("\n All tests have passed \n"); + } + else + { + MCBSP_log("Debug(Core %d): MCBSP Digital Loopback application FAILED : "\ + "Num iterations %d Num buffers per iteration %d Failed buffers %d!!!\n", + coreNum, num_iterations, NUM_BUFS, errBuffCount); + } + + /* Delete RX channel */ + status = mcbspDeleteChan(hMcbspRxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum); + return; + } + + /* Delete TX channel*/ + status = mcbspDeleteChan(hMcbspTxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum); + return; + } + return; +} + +/* + * \brief Void main(Void) + * + * Main function of the sample application. This function calls the + * function to configure the mcbsp instance. + * + * \param None + * + * \return None + */ +#include "ti/sysbios/hal/Cache.h" + +Void main(Void) +{ + Task_Params taskParams; + EDMA3_DRV_Result edmaResult = 0; +#ifdef SIMULATOR_SUPPORT + uint8_t uchValue, uchReadValue; +#endif + + Board_initCfg arg = BOARD_INIT_MODULE_CLOCK | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_UART_STDIO; + Board_init(arg); + + /* Get the core number. */ + coreNum = 0; //CSL_chipReadReg (CSL_CHIP_DNUM); + +#ifdef SIMULATOR_SUPPORT +#warn MCBSP Digital Loopback example is not supported on SIMULATOR !!! + MCBSP_log ("MCBSP Digital Loopback example is not supported on SIMULATOR. Exiting!\n"); + return; +#else + MCBSP_log ("Debug(Core %d): Running MCBSP Digital Loopback example on the DEVICE\n", coreNum); +#endif + + /* Initialize the system only if the core was configured to do so. */ + if (coreNum == CORE_SYS_INIT) + { +#if 0 + MCBSP_log ("Debug(Core %d): System Initialization for MCBSP\n", coreNum); + /* Read FPGA register */ + if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum); + return; + } + /* Clear field for configuration */ + uchValue = (uchReadValue & (~0x3)); +#ifndef PLATFORM_FPGA_MCBSP_AMC_EN + uchValue |= 0x3; +#endif + /* Drive McBSP_AMC_EN# high. Output SLCLKs, TxCLKs, RxCLKs, FSTs, FSRs as Hi-Z. + * These clocks and syncs are tri-stated and McBSP is accessed over 80-pin header */ + if (0 != (platform_fpgaWriteConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, (uchValue)))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register WRITE failed \n", coreNum); + return; + } + + /* DEBUG: Verify if FPGA register is configured correctly */ + if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum); + return; + } + + if (uchValue != uchReadValue) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register setting failed \n", coreNum); + return; + } + else + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register is set to %d \n", coreNum, uchValue); + } +#endif + /* MCBSP Driver Initialization: This should always be called before + * invoking the MCBSP Driver. */ + mcbspInit(); + + /* Device Specific MCBSP Initializations */ + McbspDevice_init(); + + /* MCBSP Driver is operational at this time. */ + MCBSP_log ("Debug(Core %d): MCBSP Driver Initialization Done\n", coreNum); + + /* Write to the SHARED memory location at this point in time. The other cores cannot execute + * till the MCBSP Driver is up and running. */ + isMCBSPInitialized[0] = 1; + + /* The MCBSP IP block has been initialized. We need to writeback the cache here because it will + * ensure that the rest of the cores which are waiting for MCBSP to be initialized would now be + * woken up. */ + //CACHE_wbL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT); + Cache_wb ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH,0x7fff, 1); + } + else + { + /* All other cores need to wait for the MCBSP to be initialized before they proceed with the test. */ + MCBSP_log ("Debug(Core %d): Waiting for MCBSP to be initialized.\n", coreNum); + + /* All other cores loop around forever till the MCBSP is up and running. + * We need to invalidate the cache so that we always read this from the memory. */ + while (isMCBSPInitialized[0] == 0) + //CACHE_invL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT); + Cache_inv ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH, 0x7fff, 1); + + + MCBSP_log ("Debug(Core %d): MCBSP can now be used.\n", coreNum); + } + + /* Initialize EDMA3 library */ + hEdma[0] = edma3init(0, &edmaResult); + + if (edmaResult != EDMA3_DRV_SOK) + { + /* Report EDMA Error */ + MCBSP_log("Debug(Core %d): EDMA Driver Initialization FAILED\n", coreNum); + } + else + { + MCBSP_log("Debug(Core %d): EDMA Driver Initialization Done\n", coreNum); + } + + /* Create the Digital Loopback Application Task */ + Task_Params_init(&taskParams); + Task_create(mcbspDigLpbkApp, &taskParams, NULL); + + /* Start BIOS */ + BIOS_start(); + + return; +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg new file mode 100644 index 000000000..44dedf67b --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg @@ -0,0 +1,78 @@ +/* + * Copyright 2012-2018 by Texas Instruments Incorporated. + * + * All rights reserved. Property of Texas Instruments Incorporated. + * Restricted rights to use, duplicate or disclose this code are + * granted through contract. + * + */ + +/* THIS FILE WAS GENERATED BY ti.sysbios.genx */ + +/* + * ======== mcbspMasterDigLpbk.cfg ======== + * + */ + +/* Load and use the required BIOS packages */ +var BIOS = xdc.useModule('ti.sysbios.BIOS'); +var Task = xdc.useModule('ti.sysbios.knl.Task'); +var cache = xdc.useModule('ti.sysbios.hal.Cache'); +var Idle = xdc.useModule('ti.sysbios.knl.Idle'); +var Queue = xdc.useModule('ti.sysbios.knl.Queue'); +var ECM = xdc.useModule('ti.sysbios.family.c64p.EventCombiner'); +//var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc'); +var Memory = xdc.useModule('xdc.runtime.Memory'); +var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); + +/* Load and use the System Package */ +var System = xdc.useModule('xdc.runtime.System'); +var SysStd = xdc.useModule('xdc.runtime.SysStd'); + +/* Create a default system heap using ti.bios.HeapMem. */ +var heapMemParams1 = new HeapMem.Params; +heapMemParams1.size = 32768; +heapMemParams1.sectionName = "systemHeap"; +Program.global.heap0 = HeapMem.create(heapMemParams1); + +/* This is the default memory heap. */ +Memory.defaultHeapInstance = Program.global.heap0; + +/* + * Create and install logger for the whole system. + * Enable Event Groups here and registering of ISR for specific GEM INTC is done + * using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs + */ +ECM.eventGroupHwiNum[0] = 7; +ECM.eventGroupHwiNum[1] = 8; +ECM.eventGroupHwiNum[2] = 9; +ECM.eventGroupHwiNum[3] = 10; + +/* Load and use the mcbsp, EDMA, PlatformLib etc. packages */ +var Edma = xdc.loadPackage('ti.sdo.edma3.drv'); + +var devType = "omapl138" +var mcbsp = xdc.useModule('ti.drv.mcbsp.Settings'); +mcbsp.deviceType = devType; + +/* Load the uart package */ +var Uart = xdc.loadPackage('ti.drv.uart'); +Uart.Settings.socType = devType; + +var Csl = xdc.useModule('ti.csl.Settings'); +Csl.deviceType = devType; +Csl.libProfile = "release"; + +/* Load the OSAL package */ +var osType = "tirtos" +var Osal = xdc.useModule('ti.osal.Settings'); +Osal.osType = osType; +Osal.socType = devType; + +/* Load the Board package and set the board name */ +var Board = xdc.loadPackage('ti.board'); +Board.Settings.boardName = "lcdkOMAPL138"; + +/* Circular buffer size for System_printf() */ +System.SupportProxy = SysStd; + diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd new file mode 100644 index 000000000..6021dd060 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd @@ -0,0 +1,9 @@ +SECTIONS +{ + .init_array: load >> IRAM + .mcbsp: load >> DDR + .mcbspSharedMem: load >> DDR + platform_lib: load >> DDR + systemHeap: load >> IRAM +} + diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c new file mode 100644 index 000000000..6cda4227c --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c @@ -0,0 +1,639 @@ +/** + * @file mcbspMasterDigLpbk_osal.c + * + * @brief + * This is the OS abstraction layer and is used by the MCBSP + * driver for the MCBSP Example Digital Loopback Application. + * + * \par + * ============================================================================ + * @n (C) Copyright 2012, Texas Instruments, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * \par +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if 0 +/* CSL Include Files */ +#include +#include +#include +#include +#endif +/* IPC includes */ +#include +#include +#include +#include + +/********************************************************************** + ************************** Local Definitions ************************* + **********************************************************************/ + +#define MCBSP_HW_SEM 1 +#define PLATFORM_SPI_HW_SEM 2 /**< SPI BUS arbitration - Used by platform library */ + +#ifdef MCBSP_LOOP_PING_PONG +#define MAX_MEM_MGR_ENTRIES 8 +#else +#define MAX_MEM_MGR_ENTRIES 4 +#endif + +typedef struct MEM_MGMT_ENTRY +{ + uint8_t* ptrMemory; + uint32_t isFree; +}MEM_MGMT_ENTRY; + +MEM_MGMT_ENTRY gDataBufferMemMgr[MAX_MEM_MGR_ENTRIES]; +int32_t gDataBufferMemMgrMaxSize = 0; + +/********************************************************************** + ************************** Global Variables ************************** + **********************************************************************/ +UInt32 malloc_counter = 0; +UInt32 free_counter = 0; + +/********************************************************************** + ************************** Extern Definitions ************************ + **********************************************************************/ + + +/********************************************************************** + **************************** OSAL Functions ************************** + **********************************************************************/ + +/** + * @b Description + * @n + * Utility function which converts a local address to global. + * + * @param[in] addr + * Local address to be converted + * + * @retval + * Global Address + */ +void *Osal_local2Global (void *addr) +{ + UInt32 corenum; + + /* Get the core number. */ + corenum = 0;//CSL_chipReadReg(CSL_CHIP_DNUM); + return addr; + + if(((UInt32)addr & 0xff000000) == 0) { + /* Compute the global address. */ + return ((void *)((UInt32)(addr) + (0x10000000 + (corenum*0x1000000)))); + } + else + return(addr); +} + +/** + * @b Description + * @n + * The function is used to allocate a memory block of the specified size. + * + * @param[in] numBytes + * Number of bytes to be allocated. + * + * @retval + * Allocated block address + */ +Void* Osal_mcbspMalloc(UInt32 numBytes) +{ + Error_Block errorBlock; + Void* ptr; + + /* Increment the allocation counter. */ + malloc_counter++; + + /* Allocate the memory. */ + ptr = Memory_alloc(NULL, numBytes, 0, &errorBlock); + + /* Return the allocated memory block. */ + return ptr; +} + +/** + * @b Description + * @n + * The function is used to clean up a specific memory block and is called + * from the MCBSP Driver. + * + * @param[in] ptr + * Pointer to the memory block to be cleaned up. + * @param[in] size + * Size of the memory block being cleaned up. + * + * @retval + * Not Applicable + */ +Void Osal_mcbspFree (Void* ptr, UInt32 size) +{ + /* Increment the free counter. */ + free_counter++; + Memory_free(NULL, ptr, size); +} + +/** + * @b Description + * @n + * The function is used to allocate a block of memory for all the data buffer + * operations. This function is called by the application. + * + * @param[in] numBuffers + * Number of data buffers + * @param[in] dataBufferSize + * Size of each data buffer + * + * @retval + * Success - 0 + * @retval + * Error - <0 + */ +int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize) +{ + Error_Block errorBlock; + uint8_t* ptrMemory; + uint32_t index; + + /* Allocate memory for all the data buffers */ + ptrMemory = (uint8_t*)Memory_alloc(NULL, MAX_MEM_MGR_ENTRIES*dataBufferSize, 128, &errorBlock); + if (ptrMemory == NULL) + return -1; + + /* Convert to a global address */ + ptrMemory = Osal_local2Global(ptrMemory); + + /* Now we chop up the memory and add it to the memory manager. */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Populate the data memory management entry. */ + gDataBufferMemMgr[index].isFree = 1; + gDataBufferMemMgr[index].ptrMemory = ptrMemory; + + /* Increment the memory to the next address */ + ptrMemory = ptrMemory + dataBufferSize; + } + + /* Remember the memory buffer size */ + gDataBufferMemMgrMaxSize = dataBufferSize; + + /* Memory Manager has been created. */ + return 0; +} + +/** + * @b Description + * @n + * The function is used to allocate a data buffer of the specified + * size. Data buffers should always be allocated from the global + * address space. + * + * @param[in] numBytes + * Number of bytes to be allocated. + * + * @retval + * Allocated block address + */ +Void* Osal_mcbspDataBufferMalloc(UInt32 numBytes) +{ + uint32_t index; + void* ptrMemory = NULL; + + /* Basic Validation: Ensure that the memory size requested is within range. */ + if (numBytes > gDataBufferMemMgrMaxSize) + return NULL; + + /* Increment the allocation counter. */ + malloc_counter++; + + /* Lock out interrupts */ + Hwi_disable(); + + /* Cycle through for a free entry. */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Check if the entry is free or not? */ + if (gDataBufferMemMgr[index].isFree == 1) + { + /* Entry was free. We can use it. */ + ptrMemory = gDataBufferMemMgr[index].ptrMemory; + + /* Mark the entry as used. */ + gDataBufferMemMgr[index].isFree = 0; + + /* We have found a match. */ + break; + } + } + + /* Unlock interrupts. */ + Hwi_enable(); + + /* Return the allocated memory. */ + return ptrMemory; +} + +/** + * @b Description + * @n + * The function is used to clean up a previously allocated data buffer + * block. All data buffers are in the global address space + * + * @param[in] ptr + * Pointer to the data buffer block to be cleaned up + * @param[in] size + * Size of the data buffer + * + * @retval + * Not Applicable + */ +void Osal_mcbspDataBufferFree(void* ptr, uint32_t numBytes) +{ + uint32_t index; + + /* Increment the free counter. */ + free_counter++; + + /* Lock out interrupts */ + Hwi_disable(); + + /* Cycle through and clean up */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Check if the entry is free or not? */ + if (gDataBufferMemMgr[index].ptrMemory == (uint8_t*)ptr) + { + /* Mark the entry as free. */ + gDataBufferMemMgr[index].isFree = 1; + + /* We have found a match. */ + break; + } + } + + /* Unlock interrupts. */ + Hwi_enable(); + return; +} + +/** + * @b Description + * @n + * The function is the MCBSP OSAL Logging API which logs + * the messages on the console. + * + * @param[in] fmt + * Formatted String. + * + * @retval + * Not Applicable + */ +Void Osal_mcbspLog( String fmt, ... ) +{ +} + +/** + * @b Description + * @n + * The function is used to create a critical section. + * + * @retval + * Semaphore Handle created + */ +Void* Osal_mcbspCreateSem(Void) +{ + return (Void*)Semaphore_create(0, NULL, NULL); +} + +/** + * @b Description + * @n + * The function is used to delete a critical section. + * + * @param[in] semHandle + * Semaphore handle to be deleted + * + * @retval + * Not Applicable + */ +Void Osal_mcbspDeleteSem(Void* semHandle) +{ + Semaphore_delete(semHandle); +} + +/** + * @b Description + * @n + * The function is used to pend on a semaphore + * + * @param[in] semHandle + * Semaphore handle on which the API will pend + * + * @retval + * Not Applicable + */ +Void Osal_mcbspPendSem(Void* semHandle) +{ + Semaphore_pend(semHandle, BIOS_WAIT_FOREVER); +} + +/** + * @b Description + * @n + * The function is used to post a semaphore + * + * @param[in] semHandle + * Semaphore handle which will be posted + * + * @retval + * Not Applicable + */ +Void Osal_mcbspPostSem(Void* semHandle) +{ + Semaphore_post(semHandle); +} + +/** + * @b Description + * @n + * This is the Multicore OSAL Implementation to protect the driver shared + * resources across multiple cores. + * + * @retval + * Semaphore Opaque Handle + */ +void* Osal_mcbspEnterMultipleCoreCriticalSection(void) +{ + /* Get the hardware semaphore */ + // while ((CSL_semAcquireDirect (MCBSP_HW_SEM)) == 0); + return NULL; +} + +/** + * @b Description + * @n + * The function is called to end the critical section which was protecting + * shared resources from access across multiple cores. + * + * @param[in] critSectHandle + * Semaphore opaque handle. + * + * @retval + * None + */ +Void Osal_mcbspExitMultipleCoreCriticalSection(Void* critSectHandle) +{ + //CSL_semReleaseSemaphore (MCBSP_HW_SEM); +} + +/** + * @b Description + * @n + * The function is used to provide critical section to prevent access of shared + * resources from single core and multiple threads. + * + * @param[in] drvHandle + * Driver Handle which needs critical section to protect its resources. + * + * @retval + * Opaque handle + */ +Void* Osal_mcbspEnterSingleCoreCriticalSection() +{ + /* Disable interrupts */ + return (Void*)Hwi_disable(); +} + +/** + * @b Description + * @n + * The function is called to end the critical section access of shared resources + * from single cores. + * + * @param[in] drvHandle + * Driver Handle which needed critical section to protect its resources. + * @param[in] critSectHandle + * Opaque handle retreived when the Single Core Protection Enter API was called + * + * @retval + * Not Applicable. + */ +Void Osal_mcbspExitSingleCoreCriticalSection(Void* critSectHandle) +{ + /* Driver Managed Configuration: We need to enable interrupts. */ + Hwi_enable(); +} + +/** + * @b Description + * @n + * The function is used by the MCBSP driver to indicate that + * its about to access a block of memory and we need to ensure + * that the cache contents for this block are invalidated before + * we try and use it. + * + * @param[in] ptr + * Pointer to the buffer which is being accessed + * @param[in] size + * Size of the buffer which is to be accessed. + * + * @retval + * None + */ +#include "ti/sysbios/hal/Cache.h" +void Osal_mcbspBeginMemAccess(void* ptr, uint32_t size) +{ + UInt key; + + /* Disable Interrupts */ + key = Hwi_disable(); + + /* Cleanup the prefetch buffer also. */ + //CSL_XMC_invalidatePrefetchBuffer(); + + /* Invalidate the cache. */ + //CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT); + + Cache_inv ((void *) ptr,size, 0x7fff, 1); + + /* Reenable Interrupts. */ + Hwi_restore(key); +} + +/** + * @b Description + * @n + * The function is used by the MCBSP driver to indicate that its + * ending access to a block of memory. We need to ensure that the + * contents of the cache are written back to the actual memory. + * + * @param[in] ptr + * Pointer to the buffer + * @param[in] size + * Size of the buffer + * + * @retval + * None + */ +void Osal_mcbspEndMemAccess(void* ptr, uint32_t size) +{ + UInt key; + + /* Disable Interrupts */ + key = Hwi_disable(); + + /* Writeback the cache. */ + //CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT); + Cache_wb ((void *) ptr,size, 0x7fff, 1); + /* Reenable Interrupts. */ + Hwi_restore(key); +} + +/** + * @brief The function is used by the MCBSP driver to test for an + * empty queue. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n TRUE - If the queue is empty + */ +Bool Osal_mcbspQueueEmpty(void* handle) +{ + return Queue_empty(handle); +} + +/** + * @brief The macro is used by the MCBSP driver to get an + * element from the front of queue. The function + * removes the element from the front of queue and + * returns a pointer to it. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n Handle (pointer) to former first element + */ +void* Osal_mcbspQueueGet(void* handle) +{ + return Queue_get(handle); +} + +/** + * @brief The macro is used by the MCBSP driver to put an + * element at the end of queue. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * @n elem - Pointer to new queue element + * + * Return Value + * @n None + */ +void Osal_mcbspQueuePut(void* handle, Mcbsp_QueueElem* elem) +{ + Queue_put(handle, (Queue_Elem *)elem); + return; +} + +/** + * @brief The macro is used by the MCBSP driver to wait 'n' + * bit clocks to ensure proper synchronization internally. + * + * Parameter + * @n nticks - Number of bit clocks to wait + * + * Return Value + * @n None + */ +void Osal_mcbspWaitNBitClocks(uint32_t nticks) +{ + Task_sleep(nticks); + return; +} + +/* OSAL functions for Platform Library */ +uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment) +{ + return malloc(num_bytes); +} + +void Osal_platformFree (uint8_t *dataPtr, uint32_t num_bytes) +{ + /* Free up the memory */ + if (dataPtr) + { + free(dataPtr); + } +} + +void Osal_platformSpiCsEnter(void) +{ + /* Get the hardware semaphore. + * + * Acquire Multi core CPPI synchronization lock + */ + //while ((CSL_semAcquireDirect (PLATFORM_SPI_HW_SEM)) == 0); + + return; +} + +void Osal_platformSpiCsExit (void) +{ + /* Release the hardware semaphore + * + * Release multi-core lock. + */ + //CSL_semReleaseSemaphore (PLATFORM_SPI_HW_SEM); + + return; +} diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_c6657_cfg.c b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_c6657_cfg.c new file mode 100644 index 000000000..8b18b501b --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_c6657_cfg.c @@ -0,0 +1,692 @@ +/* + * sample_c6657_cfg.c + * + * Platform specific EDMA3 hardware related information like number of transfer + * controllers, various interrupt ids etc. It is used while interrupts + * enabling / disabling. It needs to be ported for different SoCs. + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ +#include +#include + +/* Number of EDMA3 controllers present in the system */ +#define NUM_EDMA3_INSTANCES 1u +const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES; + +/* Number of DSPs present in the system */ +#define NUM_DSPS 2u +//const unsigned int numDsps = NUM_DSPS; + +#define CGEM_REG_START (0x01800000) + + +extern cregister volatile unsigned int DNUM; + +#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff)) + + +/* Determine the processor id by reading DNUM register. */ +unsigned short determineProcId() + { + volatile unsigned int *addr; + unsigned int core_no; + + /* Identify the core number */ + addr = (unsigned int *)(CGEM_REG_START+0x40000); + core_no = ((*addr) & 0x000F0000)>>16; + + return core_no; + } + +signed char* getGlobalAddr(signed char* addr) +{ + if (((unsigned int)addr & (unsigned int)0xFF000000) != 0) + { + return (addr); /* The address is already a global address */ + } + + return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr))); +} +/** Whether global configuration required for EDMA3 or not. + * This configuration should be done only once for the EDMA3 hardware by + * any one of the masters (i.e. DSPs). + * It can be changed depending on the use-case. + */ +unsigned int gblCfgReqdArray [NUM_DSPS] = { + 0, /* DSP#0 is Master, will do the global init */ + 1, /* DSP#1 is Slave, will not do the global init */ + }; + +unsigned short isGblConfigRequired(unsigned int dspNum) + { + return gblCfgReqdArray[dspNum]; + } + +/* Semaphore handles */ +EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; + + +/* Variable which will be used internally for referring number of Event Queues. */ +unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {4u}; + +/* Variable which will be used internally for referring number of TCs. */ +unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {4u}; + +/** + * Variable which will be used internally for referring transfer completion + * interrupt. Completion interrupts for all the shadow regions and all the + * EDMA3 controllers are captured since it is a multi-DSP platform. + */ +unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { + { + 24u, 25u, 26u, 27u, + 28u, 29u, 30u, 31u, + }, + }; + +/** + * Variable which will be used internally for referring channel controller's + * error interrupt. + */ +unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {16u}; + +/** + * Variable which will be used internally for referring transfer controllers' + * error interrupts. + */ +unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = { + { + 18u, 19u, 20u, 21u, + 0u, 0u, 0u, 0u, + }, + }; + +/* Driver Object Initialization Configuration */ +EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = + { + { + /* EDMA3 INSTANCE# 0 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 64u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 64u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 512u, + /** Total number of Event Queues in the EDMA3 Controller */ + 4u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ + 4u, + /** Number of Regions on this EDMA3 controller */ + 8u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 1u, + + /** Existence of memory protection feature */ + 1u, + + /** Global Register Region of CC Registers */ + (void *)0x02740000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x02790000u, + (void *)0x02798000u, + (void *)0x027A0000u, + (void *)0x027A8000u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + 24u, + /** Interrupt no. for CC Error */ + 16u, + /** Interrupt no. for TCs Error */ + { + 18u, + 19u, + 20u, + 21u, + 0u, + 0u, + 0u, + 0u, + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 16u, + 16u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 64u, + 64u, + 64u, + 64u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, + 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u, + 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, + 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + 0xFFFFFFFFu, + 0xFFFFFFFFu + } + }, + }; + +EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = + { + /* EDMA3 INSTANCE# 0 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFFFFFFFFu}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFFFFFFFFu}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 287 256 319 288 351 320 383 352 */ + 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 415 384 447 416 479 448 511 480 */ + 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFFFFFFFFu}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFFFFFFFFu}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + }, + }; +/** + * Variable which will be used internally for referring mcbsp Xmt + * interrupt. + */ +unsigned int ccMcbspXmtInt[CSL_MCBSP_PER_CNT] = { + CSL_INTC0_XINT0, + CSL_INTC0_XINT1 + }; +/** + * Variable which will be used internally for referring mcbsp Recv + * interrupt. + */ +unsigned int ccMcbspRcvInt[CSL_MCBSP_PER_CNT] = { + CSL_INTC0_RINT0, + CSL_INTC0_RINT1 + }; +/* End of File */ diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_c6657_int_reg.c b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_c6657_int_reg.c new file mode 100644 index 000000000..a2a36bada --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_c6657_int_reg.c @@ -0,0 +1,228 @@ +/* + * sample_c6657_int_reg.c + * + * Platform specific interrupt registration and un-registration routines. + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include +#include + +#include + +#include + +extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS]; +extern unsigned int ccErrorInt[]; +extern unsigned int tcErrorInt[][EDMA3_MAX_TC]; +extern unsigned int numEdma3Tc[]; +extern unsigned int ccMcbspXmtInt[CSL_MCBSP_PER_CNT]; +extern unsigned int ccMcbspRcvInt[CSL_MCBSP_PER_CNT]; + +void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) = + { + &lisrEdma3TC0ErrHandler0, + &lisrEdma3TC1ErrHandler0, + &lisrEdma3TC2ErrHandler0, + &lisrEdma3TC3ErrHandler0, + &lisrEdma3TC4ErrHandler0, + &lisrEdma3TC5ErrHandler0, + &lisrEdma3TC6ErrHandler0, + &lisrEdma3TC7ErrHandler0, + }; + +unsigned int hwiInterrupt = 8; + +/* Host interrupts for transfer completion */ +//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = { +unsigned int ccXferHostInt[1][2] = { + {0u, 20u}, + }; +unsigned int edma3ErrHostInt[1][2] = { + {1u, 21u}, + }; + +/* Host interrupts for Mcbsp */ +unsigned int ccMcbspHostInt[2][2] = { + {2u, 3u}, + {4u, 5u}, + }; +extern unsigned int dsp_num; + +/** To Register the ISRs with the underlying OS, if required */ +void registerEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + Int eventId = 0; /* GEM event id */ + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Transfer completion ISR */ + CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num], + lisrEdma3ComplHandler0, + edma3Id, + TRUE); + CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num], + ccXferHostInt[edma3Id][dsp_num]); + CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]); + eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]); + EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, + ccXferHostInt[edma3Id][dsp_num], TRUE); + EventCombiner_enableEvent(eventId); + + /* CC Error ISR */ + CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0, + edma3Id, TRUE); + CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id], + edma3ErrHostInt[edma3Id][dsp_num]); + /* TC Error ISR */ + while (numTc < numEdma3Tc[edma3Id]) + { + CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc], + (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]), + edma3Id, TRUE); + CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc], + edma3ErrHostInt[edma3Id][dsp_num]); + numTc++; + } + /* Enable the host interrupt which is common for both CC and TC error */ + CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]); + eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]); + EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, + edma3ErrHostInt[edma3Id][dsp_num], TRUE); + EventCombiner_enableEvent(eventId); + + Hwi_enableInterrupt(hwiInterrupt); + + /* enable the 'global' switch */ + CpIntc_enableAllHostInts(0); + + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +void unregisterEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + Int eventId = 0; /* GEM event id */ + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Transfer completion ISR */ + CpIntc_disableHostInt(0, ccXferHostInt[edma3Id][dsp_num]); + eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]); + EventCombiner_disableEvent(eventId); + + /* CC/TC Error ISR */ + CpIntc_disableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]); + eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]); + EventCombiner_disableEvent(eventId); + + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/** To Register the Xmt mcbsp interrupt with the underlying OS */ +void registerXmtMcbspInterrupt (unsigned int mcbspId, void *hChan) +{ + static UInt32 cookie = 0; + Int eventId = 0; /* GEM event id */ + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Tx Mcbsp ISR */ + CpIntc_dispatchPlug(ccMcbspXmtInt[mcbspId], + (CpIntc_FuncPtr)mcbspGblXmtIsr, + (UArg)hChan, + TRUE); + CpIntc_mapSysIntToHostInt(0, ccMcbspXmtInt[mcbspId], + ccMcbspHostInt[mcbspId][0]); + CpIntc_enableHostInt(0, ccMcbspHostInt[mcbspId][0]); + eventId = CpIntc_getEventId(ccMcbspHostInt[mcbspId][0]); + EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, + ccMcbspHostInt[mcbspId][0], TRUE); + EventCombiner_enableEvent(eventId); + + Hwi_restore(cookie); +} + +/** To Register the Xmt mcbsp interrupt with the underlying OS */ +void registerRcvMcbspInterrupt (unsigned int mcbspId, void *hChan) +{ + static UInt32 cookie = 0; + Int eventId = 0; /* GEM event id */ + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Rx Mcbsp ISR */ + CpIntc_dispatchPlug(ccMcbspRcvInt[mcbspId], + (CpIntc_FuncPtr)mcbspGblRcvIsr, + (UArg)hChan, + TRUE); + CpIntc_mapSysIntToHostInt(0, ccMcbspRcvInt[mcbspId], + ccMcbspHostInt[mcbspId][1]); + CpIntc_enableHostInt(0, ccMcbspHostInt[mcbspId][1]); + eventId = CpIntc_getEventId(ccMcbspHostInt[mcbspId][1]); + EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, + ccMcbspHostInt[mcbspId][1], TRUE); + EventCombiner_enableEvent(eventId); + /* Restore interrupts */ + Hwi_restore(cookie); +} +/** Initialize Mcbsp transmit interrupts */ +void McbspXmtInterrupt_init(void *mcbspTxChan) +{ + int i; + for(i=0; i < CSL_MCBSP_PER_CNT; i++) + { + registerXmtMcbspInterrupt(i, (void *)mcbspTxChan); + } +} +/** Initialize Mcbsp Recv interrupts */ +void McbspRcvInterrupt_init(void *mcbspRxChan) +{ + int i; + for(i=0; i < CSL_MCBSP_PER_CNT; i++) + { + registerRcvMcbspInterrupt(i, (void *)mcbspRxChan); + } +} diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_cs.c b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_cs.c new file mode 100644 index 000000000..92c20ab46 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_cs.c @@ -0,0 +1,420 @@ +/* + * sample_cs.c + * + * Sample functions showing the implementation of critical section entry/exit + * routines and various semaphore related routines (all BIOS6 depenedent). + * These implementations MUST be provided by the user / application, using the + * EDMA3 driver, for its correct functioning. + * + * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include +#include +#include + +#include "bios6_edma3_drv_sample.h" + +extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS]; +extern unsigned int ccErrorInt[]; +extern unsigned int tcErrorInt[][EDMA3_MAX_TC]; + +/** + * Shadow Region on which the executable is running. Its value is + * populated with the DSP Instance Number here in this case. + */ +extern unsigned int region_id; + +/** + * \brief EDMA3 OS Protect Entry + * + * This function saves the current state of protection in 'intState' + * variable passed by caller, if the protection level is + * EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of + * protection. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is disabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the + * Transfer Controller number whose interrupt needs to be disabled. + * + * \param level is numeric identifier of the desired degree of protection. + * \param intState is memory location where current state of protection is + * saved for future use while restoring it via edma3OsProtectExit() (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectEntry (unsigned int edma3InstanceId, + int level, unsigned int *intState) + { + if (((level == EDMA3_OS_PROTECT_INTERRUPT) + || (level == EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR)) + && (intState == NULL)) + { + return; + } + else + { + switch (level) + { + /* Disable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + *intState = Hwi_disable(); + break; + + /* Disable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_disable(); + break; + + /* Disable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_disableEvent(ccXferCompInt[edma3InstanceId][region_id]); + break; + + /* Disable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_disableEvent(ccErrorInt[edma3InstanceId]); + break; + + /* Disable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch (*intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Disable the corresponding interrupt */ + EventCombiner_disableEvent(tcErrorInt[edma3InstanceId][*intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + } + + +/** + * \brief EDMA3 OS Protect Exit + * + * This function undoes the protection enforced to original state + * as is specified by the variable 'intState' passed, if the protection + * level is EDMA3_OS_PROTECT_INTERRUPT. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is enabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the + * Transfer Controller number whose interrupt needs to be enabled. + * \param level is numeric identifier of the desired degree of protection. + * \param intState is original state of protection at time when the + * corresponding edma3OsProtectEntry() was called (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectExit (unsigned int edma3InstanceId, + int level, unsigned int intState) + { + switch (level) + { + /* Enable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + Hwi_restore(intState); + break; + + /* Enable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_enable(); + break; + + /* Enable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_enableEvent(ccXferCompInt[edma3InstanceId][region_id]); + break; + + /* Enable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_enableEvent(ccErrorInt[edma3InstanceId]); + break; + + /* Enable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch (intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Enable the corresponding interrupt */ + EventCombiner_enableEvent(tcErrorInt[edma3InstanceId][intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + + +/** + * \brief EDMA3 Cache Invalidate + * + * This function invalidates the D cache. + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr, + unsigned int num_bytes) + { + EDMA3_DRV_Result cacheInvResult = EDMA3_DRV_SOK; + + /* Verify whether the start address is cache aligned or not */ + if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u)) != 0) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n", + EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif + cacheInvResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR; + } + else + { + Cache_inv((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE); + } + + return cacheInvResult; +} + + + +/** + * \brief EDMA3 Cache Flush + * + * This function flushes (cleans) the Cache + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr, + unsigned int num_bytes) + { + EDMA3_DRV_Result cacheFlushResult = EDMA3_DRV_SOK; + + /* Verify whether the start address is cache aligned or not */ + if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u)) != 0) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n", + EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif + cacheFlushResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR; + } + else + { + Cache_wb((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE); + } + + return cacheFlushResult; +} + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 driver/RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to recieve the handle to just created + * semaphore + * \return EDMA3_DRV_SOK if succesful, else a suitable error code. + */ +EDMA3_DRV_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem) + { + EDMA3_DRV_Result semCreateResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semCreateResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + *hSem = (EDMA3_OS_Sem_Handle)Semaphore_create(initVal, semParams, NULL); + if ( (*hSem) == NULL ) + { + semCreateResult = EDMA3_DRV_E_SEMAPHORE; + } + } + + return semCreateResult; + } + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_DRV_SOK if succesful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_DRV_Result semDeleteResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semDeleteResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + Semaphore_delete((Semaphore_Handle *)&hSem); + } + + return semDeleteResult; + } + + +/** + * \brief EDMA3 OS Semaphore Take + * + * This function takes a semaphore token if available. + * If a semaphore is unavailable, it blocks currently + * running thread in wait (for specified duration) for + * a free semaphore. + * \param hSem [IN] is the handle of the specified semaphore + * \param mSecTimeout [IN] is wait time in milliseconds + * \return EDMA3_DRV_Result if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout) + { + EDMA3_DRV_Result semTakeResult = EDMA3_DRV_SOK; + unsigned short semPendResult; + + if(NULL == hSem) + { + semTakeResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + semPendResult = Semaphore_pend(hSem, mSecTimeout); + if (semPendResult == FALSE) + { + semTakeResult = EDMA3_DRV_E_SEMAPHORE; + } + } + + return semTakeResult; + } + + +/** + * \brief EDMA3 OS Semaphore Give + * + * This function gives or relinquishes an already + * acquired semaphore token + * \param hSem [IN] is the handle of the specified semaphore + * \return EDMA3_DRV_Result if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_DRV_Result semGiveResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semGiveResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + Semaphore_post(hSem); + } + + return semGiveResult; + } + +/* End of File */ + diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_init.c b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_init.c new file mode 100644 index 000000000..54fc95574 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_init.c @@ -0,0 +1,223 @@ +/* + * sample_init.c + * + * Sample Initialization for the EDMA3 Driver for BIOS 6 based applications. + * It should be MANDATORILY done once before EDMA3 usage. + * + * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include + +#include "bios6_edma3_drv_sample.h" + +/** @brief EDMA3 Driver Instance specific Semaphore handle */ +extern EDMA3_OS_Sem_Handle semHandle[]; + +/** To Register the ISRs with the underlying OS, if required. */ +extern void registerEdma3Interrupts (unsigned int edma3Id); +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +extern void unregisterEdma3Interrupts (unsigned int edma3Id); + +/* To find out the DSP# */ +extern unsigned short determineProcId(); + +/** + * To check whether the global EDMA3 configuration is required or not. + * It should be done ONCE by any of the masters present in the system. + * This function checks whether the global configuration is required by the + * current master or not. In case of many masters, it should be done only + * by one of the masters. Hence this function will return TRUE only once + * and FALSE for all other masters. + */ +extern unsigned short isGblConfigRequired(unsigned int dspNum); + +/** + * DSP instance number on which the executable is running. Its value is + * determined by reading the processor specific register DNUM. + */ +unsigned int dsp_num; + +/** + * Shadow Region on which the executable is runnig. Its value is populated + * with the DSP Instance Number here in this case. + */ +unsigned int region_id; + +/* Number of EDMA3 controllers present in the system */ +extern const unsigned int numEdma3Instances; + +/* External Global Configuration Structure */ +extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[]; + +/* External Instance Specific Configuration Structure */ +extern EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[][EDMA3_MAX_REGIONS]; + +#if defined (CHIP_TI814X) +extern EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, unsigned int edma3Id); +#endif + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 Driver and registers the + * interrupt handlers. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM; + Semaphore_Params semParams; + EDMA3_DRV_GblConfigParams *globalConfig = NULL; + EDMA3_DRV_InitConfig initCfg; + EDMA3_RM_MiscParam miscParam; + EDMA3_DRV_Handle hEdma = NULL; + + if ((edma3Id >= numEdma3Instances) || (errorCode == NULL)) + return hEdma; + + /* DSP instance number */ + dsp_num = determineProcId(); +// dsp_num = 0; /* selection of region ID */ + + globalConfig = &sampleEdma3GblCfgParams[edma3Id]; + + /* Configure it as master, if required */ + miscParam.isSlave = isGblConfigRequired(dsp_num); + edma3Result = EDMA3_DRV_create (edma3Id, globalConfig , + (void *)&miscParam); + + if (edma3Result == EDMA3_DRV_SOK) + { + /** + * Driver Object created successfully. + * Create a semaphore now for driver instance. + */ + Semaphore_Params_init(&semParams); + + initCfg.drvSemHandle = NULL; + edma3Result = edma3OsSemCreate(1, &semParams, &initCfg.drvSemHandle); + } + + if (edma3Result == EDMA3_DRV_SOK) + { + /* Save the semaphore handle for future use */ + semHandle[edma3Id] = initCfg.drvSemHandle; + + /* Driver instance specific config NULL */ + initCfg.drvInstInitConfig = NULL; + +#ifndef EDMA3_DRV_USE_DEF_RM_CFG + /* Hook for running examples with default RM config */ + /* configuration structure for the Driver */ + initCfg.drvInstInitConfig = &sampleInstInitConfig[edma3Id][dsp_num]; +#endif + + initCfg.isMaster = TRUE; + /* Choose shadow region according to the DSP# */ + initCfg.regionId = (EDMA3_RM_RegionId)dsp_num; + /*Saving the regionId for using it in the sample_cs.c file */ + region_id = (EDMA3_RM_RegionId)dsp_num; + /* Driver instance specific config NULL */ + + initCfg.gblerrCb = NULL; + initCfg.gblerrData = NULL; + + /* Open the Driver Instance */ + hEdma = EDMA3_DRV_open (edma3Id, (void *) &initCfg, &edma3Result); + } + +#if defined (CHIP_TI814X) + { + if(hEdma && (edma3Result == EDMA3_DRV_SOK)) + { + edma3Result = sampleInitXbarEvt(hEdma, edma3Id); + } + } +#endif + if(hEdma && (edma3Result == EDMA3_DRV_SOK)) + { + /** + * Register Interrupt Handlers for various interrupts + * like transfer completion interrupt, CC error + * interrupt, TC error interrupts etc, if required. + */ + registerEdma3Interrupts(edma3Id); + } + + *errorCode = edma3Result; + return hEdma; + } + + +/** + * \brief EDMA3 De-initialization + * + * This function removes the EDMA3 Driver instance and unregisters the + * interrupt handlers. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM; + + /* Unregister Interrupt Handlers first */ + unregisterEdma3Interrupts(edma3Id); + + /* Delete the semaphore */ + edma3Result = edma3OsSemDelete(semHandle[edma3Id]); + + if (EDMA3_DRV_SOK == edma3Result ) + { + /* Make the semaphore handle as NULL. */ + semHandle[edma3Id] = NULL; + + /* Now, close the EDMA3 Driver Instance */ + edma3Result = EDMA3_DRV_close (hEdma, NULL); + } + + if (EDMA3_DRV_SOK == edma3Result ) + { + /* Now, delete the EDMA3 Driver Object */ + edma3Result = EDMA3_DRV_delete (edma3Id, NULL); + } + + return edma3Result; + } + +/* End of File */ + diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_cfg.c b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_cfg.c new file mode 100644 index 000000000..5e670ca80 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_cfg.c @@ -0,0 +1,1391 @@ +/* + * sample_omapl138_cfg.c + * + * SoC specific EDMA3 hardware related information like number of transfer + * controllers, various interrupt ids etc. It is used while interrupts + * enabling / disabling. It needs to be ported for different SoCs. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include + +/* Number of EDMA3 controllers present in the system */ +#define NUM_EDMA3_INSTANCES 2u +const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES; + +/* Number of DSPs present in the system */ +#define NUM_DSPS 1u +const unsigned int numDsps = NUM_DSPS; + +/* Determine the processor id by reading DNUM register. */ +unsigned short determineProcId() +{ + return 1; +} + +signed char* getGlobalAddr(signed char* addr) +{ + return (addr); /* The address is already a global address */ +} +unsigned short isGblConfigRequired(unsigned int dspNum) +{ + (void) dspNum; + + return 1; +} + +/* Semaphore handles */ +EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL}; + +/** Number of PaRAM Sets available */ +#define EDMA3_NUM_PARAMSET (128u) +/** Number of TCCS available */ +#define EDMA3_NUM_TCC (32u) + +/** Number of Event Queues available */ +#define EDMA3_0_NUM_EVTQUE (2u) +#define EDMA3_1_NUM_EVTQUE (1u) + +/** Number of Transfer Controllers available */ +#define EDMA3_0_NUM_TC (2u) +#define EDMA3_1_NUM_TC (1u) + +#ifdef __TMS470__ /* values for ARM */ + +#else /* values for DSP */ +/** Interrupt no. for Transfer Completion */ +#define EDMA3_0_CC_XFER_COMPLETION_INT (8u) +#define EDMA3_1_CC_XFER_COMPLETION_INT (91u) + +/** Interrupt no. for CC Error */ +#define EDMA3_0_CC_ERROR_INT (56u) +#define EDMA3_1_CC_ERROR_INT (92u) + +/** Interrupt no. for TCs Error */ +#define EDMA3_0_TC0_ERROR_INT (57u) +#define EDMA3_0_TC1_ERROR_INT (58u) +#define EDMA3_0_TC2_ERROR_INT (0u) +#define EDMA3_0_TC3_ERROR_INT (0u) +#define EDMA3_0_TC4_ERROR_INT (0u) +#define EDMA3_0_TC5_ERROR_INT (0u) +#define EDMA3_0_TC6_ERROR_INT (0u) +#define EDMA3_0_TC7_ERROR_INT (0u) + +#define EDMA3_1_TC0_ERROR_INT (93u) +#define EDMA3_1_TC1_ERROR_INT (0u) +#define EDMA3_1_TC2_ERROR_INT (0u) +#define EDMA3_1_TC3_ERROR_INT (0u) +#define EDMA3_1_TC4_ERROR_INT (0u) +#define EDMA3_1_TC5_ERROR_INT (0u) +#define EDMA3_1_TC6_ERROR_INT (0u) +#define EDMA3_1_TC7_ERROR_INT (0u) + +/** + * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different + * ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. + * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding + * to transfer completion interrupt. + * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding + * to CC error interrupts. + * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding + * to TC error interrupts. + */ +/* EDMA 0 */ +#define EDMA3_0_HWI_INT_XFER_COMP (7u) +#define EDMA3_0_HWI_INT_CC_ERR (8u) +#define EDMA3_0_HWI_INT_TC0_ERR (8u) +#define EDMA3_0_HWI_INT_TC1_ERR (8u) + +/* EDMA 1 */ +#define EDMA3_1_HWI_INT_XFER_COMP (9u) +#define EDMA3_1_HWI_INT_CC_ERR (9u) +#define EDMA3_1_HWI_INT_TC0_ERR (9u) + +#endif /* __TMS470__ */ + +/** + * \brief Mapping of DMA channels 0-31 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ + /* 31 0 */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFF3FF3FFu) +#define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x3F07FFFFu) + +/** + * \brief Mapping of DMA channels 32-63 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ +/* DMA channels 32-63 DOES NOT exist in omapl138. */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u) +#define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u) + +/* Variable which will be used internally for referring number of Event Queues*/ +unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = { + EDMA3_0_NUM_EVTQUE, + EDMA3_1_NUM_EVTQUE + }; + +/* Variable which will be used internally for referring number of TCs. */ +unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = { + EDMA3_0_NUM_TC, + EDMA3_1_NUM_TC + }; + +/** + * Variable which will be used internally for referring transfer completion + * interrupt. + */ +unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { + { + 0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u, + }, + { + 0u, EDMA3_1_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u, + }, + }; + +/** + * Variable which will be used internally for referring channel controller's + * error interrupt. + */ +unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = { + EDMA3_0_CC_ERROR_INT, + EDMA3_1_CC_ERROR_INT + }; + +/** + * Variable which will be used internally for referring transfer controllers' + * error interrupts. + */ +unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = { + { + EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT, + EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT, + EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT, + EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT, + }, + { + EDMA3_1_TC0_ERROR_INT, EDMA3_1_TC1_ERROR_INT, + EDMA3_1_TC2_ERROR_INT, EDMA3_1_TC3_ERROR_INT, + EDMA3_1_TC4_ERROR_INT, EDMA3_1_TC5_ERROR_INT, + EDMA3_1_TC6_ERROR_INT, EDMA3_1_TC7_ERROR_INT, + } + }; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = { + EDMA3_0_HWI_INT_XFER_COMP, + EDMA3_1_HWI_INT_XFER_COMP + }; + +unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = { + EDMA3_0_HWI_INT_CC_ERR, + EDMA3_1_HWI_INT_CC_ERR + }; + +unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = { + { + EDMA3_0_HWI_INT_TC0_ERR, + EDMA3_0_HWI_INT_TC1_ERR, + }, + { + EDMA3_1_HWI_INT_TC0_ERR, + } + }; + +/* Driver Object Initialization Configuration */ +EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = +{ + { + /* EDMA3 INSTANCE# 0 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 32u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 32u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 128u, + /** Total number of Event Queues in the EDMA3 Controller */ + 2u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/ + 2u, + /** Number of Regions on this EDMA3 controller */ + 4u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 0u, + + /** Existence of memory protection feature */ + 0u, + + /** Global Register Region of CC Registers */ + (void *)0x01C00000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x01C08000u, + (void *)0x01C08400u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + EDMA3_0_CC_XFER_COMPLETION_INT, + /** Interrupt no. for CC Error */ + EDMA3_0_CC_ERROR_INT, + /** Interrupt no. for TCs Error */ + { + EDMA3_0_TC0_ERROR_INT, + EDMA3_0_TC1_ERROR_INT, + EDMA3_0_TC2_ERROR_INT, + EDMA3_0_TC3_ERROR_INT, + EDMA3_0_TC4_ERROR_INT, + EDMA3_0_TC5_ERROR_INT, + EDMA3_0_TC6_ERROR_INT, + EDMA3_0_TC7_ERROR_INT + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + /* DMA channels 32-63 DOES NOT exist in OMAPL138. */ + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, + 4u, 5u, 6u, 7u, + 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, + 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, + 28u, 29u, 30u, 31u, + /* DMA channels 32-63 DOES NOT exist in OMAPL138. */ + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 + } + }, + + { + /* EDMA3 INSTANCE# 1 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 32u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 32u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 128u, + /** Total number of Event Queues in the EDMA3 Controller */ + 1u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ + 1u, + /** Number of Regions on this EDMA3 controller */ + 4u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 0u, + + /** Existence of memory protection feature */ + 0u, + + /** Global Register Region of CC Registers */ + (void *)0x01E30000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x01E38000u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + EDMA3_1_CC_XFER_COMPLETION_INT, + /** Interrupt no. for CC Error */ + EDMA3_1_CC_ERROR_INT, + /** Interrupt no. for TCs Error */ + { + EDMA3_1_TC0_ERROR_INT, + EDMA3_1_TC1_ERROR_INT, + EDMA3_1_TC2_ERROR_INT, + EDMA3_1_TC3_ERROR_INT, + EDMA3_1_TC4_ERROR_INT, + EDMA3_1_TC5_ERROR_INT, + EDMA3_1_TC6_ERROR_INT, + EDMA3_1_TC7_ERROR_INT, + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + /* DMA channels 32-63 DOES NOT exist in OMAPL138. */ + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, + 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, + 12u, 13u, 14u, 15u, + 16u, 17u, 18u, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, + 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + /* DMA channels 32-63 DOES NOT exist in OMAPL138. */ + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0, + EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1 + } + }, +}; + + +/* Driver Instance Initialization Configuration */ +EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = +{ + /* EDMA3 INSTANCE# 0 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + /* Resources owned/reserved by region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 */ + {0xFF3FF3FFu, + /* 63..32 */ + 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + }, + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + }, + /* EDMA3 INSTANCE# 1 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + /* Resources owned by Region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + { + 0xFFFFFFFFu, + 0x00000000u + }, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + { + 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + }, + + /* resvdDmaChannels */ + /* 31 0 */ + { + EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1 + }, + + /* resvdQdmaChannels */ + /* 31 0 */ + { + 0x00000000u + }, + + /* resvdTccs */ + /* 31 0 */ + { + 0x3F07FFFFu, + /* 63..32 */ + 0x00000000u + }, + }, + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + } + } +}; + +/* End of File */ + diff --git a/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_int_reg.c b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_int_reg.c new file mode 100644 index 000000000..e82c9392b --- /dev/null +++ b/packages/ti/drv/mcbsp/example/c674x/MCBSPDigLpbk/sample_omapl138_int_reg.c @@ -0,0 +1,152 @@ +/* + * sample_omapl138_int_reg.c + * + * Platform specific interrupt registration and un-registration routines. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include + +#include + +/** + * EDMA3 TC ISRs which need to be registered with the underlying OS by the user + * (Not all TC error ISRs need to be registered, register only for the + * available Transfer Controllers). + */ +void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) = + { + &lisrEdma3TC0ErrHandler0, + &lisrEdma3TC1ErrHandler0, + &lisrEdma3TC2ErrHandler0, + &lisrEdma3TC3ErrHandler0, + &lisrEdma3TC4ErrHandler0, + &lisrEdma3TC5ErrHandler0, + &lisrEdma3TC6ErrHandler0, + &lisrEdma3TC7ErrHandler0, + }; + +extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS]; +extern unsigned int ccErrorInt[]; +extern unsigned int tcErrorInt[][EDMA3_MAX_TC]; +extern unsigned int numEdma3Tc[]; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +extern unsigned int hwIntXferComp[]; +extern unsigned int hwIntCcErr[]; +extern unsigned int hwIntTcErr[]; + +extern unsigned int dsp_num; + +/** To Register the ISRs with the underlying OS, if required. */ +void registerEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Enable the Xfer Completion Event Interrupt */ + EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num], + (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0), + edma3Id, 1); + EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]); + + /* Enable the CC Error Event Interrupt */ + EventCombiner_dispatchPlug(ccErrorInt[edma3Id], + (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0), + edma3Id, 1); + EventCombiner_enableEvent(ccErrorInt[edma3Id]); + + /* Enable the TC Error Event Interrupt, according to the number of TCs. */ + while (numTc < numEdma3Tc[edma3Id]) + { + EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc], + (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]), + edma3Id, 1); + EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]); + numTc++; + } + + /** + * Enabling the HWI_ID. + * EDMA3 interrupts (transfer completion, CC error etc.) + * correspond to different ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this + * mapped HWI_INT YYY, one should use the corresponding bitmask in the + * API C64_enableIER(), in which the YYY bit is SET. + */ + Hwi_enableInterrupt(hwIntXferComp[edma3Id]); + Hwi_enableInterrupt(hwIntCcErr[edma3Id]); + Hwi_enableInterrupt(hwIntTcErr[edma3Id]); + + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +void unregisterEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Disable the Xfer Completion Event Interrupt */ + EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]); + + /* Disable the CC Error Event Interrupt */ + EventCombiner_disableEvent(ccErrorInt[edma3Id]); + + /* Enable the TC Error Event Interrupt, according to the number of TCs. */ + while (numTc < numEdma3Tc[edma3Id]) + { + EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]); + numTc++; + } + + /* Restore interrupts */ + Hwi_restore(cookie); + } + diff --git a/packages/ti/drv/mcbsp/example/include/MCBSP_log.h b/packages/ti/drv/mcbsp/example/include/MCBSP_log.h new file mode 100644 index 000000000..603091b9c --- /dev/null +++ b/packages/ti/drv/mcbsp/example/include/MCBSP_log.h @@ -0,0 +1,77 @@ +/** + * \file MCBSP_log.h + * + * \brief This file contains the prototypes for the log print functions. By + default the prints will be directed to serial console using UART. + * + */ + +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _MCBSP_LOG_H +#define _MCBSP_LOG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* UART Header files */ +#include +#include + +/********************************************************************** + ************************** Global Variables ************************** + **********************************************************************/ +extern void UART_printf(const char *pcString, ...); +extern void ConsoleUtilsInit(void); + +/********************************************************************** + ************************** Macros ************************************ + **********************************************************************/ +/* Enable the below macro to have prints on the IO Console */ +//#define IO_CONSOLE + +#ifndef IO_CONSOLE +#define MCBSP_log UART_printf +#else +#define MCBSP_log System_printf +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _MCBSP_LOG_H */ diff --git a/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/MCBSP_DigLpbkevmK2Gc66ExampleProject.txt b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/MCBSP_DigLpbkevmK2Gc66ExampleProject.txt new file mode 100644 index 000000000..d0302fd85 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/MCBSP_DigLpbkevmK2Gc66ExampleProject.txt @@ -0,0 +1,8 @@ +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/device/k2g/src/device_mcbsp_loopback.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/sample_k2g_cfg.c" + +-ccs.setCompilerOptions "-DDEVICE_K2G -DMCBSP_DEBUG_TEMP -g --diag_warning=225 -I${PDK_INSTALL_PATH} -I${BIOS_INSTALL_PATH}/packages -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/include -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/include -I${PDK_INSTALL_PATH}/ti/drv/mcbsp -I${PDK_INSTALL_PATH}/ti/board" -rtsc.enableRtsc diff --git a/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/bios6_edma3_drv_sample.h b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/bios6_edma3_drv_sample.h new file mode 100644 index 000000000..5fad8a74a --- /dev/null +++ b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/bios6_edma3_drv_sample.h @@ -0,0 +1,186 @@ +/* + * bios6_edma3_drv_sample.h + * + * Header file for the sample application for the EDMA3 Driver. + * + * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef _BIOS6_EDMA3_DRV_SAMPLE_H_ +#define _BIOS6_EDMA3_DRV_SAMPLE_H_ + +#include +#include + +/* Include EDMA3 Driver */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Cache line size on the underlying SoC. It needs to be modified + * for different cache line sizes, if the Cache is Enabled. + */ +#define EDMA3_CACHE_LINE_SIZE_IN_BYTES (128u) + +/* Error returned in case of buffers are not aligned on the cache boundary */ +#define EDMA3_NON_ALIGNED_BUFFERS_ERROR (-1) + +/* Error returned in case of data mismatch */ +#define EDMA3_DATA_MISMATCH_ERROR (-2) + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 Driver for the given EDMA3 controller + * and opens a EDMA3 driver instance. It internally calls EDMA3_DRV_create() and + * EDMA3_DRV_open(), in that order. + * + * It also registers interrupt handlers for various EDMA3 interrupts like + * transfer completion or error interrupts. + * + * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0) + * \param errorCode [IN/OUT] Error code while opening DRV instance + * \return EDMA3_DRV_Handle: If successfully opened, the API will return the + * associated driver's instance handle. + */ +EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode); + +/** + * \brief EDMA3 De-initialization + * + * This function de-initializes the EDMA3 Driver for the given EDMA3 controller + * and closes the previously opened EDMA3 driver instance. It internally calls + * EDMA3_DRV_close and EDMA3_DRV_delete(), in that order. + * + * It also un-registers the previously registered interrupt handlers for various + * EDMA3 interrupts. + * + * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0) + * \param hEdma [IN] EDMA3 Driver handle, returned while using + * edma3init(). + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma); + + +/** + * \brief EDMA3 Cache Invalidate + * + * This function invalidates the D cache. + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * \brief EDMA3 Cache Flush + * + * This function flushes (cleans) the Cache + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 driver/RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to receive the handle to just created + * semaphore. + * \return EDMA3_DRV_SOK if successful, else a suitable error code. + */ +EDMA3_DRV_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem); + + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_DRV_SOK if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _BIOS6_EDMA3_DRV_SAMPLE_H_ */ + diff --git a/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/config.bld b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/config.bld new file mode 100644 index 000000000..cb4905e5a --- /dev/null +++ b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/config.bld @@ -0,0 +1,82 @@ +/* + * + * $Source: /cvsstl/ti/pa/f/s19/config.bld,v $ + * $Revision: 1.6 $ + * + * XDC/BIOS configuration file for I12 Topo/Feature Set + * + * Copyright 2008, Texas Instruments, Inc. All rights reserved. + * + * $Log: config.bld,v $ + * Revision 1.6 2009/06/10 07:51:13 mkamat + * MID 2487 Replace references to PA17 with PA + * + * Revision 1.5 2009/03/02 04:36:58 uparikh + * Add segment SDRAM_LINK_SHARED for dhared LINK memory + * + * Revision 1.4 2009/02/18 14:29:12 uparikh + * Partition SDRAM and re-order memory segments in ascending order + * + * Revision 1.3 2009/02/14 09:05:55 uparikh + * Update IRAM and SDRAM base / len + * + * Revision 1.2 2009/01/28 12:37:59 mkamat + * Made cache 64k and moved o/p buffer to L3 - MID 2144 + * + * Revision 1.1 2008/10/21 04:45:09 mkamat + * Code cleanup in s19 area - MID 1923 + * + * Revision 1.6 2008/10/13 05:22:54 uparikh + * Define section for uboot + * + * Revision 1.5 2008/09/29 11:20:53 uparikh + * Increase size of SDRAM for pa.out to build + * + * Revision 1.4 2008/09/09 23:35:52 lester + * (MID 1820) Revised to use deviceName: 'TMS320DA830', + * instead of deviceName: 'Primus' (deprecated). + * + * Revision 1.3 2008/09/05 17:18:42 martin + * Renumber array elements. Element 1 was missing in last commit + * + * Revision 1.2 2008/09/05 16:00:43 martin + * Move DSP image to upper SDRAM to cooperate with Linux images. + * + * Revision 1.1 2008/08/20 09:54:35 lester + * (MID 1820) Generated via (from latest this date): + * [/cygdrive/t/pa/f/s17/pai1] delog -f"t:/pa/f/s19/i12" .... + * + */ + +/* ......................................................................... */ + +var memory = []; + + +memory[0] = ["IRAM", + { + name : "IRAM", + base : 0x10800000, + len : 0x00080000, + space : "code/data" + }]; + +memory[1] = ["L3RAM", + { + name : "DDR3", + base : 0x80000000, + len : 0x10000000, + space : "data" + }]; + + +Build.platformTable['ti.platforms.generic:plat'] = +{ +clockRate: 600, +catalogName: 'ti.catalog.c6000', +deviceName: 'TMS320TCI6616', +regs: {l1DMode: "32k"}, +regs: {l1PMode: "32k"}, +regs: {l2Mode: "64k"}, +customMemoryMap: memory +}; diff --git a/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.c b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.c new file mode 100644 index 000000000..03a52bc0c --- /dev/null +++ b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.c @@ -0,0 +1,979 @@ +/* + * mcbspMasterDigLpbk.c + * + * This file contains the test / demo code to demonstrate the McBSP driver + * master functionality using Digital Loopback setup. The file configures + * the EVM in master mode. + * + * Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/* ========================================================================== */ +/* INCLUDE FILES */ +/* ========================================================================== */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Include EDMA3 Driver */ +#include + +/* CSL Chip Functional Layer */ +//#include + +/* CSL Cache Functional Layer */ +//#include + +/* CSL CPINTC Include Files. */ +//#include + +/* MCBSP Driver Include File. */ +#include +#include + +/* PlatformLib Include File */ +//#include + + +/* ========================================================================== */ +/* EXTERNAL FUNCTIONS */ +/* ========================================================================== */ + +extern EDMA3_DRV_Handle edma3init(unsigned int edma3Id, EDMA3_DRV_Result *); + +extern void McbspDevice_init(void); + +extern int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize); + +extern Board_STATUS Board_init(Board_initCfg); + +extern void McbspXmtInterrupt_init(void *mcbspTxChan); +extern void McbspRcvInterrupt_init(void *mcbspRxChan); + +/* FPGA Configuration Misc-1 Register offset */ +#define MCBSP_FPGA_MISC_REG_OFFSET (0x0C) + +/* ========================================================================== */ +/* MACRO DEFINTIONS */ +/* ========================================================================== */ + +#define NUM_BUFS 2 /* Max of buffers used in each direction */ +#define FRAMESIZE 40 /* e.g 5 ms 8 KHz samples */ +#define NUM_OF_ENABLED_CHANNELS 8 /* Number of slots to be used */ +#define NUM_OF_MAX_CHANNELS 128 /* Maximum number of time slots available based on clock settings */ +#define BUFSIZE (NUM_OF_ENABLED_CHANNELS * FRAMESIZE) /* Total buffer size per frame */ + +/* Defines the core number responsible for system initialization. */ +#define CORE_SYS_INIT 0 +/* Number of iterations to execute test: Only applicable to INTERNAL CLOCK Loopback test */ +#define NUM_OF_ITERATIONS 10 + +/* Number of MCBSP Frame structures used for submit channel */ +#define NUM_OF_MCBSP_FRAMES 2 + +/* Number of buffers initially submitted to Mcbsp lld: Only applicable to + External clock test ; Note: This should be set to 2*/ +#define INIT_SUBMIT_Q_CNT 2 + +/*============================================================================*/ +/* GLOBAL VARIABLES */ +/*============================================================================*/ + +/* Shared Memory Variable to ensure synchronizing MCBSP initialization + * with all the other cores. */ +/* Created an array to pad the cache line with MCBSP_CACHE_LENGTH size */ +#pragma DATA_ALIGN (isMCBSPInitialized, MCBSP_MAX_CACHE_ALIGN) +#pragma DATA_SECTION (isMCBSPInitialized, ".mcbspSharedMem"); +volatile Uint32 isMCBSPInitialized[(MCBSP_CACHE_LENGTH / sizeof(Uint32))] = { 0 }; + +/* Handle to the EDMA driver instance */ +#pragma DATA_ALIGN (hEdma, MCBSP_MAX_CACHE_ALIGN) +EDMA3_DRV_Handle hEdma[(MCBSP_CACHE_LENGTH / sizeof(EDMA3_DRV_Handle))] = { NULL }; + +/* Handle to MCBSP driver instance */ +typedef void* Mcbsp_DevHandle; +Mcbsp_DevHandle hMcbspDev; + +/* Handle to MCBSP driver channel instance */ +typedef void* Mcbsp_ChanHandle; +Mcbsp_ChanHandle hMcbspTxChan; +Mcbsp_ChanHandle hMcbspRxChan; + +/* Core Number Identifier */ +UInt32 coreNum = 0xFFFF; + +/* Array to hold the pointer to the allocated buffers */ +void* bufRx[NUM_BUFS]; +void* bufTx[NUM_BUFS]; + +#ifdef MCBSP_LOOP_PING_PONG +/* Ping pong buffers used to submit to Mcbsp lld, which will be used in a loop */ +void* bufRxPingPong[INIT_SUBMIT_Q_CNT]; +void* bufTxPingPong[INIT_SUBMIT_Q_CNT]; +#endif +/* Global Error call back function prototype */ +void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3); + +/* Variables to indicate status of EDMA TX and RX requests */ +volatile uint32_t edmaTxDone = 0; +volatile uint32_t edmaRxDone = 0; +/* Global variables to track number of buffers submitted, number of iterations, error counts etc */ +int rxSubmitCount=0, txSubmitCount=0; +uint32_t num_iterations=0; +uint32_t num_rx_Call_backs=0, num_tx_Call_backs=0, dummy_call_backs=0; +uint32_t rxunderflowcnt=0, txunderflowcnt=0; +uint32_t errBuffCount=0; +/* Debug variables */ +volatile int debugVar=1; /* This can be used to maintain a while loop, If set to 0 will exit loop */ +volatile int debugCommand=1; /* This can be used to set to value below to send command to restart channel */ + +#define DEBUG_COMMAND_RESTART_CHANNELS 1 +/** + * \brief Mcbsp Sample rate generator default parameters. + * + */ +Mcbsp_srgConfig mcbspSrgCfg = +{ + FALSE, /* No gsync to be used as input is not CLKS */ + Mcbsp_ClkSPol_RISING_EDGE, /* Dont care as input clock is not clks */ + Mcbsp_SrgClk_CLKCPU, /* McBSP internal clock to be used */ + //166666667, /* Mcbsp internal clock frequency(PLL-SYSCLK6) */ + 333333333, //sys_oscclk or cpu_clk/3 + 0 /* frame sync pulse width (val+1) is used */ +}; + +/** + * \brief Mcbsp device creation default parameters. + * + */ +const Mcbsp_Params Mcbsp_PARAMS = +{ + Mcbsp_DevMode_McBSP, /* Use the device as MCBSP */ + Mcbsp_OpMode_DMAINTERRUPT, /* Use DMA mode of operation */ + TRUE, /* cache coherency taken care of by driver */ + Mcbsp_EmuMode_FREE, /* Emulation mode free is to be enabled */ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_Loopback_DISABLE, /* Loop back mode disabled */ +#else + Mcbsp_Loopback_ENABLE, /* Loop back mode enabled */ +#endif + &mcbspSrgCfg, /* sample rate generator configuration */ + NULL, /* TX pending buffer queue from application */ + NULL, /* TX floating buffer queue in DMA */ + NULL, /* RX pending buffer queue from application */ + NULL /* RX floating buffer queue in DMA */ +}; + +#pragma DATA_ALIGN(loopTxJob, MCBSP_MAX_CACHE_ALIGN) +static Int32 loopTxJob[16] = { + /* Filling with Mu law silence pattern : Can be any user defined pattern */ + 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, + 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f +}; +#pragma DATA_ALIGN(loopRxJob, MCBSP_MAX_CACHE_ALIGN) +static Int32 loopRxJob[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/**< settings to configure the TX or RX hardware sections */ +Mcbsp_DataConfig mcbspChanConfigTx = +{ + Mcbsp_Phase_SINGLE, + Mcbsp_WordLength_8, + Mcbsp_WordLength_8, /* Dont care for single phase*/ + NUM_OF_MAX_CHANNELS, + NUM_OF_MAX_CHANNELS, // Only used with dual phase + Mcbsp_FrmSync_DETECT, +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_DataDelay_0_BIT, +#else + Mcbsp_DataDelay_1_BIT, +#endif + Mcbsp_Compand_OFF_MSB_FIRST, + Mcbsp_BitReversal_DISABLE, + Mcbsp_IntMode_ON_SYNCERR, + Mcbsp_RxJust_RZF, /* Dont care for TX */ + Mcbsp_DxEna_OFF +}; + +/**< settings to configure the TX or RX hardware sections */ +Mcbsp_DataConfig mcbspChanConfigRx = +{ + Mcbsp_Phase_SINGLE, + Mcbsp_WordLength_8, + Mcbsp_WordLength_8, /* Dont care for single phase*/ + NUM_OF_MAX_CHANNELS, + NUM_OF_MAX_CHANNELS, // Only used with dual phase + Mcbsp_FrmSync_DETECT, +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_DataDelay_0_BIT, +#else + Mcbsp_DataDelay_1_BIT, +#endif + Mcbsp_Compand_OFF_MSB_FIRST, + Mcbsp_BitReversal_DISABLE, + Mcbsp_IntMode_ON_SYNCERR, + Mcbsp_RxJust_RZF, /* Dont care for TX */ + Mcbsp_DxEna_OFF +}; +/**< clock setup for the TX section */ +Mcbsp_ClkSetup mcbspClkConfigTx = +{ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_FsClkMode_EXTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_EXTERNAL, +#else + Mcbsp_FsClkMode_INTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_INTERNAL, +#endif + Mcbsp_FsPol_ACTIVE_HIGH, + Mcbsp_ClkPol_RISING_EDGE +}; + +/**< clock setup for the RX section */ +Mcbsp_ClkSetup mcbspClkConfigRx = +{ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_FsClkMode_EXTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_EXTERNAL, +#else + Mcbsp_FsClkMode_INTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_INTERNAL, +#endif + Mcbsp_FsPol_ACTIVE_HIGH, + Mcbsp_ClkPol_FALLING_EDGE +}; + +/**< Multi channel setup */ +Mcbsp_McrSetup mcbspMultiChanCtrl = +{ + Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED, + Mcbsp_PartitionMode_CHAN_0_15, + Mcbsp_PartitionMode_CHAN_16_31, + Mcbsp_PartitionMode_2 +}; + + +Mcbsp_ChanParams mcbspChanparamTx = +{ + Mcbsp_WordLength_8, /* wordlength configured */ + &loopTxJob[0], /* loop job buffer internal */ + 8, /* user loopjob length */ + mcbsp_GblErrCallback, /* global error callback */ + NULL, /* edma Handle */ + 1, /* EDMA event queue */ + 8, /* hwi number */ + Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED, + TRUE, /* FIFO mode enabled */ + &mcbspChanConfigTx, /* channel configuration */ + &mcbspClkConfigTx, /* clock configuration */ + &mcbspMultiChanCtrl, /* multi channel control */ + 0x7531, /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */ + 0x00, + 0x00, + 0x00, + NUM_OF_ENABLED_CHANNELS /* Total number of channels enabled*/ +}; + +Mcbsp_ChanParams mcbspChanparamRx = +{ + Mcbsp_WordLength_8, /* wordlength configured */ + &loopRxJob[0], /* loop job buffer internal */ + 8, /* user loopjob length */ + mcbsp_GblErrCallback, /* global error callback */ + NULL, /* edma Handle */ + 1, /* EDMA event queue */ + 8, /* hwi number */ + Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED, + TRUE, /* FIFO mode enabled */ + &mcbspChanConfigRx, /* channel configuration */ + &mcbspClkConfigRx, /* clock configuration */ + &mcbspMultiChanCtrl, /* multi channel control */ + 0x7531, /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */ + 0x00, + 0x00, + 0x00, + NUM_OF_ENABLED_CHANNELS /* Total number of channels enabled*/ +}; + + +/* ========================================================================== */ +/* FUNCTION DEFINITIONS */ +/* ========================================================================== */ + +/* + * This is the application's callback function. The driver will + * call this function whenever an EDMA I/O operation is over. + * + */ +void mcbspAppCallback(void* arg, Mcbsp_IOBuf *ioBuf) +{ + int32_t mode; + int32_t *pmode = (int32_t *)arg; + + mode = *pmode; + if (mode == MCBSP_MODE_OUTPUT) + { + if(ioBuf) { + num_tx_Call_backs++; + edmaTxDone = 1; + }else + txunderflowcnt++; + } + else if (mode == MCBSP_MODE_INPUT) + { + if(ioBuf) { + num_rx_Call_backs++; + edmaRxDone = 1; + }else + rxunderflowcnt++; + }else + dummy_call_backs++; + return; +} + +/* + * This is the application's Global error callback function + */ +void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3) +{ + MCBSP_log ("Debug(Core %d): ERROR callback called SPCR: %x", coreNum, spcr_read); +} + +/* + * \brief This function demostrates the use of Mcbsp using digital loopback + * communication setup. + * + * \param None + * + * \return None + */ +void mcbspDigLpbkApp(UArg arg0, UArg arg1) +{ + /**< Mcbsp device params */ + Mcbsp_Params mcbspParams; + + /**< Queue to hold the pending packets received from the application */ + Queue_Struct txQueuePendingList, rxQueuePendingList; + /**< Queue to manage floating packets in DMA */ + Queue_Struct txQueueFloatingList, rxQueueFloatingList; + + uint32_t count = 0, tempCount = 0; + int32_t status = 0, retval = 0; + int32_t txChanMode = MCBSP_MODE_OUTPUT; + int32_t rxChanMode = MCBSP_MODE_INPUT; + uint32_t mcbspTxDone = 0, mcbspRxDone = 0; + Mcbsp_IOBuf txFrame[NUM_OF_MCBSP_FRAMES], rxFrame[NUM_OF_MCBSP_FRAMES]; + int txFrameIndex=0, rxFrameIndex=0; + int init_count=0; +#ifdef MCBSP_LOOP_PING_PONG + int pingPongIndex=0; +#endif + + /* Initialize the OSAL */ + if (Osal_dataBufferInitMemory(BUFSIZE) < 0) + { + MCBSP_log ("Debug(Core %d): Error: Unable to initialize the OSAL. \n", coreNum); + return; + } + + /* update EDMA3 handle to channel parameters */ + mcbspChanparamTx.edmaHandle = hEdma[0]; + mcbspChanparamRx.edmaHandle = hEdma[0]; + + /* create the pending and floating queue for the TX channel */ + Queue_construct(&txQueuePendingList, NULL); + Queue_construct(&txQueueFloatingList, NULL); + + /* create the pending and floating queue for the RX channel */ + Queue_construct(&rxQueuePendingList, NULL); + Queue_construct(&rxQueueFloatingList, NULL); + + + mcbspParams = Mcbsp_PARAMS; + mcbspParams.txQPendingList = &txQueuePendingList; + mcbspParams.txQFloatingList = &txQueueFloatingList; + mcbspParams.rxQPendingList = &rxQueuePendingList; + mcbspParams.rxQFloatingList = &rxQueueFloatingList; + + + /* Bind the driver instance with device instance */ + status = mcbspBindDev(&hMcbspDev, coreNum, &mcbspParams); + + if (status != MCBSP_STATUS_COMPLETED) + { + MCBSP_log ("Debug(Core %d): MCBSP LLD Bind Device Failed\n", coreNum); + return; + } + + /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */ + if(mcbspChanparamRx.userLoopJobBuffer) + mcbspChanparamRx.userLoopJobBuffer = (void *)Mcbsp_osalLocal2Global(mcbspChanparamRx.userLoopJobBuffer); + + /* Create a RX channel for receiving */ + status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum); + return; + } + + /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */ + if(mcbspChanparamTx.userLoopJobBuffer) + mcbspChanparamTx.userLoopJobBuffer = Mcbsp_osalLocal2Global(mcbspChanparamTx.userLoopJobBuffer); + + /* Create a TX channel for the transmission */ + status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum); + return; + } + + /* Register mcbsp interrupts */ + //McbspRcvInterrupt_init(hMcbspRxChan); + //McbspXmtInterrupt_init(hMcbspTxChan); + + /* create the buffers required for the TX and RX operations */ + for (count = 0; count < (NUM_BUFS); count++) + { + bufTx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + bufRx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + + if (bufTx[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Tx Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + if (bufRx[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Rx Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* create the ping pong buffers required for the TX and RX operations */ + for (count = 0; count < (NUM_BUFS); count++) + { + bufRxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + bufTxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + + if (bufTxPingPong[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Tx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + if (bufRxPingPong[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Rx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + } +#endif + /* Fill the buffers with known data and transmit the same and + check if the same pattern is received */ + for (count = 0; count < (NUM_BUFS); count++) + { + memset((uint8_t *)bufTx[count], 0, BUFSIZE); + for (tempCount = 0; tempCount < BUFSIZE; tempCount++) + { + ((uint8_t *)bufTx[count])[tempCount] = (tempCount % 0x100); + } + } + MCBSP_log ("Debug(Core %d): If required to restart set debugCommand variable to %d\n", coreNum, DEBUG_COMMAND_RESTART_CHANNELS); + +restart_mcbsp_point: + txFrameIndex=0; + rxFrameIndex=0; + init_count=0; +#ifdef MCBSP_EXTERNAL_CLOCK + /* Initial loading of ping ping buffers */ + for(init_count =0 ; init_count < INIT_SUBMIT_Q_CNT; init_count++) + { +#ifdef MCBSP_LOOP_PING_PONG + memset((uint8_t *)bufRxPingPong[init_count], 0, BUFSIZE); + + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRxPingPong[init_count]; +#else + memset((uint8_t *)bufRx[init_count], 0, BUFSIZE); + + + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRx[init_count]; +#endif + + rxFrame[rxFrameIndex].size = BUFSIZE; + rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan; + rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED; + rxFrame[rxFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, init_count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, init_count); +#endif + } + rxFrameIndex++; + rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex; + + rxSubmitCount++; + + /* TX frame processing */ + txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE; +#ifdef MCBSP_LOOP_PING_PONG + txFrame[txFrameIndex].addr = (void*)bufTxPingPong[init_count]; +#else + txFrame[txFrameIndex].addr = (void*)bufTx[init_count]; +#endif + txFrame[txFrameIndex].size = BUFSIZE; + txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan; + txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED; + txFrame[txFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: TX buffer #%d submission FAILED\n", coreNum, init_count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): TX buffer #%d submission is submitted to MCBSP driver\n", coreNum, init_count); +#endif + } + txFrameIndex++; + txFrameIndex = (txFrameIndex >=(NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex; + + txSubmitCount++; + } + + /* Wait for TX and RX processing to complete */ + while (1) + { + if (edmaTxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Iteration-%d frames are transmitted to TX path\n", coreNum, count); +#endif + edmaTxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 1; + } + if (edmaRxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Iteration-%d frames are received from RX path\n", coreNum, count); +#endif + edmaRxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 1; + } + if ((mcbspTxDone == 1) && (mcbspRxDone == 1)) + { + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + break; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* Change ping Pong Index */ + init_count=0; +#endif +#endif /* MCBSP_EXTERNAL_CLOCK */ + + /* Start main loop to iterate through frames */ + while(debugVar) + { + /* submit frames to the driver */ + for (count = init_count; count < NUM_BUFS; count++) + { +#ifdef MCBSP_EXTERNAL_CLOCK +/* With External clock the data coming from the RX side is copied to loop back to the Tx side */ + memcpy((uint8_t *)bufTx[count], (uint8_t *)bufRx[count], BUFSIZE); +#endif +#ifdef MCBSP_LOOP_PING_PONG + memset((uint8_t *)bufRxPingPong[pingPongIndex], 0, BUFSIZE); +#else + memset((uint8_t *)bufRx[count], 0, BUFSIZE); + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)getGlobalAddr(bufRx[count]); + rxFrame[rxFrameIndex].size = BUFSIZE; + rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan; + rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED; + rxFrame[rxFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, count); +#endif + } + rxFrameIndex++; + rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex; +#endif + rxSubmitCount++; +#ifdef MCBSP_LOOP_PING_PONG + /* Copy buffer from buffer to ping pong buffer*/ + memcpy((uint8_t *)bufTxPingPong[pingPongIndex], (uint8_t *)bufTx[count],BUFSIZE); +#else + /* TX frame processing */ + txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE; + txFrame[txFrameIndex].addr = (void*)getGlobalAddr(bufTx[count]); + txFrame[txFrameIndex].size = BUFSIZE; + txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan; + txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED; + txFrame[txFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: TX buffer #%d submission FAILED\n", coreNum, count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): TX buffer #%d is submitted to MCBSP driver\n", coreNum, count); +#endif + } + txFrameIndex++; + txFrameIndex = (txFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex; +#endif + txSubmitCount++; + + /* Wait for TX and RX processing to complete */ + while (1) + { + if (edmaTxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Buffer #-%d is transmitted to TX path\n", coreNum, count); +#endif + edmaTxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 1; + } + if (edmaRxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Buffer #-%d is received from RX path\n", coreNum, count); +#endif + edmaRxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 1; + } + if ((mcbspTxDone == 1) && (mcbspRxDone == 1)) + { + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + break; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* Change ping Pong Index */ + pingPongIndex=(pingPongIndex)?0:1; + + /* Copy buffer from buffer to other buffer*/ + memcpy((void*)bufRx[count], (uint8_t *)bufRxPingPong[pingPongIndex],BUFSIZE); +#endif + /* compare buffer contents */ + for (tempCount = 0; tempCount < BUFSIZE; tempCount++) + { + if (((char *)bufTx[count])[tempCount] != ((char *)bufRx[count])[tempCount]) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log("Debug(Core %d): Error: TX and RX frame data DOES NOT match in Buffer #-%d\n", + coreNum, count); + MCBSP_log("Debug(Core %d): Error: Buffer index = %d, Tx data = %d, Rx data = %d\n", coreNum, + tempCount, ((char *)bufTx[count])[tempCount], ((char *)bufRx[count])[tempCount]); +#endif + errBuffCount++; + break; + } + } + if (tempCount >= BUFSIZE) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log("Debug(Core %d): TX and RX frames data match in iteration-%d !!!\n", coreNum, count); +#endif + } + } + init_count=0; + num_iterations++; +#ifndef MCBSP_EXTERNAL_CLOCK + if(num_iterations >= NUM_OF_ITERATIONS) + break; +#endif + switch(debugCommand) + { + case DEBUG_COMMAND_RESTART_CHANNELS: + debugCommand=0; + /* Close channel and reopen */ + /* Delete RX channel */ + status = mcbspDeleteChan(hMcbspRxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum); + return; + } + + /* Delete TX channel*/ + status = mcbspDeleteChan(hMcbspTxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum); + return; + } + /* Create a RX channel for receiving */ + status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum); + return; + } + + /* Create a TX channel for the transmission */ + status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum); + return; + } + edmaTxDone = 0; /* Reset for next iteration */ + edmaRxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + goto restart_mcbsp_point; + + default: + debugCommand=0; + break; + + } + + } + + if ((errBuffCount == 0 ) & (retval ==0)) + { + MCBSP_log("Debug(Core %d): MCBSP Digital Loopback Application completed successfully : "\ + "Num iterations %d Num buffers per iteration %d!!!\n", + coreNum, num_iterations, NUM_BUFS); + MCBSP_log("\n All tests have passed \n"); + } + else + { + MCBSP_log("Debug(Core %d): MCBSP Digital Loopback application FAILED : "\ + "Num iterations %d Num buffers per iteration %d Failed buffers %d!!!\n", + coreNum, num_iterations, NUM_BUFS, errBuffCount); + } + + /* Delete RX channel */ + status = mcbspDeleteChan(hMcbspRxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum); + return; + } + + /* Delete TX channel*/ + status = mcbspDeleteChan(hMcbspTxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum); + return; + } + return; +} + +/* + * \brief Void main(Void) + * + * Main function of the sample application. This function calls the + * function to configure the mcbsp instance. + * + * \param None + * + * \return None + */ +#include "ti/sysbios/hal/Cache.h" + +Void main(Void) +{ + Task_Params taskParams; + EDMA3_DRV_Result edmaResult = 0; +#ifdef SIMULATOR_SUPPORT + uint8_t uchValue, uchReadValue; +#endif + + Board_initCfg arg = BOARD_INIT_MODULE_CLOCK | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_UART_STDIO; + Board_init(arg); + + /* Get the core number. */ + coreNum = 0; //CSL_chipReadReg (CSL_CHIP_DNUM); + +#ifdef SIMULATOR_SUPPORT +#warn MCBSP Digital Loopback example is not supported on SIMULATOR !!! + MCBSP_log ("MCBSP Digital Loopback example is not supported on SIMULATOR. Exiting!\n"); + return; +#else + MCBSP_log ("Debug(Core %d): Running MCBSP Digital Loopback example on the DEVICE\n", coreNum); +#endif + + /* Initialize the system only if the core was configured to do so. */ + if (coreNum == CORE_SYS_INIT) + { +#if 0 + MCBSP_log ("Debug(Core %d): System Initialization for MCBSP\n", coreNum); + /* Read FPGA register */ + if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum); + return; + } + /* Clear field for configuration */ + uchValue = (uchReadValue & (~0x3)); +#ifndef PLATFORM_FPGA_MCBSP_AMC_EN + uchValue |= 0x3; +#endif + /* Drive McBSP_AMC_EN# high. Output SLCLKs, TxCLKs, RxCLKs, FSTs, FSRs as Hi-Z. + * These clocks and syncs are tri-stated and McBSP is accessed over 80-pin header */ + if (0 != (platform_fpgaWriteConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, (uchValue)))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register WRITE failed \n", coreNum); + return; + } + + /* DEBUG: Verify if FPGA register is configured correctly */ + if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum); + return; + } + + if (uchValue != uchReadValue) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register setting failed \n", coreNum); + return; + } + else + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register is set to %d \n", coreNum, uchValue); + } +#endif + /* MCBSP Driver Initialization: This should always be called before + * invoking the MCBSP Driver. */ + mcbspInit(); + + /* Device Specific MCBSP Initializations */ + McbspDevice_init(); + + /* MCBSP Driver is operational at this time. */ + MCBSP_log ("Debug(Core %d): MCBSP Driver Initialization Done\n", coreNum); + + /* Write to the SHARED memory location at this point in time. The other cores cannot execute + * till the MCBSP Driver is up and running. */ + isMCBSPInitialized[0] = 1; + + /* The MCBSP IP block has been initialized. We need to writeback the cache here because it will + * ensure that the rest of the cores which are waiting for MCBSP to be initialized would now be + * woken up. */ + //CACHE_wbL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT); + Cache_wb ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH,0x7fff, 1); + } + else + { + /* All other cores need to wait for the MCBSP to be initialized before they proceed with the test. */ + MCBSP_log ("Debug(Core %d): Waiting for MCBSP to be initialized.\n", coreNum); + + /* All other cores loop around forever till the MCBSP is up and running. + * We need to invalidate the cache so that we always read this from the memory. */ + while (isMCBSPInitialized[0] == 0) + //CACHE_invL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT); + Cache_inv ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH, 0x7fff, 1); + + + MCBSP_log ("Debug(Core %d): MCBSP can now be used.\n", coreNum); + } + + /* Initialize EDMA3 library */ + hEdma[0] = edma3init(0, &edmaResult); + + if (edmaResult != EDMA3_DRV_SOK) + { + /* Report EDMA Error */ + MCBSP_log("Debug(Core %d): EDMA Driver Initialization FAILED\n", coreNum); + } + else + { + MCBSP_log("Debug(Core %d): EDMA Driver Initialization Done\n", coreNum); + } + + /* Create the Digital Loopback Application Task */ + Task_Params_init(&taskParams); + Task_create(mcbspDigLpbkApp, &taskParams, NULL); + + /* Start BIOS */ + BIOS_start(); + + return; +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ diff --git a/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg new file mode 100644 index 000000000..c639a820f --- /dev/null +++ b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg @@ -0,0 +1,80 @@ +/* + * Copyright 2012-2018 by Texas Instruments Incorporated. + * + * All rights reserved. Property of Texas Instruments Incorporated. + * Restricted rights to use, duplicate or disclose this code are + * granted through contract. + * + */ + +/* THIS FILE WAS GENERATED BY ti.sysbios.genx */ + +/* + * ======== mcbspMasterDigLpbk.cfg ======== + * + */ + +/* Load and use the required BIOS packages */ +var BIOS = xdc.useModule('ti.sysbios.BIOS'); +var Task = xdc.useModule('ti.sysbios.knl.Task'); +var cache = xdc.useModule('ti.sysbios.hal.Cache'); +var Idle = xdc.useModule('ti.sysbios.knl.Idle'); +var Queue = xdc.useModule('ti.sysbios.knl.Queue'); +var ECM = xdc.useModule('ti.sysbios.family.c64p.EventCombiner'); +var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc'); +var Memory = xdc.useModule('xdc.runtime.Memory'); +var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); + +/* Load and use the System Package */ +var System = xdc.useModule('xdc.runtime.System'); +var SysStd = xdc.useModule('xdc.runtime.SysStd'); + +/* Create a default system heap using ti.bios.HeapMem. */ +var heapMemParams1 = new HeapMem.Params; +heapMemParams1.size = 32768; +heapMemParams1.sectionName = "systemHeap"; +Program.global.heap0 = HeapMem.create(heapMemParams1); + +/* This is the default memory heap. */ +Memory.defaultHeapInstance = Program.global.heap0; + +/* + * Create and install logger for the whole system. + * Enable Event Groups here and registering of ISR for specific GEM INTC is done + * using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs + */ +ECM.eventGroupHwiNum[0] = 7; +ECM.eventGroupHwiNum[1] = 8; +ECM.eventGroupHwiNum[2] = 9; +ECM.eventGroupHwiNum[3] = 10; + +/* Load and use the mcbsp, EDMA, PlatformLib etc. packages */ +var Edma = xdc.loadPackage ("ti.sdo.edma3.drv.sample"); +var drv = xdc.loadPackage ("ti.sdo.edma3.drv"); +var rm = xdc.loadPackage ("ti.sdo.edma3.rm"); + +var devType = "k2g" +var mcbsp = xdc.useModule('ti.drv.mcbsp.Settings'); +mcbsp.deviceType = devType; + +/* Load the uart package */ +var Uart = xdc.loadPackage('ti.drv.uart'); +Uart.Settings.socType = devType; + +var Csl = xdc.useModule('ti.csl.Settings'); +Csl.deviceType = devType; +Csl.libProfile = "release"; + +/* Load the OSAL package */ +var osType = "tirtos" +var Osal = xdc.useModule('ti.osal.Settings'); +Osal.osType = osType; +Osal.socType = devType; + +/* Load the Board package and set the board name */ +var Board = xdc.loadPackage('ti.board'); +Board.Settings.boardName = "evmK2G"; + +/* Circular buffer size for System_printf() */ +System.SupportProxy = SysStd; + diff --git a/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd new file mode 100644 index 000000000..207553081 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd @@ -0,0 +1,9 @@ +SECTIONS +{ + .init_array: load >> L2SRAM + .mcbsp: load >> L2SRAM + .mcbspSharedMem: load >> L2SRAM + platform_lib: load >> L2SRAM + systemHeap: load >> L2SRAM +} + diff --git a/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c new file mode 100644 index 000000000..888513df5 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c @@ -0,0 +1,641 @@ +/** + * @file mcbspMasterDigLpbk_osal.c + * + * @brief + * This is the OS abstraction layer and is used by the MCBSP + * driver for the MCBSP Example Digital Loopback Application. + * + * \par + * ============================================================================ + * @n (C) Copyright 2012, Texas Instruments, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * \par +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if 0 +/* CSL Include Files */ +#include +#include +#include +#include +#endif +/* IPC includes */ +/* #include +#include +#include +#include */ + +/********************************************************************** + ************************** Local Definitions ************************* + **********************************************************************/ + +#define MCBSP_HW_SEM 1 +#define PLATFORM_SPI_HW_SEM 2 /**< SPI BUS arbitration - Used by platform library */ + +#ifdef MCBSP_LOOP_PING_PONG +#define MAX_MEM_MGR_ENTRIES 8 +#else +#define MAX_MEM_MGR_ENTRIES 4 +#endif + +typedef struct MEM_MGMT_ENTRY +{ + uint8_t* ptrMemory; + uint32_t isFree; +}MEM_MGMT_ENTRY; + +MEM_MGMT_ENTRY gDataBufferMemMgr[MAX_MEM_MGR_ENTRIES]; +int32_t gDataBufferMemMgrMaxSize = 0; + +/********************************************************************** + ************************** Global Variables ************************** + **********************************************************************/ +UInt32 malloc_counter = 0; +UInt32 free_counter = 0; + +/********************************************************************** + ************************** Extern Definitions ************************ + **********************************************************************/ + + +/********************************************************************** + **************************** OSAL Functions ************************** + **********************************************************************/ + +/** + * @b Description + * @n + * Utility function which converts a local address to global. + * + * @param[in] addr + * Local address to be converted + * + * @retval + * Global Address + */ +void *Osal_local2Global (void *addr) +{ + UInt32 corenum; + + /* Get the core number. */ + corenum = 0;//CSL_chipReadReg(CSL_CHIP_DNUM); + return addr; + + if(((UInt32)addr & 0xff000000) == 0) { + /* Compute the global address. */ + return ((void *)((UInt32)(addr) + (0x10000000 + (corenum*0x1000000)))); + } + else + return(addr); +} + +/** + * @b Description + * @n + * The function is used to allocate a memory block of the specified size. + * + * @param[in] numBytes + * Number of bytes to be allocated. + * + * @retval + * Allocated block address + */ +Void* Osal_mcbspMalloc(UInt32 numBytes) +{ + Error_Block errorBlock; + Void* ptr; + + /* Increment the allocation counter. */ + malloc_counter++; + + /* Allocate the memory. */ + ptr = Memory_alloc(NULL, numBytes, 0, &errorBlock); + + /* Return the allocated memory block. */ + return ptr; +} + +/** + * @b Description + * @n + * The function is used to clean up a specific memory block and is called + * from the MCBSP Driver. + * + * @param[in] ptr + * Pointer to the memory block to be cleaned up. + * @param[in] size + * Size of the memory block being cleaned up. + * + * @retval + * Not Applicable + */ +Void Osal_mcbspFree (Void* ptr, UInt32 size) +{ + /* Increment the free counter. */ + free_counter++; + Memory_free(NULL, ptr, size); +} + +/** + * @b Description + * @n + * The function is used to allocate a block of memory for all the data buffer + * operations. This function is called by the application. + * + * @param[in] numBuffers + * Number of data buffers + * @param[in] dataBufferSize + * Size of each data buffer + * + * @retval + * Success - 0 + * @retval + * Error - <0 + */ +int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize) +{ + Error_Block errorBlock; + uint8_t* ptrMemory; + uint32_t index; + + /* Allocate memory for all the data buffers */ + ptrMemory = (uint8_t*)Memory_alloc(NULL, MAX_MEM_MGR_ENTRIES*dataBufferSize, 128, &errorBlock); + if (ptrMemory == NULL) + return -1; + + /* Convert to a global address */ + ptrMemory = Osal_local2Global(ptrMemory); + + /* Now we chop up the memory and add it to the memory manager. */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Populate the data memory management entry. */ + gDataBufferMemMgr[index].isFree = 1; + gDataBufferMemMgr[index].ptrMemory = ptrMemory; + + /* Increment the memory to the next address */ + ptrMemory = ptrMemory + dataBufferSize; + } + + /* Remember the memory buffer size */ + gDataBufferMemMgrMaxSize = dataBufferSize; + + /* Memory Manager has been created. */ + return 0; +} + +/** + * @b Description + * @n + * The function is used to allocate a data buffer of the specified + * size. Data buffers should always be allocated from the global + * address space. + * + * @param[in] numBytes + * Number of bytes to be allocated. + * + * @retval + * Allocated block address + */ +Void* Osal_mcbspDataBufferMalloc(UInt32 numBytes) +{ + uint32_t index; + void* ptrMemory = NULL; + + /* Basic Validation: Ensure that the memory size requested is within range. */ + if (numBytes > gDataBufferMemMgrMaxSize) + return NULL; + + /* Increment the allocation counter. */ + malloc_counter++; + + /* Lock out interrupts */ + Hwi_disable(); + + /* Cycle through for a free entry. */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Check if the entry is free or not? */ + if (gDataBufferMemMgr[index].isFree == 1) + { + /* Entry was free. We can use it. */ + ptrMemory = gDataBufferMemMgr[index].ptrMemory; + + /* Mark the entry as used. */ + gDataBufferMemMgr[index].isFree = 0; + + /* We have found a match. */ + break; + } + } + + /* Unlock interrupts. */ + Hwi_enable(); + + /* Return the allocated memory. */ + return ptrMemory; +} + +/** + * @b Description + * @n + * The function is used to clean up a previously allocated data buffer + * block. All data buffers are in the global address space + * + * @param[in] ptr + * Pointer to the data buffer block to be cleaned up + * @param[in] size + * Size of the data buffer + * + * @retval + * Not Applicable + */ +void Osal_mcbspDataBufferFree(void* ptr, uint32_t numBytes) +{ + uint32_t index; + + /* Increment the free counter. */ + free_counter++; + + /* Lock out interrupts */ + Hwi_disable(); + + /* Cycle through and clean up */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Check if the entry is free or not? */ + if (gDataBufferMemMgr[index].ptrMemory == (uint8_t*)ptr) + { + /* Mark the entry as free. */ + gDataBufferMemMgr[index].isFree = 1; + + /* We have found a match. */ + break; + } + } + + /* Unlock interrupts. */ + Hwi_enable(); + return; +} + +/** + * @b Description + * @n + * The function is the MCBSP OSAL Logging API which logs + * the messages on the console. + * + * @param[in] fmt + * Formatted String. + * + * @retval + * Not Applicable + */ +Void Osal_mcbspLog( String fmt, ... ) +{ +} + +/** + * @b Description + * @n + * The function is used to create a critical section. + * + * @retval + * Semaphore Handle created + */ +Void* Osal_mcbspCreateSem(Void) +{ + return (Void*)Semaphore_create(0, NULL, NULL); +} + +/** + * @b Description + * @n + * The function is used to delete a critical section. + * + * @param[in] semHandle + * Semaphore handle to be deleted + * + * @retval + * Not Applicable + */ +Void Osal_mcbspDeleteSem(Void* semHandle) +{ + Semaphore_delete(semHandle); +} + +/** + * @b Description + * @n + * The function is used to pend on a semaphore + * + * @param[in] semHandle + * Semaphore handle on which the API will pend + * + * @retval + * Not Applicable + */ +Void Osal_mcbspPendSem(Void* semHandle) +{ + Semaphore_pend(semHandle, BIOS_WAIT_FOREVER); +} + +/** + * @b Description + * @n + * The function is used to post a semaphore + * + * @param[in] semHandle + * Semaphore handle which will be posted + * + * @retval + * Not Applicable + */ +Void Osal_mcbspPostSem(Void* semHandle) +{ + Semaphore_post(semHandle); +} + +/** + * @b Description + * @n + * This is the Multicore OSAL Implementation to protect the driver shared + * resources across multiple cores. + * + * @retval + * Semaphore Opaque Handle + */ +void* Osal_mcbspEnterMultipleCoreCriticalSection(void) +{ + /* Get the hardware semaphore */ + // while ((CSL_semAcquireDirect (MCBSP_HW_SEM)) == 0); + return NULL; +} + +/** + * @b Description + * @n + * The function is called to end the critical section which was protecting + * shared resources from access across multiple cores. + * + * @param[in] critSectHandle + * Semaphore opaque handle. + * + * @retval + * None + */ +Void Osal_mcbspExitMultipleCoreCriticalSection(Void* critSectHandle) +{ + //CSL_semReleaseSemaphore (MCBSP_HW_SEM); +} + +/** + * @b Description + * @n + * The function is used to provide critical section to prevent access of shared + * resources from single core and multiple threads. + * + * @param[in] drvHandle + * Driver Handle which needs critical section to protect its resources. + * + * @retval + * Opaque handle + */ +Void* Osal_mcbspEnterSingleCoreCriticalSection() +{ + /* Disable interrupts */ + return (Void*)Hwi_disable(); +} + +/** + * @b Description + * @n + * The function is called to end the critical section access of shared resources + * from single cores. + * + * @param[in] drvHandle + * Driver Handle which needed critical section to protect its resources. + * @param[in] critSectHandle + * Opaque handle retreived when the Single Core Protection Enter API was called + * + * @retval + * Not Applicable. + */ +Void Osal_mcbspExitSingleCoreCriticalSection(Void* critSectHandle) +{ + /* Driver Managed Configuration: We need to enable interrupts. */ + Hwi_enable(); +} + +/** + * @b Description + * @n + * The function is used by the MCBSP driver to indicate that + * its about to access a block of memory and we need to ensure + * that the cache contents for this block are invalidated before + * we try and use it. + * + * @param[in] ptr + * Pointer to the buffer which is being accessed + * @param[in] size + * Size of the buffer which is to be accessed. + * + * @retval + * None + */ +#include "ti/sysbios/hal/Cache.h" +void Osal_mcbspBeginMemAccess(void* ptr, uint32_t size) +{ + UInt key; + + /* Disable Interrupts */ + key = Hwi_disable(); + + /* Cleanup the prefetch buffer also. */ + //CSL_XMC_invalidatePrefetchBuffer(); + + /* Invalidate the cache. */ + //CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT); + + Cache_inv ((void *) ptr,size, 0x7fff, 1); + + /* Reenable Interrupts. */ + Hwi_restore(key); +} + +/** + * @b Description + * @n + * The function is used by the MCBSP driver to indicate that its + * ending access to a block of memory. We need to ensure that the + * contents of the cache are written back to the actual memory. + * + * @param[in] ptr + * Pointer to the buffer + * @param[in] size + * Size of the buffer + * + * @retval + * None + */ +void Osal_mcbspEndMemAccess(void* ptr, uint32_t size) +{ + UInt key; + + /* Disable Interrupts */ + key = Hwi_disable(); + + /* Writeback the cache. */ + //CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT); + Cache_wb ((void *) ptr,size, 0x7fff, 1); + /* Reenable Interrupts. */ + Hwi_restore(key); +} + +/** + * @brief The function is used by the MCBSP driver to test for an + * empty queue. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n TRUE - If the queue is empty + */ +Bool Osal_mcbspQueueEmpty(void* handle) +{ + return Queue_empty(handle); +} + +/** + * @brief The macro is used by the MCBSP driver to get an + * element from the front of queue. The function + * removes the element from the front of queue and + * returns a pointer to it. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n Handle (pointer) to former first element + */ +void* Osal_mcbspQueueGet(void* handle) +{ + return Queue_get(handle); +} + +/** + * @brief The macro is used by the MCBSP driver to put an + * element at the end of queue. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * @n elem - Pointer to new queue element + * + * Return Value + * @n None + */ +void Osal_mcbspQueuePut(void* handle, Mcbsp_QueueElem* elem) +{ + Queue_put(handle, (Queue_Elem *)elem); + return; +} + +/** + * @brief The macro is used by the MCBSP driver to wait 'n' + * bit clocks to ensure proper synchronization internally. + * + * Parameter + * @n nticks - Number of bit clocks to wait + * + * Return Value + * @n None + */ +void Osal_mcbspWaitNBitClocks(uint32_t nticks) +{ + //Task_sleep(nticks); + int i=0; + for (i=0; i<100; i++); + return; +} + +/* OSAL functions for Platform Library */ +uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment) +{ + return malloc(num_bytes); +} + +void Osal_platformFree (uint8_t *dataPtr, uint32_t num_bytes) +{ + /* Free up the memory */ + if (dataPtr) + { + free(dataPtr); + } +} + +void Osal_platformSpiCsEnter(void) +{ + /* Get the hardware semaphore. + * + * Acquire Multi core CPPI synchronization lock + */ + //while ((CSL_semAcquireDirect (PLATFORM_SPI_HW_SEM)) == 0); + + return; +} + +void Osal_platformSpiCsExit (void) +{ + /* Release the hardware semaphore + * + * Release multi-core lock. + */ + //CSL_semReleaseSemaphore (PLATFORM_SPI_HW_SEM); + + return; +} diff --git a/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/sample_k2g_cfg.c b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/sample_k2g_cfg.c new file mode 100644 index 000000000..36e4e45b8 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/k2g/MCBSPDigLpbk/sample_k2g_cfg.c @@ -0,0 +1,1217 @@ +/* + * sample_galileo_cfg.c + * + * Platform specific EDMA3 hardware related information like number of transfer + * controllers, various interrupt ids etc. It is used while interrupts + * enabling / disabling. It needs to be ported for different SoCs. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include + +/* Number of EDMA3 controllers present in the system */ +#define NUM_EDMA3_INSTANCES 2u +const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES; + +/* Number of DSPs present in the system */ +#define NUM_DSPS 1u +//const unsigned int numDsps = NUM_DSPS; + +#define CGEM_REG_START (0x01800000) + + +extern cregister volatile unsigned int DNUM; + +#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff)) + + +/* Determine the processor id by reading DNUM register. */ +unsigned short determineProcId() + { + volatile unsigned int *addr; + unsigned int core_no; + + /* Identify the core number */ + addr = (unsigned int *)(CGEM_REG_START+0x40000); + core_no = ((*addr) & 0x000F0000)>>16; + + return core_no; + } + +signed char* getGlobalAddr(signed char* addr) +{ + if (((unsigned int)addr & (unsigned int)0xFF000000) != 0) + { + return (addr); /* The address is already a global address */ + } + + return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr))); +} +/** Whether global configuration required for EDMA3 or not. + * This configuration should be done only once for the EDMA3 hardware by + * any one of the masters (i.e. DSPs). + * It can be changed depending on the use-case. + */ +unsigned int gblCfgReqdArray [NUM_DSPS] = { + 0, /* DSP#0 is Master, will do the global init */ + + }; + +unsigned short isGblConfigRequired(unsigned int dspNum) + { + return gblCfgReqdArray[dspNum]; + } + +/* Semaphore handles */ +EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL}; + + +/* Variable which will be used internally for referring number of Event Queues. */ +unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 2u}; + +/* Variable which will be used internally for referring number of TCs. */ +unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 2u}; + +/** + * Variable which will be used internally for referring transfer completion + * interrupt. Completion interrupts for all the shadow regions and all the + * EDMA3 controllers are captured since it is a multi-DSP platform. + */ +unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { + { + 0x88, 0x89, 0x8a, 0x8b, + 0x8c, 0x8d, 0x8e, 0x8f, + }, + { + 0x90, 0x91, 0x92, 0x93, + 0x94, 0x95, 0x96, 0x97, + }, + }; + +/** + * Variable which will be used internally for referring channel controller's + * error interrupt. + */ +unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {0x99, 0x9c}; + +/** + * Variable which will be used internally for referring transfer controllers' + * error interrupts. + */ +unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = { + { + 0xA0,0xA1, 0u, 0u, + 0u, 0u, 0u, 0u, + }, + { + 0xA4, 0xA5, 0u, 0u, + 0u, 0u, 0u, 0u, + }, + }; + +/* Driver Object Initialization Configuration */ +EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = + { + { + /* EDMA3 INSTANCE# 0 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 64u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 64u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 512u, + /** Total number of Event Queues in the EDMA3 Controller */ + 2u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ + 2u, + /** Number of Regions on this EDMA3 controller */ + 8u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 1u, + + /** Existence of memory protection feature */ + 1u, + + /** Global Register Region of CC Registers */ + (void *)0x02700000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x02760000u, + (void *)0x02768000u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + }, + /** Interrupt no. for Transfer Completion */ + 0x88, + /** Interrupt no. for CC Error */ + 0x99, + /** Interrupt no. for TCs Error */ + { + 0xA0, + 0xA1, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 128u, + 128u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, + 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u, + 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, + 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u, + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, EDMA3_RM_CH_NO_TCC_MAP, 4u, 5u, 6u, EDMA3_RM_CH_NO_TCC_MAP, + 8u, 9u, 10u, EDMA3_RM_CH_NO_TCC_MAP, 12u, 13u, 14u, EDMA3_RM_CH_NO_TCC_MAP, + 16u, 17u, 18u, EDMA3_RM_CH_NO_TCC_MAP, 20u, 21u, 22u, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, EDMA3_RM_CH_NO_TCC_MAP, + 32u, 33u, 34u, 35u, 36u, 37u, 38u, EDMA3_RM_CH_NO_TCC_MAP, + 40u, 41u, 42u, EDMA3_RM_CH_NO_TCC_MAP, 44u, 45u, 46u, EDMA3_RM_CH_NO_TCC_MAP, + 48u, 49u, 50u, 51u, 52u, 53u, 54u, EDMA3_RM_CH_NO_TCC_MAP, + 56u, 57u, 58u, 59u, 60u, 61u, 62u, EDMA3_RM_CH_NO_TCC_MAP + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + 0x0F000000u, + 0x0000000Fu + } + }, + + { + /* EDMA3 INSTANCE# 1 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 64u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 64u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 512u, + /** Total number of Event Queues in the EDMA3 Controller */ + 2u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ + 2u, + /** Number of Regions on this EDMA3 controller */ + 8u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 1u, + + /** Existence of memory protection feature */ + 1u, + + /** Global Register Region of CC Registers */ + (void *)0x02728000U, + /** Transfer Controller (TC) Registers */ + { + (void *)0x027b0000U, + (void *)0x027b8000U, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + }, + /** Interrupt no. for Transfer Completion */ + 0x90, + /** Interrupt no. for CC Error */ + 0x9c, + /** Interrupt no. for TCs Error */ + { + 0xA2, + 0xA3, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 64u, + 64u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, + 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u, + 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, + 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, + 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, + 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + 0x00000000u, + 0xFFF00000u + } + }, + + }; + +EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = + { + /* EDMA3 INSTANCE# 0 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000FFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x0f00000Fu, 0x0000000Fu}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000003u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x0f00000Fu, 0x000000FFu}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 */ + {0x00000003u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {0x00000003u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x000000F0u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x0000000Cu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x000000F0u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000030u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000030u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000F00u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000030u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000F00u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000300u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000300u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFF000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x0000F000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000C0u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x0000F000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00003000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00003000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + }, + + /* EDMA3 INSTANCE# 1 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000FFFFu, 0x00F00000u, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x0000FFFFu, 0x00F00000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000003u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x0000FFFFu, 0x00F00000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00003FFFu, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00003FFFu, 0x00000000u}, + }, + + /* Resources owned/reserved by region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 287 256 319 288 351 320 383 352 */ + 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFF0000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x0000000Cu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFF0000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x3FFF0000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x3FFF0000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 415 384 447 416 479 448 511 480 */ + 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x0000FFFFu}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000030u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x0000FFFFu}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00003FFFu}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00003FFFu}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0xFFFF0000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000C0u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0xFFFF0000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x3FFF0000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x3FFF0000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + }, + }; + +/* End of File */ diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/MCBSP_DigLpbk_lcdkOMAPL138_c674xExampleProject.txt b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/MCBSP_DigLpbk_lcdkOMAPL138_c674xExampleProject.txt new file mode 100644 index 000000000..6ef721e68 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/MCBSP_DigLpbk_lcdkOMAPL138_c674xExampleProject.txt @@ -0,0 +1,11 @@ +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/device/omapl138/src/device_mcbsp_loopback.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_cfg.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_int_reg.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_cs.c" +-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_init.c" + +-ccs.setCompilerOptions "-mv6740 --abi=eabi -g --define=SOC_OMAPL138 --define=LCDK_OMAPL138 -DMCBSP_DEBUG_TEMP -mv6740 -g --diag_warning=225 -I${PDK_INSTALL_PATH} -I${BIOS_INSTALL_PATH}/packages -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/include -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/include -I${PDK_INSTALL_PATH}/ti/drv/mcbsp -I${PDK_INSTALL_PATH}/ti/board" -rtsc.enableRtsc diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/bios6_edma3_drv_sample.h b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/bios6_edma3_drv_sample.h new file mode 100644 index 000000000..5fad8a74a --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/bios6_edma3_drv_sample.h @@ -0,0 +1,186 @@ +/* + * bios6_edma3_drv_sample.h + * + * Header file for the sample application for the EDMA3 Driver. + * + * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef _BIOS6_EDMA3_DRV_SAMPLE_H_ +#define _BIOS6_EDMA3_DRV_SAMPLE_H_ + +#include +#include + +/* Include EDMA3 Driver */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Cache line size on the underlying SoC. It needs to be modified + * for different cache line sizes, if the Cache is Enabled. + */ +#define EDMA3_CACHE_LINE_SIZE_IN_BYTES (128u) + +/* Error returned in case of buffers are not aligned on the cache boundary */ +#define EDMA3_NON_ALIGNED_BUFFERS_ERROR (-1) + +/* Error returned in case of data mismatch */ +#define EDMA3_DATA_MISMATCH_ERROR (-2) + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 Driver for the given EDMA3 controller + * and opens a EDMA3 driver instance. It internally calls EDMA3_DRV_create() and + * EDMA3_DRV_open(), in that order. + * + * It also registers interrupt handlers for various EDMA3 interrupts like + * transfer completion or error interrupts. + * + * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0) + * \param errorCode [IN/OUT] Error code while opening DRV instance + * \return EDMA3_DRV_Handle: If successfully opened, the API will return the + * associated driver's instance handle. + */ +EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode); + +/** + * \brief EDMA3 De-initialization + * + * This function de-initializes the EDMA3 Driver for the given EDMA3 controller + * and closes the previously opened EDMA3 driver instance. It internally calls + * EDMA3_DRV_close and EDMA3_DRV_delete(), in that order. + * + * It also un-registers the previously registered interrupt handlers for various + * EDMA3 interrupts. + * + * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0) + * \param hEdma [IN] EDMA3 Driver handle, returned while using + * edma3init(). + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma); + + +/** + * \brief EDMA3 Cache Invalidate + * + * This function invalidates the D cache. + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * \brief EDMA3 Cache Flush + * + * This function flushes (cleans) the Cache + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 driver/RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to receive the handle to just created + * semaphore. + * \return EDMA3_DRV_SOK if successful, else a suitable error code. + */ +EDMA3_DRV_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem); + + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_DRV_SOK if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _BIOS6_EDMA3_DRV_SAMPLE_H_ */ + diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.c b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.c new file mode 100644 index 000000000..86516a1d5 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.c @@ -0,0 +1,978 @@ +/* + * mcbspMasterDigLpbk.c + * + * This file contains the test / demo code to demonstrate the McBSP driver + * master functionality using Digital Loopback setup. The file configures + * the EVM in master mode. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/* ========================================================================== */ +/* INCLUDE FILES */ +/* ========================================================================== */ + +#include +#include +#include +#include +#include +#include + +#include + +/* Include EDMA3 Driver */ +#include + +/* CSL Chip Functional Layer */ +//#include + +/* CSL Cache Functional Layer */ +//#include + +/* CSL CPINTC Include Files. */ +//#include + +/* MCBSP Driver Include File. */ +#include +#include +#include +#include + +/* PlatformLib Include File */ +//#include + + +/* ========================================================================== */ +/* EXTERNAL FUNCTIONS */ +/* ========================================================================== */ + +extern EDMA3_DRV_Handle edma3init(unsigned int edma3Id, EDMA3_DRV_Result *); + +extern void McbspDevice_init(void); + +extern int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize); + +extern void McbspXmtInterrupt_init(void *mcbspTxChan); +extern void McbspRcvInterrupt_init(void *mcbspRxChan); + +extern Board_STATUS Board_init(Board_initCfg); + +/* FPGA Configuration Misc-1 Register offset */ +#define MCBSP_FPGA_MISC_REG_OFFSET (0x0C) + +/* ========================================================================== */ +/* MACRO DEFINTIONS */ +/* ========================================================================== */ + +#define NUM_BUFS 2 /* Max of buffers used in each direction */ +#define FRAMESIZE 40 /* e.g 5 ms 8 KHz samples */ +#define NUM_OF_ENABLED_CHANNELS 8 /* Number of slots to be used */ +#define NUM_OF_MAX_CHANNELS 128 /* Maximum number of time slots available based on clock settings */ +#define BUFSIZE (NUM_OF_ENABLED_CHANNELS * FRAMESIZE) /* Total buffer size per frame */ + +/* Defines the core number responsible for system initialization. */ +#define CORE_SYS_INIT 0 +/* Number of iterations to execute test: Only applicable to INTERNAL CLOCK Loopback test */ +#define NUM_OF_ITERATIONS 10 + +/* Number of MCBSP Frame structures used for submit channel */ +#define NUM_OF_MCBSP_FRAMES 2 + +/* Number of buffers initially submitted to Mcbsp lld: Only applicable to + External clock test ; Note: This should be set to 2*/ +#define INIT_SUBMIT_Q_CNT 2 + +/*============================================================================*/ +/* GLOBAL VARIABLES */ +/*============================================================================*/ + +/* Shared Memory Variable to ensure synchronizing MCBSP initialization + * with all the other cores. */ +/* Created an array to pad the cache line with MCBSP_CACHE_LENGTH size */ +#pragma DATA_ALIGN (isMCBSPInitialized, MCBSP_MAX_CACHE_ALIGN) +#pragma DATA_SECTION (isMCBSPInitialized, ".mcbspSharedMem"); +volatile Uint32 isMCBSPInitialized[(MCBSP_CACHE_LENGTH / sizeof(Uint32))] = { 0 }; + +/* Handle to the EDMA driver instance */ +#pragma DATA_ALIGN (hEdma, MCBSP_MAX_CACHE_ALIGN) +EDMA3_DRV_Handle hEdma[(MCBSP_CACHE_LENGTH / sizeof(EDMA3_DRV_Handle))] = { NULL }; + +/* Handle to MCBSP driver instance */ +typedef void* Mcbsp_DevHandle; +Mcbsp_DevHandle hMcbspDev; + +/* Handle to MCBSP driver channel instance */ +typedef void* Mcbsp_ChanHandle; +Mcbsp_ChanHandle hMcbspTxChan; +Mcbsp_ChanHandle hMcbspRxChan; + +/* Core Number Identifier */ +UInt32 coreNum = 0xFFFF; + +/* Array to hold the pointer to the allocated buffers */ +void* bufRx[NUM_BUFS]; +void* bufTx[NUM_BUFS]; + +#ifdef MCBSP_LOOP_PING_PONG +/* Ping pong buffers used to submit to Mcbsp lld, which will be used in a loop */ +void* bufRxPingPong[INIT_SUBMIT_Q_CNT]; +void* bufTxPingPong[INIT_SUBMIT_Q_CNT]; +#endif +/* Global Error call back function prototype */ +void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3); + +/* Variables to indicate status of EDMA TX and RX requests */ +volatile uint32_t edmaTxDone = 0; +volatile uint32_t edmaRxDone = 0; +/* Global variables to track number of buffers submitted, number of iterations, error counts etc */ +int rxSubmitCount=0, txSubmitCount=0; +uint32_t num_iterations=0; +uint32_t num_rx_Call_backs=0, num_tx_Call_backs=0, dummy_call_backs=0; +uint32_t rxunderflowcnt=0, txunderflowcnt=0; +uint32_t errBuffCount=0; +/* Debug variables */ +volatile int debugVar=1; /* This can be used to maintain a while loop, If set to 0 will exit loop */ +volatile int debugCommand=1; /* This can be used to set to value below to send command to restart channel */ + +#define DEBUG_COMMAND_RESTART_CHANNELS 1 +/** + * \brief Mcbsp Sample rate generator default parameters. + * + */ +Mcbsp_srgConfig mcbspSrgCfg = +{ + FALSE, /* No gsync to be used as input is not CLKS */ + Mcbsp_ClkSPol_RISING_EDGE, /* Dont care as input clock is not clks */ + Mcbsp_SrgClk_CLKCPU, /* McBSP internal clock to be used */ + 166666667, /* Mcbsp internal clock frequency(PLL-SYSCLK6) */ + 0 /* frame sync pulse width (val+1) is used */ +}; + +/** + * \brief Mcbsp device creation default parameters. + * + */ +const Mcbsp_Params Mcbsp_PARAMS = +{ + Mcbsp_DevMode_McBSP, /* Use the device as MCBSP */ + Mcbsp_OpMode_DMAINTERRUPT, /* Use DMA mode of operation */ + TRUE, /* cache coherency taken care of by driver */ + Mcbsp_EmuMode_FREE, /* Emulation mode free is to be enabled */ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_Loopback_DISABLE, /* Loop back mode disabled */ +#else + Mcbsp_Loopback_ENABLE, /* Loop back mode enabled */ +#endif + &mcbspSrgCfg, /* sample rate generator configuration */ + NULL, /* TX pending buffer queue from application */ + NULL, /* TX floating buffer queue in DMA */ + NULL, /* RX pending buffer queue from application */ + NULL /* RX floating buffer queue in DMA */ +}; + +#pragma DATA_ALIGN(loopTxJob, MCBSP_MAX_CACHE_ALIGN) +static Int32 loopTxJob[16] = { + /* Filling with Mu law silence pattern : Can be any user defined pattern */ + 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, + 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f +}; +#pragma DATA_ALIGN(loopRxJob, MCBSP_MAX_CACHE_ALIGN) +static Int32 loopRxJob[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/**< settings to configure the TX or RX hardware sections */ +Mcbsp_DataConfig mcbspChanConfigTx = +{ + Mcbsp_Phase_SINGLE, + Mcbsp_WordLength_8, + Mcbsp_WordLength_8, /* Dont care for single phase*/ + NUM_OF_MAX_CHANNELS, + NUM_OF_MAX_CHANNELS, // Only used with dual phase + Mcbsp_FrmSync_DETECT, +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_DataDelay_0_BIT, +#else + Mcbsp_DataDelay_1_BIT, +#endif + Mcbsp_Compand_OFF_MSB_FIRST, + Mcbsp_BitReversal_DISABLE, + Mcbsp_IntMode_ON_SYNCERR, + Mcbsp_RxJust_RZF, /* Dont care for TX */ + Mcbsp_DxEna_OFF +}; + +/**< settings to configure the TX or RX hardware sections */ +Mcbsp_DataConfig mcbspChanConfigRx = +{ + Mcbsp_Phase_SINGLE, + Mcbsp_WordLength_8, + Mcbsp_WordLength_8, /* Dont care for single phase*/ + NUM_OF_MAX_CHANNELS, + NUM_OF_MAX_CHANNELS, // Only used with dual phase + Mcbsp_FrmSync_DETECT, +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_DataDelay_0_BIT, +#else + Mcbsp_DataDelay_1_BIT, +#endif + Mcbsp_Compand_OFF_MSB_FIRST, + Mcbsp_BitReversal_DISABLE, + Mcbsp_IntMode_ON_SYNCERR, + Mcbsp_RxJust_RZF, /* Dont care for TX */ + Mcbsp_DxEna_OFF +}; +/**< clock setup for the TX section */ +Mcbsp_ClkSetup mcbspClkConfigTx = +{ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_FsClkMode_EXTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_EXTERNAL, +#else + Mcbsp_FsClkMode_INTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_INTERNAL, +#endif + Mcbsp_FsPol_ACTIVE_HIGH, + Mcbsp_ClkPol_RISING_EDGE +}; + +/**< clock setup for the RX section */ +Mcbsp_ClkSetup mcbspClkConfigRx = +{ +#ifdef MCBSP_EXTERNAL_CLOCK + Mcbsp_FsClkMode_EXTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_EXTERNAL, +#else + Mcbsp_FsClkMode_INTERNAL, + 8000, /* 8KHz */ + Mcbsp_TxRxClkMode_INTERNAL, +#endif + Mcbsp_FsPol_ACTIVE_HIGH, + Mcbsp_ClkPol_FALLING_EDGE +}; + +/**< Multi channel setup */ +Mcbsp_McrSetup mcbspMultiChanCtrl = +{ + Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED, + Mcbsp_PartitionMode_CHAN_0_15, + Mcbsp_PartitionMode_CHAN_16_31, + Mcbsp_PartitionMode_2 +}; + + +Mcbsp_ChanParams mcbspChanparamTx = +{ + Mcbsp_WordLength_8, /* wordlength configured */ + &loopTxJob[0], /* loop job buffer internal */ + 8, /* user loopjob length */ + mcbsp_GblErrCallback, /* global error callback */ + NULL, /* edma Handle */ + 1, /* EDMA event queue */ + 8, /* hwi number */ + Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED, + TRUE, /* FIFO mode enabled */ + &mcbspChanConfigTx, /* channel configuration */ + &mcbspClkConfigTx, /* clock configuration */ + &mcbspMultiChanCtrl, /* multi channel control */ + 0x7531, /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */ + 0x00, + 0x00, + 0x00, + NUM_OF_ENABLED_CHANNELS /* Total number of channels enabled*/ +}; + +Mcbsp_ChanParams mcbspChanparamRx = +{ + Mcbsp_WordLength_8, /* wordlength configured */ + &loopRxJob[0], /* loop job buffer internal */ + 8, /* user loopjob length */ + mcbsp_GblErrCallback, /* global error callback */ + NULL, /* edma Handle */ + 1, /* EDMA event queue */ + 8, /* hwi number */ + Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED, + TRUE, /* FIFO mode enabled */ + &mcbspChanConfigRx, /* channel configuration */ + &mcbspClkConfigRx, /* clock configuration */ + &mcbspMultiChanCtrl, /* multi channel control */ + 0x7531, /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */ + 0x00, + 0x00, + 0x00, + NUM_OF_ENABLED_CHANNELS /* Total number of channels enabled*/ +}; + + +/* ========================================================================== */ +/* FUNCTION DEFINITIONS */ +/* ========================================================================== */ + +/* + * This is the application's callback function. The driver will + * call this function whenever an EDMA I/O operation is over. + * + */ +void mcbspAppCallback(void* arg, Mcbsp_IOBuf *ioBuf) +{ + int32_t mode; + int32_t *pmode = (int32_t *)arg; + + mode = *pmode; + if (mode == MCBSP_MODE_OUTPUT) + { + if(ioBuf) { + num_tx_Call_backs++; + edmaTxDone = 1; + }else + txunderflowcnt++; + } + else if (mode == MCBSP_MODE_INPUT) + { + if(ioBuf) { + num_rx_Call_backs++; + edmaRxDone = 1; + }else + rxunderflowcnt++; + }else + dummy_call_backs++; + return; +} + +/* + * This is the application's Global error callback function + */ +void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3) +{ + MCBSP_log ("Debug(Core %d): ERROR callback called SPCR: %x", coreNum, spcr_read); +} + +/* + * \brief This function demostrates the use of Mcbsp using digital loopback + * communication setup. + * + * \param None + * + * \return None + */ +void mcbspDigLpbkApp(UArg arg0, UArg arg1) +{ + /**< Mcbsp device params */ + Mcbsp_Params mcbspParams; + + /**< Queue to hold the pending packets received from the application */ + Queue_Struct txQueuePendingList, rxQueuePendingList; + /**< Queue to manage floating packets in DMA */ + Queue_Struct txQueueFloatingList, rxQueueFloatingList; + + uint32_t count = 0, tempCount = 0; + int32_t status = 0, retval = 0; + int32_t txChanMode = MCBSP_MODE_OUTPUT; + int32_t rxChanMode = MCBSP_MODE_INPUT; + uint32_t mcbspTxDone = 0, mcbspRxDone = 0; + Mcbsp_IOBuf txFrame[NUM_OF_MCBSP_FRAMES], rxFrame[NUM_OF_MCBSP_FRAMES]; + int txFrameIndex=0, rxFrameIndex=0; + int init_count=0; +#ifdef MCBSP_LOOP_PING_PONG + int pingPongIndex=0; +#endif + + /* Initialize the OSAL */ + if (Osal_dataBufferInitMemory(BUFSIZE) < 0) + { + MCBSP_log ("Debug(Core %d): Error: Unable to initialize the OSAL. \n", coreNum); + return; + } + + /* update EDMA3 handle to channel parameters */ + mcbspChanparamTx.edmaHandle = hEdma[0]; + mcbspChanparamRx.edmaHandle = hEdma[0]; + + /* create the pending and floating queue for the TX channel */ + Queue_construct(&txQueuePendingList, NULL); + Queue_construct(&txQueueFloatingList, NULL); + + /* create the pending and floating queue for the RX channel */ + Queue_construct(&rxQueuePendingList, NULL); + Queue_construct(&rxQueueFloatingList, NULL); + + + mcbspParams = Mcbsp_PARAMS; + mcbspParams.txQPendingList = &txQueuePendingList; + mcbspParams.txQFloatingList = &txQueueFloatingList; + mcbspParams.rxQPendingList = &rxQueuePendingList; + mcbspParams.rxQFloatingList = &rxQueueFloatingList; + + + /* Bind the driver instance with device instance */ + status = mcbspBindDev(&hMcbspDev, coreNum, &mcbspParams); + + if (status != MCBSP_STATUS_COMPLETED) + { + MCBSP_log ("Debug(Core %d): MCBSP LLD Bind Device Failed\n", coreNum); + return; + } + + /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */ + if(mcbspChanparamRx.userLoopJobBuffer) + mcbspChanparamRx.userLoopJobBuffer = (void *)Mcbsp_osalLocal2Global(mcbspChanparamRx.userLoopJobBuffer); + + /* Create a RX channel for receiving */ + status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum); + return; + } + + /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */ + if(mcbspChanparamTx.userLoopJobBuffer) + mcbspChanparamTx.userLoopJobBuffer = Mcbsp_osalLocal2Global(mcbspChanparamTx.userLoopJobBuffer); + + /* Create a TX channel for the transmission */ + status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum); + return; + } + + /* Register mcbsp interrupts */ + //McbspRcvInterrupt_init(hMcbspRxChan); + //McbspXmtInterrupt_init(hMcbspTxChan); + + /* create the buffers required for the TX and RX operations */ + for (count = 0; count < (NUM_BUFS); count++) + { + bufTx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + bufRx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + + if (bufTx[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Tx Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + if (bufRx[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Rx Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* create the ping pong buffers required for the TX and RX operations */ + for (count = 0; count < (NUM_BUFS); count++) + { + bufRxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + bufTxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE); + + if (bufTxPingPong[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Tx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + if (bufRxPingPong[count] == NULL) + { + MCBSP_log ("Debug(Core %d): Error: Rx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count); + return; + } + } +#endif + /* Fill the buffers with known data and transmit the same and + check if the same pattern is received */ + for (count = 0; count < (NUM_BUFS); count++) + { + memset((uint8_t *)bufTx[count], 0, BUFSIZE); + for (tempCount = 0; tempCount < BUFSIZE; tempCount++) + { + ((uint8_t *)bufTx[count])[tempCount] = (tempCount % 0x100); + } + } + MCBSP_log ("Debug(Core %d): If required to restart set debugCommand variable to %d\n", coreNum, DEBUG_COMMAND_RESTART_CHANNELS); + +restart_mcbsp_point: + txFrameIndex=0; + rxFrameIndex=0; + init_count=0; +#ifdef MCBSP_EXTERNAL_CLOCK + /* Initial loading of ping ping buffers */ + for(init_count =0 ; init_count < INIT_SUBMIT_Q_CNT; init_count++) + { +#ifdef MCBSP_LOOP_PING_PONG + memset((uint8_t *)bufRxPingPong[init_count], 0, BUFSIZE); + + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRxPingPong[init_count]; +#else + memset((uint8_t *)bufRx[init_count], 0, BUFSIZE); + + + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRx[init_count]; +#endif + + rxFrame[rxFrameIndex].size = BUFSIZE; + rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan; + rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED; + rxFrame[rxFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, init_count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, init_count); +#endif + } + rxFrameIndex++; + rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex; + + rxSubmitCount++; + + /* TX frame processing */ + txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE; +#ifdef MCBSP_LOOP_PING_PONG + txFrame[txFrameIndex].addr = (void*)bufTxPingPong[init_count]; +#else + txFrame[txFrameIndex].addr = (void*)bufTx[init_count]; +#endif + txFrame[txFrameIndex].size = BUFSIZE; + txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan; + txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED; + txFrame[txFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: TX buffer #%d submission FAILED\n", coreNum, init_count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): TX buffer #%d submission is submitted to MCBSP driver\n", coreNum, init_count); +#endif + } + txFrameIndex++; + txFrameIndex = (txFrameIndex >=(NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex; + + txSubmitCount++; + } + + /* Wait for TX and RX processing to complete */ + while (1) + { + if (edmaTxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Iteration-%d frames are transmitted to TX path\n", coreNum, count); +#endif + edmaTxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 1; + } + if (edmaRxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Iteration-%d frames are received from RX path\n", coreNum, count); +#endif + edmaRxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 1; + } + if ((mcbspTxDone == 1) && (mcbspRxDone == 1)) + { + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + break; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* Change ping Pong Index */ + init_count=0; +#endif +#endif /* MCBSP_EXTERNAL_CLOCK */ + + /* Start main loop to iterate through frames */ + while(debugVar) + { + /* submit frames to the driver */ + for (count = init_count; count < NUM_BUFS; count++) + { +#ifdef MCBSP_EXTERNAL_CLOCK +/* With External clock the data coming from the RX side is copied to loop back to the Tx side */ + memcpy((uint8_t *)bufTx[count], (uint8_t *)bufRx[count], BUFSIZE); +#endif +#ifdef MCBSP_LOOP_PING_PONG + memset((uint8_t *)bufRxPingPong[pingPongIndex], 0, BUFSIZE); +#else + memset((uint8_t *)bufRx[count], 0, BUFSIZE); + /* RX frame processing */ + rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ; + rxFrame[rxFrameIndex].addr = (void*)bufRx[count]; + rxFrame[rxFrameIndex].size = BUFSIZE; + rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan; + rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED; + rxFrame[rxFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, count); +#endif + } + rxFrameIndex++; + rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex; +#endif + rxSubmitCount++; +#ifdef MCBSP_LOOP_PING_PONG + /* Copy buffer from buffer to ping pong buffer*/ + memcpy((uint8_t *)bufTxPingPong[pingPongIndex], (uint8_t *)bufTx[count],BUFSIZE); +#else + /* TX frame processing */ + txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE; + txFrame[txFrameIndex].addr = (void*)bufTx[count]; + txFrame[txFrameIndex].size = BUFSIZE; + txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan; + txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED; + txFrame[txFrameIndex].misc = 1; /* reserved - used in callback to indicate asynch packet */ + + status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]); + if (status != MCBSP_STATUS_PENDING) + { + MCBSP_log ("Debug(Core %d): Error: TX buffer #%d submission FAILED\n", coreNum, count); + retval = 1; + } + else + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): TX buffer #%d is submitted to MCBSP driver\n", coreNum, count); +#endif + } + txFrameIndex++; + txFrameIndex = (txFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex; +#endif + txSubmitCount++; + + /* Wait for TX and RX processing to complete */ + while (1) + { + if (edmaTxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Buffer #-%d is transmitted to TX path\n", coreNum, count); +#endif + edmaTxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 1; + } + if (edmaRxDone == 1) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log ("Debug(Core %d): EDMA -> Buffer #-%d is received from RX path\n", coreNum, count); +#endif + edmaRxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 1; + } + if ((mcbspTxDone == 1) && (mcbspRxDone == 1)) + { + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + break; + } + } +#ifdef MCBSP_LOOP_PING_PONG + /* Change ping Pong Index */ + pingPongIndex=(pingPongIndex)?0:1; + + /* Copy buffer from buffer to other buffer*/ + memcpy((void*)bufRx[count], (uint8_t *)bufRxPingPong[pingPongIndex],BUFSIZE); +#endif + /* compare buffer contents */ + for (tempCount = 0; tempCount < BUFSIZE; tempCount++) + { + if (((char *)bufTx[count])[tempCount] != ((char *)bufRx[count])[tempCount]) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log("Debug(Core %d): Error: TX and RX frame data DOES NOT match in Buffer #-%d\n", + coreNum, count); + MCBSP_log("Debug(Core %d): Error: Buffer index = %d, Tx data = %d, Rx data = %d\n", coreNum, + tempCount, ((char *)bufTx[count])[tempCount], ((char *)bufRx[count])[tempCount]); +#endif + errBuffCount++; + break; + } + } + if (tempCount >= BUFSIZE) + { +#ifdef MCBSP_APP_VERBOSE + MCBSP_log("Debug(Core %d): TX and RX frames data match in iteration-%d !!!\n", coreNum, count); +#endif + } + } + init_count=0; + num_iterations++; +#ifndef MCBSP_EXTERNAL_CLOCK + if(num_iterations >= NUM_OF_ITERATIONS) + break; +#endif + switch(debugCommand) + { + case DEBUG_COMMAND_RESTART_CHANNELS: + debugCommand=0; + /* Close channel and reopen */ + /* Delete RX channel */ + status = mcbspDeleteChan(hMcbspRxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum); + return; + } + + /* Delete TX channel*/ + status = mcbspDeleteChan(hMcbspTxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum); + return; + } + /* Create a RX channel for receiving */ + status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum); + return; + } + + /* Create a TX channel for the transmission */ + status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum); + return; + } + edmaTxDone = 0; /* Reset for next iteration */ + edmaRxDone = 0; /* Reset for next iteration */ + mcbspTxDone = 0; /* Reset for next iteration */ + mcbspRxDone = 0; /* Reset for next iteration */ + goto restart_mcbsp_point; + + default: + debugCommand=0; + break; + + } + + } + + if ((errBuffCount == 0 ) & (retval ==0)) + { + MCBSP_log("Debug(Core %d): MCBSP Digital Loopback Application completed successfully : "\ + "Num iterations %d Num buffers per iteration %d!!!\n", + coreNum, num_iterations, NUM_BUFS); + MCBSP_log("\n All tests have passed \n"); + } + else + { + MCBSP_log("Debug(Core %d): MCBSP Digital Loopback application FAILED : "\ + "Num iterations %d Num buffers per iteration %d Failed buffers %d!!!\n", + coreNum, num_iterations, NUM_BUFS, errBuffCount); + } + + /* Delete RX channel */ + status = mcbspDeleteChan(hMcbspRxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum); + return; + } + + /* Delete TX channel*/ + status = mcbspDeleteChan(hMcbspTxChan); + if (MCBSP_STATUS_COMPLETED != status) + { + MCBSP_log ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum); + return; + } + return; +} + +/* + * \brief Void main(Void) + * + * Main function of the sample application. This function calls the + * function to configure the mcbsp instance. + * + * \param None + * + * \return None + */ +#include "ti/sysbios/hal/Cache.h" + +Void main(Void) +{ + Task_Params taskParams; + EDMA3_DRV_Result edmaResult = 0; +#ifdef SIMULATOR_SUPPORT + uint8_t uchValue, uchReadValue; +#endif + + Board_initCfg arg = BOARD_INIT_MODULE_CLOCK | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_UART_STDIO; + Board_init(arg); + + /* Get the core number. */ + coreNum = 0; //CSL_chipReadReg (CSL_CHIP_DNUM); + +#ifdef SIMULATOR_SUPPORT +#warn MCBSP Digital Loopback example is not supported on SIMULATOR !!! + MCBSP_log ("MCBSP Digital Loopback example is not supported on SIMULATOR. Exiting!\n"); + return; +#else + MCBSP_log ("Debug(Core %d): Running MCBSP Digital Loopback example on the DEVICE\n", coreNum); +#endif + + /* Initialize the system only if the core was configured to do so. */ + if (coreNum == CORE_SYS_INIT) + { +#if 0 + MCBSP_log ("Debug(Core %d): System Initialization for MCBSP\n", coreNum); + /* Read FPGA register */ + if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum); + return; + } + /* Clear field for configuration */ + uchValue = (uchReadValue & (~0x3)); +#ifndef PLATFORM_FPGA_MCBSP_AMC_EN + uchValue |= 0x3; +#endif + /* Drive McBSP_AMC_EN# high. Output SLCLKs, TxCLKs, RxCLKs, FSTs, FSRs as Hi-Z. + * These clocks and syncs are tri-stated and McBSP is accessed over 80-pin header */ + if (0 != (platform_fpgaWriteConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, (uchValue)))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register WRITE failed \n", coreNum); + return; + } + + /* DEBUG: Verify if FPGA register is configured correctly */ + if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue))) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum); + return; + } + + if (uchValue != uchReadValue) + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register setting failed \n", coreNum); + return; + } + else + { + MCBSP_log ("Debug(Core %d): FPGA McBSP_AMC_EN# register is set to %d \n", coreNum, uchValue); + } +#endif + /* MCBSP Driver Initialization: This should always be called before + * invoking the MCBSP Driver. */ + mcbspInit(); + + /* Device Specific MCBSP Initializations */ + McbspDevice_init(); + + /* MCBSP Driver is operational at this time. */ + MCBSP_log ("Debug(Core %d): MCBSP Driver Initialization Done\n", coreNum); + + /* Write to the SHARED memory location at this point in time. The other cores cannot execute + * till the MCBSP Driver is up and running. */ + isMCBSPInitialized[0] = 1; + + /* The MCBSP IP block has been initialized. We need to writeback the cache here because it will + * ensure that the rest of the cores which are waiting for MCBSP to be initialized would now be + * woken up. */ + //CACHE_wbL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT); + Cache_wb ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH,0x7fff, 1); + } + else + { + /* All other cores need to wait for the MCBSP to be initialized before they proceed with the test. */ + MCBSP_log ("Debug(Core %d): Waiting for MCBSP to be initialized.\n", coreNum); + + /* All other cores loop around forever till the MCBSP is up and running. + * We need to invalidate the cache so that we always read this from the memory. */ + while (isMCBSPInitialized[0] == 0) + //CACHE_invL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT); + Cache_inv ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH, 0x7fff, 1); + + + MCBSP_log ("Debug(Core %d): MCBSP can now be used.\n", coreNum); + } + + /* Initialize EDMA3 library */ + hEdma[0] = edma3init(0, &edmaResult); + + if (edmaResult != EDMA3_DRV_SOK) + { + /* Report EDMA Error */ + MCBSP_log("Debug(Core %d): EDMA Driver Initialization FAILED\n", coreNum); + } + else + { + MCBSP_log("Debug(Core %d): EDMA Driver Initialization Done\n", coreNum); + } + + /* Create the Digital Loopback Application Task */ + Task_Params_init(&taskParams); + Task_create(mcbspDigLpbkApp, &taskParams, NULL); + + /* Start BIOS */ + BIOS_start(); + + return; +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg new file mode 100644 index 000000000..44dedf67b --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg @@ -0,0 +1,78 @@ +/* + * Copyright 2012-2018 by Texas Instruments Incorporated. + * + * All rights reserved. Property of Texas Instruments Incorporated. + * Restricted rights to use, duplicate or disclose this code are + * granted through contract. + * + */ + +/* THIS FILE WAS GENERATED BY ti.sysbios.genx */ + +/* + * ======== mcbspMasterDigLpbk.cfg ======== + * + */ + +/* Load and use the required BIOS packages */ +var BIOS = xdc.useModule('ti.sysbios.BIOS'); +var Task = xdc.useModule('ti.sysbios.knl.Task'); +var cache = xdc.useModule('ti.sysbios.hal.Cache'); +var Idle = xdc.useModule('ti.sysbios.knl.Idle'); +var Queue = xdc.useModule('ti.sysbios.knl.Queue'); +var ECM = xdc.useModule('ti.sysbios.family.c64p.EventCombiner'); +//var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc'); +var Memory = xdc.useModule('xdc.runtime.Memory'); +var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); + +/* Load and use the System Package */ +var System = xdc.useModule('xdc.runtime.System'); +var SysStd = xdc.useModule('xdc.runtime.SysStd'); + +/* Create a default system heap using ti.bios.HeapMem. */ +var heapMemParams1 = new HeapMem.Params; +heapMemParams1.size = 32768; +heapMemParams1.sectionName = "systemHeap"; +Program.global.heap0 = HeapMem.create(heapMemParams1); + +/* This is the default memory heap. */ +Memory.defaultHeapInstance = Program.global.heap0; + +/* + * Create and install logger for the whole system. + * Enable Event Groups here and registering of ISR for specific GEM INTC is done + * using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs + */ +ECM.eventGroupHwiNum[0] = 7; +ECM.eventGroupHwiNum[1] = 8; +ECM.eventGroupHwiNum[2] = 9; +ECM.eventGroupHwiNum[3] = 10; + +/* Load and use the mcbsp, EDMA, PlatformLib etc. packages */ +var Edma = xdc.loadPackage('ti.sdo.edma3.drv'); + +var devType = "omapl138" +var mcbsp = xdc.useModule('ti.drv.mcbsp.Settings'); +mcbsp.deviceType = devType; + +/* Load the uart package */ +var Uart = xdc.loadPackage('ti.drv.uart'); +Uart.Settings.socType = devType; + +var Csl = xdc.useModule('ti.csl.Settings'); +Csl.deviceType = devType; +Csl.libProfile = "release"; + +/* Load the OSAL package */ +var osType = "tirtos" +var Osal = xdc.useModule('ti.osal.Settings'); +Osal.osType = osType; +Osal.socType = devType; + +/* Load the Board package and set the board name */ +var Board = xdc.loadPackage('ti.board'); +Board.Settings.boardName = "lcdkOMAPL138"; + +/* Circular buffer size for System_printf() */ +System.SupportProxy = SysStd; + diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd new file mode 100644 index 000000000..6021dd060 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd @@ -0,0 +1,9 @@ +SECTIONS +{ + .init_array: load >> IRAM + .mcbsp: load >> DDR + .mcbspSharedMem: load >> DDR + platform_lib: load >> DDR + systemHeap: load >> IRAM +} + diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c new file mode 100644 index 000000000..6cda4227c --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c @@ -0,0 +1,639 @@ +/** + * @file mcbspMasterDigLpbk_osal.c + * + * @brief + * This is the OS abstraction layer and is used by the MCBSP + * driver for the MCBSP Example Digital Loopback Application. + * + * \par + * ============================================================================ + * @n (C) Copyright 2012, Texas Instruments, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * \par +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if 0 +/* CSL Include Files */ +#include +#include +#include +#include +#endif +/* IPC includes */ +#include +#include +#include +#include + +/********************************************************************** + ************************** Local Definitions ************************* + **********************************************************************/ + +#define MCBSP_HW_SEM 1 +#define PLATFORM_SPI_HW_SEM 2 /**< SPI BUS arbitration - Used by platform library */ + +#ifdef MCBSP_LOOP_PING_PONG +#define MAX_MEM_MGR_ENTRIES 8 +#else +#define MAX_MEM_MGR_ENTRIES 4 +#endif + +typedef struct MEM_MGMT_ENTRY +{ + uint8_t* ptrMemory; + uint32_t isFree; +}MEM_MGMT_ENTRY; + +MEM_MGMT_ENTRY gDataBufferMemMgr[MAX_MEM_MGR_ENTRIES]; +int32_t gDataBufferMemMgrMaxSize = 0; + +/********************************************************************** + ************************** Global Variables ************************** + **********************************************************************/ +UInt32 malloc_counter = 0; +UInt32 free_counter = 0; + +/********************************************************************** + ************************** Extern Definitions ************************ + **********************************************************************/ + + +/********************************************************************** + **************************** OSAL Functions ************************** + **********************************************************************/ + +/** + * @b Description + * @n + * Utility function which converts a local address to global. + * + * @param[in] addr + * Local address to be converted + * + * @retval + * Global Address + */ +void *Osal_local2Global (void *addr) +{ + UInt32 corenum; + + /* Get the core number. */ + corenum = 0;//CSL_chipReadReg(CSL_CHIP_DNUM); + return addr; + + if(((UInt32)addr & 0xff000000) == 0) { + /* Compute the global address. */ + return ((void *)((UInt32)(addr) + (0x10000000 + (corenum*0x1000000)))); + } + else + return(addr); +} + +/** + * @b Description + * @n + * The function is used to allocate a memory block of the specified size. + * + * @param[in] numBytes + * Number of bytes to be allocated. + * + * @retval + * Allocated block address + */ +Void* Osal_mcbspMalloc(UInt32 numBytes) +{ + Error_Block errorBlock; + Void* ptr; + + /* Increment the allocation counter. */ + malloc_counter++; + + /* Allocate the memory. */ + ptr = Memory_alloc(NULL, numBytes, 0, &errorBlock); + + /* Return the allocated memory block. */ + return ptr; +} + +/** + * @b Description + * @n + * The function is used to clean up a specific memory block and is called + * from the MCBSP Driver. + * + * @param[in] ptr + * Pointer to the memory block to be cleaned up. + * @param[in] size + * Size of the memory block being cleaned up. + * + * @retval + * Not Applicable + */ +Void Osal_mcbspFree (Void* ptr, UInt32 size) +{ + /* Increment the free counter. */ + free_counter++; + Memory_free(NULL, ptr, size); +} + +/** + * @b Description + * @n + * The function is used to allocate a block of memory for all the data buffer + * operations. This function is called by the application. + * + * @param[in] numBuffers + * Number of data buffers + * @param[in] dataBufferSize + * Size of each data buffer + * + * @retval + * Success - 0 + * @retval + * Error - <0 + */ +int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize) +{ + Error_Block errorBlock; + uint8_t* ptrMemory; + uint32_t index; + + /* Allocate memory for all the data buffers */ + ptrMemory = (uint8_t*)Memory_alloc(NULL, MAX_MEM_MGR_ENTRIES*dataBufferSize, 128, &errorBlock); + if (ptrMemory == NULL) + return -1; + + /* Convert to a global address */ + ptrMemory = Osal_local2Global(ptrMemory); + + /* Now we chop up the memory and add it to the memory manager. */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Populate the data memory management entry. */ + gDataBufferMemMgr[index].isFree = 1; + gDataBufferMemMgr[index].ptrMemory = ptrMemory; + + /* Increment the memory to the next address */ + ptrMemory = ptrMemory + dataBufferSize; + } + + /* Remember the memory buffer size */ + gDataBufferMemMgrMaxSize = dataBufferSize; + + /* Memory Manager has been created. */ + return 0; +} + +/** + * @b Description + * @n + * The function is used to allocate a data buffer of the specified + * size. Data buffers should always be allocated from the global + * address space. + * + * @param[in] numBytes + * Number of bytes to be allocated. + * + * @retval + * Allocated block address + */ +Void* Osal_mcbspDataBufferMalloc(UInt32 numBytes) +{ + uint32_t index; + void* ptrMemory = NULL; + + /* Basic Validation: Ensure that the memory size requested is within range. */ + if (numBytes > gDataBufferMemMgrMaxSize) + return NULL; + + /* Increment the allocation counter. */ + malloc_counter++; + + /* Lock out interrupts */ + Hwi_disable(); + + /* Cycle through for a free entry. */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Check if the entry is free or not? */ + if (gDataBufferMemMgr[index].isFree == 1) + { + /* Entry was free. We can use it. */ + ptrMemory = gDataBufferMemMgr[index].ptrMemory; + + /* Mark the entry as used. */ + gDataBufferMemMgr[index].isFree = 0; + + /* We have found a match. */ + break; + } + } + + /* Unlock interrupts. */ + Hwi_enable(); + + /* Return the allocated memory. */ + return ptrMemory; +} + +/** + * @b Description + * @n + * The function is used to clean up a previously allocated data buffer + * block. All data buffers are in the global address space + * + * @param[in] ptr + * Pointer to the data buffer block to be cleaned up + * @param[in] size + * Size of the data buffer + * + * @retval + * Not Applicable + */ +void Osal_mcbspDataBufferFree(void* ptr, uint32_t numBytes) +{ + uint32_t index; + + /* Increment the free counter. */ + free_counter++; + + /* Lock out interrupts */ + Hwi_disable(); + + /* Cycle through and clean up */ + for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++) + { + /* Check if the entry is free or not? */ + if (gDataBufferMemMgr[index].ptrMemory == (uint8_t*)ptr) + { + /* Mark the entry as free. */ + gDataBufferMemMgr[index].isFree = 1; + + /* We have found a match. */ + break; + } + } + + /* Unlock interrupts. */ + Hwi_enable(); + return; +} + +/** + * @b Description + * @n + * The function is the MCBSP OSAL Logging API which logs + * the messages on the console. + * + * @param[in] fmt + * Formatted String. + * + * @retval + * Not Applicable + */ +Void Osal_mcbspLog( String fmt, ... ) +{ +} + +/** + * @b Description + * @n + * The function is used to create a critical section. + * + * @retval + * Semaphore Handle created + */ +Void* Osal_mcbspCreateSem(Void) +{ + return (Void*)Semaphore_create(0, NULL, NULL); +} + +/** + * @b Description + * @n + * The function is used to delete a critical section. + * + * @param[in] semHandle + * Semaphore handle to be deleted + * + * @retval + * Not Applicable + */ +Void Osal_mcbspDeleteSem(Void* semHandle) +{ + Semaphore_delete(semHandle); +} + +/** + * @b Description + * @n + * The function is used to pend on a semaphore + * + * @param[in] semHandle + * Semaphore handle on which the API will pend + * + * @retval + * Not Applicable + */ +Void Osal_mcbspPendSem(Void* semHandle) +{ + Semaphore_pend(semHandle, BIOS_WAIT_FOREVER); +} + +/** + * @b Description + * @n + * The function is used to post a semaphore + * + * @param[in] semHandle + * Semaphore handle which will be posted + * + * @retval + * Not Applicable + */ +Void Osal_mcbspPostSem(Void* semHandle) +{ + Semaphore_post(semHandle); +} + +/** + * @b Description + * @n + * This is the Multicore OSAL Implementation to protect the driver shared + * resources across multiple cores. + * + * @retval + * Semaphore Opaque Handle + */ +void* Osal_mcbspEnterMultipleCoreCriticalSection(void) +{ + /* Get the hardware semaphore */ + // while ((CSL_semAcquireDirect (MCBSP_HW_SEM)) == 0); + return NULL; +} + +/** + * @b Description + * @n + * The function is called to end the critical section which was protecting + * shared resources from access across multiple cores. + * + * @param[in] critSectHandle + * Semaphore opaque handle. + * + * @retval + * None + */ +Void Osal_mcbspExitMultipleCoreCriticalSection(Void* critSectHandle) +{ + //CSL_semReleaseSemaphore (MCBSP_HW_SEM); +} + +/** + * @b Description + * @n + * The function is used to provide critical section to prevent access of shared + * resources from single core and multiple threads. + * + * @param[in] drvHandle + * Driver Handle which needs critical section to protect its resources. + * + * @retval + * Opaque handle + */ +Void* Osal_mcbspEnterSingleCoreCriticalSection() +{ + /* Disable interrupts */ + return (Void*)Hwi_disable(); +} + +/** + * @b Description + * @n + * The function is called to end the critical section access of shared resources + * from single cores. + * + * @param[in] drvHandle + * Driver Handle which needed critical section to protect its resources. + * @param[in] critSectHandle + * Opaque handle retreived when the Single Core Protection Enter API was called + * + * @retval + * Not Applicable. + */ +Void Osal_mcbspExitSingleCoreCriticalSection(Void* critSectHandle) +{ + /* Driver Managed Configuration: We need to enable interrupts. */ + Hwi_enable(); +} + +/** + * @b Description + * @n + * The function is used by the MCBSP driver to indicate that + * its about to access a block of memory and we need to ensure + * that the cache contents for this block are invalidated before + * we try and use it. + * + * @param[in] ptr + * Pointer to the buffer which is being accessed + * @param[in] size + * Size of the buffer which is to be accessed. + * + * @retval + * None + */ +#include "ti/sysbios/hal/Cache.h" +void Osal_mcbspBeginMemAccess(void* ptr, uint32_t size) +{ + UInt key; + + /* Disable Interrupts */ + key = Hwi_disable(); + + /* Cleanup the prefetch buffer also. */ + //CSL_XMC_invalidatePrefetchBuffer(); + + /* Invalidate the cache. */ + //CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT); + + Cache_inv ((void *) ptr,size, 0x7fff, 1); + + /* Reenable Interrupts. */ + Hwi_restore(key); +} + +/** + * @b Description + * @n + * The function is used by the MCBSP driver to indicate that its + * ending access to a block of memory. We need to ensure that the + * contents of the cache are written back to the actual memory. + * + * @param[in] ptr + * Pointer to the buffer + * @param[in] size + * Size of the buffer + * + * @retval + * None + */ +void Osal_mcbspEndMemAccess(void* ptr, uint32_t size) +{ + UInt key; + + /* Disable Interrupts */ + key = Hwi_disable(); + + /* Writeback the cache. */ + //CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT); + Cache_wb ((void *) ptr,size, 0x7fff, 1); + /* Reenable Interrupts. */ + Hwi_restore(key); +} + +/** + * @brief The function is used by the MCBSP driver to test for an + * empty queue. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n TRUE - If the queue is empty + */ +Bool Osal_mcbspQueueEmpty(void* handle) +{ + return Queue_empty(handle); +} + +/** + * @brief The macro is used by the MCBSP driver to get an + * element from the front of queue. The function + * removes the element from the front of queue and + * returns a pointer to it. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n Handle (pointer) to former first element + */ +void* Osal_mcbspQueueGet(void* handle) +{ + return Queue_get(handle); +} + +/** + * @brief The macro is used by the MCBSP driver to put an + * element at the end of queue. + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * @n elem - Pointer to new queue element + * + * Return Value + * @n None + */ +void Osal_mcbspQueuePut(void* handle, Mcbsp_QueueElem* elem) +{ + Queue_put(handle, (Queue_Elem *)elem); + return; +} + +/** + * @brief The macro is used by the MCBSP driver to wait 'n' + * bit clocks to ensure proper synchronization internally. + * + * Parameter + * @n nticks - Number of bit clocks to wait + * + * Return Value + * @n None + */ +void Osal_mcbspWaitNBitClocks(uint32_t nticks) +{ + Task_sleep(nticks); + return; +} + +/* OSAL functions for Platform Library */ +uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment) +{ + return malloc(num_bytes); +} + +void Osal_platformFree (uint8_t *dataPtr, uint32_t num_bytes) +{ + /* Free up the memory */ + if (dataPtr) + { + free(dataPtr); + } +} + +void Osal_platformSpiCsEnter(void) +{ + /* Get the hardware semaphore. + * + * Acquire Multi core CPPI synchronization lock + */ + //while ((CSL_semAcquireDirect (PLATFORM_SPI_HW_SEM)) == 0); + + return; +} + +void Osal_platformSpiCsExit (void) +{ + /* Release the hardware semaphore + * + * Release multi-core lock. + */ + //CSL_semReleaseSemaphore (PLATFORM_SPI_HW_SEM); + + return; +} diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_cs.c b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_cs.c new file mode 100644 index 000000000..92c20ab46 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_cs.c @@ -0,0 +1,420 @@ +/* + * sample_cs.c + * + * Sample functions showing the implementation of critical section entry/exit + * routines and various semaphore related routines (all BIOS6 depenedent). + * These implementations MUST be provided by the user / application, using the + * EDMA3 driver, for its correct functioning. + * + * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include +#include +#include + +#include "bios6_edma3_drv_sample.h" + +extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS]; +extern unsigned int ccErrorInt[]; +extern unsigned int tcErrorInt[][EDMA3_MAX_TC]; + +/** + * Shadow Region on which the executable is running. Its value is + * populated with the DSP Instance Number here in this case. + */ +extern unsigned int region_id; + +/** + * \brief EDMA3 OS Protect Entry + * + * This function saves the current state of protection in 'intState' + * variable passed by caller, if the protection level is + * EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of + * protection. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is disabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the + * Transfer Controller number whose interrupt needs to be disabled. + * + * \param level is numeric identifier of the desired degree of protection. + * \param intState is memory location where current state of protection is + * saved for future use while restoring it via edma3OsProtectExit() (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectEntry (unsigned int edma3InstanceId, + int level, unsigned int *intState) + { + if (((level == EDMA3_OS_PROTECT_INTERRUPT) + || (level == EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR)) + && (intState == NULL)) + { + return; + } + else + { + switch (level) + { + /* Disable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + *intState = Hwi_disable(); + break; + + /* Disable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_disable(); + break; + + /* Disable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_disableEvent(ccXferCompInt[edma3InstanceId][region_id]); + break; + + /* Disable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_disableEvent(ccErrorInt[edma3InstanceId]); + break; + + /* Disable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch (*intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Disable the corresponding interrupt */ + EventCombiner_disableEvent(tcErrorInt[edma3InstanceId][*intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + } + + +/** + * \brief EDMA3 OS Protect Exit + * + * This function undoes the protection enforced to original state + * as is specified by the variable 'intState' passed, if the protection + * level is EDMA3_OS_PROTECT_INTERRUPT. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is enabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the + * Transfer Controller number whose interrupt needs to be enabled. + * \param level is numeric identifier of the desired degree of protection. + * \param intState is original state of protection at time when the + * corresponding edma3OsProtectEntry() was called (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectExit (unsigned int edma3InstanceId, + int level, unsigned int intState) + { + switch (level) + { + /* Enable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + Hwi_restore(intState); + break; + + /* Enable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_enable(); + break; + + /* Enable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_enableEvent(ccXferCompInt[edma3InstanceId][region_id]); + break; + + /* Enable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_enableEvent(ccErrorInt[edma3InstanceId]); + break; + + /* Enable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch (intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Enable the corresponding interrupt */ + EventCombiner_enableEvent(tcErrorInt[edma3InstanceId][intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + + +/** + * \brief EDMA3 Cache Invalidate + * + * This function invalidates the D cache. + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr, + unsigned int num_bytes) + { + EDMA3_DRV_Result cacheInvResult = EDMA3_DRV_SOK; + + /* Verify whether the start address is cache aligned or not */ + if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u)) != 0) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n", + EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif + cacheInvResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR; + } + else + { + Cache_inv((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE); + } + + return cacheInvResult; +} + + + +/** + * \brief EDMA3 Cache Flush + * + * This function flushes (cleans) the Cache + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr, + unsigned int num_bytes) + { + EDMA3_DRV_Result cacheFlushResult = EDMA3_DRV_SOK; + + /* Verify whether the start address is cache aligned or not */ + if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u)) != 0) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n", + EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif + cacheFlushResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR; + } + else + { + Cache_wb((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE); + } + + return cacheFlushResult; +} + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 driver/RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to recieve the handle to just created + * semaphore + * \return EDMA3_DRV_SOK if succesful, else a suitable error code. + */ +EDMA3_DRV_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem) + { + EDMA3_DRV_Result semCreateResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semCreateResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + *hSem = (EDMA3_OS_Sem_Handle)Semaphore_create(initVal, semParams, NULL); + if ( (*hSem) == NULL ) + { + semCreateResult = EDMA3_DRV_E_SEMAPHORE; + } + } + + return semCreateResult; + } + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_DRV_SOK if succesful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_DRV_Result semDeleteResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semDeleteResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + Semaphore_delete((Semaphore_Handle *)&hSem); + } + + return semDeleteResult; + } + + +/** + * \brief EDMA3 OS Semaphore Take + * + * This function takes a semaphore token if available. + * If a semaphore is unavailable, it blocks currently + * running thread in wait (for specified duration) for + * a free semaphore. + * \param hSem [IN] is the handle of the specified semaphore + * \param mSecTimeout [IN] is wait time in milliseconds + * \return EDMA3_DRV_Result if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout) + { + EDMA3_DRV_Result semTakeResult = EDMA3_DRV_SOK; + unsigned short semPendResult; + + if(NULL == hSem) + { + semTakeResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + semPendResult = Semaphore_pend(hSem, mSecTimeout); + if (semPendResult == FALSE) + { + semTakeResult = EDMA3_DRV_E_SEMAPHORE; + } + } + + return semTakeResult; + } + + +/** + * \brief EDMA3 OS Semaphore Give + * + * This function gives or relinquishes an already + * acquired semaphore token + * \param hSem [IN] is the handle of the specified semaphore + * \return EDMA3_DRV_Result if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_DRV_Result semGiveResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semGiveResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + Semaphore_post(hSem); + } + + return semGiveResult; + } + +/* End of File */ + diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_init.c b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_init.c new file mode 100644 index 000000000..54fc95574 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_init.c @@ -0,0 +1,223 @@ +/* + * sample_init.c + * + * Sample Initialization for the EDMA3 Driver for BIOS 6 based applications. + * It should be MANDATORILY done once before EDMA3 usage. + * + * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include + +#include "bios6_edma3_drv_sample.h" + +/** @brief EDMA3 Driver Instance specific Semaphore handle */ +extern EDMA3_OS_Sem_Handle semHandle[]; + +/** To Register the ISRs with the underlying OS, if required. */ +extern void registerEdma3Interrupts (unsigned int edma3Id); +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +extern void unregisterEdma3Interrupts (unsigned int edma3Id); + +/* To find out the DSP# */ +extern unsigned short determineProcId(); + +/** + * To check whether the global EDMA3 configuration is required or not. + * It should be done ONCE by any of the masters present in the system. + * This function checks whether the global configuration is required by the + * current master or not. In case of many masters, it should be done only + * by one of the masters. Hence this function will return TRUE only once + * and FALSE for all other masters. + */ +extern unsigned short isGblConfigRequired(unsigned int dspNum); + +/** + * DSP instance number on which the executable is running. Its value is + * determined by reading the processor specific register DNUM. + */ +unsigned int dsp_num; + +/** + * Shadow Region on which the executable is runnig. Its value is populated + * with the DSP Instance Number here in this case. + */ +unsigned int region_id; + +/* Number of EDMA3 controllers present in the system */ +extern const unsigned int numEdma3Instances; + +/* External Global Configuration Structure */ +extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[]; + +/* External Instance Specific Configuration Structure */ +extern EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[][EDMA3_MAX_REGIONS]; + +#if defined (CHIP_TI814X) +extern EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, unsigned int edma3Id); +#endif + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 Driver and registers the + * interrupt handlers. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM; + Semaphore_Params semParams; + EDMA3_DRV_GblConfigParams *globalConfig = NULL; + EDMA3_DRV_InitConfig initCfg; + EDMA3_RM_MiscParam miscParam; + EDMA3_DRV_Handle hEdma = NULL; + + if ((edma3Id >= numEdma3Instances) || (errorCode == NULL)) + return hEdma; + + /* DSP instance number */ + dsp_num = determineProcId(); +// dsp_num = 0; /* selection of region ID */ + + globalConfig = &sampleEdma3GblCfgParams[edma3Id]; + + /* Configure it as master, if required */ + miscParam.isSlave = isGblConfigRequired(dsp_num); + edma3Result = EDMA3_DRV_create (edma3Id, globalConfig , + (void *)&miscParam); + + if (edma3Result == EDMA3_DRV_SOK) + { + /** + * Driver Object created successfully. + * Create a semaphore now for driver instance. + */ + Semaphore_Params_init(&semParams); + + initCfg.drvSemHandle = NULL; + edma3Result = edma3OsSemCreate(1, &semParams, &initCfg.drvSemHandle); + } + + if (edma3Result == EDMA3_DRV_SOK) + { + /* Save the semaphore handle for future use */ + semHandle[edma3Id] = initCfg.drvSemHandle; + + /* Driver instance specific config NULL */ + initCfg.drvInstInitConfig = NULL; + +#ifndef EDMA3_DRV_USE_DEF_RM_CFG + /* Hook for running examples with default RM config */ + /* configuration structure for the Driver */ + initCfg.drvInstInitConfig = &sampleInstInitConfig[edma3Id][dsp_num]; +#endif + + initCfg.isMaster = TRUE; + /* Choose shadow region according to the DSP# */ + initCfg.regionId = (EDMA3_RM_RegionId)dsp_num; + /*Saving the regionId for using it in the sample_cs.c file */ + region_id = (EDMA3_RM_RegionId)dsp_num; + /* Driver instance specific config NULL */ + + initCfg.gblerrCb = NULL; + initCfg.gblerrData = NULL; + + /* Open the Driver Instance */ + hEdma = EDMA3_DRV_open (edma3Id, (void *) &initCfg, &edma3Result); + } + +#if defined (CHIP_TI814X) + { + if(hEdma && (edma3Result == EDMA3_DRV_SOK)) + { + edma3Result = sampleInitXbarEvt(hEdma, edma3Id); + } + } +#endif + if(hEdma && (edma3Result == EDMA3_DRV_SOK)) + { + /** + * Register Interrupt Handlers for various interrupts + * like transfer completion interrupt, CC error + * interrupt, TC error interrupts etc, if required. + */ + registerEdma3Interrupts(edma3Id); + } + + *errorCode = edma3Result; + return hEdma; + } + + +/** + * \brief EDMA3 De-initialization + * + * This function removes the EDMA3 Driver instance and unregisters the + * interrupt handlers. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM; + + /* Unregister Interrupt Handlers first */ + unregisterEdma3Interrupts(edma3Id); + + /* Delete the semaphore */ + edma3Result = edma3OsSemDelete(semHandle[edma3Id]); + + if (EDMA3_DRV_SOK == edma3Result ) + { + /* Make the semaphore handle as NULL. */ + semHandle[edma3Id] = NULL; + + /* Now, close the EDMA3 Driver Instance */ + edma3Result = EDMA3_DRV_close (hEdma, NULL); + } + + if (EDMA3_DRV_SOK == edma3Result ) + { + /* Now, delete the EDMA3 Driver Object */ + edma3Result = EDMA3_DRV_delete (edma3Id, NULL); + } + + return edma3Result; + } + +/* End of File */ + diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_cfg.c b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_cfg.c new file mode 100644 index 000000000..5e670ca80 --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_cfg.c @@ -0,0 +1,1391 @@ +/* + * sample_omapl138_cfg.c + * + * SoC specific EDMA3 hardware related information like number of transfer + * controllers, various interrupt ids etc. It is used while interrupts + * enabling / disabling. It needs to be ported for different SoCs. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include + +/* Number of EDMA3 controllers present in the system */ +#define NUM_EDMA3_INSTANCES 2u +const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES; + +/* Number of DSPs present in the system */ +#define NUM_DSPS 1u +const unsigned int numDsps = NUM_DSPS; + +/* Determine the processor id by reading DNUM register. */ +unsigned short determineProcId() +{ + return 1; +} + +signed char* getGlobalAddr(signed char* addr) +{ + return (addr); /* The address is already a global address */ +} +unsigned short isGblConfigRequired(unsigned int dspNum) +{ + (void) dspNum; + + return 1; +} + +/* Semaphore handles */ +EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL}; + +/** Number of PaRAM Sets available */ +#define EDMA3_NUM_PARAMSET (128u) +/** Number of TCCS available */ +#define EDMA3_NUM_TCC (32u) + +/** Number of Event Queues available */ +#define EDMA3_0_NUM_EVTQUE (2u) +#define EDMA3_1_NUM_EVTQUE (1u) + +/** Number of Transfer Controllers available */ +#define EDMA3_0_NUM_TC (2u) +#define EDMA3_1_NUM_TC (1u) + +#ifdef __TMS470__ /* values for ARM */ + +#else /* values for DSP */ +/** Interrupt no. for Transfer Completion */ +#define EDMA3_0_CC_XFER_COMPLETION_INT (8u) +#define EDMA3_1_CC_XFER_COMPLETION_INT (91u) + +/** Interrupt no. for CC Error */ +#define EDMA3_0_CC_ERROR_INT (56u) +#define EDMA3_1_CC_ERROR_INT (92u) + +/** Interrupt no. for TCs Error */ +#define EDMA3_0_TC0_ERROR_INT (57u) +#define EDMA3_0_TC1_ERROR_INT (58u) +#define EDMA3_0_TC2_ERROR_INT (0u) +#define EDMA3_0_TC3_ERROR_INT (0u) +#define EDMA3_0_TC4_ERROR_INT (0u) +#define EDMA3_0_TC5_ERROR_INT (0u) +#define EDMA3_0_TC6_ERROR_INT (0u) +#define EDMA3_0_TC7_ERROR_INT (0u) + +#define EDMA3_1_TC0_ERROR_INT (93u) +#define EDMA3_1_TC1_ERROR_INT (0u) +#define EDMA3_1_TC2_ERROR_INT (0u) +#define EDMA3_1_TC3_ERROR_INT (0u) +#define EDMA3_1_TC4_ERROR_INT (0u) +#define EDMA3_1_TC5_ERROR_INT (0u) +#define EDMA3_1_TC6_ERROR_INT (0u) +#define EDMA3_1_TC7_ERROR_INT (0u) + +/** + * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different + * ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. + * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding + * to transfer completion interrupt. + * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding + * to CC error interrupts. + * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding + * to TC error interrupts. + */ +/* EDMA 0 */ +#define EDMA3_0_HWI_INT_XFER_COMP (7u) +#define EDMA3_0_HWI_INT_CC_ERR (8u) +#define EDMA3_0_HWI_INT_TC0_ERR (8u) +#define EDMA3_0_HWI_INT_TC1_ERR (8u) + +/* EDMA 1 */ +#define EDMA3_1_HWI_INT_XFER_COMP (9u) +#define EDMA3_1_HWI_INT_CC_ERR (9u) +#define EDMA3_1_HWI_INT_TC0_ERR (9u) + +#endif /* __TMS470__ */ + +/** + * \brief Mapping of DMA channels 0-31 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ + /* 31 0 */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFF3FF3FFu) +#define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x3F07FFFFu) + +/** + * \brief Mapping of DMA channels 32-63 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ +/* DMA channels 32-63 DOES NOT exist in omapl138. */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u) +#define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u) + +/* Variable which will be used internally for referring number of Event Queues*/ +unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = { + EDMA3_0_NUM_EVTQUE, + EDMA3_1_NUM_EVTQUE + }; + +/* Variable which will be used internally for referring number of TCs. */ +unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = { + EDMA3_0_NUM_TC, + EDMA3_1_NUM_TC + }; + +/** + * Variable which will be used internally for referring transfer completion + * interrupt. + */ +unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { + { + 0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u, + }, + { + 0u, EDMA3_1_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u, + }, + }; + +/** + * Variable which will be used internally for referring channel controller's + * error interrupt. + */ +unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = { + EDMA3_0_CC_ERROR_INT, + EDMA3_1_CC_ERROR_INT + }; + +/** + * Variable which will be used internally for referring transfer controllers' + * error interrupts. + */ +unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = { + { + EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT, + EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT, + EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT, + EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT, + }, + { + EDMA3_1_TC0_ERROR_INT, EDMA3_1_TC1_ERROR_INT, + EDMA3_1_TC2_ERROR_INT, EDMA3_1_TC3_ERROR_INT, + EDMA3_1_TC4_ERROR_INT, EDMA3_1_TC5_ERROR_INT, + EDMA3_1_TC6_ERROR_INT, EDMA3_1_TC7_ERROR_INT, + } + }; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = { + EDMA3_0_HWI_INT_XFER_COMP, + EDMA3_1_HWI_INT_XFER_COMP + }; + +unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = { + EDMA3_0_HWI_INT_CC_ERR, + EDMA3_1_HWI_INT_CC_ERR + }; + +unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = { + { + EDMA3_0_HWI_INT_TC0_ERR, + EDMA3_0_HWI_INT_TC1_ERR, + }, + { + EDMA3_1_HWI_INT_TC0_ERR, + } + }; + +/* Driver Object Initialization Configuration */ +EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = +{ + { + /* EDMA3 INSTANCE# 0 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 32u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 32u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 128u, + /** Total number of Event Queues in the EDMA3 Controller */ + 2u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/ + 2u, + /** Number of Regions on this EDMA3 controller */ + 4u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 0u, + + /** Existence of memory protection feature */ + 0u, + + /** Global Register Region of CC Registers */ + (void *)0x01C00000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x01C08000u, + (void *)0x01C08400u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + EDMA3_0_CC_XFER_COMPLETION_INT, + /** Interrupt no. for CC Error */ + EDMA3_0_CC_ERROR_INT, + /** Interrupt no. for TCs Error */ + { + EDMA3_0_TC0_ERROR_INT, + EDMA3_0_TC1_ERROR_INT, + EDMA3_0_TC2_ERROR_INT, + EDMA3_0_TC3_ERROR_INT, + EDMA3_0_TC4_ERROR_INT, + EDMA3_0_TC5_ERROR_INT, + EDMA3_0_TC6_ERROR_INT, + EDMA3_0_TC7_ERROR_INT + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + /* DMA channels 32-63 DOES NOT exist in OMAPL138. */ + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, + 4u, 5u, 6u, 7u, + 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, + 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, + 28u, 29u, 30u, 31u, + /* DMA channels 32-63 DOES NOT exist in OMAPL138. */ + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 + } + }, + + { + /* EDMA3 INSTANCE# 1 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 32u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 32u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 128u, + /** Total number of Event Queues in the EDMA3 Controller */ + 1u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ + 1u, + /** Number of Regions on this EDMA3 controller */ + 4u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 0u, + + /** Existence of memory protection feature */ + 0u, + + /** Global Register Region of CC Registers */ + (void *)0x01E30000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x01E38000u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + EDMA3_1_CC_XFER_COMPLETION_INT, + /** Interrupt no. for CC Error */ + EDMA3_1_CC_ERROR_INT, + /** Interrupt no. for TCs Error */ + { + EDMA3_1_TC0_ERROR_INT, + EDMA3_1_TC1_ERROR_INT, + EDMA3_1_TC2_ERROR_INT, + EDMA3_1_TC3_ERROR_INT, + EDMA3_1_TC4_ERROR_INT, + EDMA3_1_TC5_ERROR_INT, + EDMA3_1_TC6_ERROR_INT, + EDMA3_1_TC7_ERROR_INT, + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + /* DMA channels 32-63 DOES NOT exist in OMAPL138. */ + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, + 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, + 12u, 13u, 14u, 15u, + 16u, 17u, 18u, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, + 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + /* DMA channels 32-63 DOES NOT exist in OMAPL138. */ + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0, + EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1 + } + }, +}; + + +/* Driver Instance Initialization Configuration */ +EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = +{ + /* EDMA3 INSTANCE# 0 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + /* Resources owned/reserved by region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 */ + {0xFF3FF3FFu, + /* 63..32 */ + 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + }, + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + }, + /* EDMA3 INSTANCE# 1 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + /* Resources owned by Region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + { + 0xFFFFFFFFu, + 0x00000000u + }, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + { + 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + }, + + /* resvdDmaChannels */ + /* 31 0 */ + { + EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1 + }, + + /* resvdQdmaChannels */ + /* 31 0 */ + { + 0x00000000u + }, + + /* resvdTccs */ + /* 31 0 */ + { + 0x3F07FFFFu, + /* 63..32 */ + 0x00000000u + }, + }, + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + } + } +}; + +/* End of File */ + diff --git a/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_int_reg.c b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_int_reg.c new file mode 100644 index 000000000..e82c9392b --- /dev/null +++ b/packages/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_int_reg.c @@ -0,0 +1,152 @@ +/* + * sample_omapl138_int_reg.c + * + * Platform specific interrupt registration and un-registration routines. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include + +#include + +/** + * EDMA3 TC ISRs which need to be registered with the underlying OS by the user + * (Not all TC error ISRs need to be registered, register only for the + * available Transfer Controllers). + */ +void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) = + { + &lisrEdma3TC0ErrHandler0, + &lisrEdma3TC1ErrHandler0, + &lisrEdma3TC2ErrHandler0, + &lisrEdma3TC3ErrHandler0, + &lisrEdma3TC4ErrHandler0, + &lisrEdma3TC5ErrHandler0, + &lisrEdma3TC6ErrHandler0, + &lisrEdma3TC7ErrHandler0, + }; + +extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS]; +extern unsigned int ccErrorInt[]; +extern unsigned int tcErrorInt[][EDMA3_MAX_TC]; +extern unsigned int numEdma3Tc[]; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +extern unsigned int hwIntXferComp[]; +extern unsigned int hwIntCcErr[]; +extern unsigned int hwIntTcErr[]; + +extern unsigned int dsp_num; + +/** To Register the ISRs with the underlying OS, if required. */ +void registerEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Enable the Xfer Completion Event Interrupt */ + EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num], + (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0), + edma3Id, 1); + EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]); + + /* Enable the CC Error Event Interrupt */ + EventCombiner_dispatchPlug(ccErrorInt[edma3Id], + (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0), + edma3Id, 1); + EventCombiner_enableEvent(ccErrorInt[edma3Id]); + + /* Enable the TC Error Event Interrupt, according to the number of TCs. */ + while (numTc < numEdma3Tc[edma3Id]) + { + EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc], + (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]), + edma3Id, 1); + EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]); + numTc++; + } + + /** + * Enabling the HWI_ID. + * EDMA3 interrupts (transfer completion, CC error etc.) + * correspond to different ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this + * mapped HWI_INT YYY, one should use the corresponding bitmask in the + * API C64_enableIER(), in which the YYY bit is SET. + */ + Hwi_enableInterrupt(hwIntXferComp[edma3Id]); + Hwi_enableInterrupt(hwIntCcErr[edma3Id]); + Hwi_enableInterrupt(hwIntTcErr[edma3Id]); + + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +void unregisterEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Disable the Xfer Completion Event Interrupt */ + EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]); + + /* Disable the CC Error Event Interrupt */ + EventCombiner_disableEvent(ccErrorInt[edma3Id]); + + /* Enable the TC Error Event Interrupt, according to the number of TCs. */ + while (numTc < numEdma3Tc[edma3Id]) + { + EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]); + numTc++; + } + + /* Restore interrupts */ + Hwi_restore(cookie); + } + diff --git a/packages/ti/drv/mcbsp/include/Module.xs b/packages/ti/drv/mcbsp/include/Module.xs new file mode 100644 index 000000000..8faf45ab0 --- /dev/null +++ b/packages/ti/drv/mcbsp/include/Module.xs @@ -0,0 +1,33 @@ +/****************************************************************************** + * FILE PURPOSE: MCBSP LLD include files. + ****************************************************************************** + * FILE NAME: module.xs + * + * DESCRIPTION: + * This file contains the module specification for MCBSP LLD include directory + * + * Copyright (C) 2012, Texas Instruments, Inc. + *****************************************************************************/ + +/* Load the library utility. */ +var libUtility = xdc.loadCapsule ("../build/buildlib.xs"); + +/************************************************************************** + * FUNCTION NAME : modBuild + ************************************************************************** + * DESCRIPTION : + * The function is used to add all the header files in the include + * directory into the package. + **************************************************************************/ +function modBuild() +{ + /* Add all the .h files to the release package. */ + var testFiles = libUtility.listAllFiles (".h", "include", true); + for (var k = 0 ; k < testFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k]; + + /* Add all the .mk files to the release package. */ + var mkFiles = libUtility.listAllFiles (".mk", "include", true); + for (var k = 0 ; k < mkFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k]; +} diff --git a/packages/ti/drv/mcbsp/include/mcbsp_pvt.h b/packages/ti/drv/mcbsp/include/mcbsp_pvt.h new file mode 100644 index 000000000..9bbe7d0aa --- /dev/null +++ b/packages/ti/drv/mcbsp/include/mcbsp_pvt.h @@ -0,0 +1,448 @@ +/* + * mcbsp_pvt.h + * + * McBSP Driver internal header file + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ +/** + * \file mcbsp_pvt.h + * + * \brief Header file conataining the driver internal definitions and data + * structures. + * + * (C) Copyright 2012, Texas Instruments, Inc + * + */ + +#ifndef _MCBSP_PVT_H_ +#define _MCBSP_PVT_H_ + + +/*============================================================================*/ +/* INCLUDE FILES */ +/*============================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* MCBSP LLD includes */ +#include +#include +#include +#include + +/*============================================================================*/ +/* MACRO DEFINTIONS */ +/*============================================================================*/ + +#define Mcbsp_MAXLINKCNT (2u) +/**< Maximum number of EDMA jobs linked at a time (Must be 2). */ + +#define Mcbsp_TXEVENTQUE (1u) +/**< Transmit EDMA channel event queue number */ + +#define Mcbsp_RXEVENTQUE (2u) +/**< Receive EDMA channel event queue number */ + +#define Mcbsp_CNT_MAX_VAL (0xFFFFu) +/**< Max possible value of aCnt, bCnt and cCnt */ + +#define Mcbsp_STATUS_INVALID (0xFFFF) +/**< Generic invalidate status */ + +#define Mcbsp_STATUS_VALID (0x1) +/**< Generic validate status */ + +#define Mcbsp_MAX_IOBUF_SIZE (32768u) +/**< Maximum sixe of the I/O buffer programmable */ + +#define Mcbsp_FRAME_LENGTH (127u) +/**< No of frames Max supported by the mcbsp */ + +#ifndef CSL_MCBSP_PER_CNT +#define CSL_MCBSP_PER_CNT CSL_MCBSP_CNT +#endif +/*============================================================================*/ +/* ENUMERATED DATA TYPES */ +/*============================================================================*/ + +/** + * \brief Mcbsp driver state + * + * Mcbsp driver state enums used to track the driver and channel state. + */ +typedef enum Mcbsp_DriverState_t +{ + Mcbsp_DriverState_DELETED, + Mcbsp_DriverState_CREATED, + Mcbsp_DriverState_INITIALIZED, + Mcbsp_DriverState_OPENED, + Mcbsp_DriverState_CLOSED, + Mcbsp_DriverState_DEINITIALIZED +}Mcbsp_DriverState; +/**< Mcbsp driver and channel states */ + +/** + * \brief Mcbsp SPCR control enums + * + * These enums are used to control the settings of the SPCR register. + */ +typedef enum Mcbsp_SpcrCtrl_t +{ + Mcbsp_SpcrCtrl_RX_ENABLE = (1u), + /**< To enable receiver in resetControl Function */ + + Mcbsp_SpcrCtrl_TX_ENABLE = (2u), + /**< To enable Transmitter in resetControl Function */ + + Mcbsp_SpcrCtrl_RX_DISABLE = (4u), + /**< To disable Receiver in resetControl Function */ + + Mcbsp_SpcrCtrl_TX_DISABLE = (8u), + /**< To disable Transmitter in resetControl Function */ + + Mcbsp_SpcrCtrl_FSYNC_ENABLE = (16u), + /**< To enable Frame Sync Generation in resetControl Function */ + + Mcbsp_SpcrCtrl_SRG_ENABLE = (32u), + /**< To enable Sample Rate Generator in resetControl Function */ + + Mcbsp_SpcrCtrl_FSYNC_DISABLE = (64u), + /**< To disable Frame Sync Generation in resetControl Function*/ + + Mcbsp_SpcrCtrl_SRG_DISABLE = (128u) + /**< To disable Sample Rate Generator in resetControl Function*/ +}Mcbsp_SpcrCtrl; +/**< Mcbsp SPCR control enums */ + +/*============================================================================*/ +/* DATA STRUCTURES */ +/*============================================================================*/ + +typedef struct Mcbsp_Object_t Mcbsp_Object; + +/** + * \brief Mcbsp channel Object + * + * This structure maintains the current channel state. It also holds + * information on DMA channel being used and holds the application + * callback function to be called in case of an interrupt. + * + * This structure is initialized by mdCreateChan and a pointer to this + * is passed down to all other channel related functions. Lifetime of + * the data structure is from its creation by mdCreateChan till it + * is invalidated by mdDeleteChan.each instance object will have two channel + * object one for TX and one for the RX channel. + */ +typedef struct Mcbsp_ChannelObj_t +{ + uint16_t mode; + /**< Mode of operation of the channel (MCBSP_MODE_INPUT or MCBSP_MODE_OUTPUT) */ + + Mcbsp_DriverState chanState; + /**< operational state of the channel (opened/closed) */ + + Mcbsp_Object *devHandle; + /**< Pointer to McBSP device driver instance object */ + + Mcbsp_CallbackFxn cbFxn; + /**< Driver call back function to be called once a I/O buffer is processed*/ + + void* cbArg; + /**< Callback Function argument */ + + void* edmaHandle; + /**< Handle to the EDMA3 driver(given by application) */ + + uint32_t edmaEventQue; + /**< EDMA event queue to be used by the channel */ + + EDMA3_RM_TccCallback edmaCallback; + /**< Edma callback function pointer */ + + uint32_t xferChan; + /**< eDMA ChannelID */ + + uint32_t tcc ; + /**< EDMA transfer completion code */ + + uint32_t pramTbl[Mcbsp_MAXLINKCNT]; + /**< Logical channel numbers of EDMA, which are used for linking */ + + uint32_t pramTblAddr[Mcbsp_MAXLINKCNT]; + /**< Physical address of logical channel numbers of EDMA, which * + * are used for linking */ + + void* ptrQPendList; + /**< Queue to hold the pending I/O buffers received from the application */ + + void* ptrQFloatList; + /**< Queue to manage floating I/O buffers in DMA */ + + Mcbsp_IOBuf *tempIOBuf; + /**< Temporary I/O buffer holder */ + + Mcbsp_IOBuf *dataIOBuf; + /**< Temporary I/O buffer holder used to load the next buffer in to EDMA */ + + uint32_t submitCount; + /**< Number of submit calls pending in the driver */ + + Mcbsp_BufferFormat dataFormat; + /**< Application supplied buffer format */ + + Bool nextFlag; + /**< Flag to indicate if the state machine can be stopped or not */ + + volatile Bool bMuteON; + /**< Flag to set the mute ON/OFF status */ + + volatile Bool paused; + /**< Flag to indicate if the audio is paused or not */ + + volatile Bool flush; + /**< Flag to indicate if the Driver IO request flush is set */ + + volatile Bool isTempIOBufValid; + /**< Flag to indicate whether a valid buffer is available in tempIOBuf */ + + Bool enableHwFifo; + /**< whether the FIFO has to be enabled for this channel */ + + Mcbsp_GblErrCallback gblErrCbk; + /**< Callback to called in case an error occurs(supplied by application) */ + + uint32_t userDataBufferSize; + /**< Size of the data buffer to be transferred */ + + void* loopJobBuffer; + /**< Buffer to be transferred when the loop job is running */ + + uint16_t loopJobLength; + /** + +PackagePackager +{} + +PackageRelease +<%PatchVersion%> + +PackageSummary +{} + +PackageVersion +<%MajorVersion%>.<%MinorVersion%> + +PreserveFilePermissions +Yes + +ProjectID +7411AF15-11B6-4788-A724-5593C23D1A85 + +ProjectVersion +1.2.5.1 + +SaveOnlyToplevelDirs +No + +ScriptExt +.bat + +ShortAppName +mcbsplld + +SkipUnusedFileGroups +Yes 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- THIS IS A LEGALLY BINDING AGREEMENT. PLEASE READ IT CAREFULLY. +IF YOU DO NOT AGREE WITH THE FOLLOWING PROVISIONS, YOU MAY NOT USE THE +ENCLOSED MATERIALS. AFTER YOU READ THIS LICENSE AGREEMENT, YOU WILL BE ASKED +WHETHER YOU ACCEPT AND AGREE TO THE TERMS OF THIS LICENSE AGREEMENT. DO NOT +CLICK "I HAVE READ AND AGREE" UNLESS: (1) YOU ARE AUTHORIZED TO ACCEPT AND AGREE TO THE TERMS OF THIS LICENSE AGREEMENT ON BEHALF OF YOURSELF AND YOUR COMPANY; AND (2) YOU INTEND TO ENTER INTO AND TO BE BOUND BY THE TERMS OF THIS LEGALLY BINDING AGREEMENT ON BEHALF OF YOURSELF AND YOUR COMPANY. + +This Software Evaluation Agreement (or "Agreement") is a legal agreement +between you ("You," either an individual or entity) and Texas Instruments +Incorporated ("TI"). The "Evaluation Materials" subject to this Agreement +include the enclosed or downloaded software programs and documentation that +accompany this Agreement and any "on-line" or electronic documentation +associated with the software programs. The "Evaluation Materials" include +certain TI proprietary software programs that are specifically designed and +licensed for execution solely and exclusively on or with TI Devices. For the +purposes of this Agreement the term "TI Devices" means a TI EVM or DSK manufactured by or for TI. By installing, copying or otherwise using the Evaluation Materials, you agree to abide by the following provisions. + +This Agreement is displayed for You to read prior to using the Evaluation Materials. If You do not accept or agree with these provisions then: + +(1) do not unzip, download, copy, install or otherwise use the Evaluation Materials; and + +(2) return the Evaluation Materials to TI's designated representative. + +Intellectual Property, Title and Limited License Grants - The Evaluation Materials contain copyrighted material, trade secrets and other proprietary information of TI and its licensors and are protected by copyright laws, international copyright treaties, and trade secret laws, as well as other intellectual property laws and treaties. The Evaluation Materials are licensed, not sold to You, and can only be used in accordance with the terms of this Agreement. You agree that You will not mortgage, pledge or encumber the Evaluation Materials in any way. TI and its licensors retain all title and ownership of the Evaluation Materials, including all intellectual property rights in the Evaluation Materials and all copies of the Evaluation Materials. + +a. Limited Evaluation License. Subject to the terms of this Agreement, TI +grants to You a fully paid-up, royalty free, non-transferable, +non-sub-licensable, non-exclusive, non-assignable, site-specific, temporary, +limited license to use the Evaluation Materials solely and exclusively with or +on TI Devices and solely for testing and evaluation purposes in accordance +with the terms of this Agreement. You agree that upon termination of this +Agreement, this license expires and that You will destroy any and all copies +of the Evaluation Materials, including any portions or derivatives thereof, in +your possession, custody or control and will provide to TI's designated representative a written statement signed by You or Your companyÆs authorized representative certifying such destruction. + +b. Limited Demonstration License. Subject to the terms of this Agreement, TI +grants to You a free, non-transferable, non-exclusive, non-assignable, +worldwide, non-sub-licensable, temporary, limited license to demonstrate the +Evaluation Materials as they are used in a product that includes a TI Device +and consists of both hardware and software components, including executable +versions of the software programs included with the Evaluation Materials that +execute solely and exclusively on a TI Device and not on a device manufactured +by or for an entity other than TI, provided that such software programs are +demonstrated solely in object or executable versions only and such hardware +and software programs are not left with or retained by any third party and +remain in your possession and under your control at all times. You agree that +upon termination of this Agreement, this license expires and that You will +destroy any and all copies of the Evaluation Materials, including any portions +or derivatives thereof, in your possession, custody or control and will +provide to TI's designated representative a written statement signed by You or your companyÆs authorized representative certifying such destruction. + +c. No Development, Production or Distribution License. You acknowledge and agree that this license is limited to testing, evaluation and limited demonstration purposes only and You specifically agree not to use or distribute the Evaluation Materials, or any portion or derivative thereof, to any third party for any commercial purpose. NOTWITHSTANDING ANYTHING TO THE CONTRARY, THIS AGREEMENT DOES NOT CONVEY ANY LICENSE TO USE THE EVALUATION MATERIALS, OR ANY PORTION OR DERIVATIVE THEREOF, IN PRODUCTION, OR TO DISTRIBUTE THE EVALUATION MATERIALS, OR ANY PORTION OR DERIVATIVE THEREOF, TO ANY THIRD PARTY. YOU ARE REQUIRED TO EXECUTE A SEPARATE LICENSE AGREEMENT WITH TI BEFORE MANUFACTURING OR DISTRIBUTING THE EVALUATION MATERIALS, OR ANY PORTION OR DERIVATIVE THEREOF, OR ANY PRODUCTS THAT CONTAIN THE EVALUATION MATERIALS, OR ANY PORTION OR DERIVATIVE THEREOF. + +d. No Other License. Notwithstanding anything to the contrary, nothing in this Agreement shall be construed as a license to any intellectual property rights of TI or its licensors other than those rights embodied in the software programs provided to You by TI as part of the Evaluation Materials. EXCEPT AS PROVIDED HEREIN, NO OTHER LICENSE, WHETHER EXPRESS, IMPLIED, OR STATUTORY, BY ESTOPPEL OR OTHERWISE, TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHTS IS GRANTED HEREIN. + +e. Use Restrictions. You will not disclose the Evaluation Materials, or +any portion or derivative thereof, to any person other than those employees, +consultants and contractors whose job performance directly requires access to +the Evaluation Materials. You will use the Evaluation Materials solely for +testing, evaluation and limited demonstration purposes and will not use or +distribute the Evaluation Materials, or any portion thereof, to any third +party for any commercial purpose. You will not copy, publish, disclose, +provide, transfer or make available the Evaluation Materials, or any portion +thereof, to any third party. You will not sub-license, transfer or assign the +Evaluation Materials or Your rights under this Agreement to any third party. +You will not (a) incorporate, combine, or distribute the Evaluation Materials, +or any portions or derivatives thereof, with any Public Software, or (b) use +Public Software in the development of any derivatives of the Evaluation +Materials, in such a way that would cause the Evaluation Materials, or any +portions or derivatives thereof, to be subject to all or part of the license +obligations or other intellectual property related terms with respect to such +Public Software, including but not limited to, the obligations that the +Evaluation Materials, or any portions or derivatives thereof, incorporated +into, combined, or distributed with such Public Software (i) be disclosed or +distributed in source code form, be licensed for the purpose of making +derivatives of such software, or be redistributed free of charge, contrary to +the terms and conditions of this Agreement, (ii) be used with devices other +than TI Devices, or (iii) be otherwise used or distributed in a manner +contrary to the terms and conditions of this Agreement. As used herein, +"Public Software" means any software that contains, or is derived in whole or +in part from, any software distributed as open source software, including but +not limited to software licensed under the following or similar models: (a) +GNU's General Public License (GPL) or Lesser/Library GPL (LGPL), (b) the Artistic License (e.g., PERL), (c) the Mozilla Public License, (d) the Netscape Public License, (e) the Sun Community Source License (SCSL), (f) the Sun Industry Standards Source License (SISL), (g) the Apache Server license, (h) QT Free Edition License, (i) IBM Public License, and (j) BitKeeper. + +f. Intellectual Property Rights. You acknowledge and agree that the +Evaluation Materials contain copyrighted material, trade secrets and other +proprietary information of TI or its licensors. To protect TI and its +licensors' rights in the Evaluation Materials, You agree that You will not decompile, reverse engineer, disassemble or otherwise translate any of the software programs included with the Evaluation Materials to a human-perceivable form nor permit any person or entity under Your employ or control to do so. In no event will You alter, remove or destroy any copyright or proprietary notice of TI or its licensors included in the Evaluation Materials. TI and its licensors reserve all rights not specifically granted under this Agreement. You further acknowledge and agree that all fixes, modifications and improvements to the Evaluation Materials conceived of or made by TI that are based, either in whole or in part, on Your feedback, suggestions or recommendations are the exclusive property of TI and all right, title and interest in and to all such fixes, modifications and improvements to the Evaluation Materials will vest solely in TI. + +Warranties and Disclaimers. + +a. No Warranty of Production or Support. Nothing contained in this +Agreement will be construed as a warranty or representation by TI to maintain +production of any TI semiconductor device or other hardware or software with +which the Evaluation Materials may be used or to otherwise support the +Evaluation Materials in any manner. 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IN NO EVENT SHALL THE COPYRIGHT OWNER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +ifeq ($(RULES_MAKE), ) +include $(PDK_INSTALL_PATH)/ti/build/Rules.make +else +include $(RULES_MAKE) +endif + +COMP = drvmcbsp + +lib_$(COMP)_BUILD_DEPENDENCY = soc + +$(COMP)_DOXYGEN_SUPPORT = yes + +include $(PDK_INSTALL_PATH)/ti/build/comp_top.mk + diff --git a/packages/ti/drv/mcbsp/mcbsp_component.mk b/packages/ti/drv/mcbsp/mcbsp_component.mk new file mode 100644 index 000000000..286cde1d0 --- /dev/null +++ b/packages/ti/drv/mcbsp/mcbsp_component.mk @@ -0,0 +1,129 @@ +# +# Copyright (c) 2018, Texas Instruments Incorporated +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Texas Instruments Incorporated nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +# File: mcbsp_component.mk +# This file is component include make file of mcbsp library. +# List of variables set in this file and their purpose: +# _RELPATH - This is the relative path of the module, typically from +# top-level directory of the package +# _PATH - This is the absolute path of the module. It derives from +# absolute path of the top-level directory (set in env.mk) +# and relative path set above +# _INCLUDE - This is the path that has interface header files of the +# module. This can be multiple directories (space separated) +# _PKG_LIST - Names of the modules (and sub-modules) that are a part +# part of this module, including itself. +# _BOARD_DEPENDENCY - "yes": means the code for this module depends on +# board and the compiled obj/lib has to be kept +# under directory +# "no" or "" or if this variable is not defined: means +# this module has no board dependent code and hence +# the obj/libs are not kept under dir. +# _CORE_DEPENDENCY - "yes": means the code for this module depends on +# core and the compiled obj/lib has to be kept +# under directory +# "no" or "" or if this variable is not defined: means +# this module has no core dependent code and hence +# the obj/libs are not kept under dir. +# _APP_STAGE_FILES - List of source files that belongs to the module +# , but that needs to be compiled at application +# build stage (in the context of the app). This is +# primarily for link time configurations or if the +# source file is dependent on options/defines that are +# application dependent. This can be left blank or +# not defined at all, in which case, it means there +# no source files in the module that are required +# to be compiled in the application build stage. +# + +ifeq ($(mcbsp_component_make_include), ) + +# under other list +drvmcbsp_BOARDLIST = +drvmcbsp_SOCLIST = k2g omapl138 c6657 +drvmcbsp_k2g_CORELIST = c66x +drvmcbsp_omapl138_CORELIST = c674x +drvmcbsp_c6657_CORELIST = c66x + +############################ +# mcbsp package +# List of components included under mcbsp lib +# The components included here are built and will be part of mcbsp lib +############################ + +mcbsp_LIB_LIST = mcbsp +drvmcbsp_LIB_LIST = $(mcbsp_LIB_LIST) + +############################ +# mcbsp examples +# List of examples under mcbsp +# All the tests mentioned in list are built when test target is called +# List below all examples for allowed values +############################ +mcbsp_EXAMPLE_LIST = + +# +# mcbsp Modules +# + +# mcbsp LIB +mcbsp_COMP_LIST = mcbsp +mcbsp_RELPATH = ti/drv/mcbsp +mcbsp_PATH = $(PDK_MCBSP_COMP_PATH) +mcbsp_LIBNAME = ti.drv.mcbsp +export mcbsp_LIBNAME +mcbsp_LIBPATH = $(mcbsp_PATH)/lib +export mcbsp_LIBPATH +mcbsp_OBJPATH = $(mcbsp_RELPATH)/mcbsp +export mcbsp_OBJPATH +mcbsp_MAKEFILE = -f build/makefile.mk +export mcbsp_MAKEFILE +mcbsp_BOARD_DEPENDENCY = no +mcbsp_CORE_DEPENDENCY = no +mcbsp_SOC_DEPENDENCY = yes +export mcbsp_COMP_LIST +export mcbsp_BOARD_DEPENDENCY +export mcbsp_CORE_DEPENDENCY +export mcbsp_SOC_DEPENDENCY +mcbsp_PKG_LIST = mcbsp +export mcbsp_PKG_LIST +mcbsp_INCLUDE = $(mcbsp_PATH) +mcbsp_SOCLIST = $(drvmcbsp_SOCLIST) +export mcbsp_SOCLIST +mcbsp_$(SOC)_CORELIST = $(drvmcbsp_$(SOC)_CORELIST) +export mcbsp_$(SOC)_CORELIST + +export drvmcbsp_LIB_LIST +export mcbsp_LIB_LIST + +mcbsp_component_make_include := 1 +endif diff --git a/packages/ti/drv/mcbsp/mcbsp_drv.h b/packages/ti/drv/mcbsp/mcbsp_drv.h new file mode 100644 index 000000000..7fe90c6a1 --- /dev/null +++ b/packages/ti/drv/mcbsp/mcbsp_drv.h @@ -0,0 +1,1245 @@ +/* + * mcbsp_drv.h + * + * This file contains Application programming interface for the Mcbsp driver and + * command/macro definitions used by the Mcbsp driver. + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/** + * \file mcbsp_drv.h + * + * \brief McBSP driver interface definition file + * + * This file contains the interfaces, data types and symbolic + * definitions that are needed by the application to utilize the + * services of the McBSP device driver. + * + * (C) Copyright 2012, Texas Instruments, Inc + * + */ + +#ifndef _MCBSP_DRV_H_ +#define _MCBSP_DRV_H_ + +/*============================================================================*/ +/* INCLUDE FILES */ +/*============================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* CSL RL includes */ +#include +#include +#include "mcbspver.h" + +/*============================================================================*/ +/* MACRO TYPES */ +/*============================================================================*/ + +/** + * \def MCBSP_LOOPJOB_ENABLE + * To enable loop job mode support in the MCBSP driver, uncomment + * following compiler switch and rebuild the MCBSP LLD. + */ +/* #define MCBSP_LOOPJOB_ENABLE */ + +/** + * \def Mcbsp_POLLED_RETRYCOUNT + * This macro specifies the default retry count to be used by the Mcbsp + * driver when polling for any hardware bit to be set or reset. + * + * \note This default value used by the driver can be changed by an IOCTL + * "Mcbsp_Ioctl_SET_TIMEOUT". + */ +#define Mcbsp_POLLED_RETRYCOUNT (0xFFFFu) + +/** + * \def MCBSP_CACHE_LENGTH + * Defines the Maximum length of cache line that is possible. + */ +#define MCBSP_CACHE_LENGTH (128u) + +/** + * \def MCBSP_MAX_CACHE_ALIGN + * Defines the Maximum cache line size for alignment. + */ +#define MCBSP_MAX_CACHE_ALIGN (128u) + +/** + * \def MCBSP_COMPILE_TIME_SIZE_CHECK + * This macro generates compiler error if postulate is false, so + * allows 0 overhead compile time size check. This "works" when + * the expression contains sizeof() which otherwise doesn't work + * with preprocessor. + */ +#define MCBSP_COMPILE_TIME_SIZE_CHECK(postulate) \ + do { \ + typedef struct { \ + uint8_t McbspNegativeSizeIfPostulateFalse[((int)(postulate))*2 - 1]; \ + } McbspPostulateCheck_t; \ + } \ + while (0) + +/*============================================================================*/ +/* ENUMERATED DATA TYPES */ +/*============================================================================*/ + +/** + * \brief Mcbsp device operational mode. + * + * This enum is used to define the operational mode of the mcbsp device + * like normal mcbsp device. + */ +typedef enum Mcbsp_DevMode_t +{ + Mcbsp_DevMode_McBSP = (0u) + /**< Option to operate in normal McBSP mode */ + +}Mcbsp_DevMode; +/**< Mcbsp device operational mode. */ + +/** + * \brief Mcbsp driver operational mode + * + * Enumeration of the different modes of operation available for the + * Mcbsp device driver.(Mcbsp driver supports only EDMA mode). + */ +typedef enum Mcbsp_OpMode_t +{ + Mcbsp_OpMode_POLLED = 0, + /**< Polled Mode */ + + Mcbsp_OpMode_INTERRUPT, + /**< Interrupt Mode */ + + Mcbsp_OpMode_DMAINTERRUPT + /**< DMA Mode */ + +}Mcbsp_OpMode; +/**< Mcbsp driver operational mode */ + +/** + * \brief Mcbsp Emulation mode settings + * + * Use this symbol to set the Emulation Mode to Free mode or any other + * mode. + * + * \note The SOFT mode settings are applicable only is the FREE mode is + * disabled.Hence if the soft mode is selected (both enable or disable) + * the driver will internally disable the FREE mode. + */ +typedef enum Mcbsp_EmuMode_t +{ + Mcbsp_EmuMode_SOFT_ABORT = (0u), + /**< SOFT mode is disabled. */ + + Mcbsp_EmuMode_SOFT_STOP = (1u), + /**< SOFT mode is enabled */ + + Mcbsp_EmuMode_FREE = (2u) + /**< FREE mode is enabled */ + +}Mcbsp_EmuMode; +/**< Mcbsp emulation modes */ + +/** + * \brief McBSP digital loopback mode selection + * + * Enum to select the enable/disable of Loopback mode of the mcbsp. + */ +typedef enum Mcbsp_Loopback_t +{ + Mcbsp_Loopback_DISABLE = 0, + /**< loopback mode off */ + + Mcbsp_Loopback_ENABLE = 1 + /**< loopback mode on */ + +} Mcbsp_Loopback; +/**< McBSP digital loopback mode selection */ + +/** + * \brief ENUM for receive data justification settings + * + * Use this symbol for setting up RCV sign-extension and justification + * mode + */ +typedef enum Mcbsp_Rxjust_t +{ + Mcbsp_RxJust_RZF = (0u), + /**< RCV setting - right justify, fill MSBs with zeros */ + + Mcbsp_RxJust_RSE = (1u), + /**< RCV setting - right justify, sign-extend the data into MSBs */ + + Mcbsp_RxJust_RxJUST_LZF = (2u) + /**< RCV setting - left justify, fill LSBs with zeros */ + +}Mcbsp_Rxjust; +/**< Enumeration for the Receive data justification */ + +/** + * \brief Transmit pin mode configuration + * + * DX pin settings used for setting the pin in high impedance mode. + */ +typedef enum Mcbsp_DxEna_t +{ + Mcbsp_DxEna_OFF = (0), + /**< DX enabler is OFF */ + + Mcbsp_DxEna_ON = (1u) + /**< DX enabler is ON */ +}Mcbsp_DxEna; +/**< DX pin High impedance enable/disable option */ + +/** + * \brief Polarity of the CLKS pin + * + * Enum to Set the polarity of the CLKS pin used to generate Frame Sync + * and bit clock + */ +typedef enum Mcbsp_ClkSPol_t +{ + Mcbsp_ClkSPol_RISING_EDGE = 0, + /**< Rising edge of CLKS generates CLKG and FSG. */ + + Mcbsp_ClkSPol_FALLING_EDGE = 1 + /**< Falling edge of CLKS generates CLKG and FSG. */ + +}Mcbsp_ClkSPol; +/**< Polarity of the CLKS pin */ + +/** + * \brief SRG clock source + * + * Use this symbol to select input clock source for Sample Rate + * Generator + */ +typedef enum Mcbsp_SrgClk_t +{ + Mcbsp_SrgClk_CLKS = (0u), + /**< input clock source for Sample Rate Generator is CLKS pin */ + + Mcbsp_SrgClk_CLKCPU = (1u), + /**< input clock source for Sample Rate Generator is CPU */ + + Mcbsp_SrgClk_CLKR = (2u), + /**< input clock source for Sample Rate Generator is BCLKR pin */ + + Mcbsp_SrgClk_CLKX = (3u) + /**< input clock source for Sample Rate Generator is BCLKX pin */ + +}Mcbsp_SrgClk; +/**< SRG clock source selection */ + +/** + * \brief Enum to specify the supported buffer formats. + * + * Interleaved and non-interleaved is standard format, this enumeration + * captures the standard and custom data formats. + */ +typedef enum Mcbsp_BufferFormat_t +{ + /* This mode is used for buffer containing the data in continous * + * memory locations where each sample is "wordWidth" long. This * + * format is supported for following configurations * + * Note : interleaved and non interleaved does not apply for this * + * buffer format */ + Mcbsp_BufferFormat_1SLOT, + + /* This is used for transfer of data with multiple slots.please note * + * that the slot data is not interleaved in this format. */ + Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED, + + /* This is used for transfer of data for multiple slots.please note * + * that the slot data is interleaved in this format. */ + Mcbsp_BufferFormat_MULTISLOT_INTERLEAVED +}Mcbsp_BufferFormat; +/**< Mcbsp supported buffer formats */ + +/** + * \brief Mcbsp PHASE control enums + * + * \note These enums are used to control the Phase settings of the MCBSP. + */ +typedef enum Mcbsp_Phase_t +{ + Mcbsp_Phase_SINGLE = (0u), + /**< Single phase for frame */ + + Mcbsp_Phase_DUAL = (1u) + /**< Dual phase for frame */ +} Mcbsp_Phase; +/**< Mcbsp frame phase selection ENUMERATION */ + +/** + * \brief Mcbsp supported wordlength. + * + * Enumerated constant for wordlength supported by the MCBSP device + */ +typedef enum Mcbsp_WordLength_t +{ + Mcbsp_WordLength_8 = 8u, + /**< Word length of 8 bits */ + + Mcbsp_WordLength_12 = 12u, + /**< Word length of 12 bits */ + + Mcbsp_WordLength_16 = 16u, + /**< Word length of 16 bits */ + + Mcbsp_WordLength_20 = 20u, + /**< Word length of 20 bits */ + + Mcbsp_WordLength_24 = 24u, + /**< Word length of 24 bits */ + + Mcbsp_WordLength_32 = 32u + /**< Word length of 32 bits */ + +}Mcbsp_WordLength; +/**< Mcbsp supported wordlength. */ + +/** + * \brief Frame sync ignore status enum + * + * \note Use this symbol to detect or ignore frame synchronisation + */ +typedef enum Mcbsp_FrmSync_t +{ + Mcbsp_FrmSync_DETECT = (0u), + /**< detect frame synchronisation */ + + Mcbsp_FrmSync_IGNORE = (1u) + /**< ignore frame synchronisation */ + +}Mcbsp_FrmSync; +/**< Frame sync detection options ENUMERATION */ + +/** + * \brief Enum to select Data delay in bits + * + * Use this Enum to set XMT/RCV Data Delay (in bits) + */ +typedef enum Mcbsp_DataDelay_t +{ + Mcbsp_DataDelay_0_BIT = (0u), + /**< sets XMT/RCV Data Delay to 0 bits */ + + Mcbsp_DataDelay_1_BIT = (1u), + /**< sets XMT/RCV Data Delay to 1 bits */ + + Mcbsp_DataDelay_2_BIT = (2u) + /**< sets XMT/RCV Data Delay to 2 bits */ + +} Mcbsp_DataDelay; +/**< Enum to select Data delay in bits */ + +/** + * \brief Enum to select the companding law + * + * Use this Enum to select the appropriate companding rule applicable. + */ +typedef enum Mcbsp_Compand_t +{ + Mcbsp_Compand_OFF_MSB_FIRST = (0u), + /**< No companding, data transfer starts with MSB first. */ + + Mcbsp_Compand_OFF_LSB_FIRST = (1u), + /**< No companding, 8-bit data transfer starts with LSB first. */ + + Mcbsp_Compand_MULAW = (2u), + /**< mu-law comapanding enable for channel */ + + Mcbsp_Compand_ALAW = (3u) + /**< A-law comapanding enable for channel */ + +}Mcbsp_Compand; +/**< Enum to select the companding law */ + +/** + * \brief McBSP 32-bit reversal feature + * + * This ENUM allows the user to select the option of BIT reversal. + */ +typedef enum Mcbsp_BitReversal_t +{ + Mcbsp_BitReversal_DISABLE = (0u), + /**< 32-bit reversal disabled */ + + Mcbsp_BitReversal_ENABLE = (1u) + /**< 32-bit reversal enabled. 32-bit data is received LSB first. Word * + * length should be set for 32-bit operation; else operation undefined */ + +}Mcbsp_BitReversal; +/**< McBSP 32-bit reversal feature */ + +/** + * \brief Frame sync clock source + * + * Use this ENUM to set the frame sync clock source as internal or + * external + */ +typedef enum Mcbsp_FsClkMode_t +{ + Mcbsp_FsClkMode_EXTERNAL = (0u), + /**< frame sync clock source as internal */ + + Mcbsp_FsClkMode_INTERNAL = (1u), + /**< frame sync clock source as external */ + + Mcbsp_FsClkMode_DXR_XSR = (2u) + /**< frame sync is generated on DXR_XSR copy */ + +} Mcbsp_FsClkMode; +/**< Frame sync clock source */ + +/** + * \brief Clock source selection ENUM + * + * Use this symbol to set the clock source as internal or external + */ +typedef enum Mcbsp_TxRxClkMode_t +{ + Mcbsp_TxRxClkMode_EXTERNAL = (0u), + /**< clock source as internal */ + + Mcbsp_TxRxClkMode_INTERNAL = (1u) + /**< clock source as external */ + +} Mcbsp_TxRxClkMode; +/**< Clock source selection ENUM */ + +/** + * \brief Clock polarity + * + * Use this symbol to set XMT or RCV clock polarity as rising or + * falling edge + */ +typedef enum Mcbsp_ClkPol_t +{ + Mcbsp_ClkPol_RISING_EDGE = (0u), + /**< Data sampled on rising edge of the bit Clock */ + + Mcbsp_ClkPol_FALLING_EDGE = (1u), + /**< Data sampled on falling edge of the bit Clock */ + + Mcbsp_ClkPol_SRG_RISING_EDGE = (0u), + /**< SRG clock polarity is rising edge */ + + Mcbsp_ClkPol_SRG_FALLING_EDGE = (1u) + /**< SRG clock polarity Is falling edge */ + +} Mcbsp_ClkPol; +/**< Clock polarity */ + +/** + * \brief Frame sync polarity + * + * Use this symbol to set frame sync polarity as active-high or + * active-low + */ +typedef enum Mcbsp_FsPol_t +{ + Mcbsp_FsPol_ACTIVE_HIGH = (0u), + /**< frame sync polarity is active-high */ + + Mcbsp_FsPol_ACTIVE_LOW = (1u) + /**< frame sync polarity is active-low */ + +}Mcbsp_FsPol; +/**< Frame sync polarity */ + +/** + * \brief MCBSP Interrupt mode + * + * Use this symbol to set Interrupt mode (i.e. source of interrupt + * generation).This symbol is used on both RCV and XMT for RINT and + * XINT generation mode. + */ +typedef enum Mcbsp_IntMode_t +{ + Mcbsp_IntMode_ON_READY = (0u), + /**< Interrupt generated on RRDY of RCV or XRDY of XMT */ + + Mcbsp_IntMode_ON_EOB = (1u), + /**< Interrupt generated on end of 16-channel block transfer in * + * multichannel mode */ + + Mcbsp_IntMode_ON_FSYNC = (2u), + /**< Interrupt generated on frame sync */ + + Mcbsp_IntMode_ON_SYNCERR = (3u) + /**< Interrupt generated on synchronisation error */ + +}Mcbsp_IntMode; +/**< MCBSP Interrupt mode */ + +/** + * \brief Transmit multichannel selection mode bit. + * + * MCM determines whether all channels or only selected channels are + * enabled and unmasked for transmission/reception. + * + */ +typedef enum Mcbsp_McmMode_t +{ + Mcbsp_McmMode_ALL_CHAN_ENABLED_UNMASKED = (0u), + /**< All the 128 channels are enabled */ + + Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED = (1u), + /**< All channels are disabled unless selected by enable mask */ + + Mcbsp_McmMode_ALL_CHAN_ENABLED_MASKED = (2u), + /**< All channels are enabled but masked unless selected by Enable mask */ + + Mcbsp_McmMode_ALL_CHAN_DISABLED_MASKED = (3u) + /**< Symmetric transmission and reception */ + +}Mcbsp_McmMode; +/**< Transmit multichannel selection mode bit. */ + +/** + * \brief Partition A/B block channel selection bit. + */ +typedef enum Mcbsp_PartitionSel_t +{ + Mcbsp_PartitionMode_CHAN_0_15 = (0u), + /**< Select the channel 0-15 in block A */ + + Mcbsp_PartitionMode_CHAN_16_31 = (0u), + /**< Select the channel 16-31 in block B */ + + Mcbsp_PartitionMode_CHAN_32_47 = (1u), + /**< Select the channel 32-47 in block A */ + + Mcbsp_PartitionMode_CHAN_48_63 = (1u), + /**< Select the channel 48-63 in block B */ + + Mcbsp_PartitionMode_CHAN_64_79 = (2u), + /**< Select the channel 64-79 in block A */ + + Mcbsp_PartitionMode_CHAN_80_95 = (2u), + /**< Select the channel 80-95 in block B */ + + Mcbsp_PartitionMode_CHAN_96_111 = (3u), + /**< Select the channel 96-111 in block A */ + + Mcbsp_PartitionMode_CHAN_112_127 = (3u) + /**< Select the channel 112-127 in block B */ + +}Mcbsp_PartitionSel; +/**< Partition A/B block selection bit. */ + +/** + * \brief Multichannel partition mode selection. + * + * Multichannel mode allows selection of either an 2 partition mode or + * 8 partition mode.This enum allows the user to select the required + * partition mode of choice. + */ +typedef enum Mcbsp_PartitionMode_t +{ + Mcbsp_PartitionMode_2 = (0u), + /**< 2-partition mode. Only partitions A and B are used. */ + + Mcbsp_PartitionMode_8 = (1u) + /**< 8-partition mode. All partitions (A through H) are used */ + +}Mcbsp_PartitionMode; +/**< Multichannel partition mode selction */ + +/*============================================================================*/ +/* DATA STRUCTURES */ +/*============================================================================*/ + +/** + * \brief McBSP sample rate generator configuration structure + * + * Configurations for the Sample rate generator to generate the BCLK + * and Frame Sync signals are specified using this structure. + */ +typedef struct Mcbsp_srgConfig_t +{ + Bool gSync; + /**< sample rate generator clock syncronization bit (only if CLKS is used)*/ + + Mcbsp_ClkSPol clksPolarity; + /**< CLKS polarity used to drive the CLKG and FSG clocks */ + + Mcbsp_SrgClk srgInputClkMode; + /**< Source for the Sample rate generator (CLKS,CPU,CLKX,CLKR) */ + + uint32_t srgrInputFreq; + /**< input clock frequency for the SRGR (freq of CLKS or CLKX etc..) */ + + uint32_t srgFrmPulseWidth; + /**< Set the Frame Sync Pulse width in terms of FSG clock */ + +} Mcbsp_srgConfig; +/**< McBSP sample rate generator configuration structure */ + +/** + * \brief Mcbsp TX/RX section configuration structure. + * + * This strcuture specifies the configuration for the McBSP data stream + * including the whether it is single phase or dual phase, number of + * frames,the word length in each phase and data delay etc. + */ +typedef struct Mcbsp_DataConfig_t +{ + Mcbsp_Phase phaseNum; + /**< Phase of the McBSP data stream */ + + Mcbsp_WordLength wrdLen1; + /**< Length of the data word in first phase */ + + Mcbsp_WordLength wrdLen2; + /**< Length of the data word in second when dual phase is selected */ + + uint32_t frmLen1; + /**< Length of the data frame in first phase */ + + uint32_t frmLen2; + /**< Length of the data frame in second phase */ + + Mcbsp_FrmSync frmSyncIgn; + /**< Frame sync ignore bit */ + + Mcbsp_DataDelay dataDelay; + /**< Data delay to be configured in number of Bits */ + + Mcbsp_Compand compandSel; + /**< companding selection */ + + Mcbsp_BitReversal bitReversal; + /**< Transmit 32-bit bit reversal feature enable bit. */ + + Mcbsp_IntMode intMode; + /**< Event for which the interrupt is to be generated */ + + Mcbsp_Rxjust rjust; + /**< Receive sign extension and justification settings (RX only setting) */ + + Mcbsp_DxEna dxState; + /**< High impedance enable/disbale bit for the DX pin (TX only setting) */ + +}Mcbsp_DataConfig; +/**< Mcbsp TX/RX section configuration structure. */ + +/** + * \brief Mcbsp multi channel control settings + * + * structure to configure the multi channel settings for the mcbsp.used + * when the multi channel configuration is to be enabled. + */ +typedef struct Mcbsp_McrSetup_t +{ + Mcbsp_McmMode multiChanMode; + /**< Multi channel mode to be selcted */ + + Mcbsp_PartitionSel partitionSelA; + /**< Channel selection for partition A */ + + Mcbsp_PartitionSel partitionSelB; + /**< Channel selection for partition B */ + + Mcbsp_PartitionMode partitionMode; + /**< Channel partition mode selection */ +}Mcbsp_McrSetup; +/**< Mcbsp multi channel control settings */ + +/** + * \brief Mcbsp clock settings setup structure. + * + * This structure contains the information required to configure the + * clocks for the Mcbsp.Both the frame sync settings and the bit clock + * settings can be configured in this structure. + */ +typedef struct Mcbsp_ClkSetup_t +{ + Mcbsp_FsClkMode frmSyncMode; + /**< Frame sync mode bit (FSXM/FSRM)(Internal/External) */ + + uint32_t samplingRate; + /**< Frame sync frequency */ + + Mcbsp_TxRxClkMode clkMode; + /**< Bit clock mode (internal or external) */ + + Mcbsp_FsPol frmSyncPolarity; + /**< frmSyncTxPolarity */ + + Mcbsp_ClkPol clkPolarity; + /**< clkTxPolarity */ +}Mcbsp_ClkSetup; +/**< Mcbsp clock settings setup structure */ + +/** + * \brief Mcbsp Hardware specific information Object + * + * This structure maintains the information specific to the hardware instance + * of the Mcbsp. information like the base address and the cpu event numbers + * and DMA events is specific to the instance. This structure is a collection + * of such information. + */ +typedef struct +{ + uint32_t instNum; + /**< Instance of MCBSP being referred by this object */ + + CSL_McbspRegsOvly regs; + /**< Pointer to the register overlay structure of the MCBSP */ + + CSL_BfifoRegsOvly fifoRegs; + /**< Fifo address of the mcbsp instance */ + + CSL_BdataRegsOvly dataAddress; + /**< Mcbsp data registers address */ + + uint32_t edmaTxEventNum; + /**< edma Transmit event number */ + + uint32_t edmaRxEventNum; + /**< edma Receive event number */ + + uint32_t cpuTxEventNum; + /**< Transmit interrupt number */ + + uint32_t cpuRxEventNum; + /**< Receive interrupt number */ + +}Mcbsp_HwInfo_Unpadded; + +typedef struct +{ + /** Data structure without padding, so sizeof() can compute padding */ + Mcbsp_HwInfo_Unpadded obj; + /** Pad out to end of MCBSP_MAX_CACHE_ALIGN bytes to prevent something else + * from being placed on same cache line as Mcbsp_HwInfo. Note that pad[0] + * is illegal, so must add full MCBSP_MAX_CACHE_ALIGN if structure is + * already padded by chance. */ + uint8_t pad[MCBSP_MAX_CACHE_ALIGN - + (sizeof(Mcbsp_HwInfo_Unpadded) % MCBSP_MAX_CACHE_ALIGN)]; +} Mcbsp_HwInfo; +/**< Mcbsp Hardware specific information Object */ + +/** + * \brief Loop job buffer structure. + * This structure defines the format of the Loop job buffer. + * + * \note Loop job buffer is a buffer used by the mcbsp in edma mode. The + * Mcbsp uses this buffer when no iobufs are present and the mcbsp + * is also not stopped. In this condition the Mcbsp utilises the + * loop job buffer to transmit a known pattern of data from the loopjob + * buffer or receives the data in to a loop job buffer + */ +typedef struct Mcbsp_TempBuffer_t +{ + Uint8 scratchBuf[(4u) + MCBSP_CACHE_LENGTH]; + /**< This buffer will be aligned and also the same buffer will be used + * for all slots and also only 4 bytes are required because the + * max wordwidth is 4 and the cache length is used for buffer alignment */ + uint32_t *scratchBuffer; + /**< Pointer to hold the aligned buffer */ +}Mcbsp_TempBuffer; +/**< loop job buffer format. */ + +/*============================================================================*/ +/* DATA TYPES */ +/*============================================================================*/ + +/** + * \brief Global error callback function protype + * + * This is the global error callback function for the McBSP driver. + * This function is called directly called from ISR context in case of + * error. + * \note Since this function is called from an ISR context,care should be taken + * that this function conforms to ISR coding guidelines. + */ +typedef void (*Mcbsp_GblErrCallback)(uint32_t Arg1,uint32_t Arg2,uint32_t Arg3); + +/** + * \brief McBSP channel setup params + * + * This structure holds configuration to be used for + * creating a channel of the Mcbsp. These parameters need to be + * specified during the creation of the channel. + */ +typedef struct Mcbsp_ChanParams_t +{ + uint32_t wordWidth; + /**< This parameter informs the driver what is the width word (not * + * slot) and this help driver indirectly to decided no. of bytes to * + * be transfered for each slot- This is very * + * important parameter - in case of invalid value default value * + * driver will assume is 32 */ + + void* userLoopJobBuffer; + /**< Buffer to be transferred when the loop job is running. */ + + uint16_t userLoopJobLength; + /**< Number of bytes of the userloopjob buffer for each slot + * Please note that this is no. of bytes and this should be + * pre-calcuated properly for word width of slot - Please refer the + * wordWidth of this structure */ + + Mcbsp_GblErrCallback gblCbk; + /**< callback required when global error occurs - must be callable * + * directly from the ISR context */ + + void* edmaHandle; + /**< Handle to the EDMA Driver */ + + uint32_t edmaEventQue; + /**< EDMA event queue to be used by the channel */ + + uint32_t hwiNumber; + /**< Variable to specify the Hwi number to be used by the driver */ + + Mcbsp_BufferFormat dataFormat; + /**< Format of the application supplied buffer */ + + Bool enableHwFifo; + /**< Option to enable/disable the Hardware FIFO */ + + Mcbsp_DataConfig *chanConfig; + /**< settings to configure the TX or RX hardware sections */ + + Mcbsp_ClkSetup *clkSetup; + /**< clock setup for the RX or the TX section */ + + Mcbsp_McrSetup *multiChanCtrl; + /**< multiple channel control settings */ + + uint32_t chanEnableMask[4]; + /**< Mask of the channels to be enabled or disabled */ + + uint32_t numEnabledChannels; + /**< Number of channels enabled with multichannel mode + * Note: This should match the number of bits in chanEnable Mask if in + * Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED mode */ + +}Mcbsp_ChanParams; +/**< Mcbsp Channel setup parameters */ + +/** + * \brief McBSP device create params + * + * This structure holds the configuration to be used for the + * creation of the Mcbsp device instance.This configuration need to be + * supplied during the creation of the device instance. + */ +typedef struct Mcbsp_Params_t +{ + Mcbsp_DevMode mode; + /**< Mode in which mcbsp instance needs to be created */ + + Mcbsp_OpMode opMode; + /**< Operation mode of driver i.e. interrupt or EDMA.Mcbsp supports only + * EDMA mode */ + + Bool enablecache; + /**< whether the cache operations are to be performed on the application + * buffers or not */ + + Mcbsp_EmuMode emulationMode; + /**< Emulation mode settings for the Mcbsp */ + + Mcbsp_Loopback dlbMode; + /**< digital loop back mode (ENABLE/DISABLE) */ + + Mcbsp_srgConfig *srgSetup; + /**< configuration for the sample rate generator configurations */ + + void* txQPendingList; + /**< Queue to hold the pending buffers received from the application */ + + void* txQFloatingList; + /**< Queue to manage floating buffers in DMA */ + + void* rxQPendingList; + /**< Queue to hold the pending buffers received from the application */ + + void* rxQFloatingList; + /**< Queue to manage floating buffers in DMA */ + +} Mcbsp_Params; +/**< McBSP device setup params */ + +/** + * \brief McBSP queue element + * + * Doubly linked list for queue elements. + * Required for Mcbsp_IOBuf structure. + */ +typedef struct Mcbsp_QueueElem_t { + struct Mcbsp_QueueElem_t* volatile next; + struct Mcbsp_QueueElem_t* volatile prev; +} Mcbsp_QueueElem; + +/** + * \brief McBSP frame object params + * + * Mcbsp_IOBuf structures are managed by the driver. MCBSP + * buffers are the basis for all I/O operations. 'cmd' field + * contains the command id for the driver. 'status' is filled + * in by the driver and contains the status of the commmand. + */ +typedef struct Mcbsp_IOBuf_t +{ + Mcbsp_QueueElem link; + /**< queue link */ + + void* addr; + /**< buffer address */ + + uint32_t size; + /**< buffer size */ + + uint32_t arg; + /**< arg to be used by end app */ + + uint32_t cmd; + /**< command for driver - READ, WRITE, ABORT or FLUSH */ + + int32_t status; + /**< status of command */ + + uint32_t misc; + /**< reserved for driver */ +} Mcbsp_IOBuf; +/**< Mcbsp frame object params */ + +/** + * \brief MCBSP driver callback function + * + * This is the driver's callback function. The driver will + * call a function of this type whenever an I/O operation + * is over. + */ +typedef void (*Mcbsp_CallbackFxn)(void* arg, Mcbsp_IOBuf *ioBuf); + +/*============================================================================*/ +/* IOCTL COMMANDS */ +/*============================================================================*/ + +/** + * \brief McBSP Ioctl commands + * + * List of all the ioctl commands supported by the Mcbsp driver. + * + */ +typedef enum Mcbsp_IOCTL_t +{ + Mcbsp_IOCTL_START = 128, + /**< Starts the data transfer */ + + Mcbsp_IOCTL_SAMPLE_RATE_CHANGE, + /**< Command to chnage the sample rate */ + + Mcbsp_IOCTL_STOP, + /**< Stops the data transfer */ + + Mcbsp_IOCTL_SRGR_START, + /**< Start the McBSP SRG */ + + Mcbsp_IOCTL_SRGR_STOP, + /**< Stop the McBSP SRG */ + + Mcbsp_IOCTL_FSGR_START, + /**< Start the McBSP FSG */ + + Mcbsp_IOCTL_FSGR_STOP, + /**< Stop the McBSP FSG */ + + Mcbsp_IOCTL_SET_TIMEOUT, + /**< Modify the timeout value in the driver */ + + Mcbsp_IOCTL_MUTE_ON, + /**< Mute ON the transfer */ + + Mcbsp_IOCTL_MUTE_OFF, + /**< Take out of Muted state */ + + Mcbsp_IOCTL_PAUSE, + /**< Pause the playback operation */ + + Mcbsp_IOCTL_RESUME, + /**< Resume the playback operation */ + + Mcbsp_IOCTL_CHAN_RESET, + /**< Reset an I/O channel */ + + Mcbsp_IOCTL_DEVICE_RESET, + /**< Reset both input and output channel */ + + Mcbsp_IOCTL_SET_CLKMODE, + /**< Set Bit clock mode for the McBSP */ + + Mcbsp_IOCTL_SET_FRMSYNCMODE, + /**< Set Frame Sync mode for the McBSP */ + + Mcbsp_IOCTL_CONFIG_SRGR, + /**< configure Sample Rate Generator */ + + Mcbsp_IOCTL_SET_BCLK_POL, + /**< Set the CLKR or CLKX clock polarity */ + + Mcbsp_IOCTL_SET_FRMSYNC_POL, + /**< Set the FSR and FSX polarity */ + + Mcbsp_IOCTL_MODIFY_LOOPJOB, + /**< Enable/disable the loopjob */ + + Mcbsp_IOCTL_SYNCERR_INT_ENABLE, + /**< Enable/disable the sync error */ + + Mcbsp_IOCTL_LOOPBACK, + /**< enable/disable the loop back mode */ + + Mcbsp_IOCTL_CANCEL_PENDING_IO + /**< Cancel all the current pending IO in the driver */ + +} Mcbsp_IOCTL; +/**< McBSP Ioctl commands list */ + +/*============================================================================*/ +/* MCBSP MODES */ +/*============================================================================*/ +/** + * \brief McBSP Create Modes + * + * Mcbsp driver create functions take a mode parameter. + * + */ +/** + * \def MCBSP_MODE_INPUT + * Defines the mode as input. + */ +#define MCBSP_MODE_INPUT 0x0001 +/** + * \def MCBSP_MODE_OUTPUT + * Defines the mode as output. + */ +#define MCBSP_MODE_OUTPUT 0x0002 +/** + * \def MCBSP_MODE_INOUT + * Defines the mode as input and output. + */ +#define MCBSP_MODE_INOUT (MCBSP_MODE_INPUT | MCBSP_MODE_OUTPUT) + +/*============================================================================*/ +/* MCBSP STATUS CODES */ +/*============================================================================*/ +/** + * \brief McBSP Driver Status Codes + * + * Mcbsp driver status codes. + * + */ +/** + * \def MCBSP_STATUS_COMPLETED + * Defines the status as completed successfully. + */ +#define MCBSP_STATUS_COMPLETED 0 +/** + * \def MCBSP_STATUS_PENDING + * Defines the status as queued and pending. + */ +#define MCBSP_STATUS_PENDING 1 +/** + * \def MCBSP_STATUS_FLUSHED + * Defines the status as request flushed. Queued writes + * will be completed w/ MCBSP_STATUS_COMPLETED. Queued + * read requests return w/ MCBSP_STATUS_FLUSHED. + */ +#define MCBSP_STATUS_FLUSHED 2 + +/** + * \def MCBSP_STATUS_ABORTED + * Defines the status as request aborted. Non-completed + * read or write requests return w/ MCBSP_STATUS_ABORTED. + */ +#define MCBSP_STATUS_ABORTED 3 + + +/*============================================================================*/ +/* MCBSP DRIVER ERROR CODES */ +/*============================================================================*/ +/** + * \brief McBSP Driver Error Codes + * + * Mcbsp driver error codes. + * + */ +/** + * \def MCBSP_ERR_BADIO + * Generic failure condition + */ +#define MCBSP_ERR_BADIO -1 +/** + * \def MCBSP_ERR_TIMEOUT + * Timeout occurred + */ +#define MCBSP_ERR_TIMEOUT -2 +/** + * \def MCBSP_ERR_NOIOBUFFERS + * No buffers available for I/O + */ +#define MCBSP_ERR_NOIOBUFFERS -3 +/** + * \def MCBSP_ERR_FREE + * Unable to free resources + */ +#define MCBSP_ERR_FREE -4 +/** + * \def MCBSP_ERR_ALLOC + * Unable to allocate resource + */ +#define MCBSP_ERR_ALLOC -5 +/** + * \def MCBSP_ERR_ABORT + * I/O was aborted before completed + */ +#define MCBSP_ERR_ABORT -6 +/** + * \def MCBSP_ERR_BADMODE + * Invalid device mode + */ +#define MCBSP_ERR_BADMODE -7 +/** + * \def MCBSP_ERR_EOF + * End-of-File was encountered + */ +#define MCBSP_ERR_EOF -8 +/** + * \def MCBSP_ERR_NOTIMPL + * Operation not implemented or supported + */ +#define MCBSP_ERR_NOTIMPL -9 +/** + * \def MCBSP_ERR_BADARGS + * Invalid arguments specified + */ +#define MCBSP_ERR_BADARGS -10 +/** + * \def MCBSP_ERR_TIMEOUTUNREC + * Unrecoverable timeout occurred + */ +#define MCBSP_ERR_TIMEOUTUNREC -11 +/** + * \def MCBSP_ERR_INUSE + * Device already in use + */ +#define MCBSP_ERR_INUSE -12 + +/** + * \brief McBSP Driver Buffer Frame Command Codes + * + * Mcbsp driver frame command codes. + * + */ +/** + * \def Mcbsp_IOBuf_Cmd_READ + * Read command + */ +#define Mcbsp_IOBuf_Cmd_READ 0 +/** + * \def Mcbsp_IOBuf_Cmd_WRITE + * Write command + */ +#define Mcbsp_IOBuf_Cmd_WRITE 1 +/** + * \def Mcbsp_IOBuf_Cmd_ABORT + * Abort command + */ +#define Mcbsp_IOBuf_Cmd_ABORT 2 +/** + * \def Mcbsp_IOBuf_Cmd_FLUSH + * Flush command + */ +#define Mcbsp_IOBuf_Cmd_FLUSH 3 + +/** + * \brief McBSP Driver Command Codes Reserved for Control + * + * Mcbsp driver command codes reserved for control. + * + */ +/** + * \def MCBSP_CTRL_CHAN_RESET + * Reset channel only + */ +#define MCBSP_CTRL_CHAN_RESET 0 +/** + * \def MCBSP_CTRL_CHAN_TIMEDOUT + * Channel timeout occured + */ +#define MCBSP_CTRL_CHAN_TIMEDOUT 1 +/** + * \def MCBSP_CTRL_DEVICE_RESET + * Reset entire device + */ +#define MCBSP_CTRL_DEVICE_RESET 2 + +/********************************************************************** + **************************** EXPORTED API **************************** + **********************************************************************/ + +int32_t mcbspInit (void); +int32_t mcbspBindDev(void* *devp, int32_t devid, void* devParams); +int32_t mcbspUnBindDev(void* devp); +int32_t mcbspCreateChan(void* *chanp, void* devp, int32_t mode, + void* chanParams, Mcbsp_CallbackFxn cbFxn, + void* cbArg); +int32_t mcbspDeleteChan(void* chanp); +int32_t mcbspSubmitChan(void* chanp, Mcbsp_IOBuf *const ioBuf); +int32_t mcbspControlChan(void* chanp, Mcbsp_IOCTL cmd, void* arg); +void mcbspGblXmtIsr(void *hChan); +void mcbspGblRcvIsr(void *hChan); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _MCBSP_DRV_H_ */ +/*============================================================================*/ +/* END OF FILE */ +/*============================================================================*/ diff --git a/packages/ti/drv/mcbsp/mcbsp_osal.h b/packages/ti/drv/mcbsp/mcbsp_osal.h new file mode 100644 index 000000000..bd1b5c11a --- /dev/null +++ b/packages/ti/drv/mcbsp/mcbsp_osal.h @@ -0,0 +1,515 @@ +/** + * @file mcbsp_osal.h + * + * @brief + * This is the sample OS Adaptation layer which is used by the MCBSP + * driver. The OSAL layer can be ported in either of the following + * manners to a native OS: + * + * Approach 1: + * @n Use Prebuilt Libraries + * - Ensure that the provide an implementation of all + * Osal_XXX API for their native OS. + * - Link the prebuilt libraries with their application. + * - Refer to the "example" directory for an example of this + * @n Pros: + * - Customers can reuse prebuilt TI provided libraries + * @n Cons: + * - Level of indirection in the API to get to the actual OS call + * + * Approach 2: + * @n Rebuilt Library + * - Create a copy of this file and modify it to directly + * inline the native OS calls + * - Rebuild the MCBSP Driver library; ensure that the Include + * path points to the directory where the copy of this file + * has been provided. + * - Please refer to the "test" directory for an example of this + * @n Pros: + * - Optimizations can be done to remove the level of indirection + * @n Cons: + * - MCBSP Libraries need to be rebuilt by the customer. + * + * \par + * NOTE: + * (C) Copyright 2012 Texas Instruments, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * \par +*/ +#ifndef __MCBSP_OSAL_H__ +#define __MCBSP_OSAL_H__ + +#include +#include + +/** @addtogroup MCBSP_OSAL_API + @{ */ + +/********************************************************************** + ************************* Extern Declarations ************************ + **********************************************************************/ + +extern void* Osal_mcbspMalloc(uint32_t numBytes); +extern void Osal_mcbspFree (void* ptr, uint32_t size); +extern void* Osal_mcbspDataBufferMalloc(uint32_t numBytes); +extern void Osal_mcbspDataBufferFree(void* ptr, uint32_t numBytes); +extern void Osal_mcbspLog(char* fmt, ... ); +extern void* Osal_mcbspCreateSem(void); +extern void Osal_mcbspDeleteSem(void* semHandle); +extern void Osal_mcbspPendSem(void* semHandle); +extern void Osal_mcbspPostSem(void* semHandle); +extern void* Osal_mcbspEnterMultipleCoreCriticalSection(void); +extern void Osal_mcbspExitMultipleCoreCriticalSection(void* critSectHandle); +extern void* Osal_mcbspEnterSingleCoreCriticalSection(); +extern void Osal_mcbspExitSingleCoreCriticalSection(void* critSectHandle); +extern void Osal_mcbspBeginMemAccess(void* ptr, uint32_t size); +extern void Osal_mcbspEndMemAccess(void* ptr, uint32_t size); + +extern Bool Osal_mcbspQueueEmpty(void* handle); +extern void* Osal_mcbspQueueGet(void* handle); +extern void Osal_mcbspQueuePut(void* handle, Mcbsp_QueueElem* elem); +extern void Osal_mcbspWaitNBitClocks(uint32_t nticks); +extern void *Osal_local2Global (void *addr); +/** + * @brief The macro is used by the MCBSP driver to create a semaphore for + * each MCBSP socket opened in blocking mode. Semaphores created should + * *initially* be created with a count of 0 i.e. unavailable. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void* Osal_mcbspCreateSem(void); + @endverbatim + * + * Parameter + * @n Not Applicable + * + * Return Value + * @n Semaphore Handle + */ +#define Mcbsp_osalCreateSem() Osal_mcbspCreateSem() + +/** + * @brief The macro is used by the MCBSP driver to delete a previously + * created semaphore. This is called when a MCBSP socket opened in blocking mode + * is being closed. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspDeleteSem(void* semHandle) + @endverbatim + + * Parameter + * @n Semaphore Handle returned by the create semaphore + * + * Return Value + * @n Not Applicable + */ +#define Mcbsp_osalDeleteSem(X) Osal_mcbspDeleteSem(X) + +/** + * @brief The macro is used by the MCBSP driver to pend on a semaphore + * This is called when an application tries to receive data on a blocking + * socket when there is no data available. Since all semaphores are initially + * created to be unavailable; this will cause the application to block. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspPendSem(void* semHandle) + @endverbatim + * + * Parameter + * @n Semaphore Handle + * + * Return Value + * @n Not Applicable + */ +#define Mcbsp_osalPendSem(X) Osal_mcbspPendSem(X) + +/** + * @brief The macro is used by the MCBSP driver to post the semaphore + * The driver posts the semaphore once data is received on a specific + * socket. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspPostSem(void* semHandle) + @endverbatim + * + * Parameter + * @n Semaphore Handle + * + * Return Value + * @n Not Applicable + */ +#define Mcbsp_osalPostSem(X) Osal_mcbspPostSem(X) + +/** + * @brief The macro is used by the MCBSP driver to allocate memory + * The MCBSP driver uses this macro to allocate memory for its internal + * driver structures. This is invoked during the driver initialization + * and startup process. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void* Osal_mcbspMalloc(uint32_t numBytes) + @endverbatim + * + * Parameter + * @n Number of bytes to be allocated + * + * Return Value + * @n Pointer to the allocated block size + * + * @sa + * Mcbsp_osalDataBufferMalloc + */ +#define Mcbsp_osalMalloc(X) Osal_mcbspMalloc(X) + +/** + * @brief The macro is used by the MCBSP driver to free a previously + * allocated block of memory + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspFree(void* ptr, uint32_t numBytes) + @endverbatim + * + * Parameter + * @n Pointer to the block of memory to be cleaned up. + * @n Size of the allocated memory which is being freed. + * + * Return Value + * @n Not applicable. + */ +#define Mcbsp_osalFree(X, Y) Osal_mcbspFree(X, Y) + +/** + * @brief The macro is used by the MCBSP driver to allocate memory + * for the data buffers in Driver Managed Configuration. All data + * buffers should allocated should be in the global address space. + * This macro is invoked during the data path. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void* Osal_mcbspDataBufferMalloc(uint32_t numBytes) + @endverbatim + * + * Parameter + * @n Number of bytes to be allocated + * + * Return Value + * @n Pointer to the allocated block size + */ +#define Mcbsp_osalDataBufferMalloc(X) Osal_mcbspDataBufferMalloc(X) + +/** + * @brief The macro is used by the MCBSP driver to convert local address + * to Global address space + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void *Osal_local2Global (void *addr) + @endverbatim + * + * Parameter + * @n Local address pointer + * + * Return Value + * @n Global address pointer + */ + +#define Mcbsp_osalLocal2Global(X) Osal_local2Global(X) +/** + * @brief The macro is used by the MCBSP driver to free a previously + * allocated block data buffer. This macro is used to clean up previously + * allocated data buffers and is invoked during the data path. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspDataBufferFree(void* ptr, uint32_t numBytes) + @endverbatim + * + * Parameter + * @n Pointer to the block of memory to be cleaned up. + * @n Size of the allocated memory which is being freed. + * + * Return Value + * @n Not applicable. + */ +#define Mcbsp_osalDataBufferFree(X, Y) Osal_mcbspDataBufferFree(X, Y) + +/** + * @brief The macro is used by the MCBSP driver to log various + * messages. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspLog( char* fmt, ... ) + @endverbatim + * + * Parameter + * @n printf-style format string + * + * Return Value + * @n Not applicable. + */ +#define Mcbsp_osalLog Osal_mcbspLog + +/** + * @brief The macro is used by the MCBSP Driver to protect its shared resources + * access from MULTIPLE CORES. This is required if the MCBSP Driver API's are being + * invoked from multiple cores. If this is not the case then these macros can be + * defined to be NOP. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void* Osal_mcbspEnterMultipleCoreCriticalSection(void) + @endverbatim + * + * Parameter + * @n None + * + * Return Value + * @n Opaque Handle used for holding critical section locking information + */ +#define Mcbsp_osalEnterMultipleCoreCriticalSection Osal_mcbspEnterMultipleCoreCriticalSection + +/** + * @brief The macro is used by the MCBSP driver to end the protection of its + * internal shared "resources" from MULTIPLE CORE access. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspExitMultipleCoreCriticalSection(void* critSectHandle) + @endverbatim + * + * Parameter + * @n Opaque Handle used for holding critical section locking information + * + * Return Value + * @n None + */ +#define Mcbsp_osalExitMultipleCoreCriticalSection Osal_mcbspExitMultipleCoreCriticalSection + +/** + * @brief The macro is used by the MCBSP driver to protect its internal shared + * resources from SINGLE CORE MULTIPLE CONTEXT (thread or ISR) access. If all + * the MCBSP Driver APIs are being called from threads then this API could + * use semaphores. However if the MCBSP driver API's are being called from + * both ISR & Thread context then the critical section here would need to + * disable/enable interrupts. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void* Osal_mcbspEnterSingleCoreCriticalSection() + @endverbatim + * + * Parameter + * @n None + * + * Return Value + * @n Opaque Handle used for holding critical section locking information + */ +#define Mcbsp_osalEnterSingleCoreCriticalSection Osal_mcbspEnterSingleCoreCriticalSection + +/** + * @brief The macro is used to denote the end of the protection of the internal + * shared resource from SINGLE CORE MULTIPLE CONTEXT access. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspExitSingleCoreCriticalSection(void* critSectHandle) + @endverbatim + * + * Parameter + * @n critSectHandle - Opaque Handle used for holding critical section locking information + * + * Return Value + * @n None + */ +#define Mcbsp_osalExitSingleCoreCriticalSection Osal_mcbspExitSingleCoreCriticalSection + +/** + * @brief The macro is used by the MCBSP driver to indicate that a block + * of memory is about to be accessed. If the memory block is cached then + * this indicates that the application would need to ensure that the cache + * is updated with the data from the actual memory. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspBeginMemAccess(void* ptr, uint32_t size) + @endverbatim + * + * Parameter + * @n ptr - Pointer to the memory + * @n size - Size of the memory being accessed. + * + * Return Value + * @n None + */ +#define Mcbsp_osalBeginMemAccess Osal_mcbspBeginMemAccess + +/** + * @brief The macro is used by the MCBSP driver to indicate that the block of + * memory has finished being accessed. If the memory block is cached then the + * application would need to ensure that the contents of the cache are updated + * immediately to the actual memory. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspEndMemAccess(void* ptr, uint32_t size) + @endverbatim + * + * Parameter + * @n ptr - Pointer to the memory + * @n size - Size of the memory + * + * Return Value + * @n None + */ +#define Mcbsp_osalEndMemAccess Osal_mcbspEndMemAccess + +/** + * @brief The macro is used by the MCBSP driver to test for an + * empty queue. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspQueueEmpty(void* handle) + @endverbatim + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n TRUE - If the queue is empty + */ +#define Mcbsp_osalQueueEmpty Osal_mcbspQueueEmpty + +/** + * @brief The macro is used by the MCBSP driver to get an + * element from the front of queue. The function + * removes the element from the front of queue and + * returns a pointer to it. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void* Osal_mcbspQueueGet(void* handle) + @endverbatim + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * + * Return Value + * @n Handle (pointer) to former first element + */ +#define Mcbsp_osalQueueGet Osal_mcbspQueueGet + +/** + * @brief The macro is used by the MCBSP driver to put an + * element at the end of queue. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspQueuePut(void* handle, Mcbsp_QueueElem* elem) + @endverbatim + * + * Parameter + * @n handle - Handle of a previously created Queue instance object + * @n elem - Pointer to new queue element + * + * Return Value + * @n None + */ +#define Mcbsp_osalQueuePut Osal_mcbspQueuePut + +/** + * @brief The macro is used by the MCBSP driver to wait 'n' + * bit clocks to ensure proper synchronization internally. + * + * Prototype: + * The following is the C prototype for the expected OSAL API. + * + * @verbatim + void Osal_mcbspWaitNBitClocks(uint32_t nticks) + @endverbatim + * + * Parameter + * @n nticks - Number of bit clocks to wait + * + * Return Value + * @n None + */ +#define Mcbsp_osalWaitNBitClocks Osal_mcbspWaitNBitClocks +/** +@} +*/ + +#endif /* __MCBSP_OSAL_H__ */ + diff --git a/packages/ti/drv/mcbsp/mcbsp_types.h b/packages/ti/drv/mcbsp/mcbsp_types.h new file mode 100644 index 000000000..60146ef6e --- /dev/null +++ b/packages/ti/drv/mcbsp/mcbsp_types.h @@ -0,0 +1,49 @@ +/** + * @file mcbsp_types.h + * + * @brief + * This is a wrapper header file which includes the standard types + * which are used by the MCBSP Driver. + * + * \par + * NOTE: + * (C) Copyright 2012 Texas Instruments, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * \par +*/ +#ifndef __MCBSP_TYPES_H__ +#define __MCBSP_TYPES_H__ + +#include +#include + +#endif /* __MCBSP_TYPES_H__ */ + diff --git a/packages/ti/drv/mcbsp/mcbspver.h b/packages/ti/drv/mcbsp/mcbspver.h new file mode 100644 index 000000000..b48d624e3 --- /dev/null +++ b/packages/ti/drv/mcbsp/mcbspver.h @@ -0,0 +1,68 @@ +#ifndef _MCBSPVER_H +#define _MCBSPVER_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* ============================================================= */ +/** + * @file mcbspver.h + * + * path ti/drv/mcbsp/mcbspver.h + * + * @brief MCBSP Driver Version Definitions + * + * ============================================================ + * Copyright (c) Texas Instruments Incorporated 2012 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/** + * @brief This is the MCBSP Driver Version. Versions numbers are encoded in the following + * format: + * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD) + */ +#define MCBSP_DRV_VERSION_ID (0x0100000C) + +/** + * @brief This is the version string which describes the MCBSP driver along with the + * date and build information. + */ +#define MCBSP_DRV_VERSION_STR "MCBSP Driver Revision: 01.00.00.12" + + +#ifdef __cplusplus +} +#endif + + +#endif /* _MCBSPVER_H */ diff --git a/packages/ti/drv/mcbsp/mcbspver.h.xdt b/packages/ti/drv/mcbsp/mcbspver.h.xdt new file mode 100644 index 000000000..69dfdb0e0 --- /dev/null +++ b/packages/ti/drv/mcbsp/mcbspver.h.xdt @@ -0,0 +1,100 @@ +%%{ +/*! + * This template implements the mcbspver.h + */ + /* Versioning */ + var ver = this; + var ver1 = [00,00,00,00]; + var ver2 = [00,00,00,00]; + + for each(i=0;i Arch (AA); API Changes (BB); Major (CC); Minor (DD) + */ +#define MCBSP_DRV_VERSION_ID `versionID` + +/** + * @brief This is the version string which describes the MCBSP driver along with the + * date and build information. + */ +#define MCBSP_DRV_VERSION_STR `versionStr` + + +#ifdef __cplusplus +} +#endif + + +#endif /* _MCBSPVER_H */ diff --git a/packages/ti/drv/mcbsp/package.bld b/packages/ti/drv/mcbsp/package.bld new file mode 100644 index 000000000..3b0e0b185 --- /dev/null +++ b/packages/ti/drv/mcbsp/package.bld @@ -0,0 +1,122 @@ +/****************************************************************************** + * FILE PURPOSE: Build description for the MCBSP Driver + ****************************************************************************** + * FILE NAME: package.bld + * + * DESCRIPTION: + * This file contains the build specification and description for the MCBSP driver + * + * The file takes the following parameters from the command line through the + * XDCARGS variable. + * XDCARGS[0] = MCBSP Driver Install Type + * Valid Values are "TAR" or "SETUP" + * DEFAULT is "SETUP" + * + * Example for a valid command: + * xdc XDCARGS="SETUP" release + * + * Copyright (C) 2012, Texas Instruments, Inc. + *****************************************************************************/ + +/* List of all subdirectories that combine to make the MCBSP Driver Package. */ +var subDirectories = [ "src", "docs", "include","device","example" ]; + +var mcbspDriverInstallType; + +/* Determine if we need to create the InstallJammer Application or not? + * MCBSP LLD Deliverables be either of the following formats: + * - TAR Ball Package + * - Setup Executable + * DEFAULT is a SETUP Executable. */ + +if ((arguments[0] != "TAR") && (arguments[0] != "SETUP")) + mcbspDriverInstallType = "TAR"; +else + mcbspDriverInstallType = arguments[0]; + +/* Irrespective of the InstallType we always create a TAR Ball Package as a part + * of the RTSC Build. Here we determine the name of the TAR Ball Package + * Format is as follows: + * mcbsp_ */ +var mcbspRTSCFileName = "mcbsp" + "_" + + mcbspDriverReleaseVersion[0] + "_" + mcbspDriverReleaseVersion[1] + "_" + + mcbspDriverReleaseVersion[2] + "_" + mcbspDriverReleaseVersion[3]; + +/****************************************************************** + ************************ Release Banner ************************** + ******************************************************************/ + +print ("************* MCBSP Driver Build Information *************"); +print ("MCBSP Driver Install : " + mcbspDriverInstallType); +print ("MCBSP Driver LLD Version : " + mcbspDriverReleaseVersion); +print ("Tools Directory : " + toolsBaseDir); +print ("RTSC File Name : " + mcbspRTSCFileName); +print ("MCBSP Driver LLD Path : " + driverPath); +if (pOpts == 1) +{ + print ("CC LE opts : " + C66LE.ccOpts.prefix); + print ("CC BE opts : " + C66BE.ccOpts.prefix); + print ("****************************************************************"); +} + +/* Create the release package for the MCBSP LLD */ +Pkg.defaultRelease = Pkg.addRelease (mcbspRTSCFileName, {prefix: "./packages/"}); + +/* Moving forward we need to set the Archiver of the package to be ZIP. This is currently + * not supported in the XDC tools being used. Currenly builds need to be done with the + * following options:- + * xdc MK_FIXLISTOPTS=-t release + * ZIP is a better option as it works natively with INSTALL Jammer and we can remove the + * uncompression into a temporary directory. XDC Tools with xdc-rXX support the ZIP archiver. */ +//Pkg.attrs = {archiver : "zip"}; + +/* Cycle through all the sub-directories and build all the files */ +for (var i = 0; i < subDirectories.length; i++) +{ + /* Load the capsule in the sub directory. */ + var caps = xdc.loadCapsule (subDirectories[i]+"/Module.xs"); + + print ("Building directory " + subDirectories[i]); + + /* Build the capsule. */ + caps.modBuild(); + + /* Package the module.xs files for building via package */ + Pkg.otherFiles[Pkg.otherFiles.length++] = subDirectories[i]+"/Module.xs"; +} + +/* Package the remaining files */ +Pkg.otherFiles[Pkg.otherFiles.length++] = "config.bld"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "config_mk.bld"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "package.bld"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "package.xdc"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "package.xs"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "Settings.xdc"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "Settings.xdc.xdt"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "mcbsp_drv.h"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "mcbsp_osal.h"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "mcbsp_types.h"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "mcbspver.h"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "mcbspver.h.xdt"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/Doxyfile"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxyfile.xdt"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "build/buildlib.xs"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "makefile"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile.mk"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "src/src_files_common.mk"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "mcbsp_component.mk"; +Pkg.otherFiles[Pkg.otherFiles.length++] = "./lib"; + +/* Generate Users Manual Doxyfile */ +var tplt = xdc.loadTemplate("./docs/doxyfile.xdt"); +tplt.genFile("./docs/Doxyfile",mcbspDriverReleaseVersion); + +/* Generate Settings.xdc */ +var tplt = xdc.loadTemplate("./Settings.xdc.xdt"); +tplt.genFile("./Settings.xdc",mcbspDriverReleaseVersion); + +/* Generate paver.h */ +var tplt = xdc.loadTemplate("./mcbspver.h.xdt"); +tplt.genFile("./mcbspver.h",mcbspDriverReleaseVersion); + + diff --git a/packages/ti/drv/mcbsp/package.xdc b/packages/ti/drv/mcbsp/package.xdc new file mode 100644 index 000000000..2ce1672e7 --- /dev/null +++ b/packages/ti/drv/mcbsp/package.xdc @@ -0,0 +1,15 @@ +/****************************************************************************** + * FILE PURPOSE: Package specification file + ****************************************************************************** + * FILE NAME: package.xdc + * + * DESCRIPTION: + * This file contains the package specification for the MCBSP Driver + * + * Copyright (C) 2012-2019, Texas Instruments, Inc. + *****************************************************************************/ + +package ti.drv.mcbsp[1, 0, 0, 12] { + module Settings; +} + diff --git a/packages/ti/drv/mcbsp/package.xs b/packages/ti/drv/mcbsp/package.xs new file mode 100644 index 000000000..9978fe306 --- /dev/null +++ b/packages/ti/drv/mcbsp/package.xs @@ -0,0 +1,86 @@ +/* + * ======== package.xs ======== + * + */ + + +/* + * ======== Package.getLibs ======== + * This function is called when a program's configuration files are + * being generated and it returns the name of a library appropriate + * for the program's configuration. + */ + +function getLibs(prog) +{ + var suffix = prog.build.target.suffix; + + var name = this.$name + ".a" + suffix; + + /* Read LIBDIR variable */ + var lib = java.lang.System.getenv("LIBDIR"); + + /* If NULL, default to "lib" folder */ + if (lib == null) + { + lib = "./lib"; + } else { + print ("\tSystem environment LIBDIR variable defined : " + lib); + } + + /* Device types supported */ + var deviceTypes = [ + 'k2g', + 'omapl138', + 'c6657' + ]; + + /* Search for the supported devices (defined in config.bld) */ + for each(var device in deviceTypes) + { + if (this.Settings.deviceType.equals(device)) + { + lib = lib + "/" + device; + break; + } + } + + /* Get target folder, if applicable */ + if ( java.lang.String(suffix).contains('66') ) + lib = lib + "/c66"; + else if ( java.lang.String(suffix).contains('674') ) + lib = lib + "/c674"; + + var libProfiles = ["debug", "release"]; + for each(var profile in libProfiles) + { + if (this.Settings.libProfile.equals(profile)) + { + lib = lib + "/" + profile; + break; + } + } + + + /* Get library name with path */ + lib = lib + "/" + name; + if (java.io.File(this.packageBase + lib).exists()) { + print ("\tLinking with library " + this.$name + ":" + lib); + return lib; + } + + /* Could not find any library, throw exception */ + throw new Error("\tLibrary not found: " + this.packageBase + lib); +} + +/* + * ======== package.close ======== + */ +function close() +{ + if (xdc.om.$name != 'cfg') { + return; + } +} + + diff --git a/packages/ti/drv/mcbsp/setupenv.bat b/packages/ti/drv/mcbsp/setupenv.bat new file mode 100644 index 000000000..9a1dbfb25 --- /dev/null +++ b/packages/ti/drv/mcbsp/setupenv.bat @@ -0,0 +1,84 @@ +@REM ****************************************************************************** +@REM * FILE PURPOSE: Environment Setup for building MCBSP LLD +@REM ****************************************************************************** +@REM * FILE NAME: setupenv.bat +@REM * +@REM * DESCRIPTION: +@REM * Configures and sets up the Build Environment +@REM * +@REM * Copyright (C) 2012, Texas Instruments, Inc. +@REM ***************************************************************************** + +@echo --------------------------------------- +@echo Configuring MCBSP LLD Build Environment +@echo off + +IF DEFINED PARTNO GOTO partno_defined +@REM Configure the Part Number +set PARTNO=K2G +:partno_Defined + +IF DEFINED PDK_INSTALL_PATH GOTO pdk_defined +set PDK_INSTALL_PATH=C:\ti3\pdk_keystone2_3_02_00_00\packages +:pdk_defined + +@REM --------------------------------- +@REM Enabling MINI PACKAGE to be Built +@REM --------------------------------- +set MINI_PACKAGE=OFF +@echo MINI PACKAGE is set to %MINI_PACKAGE% + +@REM This is the base location for the various tools. +set XDCCGROOT=T:\c6xx\cgen7_4_02\c6000\cgtools +set C6X_GEN_INSTALL_PATH=T:\c6xx\cgen7_4_02\c6000\cgtools +set EDMA3_INSTALL_PATH=C:\ti\edma3_lld_02_11_09_08\packages + +@REM EDMA3 LLD installation path variables +@REM set EDMA3LLD_BIOS6_INSTALLDIR=C:/ti/edma3_lld_02_11_05_02 + +REM ******************************************************************************* +REM *************************** XDC PATH Configuration **************************** +REM ******************************************************************************* +REM MCBSP LLD depends upon the following packages:- +REM - CSL Package for the CSL Register Layer +REM - EDMA3 LLD +REM - RM LLD +REM - BIOS Package +REM These packages should be installed before trying to build the driver else +REM compilations will fail. +REM CSL/LLDs Package: CSL, MCBSP and RM are a part of the CSL/LLDs package. + +@REM Specify the XDC Tool Path +set XDC_INSTALL_PATH=T:/gen/xdc/xdctools_3_24_06_63 +set XDCPATH=../../..;%XDC_INSTALL_PATH%/packages + +@REM Configure the XDCPATH +set XDCPATH=%XDCPATH%;%PDK_INSTALL_PATH%;%C6X_GEN_INSTALL_PATH%/include;%EDMA3_INSTALL_PATH% + +@REM Eclipse Help Plugin (Not required by customers) +set XDC_ECLIPSE_PLUGIN_INSTALL_PATH=T:/gen/xdc/xdc_eclipse_plugin_gen/20091203 +set XDC_FILTER_INSTALL_PATH=T:/gen/xdc/xdcFilter/20100428 +set XDCPATH=%XDCPATH%;%XDC_ECLIPSE_PLUGIN_INSTALL_PATH% +set XDCPATH=%XDCPATH%;%XDC_FILTER_INSTALL_PATH% + +@REM Configure the paths to ensure that the XDC is available. +set PATH=%PATH%;%XDC_INSTALL_PATH%;%XDC_INSTALL_PATH%\bin;T:\Doxygen\doxygen\1.5.1-p1\bin + +@REM Third Party Tools: Install-Jammer (Not required by customers) +set PATH=%PATH%;T:\gen\InstallJammer\v1_3_0 + +set PATH=%PATH%;%XDCCGROOT%\bin;T:\gen\gnu\99-11-01\cygwin-b20\H-i586-cygwin32\bin +set PATH=%PATH%;T:\SDOApps\cg_xml\cg_xml_v2_30_00\bin + +@REM Third Party Tools: HTML Help compiler. +set PATH=%PATH%;T:\Doxygen\HTML_Help_Workshop\10-01-2007 + +@REM Environment Variable which control STATIC Analysis of the code +set STATIC_ANALYZE_PATH=T:\gen\coverity\prevent-mingw-3.4.0 +set PATH=%PATH%;%STATIC_ANALYZE_PATH%\bin + +@REM Set the Title Window appropriately. +Title MCBSP LLD Build Environment + +@echo MCBSP LLD Build Environment Configured +@echo --------------------------------------- diff --git a/packages/ti/drv/mcbsp/setupenv.sh b/packages/ti/drv/mcbsp/setupenv.sh new file mode 100644 index 000000000..4df8d24d3 --- /dev/null +++ b/packages/ti/drv/mcbsp/setupenv.sh @@ -0,0 +1,4 @@ +export C6X_GEN_INSTALL_PATH="D:/ti/ccsv5/tools/compiler/c6000_7.4.1" +export PDK_INSTALL_PATH="d:/ti/git/freon" +export XDC_INSTALL_PATH="d:/tixdctools_3_24_05_48" +export EDMA3LLD_BIOS6_INSTALLDIR="d:/ti/edma3_lld_02_11_05_02" diff --git a/packages/ti/drv/mcbsp/src/Module.xs b/packages/ti/drv/mcbsp/src/Module.xs new file mode 100644 index 000000000..a91726d8c --- /dev/null +++ b/packages/ti/drv/mcbsp/src/Module.xs @@ -0,0 +1,87 @@ +/****************************************************************************** + * FILE PURPOSE: MCBSP Source module specification file. + ****************************************************************************** + * FILE NAME: Module.xs + * + * DESCRIPTION: + * This file contains the module specification for the MCBSP source directory. + * + * Copyright (C) 2012, Texas Instruments, Inc. + *****************************************************************************/ + +/* Load the library utility. */ +var libUtility = xdc.loadCapsule ("../build/buildlib.xs"); + +/* List of all the MCBSP LLD Files */ +var mcbsplldFile = [ + "src/mcbsp_drv.c", + "src/mcbsp_ioctl.c", + "src/mcbsp_edma.c" +]; + +/************************************************************************** + * FUNCTION NAME : modBuild + ************************************************************************** + * DESCRIPTION : + * The function is used to build all the components of the MCBSP library + **************************************************************************/ +function modBuild() +{ + + if (socs.length != 0) + { + /* Build the device independent libraries for all the targets specified. */ + for (var targets=0; targets < socs["all"].targets.length; targets++) + { + if(socs["all"].build == "false") + continue; + var targetFiles = mcasplldFiles.slice(); /* make copy */ + var libOptions = { + copts: socs["all"].copts, + incs: lldIncludePath, + }; + libUtility.buildLibrary ("", "false", "false", libOptions, Pkg.name, socs["all"].targets[targets], targetFiles); + } + + /* Build library targets for device dependent SoCs */ + for (var soc=0; soc < soc_names.length; soc++) + { + var dev = socs[soc_names[soc]]; + + /* do not proceed if this SoC is not configured to be built */ + if (dev.build == "false") + continue; + + if (dev.socDevLib == "true") + { + var targetFiles_soc = mcasplldFiles.slice(); /* make copy */ + targetFiles_soc.push (deviceConstruct[0]+soc_names[soc]+deviceConstruct[1]); + /* Build the libraries for all the targets specified. */ + for (var targets=0; targets < dev.targets.length; targets++) + { + var libOptions = { + copts: dev.copts, + incs: lldIncludePath, + }; + libUtility.buildLibrary (soc_names[soc], "false", "true", libOptions, Pkg.name, dev.targets[targets], targetFiles_soc); + } + } + } + } + + /* Add all the .c files to the release package. */ + var testFiles = libUtility.listAllFiles (".c", "src", true); + for (var k = 0 ; k < testFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k]; + + /* Add all the .h files to the release package. */ + var testFiles = libUtility.listAllFiles (".h", "src", true); + for (var k = 0 ; k < testFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k]; + + /* Add all the .mk files to the release package. */ + var mkFiles = libUtility.listAllFiles (".mk", "src", true); + for (var k = 0 ; k < mkFiles.length; k++) + Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k]; +} + diff --git a/packages/ti/drv/mcbsp/src/mcbsp_drv.c b/packages/ti/drv/mcbsp/src/mcbsp_drv.c new file mode 100644 index 000000000..f9f114e7e --- /dev/null +++ b/packages/ti/drv/mcbsp/src/mcbsp_drv.c @@ -0,0 +1,2724 @@ +/* + * mcbsp_drv.c + * + * This file contains Driver Layer Interface implementation for the McBSP Driver. + * McBSP Driver provides Driver Layer Interface to do operations on the McBSP + * peripheral like device initialization, channel creation, control commands for + * peripheral specific operations etc. It uses EDMA3 for data transfer. + * + * Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/*============================================================================*/ +/* INCLUDE FILES */ +/*============================================================================*/ + +/* MCBSP Types and OSAL definitions: These files can be override by customers + * to point to their copies. Because of this the files have not been explicitly + * specified to include the driver path.*/ +#include +#include + +/* MCBSP Driver Includes */ +#include +#include + + +/* ========================================================================== */ +/* GLOBAL MODULE STATE */ +/* ========================================================================== */ + +/** + * \brief Array of Mcbsp instance State objects array + */ +#ifdef __cplusplus +#pragma DATA_SECTION (".mcbsp") +#pragma DATA_ALIGN (MCBSP_MAX_CACHE_ALIGN) +#else +#pragma DATA_SECTION (Mcbsp_Instances, ".mcbsp"); +#pragma DATA_ALIGN (Mcbsp_Instances, MCBSP_MAX_CACHE_ALIGN) +#endif + +Mcbsp_Object Mcbsp_Instances[CSL_MCBSP_PER_CNT]; + +/** + * \brief Mcbsp structure containing the information specific to an instance. + */ +/* Shared Memory Variable to ensure synchronizing SRIO initialization + * with all the other cores. */ +/* Created an array to pad the cache line with MCBSP_MAX_CACHE_ALIGN size */ +#ifdef __cplusplus +#pragma DATA_SECTION (".mcbsp") +#pragma DATA_ALIGN (MCBSP_MAX_CACHE_ALIGN) +#else +#pragma DATA_SECTION (Mcbsp_deviceInstInfo, ".mcbsp"); +#pragma DATA_ALIGN (Mcbsp_deviceInstInfo, MCBSP_MAX_CACHE_ALIGN) +#endif +Mcbsp_HwInfo Mcbsp_deviceInstInfo[CSL_MCBSP_PER_CNT]; + +/** + * \brief Mute buffer per instance + * + * \note Buffer used when the mcbsp is placed in mute. + */ +#ifdef __cplusplus +#pragma DATA_SECTION (".mcbsp") +#pragma DATA_ALIGN (MCBSP_MAX_CACHE_ALIGN) +#else +#pragma DATA_SECTION (Mcbsp_muteBuf, ".mcbsp"); +#pragma DATA_ALIGN (Mcbsp_muteBuf, MCBSP_MAX_CACHE_ALIGN) +#endif +Mcbsp_TempBuffer Mcbsp_muteBuf[CSL_MCBSP_PER_CNT]; + +#ifdef MCBSP_LOOPJOB_ENABLE +/** + * \brief Destination loop buffer per instance + * + * \note Buffer used during the loop job mode for the Transmit section + */ +#ifdef __cplusplus +#pragma DATA_SECTION (".mcbsp") +#pragma DATA_ALIGN (MCBSP_MAX_CACHE_ALIGN) +#else +#pragma DATA_SECTION (Mcbsp_loopDstBuf, ".mcbsp"); +#pragma DATA_ALIGN (Mcbsp_loopDstBuf, MCBSP_MAX_CACHE_ALIGN) +#endif +Mcbsp_TempBuffer Mcbsp_loopDstBuf[CSL_MCBSP_PER_CNT]; + +/** + * \brief Receive loop buffer per instance + * + * \note Buffer used during the loop job mode for the Receive section + */ +#ifdef __cplusplus +#pragma DATA_SECTION (".mcbsp") +#pragma DATA_ALIGN (MCBSP_MAX_CACHE_ALIGN) +#else +#pragma DATA_SECTION (Mcbsp_loopSrcBuf, ".mcbsp"); +#pragma DATA_ALIGN (Mcbsp_loopSrcBuf, MCBSP_MAX_CACHE_ALIGN) +#endif +Mcbsp_TempBuffer Mcbsp_loopSrcBuf[CSL_MCBSP_PER_CNT]; +#endif /* MCBSP_LOOPJOB_ENABLE */ + +/*============================================================================*/ +/* LOCAL FUNCTION PROTOTYPES */ +/*============================================================================*/ +int32_t mcbspSubmitReq(Mcbsp_Object_Unpadded *instHandle, + Mcbsp_ChannelObj *chanHandle, + Mcbsp_IOBuf *ioBuf); +void mcbspConfigureFifo(Mcbsp_HwInfo_Unpadded *hMcbsp, + Mcbsp_ChannelObj *chanHandle, + Bool enableHwFifo); + +#ifndef MCBSP_LOOPJOB_ENABLE +extern uint32_t Mcbsp_edmaChanNum; +#endif /* MCBSP_LOOPJOB_ENABLE */ + + +/* ========================================================================== */ +/* MODULE PUBLIC FUNCTIONS */ +/* ========================================================================== */ + +/** + * @b Description + * @n + * This is the MCBSP Driver Initialization API which needs to be + * invoked by the users to initialize the MCBSP peripheral. This call + * is *mandatory* and should be called before calling any of the + * other driver API's. + * + * This should only be called *ONCE* for the device. + * + * @retval + * MCBSP_STATUS_COMPLETED if successful + * @retval + * MCBSP_ERR_BADARGS if not successful + * MCBSP_ERR_ALLOC + */ +int32_t mcbspInit (void) +{ + int32_t devId = 0; + void *criticalSectionInfo; + + /* Begin Critical Section before accessing shared resources. */ + criticalSectionInfo = Mcbsp_osalEnterMultipleCoreCriticalSection (); + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_Instances, sizeof(Mcbsp_Instances)); + + /* initialize the information for all the device instances */ + for (devId = 0; devId < CSL_MCBSP_PER_CNT; devId++) + { + /* initialise the instance object */ + memset((void *)&Mcbsp_Instances[devId], 0, sizeof(Mcbsp_Object)); + Mcbsp_Instances[devId].obj.inUse = FALSE; + } + + /* Writeback Global Object */ + Mcbsp_osalEndMemAccess ((void *)Mcbsp_Instances, sizeof(Mcbsp_Instances)); + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (criticalSectionInfo); + + return MCBSP_STATUS_COMPLETED; +} + +/** + * \brief Allocates and configures the McBSP instance specified by devid. + * + * Acquires the Handle of the McBSP and configure the McBSP by + * default for the following things. + * o Data output for audio playback + * o Data input for audio recording + * o Configure the McBSP in DSP/TDM data format mode of the audio + * codec. + * o Configure the McBSP to receive the Frame Sync and bit clock + * externally for both receiver and transmitter. + * o McBSP can also be configured to generate Frame Sync and + * bit clock internally by enabling sample rate generator and + * frame sync generator blocks respectively depending on the + * fields set in the device parameter structure which shall + * be passed to mcbspBindDev() function as one of the parameter. + * + * \param devp [OUT] pointer to hold allocated instance object ptr + * \param devid [IN] instance number of the mcbsp + * \param devParams [IN] user supplied data params. + * + * \return MCBSP_STATUS_COMPLETED if successful + * + * MCBSP_ERR_BADARGS if not successful + * MCBSP_ERR_ALLOC + * + * \enter devp should be non NULL and valid pointer, + * devId should be < CSL_MCBSP_PER_CNT + * devParams should be non NULL and valid pointer, + * + * \leave Not implemented + */ +int32_t mcbspBindDev(void* *devp, int32_t devid, void* devParams) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_Params *params = NULL; + uint32_t ctrlMask = 0x00; + uint32_t count = 0x00; + int32_t status = MCBSP_STATUS_COMPLETED; + void *criticalSectionInfo; + + /* Begin Critical Section before accessing shared resources. */ + criticalSectionInfo = Mcbsp_osalEnterMultipleCoreCriticalSection (); + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_Instances, sizeof(Mcbsp_Instances)); + Mcbsp_osalBeginMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if ((NULL == devp) || (NULL == devParams) || (devid >= CSL_MCBSP_PER_CNT)) + { + status = MCBSP_ERR_BADARGS; + } + + if (MCBSP_STATUS_COMPLETED == status) + { + if (TRUE == Mcbsp_Instances[devid].obj.inUse) + { + status = MCBSP_ERR_INUSE; + } + else + { +#endif /* MCBSP_DISABLE_INPUT_PARAM_CHECK */ + /* copy the pointer to the instance object */ + instHandle = &(Mcbsp_Instances[devid].obj); + + /* set the module state as in use */ + Mcbsp_Instances[devid].obj.inUse = TRUE; + + params = (Mcbsp_Params *)devParams; + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + /* Only DMA mode of the operation is supported for Mcbsp mode */ + if ((Mcbsp_DevMode_McBSP == params->mode) && + (Mcbsp_OpMode_DMAINTERRUPT != params->opMode)) + { + status = MCBSP_ERR_BADMODE; + } + else + { + if (NULL == params->srgSetup) + { + status = MCBSP_ERR_BADMODE; + } + } + } + } +#endif /* MCBSP_DISABLE_INPUT_PARAM_CHECK */ + + if (MCBSP_STATUS_COMPLETED == status) + { + /* update the instance of the device being created */ + instHandle->instNum = devid; + + /* update the user supplied params to the instance object */ + instHandle->mode = params->mode; + instHandle->opMode = params->opMode; + instHandle->enablecache = params->enablecache; + + /* copy the SOC related information in to the instance object */ + instHandle->hwInfo = Mcbsp_deviceInstInfo[devid].obj; + + /* stop the state machine of RX and TX */ + instHandle->stopSmFsXmt = TRUE; + instHandle->stopSmFsRcv = TRUE; + + instHandle->retryCount = Mcbsp_POLLED_RETRYCOUNT; + + /* configure the default values for the transmit channel */ + instHandle->xmtObj.mode = (uint16_t)MCBSP_MODE_OUTPUT; + instHandle->xmtObj.devHandle = NULL; + instHandle->xmtObj.cbFxn = NULL; + instHandle->xmtObj.cbArg = NULL; + instHandle->xmtObj.edmaHandle = NULL; + instHandle->xmtObj.edmaEventQue = Mcbsp_TXEVENTQUE; + instHandle->xmtObj.edmaCallback = NULL; + instHandle->xmtObj.xferChan = 0x00; + instHandle->xmtObj.tcc = 0x00; + instHandle->xmtObj.tempIOBuf = NULL; + instHandle->xmtObj.submitCount = 0x00; + instHandle->xmtObj.dataFormat = Mcbsp_BufferFormat_1SLOT; + instHandle->xmtObj.bMuteON = FALSE; + instHandle->xmtObj.paused = FALSE; + instHandle->xmtObj.flush = FALSE; + instHandle->xmtObj.isTempIOBufValid = FALSE; + instHandle->xmtObj.enableHwFifo = TRUE; + instHandle->xmtObj.gblErrCbk = NULL; + instHandle->xmtObj.userDataBufferSize = 0x00; + instHandle->xmtObj.loopJobBuffer = NULL; + instHandle->xmtObj.loopJobLength = 0x00; + instHandle->xmtObj.nextLinkParamSetToBeUpdated = 0x00; + instHandle->xmtObj.loopjobUpdatedinParamset = FALSE; + instHandle->xmtObj.roundedWordWidth = 0x00; + + instHandle->rcvObj.mode = (uint16_t)MCBSP_MODE_INPUT; + instHandle->rcvObj.devHandle = NULL; + instHandle->rcvObj.cbFxn = NULL; + instHandle->rcvObj.cbArg = NULL; + instHandle->rcvObj.edmaHandle = NULL; + instHandle->rcvObj.edmaEventQue = Mcbsp_RXEVENTQUE; + instHandle->rcvObj.edmaCallback = NULL; + instHandle->rcvObj.xferChan = 0x00; + instHandle->rcvObj.tcc = 0x00; + instHandle->rcvObj.tempIOBuf = NULL; + instHandle->rcvObj.submitCount = 0x00; + instHandle->rcvObj.dataFormat = Mcbsp_BufferFormat_1SLOT; + instHandle->rcvObj.bMuteON = FALSE; + instHandle->rcvObj.paused = FALSE; + instHandle->rcvObj.flush = FALSE; + instHandle->rcvObj.isTempIOBufValid = FALSE; + instHandle->rcvObj.enableHwFifo = TRUE; + instHandle->rcvObj.gblErrCbk = NULL; + instHandle->rcvObj.userDataBufferSize = 0x00; + instHandle->rcvObj.loopJobBuffer = NULL; + instHandle->rcvObj.loopJobLength = 0x00; + instHandle->rcvObj.nextLinkParamSetToBeUpdated = 0x00; + instHandle->rcvObj.loopjobUpdatedinParamset = FALSE; + instHandle->rcvObj.roundedWordWidth = 0x00; + +#ifdef MCBSP_LOOPJOB_ENABLE + /* driver is compiled in loop Job mode */ + instHandle->loopJobMode = TRUE; +#else + instHandle->loopJobMode = FALSE; +#endif + + for (count = 0; count < Mcbsp_MAXLINKCNT; count++) + { + instHandle->xmtObj.pramTbl[count] = 0x00; + instHandle->rcvObj.pramTbl[count] = 0x00; + instHandle->xmtObj.pramTblAddr[count] = 0x00; + instHandle->rcvObj.pramTblAddr[count] = 0x00; + } + + /* set the status of the channel to closed */ + instHandle->xmtObj.chanState = Mcbsp_DriverState_CLOSED; + instHandle->rcvObj.chanState = Mcbsp_DriverState_CLOSED; + + /* Pending and Floating queues for TX and RX channels */ + instHandle->xmtObj.ptrQPendList = params->txQPendingList; + instHandle->xmtObj.ptrQFloatList = params->txQFloatingList; + instHandle->rcvObj.ptrQPendList = params->rxQPendingList; + instHandle->rcvObj.ptrQFloatList = params->rxQFloatingList; + + if (MCBSP_STATUS_COMPLETED == status) + { + /* Reset the McBSP Transmitter, receiver and SRGR before * + * configuration */ + ctrlMask = ((Mcbsp_SpcrCtrl_TX_DISABLE | + Mcbsp_SpcrCtrl_RX_DISABLE) | + (Mcbsp_SpcrCtrl_SRG_DISABLE | + Mcbsp_SpcrCtrl_FSYNC_DISABLE)); + + status = Mcbsp_localResetCtrl(instHandle,ctrlMask); + if (MCBSP_STATUS_COMPLETED != status) + { + /* Writeback Global Object */ + Mcbsp_osalEndMemAccess ((void *)Mcbsp_Instances, sizeof(Mcbsp_Instances)); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (criticalSectionInfo); + + return status; + } + + /* copy the configuration for the sample rate generator and config* + * the emulation mode and DLB mode settings */ + + /* Configure the McBSP with user supplied parameters */ + instHandle->srgrConfig = *(params->srgSetup); + + /* reset the Mcbsp */ + instHandle->hwInfo.regs->SPCR = 0x00u; + + /* set the DLB mode settings */ + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_DLB_MASK); + instHandle->hwInfo.regs->SPCR |= + (params->dlbMode << CSL_MCBSP_SPCR_DLB_SHIFT); + + /* set the clock stop mode settings */ + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_CLKSTP_MASK); + + /* set the emulation state */ + instHandle->hwInfo.regs->SPCR &= (~(CSL_MCBSP_SPCR_SOFT_MASK | + CSL_MCBSP_SPCR_FREE_MASK)); + instHandle->hwInfo.regs->SPCR |= + (params->emulationMode << CSL_MCBSP_SPCR_SOFT_SHIFT); + } + + if (MCBSP_STATUS_COMPLETED != status) + { + *devp = NULL; + } + else + { + *devp = &(Mcbsp_Instances[devid]); + + /* set the status of the driver to created */ + instHandle->devState = Mcbsp_DriverState_CREATED; + } + } + + /* Writeback Global Object */ + Mcbsp_osalEndMemAccess ((void *)Mcbsp_Instances, sizeof(Mcbsp_Instances)); + Mcbsp_osalEndMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo)); + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (criticalSectionInfo); + + return status; +} + +/** + * \brief Creates a communication channel in specified mode to communicate + * data between the application and the McBSP device instance. This + * function sets the required hardware configurations for the data + * transactions. It returns configured channel handle to application + * which will be used in all further transactions with the channel. + * + * Pre-requisites: + * 1. Valid chanParams structure + * This takes much information pertaining to mcbsp channel + * configuration such as how many slots are used for this + * channel what are their communication parameters, clock settings etc. + * 2. Valid device pointer + * + * \param chanp [IN] Channel Handler + * \param devp [IN] Device pointer + * \param mode [IN] channel mode -> input or output + * \param chanParams [IN] channel parameters from user + * \param cbFxn [IN] callback function pointer + * \param cbArg [IN] callback function Arguments + * + * \return MCBSP_STATUS_COMPLETED if successful + * MCBSP_ERR_BADIO if not successful + * MCBSP_ERR_ALLOC " + * MCBSP_ERR_BADARGS if passed invalid chanParams structure + */ +int32_t mcbspCreateChan(void* *chanp, + void* devp, + int32_t mode, + void* chanParams, + Mcbsp_CallbackFxn cbFxn, + void* cbArg) +{ + Mcbsp_Object *hInst = NULL; + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_ChannelObj *chanHandle = NULL; + Mcbsp_ChanParams *chanparam = NULL; + void* criticalSectionInfo; + int32_t status = MCBSP_STATUS_COMPLETED; + +/* Begin parameter checking */ +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if (((NULL == chanParams) + || (NULL == cbFxn) + || (NULL == cbArg) + || (NULL == devp)) + || ((MCBSP_MODE_INPUT != mode) && (MCBSP_MODE_OUTPUT != mode))) + { + return MCBSP_ERR_BADARGS; + } + else + { +#endif + chanparam = (Mcbsp_ChanParams *)chanParams; +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if (NULL == chanparam->edmaHandle) + { + return MCBSP_ERR_BADARGS; + } + } +#endif /* MCBSP_DISABLE_INPUT_PARAM_CHECK */ +/* End parameter checking */ + + /* Begin Critical Section before accessing shared resources. */ + criticalSectionInfo = Mcbsp_osalEnterMultipleCoreCriticalSection (); + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)devp, sizeof(Mcbsp_Object)); + + if (MCBSP_STATUS_COMPLETED == status) + { + hInst = (Mcbsp_Object *)devp; + instHandle = (Mcbsp_Object_Unpadded *)&(hInst->obj); + + /* get the pointer to the required channel structure */ + if (MCBSP_MODE_INPUT == mode) + { + chanHandle = &instHandle->rcvObj; + } + else + { + chanHandle = &instHandle->xmtObj; + } + + /* we will check if the current requested channel is availablehere* + * protect the channel status so that multiple threads requesting * + * same channel do not cause a corruption */ + if (Mcbsp_DriverState_CLOSED == chanHandle->chanState) + { + chanHandle->chanState = Mcbsp_DriverState_OPENED; + } + else + { + /* Requested channel is already taken hence we will set status* + * as invalid */ + status = MCBSP_ERR_BADMODE; + } + + if (MCBSP_STATUS_COMPLETED == status) + { + chanHandle->mode = (uint16_t)mode; + chanHandle->devHandle = hInst; + + /* Assign the respective callback function */ + chanHandle->cbFxn = cbFxn; + chanHandle->cbArg = cbArg; + + /* This is used in EDMA mode to populate paramsets in PINGPONG */ + chanHandle->nextLinkParamSetToBeUpdated = 0; + + /* Initialize Mute parameter */ + chanHandle->bMuteON = FALSE; + + chanHandle->isTempIOBufValid = FALSE; + + /* Counter that counts outstanding requests of this channel */ + chanHandle->submitCount = 0; + + /* Global error callback registered to channel */ + chanHandle->gblErrCbk = chanparam->gblCbk; + + /* copy the edma event queue details */ + chanHandle->edmaEventQue = chanparam->edmaEventQue; + + /* store the EDMA3 module handle */ + chanHandle->edmaHandle = chanparam->edmaHandle; + + /* configure the FIFO */ + chanHandle->enableHwFifo = chanparam->enableHwFifo; + + /* copy the user settings in to the channel object */ + chanHandle->chanConfig = *(chanparam->chanConfig); + chanHandle->clkSetup = *(chanparam->clkSetup); + chanHandle->numEnabledChannels = chanparam->numEnabledChannels; + chanHandle->dataFormat = chanparam->dataFormat; + } + + if (MCBSP_STATUS_COMPLETED == status) + { + /* configure the actual wordwidth to be used */ + switch (chanparam->wordWidth) + { + case Mcbsp_WordLength_8: + chanHandle->roundedWordWidth = 1u; + break; + case Mcbsp_WordLength_12: + case Mcbsp_WordLength_16: + chanHandle->roundedWordWidth = 2u; + break; + case Mcbsp_WordLength_20: + case Mcbsp_WordLength_24: + chanHandle->roundedWordWidth = 3u; + break; + case Mcbsp_WordLength_32: + default: + chanHandle->roundedWordWidth = 4u; + break; + } + +#ifdef MCBSP_LOOPJOB_ENABLE + /* Configure the loop job for the user specified buffer if given */ + if (NULL == chanparam->userLoopJobBuffer) + { + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + chanHandle->loopJobBuffer = + Mcbsp_loopDstBuf[instHandle->instNum].scratchBuffer; + } + else + { + chanHandle->loopJobBuffer = + Mcbsp_loopSrcBuf[instHandle->instNum].scratchBuffer; + } + chanHandle->loopJobLength = chanHandle->roundedWordWidth; + } + else + { + /* Apps has preference on the loopjob buffer & lets use it */ + chanHandle->loopJobBuffer = chanparam->userLoopJobBuffer; + chanHandle->userLoopJobLength = chanparam->userLoopJobLength; + + /* user loopJob is being used */ + chanHandle->userLoopJob = TRUE; + if (chanHandle->roundedWordWidth > + chanparam->userLoopJobLength) + { + /* not enough loopjob buffer has been provided we * + * should have at least loopbuffer for 1 sync event */ + status = MCBSP_ERR_BADARGS; + } + } +#endif + } + + if ((Mcbsp_DevMode_McBSP == instHandle->mode) && (MCBSP_STATUS_COMPLETED == status)) + { + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* Assign the Channel ID and TCC */ + chanHandle->xferChan = instHandle->hwInfo.edmaRxEventNum; + chanHandle->tcc = instHandle->hwInfo.edmaRxEventNum; + chanHandle->edmaCallback = + (EDMA3_RM_TccCallback)&Mcbsp_localEdmaCallback; + } + else + { + /* Assign the Channel ID and TCC */ + chanHandle->xferChan = instHandle->hwInfo.edmaTxEventNum; + chanHandle->tcc = instHandle->hwInfo.edmaTxEventNum; + chanHandle->edmaCallback = + (EDMA3_RM_TccCallback)&Mcbsp_localEdmaCallback; + } + + if (MCBSP_STATUS_COMPLETED == status) + { + mcbspConfigureFifo(&(instHandle->hwInfo), + chanHandle, + chanHandle->enableHwFifo); + } + + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* configure the RX section */ + status = Mcbsp_localConfigureRcvChannel(instHandle,chanparam); + } + else + { + /* configure the TX section */ + status = Mcbsp_localConfigureXmtChannel(instHandle,chanparam); + } + + if (MCBSP_STATUS_COMPLETED == status) + { + /* configure the sample rate generator */ + status = Mcbsp_localConfigureSrgr(instHandle,chanHandle); + } + + if (MCBSP_STATUS_COMPLETED == status) + { + /* enable the internal sample rate generator if required */ + if (((MCBSP_MODE_INPUT == chanHandle->mode) && + (TRUE == instHandle->rxSrgEnable)) || + ((MCBSP_MODE_OUTPUT == chanHandle->mode) && + (TRUE == instHandle->txSrgEnable))) + { + /* enable the sample rate generator */ + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_SRG_ENABLE); + instHandle->srgEnabled = TRUE; + + /* wait for the 2CLKG clock cycles */ + Mcbsp_osalWaitNBitClocks(2u); + } + + /* clear the XSYNCERR (to be done only if TX is used) */ + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + /* Enable the TX section */ + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_TX_ENABLE); + + /* wait for 2 CLKR or CLX cycles */ + Mcbsp_osalWaitNBitClocks(2u); + + /* Disable the TX section to clear any XYNCERR */ + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_TX_DISABLE); + } + + /* complete the EDMA setup for the driver */ + status = Mcbsp_localSetupEdmaDuringOpen(chanHandle); + } + +#ifdef MCBSP_LOOPJOB_ENABLE + if (MCBSP_STATUS_COMPLETED == status) + { + /* configure the FIFO for the specific channel */ + if (TRUE == chanHandle->enableHwFifo) + { + /* Disable and enable the FIFO so that the events are * + * generated to the Mcbsp for the first time */ + mcbspConfigureFifo(&instHandle->hwInfo,chanHandle,FALSE); + mcbspConfigureFifo(&instHandle->hwInfo,chanHandle,TRUE); + } + + /* enable the EDMA transfer for the channel so that it is * + * ready to transfer the data as soon as the state machine is * + * enabled */ + EDMA3_DRV_enableTransfer( + chanHandle->edmaHandle, + chanHandle->xferChan, + EDMA3_DRV_TRIG_MODE_EVENT); + + /* Start the McBSP hardware */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_RX_ENABLE); + } + else + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_TX_ENABLE); + } + + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + if (TRUE == instHandle->rxFsgEnable) + { + /* enable the sample rate generator */ + Mcbsp_localResetCtrl( + instHandle, + Mcbsp_SpcrCtrl_FSYNC_ENABLE); + } + } + else + { + if (TRUE == instHandle->txFsgEnable) + { + /* enable the sample rate generator */ + Mcbsp_localResetCtrl( + instHandle, + Mcbsp_SpcrCtrl_FSYNC_ENABLE); + } + } + + /* State machine stop status */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + instHandle->stopSmFsRcv = FALSE; + } + else + { + instHandle->stopSmFsXmt = FALSE; + } + } +#endif + } + } + + if (MCBSP_STATUS_COMPLETED != status ) + { + if (NULL != chanHandle) + { + /* set the status of the channel to closed */ + chanHandle->mode = (uint16_t)Mcbsp_DriverState_CLOSED; + } + + /* channel opening for transaction has failed */ + chanHandle = NULL; + } + else + { + *chanp = chanHandle; + } + + /* Writeback Global Object */ + Mcbsp_osalEndMemAccess ((void *)devp, sizeof(Mcbsp_Object)); + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (criticalSectionInfo); + + return status; +} + +/** + * \brief frees a channel and all it's associated resources. + * + * Frees the EDMA resources including EDMA master channel and link + * PaRAM entries held by the channel.it also unregisters all the + * interrupt handlers. + * + * \param chanp [IN] Handle to the channel + * + * \return MCBSP_STATUS_COMPLETED if successful + * MCBSP_STATUS_ABORTED if not successful + * + * \enter chanp should be non NULL and valid pointer, + * + * \leave Not implemented + */ +int32_t mcbspDeleteChan(void* chanp) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_ChannelObj *chanHandle = NULL; + Uint8 linkCnt = 0; + uint32_t timeOut = 0x00; + int32_t status = MCBSP_STATUS_COMPLETED; + void *criticalSectionInfo; + + /* Begin Critical Section before accessing shared resources. */ + criticalSectionInfo = Mcbsp_osalEnterMultipleCoreCriticalSection (); + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if (NULL == chanp) + { + status = MCBSP_ERR_BADARGS; + } + else + { +#endif /* MCBSP_DISABLE_INPUT_PARAM_CHECK */ + chanHandle = (Mcbsp_ChannelObj *)chanp; + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)chanHandle->devHandle, sizeof(Mcbsp_Object)); + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if (Mcbsp_DriverState_OPENED != chanHandle->chanState) + { + status = MCBSP_ERR_BADMODE; + } + else + { + if (NULL == chanHandle->devHandle) + { + status = MCBSP_ERR_BADARGS; + } + else + { +#endif + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if (NULL == instHandle) + { + status = MCBSP_ERR_BADARGS; + } + } + } + } +#endif /* MCBSP_DISABLE_INPUT_PARAM_CHECK */ + + if (MCBSP_STATUS_COMPLETED == status) + { + /* reset the channel . */ + Mcbsp_localAbortReset(chanHandle); + + /* Disable the current transfer to make sure that there is no * + * running EDMA transfer taking place */ + status = EDMA3_DRV_disableTransfer( + chanHandle->edmaHandle, + chanHandle->xferChan, + EDMA3_DRV_TRIG_MODE_EVENT); + + /* Disable current EDMA transfer */ + if (MCBSP_STATUS_COMPLETED == status) + { + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + timeOut = instHandle->retryCount; + + /* Poll for TXEMPTY */ + while ((CSL_MCBSP_SPCR_XEMPTY_MASK == + (CSL_MCBSP_SPCR_XEMPTY_MASK & instHandle->hwInfo.regs->SPCR)) + && (0 != timeOut)) + { + timeOut--; + } + } + + /* Reset McBSP before freeing the edma channels */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_RX_DISABLE); + } + else + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_TX_DISABLE); + } + + /* Free Edma channels */ + status = EDMA3_DRV_freeChannel( + chanHandle->edmaHandle, + chanHandle->xferChan); +#ifndef MCBSP_LOOPJOB_ENABLE + + /* free the already allocated dummy PaRAM entries */ + EDMA3_DRV_freeChannel(chanHandle->edmaHandle, + Mcbsp_edmaChanNum); +#endif + + if (MCBSP_STATUS_COMPLETED == status) + { + /* free the EDMA PaRAM entries used for Ping pong buffer */ + for (linkCnt = 0; linkCnt < Mcbsp_MAXLINKCNT; linkCnt++) + { + status = EDMA3_DRV_freeChannel( + chanHandle->edmaHandle, + chanHandle->pramTbl[linkCnt]); + if (MCBSP_STATUS_COMPLETED != status) + { + break; + } + } + } + + if (MCBSP_STATUS_COMPLETED == status) + { + /* Set the state of the channel as closed */ + chanHandle->chanState = Mcbsp_DriverState_CLOSED; + + /* Set the Muted state to FALSE */ + chanHandle->bMuteON = FALSE; + + /* Set the Paused state to FALSE */ + chanHandle->paused = FALSE; + } + } + + /* Writeback Global Object */ + Mcbsp_osalEndMemAccess ((void *)chanHandle->devHandle, sizeof(Mcbsp_Object)); + } + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (criticalSectionInfo); + + return (status); +} + +/** + * \brief Closes the McBSP device instance from use. + * This API is called by the application when it no longer requires the + * device instance. Note that all the channels have to be closed for + * the device instance to be deleted sucessfully. + * + * \param devp [IN] Handle to the device created. + * + * \return MCBSP_STATUS_COMPLETED if successful + * MCBSP_STATUS_ABORTED if not successful + * + * \enter devp should be non NULL and valid pointer, + * + * \leave Not implemented + */ +int32_t mcbspUnBindDev(void* devp) +{ + Mcbsp_Object *hInst = NULL; + Mcbsp_Object_Unpadded *instHandle = NULL; + int32_t status = MCBSP_STATUS_COMPLETED; + void* criticalSectionInfo; + + /* Begin Critical Section before accessing shared resources. */ + criticalSectionInfo = Mcbsp_osalEnterMultipleCoreCriticalSection (); + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if (NULL == devp) + { + status = MCBSP_ERR_BADARGS; + } + else + { +#endif /* MCBSP_DISABLE_INPUT_PARAM_CHECK */ + + hInst = (Mcbsp_Object *)devp; + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)hInst, sizeof(Mcbsp_Object)); + + instHandle = (Mcbsp_Object_Unpadded *)&(hInst->obj); + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if ((CSL_MCBSP_PER_CNT <= instHandle->instNum) || + (Mcbsp_DriverState_CLOSED != instHandle->xmtObj.chanState) || + (Mcbsp_DriverState_CLOSED != instHandle->rcvObj.chanState)) + { + status = MCBSP_ERR_BADARGS; + } + } +#endif /* MCBSP_DISABLE_INPUT_PARAM_CHECK */ + + if (MCBSP_STATUS_COMPLETED == status) + { + /* reset the Mcbsp */ + instHandle->hwInfo.regs->SPCR = 0x00u; + + /* Mark driver state as deleted and module as not in use */ + instHandle->devState = Mcbsp_DriverState_DELETED; + instHandle->inUse = FALSE; + + /* update the user params to the instance object */ + instHandle->instNum = -1; + + /* Intialize the mcbsp driver to default values */ + memset(instHandle, 0, sizeof(Mcbsp_Object_Unpadded)); + + /* Writeback Global Object */ + Mcbsp_osalEndMemAccess ((void *)hInst, sizeof(Mcbsp_Object)); + } + + /* End Critical Section */ + Mcbsp_osalExitMultipleCoreCriticalSection (criticalSectionInfo); + + return status; +} + +/** + * \brief Submit a I/O buffer to a channel for processing + * + * The application calls this function to cause the driver + * to process the Mcbsp_IOBuf for read/write/flush/abort operations. + * + * \param chanp [IN] Pointer to channel + * \param ioBuf [IN] Pointer to buffer to be submitted + * + * \return MCBSP_STATUS_COMPLETED, if buffer is fully processed + * MCBSP_STATUS_ABORTED, if buffer is aborted + * MCBSP_STATUS_PENDING, if buffer is not fully processed + * MCBSP_ERR_BADIO in case of an error in processing + * + */ +int32_t mcbspSubmitChan(void* chanp, Mcbsp_IOBuf *const ioBuf) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_ChannelObj *chanHandle = NULL; + int32_t status = MCBSP_STATUS_COMPLETED; + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if ((NULL == chanp) || ( NULL == ioBuf)) + { + status = MCBSP_ERR_BADARGS; + } + else + { +#endif + chanHandle = (Mcbsp_ChannelObj *)chanp; + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + + if ((NULL == chanHandle) || (NULL == chanHandle->devHandle)) + { + status = MCBSP_ERR_BADARGS; + } + else + { +#endif + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if (NULL == instHandle) + { + status = MCBSP_ERR_BADARGS; + } + else + { + if (NULL == ioBuf->addr) + { + if ((Mcbsp_IOBuf_Cmd_READ == ioBuf->cmd) || + (Mcbsp_IOBuf_Cmd_WRITE == ioBuf->cmd)) + { + status = MCBSP_ERR_BADARGS; + } + } + } + } + } +#endif /* MCBSP_DISABLE_INPUT_PARAM_CHECK */ + + if (MCBSP_STATUS_COMPLETED == status) + { + /* process the command sent by the application */ + switch (ioBuf->cmd) + { + case Mcbsp_IOBuf_Cmd_READ: + case Mcbsp_IOBuf_Cmd_WRITE: + if (TRUE != chanHandle->flush) + { + status = mcbspSubmitReq(instHandle,chanHandle,ioBuf); + } + else + { + status = MCBSP_ERR_BADIO; + } + break; + case Mcbsp_IOBuf_Cmd_FLUSH: + /* Flush command has been issued need to abort the receive * + * channel buffers and complete the TX buffers normally */ + chanHandle->flush = TRUE; + Mcbsp_localAbortReset(chanHandle); + chanHandle->flush = FALSE; + break; + case Mcbsp_IOBuf_Cmd_ABORT: + Mcbsp_localAbortReset(chanHandle); + break; + default: + status = MCBSP_ERR_BADIO; + break; + } + } + + return status; +} + +/** + * \brief Implements the IOCTLS for McBSP driver. + * + * ControlChan() implements recieved IOCTL commands from the + * application and executes them accordingly. + * + * \param chanp [IN] Pointer to channel + * \param cmd [IN] specific IOCTL command + * \param arg [IN] arguments required for specific commands + * + * \return MCBSP_STATUS_COMPLETED, if command is executed correctly + * MCBSP_STATUS_ABORTED, if command returns error during execution + * MCBSP_ERR_NOTIMPL, if command is not supported + * MCBSP_ERR_BADARGS if args are not correct + */ +int32_t mcbspControlChan(void* chanp, Mcbsp_IOCTL cmd, void* arg) +{ + Mcbsp_ChannelObj *chanHandle = NULL; + int32_t status = MCBSP_STATUS_COMPLETED; + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if (NULL == chanp) + { + status = MCBSP_ERR_BADARGS; + } + else + { +#endif /* MCBSP_DISABLE_INPUT_PARAM_CHECK */ + + chanHandle = (Mcbsp_ChannelObj *)chanp; + + /* Invalidate the Cache Contents */ + Mcbsp_osalBeginMemAccess ((void *)chanHandle->devHandle, sizeof(Mcbsp_Object)); + +#ifndef MCBSP_DISABLE_INPUT_PARAM_CHECK + if (NULL == chanHandle->devHandle) + { + status = MCBSP_ERR_BADARGS; + } + } +#endif + + if (MCBSP_STATUS_COMPLETED == status) + { + /* call the function to process the IOCTL command */ + status = Mcbsp_localSubmitIoctl( + chanHandle, + cmd, + arg, + NULL); + } + + /* Writeback Global Object */ + Mcbsp_osalEndMemAccess ((void *)chanHandle->devHandle, sizeof(Mcbsp_Object)); + + return (status); +} + +/** + * \brief McBSP Tx ISR function + * + * This Function is the interrupt service routine for the Mcbsp TX + * event. + * + * \param hChan [IN] Handle to the channel + * + * \return None + */ +void mcbspGblXmtIsr(void *hChan) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_ChannelObj *chanHandle = (Mcbsp_ChannelObj *)hChan; + + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); + + /* Only DMA mode of operation is supported by the Mcbsp driver hence we * + * will only check if there is an sync error and notify the application */ + if (CSL_MCBSP_SPCR_XSYNCERR_MASK == + (CSL_MCBSP_SPCR_XSYNCERR_MASK & instHandle->hwInfo.regs->SPCR)) + { + /* call the application registered global callback function */ + if (NULL != chanHandle->gblErrCbk) + { + (*chanHandle->gblErrCbk)((uint32_t)chanHandle, + instHandle->hwInfo.regs->SPCR, + NULL); + } + } + + return; +} + +/** + * \brief McBSP Rx ISR function + * + * This Function is the interrupt service routine for the Mcbsp RX + * event. + * + * \param hChan [IN] Handle to the channel + * + * \return None + */ +void mcbspGblRcvIsr(void *hChan) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_ChannelObj *chanHandle = (Mcbsp_ChannelObj *)hChan; + + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); + + /* Only DMA mode of operation is supported by the Mcbsp driver hence we * + * will only check if there is an sync error and notify the application */ + if (CSL_MCBSP_SPCR_RSYNCERR_MASK == + (CSL_MCBSP_SPCR_RSYNCERR_MASK & instHandle->hwInfo.regs->SPCR)) + { + /* call the application registered global callback function */ + if (NULL != chanHandle->gblErrCbk) + { + (*chanHandle->gblErrCbk)((uint32_t)chanHandle, + instHandle->hwInfo.regs->SPCR, + NULL); + } + } + + return; +} + +/*============================================================================*/ +/* LOCAL FUNCTION DEFINTIONS */ +/*============================================================================*/ + +/** + * \brief Submit a I/O buffer to a channel for processing + * + * This function is called with the Mcbsp_IOBuf_Cmd_READ or Mcbsp_IOBuf_Cmd_WRITE + * command to process the IOP. The function handles the MCBSP mode. In case + * that the driver is currently idle it sets up buffer for transfer. In case + * that the driver is currently processing a buffer then it will queue up the + * current buffer and exit. + * + * \param instHandle [IN] pointer to the instance object + * \param chanHandle [IN] handle to the channel + * \param ioBuf [IN] pointer to Mcbsp I/O buffer. + * + * \return MCBSP_STATUS_PENDING in case the buffer is sucesfully processed + * MCBSP_ERR_BADIO in case of any error. + */ +int32_t mcbspSubmitReq(Mcbsp_Object_Unpadded *instHandle, + Mcbsp_ChannelObj *chanHandle, + Mcbsp_IOBuf *ioBuf) +{ + void* criticalSectionInfo; + int32_t status = MCBSP_STATUS_COMPLETED; + + if ((NULL == chanHandle) || (NULL == ioBuf) || (NULL == instHandle)) + { + return MCBSP_ERR_BADIO; + } + if((0 == ioBuf->size) || (ioBuf->size > Mcbsp_MAX_IOBUF_SIZE)) + { + return MCBSP_ERR_BADIO; + } + + /* clean the buffers if the cache operation mode is enabled */ + if (TRUE == instHandle->enablecache) + { + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* Invalidate the cache */ + Mcbsp_osalBeginMemAccess(ioBuf->addr, ioBuf->size); + } + else + { + /* Writeback the cache */ + Mcbsp_osalEndMemAccess(ioBuf->addr, ioBuf->size); + } + } + + /*==========================MCBSP MODE ===================================*/ + if (Mcbsp_DevMode_McBSP == instHandle->mode) + { + /* We are entering the crictical section because the current active * + * IOP is being check and it can become NULL at any point. Hence we * + * will protect this code from the interrupt handler. */ + criticalSectionInfo = Mcbsp_osalEnterSingleCoreCriticalSection(); + +#ifdef MCBSP_LOOPJOB_ENABLE + if ((Mcbsp_MAXLINKCNT <= chanHandle->submitCount) || +#else + /* We now have 3 buffers loaded in the EDMA */ + if (((Mcbsp_MAXLINKCNT + 1) <= chanHandle->submitCount) || +#endif + (TRUE == chanHandle->paused)) + { + /* There are enough buffers programmed in the EDMA or if the MCBSP* + * is issued a pause command,hence queue buffer in to the pending * + * queue */ + chanHandle->submitCount++; + + Mcbsp_osalQueuePut(chanHandle->ptrQPendList, (Mcbsp_QueueElem *)ioBuf); + + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); + } + else + { + /* Either one of the paramset or Both the paramsets are free */ + + /* increment the submit count */ + chanHandle->submitCount++; + + Mcbsp_osalQueuePut(chanHandle->ptrQFloatList, (Mcbsp_QueueElem *)ioBuf); + + Mcbsp_localLoadPktToEdma(chanHandle,ioBuf); + + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); + + } /* Pending queue empty or not*/ + } + if (MCBSP_STATUS_COMPLETED == status) + { + status = MCBSP_STATUS_PENDING; + } + return (status); +} + +/** + * \brief McBSP SPCR configuration function + * + * This Function is used to set/reset specific bit of SPCR as specified in + * the given mask. + * + * \param instHandle [IN] pointer to the mcbsp instance object. + * \param selectMask [IN] the SPCR control mask + * + * \return MCBSP_STATUS_COMPLETED if successful + * + * MCBSP_ERR_BADARGS if not successful + */ +int32_t Mcbsp_localResetCtrl(Mcbsp_Object_Unpadded *instHandle, uint32_t selectMask) +{ + if ((NULL == instHandle) || (NULL == instHandle->hwInfo.regs)) + { + return MCBSP_ERR_BADARGS; + } + + /* Configuring SPCR for Frame sync generator enable/disable */ + if (0u != (selectMask & Mcbsp_SpcrCtrl_FSYNC_DISABLE)) + { + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_FRST_MASK ); + } + + if (0 != (selectMask & Mcbsp_SpcrCtrl_RX_DISABLE)) + { + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_RRST_MASK ); + } + + /* start the sample rate generator */ + if (0u != (selectMask & Mcbsp_SpcrCtrl_SRG_ENABLE)) + { + instHandle->hwInfo.regs->SPCR |= CSL_MCBSP_SPCR_GRST_MASK; + } + + /* Configuring SPCR for Transmit enable/disable */ + if (0 != (selectMask & Mcbsp_SpcrCtrl_TX_DISABLE)) + { + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_XRST_MASK); + } + + /* Configuring SPCR for transmit section enable */ + if (0 != (selectMask & Mcbsp_SpcrCtrl_TX_ENABLE)) + { + instHandle->hwInfo.regs->SPCR |= CSL_MCBSP_SPCR_XRST_MASK; + } + + /* Configuring SPCR for Receive section enable */ + if (0 != (selectMask & Mcbsp_SpcrCtrl_RX_ENABLE)) + { + instHandle->hwInfo.regs->SPCR |= CSL_MCBSP_SPCR_RRST_MASK ; + } + + /* Set the FRST bit to 1 to start the internal frame sync generator */ + if (0u != (selectMask & Mcbsp_SpcrCtrl_FSYNC_ENABLE)) + { + instHandle->hwInfo.regs->SPCR |= CSL_MCBSP_SPCR_FRST_MASK; + } + + /* Configuring SPCR for sample rate generator enable/disable */ + if (0u != (selectMask & Mcbsp_SpcrCtrl_SRG_DISABLE)) + { + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_GRST_MASK); + } + + return MCBSP_STATUS_COMPLETED; +} + +/** + * \brief This function completes the current pending request and then + * invokes the application registered callback. + * + * \param chanHandle [IN] Handle to the channel + * + * \return None + * + * \enter chanHandle is a valid non null pointer + * + * \leave Not implemented + */ +void Mcbsp_localCompleteCurrentIo(Mcbsp_ChannelObj *chanHandle) +{ + Mcbsp_IOBuf *ioBuf = NULL; + + if (TRUE == chanHandle->isTempIOBufValid) + { + ioBuf = chanHandle->tempIOBuf; + + chanHandle->tempIOBuf = NULL; + chanHandle->isTempIOBufValid = FALSE; + /* call the completion callback function registered with us * + * during channel creation */ + if ((NULL != chanHandle->cbFxn) && (NULL != chanHandle->cbArg)) + { + /* Application callback */ + (*chanHandle->cbFxn)((void*)chanHandle->cbArg,ioBuf); + } + } + + chanHandle->currentError = MCBSP_STATUS_COMPLETED; + chanHandle->userDataBufferSize = 0; +} + +/** + * \brief This function configures the transmit section of the mcbsp + * sync properties. + * + * \param instHandle [IN] pointer to the instance object. + * \param params [IN] User supplied channel parameters + * + * \return MCBSP_ERR_BADARGS if configuration fails. + * MCBSP_STATUS_COMPLETED if configuration is sucessful. + */ +int32_t Mcbsp_localConfigureXmtChannel(Mcbsp_Object_Unpadded *instHandle, + Mcbsp_ChanParams *params) +{ + uint32_t tempVal = 0x00; + int32_t status = MCBSP_STATUS_COMPLETED; + + if ((NULL == instHandle) || (NULL == params)) + { + return MCBSP_ERR_BADARGS; + } + + /* configure the transmit section */ + /* configure the transmit interrupt setting */ + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_XINTM_MASK); + instHandle->hwInfo.regs->SPCR |= + (params->chanConfig->intMode << CSL_MCBSP_SPCR_XINTM_SHIFT); + + /* configure the DX enabler */ + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_DXENA_MASK); + instHandle->hwInfo.regs->SPCR |= + (params->chanConfig->dxState << CSL_MCBSP_SPCR_DXENA_SHIFT); + + /* configure the transmit control register settings */ + instHandle->hwInfo.regs->XCR &= (~CSL_MCBSP_XCR_XPHASE_MASK); + instHandle->hwInfo.regs->XCR |= + (params->chanConfig->phaseNum << CSL_MCBSP_XCR_XPHASE_SHIFT); + + /* configure the frame length for single and dual phase frames */ + instHandle->hwInfo.regs->XCR &= (~CSL_MCBSP_XCR_XFRLEN1_MASK); + instHandle->hwInfo.regs->XCR |= + ((params->chanConfig->frmLen1 - 1u) << CSL_MCBSP_XCR_XFRLEN1_SHIFT); + + /* configure the word length of the single and dual phase frames */ + switch (params->chanConfig->wrdLen1) + { + case Mcbsp_WordLength_8: + tempVal = 0u; + break; + case Mcbsp_WordLength_12: + tempVal = 1u; + break; + case Mcbsp_WordLength_16: + tempVal = 2u; + break; + case Mcbsp_WordLength_20: + tempVal = 3u; + break; + case Mcbsp_WordLength_24: + tempVal = 4u; + break; + case Mcbsp_WordLength_32: + tempVal = 5u; + break; + default: + /* wordlength is not supported by the driver */ + status = MCBSP_ERR_BADARGS; + break; + } + + instHandle->hwInfo.regs->XCR &= (~CSL_MCBSP_XCR_XWDLEN1_MASK); + instHandle->hwInfo.regs->XCR |= + (tempVal << CSL_MCBSP_XCR_XWDLEN1_SHIFT); + + if (Mcbsp_Phase_DUAL == params->chanConfig->phaseNum) + { + + instHandle->hwInfo.regs->XCR &= (~CSL_MCBSP_XCR_XFRLEN2_MASK); + instHandle->hwInfo.regs->XCR |= + ((params->chanConfig->frmLen2 -1u) << CSL_MCBSP_XCR_XFRLEN2_SHIFT); + + /* configure the word length of the single and dual phase frames */ + switch (params->chanConfig->wrdLen2) + { + case Mcbsp_WordLength_8: + tempVal = 0u; + break; + case Mcbsp_WordLength_12: + tempVal = 1u; + break; + case Mcbsp_WordLength_16: + tempVal = 2u; + break; + case Mcbsp_WordLength_20: + tempVal = 3u; + break; + case Mcbsp_WordLength_24: + tempVal = 4u; + break; + case Mcbsp_WordLength_32: + tempVal = 5u; + break; + default: + /* wordlength is not supported by the driver */ + status = MCBSP_ERR_BADARGS; + break; + } + + instHandle->hwInfo.regs->XCR &= (~CSL_MCBSP_XCR_XWDLEN2_MASK); + instHandle->hwInfo.regs->XCR |= + (tempVal << CSL_MCBSP_XCR_XWDLEN2_SHIFT); + } + /* set the companding selection */ + instHandle->hwInfo.regs->XCR &= (~CSL_MCBSP_XCR_XCOMPAND_MASK); + instHandle->hwInfo.regs->XCR |= + (params->chanConfig->compandSel << CSL_MCBSP_XCR_XCOMPAND_SHIFT); + + /* set the bit reverse settings */ + instHandle->hwInfo.regs->XCR &= (~CSL_MCBSP_XCR_XWDREVRS_MASK); + instHandle->hwInfo.regs->XCR |= + (params->chanConfig->bitReversal << CSL_MCBSP_XCR_XWDREVRS_SHIFT); + + /* frame ignore settings */ + instHandle->hwInfo.regs->XCR &= (~CSL_MCBSP_XCR_XFIG_MASK); + instHandle->hwInfo.regs->XCR |= + (params->chanConfig->frmSyncIgn << CSL_MCBSP_XCR_XFIG_SHIFT); + + /* configure the data delay */ + instHandle->hwInfo.regs->XCR &= (~CSL_MCBSP_XCR_XDATDLY_MASK); + instHandle->hwInfo.regs->XCR |= + (params->chanConfig->dataDelay << CSL_MCBSP_XCR_XDATDLY_SHIFT); + + /* configure the multi channel control register settings */ + instHandle->hwInfo.regs->MCR &= (~CSL_MCBSP_MCR_XMCM_MASK); + instHandle->hwInfo.regs->MCR |= (params->multiChanCtrl->multiChanMode + << CSL_MCBSP_MCR_XMCM_SHIFT); + + /* select the partition mode and the channel selection controls */ + instHandle->hwInfo.regs->MCR &= (~CSL_MCBSP_MCR_XPABLK_MASK); + instHandle->hwInfo.regs->MCR |= (params->multiChanCtrl->partitionSelA + << CSL_MCBSP_MCR_XPABLK_SHIFT); + + instHandle->hwInfo.regs->MCR &= (~CSL_MCBSP_MCR_XPBBLK_MASK); + instHandle->hwInfo.regs->MCR |= (params->multiChanCtrl->partitionSelB + << CSL_MCBSP_MCR_XPBBLK_SHIFT); + + instHandle->hwInfo.regs->MCR &= (~CSL_MCBSP_MCR_XMCME_MASK); + instHandle->hwInfo.regs->MCR |= (params->multiChanCtrl->partitionMode + << CSL_MCBSP_MCR_XMCME_SHIFT); + + /* Configure the channels to be enabled */ + instHandle->hwInfo.regs->XCERE0 = params->chanEnableMask[0]; + instHandle->hwInfo.regs->XCERE1 = params->chanEnableMask[1]; + instHandle->hwInfo.regs->XCERE2 = params->chanEnableMask[2]; + instHandle->hwInfo.regs->XCERE3 = params->chanEnableMask[3]; + + + /* configure the clock polarity */ + if (Mcbsp_ClkPol_RISING_EDGE == params->clkSetup->clkPolarity) + { + /* clock data sampled on rising edge */ + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_CLKXP_MASK); + } + else + { + /* clock data sampled on falling edge */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_CLKXP_MASK); + } + + /* configure the frame sync polarity */ + if (Mcbsp_FsPol_ACTIVE_HIGH == params->clkSetup->frmSyncPolarity) + { + /* frame sync polarity is active high */ + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_FSXP_MASK); + } + else + { + /* frame sync polarity is active low */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_FSXP_MASK); + } + + /* check if the frame sync generator is to be enabled for this TX section */ + if (Mcbsp_FsClkMode_EXTERNAL == params->clkSetup->frmSyncMode) + { + /* External frame sync to be used */ + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_FSXM_MASK); + + /* frame sync generator needs to be disabled */ + instHandle->txFsgEnable = FALSE; + } + else + { + /* internal frame sync to be used */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_FSXM_MASK); + + /* The FRST and GRST has to be cleared to configure the FSGM bit. + * By clearing the FRST and GRST bit, the sample rate generator and the + * frame sync generator will be kept in the reset mode. + * Ref IR SDOCM00077966 + */ + tempVal = instHandle->hwInfo.regs->SPCR; + instHandle->hwInfo.regs->SPCR &= ~(CSL_MCBSP_SPCR_FRST_MASK | + CSL_MCBSP_SPCR_GRST_MASK ); + + /* could be internal or configured for DXR to XSR copy */ + if (Mcbsp_FsClkMode_INTERNAL == params->clkSetup->frmSyncMode) + { + /* set the FSGM bit in the SRGR register */ + instHandle->hwInfo.regs->SRGR |= (CSL_MCBSP_SRGR_FSGM_MASK); + + /* frame sync generator needs to be enabled */ + instHandle->txFsgEnable = TRUE; + } + else + { /* DXR to XSR copy generates frame sync */ + /* reset the FSGM bit in the SRGR register */ + instHandle->hwInfo.regs->SRGR &= (~CSL_MCBSP_SRGR_FSGM_MASK); + + /* frame sync generator needs to be disabled */ + instHandle->txFsgEnable = FALSE; + } + /* The SPCR register values are reverted back once the FSGM bit is set + */ + instHandle->hwInfo.regs->SPCR = tempVal; + } + + /* configure the clock mode (external or internal) */ + if (Mcbsp_TxRxClkMode_EXTERNAL == params->clkSetup->clkMode) + { + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_CLKXM_MASK); + + if (TRUE == instHandle->txFsgEnable) + { + /* frame sync generator is using the internal clock hence need to * + * enable the sample rate generator */ + instHandle->txSrgEnable = TRUE; + } + else + { + /* dont require to enable the sample rate generator */ + instHandle->txSrgEnable = FALSE; + } + } + else + { + /* external mode clock enabled */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_CLKXM_MASK); + + /* sample rate generator is enabled */ + instHandle->txSrgEnable = TRUE; + } + + return (status); +} + + +/** + * \brief This function configures the receives section of the mcbsp. + * + * \param instHandle [IN] pointer to the instance object. + * \param params [IN] User supplied channel parameters + * + * \return MCBSP_ERR_BADARGS if configuration fails. + * MCBSP_STATUS_COMPLETED if confioguration is sucessful. + */ +int32_t Mcbsp_localConfigureRcvChannel(Mcbsp_Object_Unpadded *instHandle, + Mcbsp_ChanParams *params) +{ + uint32_t tempVal = 0x00; + int32_t status = MCBSP_STATUS_COMPLETED; + + if ((NULL == instHandle) || (NULL == params)) + { + return MCBSP_ERR_BADARGS; + } + + /* configure the receive section */ + /* configure the receive interrupt setting */ + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_RINTM_MASK); + instHandle->hwInfo.regs->SPCR |= + (params->chanConfig->intMode << CSL_MCBSP_SPCR_RINTM_SHIFT); + + /* configure the Receive sign-extension and justification */ + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_RJUST_MASK); + instHandle->hwInfo.regs->SPCR |= + (params->chanConfig->rjust << CSL_MCBSP_SPCR_RJUST_SHIFT); + + /* configure the receive control register settings */ + instHandle->hwInfo.regs->RCR &= (~CSL_MCBSP_RCR_RPHASE_MASK); + instHandle->hwInfo.regs->RCR |= + (params->chanConfig->phaseNum << CSL_MCBSP_RCR_RPHASE_SHIFT); + + /* configure the frame length for single and dual phase frames */ + instHandle->hwInfo.regs->RCR &= (~CSL_MCBSP_RCR_RFRLEN1_MASK); + instHandle->hwInfo.regs->RCR |= + ((params->chanConfig->frmLen1 - 1u) << CSL_MCBSP_RCR_RFRLEN1_SHIFT); + + /* configure the word length of the single and dual phase frames */ + switch (params->chanConfig->wrdLen1) + { + case Mcbsp_WordLength_8: + tempVal = 0u; + break; + case Mcbsp_WordLength_12: + tempVal = 1u; + break; + case Mcbsp_WordLength_16: + tempVal = 2u; + break; + case Mcbsp_WordLength_20: + tempVal = 3u; + break; + case Mcbsp_WordLength_24: + tempVal = 4u; + break; + case Mcbsp_WordLength_32: + tempVal = 5u; + break; + default: + /* wordlength is not supported by the driver */ + status = MCBSP_ERR_BADARGS; + break; + } + + + instHandle->hwInfo.regs->RCR &= (~CSL_MCBSP_RCR_RWDLEN1_MASK); + instHandle->hwInfo.regs->RCR |= + (tempVal << CSL_MCBSP_RCR_RWDLEN1_SHIFT); + + if (Mcbsp_Phase_DUAL == params->chanConfig->phaseNum) + { + instHandle->hwInfo.regs->RCR &= (~CSL_MCBSP_RCR_RFRLEN2_MASK); + instHandle->hwInfo.regs->RCR |= + ((params->chanConfig->frmLen2 - 1u) << CSL_MCBSP_RCR_RFRLEN2_SHIFT); + + /* configure the word length of the single and dual phase frames */ + switch (params->chanConfig->wrdLen2) + { + case Mcbsp_WordLength_8: + tempVal = 0u; + break; + case Mcbsp_WordLength_12: + tempVal = 1u; + break; + case Mcbsp_WordLength_16: + tempVal = 2u; + break; + case Mcbsp_WordLength_20: + tempVal = 3u; + break; + case Mcbsp_WordLength_24: + tempVal = 4u; + break; + case Mcbsp_WordLength_32: + tempVal = 5u; + break; + default: + /* wordlength is not supported by the driver */ + status = MCBSP_ERR_BADARGS; + break; + } + + instHandle->hwInfo.regs->RCR &= (~CSL_MCBSP_RCR_RWDLEN2_MASK); + instHandle->hwInfo.regs->RCR |= + (tempVal << CSL_MCBSP_RCR_RWDLEN2_SHIFT); + } + /* set the companding selection */ + instHandle->hwInfo.regs->RCR &= (~CSL_MCBSP_RCR_RCOMPAND_MASK); + instHandle->hwInfo.regs->RCR |= + (params->chanConfig->compandSel << CSL_MCBSP_RCR_RCOMPAND_SHIFT); + + /* set the bit reverse settings */ + instHandle->hwInfo.regs->RCR &= (~CSL_MCBSP_RCR_RWDREVRS_MASK); + instHandle->hwInfo.regs->RCR |= + (params->chanConfig->bitReversal << CSL_MCBSP_RCR_RWDREVRS_SHIFT); + + /* frame ignore settings */ + instHandle->hwInfo.regs->RCR &= (~CSL_MCBSP_RCR_RFIG_MASK); + instHandle->hwInfo.regs->RCR |= + (params->chanConfig->frmSyncIgn << CSL_MCBSP_RCR_RFIG_SHIFT); + + /* configure the data delay */ + instHandle->hwInfo.regs->RCR &= (~CSL_MCBSP_RCR_RDATDLY_MASK); + instHandle->hwInfo.regs->RCR |= + (params->chanConfig->dataDelay << CSL_MCBSP_RCR_RDATDLY_SHIFT); + + /* Configure the channels to be enabled */ + instHandle->hwInfo.regs->RCERE0 = params->chanEnableMask[0]; + instHandle->hwInfo.regs->RCERE1 = params->chanEnableMask[1]; + instHandle->hwInfo.regs->RCERE2 = params->chanEnableMask[2]; + instHandle->hwInfo.regs->RCERE3 = params->chanEnableMask[3]; + + /* configure the MCR register */ + switch (params->multiChanCtrl->multiChanMode) + { + case Mcbsp_McmMode_ALL_CHAN_ENABLED_UNMASKED: + case Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED: + break; + default: + status = MCBSP_ERR_BADARGS; + break; + } + + if (MCBSP_STATUS_COMPLETED == status) + { + instHandle->hwInfo.regs->MCR &= (~CSL_MCBSP_MCR_RMCM_MASK); + instHandle->hwInfo.regs->MCR |= (params->multiChanCtrl->multiChanMode + << CSL_MCBSP_MCR_RMCM_SHIFT); + } + + /* select the partition mode and the channel selection controls */ + instHandle->hwInfo.regs->MCR &= (~CSL_MCBSP_MCR_RPABLK_MASK); + instHandle->hwInfo.regs->MCR |= (params->multiChanCtrl->partitionSelA + << CSL_MCBSP_MCR_RPABLK_SHIFT); + + instHandle->hwInfo.regs->MCR &= (~CSL_MCBSP_MCR_RPBBLK_MASK); + instHandle->hwInfo.regs->MCR |= (params->multiChanCtrl->partitionSelB + << CSL_MCBSP_MCR_RPBBLK_SHIFT); + + instHandle->hwInfo.regs->MCR &= (~CSL_MCBSP_MCR_RMCME_MASK); + instHandle->hwInfo.regs->MCR |= (params->multiChanCtrl->partitionMode + << CSL_MCBSP_MCR_RMCME_SHIFT); + + /* configure the clock polarity */ + if (Mcbsp_ClkPol_RISING_EDGE == params->clkSetup->clkPolarity) + { + /* clock data sampled on rising edge */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_CLKRP_MASK); + } + else + { + /* clock data sampled on falling edge */ + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_CLKRP_MASK); + } + + /* configure the frame sync polarity */ + if (Mcbsp_FsPol_ACTIVE_HIGH == params->clkSetup->frmSyncPolarity) + { + /* frame sync polarity is active high */ + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_FSRP_MASK); + } + else + { + /* frame sync polarity is active low */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_FSRP_MASK); + } + + + /* check if the frame sync generator is to be enabled for this section */ + if (Mcbsp_FsClkMode_INTERNAL == params->clkSetup->frmSyncMode) + { + /* set the frame sync generation mode */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_FSRM_MASK); + + /* frame sync generator needs to be enabled */ + instHandle->rxFsgEnable = TRUE; + } + else + { + /* reset the frame sync generation mode */ + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_FSRM_MASK); + + /* frame sync generator needs to be disabled */ + instHandle->rxFsgEnable = FALSE; + } + + /* configure the clock mode (external or internal) */ + if (Mcbsp_TxRxClkMode_EXTERNAL == params->clkSetup->clkMode) + { + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_CLKRM_MASK); + + if (TRUE == instHandle->rxFsgEnable) + { + /* frame sync generator is using the internal clock hence need to * + * enable the sample rate generator */ + instHandle->rxSrgEnable = TRUE; + } + else + { + /* dont require to enable the sample rate generator */ + instHandle->rxSrgEnable = FALSE; + } + } + else + { + /* external mode clock */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_CLKRM_MASK); + + /* sample rate generator is enabled */ + instHandle->rxSrgEnable = TRUE; + } + return (status); +} + +/** + * \brief This function configures the sample rate generator and frame + * sync properties. + * + * \param instHandle [IN] pointer to the instance object. + * \param chanHandle [IN] Handle to the channel. + * + * \return MCBSP_ERR_BADARGS if calculation fails. + * MCBSP_STATUS_COMPLETED if calculation is sucessful. + */ +int32_t Mcbsp_localConfigureSrgr(Mcbsp_Object_Unpadded *instHandle, + Mcbsp_ChannelObj *chanHandle) +{ + Bool srgrConfig = FALSE; + uint32_t clkgDiv = 0x00; + uint32_t noOfBits = 0x00; + uint32_t framePeriod = 0x00; + Bool sclkme = 0x00; + Bool clksm = 0x00; + int32_t status = MCBSP_STATUS_COMPLETED; + void* criticalSectionInfo; + + if ((NULL == instHandle) || (NULL == chanHandle)) + { + return MCBSP_ERR_BADARGS; + } + + /* check if the SRGR is not configured already */ + /* critical section starts */ + criticalSectionInfo = Mcbsp_osalEnterSingleCoreCriticalSection(); + + if (FALSE == instHandle->srgConfigured) + { + /* set the status that SRGR is configured */ + instHandle->srgConfigured = TRUE; + + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); + + /* check if this channel requires the SRGR to be enabled */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + if (TRUE == instHandle->rxSrgEnable) + { + /* Need to configure the SRGR */ + srgrConfig = TRUE; + } + else + { + instHandle->srgConfigured = FALSE; + } + } + else + { + if (TRUE == instHandle->txSrgEnable) + { + /* Need to configure the SRGR */ + srgrConfig = TRUE; + } + else + { + instHandle->srgConfigured = FALSE; + } + } + } + else + { + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); + } + + if (TRUE == srgrConfig) + { + /* set the input clock selection for Sample rate generator */ + switch (instHandle->srgrConfig.srgInputClkMode) + { + /* Input clock is CLKS */ + case Mcbsp_SrgClk_CLKS: + sclkme = 0x00; + clksm = 0x00; + + /* set the CLKS polarity (only if CLKS is used) */ + instHandle->hwInfo.regs->SRGR &= (~CSL_MCBSP_SRGR_CLKSP_MASK); + instHandle->hwInfo.regs->SRGR |= + (instHandle->srgrConfig.clksPolarity + << CSL_MCBSP_SRGR_CLKSP_SHIFT); + + /* set the GSYNC option */ + instHandle->hwInfo.regs->SRGR &= (~CSL_MCBSP_SRGR_GSYNC_MASK); + instHandle->hwInfo.regs->SRGR |= + (instHandle->srgrConfig.gSync + << CSL_MCBSP_SRGR_GSYNC_SHIFT); + break; + /* Input clock for SRG is from CPU clock */ + case Mcbsp_SrgClk_CLKCPU: + sclkme = 0x00; + clksm = 0x01u; + break; + /* Input clock is from receive pin */ + case Mcbsp_SrgClk_CLKR: + sclkme = 0x01u; + clksm = 0x00; + break; + /* Input clock is from transmit pin */ + case Mcbsp_SrgClk_CLKX: + sclkme = 0x01u; + clksm = 0x01u; + break; + default: + status = MCBSP_ERR_BADARGS; + break; + } + + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_SCLKME_MASK); + instHandle->hwInfo.regs->PCR |= (sclkme << CSL_MCBSP_PCR_SCLKME_SHIFT); + + instHandle->hwInfo.regs->SRGR &= (~CSL_MCBSP_SRGR_CLKSM_MASK); + instHandle->hwInfo.regs->SRGR |= (clksm << CSL_MCBSP_SRGR_CLKSM_SHIFT); + + /* calculate and set the CLKG div values */ + if (Mcbsp_Phase_DUAL == chanHandle->chanConfig.phaseNum) + { + noOfBits = ((chanHandle->chanConfig.wrdLen1 + * chanHandle->chanConfig.frmLen1) + + (chanHandle->chanConfig.wrdLen2 + * chanHandle->chanConfig.frmLen2)); + } + else + { + noOfBits = (chanHandle->chanConfig.wrdLen1 + * chanHandle->chanConfig.frmLen1) + + chanHandle->chanConfig.dataDelay; + } + + clkgDiv = ((instHandle->srgrConfig.srgrInputFreq/ + (chanHandle->clkSetup.samplingRate + * noOfBits)) - 1u); + + framePeriod = (noOfBits - 1u); + + if ((0xFF < clkgDiv) || (0xFFF < framePeriod) || + (MCBSP_STATUS_COMPLETED != status)) + { + /* The CLKGDIV or frame period value has exceeded the limit */ + status = MCBSP_ERR_BADARGS; + } + else + { + /* set the value of the CLKGDIV */ + instHandle->hwInfo.regs->SRGR &= (~CSL_MCBSP_SRGR_CLKGDV_MASK); + instHandle->hwInfo.regs->SRGR |= clkgDiv; + + /* set the value of the frame period */ + instHandle->hwInfo.regs->SRGR &= (~CSL_MCBSP_SRGR_FPER_MASK); + instHandle->hwInfo.regs->SRGR |= + (framePeriod << CSL_MCBSP_SRGR_FPER_SHIFT); + + /* set the frame width */ + instHandle->hwInfo.regs->SRGR &= (~CSL_MCBSP_SRGR_FWID_MASK); + instHandle->hwInfo.regs->SRGR |= + (instHandle->srgrConfig.srgFrmPulseWidth << + CSL_MCBSP_SRGR_FWID_SHIFT); + } + } + + return (status); +} + +/** + * \brief Abort the queued up requests. + * + * This commands aborts all the pending IO requests and returns them + * to the application. The current state of the IO request will be set + * to ABORTED. + * + * \param chanHandle [IN] Handle to the channel whose requests are to be + * aborted + * + * \return None + */ +void Mcbsp_localAbortReset(Mcbsp_ChannelObj *chanHandle) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_IOBuf *ioBuf = NULL; + void* criticalSectionInfo; + uint32_t timeoutCount = 0x00; + + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); + + /* initialize the retry count value */ + timeoutCount = instHandle->retryCount; + + /* critical section starts */ + criticalSectionInfo = Mcbsp_osalEnterSingleCoreCriticalSection(); + + if (Mcbsp_DevMode_McBSP == instHandle->mode) + { + /* Disable the EDMA transfer for the current transfer channel */ + EDMA3_DRV_disableTransfer( + chanHandle->edmaHandle, + chanHandle->xferChan, + EDMA3_DRV_TRIG_MODE_EVENT); + + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + /* Wait for the TX to be empty */ + while ((CSL_MCBSP_SPCR_XEMPTY_MASK == + (CSL_MCBSP_SPCR_XEMPTY_MASK & instHandle->hwInfo.regs->SPCR)) && + (0 != timeoutCount)) + { + timeoutCount--; + } + } + + /* Stop the McBSP instance */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_RX_DISABLE); + } + else + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_TX_DISABLE); + } + + /* Empty the floating queue. Aborted request is currently enqueued * + * in the floating queue. Dequeue the floating request in EDMA * + * param table and return the actual transfer element count */ + while (TRUE != Mcbsp_osalQueueEmpty(chanHandle->ptrQFloatList)) + { + ioBuf = (Mcbsp_IOBuf *) Mcbsp_osalQueueGet(chanHandle->ptrQFloatList); + + if (NULL != ioBuf) + { + /* if FLUSH cmd called for INPUT channel then status is equal * + * to FLUSHED otherwise status is equal to ABORTED */ + if ((TRUE == chanHandle->flush) && + (MCBSP_MODE_INPUT == chanHandle->mode)) + { + ioBuf->status = MCBSP_STATUS_FLUSHED; + } + else + { + ioBuf->status = MCBSP_STATUS_ABORTED; + } + + if ((NULL != chanHandle->cbFxn) && (NULL != chanHandle->cbArg)) + { + /* Application callback */ + (*chanHandle->cbFxn)((void*)chanHandle->cbArg,ioBuf); + } + /* Decrement the submit count */ + chanHandle->submitCount--; + } + } + + /* Empty the pending queue */ + while (TRUE != Mcbsp_osalQueueEmpty(chanHandle->ptrQPendList)) + { + ioBuf = (Mcbsp_IOBuf *) Mcbsp_osalQueueGet(chanHandle->ptrQPendList); + + if (NULL != ioBuf) + { + /* if FLUSH cmd called for INPUT channel then status is equal * + * to MCBSP_STATUS_FLUSHED otherwise status is equal to MCBSP_STATUS_ABORTED */ + if ((TRUE == chanHandle->flush) && + (MCBSP_MODE_INPUT == chanHandle->mode)) + { + ioBuf->status = MCBSP_STATUS_FLUSHED; + } + else + { + ioBuf->status = MCBSP_STATUS_ABORTED; + } + + if ((NULL != chanHandle->cbFxn) && (NULL != chanHandle->cbArg)) + { + /* Application callback */ + (*chanHandle->cbFxn)((void*)chanHandle->cbArg,ioBuf); + } + + /* Decrement the submit count */ + chanHandle->submitCount--; + } + } + + /* As EDMA is disabled it might have thrown an error and set error bit* + * Clear the error bit to enable the transfer again */ + EDMA3_DRV_clearErrorBits(chanHandle->edmaHandle,chanHandle->xferChan); + + /* Configure the EDMA channel and EDMA param tables with * + * intialization configuration as they are configured at the * + * create time. */ + Mcbsp_localEdmaChanPaRAMsetup(chanHandle); + +#ifdef MCBSP_LOOPJOB_ENABLE + + /* configure the FIFO for the specific channel */ + if (TRUE == chanHandle->enableHwFifo) + { + /* Disable and enable the FIFO so that the events are * + * generated to the Mcbsp for the first time */ + mcbspConfigureFifo(&instHandle->hwInfo,chanHandle,FALSE); + mcbspConfigureFifo(&instHandle->hwInfo,chanHandle,TRUE); + } + + /* Enable the EDMA transfer to start the Loop job running */ + EDMA3_DRV_enableTransfer( + chanHandle->edmaHandle, + chanHandle->xferChan, + EDMA3_DRV_TRIG_MODE_EVENT); + + chanHandle->loopjobUpdatedinParamset = TRUE; + chanHandle->nextLinkParamSetToBeUpdated = 0; + + /* start the Mcbsp channel */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_RX_ENABLE); + } + else + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_TX_ENABLE); + } +#endif + } + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); +} +/** + * + * \brief This function configures the Hardware FIFO + * + * \param hMcbsp [IN] pointer to the Mcbsp Hardware information struct + * \param chanHandle [IN] handle to the channel + * \param enableHwFifo [IN] option to Enable or disbale the FIFO + * + * \return None + * + * \enter hMcbsp is a valid non null pointer + * chanHandle is a valid non null pointer + * + * \leave Not implemented + * + */ +void mcbspConfigureFifo(Mcbsp_HwInfo_Unpadded *hMcbsp, + Mcbsp_ChannelObj *chanHandle, + Bool enableHwFifo) +{ + /* check if the HW FIFO usage is requested by the user for this channel */ + if (TRUE == enableHwFifo) + { + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* configure the receive channel */ + /* Step 1 : configure the "WNUMDMA" and "WNUMEVT" bits before * + * enabling the FIFO */ + hMcbsp->fifoRegs->RFIFOCTL = + (1 << CSL_BFIFO_RFIFOCTL_RNUMEVT_SHIFT); + + hMcbsp->fifoRegs->RFIFOCTL |= + (CSL_BFIFO_RFIFOCTL_RNUMDMA_1WORDS + << CSL_BFIFO_RFIFOCTL_RNUMDMA_SHIFT); + + /* enable the FIFO now by setting the "WENA" bit */ + hMcbsp->fifoRegs->RFIFOCTL |= + (CSL_BFIFO_RFIFOCTL_RENA_ENABLED + << CSL_BFIFO_RFIFOCTL_RENA_SHIFT); + } + else + { + /* configure the transmit channel */ + /* Step 1 : configure the "WNUMDMA" and "WNUMEVT" bits before * + * enabling the FIFO */ + hMcbsp->fifoRegs->WFIFOCTL = + (1 << CSL_BFIFO_WFIFOCTL_WNUMEVT_SHIFT); + + hMcbsp->fifoRegs->WFIFOCTL |= + (CSL_BFIFO_WFIFOCTL_WNUMDMA_1WORDS + << CSL_BFIFO_WFIFOCTL_WNUMDMA_SHIFT); + + /* enable the FIFO now by setting the "WENA" bit */ + hMcbsp->fifoRegs->WFIFOCTL |= + (CSL_BFIFO_WFIFOCTL_WENA_ENABLED + << CSL_BFIFO_WFIFOCTL_WENA_SHIFT); + } + } + else + { + /* FIFO needs to be disabled */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* disable the FIFO now by resetting the "WENA" bit */ + hMcbsp->fifoRegs->RFIFOCTL = + (CSL_BFIFO_RFIFOCTL_RENA_DISABLED + << CSL_BFIFO_RFIFOCTL_RENA_SHIFT); + } + else + { + /* disable the FIFO now by resetting the "WENA" bit */ + hMcbsp->fifoRegs->WFIFOCTL = + (CSL_BFIFO_WFIFOCTL_WENA_DISABLED + << CSL_BFIFO_WFIFOCTL_WENA_SHIFT); + } + } +} + +/** + * \brief This is going to complete the current request and abort + * all other reqest. + * + * \param chanHandle [IN] Channel handle + * + * \return None + * + * \enter chanHandle is a valid non null pointer + * + * \leave Not implemented + */ +void Mcbsp_localCancelAndAbortAllIo(Mcbsp_ChannelObj *chanHandle) +{ + chanHandle->submitCount--; + chanHandle->tempIOBuf->status = MCBSP_STATUS_ABORTED; + + Mcbsp_localCompleteCurrentIo(chanHandle); + + Mcbsp_localAbortReset(chanHandle); +} + +#ifndef MCBSP_LOOPJOB_ENABLE +/** + * \brief This function waits for the FIFO to be emptied(if enabled) and the + * TX empty bit to be set so that the TX section could be disabled when + * there is no data present. + * + * \param arg0 [IN] Handle to the TX channel + * \param arg1 [IN] unused + * + * \return None + * + * \enter arg0 is a valid non null pointer + * + * \leave Not implemented + */ +void Mcbsp_TxFifo(int32_t arg0, int32_t arg1) +{ + Mcbsp_ChannelObj *chanHandle = NULL; + Mcbsp_Object *hInst = NULL; + Mcbsp_Object_Unpadded *instHandle = NULL; + uint32_t timeOut = 0x00; + void* criticalSectionInfo; + + chanHandle = (Mcbsp_ChannelObj *)arg0; + hInst = (Mcbsp_Object *)arg1; + instHandle = (Mcbsp_Object_Unpadded *)&(hInst->obj); + + /* critical section starts */ + criticalSectionInfo = Mcbsp_osalEnterSingleCoreCriticalSection(); + + /* update the timeout value from the instance handle */ + timeOut = instHandle->retryCount; + + /* we have come here means that the Mcbsp has got an callback but it * + * did have any more buffer to load Hence here we will wait for the * + * FIFO to become empty (if FIFO is enabled) else wait for the TX to * + * become empty.then we will disable the TX section */ + if (TRUE == chanHandle->enableHwFifo) + { + while ((0 != (instHandle->hwInfo.fifoRegs->WFIFOSTS & + CSL_BFIFO_WFIFOSTS_WLVL_MASK)) + && (0 != timeOut)) + { + /* reduce the timeout count and check if the FIFO is empty */ + timeOut--; + } + } + + /* reinitialize the retry count */ + timeOut = instHandle->retryCount; + + while ((CSL_MCBSP_SPCR_XEMPTY_MASK == + (instHandle->hwInfo.regs->SPCR & CSL_MCBSP_SPCR_XEMPTY_MASK)) + && (0 != timeOut)) + { + /* reduce the retry count and check if the TX has completed * + * transmitting all the bytes */ + timeOut--; + } + + /* we need to stop the frame sycn generator now.But also need to check * + * if 1.The frame sycn generator is actually started By TX. * + * 2.The RX is not feeding of the sample rate generator */ + if ((TRUE == instHandle->txFsgEnable) && + ((TRUE != instHandle->rxFsgEnable) + || (TRUE == instHandle->stopSmFsRcv))) + { + /* Now we can disable the frame sync generator */ + Mcbsp_localResetCtrl( + (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj), + Mcbsp_SpcrCtrl_FSYNC_DISABLE); + instHandle->fsgEnabled = FALSE; + } + + /* Stop the TX section */ + Mcbsp_localResetCtrl( + (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj), + Mcbsp_SpcrCtrl_TX_DISABLE); + + /* Transmit state machine is stopped */ + instHandle->stopSmFsXmt = TRUE; + + /* clear the error bits in the EDMA(as this is the last buffer) */ + EDMA3_DRV_clearErrorBits( + chanHandle->edmaHandle, + chanHandle->xferChan); + + /* complete the IOP now and call the callback to the stream */ + chanHandle->tempIOBuf = (Mcbsp_IOBuf *) Mcbsp_osalQueueGet(chanHandle->ptrQFloatList); + + /* Decrement the submit count for the IO buffers */ + chanHandle->submitCount--; + + chanHandle->isTempIOBufValid = TRUE; + chanHandle->tempIOBuf->status = chanHandle->currentError; + Mcbsp_localCompleteCurrentIo(chanHandle); + + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); + + +} +#endif /* #ifndef MCBSP_LOOPJOB_ENABLE */ + + +/** + * \brief This function toggles the index of the edma params + * + * \param index [IN] pointer to current index + * + * \return None + * + * \enter index is a valid non null pointer + * + * \leave Not implemented + */ +void Mcbsp_localGetNextIndex(uint32_t *index) +{ + *index = (((*index) + 1u) & 0x01u); +} + +/** + * \brief This function loads the buffers to the actual EDMA paramset. + * + * \param chanHandle [IN] Handle to channel. + * \param ioBuf [IN] pointer to the ioBuf + * + * \return None + * + * \enter Not implemented + * + * \leave Not implemented + */ +void Mcbsp_localLoadPktToEdma(Mcbsp_ChannelObj *chanHandle,Mcbsp_IOBuf *ioBuf) +{ +#ifndef MCBSP_LOOPJOB_ENABLE + Mcbsp_Object_Unpadded *instHandle = NULL; +#endif + int32_t status = MCBSP_STATUS_COMPLETED; + +#ifndef MCBSP_LOOPJOB_ENABLE + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); +#endif + + chanHandle->currentDataSize = (uint16_t)ioBuf->size; + chanHandle->userDataBufferSize = (uint32_t)ioBuf->size; + +#ifdef MCBSP_LOOPJOB_ENABLE + if (Mcbsp_MAXLINKCNT == chanHandle->submitCount) + { +#else + /* The second and the third buffer will go the link paramsets */ + if (Mcbsp_MAXLINKCNT <= chanHandle->submitCount) + { +#endif + /* Though we have to post to param set directly from here, * + * there will be differene between first such buffer and * + * second buffer. As we have control here we are second buffer * + * and first buffer has not yet returned (or corresponding * + * edma callback has not been called.For second buffer, we * + * will be updating the second param set, which is currently * + * hosting loopjob parameter. Hence increment the index to * + * point second paramset and since we are moving out loopjob * + * from both param sets, the loopjobUpdatedinParamset is reset */ + chanHandle->loopjobUpdatedinParamset = FALSE; + Mcbsp_localGetNextIndex( + &chanHandle->nextLinkParamSetToBeUpdated); + } + + /* Now update the data buffer to the link params. The paramset to * + * be updated is decidec by the "nextLinkParamSetToBeUpdated" */ + if (MCBSP_STATUS_COMPLETED != Mcbsp_localUpdtDtPktToLnkPrms(chanHandle,ioBuf)) + { + status = MCBSP_ERR_BADIO; + } + + if ((1u == chanHandle->submitCount) && (MCBSP_STATUS_COMPLETED == status)) + { +#ifdef MCBSP_LOOPJOB_ENABLE + /* if at all this is the very first buffer, then one param set * + * has loop job loaded , self linked and active with the main * + * xfer channel param. other param set is ready loaded (just * + * now)and has link param set as the one having loopjob (this * + * is to ensure that if at all we are not getting any more * + * buffers loopjob be will taken over). Now we have to link * + * the floating / newly loaded param set to xfer channel. */ + if (MCBSP_STATUS_COMPLETED != EDMA3_DRV_linkChannel( + chanHandle->edmaHandle, + chanHandle->xferChan, + chanHandle->pramTbl[chanHandle->nextLinkParamSetToBeUpdated])) + { + status = MCBSP_ERR_BADIO; + } +#else + /* configure the FIFO for the specific channel */ + if (TRUE == chanHandle->enableHwFifo) + { + /* Disable and enable the FIFO so that the events are * + * generated to the Mcbsp for the first time */ + mcbspConfigureFifo(&instHandle->hwInfo,chanHandle,FALSE); + mcbspConfigureFifo(&instHandle->hwInfo,chanHandle,TRUE); + } + + /* enable the EDMA transfer for the channel so that it is * + * ready to transfer the data as soon as the state machine is * + * enabled */ + EDMA3_DRV_enableTransfer( + chanHandle->edmaHandle, + chanHandle->xferChan, + EDMA3_DRV_TRIG_MODE_EVENT); + + /* Start the McBSP hardware */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + instHandle->stopSmFsRcv = FALSE; + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_RX_ENABLE); + } + else + { + instHandle->stopSmFsXmt = FALSE; + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_TX_ENABLE); + } + + if (((MCBSP_MODE_INPUT == chanHandle->mode) && + (TRUE == instHandle->rxFsgEnable)) || + ((MCBSP_MODE_OUTPUT == chanHandle->mode) && + (TRUE == instHandle->txFsgEnable))) + { + /* enable the sample rate generator */ + Mcbsp_localResetCtrl( + instHandle, + Mcbsp_SpcrCtrl_FSYNC_ENABLE); + } +#endif /* MCBSP_LOOPJOB_ENABLE */ + } +} + +/** + * \brief Function to modify the sample rate generator configuration + * + * \param chanHandle [IN] Handle to the channel + * \param arg [IN] pointer to the srg config setup + * + * \return None + */ +int32_t Mcbsp_localModifySampleRate(Mcbsp_ChannelObj *chanHandle,void* arg) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_ClkSetup *clkConfig = NULL; + int32_t status = MCBSP_STATUS_COMPLETED; + + if ((NULL == arg) || (NULL == chanHandle)) + { + return MCBSP_ERR_BADARGS; + } + + instHandle = &(chanHandle->devHandle->obj); + if (NULL == instHandle) + { + return MCBSP_ERR_BADARGS; + } + + clkConfig = (Mcbsp_ClkSetup *)arg; + + /* check if the Frame sync clock is generated by the module */ + if (TRUE == instHandle->srgConfigured) + { + /* Configure the McBSP with user supplied parameters */ + chanHandle->clkSetup = *(clkConfig); + instHandle->srgConfigured = FALSE; + + /* stop the sample rate generator */ + if (TRUE == instHandle->srgEnabled) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_SRG_DISABLE); + + status = Mcbsp_localConfigureSrgr(instHandle,chanHandle); + + if (MCBSP_STATUS_COMPLETED == status) + { + /* enable the sample rate generator */ + Mcbsp_localResetCtrl( + instHandle, + Mcbsp_SpcrCtrl_SRG_ENABLE); + + /* wait for the 2CLKG clock cycles */ + Mcbsp_osalWaitNBitClocks(2u); + } + + /* clear the XSYNCERR (to be done only if TX is used) */ + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + /* Enable the TX section */ + Mcbsp_localResetCtrl( + instHandle, + Mcbsp_SpcrCtrl_TX_ENABLE); + + /* wait for 2 CLKR or CLX cycles */ + Mcbsp_osalWaitNBitClocks(2u); + + /* Disable the TX section to clear any XYNCERR */ + Mcbsp_localResetCtrl( + instHandle, + Mcbsp_SpcrCtrl_TX_DISABLE); + } + } + } + else + { + status = MCBSP_ERR_BADMODE; + + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + if (TRUE != instHandle->rxSrgEnable) + { + /* Since this mode does not use the sample rate generator, so + * there is no point in changing the sample rate. So return + * with success*/ + status = MCBSP_STATUS_COMPLETED; + } + } + else + { + if (TRUE != instHandle->txSrgEnable) + { + /* Since this mode does not use the sample rate generator, so + * there is no point in changing the sample rate. So return + * with success*/ + status = MCBSP_STATUS_COMPLETED; + } + } + } + return (status); +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ diff --git a/packages/ti/drv/mcbsp/src/mcbsp_edma.c b/packages/ti/drv/mcbsp/src/mcbsp_edma.c new file mode 100644 index 000000000..64fc8ad7c --- /dev/null +++ b/packages/ti/drv/mcbsp/src/mcbsp_edma.c @@ -0,0 +1,1952 @@ +/* + * mcbsp_edma.c + * + * This file contains local functions for MCBSP driver which contain implemen- + * tation for EDMA operation specifc calls like starting an EDMA transfer for + * for McBSP peripheral, EDMA completion and/or error callbacks etc. + * + * Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/*============================================================================*/ +/* INCLUDE FILES */ +/*============================================================================*/ + +/* CSL-RLs required for MCBSP LLD */ +#include // Freon only has cslr directory + +/* MCBSP Types includes */ +#include + +/* MCBSP LLD includes */ +#include +#include + +/* MCBSP OSAL layer */ +#include + + + +/*============================================================================*/ +/* IMPORTED VARIABLES */ +/*============================================================================*/ + +extern far Mcbsp_TempBuffer Mcbsp_muteBuf[CSL_MCBSP_PER_CNT]; + +/*============================================================================*/ +/* LOCAL FUNCTION PROTOTYPES */ +/*============================================================================*/ + +int32_t mcbspIsValidIOBuf(Mcbsp_ChannelObj *chanHandle); + +/*============================================================================*/ +/* LOCAL VARIABLES */ +/*============================================================================*/ + +#ifndef MCBSP_LOOPJOB_ENABLE +uint32_t Mcbsp_edmaChanNum; +uint32_t Mcbsp_dummyParamSetAddr; + +/* Edma dummy function*/ +void doNothing(uint32_t tcc, EDMA3_RM_TccStatus edmaStatus, void* appData) +{ +/* DO NOTHING (This is a callback for the dummy transfer) */ +} +#endif +/* ========================================================================== */ +/* FUNCTION DEFINITIONS */ +/* ========================================================================== */ + +/** + * \brief Function to intialize and set up the edma for transfer. + * + * This function does the following + * 1) Requests the EDMA channel from the edma driver. + * 2) Requests the link channels for linking (exclusive for tx & rx) + * 3) set up the param set of main xfer channel (for loopjob transfers) + * 4) set up the param sets of all link channel (for loopjob transfers) + * 5) link the last link channel to itself (this channel will be linked + * to main xfer channel later and to supply the loopjob xfer + * information infinely this is done so; + * other link channels are setup here just for completion sake + * + * \param chanHandle [IN] Handle to the channel for which the edma is setup + * + * \return status MCBSP_STATUS_COMPLETED if is sucess + * error id in case of failure + * + */ +int32_t Mcbsp_localSetupEdmaDuringOpen(Mcbsp_ChannelObj *chanHandle) +{ + uint32_t reqTcc = EDMA3_DRV_TCC_ANY; + Bool falsewhile = TRUE; + uint32_t linkCnt = 0; + uint32_t edmaChanNum = 0; + uint32_t count = 0; + int32_t status = MCBSP_STATUS_COMPLETED; +#ifndef MCBSP_LOOPJOB_ENABLE + EDMA3_RM_EventQueue queueNum = 0; +#endif + + + do + { + falsewhile = FALSE; + if (NULL == chanHandle) + { + return MCBSP_ERR_BADARGS; + } + + /* request the transfer channel from the EDMA driver */ + status = EDMA3_DRV_requestChannel( + chanHandle->edmaHandle, + &chanHandle->xferChan, + &chanHandle->tcc, + chanHandle->edmaEventQue, + (chanHandle->edmaCallback), + chanHandle); + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADARGS; + break; + } + + /* if there are any errors set in the EDMA clear them here */ + EDMA3_DRV_clearErrorBits( + chanHandle->edmaHandle, + chanHandle->xferChan); + + /* Acquire the PaRAM entries used for EDMA transfers linking */ + for (count = 0; count < Mcbsp_MAXLINKCNT; count++) + { + /* For requesting for a PaRam set */ + edmaChanNum = EDMA3_DRV_LINK_CHANNEL; + reqTcc = EDMA3_DRV_TCC_ANY; + + status = EDMA3_DRV_requestChannel( + chanHandle->edmaHandle, + &edmaChanNum, + &reqTcc, + chanHandle->edmaEventQue, + (chanHandle->edmaCallback), + NULL); + + if (MCBSP_STATUS_COMPLETED == status) + { + chanHandle->pramTbl[count] = edmaChanNum; + + status = EDMA3_DRV_getPaRAMPhyAddr( + chanHandle->edmaHandle, + chanHandle->pramTbl[count], + &(chanHandle->pramTblAddr[count])); + } + + if (MCBSP_STATUS_COMPLETED != status ) + { + /* free the Synchonized EDMA channel */ + EDMA3_DRV_freeChannel( + chanHandle->edmaHandle, + chanHandle->xferChan); + + /* free the already allocated PaRAM entries */ + for (linkCnt = 0; linkCnt < count; linkCnt++) + { + EDMA3_DRV_freeChannel( + chanHandle->edmaHandle, + chanHandle->pramTbl[linkCnt]); + } + + status = MCBSP_ERR_BADARGS; + break; + } + } + +#ifndef MCBSP_LOOPJOB_ENABLE + /* Configure for dummy PaRAM set*/ + Mcbsp_edmaChanNum = EDMA3_DRV_LINK_CHANNEL; + reqTcc = EDMA3_DRV_TCC_ANY; + + status = EDMA3_DRV_requestChannel( + chanHandle->edmaHandle, + &Mcbsp_edmaChanNum, + &reqTcc, + queueNum, + &doNothing, + NULL); + + if (MCBSP_STATUS_COMPLETED == status) + { + status = EDMA3_DRV_getPaRAMPhyAddr( + chanHandle->edmaHandle, + Mcbsp_edmaChanNum, + &Mcbsp_dummyParamSetAddr); + } +#endif + + /* Configure EDMA channels */ + if (MCBSP_STATUS_COMPLETED == status) + { + status = Mcbsp_localEdmaChanPaRAMsetup(chanHandle); + } + }while(falsewhile); + return status; +} +#ifdef MCBSP_LOOPJOB_ENABLE +/** + * \brief This calls the registered application callback for the current + * receive request and processes the next request in queue. + * This is a mcbsp edma callback function called in edma context + * + * \param tcc [IN] tcc number of EDMA + * \param edmaStatus [IN] status of EDMA transaction + * \param data [IN] paramaters sent to EDMA ISR (chan handler) + * + * \return Nothing + * + * \entry tcc should be a valid value + * status should be a valid value + * data should be a non NULL and valid pointer + * + * \leave Not implemented + */ +void Mcbsp_localEdmaCallback(uint32_t tcc, EDMA3_RM_TccStatus edmaStatus, void* data) +{ + Mcbsp_ChannelObj *chanHandle = NULL; + EDMA3_DRV_PaRAMRegs pramTbl = {0}; + int32_t status = MCBSP_STATUS_COMPLETED; + Mcbsp_IOBuf *ioBuf = NULL; + void* criticalSectionInfo; + + chanHandle = (Mcbsp_ChannelObj *)data; + /* to remove the compiler warning */ + tcc= tcc; + + /* critical section starts */ + criticalSectionInfo = Mcbsp_osalEnterMultipleCoreCriticalSection(); + + if (TRUE != Mcbsp_osalQueueEmpty(chanHandle->ptrQFloatList)) + { + /* should always have a buffer present because this callback is * + * due to that buffer */ + + /* Get the buffer from the top of the queue (atommic operation) */ + chanHandle->tempIOBuf = Mcbsp_osalQueueGet(chanHandle->ptrQFloatList); + + /* get the param table information of transfer channel */ + EDMA3_DRV_getPaRAM(chanHandle->edmaHandle,chanHandle->xferChan,&pramTbl); + + /* Handle the I/O buffers appropriately in case of an breakpoint * + * in case of an breakpoint.either of the buffers (2 link param Pkts) * + * could have caused a callback as both of them as linkedto each other* + * Hence we will handle that condition here */ + if (chanHandle->mode == MCBSP_MODE_INPUT) + { + /* Check if destination address falls into the range of 1st req * + * in the floating queue. */ + if (((pramTbl.destAddr >= (uint32_t)chanHandle->tempIOBuf->addr) + && (pramTbl.destAddr < (uint32_t)chanHandle->tempIOBuf->addr + + chanHandle->tempIOBuf->size)) && + (FALSE == Mcbsp_osalQueueEmpty(chanHandle->ptrQFloatList))) + { + /* Since we have already dequeue the 1st request, dequeue * + * 2nd io request from floating queue */ + ioBuf = (Mcbsp_IOBuf *)Mcbsp_osalQueueGet(chanHandle->ptrQFloatList); + + /* Queue the tempIOBuf (i.e. 1st io request) as this pkt * + * should be first in a queue */ + Mcbsp_osalQueuePut( + chanHandle->ptrQFloatList, + (void*)chanHandle->tempIOBuf); + + /* Queue the ioBuf i.e. 2nd request in floating queue */ + Mcbsp_osalQueuePut(chanHandle->ptrQFloatList,(void*)ioBuf); + } + } + else + { + /* Check if destination address falls into the range of1st request* + * in the floating queue. */ + if (((pramTbl.srcAddr >= (uint32_t)chanHandle->tempIOBuf->addr)&& + (pramTbl.srcAddr < (uint32_t)chanHandle->tempIOBuf->addr + chanHandle->tempIOBuf->size)) && + (FALSE == Mcbsp_osalQueueEmpty(chanHandle->ptrQFloatList))) + { + /* Since we have already dequeue the 1st request, dequeue * + * io request from floating queue */ + ioBuf = (Mcbsp_IOBuf *)Mcbsp_osalQueueGet(chanHandle->ptrQFloatList); + + /* Queue the tempIOBuf (i.e. 1st io request) as this * + * buffer should be first in a queue */ + Mcbsp_osalQueuePut( + chanHandle->ptrQFloatList, + (void*)chanHandle->tempIOBuf); + + /* Queue the ioBuf i.e. 2nd request in floating queue */ + Mcbsp_osalQueuePut(chanHandle->ptrQFloatList,(void*)ioBuf); + status = MCBSP_ERR_NOIOBUFFERS; + } + } + + if (MCBSP_STATUS_COMPLETED == status) + { + if (EDMA3_RM_XFER_COMPLETE != edmaStatus) + { + /* update the status of the IOP as error */ + chanHandle->tempIOBuf->status = MCBSP_ERR_ABORT; + + /* There is a data transfer error in EDMA transfer. clear the * + * Error bits and return */ + EDMA3_DRV_clearErrorBits( + chanHandle->edmaHandle, + chanHandle->xferChan); + } + else + { + chanHandle->tempIOBuf->status = MCBSP_STATUS_COMPLETED; + } + + chanHandle->submitCount--; + } +#ifdef MCBSP_LOOP_PING_PONG + if(MCBSP_STATUS_COMPLETED == status) + { + /* Put back the buffer in the queue */ + chanHandle->submitCount++; + /* Queue the tempIOBuf */ + Mcbsp_osalQueuePut( + chanHandle->ptrQFloatList, + (void*)chanHandle->tempIOBuf); + } +#endif + + if (MCBSP_STATUS_COMPLETED == status) + { +#ifndef MCBSP_LOOP_PING_PONG + /* if the channel is not in a pause mode */ + if (FALSE == chanHandle->paused) + { + /* Now that we have done with the last data buffer - we check * + * if next buffer is available for transmission. Even if we * + * are not having a valid buffer - previous programming of * + * linkchannels (designed in such a way) to send out null * + * buffer Also note that Mcbsp_localIsValidIOBuf function * + * will set the chanHandle->dataIOBuf with next (current now) * + * data buffer from queue */ + if ((Mcbsp_STATUS_VALID == (mcbspIsValidIOBuf(chanHandle)))) + { + /* This is a valid data request. Call function to process * + * it. If DMA cannot be programmed properly with request * + * contents, abort all queued up requests and put state * + * M/C into reset. */ + status = Mcbsp_localEdmaProcessPkt( + chanHandle, + chanHandle->dataIOBuf); + + if (MCBSP_STATUS_COMPLETED != status) + { + Mcbsp_localCancelAndAbortAllIo(chanHandle); + } + } + else + { + + Mcbsp_localGetNextIndex( + &chanHandle->nextLinkParamSetToBeUpdated); + + /* The following function will assign loopjob buffer to * + * free param set Also the control will come here two times* + * for last buffer and last but one buffer (obviously for * + * more than one buffer xfer) For last but buffer callback * + * itself we will come to know that there is no more buffer * + * pending and hence we load loopjob info into next param * + * set and for the last buffer callback will not do it * + * again (for only one buffer scenario the following flag * + * will take care not to update the loopjob second time) */ + if (FALSE == chanHandle->loopjobUpdatedinParamset) + { + chanHandle->loopjobUpdatedinParamset = TRUE; + + Mcbsp_localUpdtDtPktToLnkPrms(chanHandle,NULL); + } + } + } + else +#else + if (TRUE == chanHandle->paused) +#endif + { + /* Control will come over here when either of receive or * + * transmit state machine stop command is issued for receive * + * or transmit channel. If the nextFlag is already set * + * indicates that its time to reset the state machines and * + * disable the edma transfer */ + if (TRUE == chanHandle->nextFlag) + { + chanHandle->nextFlag = FALSE; + } + else + { + /* For the first time when the stop port command is issued* + * we will have one more buffer linked with the transfer * + * channel. So we will not stop at this time. We link the * + * buffer with NULL loopjob buffer and set a nextFlag to * + * TRUE. We will wait for another callback(indicating the * + * io request is complete) to disable EDMA transfer and * + * reset state machines */ + chanHandle->nextFlag = TRUE; + + Mcbsp_localGetNextIndex(&chanHandle->nextLinkParamSetToBeUpdated); + + Mcbsp_localUpdtDtPktToLnkPrms(chanHandle, NULL); + } + } + if (MCBSP_STATUS_COMPLETED == status) + { + chanHandle->isTempIOBufValid = TRUE; + Mcbsp_localCompleteCurrentIo(chanHandle); + } + } + else if (MCBSP_ERR_NOIOBUFFERS == status) + { + /* Handle Underflow condition */ + chanHandle->isTempIOBufValid = TRUE; + chanHandle->tempIOBuf = NULL; + Mcbsp_localCompleteCurrentIo(chanHandle); + } + } + /* critical section ends */ + Mcbsp_osalExitMultipleCoreCriticalSection(criticalSectionInfo); + +} + +/*! + * \brief This function updates the link param set accordingly with data or + * loopjobbuffer. This uses properly maintained index to identify to + * what param set the info has to be updated. + * + * \param chanHandle [IN] Handle to the mcbsp channel + * \param ioBuf [IN] Pointer to I/O buffer + * + * \return MCBSP_STATUS_COMPLETED in case of sucess + * else Error code in case of failure + * + * \entry chanHandle should be non NULL and valid pointer + * ioBuf should be non NULL and valid pointer + * + * \leave Not implemented + */ +int32_t Mcbsp_localUpdtDtPktToLnkPrms(Mcbsp_ChannelObj *chanHandle, + Mcbsp_IOBuf *const ioBuf) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + EDMA3_DRV_PaRAMRegs pramPtr = {0}; + Bool falsewhile = TRUE; + int32_t status = MCBSP_STATUS_COMPLETED; + EDMA3_DRV_SyncType syncType; + + do + { + falsewhile = FALSE; + if ((NULL == chanHandle) || (NULL == chanHandle->devHandle)) + { + return MCBSP_ERR_BADARGS; + } + + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); + if (NULL == instHandle) + { + return MCBSP_ERR_BADARGS; + } + + /* if at all this is the first buffer we will update the main params * + * else we will update the link params */ + status = EDMA3_DRV_getPaRAM( + chanHandle->edmaHandle, + chanHandle->pramTbl[chanHandle->nextLinkParamSetToBeUpdated], + &pramPtr); + if (MCBSP_STATUS_COMPLETED != status ) + { + status = MCBSP_ERR_BADARGS; + break; + } + + /* Following the explanation behind the EDMA configuration * + * 1) We will have n arrays of data (now it is data buffer each of length * + * databuffersize bytes) * + * 2) for each sync event we have to fetch the data from each array and * + * write to each slot * + * 3) and the no. bytes transferred in this case from each array will be * + * roundedwordwidth/4 * + * 4) as the loopjob buffer is contigous, we configure the counts as * + * follows * + * a) consider there are arrays of length roundedwordwidth/4 (aCnt) * + * b) these arrays are located apart databuffersize size (bindex) * + * c) there are 'no.of.slots' no. of such arrays (bCnt) * + * d) (a) and (b) constitute one frame of EDMA transfer and it happens * + * for one sync event in AB sync mode. * + * e) such frames have to be sent till we have buffer - ie * + * databuffersize / (roundedwordwidth/8 ) and this constitutes cCnt* + * f) address of buffer (rather offset from start of previous frame) * + * is roundedwordwidth/8 and this forms cIndex * + * * + * Please take some time to visualise the setup mentioned above to check * + * with EDMA configuration * + * Also we change only specific parameters because others will not have * + * change from what we programed intially */ + + /* control will reach this function is two contexts * + * 1) From submitreq function for first time buffers * + * 2) From EDMA callback for further handling of buffers in Queue * + * - we are from EDMA callback becuase we have completed some user * + * data buffer just now */ + + if (NULL != ioBuf) + { + /* 1) when control comes to this function from submitreq control * + * will surely comeinto the block * + * 2) When control comes to this function from EDMA callback, * + * control will some only if there is fuirther more buffers to * + * handle */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + pramPtr.destAddr = (uint32_t)ioBuf->addr; + Mcbsp_localGetIndicesSyncType( + chanHandle, + &(pramPtr.destBIdx), + &(pramPtr.destCIdx), + &(pramPtr.aCnt), + &(pramPtr.bCnt), + &(pramPtr.cCnt), + &syncType, + FALSE); + } + else + { + if (TRUE == chanHandle->bMuteON) + { + /* Mute is set hence we need to switch to the mute buffer */ + pramPtr.srcAddr = + (uint32_t)&Mcbsp_muteBuf[instHandle->instNum].scratchBuffer; + Mcbsp_localGetIndicesSyncType( + chanHandle, + &(pramPtr.srcBIdx), + &(pramPtr.srcCIdx), + &(pramPtr.aCnt), + &(pramPtr.bCnt), + &(pramPtr.cCnt), + &syncType, + TRUE); + } + else + { + pramPtr.srcAddr = (uint32_t)ioBuf->addr; + Mcbsp_localGetIndicesSyncType( + chanHandle, + &(pramPtr.srcBIdx), + &(pramPtr.srcCIdx), + &(pramPtr.aCnt), + &(pramPtr.bCnt), + &(pramPtr.cCnt), + &syncType, + FALSE); + } + } + + /* Here we are enabling the interrupt for this param set info * + * we do it here in this way because using int enable API after * + * calling EDMA3_DRV_setPaRAM, may fail our intention. This is * + * because immediately after the set param the paramset might be * + * copied to linked param and will make the consecutive int enable* + * (set opt field) api useless for our purpose */ + pramPtr.opt |= (0x01u<<20u); + + /* we are loading data request in the param set. As per our design* + * when we load the data, we should link this param set with next* + * one most probably * + * a) That may have loopjob loaded * + * b) it may be the currently loaded set, which will be updated * + * in next edma callback. * + * hence in both cases to be run next to this data request */ + pramPtr.linkAddr = + (uint16_t)(chanHandle->pramTblAddr[ \ + ((chanHandle->nextLinkParamSetToBeUpdated+1) & 0x01)] & 0x0000FFFF); + } + else + { + /* we have reached here becuase we dont have any more buffer to * + * submit for Xfer assign loop job to params- no change in linking* + * IMP: The following assignment will be skipped if already both * + * params are having loopjob buffer */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + pramPtr.destAddr = (uint32_t)chanHandle->loopJobBuffer; + Mcbsp_localGetIndicesSyncType( + chanHandle, + &(pramPtr.destBIdx), + &(pramPtr.destCIdx), + &(pramPtr.aCnt), + &(pramPtr.bCnt), + &(pramPtr.cCnt), + &syncType, + TRUE); + } + else + { + pramPtr.srcAddr = (uint32_t)chanHandle->loopJobBuffer; + Mcbsp_localGetIndicesSyncType( + chanHandle, + &(pramPtr.srcBIdx), + &(pramPtr.srcCIdx), + &(pramPtr.aCnt), + &(pramPtr.bCnt), + &(pramPtr.cCnt), + &syncType, + TRUE); + } + + /* we are loading loopjob into this param. That means we have * + * reached the end of buffers inpending and floating queues. So * + * this loopjob had to be linked to itself. Also we need to point* + * the index to other param set in order to load data request * + * directly from submit call */ + pramPtr.linkAddr = + (uint16_t)(chanHandle->pramTblAddr[ \ + chanHandle->nextLinkParamSetToBeUpdated] & 0x0000FFFF); + + pramPtr.opt &= (~(0x01<<20)); + } + + /* Update the changed param set info into the appropriate paramset */ + status = EDMA3_DRV_setPaRAM( + chanHandle->edmaHandle, + chanHandle->pramTbl[chanHandle->nextLinkParamSetToBeUpdated], + &pramPtr); + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADARGS; + break; + } + + if (NULL == ioBuf) + { + /* we are loading loopjob into this param. we need to point the * + * index to other param set in order to load data request directly* + * from submit call */ + Mcbsp_localGetNextIndex(&chanHandle->nextLinkParamSetToBeUpdated); + } + }while(falsewhile); + + return status; +} + +/** + * \brief setup the EDMA channel for the specific channel requested. + * + * This function configures the McBSP synchonized EDMA channel PaRAM + * entries it also configures the various other parameters like + * source and destination address / modes + * + * \param chanHandle [IN] Channel handle + * + * \return MCBSP_STATUS_COMPLETED if setup successful + * Appropriate MCBSP driver error code if configuration has any error + */ +int32_t Mcbsp_localEdmaChanPaRAMsetup(Mcbsp_ChannelObj *chanHandle) +{ + uint32_t linkCnt = 0; + Mcbsp_Object_Unpadded *instHandle = NULL; + EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0}; + int32_t status = MCBSP_STATUS_COMPLETED; + EDMA3_DRV_SyncType tempSyncType; + + if ((NULL == chanHandle) || (NULL == chanHandle->devHandle)) + { + return MCBSP_ERR_BADARGS; + } + + instHandle = &(chanHandle->devHandle->obj); + if (NULL == instHandle) + { + return MCBSP_ERR_BADARGS; + } + + /* Configure the McBSP synchonized EDMA channel PaRAM entries * + * Configure source and destination address / modes * + * first - main xfer channel */ + + /* following is the explanation behind the EDMA configuration * + * + * 1) We will have n arrays of data (now it is loopjob buffer each of * + * length x bytes) * + * 2) for each sync event we have to fetch the data from each array * + * and write to each serilaiser * + * 3) and the no. bytes transferred in this case from each array will * + * be roundedwordwidth/4 * + * 4) as the loopjob buffer is continous, we configure the counts as * + * follows * + * a) consider there are arrays of length roundedwordwidth/8(aCnt) * + * b) these arrays are located apart lengthofloopjob size (bindex) * + * c) there are 'no.of.slots' no. of such arrays (bCnt) * + * d) (a) and (b) constitute one frame of EDMA transfer and it * + * happens for one sync event in AB sync mode * + * e) such frames have to be sent till we have buffer - ie * + * lengthofloopjob / (roundedwordwidth/8 ) and this * + * constitutes cCnt * + * f) address of buffer (rather offset from start of previous * + * frame) is roundedwordwidth/8 and this forms cIndex * + * Please take some time to visualise the setup mentioned above to * + * check with EDMA configuration The same kind of setup will be used * + * for data transfers also and the change will be buffer pointer * + * and length of data buffer. */ + + /* Get the PaRAM set for default parameters */ + EDMA3_DRV_getPaRAM(chanHandle->edmaHandle,chanHandle->xferChan,¶mSet); + + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* Configuring Source and Dest addresses */ + if (TRUE == chanHandle->enableHwFifo) + { + paramSet.srcAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + paramSet.srcAddr = (uint32_t)&(instHandle->hwInfo.regs->DRR); + } +#ifdef _BIG_ENDIAN + paramSet.srcAddr += (4 - chanHandle->roundedWordWidth); +#endif + paramSet.destAddr = (unsigned int)(chanHandle->loopJobBuffer); + + /* Configuring Src and Dest B&C Indexes */ + paramSet.srcBIdx = 0; + paramSet.srcCIdx = 0; + + if (MCBSP_STATUS_COMPLETED != Mcbsp_localGetIndicesSyncType( + chanHandle, + ¶mSet.destBIdx, + ¶mSet.destCIdx, + ¶mSet.aCnt, + ¶mSet.bCnt, + ¶mSet.cCnt, + &tempSyncType, + TRUE)) + { + status = MCBSP_ERR_BADARGS; + } + } + else + { + /* Configuring Source and Dest addresses */ + paramSet.srcAddr = (unsigned int)(chanHandle->loopJobBuffer); + + if (TRUE == chanHandle->enableHwFifo) + { + paramSet.destAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + paramSet.destAddr = (uint32_t)&(instHandle->hwInfo.regs->DXR); + } +#ifdef _BIG_ENDIAN + paramSet.destAddr += (4 - chanHandle->roundedWordWidth); +#endif + /* Configuring Src and Dest B&C Indexes */ + paramSet.destBIdx = 0; + paramSet.destCIdx = 0; + + if (MCBSP_STATUS_COMPLETED != Mcbsp_localGetIndicesSyncType( + chanHandle, + ¶mSet.srcBIdx, + ¶mSet.srcCIdx, + ¶mSet.aCnt, + ¶mSet.bCnt, + ¶mSet.cCnt, + &tempSyncType, + TRUE)) + { + status = MCBSP_ERR_BADARGS; + } + } + + + /* Configuring bCntReload */ + paramSet.bCntReload = paramSet.bCnt; + + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + + /* FIFO width is 8 bit */ + paramSet.opt &= 0xFFFFF8FFu; + + /* Set EDMA3_DRV_OPT_FIELD_TCINTEN to FALSE */ + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_ITCINTEN_MASK)); + + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_TCINTEN_MASK)); + paramSet.opt |= (CSL_TPCC_PARAM_OPT_TCINTEN_DISABLE + << CSL_TPCC_PARAM_OPT_TCINTEN_SHIFT); + + /* Program the TCC */ + paramSet.opt |= ((chanHandle->tcc << CSL_TPCC_PARAM_OPT_TCC_SHIFT) + & CSL_TPCC_PARAM_OPT_TCC_MASK); + + /* EDMA3_DRV_SYNC_AB */ + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_SYNCDIM_MASK)); + paramSet.opt |= (tempSyncType << CSL_TPCC_PARAM_OPT_SYNCDIM_SHIFT); + + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_TCCMOD_MASK)); + paramSet.opt |= (1 << CSL_TPCC_PARAM_OPT_TCCMOD_SHIFT); + + /* Now, write the PaRAM Set. */ + status = EDMA3_DRV_setPaRAM( + chanHandle->edmaHandle, + chanHandle->xferChan, + ¶mSet); + + if (MCBSP_STATUS_COMPLETED == status) + { + /* Configure the link PaRAMs with the appropriate parameters Though * + * we configure all the link paramsets, we will be using only one of * + * them to link with main xfer channel */ + for (linkCnt = 0; linkCnt < Mcbsp_MAXLINKCNT; linkCnt++) + { + /* Get the PaRAM set for default parameters */ + EDMA3_DRV_getPaRAM (chanHandle->edmaHandle, + chanHandle->pramTbl[linkCnt], + ¶mSet); + + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* Configuring Source and Dest addresses */ + if (TRUE == chanHandle->enableHwFifo) + { + paramSet.srcAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + paramSet.srcAddr = (uint32_t)&(instHandle->hwInfo.regs->DRR); + } +#ifdef _BIG_ENDIAN + paramSet.srcAddr += (4 - chanHandle->roundedWordWidth); +#endif + paramSet.destAddr = (uint32_t)(chanHandle->loopJobBuffer); + + /* Configuring Src and Dest B&C Indexes */ + paramSet.srcBIdx = 0; + paramSet.srcCIdx = 0; + + if (MCBSP_STATUS_COMPLETED != Mcbsp_localGetIndicesSyncType( + chanHandle, + ¶mSet.destBIdx, + ¶mSet.destCIdx, + ¶mSet.aCnt, + ¶mSet.bCnt, + ¶mSet.cCnt, + &tempSyncType, + TRUE)) + { + status = MCBSP_ERR_BADARGS; + } + } + else + { + /* Configuring Source and Dest addresses */ + paramSet.srcAddr = (uint32_t)(chanHandle->loopJobBuffer); + + if (TRUE == chanHandle->enableHwFifo) + { + paramSet.destAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + paramSet.destAddr = (uint32_t)&(instHandle->hwInfo.regs->DXR); + } + +#ifdef _BIG_ENDIAN + paramSet.destAddr += (4 - chanHandle->roundedWordWidth); +#endif + + paramSet.destBIdx = 0; + paramSet.destCIdx = 0; + + if (MCBSP_STATUS_COMPLETED != Mcbsp_localGetIndicesSyncType( + chanHandle, + ¶mSet.srcBIdx, + ¶mSet.srcCIdx, + ¶mSet.aCnt, + ¶mSet.bCnt, + ¶mSet.cCnt, + &tempSyncType, + TRUE)) + { + status = MCBSP_ERR_BADARGS; + } + } + + /* Configuring bCntReload */ + paramSet.bCntReload = paramSet.bCnt; + + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + + /* FIFO width is 8 bit */ + paramSet.opt &= 0xFFFFF8FFu; + + /* EDMA3_DRV_SYNC_AB */ + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_SYNCDIM_MASK)); + paramSet.opt |= (tempSyncType << CSL_TPCC_PARAM_OPT_SYNCDIM_SHIFT); + + /* Set EDMA3_DRV_OPT_FIELD_TCINTEN to FALSE */ + paramSet.opt |= (CSL_TPCC_PARAM_OPT_TCINTEN_DISABLE + << CSL_TPCC_PARAM_OPT_TCINTEN_SHIFT); + + /* Program the TCC */ + paramSet.opt |= ((chanHandle->tcc << CSL_TPCC_PARAM_OPT_TCC_SHIFT) + & CSL_TPCC_PARAM_OPT_TCC_MASK); + + /* early completion interrupt */ + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_TCCMOD_MASK)); + paramSet.opt |= (1 << CSL_TPCC_PARAM_OPT_TCCMOD_SHIFT); + + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_TCINTEN_MASK)); + + if (MCBSP_STATUS_COMPLETED == status) + { + /* Now, write the PaRAM Set. */ + status = EDMA3_DRV_setPaRAM(chanHandle->edmaHandle, + chanHandle->pramTbl[linkCnt], + ¶mSet); + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADARGS; + break; + } + } + + if (Mcbsp_MAXLINKCNT - 1 > linkCnt ) + { + /* link with next paramset both param sets are linked to each* + * other to enable continous xfer - either user audio data or * + * loopjob buffer MAXLINKCNT must be 2 */ + status = EDMA3_DRV_linkChannel( + chanHandle->edmaHandle, + chanHandle->xferChan, + chanHandle->pramTbl[linkCnt]); + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADARGS; + break; + } + + status = EDMA3_DRV_linkChannel( + chanHandle->edmaHandle, + chanHandle->pramTbl[linkCnt] , + chanHandle->pramTbl[linkCnt]); + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADARGS; + break; + } + + status = EDMA3_DRV_linkChannel( + chanHandle->edmaHandle, + chanHandle->pramTbl[linkCnt+1] , + chanHandle->pramTbl[linkCnt+1]); + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADARGS; + break; + } + + chanHandle->nextLinkParamSetToBeUpdated = 0; + + chanHandle->loopjobUpdatedinParamset = TRUE; + } + }/*for loop for linkcount*/ + } + return (status); +} + +#else +/** + * \brief This calls the registered application callback for the current + * receive request and processes the next request in queue. + * This is a mcbsp edma callback function called in edma context + * + * \param tcc [IN] tcc number of EDMA + * \param edmaStatus [IN] status of EDMA transaction + * \param data [IN] paramaters sent to EDMA ISR (chan handler) + * + * \return Nothing + * + * \entry tcc should be a valid value + * status should be a valid value + * data should be a non NULL and valid pointer + * + * \leave Not implemented + */ +void Mcbsp_localEdmaCallback(uint32_t tcc, EDMA3_RM_TccStatus edmaStatus, void* data) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_ChannelObj *chanHandle = NULL; + int32_t status = MCBSP_STATUS_COMPLETED; + Bool falseWhile = TRUE; + void* criticalSectionInfo; + + /* critical section starts */ + criticalSectionInfo = Mcbsp_osalEnterSingleCoreCriticalSection(); + + do + { + falseWhile = FALSE; + + chanHandle = (Mcbsp_ChannelObj *)data; + + if (1u == chanHandle->submitCount) + { + /* This is the last buffer available with the driver.Hence we will* + * stop the EDMA and then proceed to process the buffer */ + EDMA3_DRV_disableTransfer( + chanHandle->edmaHandle, + chanHandle->xferChan, + EDMA3_DRV_TRIG_MODE_EVENT); + + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); + + /* close the IOP now */ + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + /* update the status of the IOP */ + if (EDMA3_RM_XFER_COMPLETE != edmaStatus) + { + /* update the status of the IOP as error */ + chanHandle->currentError = MCBSP_ERR_ABORT; + } + else + { + chanHandle->currentError = MCBSP_STATUS_COMPLETED; + } + + Mcbsp_TxFifo((int32_t)&instHandle->xmtObj, (int32_t)instHandle); + + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); + + break; + } + + /* Stop the McBSP hardware. * + * 1. check if the RX has enabled the FSG and also it is running * + * 2. Also check that the TX state machine is not running off FSG */ + if (TRUE == instHandle->rxFsgEnable) + { + if ((TRUE != instHandle->txFsgEnable) || + (TRUE == instHandle->stopSmFsXmt)) + { + Mcbsp_localResetCtrl( + (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj), + Mcbsp_SpcrCtrl_FSYNC_DISABLE); + + instHandle->fsgEnabled = FALSE; + } + } + + Mcbsp_localResetCtrl( + (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj), + Mcbsp_SpcrCtrl_RX_DISABLE); + + /* receive state machine is stopped */ + instHandle->stopSmFsRcv = TRUE; + + /* clear the error bits that have been set */ + EDMA3_DRV_clearErrorBits( + chanHandle->edmaHandle, + chanHandle->xferChan); + } + else + { + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); + } + + /* To remove the compiler warning */ + tcc = tcc; + + if (EDMA3_RM_XFER_COMPLETE != edmaStatus) + { + /* clear the error bits that have been set */ + EDMA3_DRV_clearErrorBits( + chanHandle->edmaHandle, + chanHandle->xferChan); + + /* update the status of the IOP as error */ + chanHandle->currentError = MCBSP_ERR_ABORT; + break; + } + else + { + chanHandle->currentError = MCBSP_STATUS_COMPLETED; + + /* reduce the submit count as the buffer callback is completed */ + chanHandle->submitCount--; + } + + + if (TRUE == Mcbsp_osalQueueEmpty(chanHandle->ptrQFloatList)) + { + /* This cannot happen, if it happens then it is a sprurios one */ + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); + break; + } + + /* Get the buffer from the top of the queue (atomic operation) */ + chanHandle->tempIOBuf = (Mcbsp_IOBuf *) Mcbsp_osalQueueGet(chanHandle->ptrQFloatList); + + + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); + + /* check if the STOP command is issued for the channel. if the stop * + * command is issued we will not load the next buffer so that the * + * state machine is stopped */ + if (((MCBSP_MODE_INPUT == chanHandle->mode) && (FALSE == instHandle->stopSmFsRcv)) || + ((MCBSP_MODE_OUTPUT == chanHandle->mode) && (FALSE == instHandle->stopSmFsXmt))) + { + /* now check if any other buffer is available and load that */ + if ((Mcbsp_STATUS_VALID == (mcbspIsValidIOBuf(chanHandle)))) + { + /* Valid buffer is found,load the buffer in to link params*/ + status = Mcbsp_localEdmaProcessPkt( + chanHandle, + chanHandle->dataIOBuf); + + if (MCBSP_STATUS_COMPLETED != status) + { + Mcbsp_localCancelAndAbortAllIo(chanHandle); + } + } + } + + /* complete the IO pkt processing by calling the callback function */ + chanHandle->isTempIOBufValid = TRUE; + Mcbsp_localCompleteCurrentIo(chanHandle); + + /* critical section ends */ + Mcbsp_osalExitSingleCoreCriticalSection(criticalSectionInfo); + }while (falseWhile); + +} + +/** + * \brief This function updates the link param set accordingly with data or + * loopjobbuffer. This uses properly maintained index to identify to + * what param set the info has to be updated. + * + * \param chanHandle [IN] Handle to the mcbsp channel + * \param ioBuf [IN] Pointer to I/O buffer + * + * \return MCBSP_STATUS_COMPLETED in case of sucess + * else Error code in case of failure + * + * \entry chanHandle should be non NULL and valid pointer + * ioBuf should be non NULL and valid pointer + * + * \leave Not implemented + */ +int32_t Mcbsp_localUpdtDtPktToLnkPrms(Mcbsp_ChannelObj *chanHandle, + Mcbsp_IOBuf *const ioBuf) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + EDMA3_DRV_PaRAMRegs pramPtr = {0}; + Bool falsewhile = TRUE; + int32_t status = MCBSP_STATUS_COMPLETED; + EDMA3_DRV_SyncType syncType; + EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0}; + + do + { + falsewhile = FALSE; + if ((NULL == chanHandle) || (NULL == chanHandle->devHandle)) + { + return MCBSP_ERR_BADARGS; + } + + instHandle = (Mcbsp_Object_Unpadded *)&(chanHandle->devHandle->obj); + if (NULL == instHandle) + { + return MCBSP_ERR_BADARGS; + } + + /* if at all this is the first buffer we will update the main params * + * else we will update the link params */ + if (1u == chanHandle->submitCount) + { + status = EDMA3_DRV_getPaRAM( + chanHandle->edmaHandle, + chanHandle->xferChan, + &pramPtr); + } + else + { + status = EDMA3_DRV_getPaRAM( + chanHandle->edmaHandle, + chanHandle->pramTbl[chanHandle->nextLinkParamSetToBeUpdated], + &pramPtr); + } + + if (MCBSP_STATUS_COMPLETED != status ) + { + status = MCBSP_ERR_BADARGS; + break; + } + + if (NULL != ioBuf) + { + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + if (TRUE == chanHandle->enableHwFifo) + { + pramPtr.srcAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + pramPtr.srcAddr = (uint32_t)&(instHandle->hwInfo.regs->DRR); + } +#ifdef _BIG_ENDIAN + pramPtr.srcAddr += (4 - chanHandle->roundedWordWidth); +#endif + pramPtr.destAddr = (uint32_t)ioBuf->addr; + Mcbsp_localGetIndicesSyncType( + chanHandle, + &(pramPtr.destBIdx), + &(pramPtr.destCIdx), + &(pramPtr.aCnt), + &(pramPtr.bCnt), + &(pramPtr.cCnt), + &syncType, + FALSE); + } + else + { + if (TRUE == chanHandle->enableHwFifo) + { + pramPtr.destAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + pramPtr.destAddr = (uint32_t)&(instHandle->hwInfo.regs->DXR); + } +#ifdef _BIG_ENDIAN + pramPtr.destAddr += (4 - chanHandle->roundedWordWidth); +#endif + if (TRUE == chanHandle->bMuteON) + { + /* Mute is set hence we need to switch to the mute buffer */ + pramPtr.srcAddr = + (uint32_t)&Mcbsp_muteBuf[instHandle->instNum].scratchBuffer; + Mcbsp_localGetIndicesSyncType( + chanHandle, + &(pramPtr.srcBIdx), + &(pramPtr.srcCIdx), + &(pramPtr.aCnt), + &(pramPtr.bCnt), + &(pramPtr.cCnt), + &syncType, + TRUE); + } + else + { + pramPtr.srcAddr = (uint32_t)ioBuf->addr; + Mcbsp_localGetIndicesSyncType( + chanHandle, + &(pramPtr.srcBIdx), + &(pramPtr.srcCIdx), + &(pramPtr.aCnt), + &(pramPtr.bCnt), + &(pramPtr.cCnt), + &syncType, + FALSE); + } + } + + /* Here we are enabling the interrupt for this param set info * + * we do it here in this way because using int enable API after * + * calling EDMA3_DRV_setPaRAM, may fail our intention. This is * + * because immediately after the set param the paramset might be * + * copied to linked param and will make the consecutive int enable* + * (set opt field) api useless for our purpose */ + pramPtr.opt |= (0x01u<<20u); + + /* early completion interrupt is enabled */ + pramPtr.opt &= (~(CSL_TPCC_PARAM_OPT_TCCMOD_MASK)); + pramPtr.opt |= (1 << CSL_TPCC_PARAM_OPT_TCCMOD_SHIFT); + + /* set the link address as 0xFFFF */ + pramPtr.linkAddr = 0xFFFFu; + + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + status = EDMA3_DRV_getPaRAM (chanHandle->edmaHandle, + Mcbsp_edmaChanNum, + ¶mSet); + + paramSet.aCnt = 1u; + paramSet.linkAddr = 0xFFFF; + paramSet.opt &= ~(0x01 << 3); + + if (MCBSP_STATUS_COMPLETED == status) + { + /* Now, write the dummy PaRAM Set. */ + status = EDMA3_DRV_setPaRAM(chanHandle->edmaHandle, + Mcbsp_edmaChanNum, + ¶mSet); + } + } + } + else + { + status = MCBSP_ERR_BADARGS; + break; + } + + if (1u == chanHandle->submitCount) + { + /* Configuring bCntReload */ + pramPtr.bCntReload = pramPtr.bCnt; + + /* Src & Dest are in INCR modes */ + pramPtr.opt &= 0xFFFFFFFCu; + + /* FIFO width is 8 bit */ + pramPtr.opt &= 0xFFFFF8FFu; + + /* Set EDMA3_DRV_OPT_FIELD_TCINTEN to TRUE */ + pramPtr.opt |= (CSL_TPCC_PARAM_OPT_TCINTEN_ENABLE + << CSL_TPCC_PARAM_OPT_TCINTEN_SHIFT); + + /* Program the TCC */ + pramPtr.opt |= ((chanHandle->tcc << CSL_TPCC_PARAM_OPT_TCC_SHIFT) + & CSL_TPCC_PARAM_OPT_TCC_MASK); + + /* EDMA3_DRV_SYNC_AB */ + pramPtr.opt &= (~(CSL_TPCC_PARAM_OPT_SYNCDIM_MASK)); + pramPtr.opt |= (syncType << CSL_TPCC_PARAM_OPT_SYNCDIM_SHIFT); + + /* set the link address as dummy address for Tx and 0xFFFF for Rx */ + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + pramPtr.linkAddr = + (uint16_t)(Mcbsp_dummyParamSetAddr & 0x0000FFFF); + } + else + { + pramPtr.linkAddr = 0xFFFFu; + } + + /* early completion interrupt is enabled */ + pramPtr.opt &= (~(CSL_TPCC_PARAM_OPT_TCCMOD_MASK)); + pramPtr.opt |= (1 << CSL_TPCC_PARAM_OPT_TCCMOD_SHIFT); + + status = EDMA3_DRV_setPaRAM( + chanHandle->edmaHandle, + chanHandle->xferChan, + &pramPtr); + + } + else + { + status = EDMA3_DRV_setPaRAM( + chanHandle->edmaHandle, + chanHandle->pramTbl[chanHandle-> + nextLinkParamSetToBeUpdated], + &pramPtr); + } + + if (2u == chanHandle->submitCount) + { + /* link this paramset with the main channel */ + status = EDMA3_DRV_linkChannel( + chanHandle->edmaHandle, + chanHandle->xferChan, + chanHandle->pramTbl \ + [chanHandle->nextLinkParamSetToBeUpdated]); + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADIO; + break; + } + + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + /* link the dummy transfer at the end of the link PaRAM */ + status = EDMA3_DRV_linkChannel( + chanHandle->edmaHandle, + chanHandle->pramTbl \ + [chanHandle->nextLinkParamSetToBeUpdated], + Mcbsp_edmaChanNum); + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADIO; + break; + } + } + } + + /* link this paramset with the other paramset */ + if (3u == chanHandle->submitCount) + { + status = EDMA3_DRV_linkChannel( + chanHandle->edmaHandle, + chanHandle->pramTbl[ + (chanHandle->nextLinkParamSetToBeUpdated + 1u) & 0x01u], + chanHandle->pramTbl \ + [chanHandle->nextLinkParamSetToBeUpdated]); + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADIO; + break; + } + + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + /* link the dummy transfer at the end of the link PaRAM */ + status = EDMA3_DRV_linkChannel( + chanHandle->edmaHandle, + chanHandle->pramTbl \ + [chanHandle->nextLinkParamSetToBeUpdated], + Mcbsp_edmaChanNum); + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADIO; + break; + } + } + + } + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADARGS; + break; + } + }while(falsewhile); + return status; +} + +/** + * \brief setup the EDMA channel for the specific channel requested. + * + * This function configures the McBSP synchonized EDMA channel PaRAM + * entries it also configures the various other parameters like + * source and destination address / modes + * + * \param chanHandle [IN] Channel handle + * + * \return MCBSP_STATUS_COMPLETED if setup successful + * Appropriate MCBSP driver error code if configuration has any error + */ +int32_t Mcbsp_localEdmaChanPaRAMsetup(Mcbsp_ChannelObj *chanHandle) +{ + uint32_t linkCnt = 0; + Mcbsp_Object_Unpadded *instHandle = NULL; + EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0}; + int32_t status = MCBSP_STATUS_COMPLETED; + EDMA3_DRV_SyncType tempSyncType; + + if ((NULL == chanHandle) || (NULL == chanHandle->devHandle)) + { + return MCBSP_ERR_BADARGS; + } + + instHandle = &(chanHandle->devHandle->obj); + if (NULL == instHandle) + { + return MCBSP_ERR_BADARGS; + } + + /* Configure the McBSP synchonized EDMA channel PaRAM entries * + * Configure source and destination address / modes * + * first - main xfer channel */ + + /* following is the explanation behind the EDMA configuration * + * + * 1) We will have n arrays of data (now it is loopjob buffer each of * + * length x bytes) * + * 2) for each sync event we have to fetch the data from each array * + * and write to each serilaiser * + * 3) and the no. bytes transferred in this case from each array will * + * be roundedwordwidth/4 * + * 4) as the loopjob buffer is continous, we configure the counts as * + * follows * + * a) consider there are arrays of length roundedwordwidth/8(aCnt) * + * b) these arrays are located apart lengthofloopjob size (bindex) * + * c) there are 'no.of.slots' no. of such arrays (bCnt) * + * d) (a) and (b) constitute one frame of EDMA transfer and it * + * happens for one sync event in AB sync mode * + * e) such frames have to be sent till we have buffer - ie * + * lengthofloopjob / (roundedwordwidth/8 ) and this * + * constitutes cCnt * + * f) address of buffer (rather offset from start of previous * + * frame) is roundedwordwidth/8 and this forms cIndex * + * Please take some time to visualise the setup mentioned above to * + * check with EDMA configuration The same kind of setup will be used * + * for data transfers also and the change will be buffer pointer * + * and length of data buffer. */ + + /* Get the PaRAM set for default parameters */ + EDMA3_DRV_getPaRAM(chanHandle->edmaHandle,chanHandle->xferChan,¶mSet); + + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* Configuring Source and Dest addresses */ + if (TRUE == chanHandle->enableHwFifo) + { + paramSet.srcAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + paramSet.srcAddr = (uint32_t)&(instHandle->hwInfo.regs->DRR); + } + +#ifdef _BIG_ENDIAN + paramSet.srcAddr += (4 - chanHandle->roundedWordWidth); +#endif + /* Configuring Src and Dest B&C Indexes */ + paramSet.srcBIdx = 0; + paramSet.srcCIdx = 0; + + if (MCBSP_STATUS_COMPLETED != Mcbsp_localGetIndicesSyncType( + chanHandle, + ¶mSet.destBIdx, + ¶mSet.destCIdx, + ¶mSet.aCnt, + ¶mSet.bCnt, + ¶mSet.cCnt, + &tempSyncType, + TRUE)) + { + status = MCBSP_ERR_BADARGS; + } + } + else + { + /* Configuring Source and Dest addresses */ + if (TRUE == chanHandle->enableHwFifo) + { + paramSet.destAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + paramSet.destAddr = (uint32_t)&(instHandle->hwInfo.regs->DXR); + } +#ifdef _BIG_ENDIAN + paramSet.destAddr += (4 - chanHandle->roundedWordWidth); +#endif + /* Configuring Src and Dest B&C Indexes */ + paramSet.destBIdx = 0; + paramSet.destCIdx = 0; + + if (MCBSP_STATUS_COMPLETED != Mcbsp_localGetIndicesSyncType( + chanHandle, + ¶mSet.srcBIdx, + ¶mSet.srcCIdx, + ¶mSet.aCnt, + ¶mSet.bCnt, + ¶mSet.cCnt, + &tempSyncType, + TRUE)) + { + status = MCBSP_ERR_BADARGS; + } + } + + /* Configuring bCntReload */ + paramSet.bCntReload = paramSet.bCnt; + + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + + /* FIFO width is 8 bit */ + paramSet.opt &= 0xFFFFF8FFu; + + /* Set EDMA3_DRV_OPT_FIELD_TCINTEN to FALSE */ + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_ITCINTEN_MASK)); + + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_TCINTEN_MASK)); + paramSet.opt |= (CSL_TPCC_PARAM_OPT_TCINTEN_DISABLE + << CSL_TPCC_PARAM_OPT_TCINTEN_SHIFT); + + /* Program the TCC */ + paramSet.opt |= ((chanHandle->tcc << CSL_TPCC_PARAM_OPT_TCC_SHIFT) + & CSL_TPCC_PARAM_OPT_TCC_MASK); + + /* EDMA3_DRV_SYNC_AB */ + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_SYNCDIM_MASK)); + paramSet.opt |= (tempSyncType << CSL_TPCC_PARAM_OPT_SYNCDIM_SHIFT); + + /* early completion interrupt is enabled */ + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_TCCMOD_MASK)); + paramSet.opt |= (1 << CSL_TPCC_PARAM_OPT_TCCMOD_SHIFT); + + /* Now, write the PaRAM Set. */ + status = EDMA3_DRV_setPaRAM( + chanHandle->edmaHandle, + chanHandle->xferChan, + ¶mSet); + + if (MCBSP_STATUS_COMPLETED == status) + { + /* Configure the link PaRAMs with the appropriate parameters Though * + * we configure all the link paramsets, we will be using only one of * + * them to link with main xfer channel */ + for (linkCnt = 0; linkCnt < Mcbsp_MAXLINKCNT; linkCnt++) + { + /* Get the PaRAM set for default parameters */ + EDMA3_DRV_getPaRAM (chanHandle->edmaHandle, + chanHandle->pramTbl[linkCnt], + ¶mSet); + + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* Configuring Source and Dest addresses */ + if (TRUE == chanHandle->enableHwFifo) + { + paramSet.srcAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + paramSet.srcAddr = (uint32_t)&(instHandle->hwInfo.regs->DRR); + } +#ifdef _BIG_ENDIAN + paramSet.srcAddr += (4 - chanHandle->roundedWordWidth); +#endif + /* Configuring Src and Dest B&C Indexes */ + paramSet.srcBIdx = 0; + paramSet.srcCIdx = 0; + + if (MCBSP_STATUS_COMPLETED != Mcbsp_localGetIndicesSyncType( + chanHandle, + ¶mSet.destBIdx, + ¶mSet.destCIdx, + ¶mSet.aCnt, + ¶mSet.bCnt, + ¶mSet.cCnt, + &tempSyncType, + TRUE)) + { + status = MCBSP_ERR_BADARGS; + } + } + else + { + /* Configuring Source and Dest addresses */ + if (TRUE == chanHandle->enableHwFifo) + { + paramSet.destAddr = (uint32_t)(instHandle->hwInfo.dataAddress); + } + else + { + paramSet.destAddr = (uint32_t)&(instHandle->hwInfo.regs->DXR); + } +#ifdef _BIG_ENDIAN + paramSet.destAddr += (4 - chanHandle->roundedWordWidth); +#endif + paramSet.destBIdx = 0; + paramSet.destCIdx = 0; + + if (MCBSP_STATUS_COMPLETED != Mcbsp_localGetIndicesSyncType( + chanHandle, + ¶mSet.srcBIdx, + ¶mSet.srcCIdx, + ¶mSet.aCnt, + ¶mSet.bCnt, + ¶mSet.cCnt, + &tempSyncType, + TRUE)) + { + status = MCBSP_ERR_BADARGS; + } + } + + /* Configuring bCntReload */ + paramSet.bCntReload = paramSet.bCnt; + + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + + /* FIFO width is 8 bit */ + paramSet.opt &= 0xFFFFF8FFu; + + /* EDMA3_DRV_SYNC_AB */ + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_SYNCDIM_MASK)); + paramSet.opt |= (tempSyncType << CSL_TPCC_PARAM_OPT_SYNCDIM_SHIFT); + + /* Set EDMA3_DRV_OPT_FIELD_TCINTEN to FALSE */ + paramSet.opt |= (CSL_TPCC_PARAM_OPT_TCINTEN_DISABLE + << CSL_TPCC_PARAM_OPT_TCINTEN_SHIFT); + + /* Program the TCC */ + paramSet.opt |= ((chanHandle->tcc << CSL_TPCC_PARAM_OPT_TCC_SHIFT) + & CSL_TPCC_PARAM_OPT_TCC_MASK); + + /* early completion interrupt */ + paramSet.opt &= (~(CSL_TPCC_PARAM_OPT_TCCMOD_MASK)); + paramSet.opt |= (1 << CSL_TPCC_PARAM_OPT_TCCMOD_SHIFT); + + if (MCBSP_STATUS_COMPLETED == status) + { + /* Now, write the PaRAM Set. */ + status = EDMA3_DRV_setPaRAM(chanHandle->edmaHandle, + chanHandle->pramTbl[linkCnt], + ¶mSet); + } + }/*for loop for linkcount*/ + } + return (status); +} +#endif /* #ifdef MCBSP_LOOPJOB_ENABLE */ + +/** + * \brief This checks is the next request in queue is data request. If this is + * an abort request, it calls the appropriate function to deal + * with it. + * + * \param chanHandle [IN] Handle to the Mcbsp Channel + * + * \return Mcbsp_STATUS_INVALID,if no outstanding requests + * Mcbsp_STATUS_VALID, if pending buffer is there + * + */ +int32_t mcbspIsValidIOBuf(Mcbsp_ChannelObj *chanHandle) +{ + int32_t status = Mcbsp_STATUS_INVALID; + + if ((NULL == chanHandle) || (NULL == chanHandle->devHandle)) + { + return MCBSP_ERR_BADARGS; + } + + /* check if the queue has any request to be processed */ + if (FALSE == Mcbsp_osalQueueEmpty(chanHandle->ptrQPendList)) + { + chanHandle->dataIOBuf = (Mcbsp_IOBuf *) Mcbsp_osalQueueGet(chanHandle->ptrQPendList); + + if (NULL != chanHandle->dataIOBuf) + { + /* we have a valid buffer to process next */ + chanHandle->currentDataSize = + (uint16_t)(chanHandle->dataIOBuf->size); + chanHandle->userDataBufferSize = + (uint32_t)(chanHandle->dataIOBuf->size); + + /* Additional to assigning the important parameters as above * + * for DMA mode , we will have max 2 buffers floating and hence * + * we use a activequue to manage this */ + Mcbsp_osalQueuePut(chanHandle->ptrQFloatList, (Mcbsp_QueueElem *)chanHandle->dataIOBuf); + + /* Set the status as valid */ + status = Mcbsp_STATUS_VALID; + } + } + else + { + /* we dont have any buffer in queue stop xmt/rcv SM before giving * + * error */ + chanHandle->dataIOBuf = NULL; + + /* Set the status as invalid to program the loopjob buffer */ + status = Mcbsp_STATUS_INVALID; + } + return status; +} + +/** + * \brief Process the buffer and update the EDMA paramset + * + * For the transmit operation, the eDMA channel's destination + * port is tied to the MCBSP DAT port. In case of receive, the eDMA + * channel's source port is tied to the MCBSP DAT port. The source + * address for transmit eDMA channel and the destination address for + * the receive eDMA channel are set here. + * + * \param chanHandle [IN] Pointer to channel + * \param ioBuf [IN] Pointer to request to be processed + * + * \return MCBSP_STATUS_COMPLETED, if the address is set correctly + * MCBSP_ERR_BADIO otherwise + */ +int32_t Mcbsp_localEdmaProcessPkt(Mcbsp_ChannelObj *chanHandle, + Mcbsp_IOBuf *ioBuf) +{ + int32_t status = MCBSP_STATUS_COMPLETED; + + if ((NULL == chanHandle) || (NULL == ioBuf)) + { + return MCBSP_ERR_BADARGS; + } + + /* we are going to update the paramset from EDMA callback context. That * + * means the one of the param sets are having audio data just completed * + * data request and one having currently loaded (active) data request * + * Current index is pointing only latest paramset (that is active) so * + * move the index */ + Mcbsp_localGetNextIndex(&chanHandle->nextLinkParamSetToBeUpdated); + + /* update the edma paramset with the buffer details */ + status = Mcbsp_localUpdtDtPktToLnkPrms(chanHandle, ioBuf); + + return (status); +} + +/** + * \brief Mcbsp_localGetIndicesSyncType + * + * This function computes the parameters requied to configure EDMA 3 based + * on the buffer format seleted while creating the driver. + * + * Entry Criteria : This function expects channel variables such as no of slots + * length of buffers is updated. + * + * \param chanHandle [IN] Pointer to channel handle + * \param bIndex [IN] Pointer to stores computed bIndex + * \param cIndex [IN] Pointer to stores computed cIndex + * \param aCnt [IN] Pointer to stores computed aCnt + * \param bCnt [IN] Pointer to stores computed bCnt + * \param cCnt [IN] Pointer to stores computed cCnt + * \param syncType [IN] Pointer to stores computed mode of EDMA + * \param forLoopJobBuf [IN] To calucalate above for loopJob or data + * + * CAUTION: This function could be called with pointer pointing to EDMA 3 + * paramset pointer (avoiding couple of variables). Care should be + * take to ensure that data types used in EDMA 3 paramset is + * consistent with EDMA 3 defined data types. + * + * \return MCBSP_ERR_BADARGS on invalid buffer format, else MCBSP_STATUS_COMPLETED + */ +int32_t Mcbsp_localGetIndicesSyncType(Mcbsp_ChannelObj *chanHandle, + volatile int16_t *bIndex, + volatile int16_t *cIndex, + volatile uint16_t *aCnt, + volatile uint16_t *bCnt, + volatile uint16_t *cCnt, + EDMA3_DRV_SyncType *syncType, + Bool forLoopJobBuf) +{ + uint32_t tempSize = 0x0; + int32_t status = MCBSP_STATUS_COMPLETED; + + if(((NULL == chanHandle) || (NULL == bIndex) || (NULL == cIndex) + || (NULL == aCnt) || (NULL == bCnt) || (NULL == cCnt) + || (NULL == syncType))) + { + return MCBSP_ERR_BADARGS; + } + + /* Get the size of the buffer to be used. In case of mute command and * + * normal IOP we will use the actual size of the buffer. For the loop job * + * case 1. if internal loop job then the minimum loop job length will be * + * used. * + * case 2. user supplied loop job buffer then the user loop job length * + * will be used. */ + if ((TRUE == forLoopJobBuf) && (FALSE == chanHandle->bMuteON)) + { + if (TRUE == chanHandle->userLoopJob) + { + /* use the user supplied buffer length for the EDMA params */ + tempSize = chanHandle->userLoopJobLength; + } + else + { + tempSize = chanHandle->loopJobLength; + } + } + else + { + tempSize = chanHandle->userDataBufferSize; + } + + /* Get the indices */ + switch (chanHandle->dataFormat) + { + case Mcbsp_BufferFormat_1SLOT: + case Mcbsp_BufferFormat_MULTISLOT_INTERLEAVED: + *aCnt = chanHandle->roundedWordWidth; + *bCnt = 1u; + *cCnt = (uint16_t)(tempSize/(*aCnt)); + *bIndex = (int16_t)tempSize; + *cIndex = (int16_t)(*aCnt); + *syncType = EDMA3_DRV_SYNC_AB; + break; + case Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED: + *aCnt = chanHandle->roundedWordWidth; + *bCnt = (uint16_t)(chanHandle->numEnabledChannels); + + /* temp Size is always a multiple of the acnt hence the division * + * result will always be an integer */ + *cCnt = (uint16_t)(tempSize /((*aCnt) * (*bCnt))); + /* temp Size is always a multiple of the bcnt when using the * + * multiple slots hence the result will be always an integer */ + *bIndex = (int16_t)(tempSize/(*bCnt)); + *cIndex = (int16_t)((*aCnt) - (((*bCnt)- 1u) * (tempSize/(*bCnt)))); + *syncType = EDMA3_DRV_SYNC_A; + break; + default: + status = MCBSP_ERR_BADARGS; + break; + } + + /* if the loop job buffer being used is the driver internal loop job * + * buffer, dont increment the index for it.Same is the case if mute is ON */ + if (TRUE == forLoopJobBuf) + { + if ((TRUE == chanHandle->bMuteON) || + (FALSE == chanHandle->userLoopJob)) + { + *bIndex = 0; + *cIndex = 0; + } + } + return status; +} + +/* ========================================================================== */ +/* END OF FILE */ +/* ========================================================================== */ + diff --git a/packages/ti/drv/mcbsp/src/mcbsp_ioctl.c b/packages/ti/drv/mcbsp/src/mcbsp_ioctl.c new file mode 100644 index 000000000..43f6f42e2 --- /dev/null +++ b/packages/ti/drv/mcbsp/src/mcbsp_ioctl.c @@ -0,0 +1,630 @@ +/* + * mcbsp_ioctl.c + * + * This file contains local functions for McBSP driver which contain implemen- + * tation for control operation specifc for the McBSP peripheral. + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/* ========================================================================== */ +/* INCLUDE FILES */ +/* ========================================================================== */ + +/* MCBSP CSL-RL */ +#include + +/* MCBSP Types includes */ +#include + +/* MCBSP LLD includes */ +#include +#include + +/* MCBSP OSAL layer */ +#include + +#ifdef MCBSP_LOOPJOB_ENABLE +extern far Mcbsp_TempBuffer Mcbsp_loopDstBuf[CSL_MCBSP_PER_CNT]; +extern far Mcbsp_TempBuffer Mcbsp_loopSrcBuf[CSL_MCBSP_PER_CNT]; +#endif + +/* ========================================================================== */ +/* FUNCTION DEFINTIONS */ +/* ========================================================================== */ + +/** + * \brief Implements the IOCTLS for McBSP driver. + * + * This function implements the McBSP device specific control operations + * including Start/Stop, Pause/Resume, Channel and Device Reset, + * Mute-ON/OFF, McBSP sample rate generator configuration etc. + * + * \param chanHandle [IN] Handle to channel + * \param cmd [IN] Control command number + * \param arg [IN] Arguments for control command + * \param param [IN] user defined data structure + * + * \return MCBSP_STATUS_COMPLETED in case of sucess. + * MCBSP_ERR_NOTIMPL in case the command is not supported. + * MCBSP driver error code in case of any error. + */ +int32_t Mcbsp_localSubmitIoctl(Mcbsp_ChannelObj *chanHandle, + Mcbsp_IOCTL cmd, + void* arg, + void* param) +{ + Mcbsp_Object_Unpadded *instHandle = NULL; + Mcbsp_srgConfig *srgConfig = NULL; + int32_t status = MCBSP_STATUS_COMPLETED; +#ifdef MCBSP_LOOPJOB_ENABLE + Mcbsp_IOBuf *ioBuf = NULL; + uint16_t linkCnt = 0; + Mcbsp_ChanParams *params = NULL; +#endif + + if ((NULL == chanHandle) || (NULL == chanHandle->devHandle)) + { + return MCBSP_ERR_BADARGS; + } + + instHandle = &(chanHandle->devHandle->obj); + if (NULL == instHandle) + { + return MCBSP_ERR_BADARGS; + } + + /* To remove compiler warning */ + param = param; + + /********************command to start the Mcbsp section********************/ + if (Mcbsp_IOCTL_START == cmd) + { + /* stop the Mcbsp channel */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + if (TRUE == instHandle->stopSmFsRcv) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_RX_ENABLE); + instHandle->stopSmFsRcv = FALSE; + } + else + { + /* Already stop port command is issued. This is a redundant * + * command. */ + status = MCBSP_ERR_BADARGS; + } + } + else + { + if (TRUE == instHandle->stopSmFsXmt) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_TX_ENABLE); + instHandle->stopSmFsXmt = FALSE; + } + else + { + /* Already stop port command is issued. This is a redundant * + * command. */ + status = MCBSP_ERR_BADARGS; + } + } + } + + /********************command to stop the Mcbsp section*********************/ + else if (Mcbsp_IOCTL_STOP == cmd) + { + /* abort all the buffers in the driver */ + Mcbsp_localAbortReset(chanHandle); + + /* stop the hardware */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_RX_DISABLE); + instHandle->stopSmFsRcv = TRUE; + } + else + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_TX_DISABLE); + instHandle->stopSmFsXmt = TRUE; + } + } + /****************command to start sample rate generator********************/ + else if (Mcbsp_IOCTL_SRGR_START == cmd) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_SRG_ENABLE); + } + /*****************command to stop sample rate generator********************/ + else if (Mcbsp_IOCTL_SRGR_STOP == cmd) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_SRG_DISABLE); + } + /*****************command to start frame sync generator********************/ + else if (Mcbsp_IOCTL_FSGR_START == cmd) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_FSYNC_ENABLE); + } + else if (Mcbsp_IOCTL_FSGR_STOP == cmd) + { + Mcbsp_localResetCtrl(instHandle,Mcbsp_SpcrCtrl_FSYNC_DISABLE); + } + /******************command to configure the clock polarity*****************/ + else if (Mcbsp_IOCTL_SET_BCLK_POL == cmd) + { + if (NULL == arg) + { + return MCBSP_ERR_BADARGS; + } + + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + if (Mcbsp_ClkPol_FALLING_EDGE == (Mcbsp_ClkPol)(*(uint32_t *)arg)) + { + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_CLKRP_MASK); + } + else + { + instHandle->hwInfo.regs->PCR |= CSL_MCBSP_PCR_CLKRP_MASK; + } + } + else + { + if (Mcbsp_ClkPol_FALLING_EDGE == (Mcbsp_ClkPol)(*(uint32_t *)arg)) + { + instHandle->hwInfo.regs->PCR |= CSL_MCBSP_PCR_CLKXP_MASK; + } + else + { + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_CLKXP_MASK); + } + } + } + /*****************command to configure the frame sync polarity*************/ + else if (Mcbsp_IOCTL_SET_FRMSYNC_POL == cmd) + { + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + if (Mcbsp_FsPol_ACTIVE_LOW == (Mcbsp_FsPol)(*(uint32_t *)arg)) + { + instHandle->hwInfo.regs->PCR |= CSL_MCBSP_PCR_FSRP_MASK; + } + else + { + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_FSRP_MASK); + } + } + else + { + if (Mcbsp_FsPol_ACTIVE_LOW == (Mcbsp_FsPol)(*(uint32_t *)arg)) + { + instHandle->hwInfo.regs->PCR |= CSL_MCBSP_PCR_FSXP_MASK; + } + else + { + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_FSXP_MASK); + } + } + } + /****************** commmand to enable the sync error interrupt************/ + else if (Mcbsp_IOCTL_SYNCERR_INT_ENABLE == cmd) + { + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + instHandle->hwInfo.regs->SPCR |= CSL_MCBSP_SPCR_RINTM_MASK; + } + else + { + instHandle->hwInfo.regs->SPCR |= CSL_MCBSP_SPCR_XINTM_MASK; + } + } + /*****************command to enable disable the LOOP back mode*************/ + else if (Mcbsp_IOCTL_LOOPBACK == cmd) + { + if (NULL != arg) + { + if (Mcbsp_Loopback_DISABLE == (Mcbsp_Loopback)(*(uint32_t *)arg)) + { + instHandle->hwInfo.regs->SPCR |= (CSL_MCBSP_SPCR_DLB_MASK); + } + else + { + instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_DLB_MASK); + } + } + else + { + status = MCBSP_ERR_BADARGS; + } + } + /*********************command to set the bit clock mode *******************/ + else if (Mcbsp_IOCTL_SET_CLKMODE == cmd) + { + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* configure the clock mode (external or internal) */ + if (Mcbsp_TxRxClkMode_EXTERNAL == (Mcbsp_TxRxClkMode)(*(Uint8 *)arg)) + { + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_CLKRM_MASK); + + if (TRUE == instHandle->rxFsgEnable) + { + /* frame sync generator is using the internal clock hence * + * need to enable the sample rate generator */ + instHandle->rxSrgEnable = TRUE; + } + else + { + /* dont require to enable the sample rate generator */ + instHandle->rxSrgEnable = FALSE; + } + } + else + { + /* external mode clock */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_CLKRM_MASK); + + /* sample rate generator is enabled */ + instHandle->rxSrgEnable = TRUE; + } + + } + else + { + /* configure the clock mode (external or internal) */ + if (Mcbsp_TxRxClkMode_EXTERNAL == (Mcbsp_TxRxClkMode)(*(Uint8 *)arg)) + { + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_CLKXM_MASK); + + if (TRUE == instHandle->txFsgEnable) + { + /* frame sync generator is using the internal clock hence * + * need to enable the sample rate generator */ + instHandle->txSrgEnable = TRUE; + } + else + { + /* dont require to enable the sample rate generator */ + instHandle->txSrgEnable = FALSE; + } + } + else + { + /* external mode clock enabled */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_CLKXM_MASK); + + /* sample rate generator is enabled */ + instHandle->txSrgEnable = TRUE; + } + } + } + + /******************** Command to set the frame sycn mode*******************/ + else if (Mcbsp_IOCTL_SET_FRMSYNCMODE == cmd) + { + /* Reciever Bit Clock mode */ + if (MCBSP_MODE_INPUT == chanHandle->mode) + { + /* check if the frame sync generator is to be enabled for section */ + if (Mcbsp_FsClkMode_INTERNAL == (Mcbsp_FsClkMode)(*(Uint8 *)arg)) + { + /* set the frame sync generation mode */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_FSRM_MASK); + + /* frame sync generator needs to be enabled */ + instHandle->rxFsgEnable = TRUE; + } + else + { + /* reset the frame sync generation mode */ + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_FSRM_MASK); + + /* frame sync generator needs to be disabled */ + instHandle->rxFsgEnable = FALSE; + } + } + else + { + /* check if the frame sync generator is to be enabled for section */ + if (Mcbsp_FsClkMode_EXTERNAL == (Mcbsp_FsClkMode)(*(Uint8 *)arg)) + { + /* External frame sync to be used */ + instHandle->hwInfo.regs->PCR &= (~CSL_MCBSP_PCR_FSXM_MASK); + + /* frame sync generator needs to be disabled */ + instHandle->txFsgEnable = FALSE; + } + else + { + /* could be internal or configured for DXR to XSR copy */ + if (Mcbsp_FsClkMode_INTERNAL == (Mcbsp_FsClkMode)(*(Uint8 *)arg)) + { + /* internal frame sync to be used */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_FSXM_MASK); + + /* set the FSGM bit in the SRGR register */ + instHandle->hwInfo.regs->SRGR |= (CSL_MCBSP_SRGR_FSGM_MASK); + + /* frame sync generator needs to be enabled */ + instHandle->txFsgEnable = TRUE; + } + else + { /* DXR to XSR copy generates frame sync */ + /* internal frame sync to be used */ + instHandle->hwInfo.regs->PCR |= (CSL_MCBSP_PCR_FSXM_MASK); + + /* reset the FSGM bit in the SRGR register */ + instHandle->hwInfo.regs->SRGR &= (~CSL_MCBSP_SRGR_FSGM_MASK); + + /* frame sync generator needs to be disabled */ + instHandle->txFsgEnable = FALSE; + } + } + } + } + /****************** command to configure the sample rate generator*********/ + else if (Mcbsp_IOCTL_CONFIG_SRGR == cmd) + { + if (NULL == arg) + { + return MCBSP_ERR_BADARGS; + } + + srgConfig = (Mcbsp_srgConfig *)(arg); + + memcpy(&instHandle->srgrConfig,srgConfig,sizeof(Mcbsp_srgConfig)); + + Mcbsp_localConfigureSrgr(instHandle,chanHandle); + } + /********************command to reset the channel**************************/ + else if ((Mcbsp_IOCTL_CHAN_RESET == cmd) || (MCBSP_CTRL_CHAN_RESET == cmd)) + { + Mcbsp_localAbortReset(chanHandle); + } + /********************command to reset the device***************************/ + else if ((Mcbsp_IOCTL_DEVICE_RESET == cmd) || (MCBSP_CTRL_DEVICE_RESET == cmd)) + { + Mcbsp_localAbortReset(&instHandle->rcvObj); + Mcbsp_localAbortReset(&instHandle->xmtObj); + } + /********************command to change the sample rate*********************/ + else if (Mcbsp_IOCTL_SAMPLE_RATE_CHANGE == cmd) + { + status = Mcbsp_localModifySampleRate(chanHandle,arg); + } + /********************command to cancel pending IO**************************/ + else if (Mcbsp_IOCTL_CANCEL_PENDING_IO == cmd) + { + Mcbsp_localAbortReset(chanHandle); + } +#ifdef MCBSP_LOOPJOB_ENABLE + /****************command to pause the Mcbsp channel************************/ + else if (Mcbsp_IOCTL_PAUSE == cmd) + { + if (FALSE == chanHandle->paused) + { + chanHandle->paused = TRUE; + } + else + { + status = MCBSP_ERR_BADMODE; + } + } + /***************** command to resume the Mcbsp channel*********************/ + else if (Mcbsp_IOCTL_RESUME == cmd) + { + if (TRUE == Mcbsp_osalQueueEmpty(chanHandle->ptrQFloatList)) + { + for (linkCnt = 0;linkCnt < Mcbsp_MAXLINKCNT;linkCnt++) + { + if (FALSE == Mcbsp_osalQueueEmpty(chanHandle->ptrQPendList)) + { + ioBuf = (Mcbsp_IOBuf *)Mcbsp_osalQueueGet(chanHandle->ptrQPendList); + + if (NULL == ioBuf) + { + return MCBSP_ERR_BADARGS; + } + + /* floating queue not full . Process this request. */ + Mcbsp_osalQueuePut(chanHandle->ptrQFloatList, (void*)ioBuf); + + chanHandle->currentDataSize = (uint16_t)ioBuf->size; + chanHandle->userDataBufferSize = (uint32_t)ioBuf->size; + + /* for DMA mode we will not use chanHandke->dataIOBuf * + * to hold current buffer - we use floatingqueue */ + chanHandle->dataIOBuf = NULL; + + if ((Mcbsp_MAXLINKCNT - 1u) == linkCnt) + { + /* Though we have to post to param set directly * + * from here,there will be differene between first * + * such buffer and second buffer. As we have control * + * here we are second buffer and first buffer has not * + * yet returned (or corresponding edma callback has * + * not been called.For second buffer, we will be * + * updating the second param set, which is currently * + * hosting loopjob parameter. Hence increment the * + * index to point second paramset and since we are * + * moving out loopjob from both param sets, the * + * oopjobUpdatedinParamset is reset */ + chanHandle->loopjobUpdatedinParamset =FALSE; + Mcbsp_localGetNextIndex( + &chanHandle->nextLinkParamSetToBeUpdated); + } + + /* Now update the data buffer to the link params. The * + * paramset to be updated is decidec by the * + * "nextLinkParamSetToBeUpdated" */ + if (MCBSP_STATUS_COMPLETED != + Mcbsp_localUpdtDtPktToLnkPrms(chanHandle,ioBuf)) + { + status = MCBSP_ERR_BADIO; + break; + } + + if (0 == linkCnt) + { + /* if at all this is the very first buffer, then * + * one param set has loop job loaded , self linked * + * and active with the main xfer channel param. * + * other param set is ready loaded (just now and * + * has link paramater set as the one having loopjob * + * (this is to ensure that if at all we are not * + * getting any more buffers loopjob be will taken * + * over). Now we have to link the floating / newly * + * loaded param set to xfer channel. */ + status = EDMA3_DRV_linkChannel( + chanHandle->edmaHandle, + chanHandle->xferChan, + chanHandle->pramTbl[chanHandle->nextLinkParamSetToBeUpdated]); + + if (MCBSP_STATUS_COMPLETED != status) + { + status = MCBSP_ERR_BADIO; + break; + } + else + { + EDMA3_DRV_enableTransfer( + chanHandle->edmaHandle, + chanHandle->xferChan, + EDMA3_DRV_TRIG_MODE_EVENT); + } + } + } + } + } + chanHandle->paused = FALSE; + } + /********************command to Mute the Mcbsp section*********************/ + else if (Mcbsp_IOCTL_MUTE_ON == cmd) + { + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + if(TRUE == chanHandle->bMuteON) + { + status = MCBSP_ERR_BADMODE; + } + else + { + chanHandle->bMuteON = (Bool)TRUE; + } + } + else + { + status = MCBSP_ERR_BADMODE; + } + } + /********************command to UnMute the Mcbsp section*******************/ + else if (Mcbsp_IOCTL_MUTE_OFF == cmd) + { + /* Take out from the the Muted state */ + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + /* Check if mute is not ON */ + if (FALSE == chanHandle->bMuteON) + { + status = MCBSP_ERR_BADARGS; + } + else + { + chanHandle->bMuteON =(Bool)FALSE; + } + } + else + { + status = MCBSP_ERR_NOTIMPL; + } + } + /********************command to Modify the loop job buffer*****************/ + else if (Mcbsp_IOCTL_MODIFY_LOOPJOB == cmd) + { + params = (Mcbsp_ChanParams *)arg; + if (NULL == params) + { + return MCBSP_ERR_BADARGS; + } + + if (NULL == params->userLoopJobBuffer) + { + if (MCBSP_MODE_OUTPUT == chanHandle->mode) + { + chanHandle->loopJobBuffer = &Mcbsp_loopSrcBuf[instHandle->instNum].scratchBuffer; + } + else + { + chanHandle->loopJobBuffer = &Mcbsp_loopDstBuf[instHandle->instNum].scratchBuffer; + } + chanHandle->userLoopJob = FALSE; + } + else + { + chanHandle->loopJobBuffer = params->userLoopJobBuffer; + + if (chanHandle->roundedWordWidth > params->userLoopJobLength) + { + chanHandle->loopJobLength = chanHandle->roundedWordWidth; + } + else + { + chanHandle->loopJobLength = params->userLoopJobLength; + chanHandle->userLoopJobLength = params->userLoopJobLength; + chanHandle->userLoopJob = TRUE; + } + } + } +#endif +#ifndef MCBSP_LOOPJOB_ENABLE + /*****************command to modify the Timeout count value****************/ + else if (Mcbsp_IOCTL_SET_TIMEOUT == cmd) + { + if (NULL == arg) + { + return MCBSP_ERR_BADARGS; + } + + /* modify the retry count value to be used */ + instHandle->retryCount = *(uint32_t *)arg; + } +#endif + else + { + status = MCBSP_ERR_NOTIMPL; + } + return (status); +} + +/*============================================================================*/ +/* END OF FILE */ +/*============================================================================*/ diff --git a/packages/ti/drv/mcbsp/src/src_files_common.mk b/packages/ti/drv/mcbsp/src/src_files_common.mk new file mode 100644 index 000000000..4c8eb62cb --- /dev/null +++ b/packages/ti/drv/mcbsp/src/src_files_common.mk @@ -0,0 +1,12 @@ + +SRCDIR = . src +INCDIR = . src +# Common source files across all platforms and cores +SRCS_COMMON += mcbsp_drv.c mcbsp_ioctl.c mcbsp_edma.c + +PACKAGE_SRCS_COMMON = makefile mcbsp_component.mk mcbsp_osal.h \ + docs/ReleaseNotes_MCBSP_LLD.pdf \ + mcbsp_drv.h include/mcbsp_pvt.h \ + mcbsp_types.h \ + build/makefile.mk src/src_files_common.mk + -- 2.39.2