From b431aefd763ff2f15468e87f67038ed5db55f50f Mon Sep 17 00:00:00 2001 From: sujith Date: Fri, 28 Aug 2020 14:43:00 +0530 Subject: [PATCH] PDK-7060 : VCL OSAL updates OSAL UT works for mcu 10, mcu20 and mpu 10 mcusw can_app works for mcu21 Signed-off-by: sujith --- .../board/diag/common/j7200/diag_common_cfg.c | 5 +- packages/ti/drv/mmcsd/soc/j7200/MMCSD_soc.c | 4 +- packages/ti/osal/arch/core/r5/Arch_util.c | 3 +- packages/ti/osal/soc/am335x/osal_soc.h | 3 + packages/ti/osal/soc/am437x/osal_soc.h | 3 + packages/ti/osal/soc/am571x/osal_soc.h | 2 + packages/ti/osal/soc/am572x/osal_soc.h | 3 + packages/ti/osal/soc/am574x/osal_soc.h | 3 + packages/ti/osal/soc/am64x/osal_soc.h | 3 + packages/ti/osal/soc/am65xx/osal_soc.h | 3 + packages/ti/osal/soc/dra72x/osal_soc.h | 2 + packages/ti/osal/soc/dra78x/osal_soc.h | 3 + packages/ti/osal/soc/j7200/TimerP_default.c | 505 +++++++++--------- packages/ti/osal/soc/j7200/osal_soc.h | 25 +- packages/ti/osal/soc/j721e/osal_soc.h | 3 + packages/ti/osal/src/nonos/Nonos_config.h | 0 .../ti/osal/src/nonos/timer/v1/TimerP_nonos.c | 2 +- packages/ti/osal/test/src/main_osal_test.c | 3 +- 18 files changed, 309 insertions(+), 266 deletions(-) mode change 100644 => 100755 packages/ti/osal/soc/am335x/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/am437x/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/am571x/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/am572x/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/am574x/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/am64x/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/am65xx/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/dra72x/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/dra78x/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/j7200/osal_soc.h mode change 100644 => 100755 packages/ti/osal/soc/j721e/osal_soc.h mode change 100644 => 100755 packages/ti/osal/src/nonos/Nonos_config.h mode change 100644 => 100755 packages/ti/osal/src/nonos/timer/v1/TimerP_nonos.c mode change 100644 => 100755 packages/ti/osal/test/src/main_osal_test.c diff --git a/packages/ti/board/diag/common/j7200/diag_common_cfg.c b/packages/ti/board/diag/common/j7200/diag_common_cfg.c index 4cf88c0ba..6bf7f757a 100755 --- a/packages/ti/board/diag/common/j7200/diag_common_cfg.c +++ b/packages/ti/board/diag/common/j7200/diag_common_cfg.c @@ -398,7 +398,10 @@ void BoardDiag_timerIntrDisable(void) /* Disable all the timer interrupts */ for (timerCnt = 0; timerCnt < TimerP_numTimerDevices; timerCnt++) { - Intc_IntDisable(gDmTimerPInfoTbl[timerCnt].intNum); + if (0x0 != gDmTimerPInfoTbl[timerCnt].baseAddr) + { + Intc_IntDisable(gDmTimerPInfoTbl[timerCnt].intNum); + } } } #endif diff --git a/packages/ti/drv/mmcsd/soc/j7200/MMCSD_soc.c b/packages/ti/drv/mmcsd/soc/j7200/MMCSD_soc.c index 2797b204b..4e129a61b 100755 --- a/packages/ti/drv/mmcsd/soc/j7200/MMCSD_soc.c +++ b/packages/ti/drv/mmcsd/soc/j7200/MMCSD_soc.c @@ -260,7 +260,7 @@ MMCSD_Error MMCSD_configSocIntrPath(const void *hwAttrs_ptr, bool setIntrPath) { MMCSD_Error ret=MMCSD_OK; /* Only mcu R5f requires routing of interrupts */ -#if defined(BUILD_MCU1_0) || defined (BUILD_MCU1_1) +#if defined(BUILD_MCU) CSL_ArmR5CPUInfo r5CpuInfo; int32_t retVal; MMCSD_v2_HwAttrs const *hwAttrs = (MMCSD_v2_HwAttrs const *)(hwAttrs_ptr); @@ -308,7 +308,7 @@ MMCSD_Error MMCSD_configSocIntrPath(const void *hwAttrs_ptr, bool setIntrPath) { /* Nothing to be configured as the MMCSD0 -> MAIN R5 does not need any configuration. * It is direct to the core, bypassing INTR and MAIN2MCU RTR. Hence there is no - * firmware involvment needed. Consequently, the interrupt path configuration should + * firmware involvement needed. Consequently, the interrupt path configuration should * bypassed entirely. */ ret = MMCSD_OK; diff --git a/packages/ti/osal/arch/core/r5/Arch_util.c b/packages/ti/osal/arch/core/r5/Arch_util.c index eb6e6269c..1e99d2dab 100755 --- a/packages/ti/osal/arch/core/r5/Arch_util.c +++ b/packages/ti/osal/arch/core/r5/Arch_util.c @@ -41,6 +41,7 @@ #include #include #include +#include /* Local define */ #define HWIP_R5F_DEFAULT_PRIORITY ((uint32_t) 0x0FU) @@ -478,7 +479,7 @@ void osalArch_TimestampInit(void) timerParams.startMode = (uint32_t)TimerP_StartMode_USER; timerParams.periodType = (uint32_t)TimerP_PeriodType_MICROSECS; timerParams.period = 1000000u; - timerHandle = TimerP_create((int32_t)TimerP_ANY, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams); + timerHandle = TimerP_create(OSAL_ARCH_TIMER_INST_FOR_TS, (TimerP_Fxn)&osalArch_TimestampCcntAutoRefresh, &timerParams); if ( timerHandle != NULL_PTR) { diff --git a/packages/ti/osal/soc/am335x/osal_soc.h b/packages/ti/osal/soc/am335x/osal_soc.h old mode 100644 new mode 100755 index f45cfd251..ea5b878b4 --- a/packages/ti/osal/soc/am335x/osal_soc.h +++ b/packages/ti/osal/soc/am335x/osal_soc.h @@ -75,6 +75,9 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 10U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ + #ifdef __cplusplus } #endif diff --git a/packages/ti/osal/soc/am437x/osal_soc.h b/packages/ti/osal/soc/am437x/osal_soc.h old mode 100644 new mode 100755 index a6faf7f49..af100a964 --- a/packages/ti/osal/soc/am437x/osal_soc.h +++ b/packages/ti/osal/soc/am437x/osal_soc.h @@ -75,6 +75,9 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ + #ifdef __cplusplus } #endif diff --git a/packages/ti/osal/soc/am571x/osal_soc.h b/packages/ti/osal/soc/am571x/osal_soc.h old mode 100644 new mode 100755 index ef971b06f..b0fa35e9f --- a/packages/ti/osal/soc/am571x/osal_soc.h +++ b/packages/ti/osal/soc/am571x/osal_soc.h @@ -73,6 +73,8 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ #ifdef __cplusplus } diff --git a/packages/ti/osal/soc/am572x/osal_soc.h b/packages/ti/osal/soc/am572x/osal_soc.h old mode 100644 new mode 100755 index 692aff112..cb5fd9494 --- a/packages/ti/osal/soc/am572x/osal_soc.h +++ b/packages/ti/osal/soc/am572x/osal_soc.h @@ -74,6 +74,9 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ + #ifdef __cplusplus } #endif diff --git a/packages/ti/osal/soc/am574x/osal_soc.h b/packages/ti/osal/soc/am574x/osal_soc.h old mode 100644 new mode 100755 index 4188b2c9c..e20e69407 --- a/packages/ti/osal/soc/am574x/osal_soc.h +++ b/packages/ti/osal/soc/am574x/osal_soc.h @@ -73,6 +73,9 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ + #ifdef __cplusplus } #endif diff --git a/packages/ti/osal/soc/am64x/osal_soc.h b/packages/ti/osal/soc/am64x/osal_soc.h old mode 100644 new mode 100755 index 16cfa7a79..9a8433a2d --- a/packages/ti/osal/soc/am64x/osal_soc.h +++ b/packages/ti/osal/soc/am64x/osal_soc.h @@ -94,6 +94,9 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ + /* external references */ extern Osal_HwAttrs gOsal_HwAttrs; diff --git a/packages/ti/osal/soc/am65xx/osal_soc.h b/packages/ti/osal/soc/am65xx/osal_soc.h old mode 100644 new mode 100755 index 115c63834..4c76759d1 --- a/packages/ti/osal/soc/am65xx/osal_soc.h +++ b/packages/ti/osal/soc/am65xx/osal_soc.h @@ -89,6 +89,9 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ + /* external references */ extern Osal_HwAttrs gOsal_HwAttrs; diff --git a/packages/ti/osal/soc/dra72x/osal_soc.h b/packages/ti/osal/soc/dra72x/osal_soc.h old mode 100644 new mode 100755 index 3c2139646..2df339c6a --- a/packages/ti/osal/soc/dra72x/osal_soc.h +++ b/packages/ti/osal/soc/dra72x/osal_soc.h @@ -74,6 +74,8 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ #ifdef __cplusplus } diff --git a/packages/ti/osal/soc/dra78x/osal_soc.h b/packages/ti/osal/soc/dra78x/osal_soc.h old mode 100644 new mode 100755 index 3ed446d24..b32bdf235 --- a/packages/ti/osal/soc/dra78x/osal_soc.h +++ b/packages/ti/osal/soc/dra78x/osal_soc.h @@ -72,6 +72,9 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ + #ifdef __cplusplus } #endif diff --git a/packages/ti/osal/soc/j7200/TimerP_default.c b/packages/ti/osal/soc/j7200/TimerP_default.c index 79dad900c..e91b77b70 100755 --- a/packages/ti/osal/soc/j7200/TimerP_default.c +++ b/packages/ti/osal/soc/j7200/TimerP_default.c @@ -33,309 +33,293 @@ * ======== TimerP_default.c ======== */ - #include #include #include #include #include -/* +/*! + * @brief gDmTimerPInfoTbl + * * This table sets the default configurations for the DM Timers - * R5: configures MCU domain's DM Timer instance 0 - 9 - * A72: configures Main domain's DM Timer instance 0 - 19 + * MCU Domain R5: configures MCU domain's DM Timer instance 0 - 9 + * Main Domain R5: configures Main domain's DM Timer instance 0 - 19 + * Main Domain A72: configures Main domain's DM Timer instance 0 - 19 * - * TimerP_updateDefaultInfoTbl() is called when TimerP_getTimerBaseAddr() - * is called first time to overwrite the defaut configurations with - * the configurations of Main domain's DM Timer instances if - * R5 is on the Main domain */ + +#if (BUILD_MCU) +TimerP_dmTimerDefault gDmTimerPInfoTbl[OSAL_NONOS_MAX_TIMERP_PER_SOC] = { + { + "DMTimer0", + (uint32_t)CSL_MCU_TIMER0_CFG_BASE, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER0_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer1", + (uint32_t)CSL_MCU_TIMER1_CFG_BASE, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER1_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer2", + (uint32_t)CSL_MCU_TIMER2_CFG_BASE, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER2_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer3", + (uint32_t)CSL_MCU_TIMER3_CFG_BASE, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER3_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer4", + (uint32_t)CSL_MCU_TIMER4_CFG_BASE, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER4_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer5", + (uint32_t)CSL_MCU_TIMER5_CFG_BASE, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER5_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer6", + (uint32_t)CSL_MCU_TIMER6_CFG_BASE, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER6_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer7", + (uint32_t)CSL_MCU_TIMER7_CFG_BASE, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER7_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer8", + (uint32_t)0x0, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER8_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer9", + (uint32_t)0x0, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER9_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer10", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer11", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer12", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer13", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer14", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer15", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer16", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer17", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer18", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + }, + { + "DMTimer18", + (uint32_t)0x0, + (int32_t)0, + TIMERP_EVENT_NOT_AVAILABLE + } +}; +#endif /* MCU - R5F*/ + +#if defined (BUILD_MPU) TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = { /* Timer ID 0 */ { - "DMTimer0", /* Timer Name */ -#if defined (BUILD_MCU) - /* Default configurations for R5 core */ - (uint32_t)CSL_MCU_TIMER0_CFG_BASE, /* MCU domain's DM Timer base address */ - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER0_INTR_PEND_0, /* MCU domain's DM Timer interrupt number */ - TIMERP_EVENT_NOT_AVAILABLE /* Event Id */ -#endif -#if defined (BUILD_MPU) - /* Default configurations for A72 core */ - (uint32_t)CSL_TIMER0_CFG_BASE, /* Main domain's DM Timer base address */ - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER0_INTR_PEND_0, /* Main domain's DM Timer interrupt number */ - TIMERP_EVENT_NOT_AVAILABLE /* Event Id */ -#endif + "DMTimer0", + (uint32_t)CSL_TIMER0_CFG_BASE, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER0_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 1 */ { "DMTimer1", -#if defined (BUILD_MCU) - (uint32_t)CSL_MCU_TIMER1_CFG_BASE, - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER1_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER1_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER1_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)CSL_TIMER1_CFG_BASE, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER1_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 2 */ { "DMTimer2", -#if defined (BUILD_MCU) - (uint32_t)CSL_MCU_TIMER2_CFG_BASE, - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER2_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER2_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER2_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)CSL_TIMER2_CFG_BASE, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER2_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 3 */ { "DMTimer3", -#if defined (BUILD_MCU) - (uint32_t)CSL_MCU_TIMER3_CFG_BASE, - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER3_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER3_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER3_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)CSL_TIMER3_CFG_BASE, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER3_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 4 */ { "DMTimer4", -#if defined (BUILD_MCU) - (uint32_t)CSL_MCU_TIMER4_CFG_BASE, - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER4_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER4_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER4_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)CSL_TIMER4_CFG_BASE, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER4_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 5 */ { "DMTimer5", -#if defined (BUILD_MCU) - (uint32_t)CSL_MCU_TIMER5_CFG_BASE, - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER5_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER5_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER5_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)CSL_TIMER5_CFG_BASE, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER5_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 6 */ { "DMTimer6", -#if defined (BUILD_MCU) - (uint32_t)CSL_MCU_TIMER6_CFG_BASE, - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER6_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER6_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER6_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)CSL_TIMER6_CFG_BASE, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER6_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 7 */ { "DMTimer7", -#if defined (BUILD_MCU) - (uint32_t)CSL_MCU_TIMER7_CFG_BASE, - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER7_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER7_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER7_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)CSL_TIMER7_CFG_BASE, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER7_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 8 */ { "DMTimer8", -#if defined (BUILD_MCU) - (uint32_t)CSL_MCU_TIMER8_CFG_BASE, - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER8_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER8_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER8_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER8_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 9 */ { "DMTimer9", -#if defined (BUILD_MCU) - (uint32_t)CSL_MCU_TIMER9_CFG_BASE, - (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER9_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER9_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER9_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_MCU_R5FSS0_CORE0_INTR_MCU_TIMER9_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 10 */ { "DMTimer10", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER10_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER10_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER10_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 11 */ { "DMTimer11", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER11_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER11_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER11_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 12 */ { "DMTimer12", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER12_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER12_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER12_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 13 */ { "DMTimer13", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER13_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER13_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER13_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 14 */ { "DMTimer14", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER14_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER14_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER14_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 15 */ { "DMTimer15", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER15_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER15_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER15_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 16 */ { "DMTimer16", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER16_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER16_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER16_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 17 */ { "DMTimer17", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER17_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER17_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER17_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 18 */ { "DMTimer18", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER18_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER18_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER18_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE }, /* Timer ID 19 */ { "DMTimer19", -#if defined (BUILD_MCU) - 0U, - 0, - TIMERP_EVENT_NOT_AVAILABLE -#endif -#if defined (BUILD_MPU) - (uint32_t)CSL_TIMER19_CFG_BASE, - (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER19_INTR_PEND_0, - TIMERP_EVENT_NOT_AVAILABLE -#endif + (uint32_t)0x0, + (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER19_INTR_PEND_0, + TIMERP_EVENT_NOT_AVAILABLE } }; +#endif /* Main domain compute */ -/* Returns the default frquency lower 32 bits */ +/* Returns the default frequency lower 32 bits */ int32_t TimerP_getDefaultFreqLo(uint32_t timerId) { (void)timerId; @@ -343,7 +327,7 @@ int32_t TimerP_getDefaultFreqLo(uint32_t timerId) return(TIMERP_TIMER_FREQ_LO); } -/* Returns the default frquency higher 32 bits */ +/* Returns the default frequency higher 32 bits */ int32_t TimerP_getDefaultFreqHi(uint32_t timerId) { (void)timerId; @@ -354,62 +338,79 @@ int32_t TimerP_getDefaultFreqHi(uint32_t timerId) #if defined (BUILD_MCU) uint32_t TimerP_mapId(uint32_t id) { - uint32_t translate_id; - - CSL_ArmR5CPUInfo info; - - CSL_armR5GetCpuID(&info); - - if (info.grpId == (uint32_t)CSL_ARM_R5_CLUSTER_GROUP_ID_0) - { - translate_id = id; - } - else - { - /* - * The interrupt events of Main domain's DM Timer instance 12 - 19 - * are directly connected to the MAIN Pulsar VIMs. - * This translation matches to sysbios implementation, where id=0 is - * for dmTimer12, id =1 is for dmTimer13 etc. - */ - translate_id = id + 6U; - } - return (translate_id); + /* No remaps required */ + return (id); } +/*! + * @brief TimerP_updateDefaultInfoTbl + * + * The OSAL is built once for a given class of processors (i.e. one lib for R5F + * which would be used for R5F in mcu & main domains. If we were to support + * one lib per core the size would increase drastically) + * + * TimerP_updateDefaultInfoTbl() is called when TimerP_getTimerBaseAddr() + * is called first time to overwrite the default configurations if any. + * + * By default timer details for timer in MCU domain is stored, we will override + * with timer details in main domain for R5F in main domain + */ + void TimerP_updateDefaultInfoTbl(void) { - uint32_t i; + uint32_t i, intBase; CSL_ArmR5CPUInfo info; CSL_armR5GetCpuID(&info); - if (info.grpId != (uint32_t)CSL_ARM_R5_CLUSTER_GROUP_ID_0) + /* Main domain R5F only */ + if ((uint32_t)CSL_ARM_R5_CLUSTER_GROUP_ID_1 == info.grpId) { - /* Pulsar R5 SS is on the Main domain */ + intBase = CSLR_R5FSS0_CORE0_INTR_TIMER0_INTR_PEND_0; for (i = 0U; i < TimerP_numTimerDevices; i++) { - gDmTimerPInfoTbl[i].baseAddr = ((uint32_t)CSL_TIMER0_CFG_BASE) + \ - (((uint32_t)0x10000U) * i); - if (i < 12U) + gDmTimerPInfoTbl[i].baseAddr = CSL_TIMER0_CFG_BASE + (i * 0x10000U); + gDmTimerPInfoTbl[i].intNum = intBase + i; + gDmTimerPInfoTbl[i].eventId = TIMERP_EVENT_NOT_AVAILABLE; + + if (CSL_TIMER12_CFG_BASE == gDmTimerPInfoTbl[i].baseAddr) { - /* - * The interrupt events of Main domain's DM Timer instance 0 - 11 are routed - * by default through the MAIN_PULSARx Int Routers for connection to the R5 VIMs - */ - gDmTimerPInfoTbl[i].intNum = (int32_t)CSLR_COMPUTE_CLUSTER0_MSMC_1MB_GIC_SPI_RTI0_INTR_WWD_0 + (int32_t)i; + intBase = CSLR_R5FSS0_CORE0_INTR_TIMER12_INTR_PEND_0; } - else + + /* Main domain timers 8 to 19 requires to be powered up, explicitly + current SBL, do not perform this op + When additional timer are required, please power up using + LPSC_PER_SPARE0 and skip this condition */ + if (CSL_TIMER8_CFG_BASE <= gDmTimerPInfoTbl[i].baseAddr) { - /* - * The interrupt events of Main domain's DM Timer instance 12 - 19 - * are directly connected to the MAIN Pulsar VIMs. - */ - gDmTimerPInfoTbl[i].intNum = (int32_t)CSLR_R5FSS0_CORE0_INTR_TIMER12_INTR_PEND_0 + (int32_t)i - 12; + gDmTimerPInfoTbl[i].baseAddr = 0x0; } } } + return; } -#endif + +inline int32_t TimerP_getPreferredDefInst(void) +{ + int32_t instVal; + CSL_ArmR5CPUInfo info; + CSL_armR5GetCpuID(&info); + + /* Main domain R5F only */ + instVal = 4; + if ((uint32_t)CSL_ARM_R5_CLUSTER_GROUP_ID_1 == info.grpId) + { + instVal = 6; + } + if (CSL_ARM_R5_CPU_ID_1 == info.cpuID) + { + instVal++; + } + return (instVal); +} + +#endif /* MCU Specific */ + /* Nothing past this point */ diff --git a/packages/ti/osal/soc/j7200/osal_soc.h b/packages/ti/osal/soc/j7200/osal_soc.h old mode 100644 new mode 100755 index ad2d675c0..92bbfaa89 --- a/packages/ti/osal/soc/j7200/osal_soc.h +++ b/packages/ti/osal/soc/j7200/osal_soc.h @@ -67,14 +67,15 @@ extern "C" { #define TIMERP_TIMER_FREQ_LO ((int32_t) 25000000) #define TIMERP_TIMER_FREQ_HI ((int32_t) 0) -#define TimerP_numTimerDevices ((uint32_t) 20U ) -#if defined (BUILD_MCU) - #define TIMERP_ANY_MASK ((uint32_t) 0x000F) - #define TIMERP_AVAILABLE_MASK ((uint32_t)(0x000F)) -#else - #define TIMERP_ANY_MASK ((uint32_t) 0x0FFF) - #define TIMERP_AVAILABLE_MASK ((uint32_t)(0x0FFF)) -#endif +#define TimerP_numTimerDevices (20U) +/**< Total number of instances in a given domain */ +#define TIMERP_ANY_MASK ((uint32_t) 0x1FFFFF) +/**< Any available */ +#define TIMERP_AVAILABLE_MASK ((uint32_t)(0x1FFFFF)) +/**< Which instances are available */ +#define TIMERP_INST_4_TS (TimerP_getPreferredDefInst) + + /* using the default timer base addresses */ #if defined(__aarch64__) @@ -100,6 +101,14 @@ extern "C" { /* external references */ extern Osal_HwAttrs gOsal_HwAttrs; +#if defined (BUILD_MCU) +extern inline int32_t TimerP_getPreferredDefInst(void); +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_getPreferredDefInst()) +/**< Returns the instance of timers required for given instance */ +#else +#define OSAL_ARCH_TIMER_INST_FOR_TS (2) +/**< Default timer for MPU */ +#endif #ifdef __cplusplus } diff --git a/packages/ti/osal/soc/j721e/osal_soc.h b/packages/ti/osal/soc/j721e/osal_soc.h old mode 100644 new mode 100755 index b77ba5745..9afa59b93 --- a/packages/ti/osal/soc/j721e/osal_soc.h +++ b/packages/ti/osal/soc/j721e/osal_soc.h @@ -98,6 +98,9 @@ extern "C" { #define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) #define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) +#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) +/**< Default timer instance for timer */ + /* external references */ extern Osal_HwAttrs gOsal_HwAttrs; diff --git a/packages/ti/osal/src/nonos/Nonos_config.h b/packages/ti/osal/src/nonos/Nonos_config.h old mode 100644 new mode 100755 diff --git a/packages/ti/osal/src/nonos/timer/v1/TimerP_nonos.c b/packages/ti/osal/src/nonos/timer/v1/TimerP_nonos.c old mode 100644 new mode 100755 index 1f9ce159f..51f366bf4 --- a/packages/ti/osal/src/nonos/timer/v1/TimerP_nonos.c +++ b/packages/ti/osal/src/nonos/timer/v1/TimerP_nonos.c @@ -544,7 +544,7 @@ static TimerP_Status TimerP_dmTimerInstanceInit(TimerP_Struct *timer, uint32_t i HwiP_restore(key); - if (tempId == 0xffffU) { + if ((tempId == 0xffffU) || (0x0 == baseAddr)) { ret = TimerP_NOT_AVAILABLE; } } diff --git a/packages/ti/osal/test/src/main_osal_test.c b/packages/ti/osal/test/src/main_osal_test.c old mode 100644 new mode 100755 index 54468ddbc..13893da7b --- a/packages/ti/osal/test/src/main_osal_test.c +++ b/packages/ti/osal/test/src/main_osal_test.c @@ -579,7 +579,7 @@ bool OSAL_timer_test() #endif #endif -#if !defined(SOC_J721E) || defined(SOC_J7200) +#if !defined(SOC_J721E) || !defined(SOC_J7200) #if defined(_TMS320C6X) timerParams.intNum = 15; OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id); @@ -1578,6 +1578,7 @@ void sysIdleLoop(void) */ int main(void) { + #if defined(BUILD_C66X_1) || defined(BUILD_C66X_2) /* To set C66 timer interrupts on J7ES VLAB */ C66xTimerInterruptInit(); -- 2.39.2