pasdk/shared/config.bld

   1 /*
   2 Copyright (c) 2017, Texas Instruments Incorporated - http://www.ti.com/
   3 All rights reserved.
   4
   5 * Redistribution and use in source and binary forms, with or without
   6 * modification, are permitted provided that the following conditions
   7 * are met:
   8 *
   9 * Redistributions of source code must retain the above copyright
  10 * notice, this list of conditions and the following disclaimer.
  11 *
  12 * Redistributions in binary form must reproduce the above copyright
  13 * notice, this list of conditions and the following disclaimer in the
  14 * documentation and/or other materials provided with the
  15 * distribution.
  16 *
  17 * Neither the name of Texas Instruments Incorporated nor the names of
  18 * its contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 *
  33 */
  34
  35
  36 /*
  37  *  ======== config.bld ========
  38  *
  39  */
  40 var Build = xdc.useModule('xdc.bld.BuildEnvironment');
  41
  42 /*  Memory Map for ti.platforms.evmTCI66AK2G02
  43  *
  44  *    Address          Size             Comment
  45  *  -------------------------------------------------------------
  46  *    0C00_0000   0008_0000  ( 512 KB)  SR_MSMC     (ipc:data)
  47  *    0C08_0000   0004_0000  ( 256 KB)  HOST_MSMC   (code, data)
  48  *    0C0C_0000   0004_0000  ( 256 KB)  CORE0_MSMC  (code, data)
  49  *    8000_0000   0020_0000  (   2 MB)  SR_0        (ipc)
  50  *    8020_0000   0060_0000  (   6 MB)  COMMON_DDR3 (data)
  51  *    8100_0000   0100_0000  (  16 MB)  COMMON2_DDR3(code, data)      // aligned to MAR memory region
  52  *    8200_0000   0100_0000  (  16 MB)  SR_DDR3     (ipc:data)
  53  *    8300_0000   0300_0000  (  48 MB)  HOST_DDR3   (code, data)
  54  *    8600_0000   0400_0000  (  64 MB)  CORE0_DDR3  (code, data)
  55  *    8A00_0000   7600_0000  (1888 MB)  DDR3        (code, data)
  56  */
  57
  58 var SR_MSMC = {
  59         name: "SR_MSMC", space: "data", access: "RW",
  60         base: 0x0C000000, len: 0x00080000,
  61         comment: "SR MSMC Memory (512 KB)"
  62     };
  63
  64 var SR_0 = {
  65         name: "SR_0", space: "data", access: "RW",
  66         base: 0x80000000, len: 0x00200000,
  67         comment: "SR#0 Memory"
  68     };
  69
  70 var SR_DDR3 = {
  71         name: "SR_DDR3", space: "data", access: "RW",
  72         base: 0x82000000, len: 0x01000000,
  73         comment: "SR DDR3 Memory"
  74     };
  75
  76 var COMMON_DDR3 = {
  77         name: "COMMON_DDR3", space: "data", access: "RW",
  78         base: 0x80200000, len: 0x00600000,
  79         comment: "COMMON DDR3 Memory"
  80     };
  81
  82 var COMMON2_DDR3 = {  // Common Structure for shared data, Non cacheable
  83         name: "COMMON2_DDR3", space: "data", access: "RW",
  84         base: 0x81000000, len: 0x01000000,
  85         comment: "COMMON 2 PP DDR3 Memory"
  86     };
  87
  88 var DDR3 = {
  89         name: "DDR3", space: "code/data", access: "RW",
  90         base: 0x8A000000, len: 0x76000000,
  91         comment: "DDR3 Memory"
  92     };
  93
  94 // This is ARM
  95 Build.platformTable["ti.platforms.evmTCI66AK2G02:host"] = {
  96     customMemoryMap: [
  97         ["SR_MSMC", SR_MSMC],
  98
  99         [ "HOST_MSMC",  {
 100             name: "HOST_MSMC", space: "code/data", access: "RWX",
 101             base: 0x0C080000, len: 0x00040000,
 102             comment: "HOST MSMC SRAM"
 103         }],
 104
 105         ["SR_0", SR_0],
 106
 107         ["SR_DDR3", SR_DDR3],
 108
 109         ["COMMON_DDR3", COMMON_DDR3],
 110
 111         ["COMMON2_DDR3", COMMON2_DDR3],
 112
 113         [ "HOST_DDR3",  {
 114             name: "HOST_DDR3", space: "code/data", access: "RWX",
 115             base: 0x83000000, len: 0x03000000,
 116             comment: "HOST DDR3"
 117         }],
 118
 119         ["DDR3", DDR3]
 120     ],
 121
 122     codeMemory:  "HOST_DDR3",
 123     dataMemory:  "HOST_DDR3",
 124     stackMemory: "HOST_DDR3"
 125 };
 126
 127 // This is DSP
 128 Build.platformTable["ti.platforms.evmTCI66AK2G02:core0"] = {
 129     customMemoryMap: [
 130         ["L2SRAM", {
 131             comment:    "1MB L2 SRAM/CACHE",
 132             name:       "L2SRAM",
 133             base:       0x00800000,
 134             len:        0x00100000,
 135             space:      "code/data",
 136             access:     "RWX"
 137         }],
 138
 139         ["L1PSRAM", {
 140             comment:    "32KB RAM/CACHE L1 program memory",
 141             name:       "L1PSRAM",
 142             base:       0x00E00000,
 143             len:        0x00008000,
 144             space:      "code",
 145             access:     "RWX"
 146         }],
 147
 148         ["L1DSRAM", {
 149             comment:    "32KB RAM/CACHE L1 data memory",
 150             name:       "L1DSRAM",
 151             base:       0x00F00000,
 152             len:        0x00008000,
 153             space:      "data",
 154             access:     "RW"
 155         }],
 156
 157         ["SR_MSMC", SR_MSMC],
 158
 159         [ "CORE0_MSMC",  {
 160             name: "CORE0_MSMC", space: "code/data", access: "RWX",
 161             base: 0x0C0C0000, len: 0x00040000,
 162             comment: "CORE0 MSMC SRAM"
 163         }],
 164
 165         ["SR_0", SR_0],
 166
 167         ["SR_DDR3", SR_DDR3],
 168
 169         ["COMMON_DDR3", COMMON_DDR3],
 170
 171         ["COMMON2_DDR3", COMMON2_DDR3],
 172
 173         [ "CORE0_DDR3",  {
 174             name: "CORE0_DDR3", space: "code/data", access: "RWX",
 175             base: 0x86000000, len: 0x04000000,
 176             comment: "CORE0 DDR3"
 177         }],
 178
 179         ["DDR3", DDR3]
 180     ],
 181
 182     codeMemory:  "CORE0_DDR3",
 183     dataMemory:  "CORE0_DDR3",
 184     stackMemory: "CORE0_DDR3",
 185
 186     l1DMode: "32k",
 187     l1PMode: "32k",
 188     l2Mode: "256k"
 189 };