pasdk/shared/config.bld

   1 /*
   2 Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/
   3 All rights reserved.
   4
   5 * Redistribution and use in source and binary forms, with or without
   6 * modification, are permitted provided that the following conditions
   7 * are met:
   8 *
   9 * Redistributions of source code must retain the above copyright
  10 * notice, this list of conditions and the following disclaimer.
  11 *
  12 * Redistributions in binary form must reproduce the above copyright
  13 * notice, this list of conditions and the following disclaimer in the
  14 * documentation and/or other materials provided with the
  15 * distribution.
  16 *
  17 * Neither the name of Texas Instruments Incorporated nor the names of
  18 * its contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 *
  33 */
  34
  35
  36 /*
  37  *  ======== config.bld ========
  38  *
  39  */
  40 var Build = xdc.useModule('xdc.bld.BuildEnvironment');
  41
  42 /*  Memory Map for ti.platforms.evmTCI66AK2G02
  43  *
  44  *    Address          Size             Comment
  45  *  -------------------------------------------------------------
  46  *    0C00_0000   0008_0000  ( 512 KB)  SR_MSMC     (ipc:data)
  47  *    0C08_0000   0004_0000  ( 256 KB)  HOST_MSMC   (code, data)
  48  *    0C0C_0000   0004_0000  ( 256 KB)  CORE_MSMC   (code, data)
  49  *    8000_0000   0020_0000  (   2 MB)  SR_0        (ipc)
  50  *    8020_0000   0080_0000  (   8 MB)  SR_DDR3     (ipc:data)
  51  *    80A0_0000   0080_0000  (   8 MB)  COMMON_DDR3 (data)
  52  *    8120_0000   0400_0000  (  64 MB)  HOST_DDR3   (code, data)
  53  *    8520_0000   0400_0000  (  64 MB)  CORE0_DDR3  (code, data)
  54  *    8920_0000   76E0_0000  (1902 MB)  DDR3        (code, data)
  55  */
  56
  57 var SR_MSMC = {
  58         name: "SR_MSMC", space: "data", access: "RW",
  59         base: 0x0C000000, len: 0x00080000,
  60         comment: "SR MSMC Memory (512 KB)"
  61     };
  62
  63 var SR_0 = {
  64         name: "SR_0", space: "data", access: "RW",
  65         base: 0x80000000, len: 0x00200000,
  66         comment: "SR#0 Memory"
  67     };
  68
  69 var SR_DDR3 = {
  70         name: "SR_DDR3", space: "data", access: "RW",
  71         base: 0x80200000, len: 0x00800000,
  72         comment: "SR DDR3 Memory"
  73     };
  74
  75 var COMMON_DDR3 = {
  76         name: "COMMON_DDR3", space: "data", access: "RW",
  77         base: 0x80A00000, len: 0x00800000,
  78         comment: "COMMON DDR3 Memory"
  79     };
  80
  81 var DDR3 = {
  82         name: "DDR3", space: "code/data", access: "RW",
  83         base: 0x89200000, len: 0x76E00000,
  84         comment: "DDR3 Memory"
  85     };
  86
  87 // This is ARM
  88 Build.platformTable["ti.platforms.evmTCI66AK2G02:host"] = {
  89     customMemoryMap: [
  90         ["SR_MSMC", SR_MSMC],
  91
  92         [ "HOST_MSMC",  {
  93             name: "HOST_MSMC", space: "code/data", access: "RWX",
  94             base: 0x0C080000, len: 0x00040000,
  95             comment: "HOST MSMC SRAM"
  96         }],
  97
  98         ["SR_0", SR_0],
  99
 100         ["SR_DDR3", SR_DDR3],
 101
 102         ["COMMON_DDR3", COMMON_DDR3],
 103
 104         [ "HOST_DDR3",  {
 105             name: "HOST_DDR3", space: "code/data", access: "RWX",
 106             base: 0x81200000, len: 0x04000000,
 107             comment: "HOST DDR3"
 108         }],
 109
 110         ["DDR3", DDR3]
 111     ],
 112
 113     codeMemory:  "HOST_DDR3",
 114     dataMemory:  "HOST_DDR3",
 115     stackMemory: "HOST_DDR3"
 116 };
 117
 118 // This is DSP
 119 Build.platformTable["ti.platforms.evmTCI66AK2G02:core0"] = {
 120     customMemoryMap: [
 121         ["L2SRAM", {
 122             comment:    "1MB L2 SRAM/CACHE",
 123             name:       "L2SRAM",
 124             base:       0x00800000,
 125             len:        0x00100000,
 126             space:      "code/data",
 127             access:     "RWX"
 128         }],
 129
 130         ["L1PSRAM", {
 131             comment:    "32KB RAM/CACHE L1 program memory",
 132             name:       "L1PSRAM",
 133             base:       0x00E00000,
 134             len:        0x00008000,
 135             space:      "code",
 136             access:     "RWX"
 137         }],
 138
 139         ["L1DSRAM", {
 140             comment:    "32KB RAM/CACHE L1 data memory",
 141             name:       "L1DSRAM",
 142             base:       0x00F00000,
 143             len:        0x00008000,
 144             space:      "data",
 145             access:     "RW"
 146         }],
 147
 148         ["SR_MSMC", SR_MSMC],
 149
 150         [ "CORE0_MSMC",  {
 151             name: "CORE0_MSMC", space: "code/data", access: "RWX",
 152             base: 0x0C0C0000, len: 0x00040000,
 153             comment: "CORE0 MSMC SRAM"
 154         }],
 155
 156         ["SR_0", SR_0],
 157
 158         ["SR_DDR3", SR_DDR3],
 159
 160         ["COMMON_DDR3", COMMON_DDR3],
 161
 162         [ "CORE0_DDR3",  {
 163             name: "CORE0_DDR3", space: "code/data", access: "RWX",
 164             base: 0x85200000, len: 0x04000000,
 165             comment: "CORE0 DDR3"
 166         }],
 167
 168         ["DDR3", DDR3]
 169     ],
 170
 171     codeMemory:  "CORE0_DDR3",
 172     dataMemory:  "CORE0_DDR3",
 173     stackMemory: "CORE0_DDR3",
 174
 175     l1DMode: "32k",
 176     l1PMode: "32k",
 177     l2Mode: "256k"
 178 };