[processor-sdk/performance-audio-sr.git] / pasdk / test_dsp / application / itopo / evmk2g / audio_dc_cfg.c
2 /*
3 Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
4 All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
36 /**
37 * \file audio_dc_config.c
38 *
39 * \brief Configures Audio daughter card HW modules
40 *
41 */
43 #include "audio_dc_cfg.h"
44 #include "vproccmds_a.h"
45 #include <stdarg.h>
46 #include "string.h"
47 #include <xdc/runtime/Log.h>
48 #include "aud_audio.h"
50 #define HSR4_I2C_ADDR 0x5D
51 #define HSR4_I2C_PORT_NUM CSL_I2C_1
52 #define I2C_TRANSACTION_TIMEOUT (2000U)
54 I2C_Params i2cParams;
55 I2C_Handle i2cHandle = NULL;
56 I2C_Transaction i2cTransaction;
57 uint32_t gI2cDelay=I2C_TRANSACTION_TIMEOUT;
59 Aud_STATUS audioHDMIConfig(void);
60 int alpha_i2c_write(unsigned short, ...);
61 void set_audio_desc(unsigned char ,unsigned char ,unsigned char ,unsigned char ,unsigned char );
62 void hrptredid();
63 void hdmi128();
65 int gret_val=0;
67 /* ------------------------------------------------------------------------ *
68 * Prototypes *
69 * ------------------------------------------------------------------------ */
71 /**
72 * \brief Initializes ADC module
73 *
74 * This function initializes and configures the ADC modules
75 * on audio daughter card
76 *
77 * \param devId [IN] ADC Device Id
78 * \param config [IN] ADC configuration parameters
79 *
80 * \return Platform_EOK on Success or error code
81 */
82 Aud_STATUS audioAdcConfig(AudAdcDevId devId, AdcConfig *config)
83 {
84 Aud_STATUS status;
86 if(config == NULL)
87 {
88 IFPRINT(aud_write("Invalid Inputs\n"));
89 return (Aud_EINVALID);
90 }
92 /* Initialize all the HW instances of ADC */
93 status = aud_AudioAdcInit(devId);
94 if(status != Aud_EOK)
95 {
96 IFPRINT(aud_write("audioAdcConfig : aud_AudioAdcInit Failed\n"));
97 return (status);
98 }
100 /* Set ADC channel gain */
101 status = aud_AudioAdcSetGain(devId, AUD_ADC_CH_ALL, config->gain);
102 if(status != Aud_EOK)
103 {
104 IFPRINT(aud_write("audioAdcConfig : aud_AudioAdcSetGain Failed\n"));
105 return (status);
106 }
108 /* Configure Left input mux for ADC1L */
109 status = aud_AudioAdcSetLeftInputMux(devId, AUD_ADC_CH1_LEFT,
110 config->adc1LMux);
111 if(status != Aud_EOK)
112 {
113 IFPRINT(aud_write("audioAdcConfig : aud_AudioAdcSetLeftInputMux Failed\n"));
114 return (status);
115 }
117 /* Configure Left input mux for ADC2L*/
118 status = aud_AudioAdcSetLeftInputMux(devId, AUD_ADC_CH2_LEFT,
119 config->adc2LMux);
120 if(status != Aud_EOK)
121 {
122 IFPRINT(aud_write("audioAdcConfig : aud_AudioAdcSetLeftInputMux Failed\n"));
123 return (status);
124 }
126 /* Configure Right input mux for ADC1R */
127 status = aud_AudioAdcSetRightInputMux(devId, AUD_ADC_CH1_RIGHT,
128 config->adc1RMux);
129 if(status != Aud_EOK)
130 {
131 IFPRINT(aud_write("audioAdcConfig : aud_AudioAdcSetRightInputMux Failed\n"));
132 return (status);
133 }
135 /* Configure Right input mux for ADC2R */
136 status = aud_AudioAdcSetRightInputMux(devId, AUD_ADC_CH2_RIGHT,
137 config->adc2RMux);
138 if(status != Aud_EOK)
139 {
140 IFPRINT(aud_write("audioAdcConfig : aud_AudioAdcSetRightInputMux Failed\n"));
141 return (status);
142 }
144 /* Configure audio data format */
145 status = aud_AudioAdcDataConfig(devId, config->wlen, config->format);
146 if(status != Aud_EOK)
147 {
148 IFPRINT(aud_write("audioAdcConfig : aud_AudioAdcDataConfig Failed\n"));
149 return (status);
150 }
152 /* Configure all the interrupts */
153 status = aud_AudioAdcConfigIntr(devId, AUD_ADC_INTR_ALL,
154 config->intEnable);
155 if(status != Aud_EOK)
156 {
157 IFPRINT(aud_write("audioAdcConfig : aud_AudioAdcConfigIntr Failed\n"));
158 return (status);
159 }
161 return (status);
162 }
164 /**
165 * \brief Initializes DAC module
166 *
167 * This function initializes and configures the DAC modules
168 * on audio daughter card
169 *
170 * \param devId [IN] DAC Device Id
171 * \param config [IN] DAC configuration parameters
172 *
173 * \return Platform_EOK on Success or error code
174 */
175 Aud_STATUS audioDacConfig(AudDacDevId devId, DacConfig *config)
176 {
177 Aud_STATUS status;
179 if(config == NULL)
180 {
181 IFPRINT(aud_write("Invalid Inputs\n"));
182 return (Aud_EINVALID);
183 }
185 /* Initialize Audio DAC */
186 status = aud_AudioDacInit(devId);
187 if(status != Aud_EOK)
188 {
189 IFPRINT(aud_write("audioDacConfig : aud_AudioDacInit Failed\n"));
190 return (status);
191 }
193 /* Configure AMUTE control event */
194 status = aud_AudioDacAmuteCtrl(devId, config->amuteCtrl,
195 config->amuteEnable);
196 if(status != Aud_EOK)
197 {
198 IFPRINT(aud_write("audioDacConfig : aud_AudioDacAmuteCtrl Failed\n"));
199 return (status);
200 }
202 /* Set sampling mode */
203 status = aud_AudioDacSetSamplingMode(devId, config->samplingMode);
204 if(status != Aud_EOK)
205 {
206 IFPRINT(aud_write("audioDacConfig : aud_AudioDacSetSamplingMode Failed\n"));
207 return (status);
208 }
210 /* Set data format */
211 status = aud_AudioDacSetDataFormat(devId, config->dataFormat);
212 if(status != Aud_EOK)
213 {
214 IFPRINT(aud_write("audioDacConfig : aud_AudioDacSetDataFormat Failed\n"));
215 return (status);
216 }
218 /* Enable soft mute control */
219 status = aud_AudioDacSoftMuteCtrl(devId, AUD_DAC_CHAN_ALL,
220 config->softMuteEnable);
221 if(status != Aud_EOK)
222 {
223 IFPRINT(aud_write("audioDacConfig : aud_AudioDacSoftMuteCtrl Failed\n"));
224 return (status);
225 }
227 /* Set attenuation mode */
228 status = aud_AudioDacSetAttnMode(devId, config->attnMode);
229 if(status != Aud_EOK)
230 {
231 IFPRINT(aud_write("audioDacConfig : aud_AudioDacSetAttnMode Failed\n"));
232 return (status);
233 }
235 /* Set De-emphasis control */
236 status = aud_AudioDacDeempCtrl(devId, config->deempCtrl);
237 if(status != Aud_EOK)
238 {
239 IFPRINT(aud_write("audioDacConfig : aud_AudioDacDeempCtrl Failed\n"));
240 return (status);
241 }
243 /* Set DAC volume */
244 status = aud_AudioDacSetVolume(devId, AUD_DAC_CHAN_ALL, config->volume);
245 if(status != Aud_EOK)
246 {
247 IFPRINT(aud_write("audioDacConfig : aud_AudioDacSetVolume Failed\n"));
248 return (status);
249 }
251 return (status);
252 }
254 /**
255 * \brief Initializes DIR module
256 *
257 * This function initializes and configures the DIR modules
258 * on audio daughter card
259 *
260 * \return Platform_EOK on Success or error code
261 */
262 Aud_STATUS audioDirConfig(void)
263 {
264 Aud_STATUS status;
265 int8_t fsout;
266 #ifdef CHECK_ERROR_STATUS
267 uint32_t timeout;
268 #endif
270 status = aud_AudioDirInit();
271 if(status != Aud_EOK)
272 {
273 IFPRINT(aud_write("audioDirConfig : Audio DIR Configuration Failed!\n"));
274 return (status);
275 }
277 #ifdef CHECK_ERROR_STATUS
278 /* DIR should be in PLL mode.
279 Wait for ERROR signal to be low as DIR is configured for
280 AUTO mode */
281 timeout = ERROR_STATUS_WAIT_TIMEOUT;
282 while (timeout)
283 {
284 if(!aud_AudioDirGetErrStatus())
285 {
286 IFPRINT(aud_write("audioDirConfig : DIR in PLL Mode\n"));
287 break;
288 }
290 IFPRINT(aud_write("audioDirConfig : Waiting for DIR to Enter PLL Mode...\n"));
291 aud_delay(10);
292 timeout--;
293 }
295 if(!timeout)
296 {
297 IFPRINT(aud_write("audioDirConfig : DIR is not in PLL Mode!!\n"));
298 return (Platform_EFAIL);
299 }
300 #endif
302 fsout = aud_AudioDirGetFsOut();
303 if(fsout == 2)
304 {
305 IFPRINT(aud_write("audioDirConfig : Out of Range Sampling Frequency\n"));
306 }
307 else if(fsout == 0)
308 {
309 IFPRINT(aud_write("audioDirConfig : Calculated Sampling Frequency Output is 43 kHz\9645.2 kHz\n"));
310 }
311 else if(fsout == 1)
312 {
313 IFPRINT(aud_write("audioDirConfig : Calculated Sampling Frequency Output is 46.8 kHz\9649.2 kHz\n"));
314 }
315 else if(fsout == 3)
316 {
317 IFPRINT(aud_write("audioDirConfig : Calculated Sampling Frequency Output is 31.2 kHz\9632.8 kHz\n"));
318 }
319 else
320 {
321 IFPRINT(aud_write("audioDirConfig : Error in Reading FSOUT status \n"));
322 status = Aud_EFAIL;
323 }
325 return (status);
326 }
328 /**
329 * \brief Prepare Alpha commands for serial (I2C) communication
330 *
331 * This function parses the presented HSR41 alpha commands
332 * and prepares CPM-formatted messages to be sent over the serial interface.
333 *
334 * \return '1' on completion
335 */
337 int alpha_i2c_write(unsigned short var1, ...)
338 {
339 unsigned short alpha_type,length,temp_var;
340 int i,offset,ret_val;
341 unsigned char cmd[50];
342 char *s;
343 va_list argp;
344 va_start(argp, var1);
346 alpha_type = var1>> 8;
347 switch(alpha_type)
348 {
349 case 0xca:
350 case 0xc2:
351 case 0xc3:
352 case 0xc4:
353 length = 4;
354 break;
355 case 0xcb:
356 length = 6;
357 break;
358 case 0xcc:
359 length = 8;
360 break;
361 case 0xcd:
362 case 0xc5:
363 length= 8; // temporary - data starts after 8 bytes
364 break;
365 }
367 cmd[0]=length;
368 temp_var=var1;
369 for(i=0;i<length-2;i+=2) // convert to bytes as per protocol
370 {
371 cmd[i+1]= temp_var & 0xff;
372 cmd[i+2]= temp_var >> 8;
373 temp_var=va_arg(argp, short);
374 }
375 cmd[i+1]= temp_var & 0xff;
376 cmd[i+2]= temp_var >> 8;
379 if(alpha_type == 0xcd) // special processing for variable length
380 {
381 offset=9;
382 s = va_arg(argp, char *); // remaining data is in form of string
383 length = temp_var; // last short indicates data length
384 cmd[0]+=length;
385 for(i=offset;i<offset+length;i++)
386 cmd[i]=s[i-offset];
387 }
388 va_end(argp);
390 do
391 {
392 I2C_transactionInit(&i2cTransaction);
393 i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
394 i2cTransaction.writeBuf = cmd;
395 i2cTransaction.writeCount = cmd[0]+1;
396 i2cTransaction.timeout = I2C_TRANSACTION_TIMEOUT;
397 ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
399 if(ret_val !=I2C_STS_SUCCESS)
400 {
401 gret_val++;
402 I2C_control(i2cHandle, I2C_CMD_RECOVER_BUS, &gI2cDelay);
403 }
404 }while(ret_val !=I2C_STS_SUCCESS);
406 return ret_val;
407 }
409 /**
410 * \brief Prepares audio format descriptors
411 *
412 * This function prepares the configuration data to be programmed in HSR41's
413 * audio format descriptor registers.
414 *
415 *
416 * \return none
417 */
418 void set_audio_desc(unsigned char var1,unsigned char var2,unsigned char var3,unsigned char var4,unsigned char var5)
419 {
420 int ret_val=I2C_STS_SUCCESS;
422 do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_FORMAT(var1, var2));}while (ret_val !=I2C_STS_SUCCESS);
423 do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_NUM_CHANNELS(var1, var3));}while (ret_val !=I2C_STS_SUCCESS);
424 do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_SAMPLE_RATES(var1, var4));}while (ret_val !=I2C_STS_SUCCESS);
425 do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_MISC(var1, var5));}while (ret_val !=I2C_STS_SUCCESS);
426 }
428 /**
429 * \brief Program HDMI CEA / EDID values, as necessary.
430 *
431 * This function configures the HSR41 HDMI Repeater
432 * with the necessary CEA/EDID information, enabling support for
433 * the required audio formats.
434 *
435 * \return none
436 */
438 void hrptredid()
439 {
440 int ret_val=I2C_STS_SUCCESS;
442 do{ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK(0xFF));}while (ret_val !=I2C_STS_SUCCESS);
443 aud_delay(10);
444 do{ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK_2(0x7));}while (ret_val !=I2C_STS_SUCCESS);
446 set_audio_desc(0,1,2,0x7f,7); // PCM 2 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4 KHz, 192 KHz, 16bit, 20bit, 24bit
447 set_audio_desc(1,1,8,0x7f,7); // PCM 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4 KHz, 192 KHz, 16bit, 20bit, 24bit
448 set_audio_desc(2,2,6,0x7,80); // AC3 6 channel, 32kHz, 44.1kHz, 48kHz, 640kHz max bit rate
449 set_audio_desc(3,10,8,0x07,1); // Dolby Digital Plus, 8 channel, 32kHz, 44.1kHz, 48kHz, codec specific:1
450 set_audio_desc(4,12,8,0x7F,1); // MAT(MPL)(Dolby TrueHD), 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz,
451 // 176.4kHz, 192kHz, codec specific:1
452 set_audio_desc(5,7,6,0x1E,192); // DTS 6 channel, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 1,536kHz max bit rate
453 set_audio_desc(6,7,8,0x6,192); // DTS 8 channel, 44.1kHz, 48kHz, 1,536kHz max bit rate
454 set_audio_desc(7,11,8,0x7F,3); // DTS-HD, 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz,
455 // last byte is 3 for DTS:X, 1 otherwise.
456 set_audio_desc(8,11,8,0x7F,1); // DTS-HD, 8 channel - same as above, but last byte = 1
457 set_audio_desc(9,6,6,0x1f,192); //AAC LC (9,6,6,0x1f,192);
458 set_audio_desc(10,0,0,0,0);
459 set_audio_desc(11,0,0,0,0);
460 set_audio_desc(12,0,0,0,0);
461 set_audio_desc(13,0,0,0,0);
462 set_audio_desc(14,0,0,0,0);
463 set_audio_desc(15,0,0,0,0);
464 set_audio_desc(16,0,0,0,0);
465 set_audio_desc(17,0,0,0,0);
466 set_audio_desc(18,0,0,0,0);
467 set_audio_desc(19,0,0,0,0);
468 do{ret_val=alpha_i2c_write(HSDIO_EDID_GO);}while (ret_val !=I2C_STS_SUCCESS);
469 }
471 /**
472 * \brief Configures HSR41's TO_HOST interface
473 *
474 * This function configures the HDMI repeater for EXTRACT mode of operation
475 * with the necessary HOST interface programming.
476 *
477 * \return None
478 */
479 // Note: HDMI Tx/Out Port's state is not cared for, at all.
481 void hdmi128()
482 {
483 int ret_val=I2C_STS_SUCCESS;
485 do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_CHANGE_msk));}while (ret_val !=I2C_STS_SUCCESS);
486 do{ret_val=alpha_i2c_write(HSDIO_AUDIO_MCLK_TO_HOST(HSDIO_AudioMClk_128X));}while (ret_val !=I2C_STS_SUCCESS);
487 do{ret_val=alpha_i2c_write(HSDIO_AUDIO_UNMUTE_DELAY_TO_HOST(HSDIO_AudioUnMuteDelay_NO_DELAY));}while (ret_val !=I2C_STS_SUCCESS);
488 do{ret_val=alpha_i2c_write(HSDIO_AUDIO_FORMAT_TO_HOST(HSDIO_AudioFmt_I2S));}while (ret_val !=I2C_STS_SUCCESS);
489 do{ret_val=alpha_i2c_write(HSDIO_IMPLEMENT_AUDIO_TO_HOST_CMDS);}while (ret_val !=I2C_STS_SUCCESS);
490 do{ret_val=alpha_i2c_write(HSDIO_AUDIO_ROUTING(HSDIO_AudioRouting_HSDIOIN_NOOUT));}while (ret_val !=I2C_STS_SUCCESS);
491 do{ret_val=alpha_i2c_write(HSDIO_SYS_CFG_GO);}while (ret_val !=I2C_STS_SUCCESS);
492 }
494 /**
495 * \brief Fetch Video Sync Status from HSR41
496 *
497 * This function retrieves the Video Sync status from HSR41
498 * as part of the 'D10 initialization' sequence, prior to
499 * any subsequent interaction.
500 *
501 * \return 1 on Success
502 */
504 unsigned int read_hdmi_videosyncstatus()
505 {
506 unsigned char data[50];
507 Uint8 length=0;
508 int ret_val=0;
510 aud_delay(10);
511 ret_val=alpha_i2c_write(HSDIO_INPUT_SYNC_STS);
512 Log_info0("read_hdmi_videosyncstatus: After writing HSDIO_INPUT_SYNC_STS.");
514 if(ret_val ==I2C_STS_SUCCESS)
515 {
516 I2C_transactionInit(&i2cTransaction);
517 i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
518 i2cTransaction.readBuf = &length;
519 i2cTransaction.readCount = 1;
520 i2cTransaction.timeout = I2C_TRANSACTION_TIMEOUT;
521 ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
522 if(ret_val ==I2C_STS_SUCCESS)
523 {
524 Log_info1("read_hdmi_videosyncstatus: The read count is %d.",length);
525 I2C_transactionInit(&i2cTransaction);
526 i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
527 i2cTransaction.readBuf = &data[0];
528 i2cTransaction.readCount = length;
529 i2cTransaction.timeout = I2C_TRANSACTION_TIMEOUT;
530 ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
531 Log_info1("read_hdmi_videosyncstatus: returned status = 0x%x", data[2]);
532 }
534 }
535 else
536 {
537 gret_val++;
538 I2C_control(i2cHandle, I2C_CMD_RECOVER_BUS, &gI2cDelay);
539 }
541 if(ret_val == I2C_STS_SUCCESS) ret_val= data[2]; // 1-byte / indicates error status
542 else
543 {
544 gret_val++;
545 I2C_control(i2cHandle, I2C_CMD_RECOVER_BUS, &gI2cDelay);
546 }
548 return ret_val;
549 }
551 /**
552 * \brief Clear the HMINT status
553 *
554 * This function clears the status of HMINT signal on HSR41.
555 *
556 * \return none
557 */
558 void clear_hdmi_hmint()
559 {
560 int ret_val=0;
562 aud_delay(10);
563 ret_val=alpha_i2c_write(HSDIO_ALERT_STS); //clear the interrupt on ~HMINT by reading the Alert Status register
565 if(ret_val !=I2C_STS_SUCCESS)
566 while(1); // Control shouldn't be here
568 return;
569 }
571 /**
572 * \brief Retrieve the HDMI input interface rate
573 *
574 * This function retrieves the input sample rate (or interface rate for bitstreams)
575 * from the HSR41 card.
576 *
577 * \return HSDIO Sample Rate on Success
578 */
579 Uint32 read_hdmi_samprate()
580 {
581 unsigned char data[50];
582 Uint8 length;
583 int ret_val=7;
585 Log_info0("Audio DC CFG: Entered read_hdmi_samprate");
586 aud_delay(10);
587 ret_val=alpha_i2c_write(HSDIO_AUDIO_INPUT_FREQ_STS);\
588 if(ret_val==I2C_STS_SUCCESS)
589 {
590 I2C_transactionInit(&i2cTransaction);
591 i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
592 i2cTransaction.readBuf = &length;
593 i2cTransaction.readCount = 1;
594 i2cTransaction.timeout = I2C_TRANSACTION_TIMEOUT;
595 ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
596 if(ret_val==I2C_STS_SUCCESS)
597 {
598 I2C_transactionInit(&i2cTransaction);
599 i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
600 i2cTransaction.readBuf = &data[0];
601 i2cTransaction.readCount = length;
602 i2cTransaction.timeout = I2C_TRANSACTION_TIMEOUT;
603 ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
604 }
606 }
607 else
608 while(1);
610 Log_info0("Audio DC CFG: Leaving read_hdmi_samprate");
612 if(ret_val==I2C_STS_SUCCESS) ret_val= data[2]; // indicates sample rate
613 else
614 while(1);
616 return ret_val;
617 }
619 /**
620 * \brief Initializes the HSR41 HDMI repeater module
621 *
622 * This function initializes and configures the HSR41 module
623 * via the serial (I2C1) command interface for the necessary
624 * audio operations.
625 *
626 * \return Aud_EOK on Success
627 */
628 Aud_STATUS audioHDMIConfig(void)
629 {
630 Aud_STATUS status = Aud_EOK;
632 I2C_HwAttrs i2c_cfg;
634 /* Get the default I2C init configurations */
635 I2C_socGetInitCfg(HSR4_I2C_PORT_NUM, &i2c_cfg);
637 i2c_cfg.enableIntr = 0; // disable interrupt
639 /* Set the default I2C init configurations */
640 I2C_socSetInitCfg(HSR4_I2C_PORT_NUM, &i2c_cfg);
642 I2C_init();
644 I2C_Params_init(&i2cParams);
645 /* BitRate : 400 Kbps */
646 i2cParams.bitRate = I2C_400kHz;
648 i2cHandle = I2C_open(HSR4_I2C_PORT_NUM, &i2cParams);
650 Log_info0("Before EDID config.");
651 hrptredid();
653 Log_info0("Before HSR4 Clock config.");
654 hdmi128();
656 Log_info0("Before HSR4 Video Sync Detection.");
658 while((HSDIO_InSync_SYNC_DETECTED != read_hdmi_videosyncstatus()));
660 Log_info0("After HSR4 Video Sync Detection.");
662 return (status);
663 }
666 /* Nothing past this point */