481cc7221666ae66505d0c164956cca5ee6f7cad
[processor-sdk/performance-audio-sr.git] / pasdk / test_dsp / application / itopo / evmk2g / mcasp_cfg.c
1 /*
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file mcasp_config.c
36 *
37 * \brief Configures McASP module
38 *
39 */
41 #include "mcasp_cfg.h"
42 #include "ioConfig.h"
44 #define AUDIO_DAC0_TEST
46 /* McASP device handles - one for each McASP port. */
47 Ptr mcaspDevHandles[NUM_MCASP_PORTS] = {NULL, NULL, NULL};
49 /* McASP parameters needed by mcaspBindDev */
50 Mcasp_Params mcaspParams;
52 /* Error flag */
53 uint32_t gblErrFlag = 0;
54 Error_Block eb;
56 void GblErr(Mcasp_errCbStatus arg);
58 /* Handle to eDMA */
59 extern EDMA3_DRV_Handle hEdma0;
60 extern EDMA3_DRV_Handle hEdma1;
62 /* External function declarations */
63 extern void McaspDevice_init(void);
64 extern signed char* getGlobalAddr(signed char* addr);
66 #ifdef IO_LOOPBACK_TEST
67 extern void mcaspAppCallbackRx(void* arg, MCASP_Packet *mcasp_packet);
68 extern void mcaspAppCallbackTx(void* arg, MCASP_Packet *mcasp_packet);
69 #else
70 extern void asipMcaspCallback(void* arg, MCASP_Packet *mcasp_packet);
71 extern void asopMcaspCallback(void* arg, MCASP_Packet *mcasp_packet);
72 #endif
75 /* McASP HW setup for receive (ADC) */
76 Mcasp_HwSetupData mcaspRcvSetupADC = {
77 /* .rmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
78 /* .rfmt = */ 0x0001C0F0, /*
79 * 0 bit delay from framesync
80 * MSB first
81 * No extra bit padding
82 * Padding bit (ignore)
83 * slot Size is 32
84 * Reads from DMA port
85 * NO rotation
86 */
87 /* .afsrctl = */ 0X00000112, /* I2S mode - 2 slot TDM
88 * Frame sync is one word
89 * Internally generated frame sync
90 * Rising edge is start of frame
91 */
92 /* .rtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */
93 /* .rintctl = */ 0x00000000, /* sync error and overrun error */
94 /* .rstat = */ 0x000001FF, /* reset any existing status bits */
95 /* .revtctl = */ 0x00000000, /* DMA request is enabled */
96 {
97 /* .aclkrctl = */ 0x000000A7, // Receiver samples data on the rising edge of the serial clock
98 // Internal receive clock source from output of programmable bit clock divider
99 // Receive bit clock divide ratio = 8
100 /* .ahclkrctl = */ 0x00008000, // Internal receive high-frequency clock source from output of programmable high clock divider.
101 // Falling edge. AHCLKR is inverted before programmable bit clock divider.
102 /* .rclkchk = */ 0x00000000
103 }
104 };
106 /* McASP HW setup for receive (S/PDIF or HDMI)*/
107 Mcasp_HwSetupData mcaspRcvSetupDIR = {
108 MCASP_DIR_RMASK, /* .rmask: 0xFFFFFFFF */
109 MCASP_DIR_RFMT, /* .rfmt: 0x000180F0 */
110 MCASP_DIR_AFSRCTL, /* .afsrctl: 0x00000111 */
111 MCASP_DIR_RTDM, /* .rtdm: 0x00000003 */
112 MCASP_DIR_RINTCTL, /* .rintctl: 0x00000000 */
113 MCASP_DIR_RSTAT, /* .rstat: 0x000001FF */
114 MCASP_DIR_REVTCTL, /* .revtctl */
115 {
116 MCASP_DIR_ACLKRCTL, /* .aclkrctl: 0x00000080 */ // Receiver samples data on the rising edge of the serial clock
117 // External receive clock source from ACLKR pin.
118 // Receive bit clock divide ratio = 1
119 MCASP_DIR_AHCLKRCTL, /* .ahclkrctl: 0x00000000 */
120 MCASP_DIR_RCLKCHK /* .rclkchk: 0x00000000 */
121 }
122 };
124 /* McASP HW setup for transmit (DAC) */
125 Mcasp_HwSetupData mcaspXmtSetupDAC = {
126 /* .xmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
127 /* .xfmt = */ 0x000180F0, /*
128 * 0 bit delay from framesync
129 * MSB first
130 * No extra bit padding
131 * Padding bit (ignore)
132 * slot Size is 32
133 * Reads from DMA port
134 * NO rotation
135 */
136 /* .afsxctl = */ 0x00000112, /* I2S mode - 2 slot TDM
137 * Frame sync is one word
138 * Rising edge is start of frame
139 * Internally generated frame sync
140 */
141 /* .xtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */
142 /* .xintctl = */ 0x00000000, /* sync error,overrun error,clK error */
143 /* .xstat = */ 0x000001FF, /* reset any existing status bits */
144 /* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */
145 {
146 // /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2 --> works for 48khz PCM but not for DDP
147 /* .aclkxctl = */ 0X000000E7, // Transmit bit clock divide ratio = 8 --> working for DDP/MAT/THD 48khz but not for PCM
148 // /* .aclkxctl = */ 0X000000E3, // Transmit bit clock divide ratio = 4 --> THD 96khz
149 // /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2 --> THD 192khz
150 /* .ahclkxctl = */ 0x00004000,
151 /* .xclkchk = */ 0x00000000
152 },
153 };
155 /* McASP HW setup for transmit (DAC slave) */
156 Mcasp_HwSetupData mcaspXmtSetupDACSlave = {
157 /* .xmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
158 /* .xfmt = */ 0x000180F0, /*
159 * 0 bit delay from framesync
160 * MSB first
161 * No extra bit padding
162 * Padding bit (ignore)
163 * slot Size is 32
164 * Reads from DMA port
165 * NO rotation
166 */
167 /* .afsxctl = */ 0x00000113, /* I2S mode - 2 slot TDM
168 * Frame sync is one word
169 * Rising edge is start of frame
170 * Internally generated frame sync
171 */
172 /* .xtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */
173 /* .xintctl = */ 0x00000000, /* sync error,overrun error,clK error */
174 /* .xstat = */ 0x000001FF, /* reset any existing status bits */
175 /* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */
176 {
177 /* .aclkxctl = */ 0X000000A7,
178 /* .ahclkxctl = */ 0x0000C000,
179 /* .xclkchk = */ 0x00000000
180 },
181 };
183 /* McASP channel parameters for ADC input */
184 Mcasp_ChanParams mcaspRxChanParamADC =
185 {
186 0x0004, /* number of serializers */
187 {Mcasp_SerializerNum_0,
188 Mcasp_SerializerNum_1,
189 Mcasp_SerializerNum_2,
190 Mcasp_SerializerNum_3 }, /* serializer index */
191 &mcaspRcvSetupADC,
192 TRUE, /* isDmaDriven */
193 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
194 Mcasp_WordLength_32, /* wordWidth */
195 NULL, /* void * userLoopJobBuffer */
196 0, /* userLoopJobLength */
197 NULL, /* edmaHandle */
198 GblErr,
199 2, /* number of TDM channels */
200 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
201 TRUE, /* enableHwFifo */
202 1, /* hwFifoEventDMARatio */
203 TRUE, /* isDataPacked */
204 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
205 };
207 /* McASP channel parameters for ADC 6 channel input */
208 Mcasp_ChanParams mcaspRxChanParamADC6ch =
209 {
210 0x0003, /* number of serializers */
211 {Mcasp_SerializerNum_0,
212 Mcasp_SerializerNum_1,
213 Mcasp_SerializerNum_2}, /* serializer index */
214 &mcaspRcvSetupADC,
215 TRUE,
216 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
217 Mcasp_WordLength_32,
218 NULL,
219 0,
220 NULL,
221 GblErr,
222 2, /* number of TDM channels */
223 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
224 TRUE, /* enableHwFifo */
225 1, /* hwFifoEventDMARatio */
226 TRUE, /* isDataPacked */
227 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
228 };
230 /* McASP channel parameters for ADC stereo input */
231 Mcasp_ChanParams mcaspRxChanParamADCStereo =
232 {
233 0x0001, /* number of serializers */
234 {Mcasp_SerializerNum_0}, /* serializer index */
235 &mcaspRcvSetupADC,
236 TRUE,
237 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
238 Mcasp_WordLength_32,
239 NULL,
240 0,
241 NULL,
242 GblErr,
243 2, /* number of TDM channels */
244 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
245 TRUE, /* enableHwFifo */
246 1, /* hwFifoEventDMARatio */
247 TRUE, /* isDataPacked */
248 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
249 };
251 /* McAsp channel parameters for DIR input */
252 Mcasp_ChanParams mcaspRxChanParamDIR =
253 {
254 0x0001, /* Number of serializers */
255 {Mcasp_SerializerNum_5}, /* Serializer index */
256 &mcaspRcvSetupDIR,
257 TRUE,
258 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
259 Mcasp_WordLength_16, /* 16-bit by default */
260 NULL,
261 0,
262 NULL,
263 GblErr,
264 2, /* number of TDM channels */
265 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
266 TRUE,
267 1, /* hwFifoEventDMARatio */
268 TRUE, /* isDataPacked */
269 Mcasp_WordBitsSelect_MSB /* wordBitsSelect */
270 };
272 /* McASP LLD channel parameters for HDMI input with 4XI2S:
273 * When slot size of McASP is configured to 32-bit, HDMI data always come to 16 MSBs of the slot
274 * and the 16 LSBs are filled with 0's. This is the nature of HDMI and I2S.
275 * For PCM data, we want all 32 bits in the slot to be transferred to the input buffer:
276 * - wordWidth = Mcasp_WordLength_32
277 * - isDataPacked = 1,
278 * - wordBitsSelect having no effect since wordWidth = slot size
279 * For bit stream, we want only 16 MSBs in the slot to be transferred to the input buffer:
280 * - wordWidth = Mcasp_WordLength_16
281 * - isDataPacked = 1,
282 * - wordBitsSelect = Mcasp_WordBitsSelect_MSB
283 */
284 Mcasp_ChanParams mcaspRxChanParamHDMI =
285 {
286 0x0004, /* number of serializers */
287 {Mcasp_SerializerNum_12,
288 Mcasp_SerializerNum_13,
289 Mcasp_SerializerNum_14,
290 Mcasp_SerializerNum_15 }, /* serializer index */
291 &mcaspRcvSetupDIR,
292 TRUE,
293 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
294 Mcasp_WordLength_16, /* 16-bit word length, MSB or LSB of slot to be transfered, depending on wordBitsSelect */
295 NULL,
296 0,
297 NULL,
298 GblErr,
299 2, /* number of TDM channels */
300 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
301 TRUE, /* enableHwFifo */
302 1, /* hwFifoEventDMARatio */
303 TRUE, /* isDataPacked, only transfer the selected bits of slot, based on wordWidth and wordBitsSelect */
304 Mcasp_WordBitsSelect_MSB /* wordBitsSelect, only matters if wordWidth < slot size */
305 };
307 /* McAsp channel parameters for HDMI stereo input with 1XI2S */
308 Mcasp_ChanParams mcaspRxChanParamHDMIStereo =
309 {
310 0x0001, /* Number of serializers */
311 {Mcasp_SerializerNum_12}, /* Serializer index */
312 &mcaspRcvSetupDIR,
313 TRUE,
314 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
315 Mcasp_WordLength_16, /* 16-bit by default */
316 NULL,
317 0,
318 NULL,
319 GblErr,
320 2, /* number of TDM channels */
321 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
322 TRUE, /* enableHwFifo */
323 1, /* hwFifoEventDMARatio */
324 TRUE, /* isDataPacked */
325 Mcasp_WordBitsSelect_MSB /* wordBitsSelect */
326 };
328 /* McAsp channel parameters for DAC output - DAC0 */
329 Mcasp_ChanParams mcaspTx0ChanParamDAC =
330 {
331 0x0004, /* number of serializers */
332 {Mcasp_SerializerNum_0,
333 Mcasp_SerializerNum_1,
334 Mcasp_SerializerNum_2,
335 Mcasp_SerializerNum_3 }, /* serializer index for DAC0 */
336 &mcaspXmtSetupDAC,
337 TRUE,
338 Mcasp_OpMode_TDM,
339 Mcasp_WordLength_32, /* word width */
340 NULL,
341 0,
342 NULL,
343 GblErr,
344 2, /* number of TDM channels */
345 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
346 TRUE,
347 1, /* hwFifoEventDMARatio */
348 TRUE, /* isDataPacked */
349 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
350 };
352 /* McAsp channel parameters for DAC stereo output - DAC0 */
353 Mcasp_ChanParams mcaspTx0ChanParamDACStereo =
354 {
355 0x0001, /* number of serializers */
356 {Mcasp_SerializerNum_0}, /* serializer index for DAC0 */
357 &mcaspXmtSetupDAC,
358 TRUE,
359 Mcasp_OpMode_TDM,
360 Mcasp_WordLength_32, /* word width */
361 NULL,
362 0,
363 NULL,
364 GblErr,
365 2, /* number of TDM channels */
366 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
367 TRUE,
368 1, /* hwFifoEventDMARatio */
369 TRUE, /* isDataPacked */
370 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
371 };
373 /* McAsp channel parameters for DAC 12 channel output */
374 Mcasp_ChanParams mcaspTx0ChanParamDAC12ch =
375 {
376 0x0006, /* number of serializers */
377 {Mcasp_SerializerNum_0,
378 Mcasp_SerializerNum_1,
379 Mcasp_SerializerNum_2,
380 Mcasp_SerializerNum_3,
381 Mcasp_SerializerNum_4,
382 Mcasp_SerializerNum_5 }, /* serializer index for DAC0 */
383 &mcaspXmtSetupDAC,
384 TRUE,
385 Mcasp_OpMode_TDM,
386 Mcasp_WordLength_32, /* word width */
387 NULL,
388 0,
389 NULL,
390 GblErr,
391 2, /* number of TDM channels */
392 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
393 TRUE,
394 1, /* hwFifoEventDMARatio */
395 TRUE, /* isDataPacked */
396 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
397 };
399 /* McAsp channel parameters for DAC 16 channel output */
400 Mcasp_ChanParams mcaspTx0ChanParamDAC16ch =
401 {
402 0x0008, /* number of serializers */
403 {Mcasp_SerializerNum_0,
404 Mcasp_SerializerNum_1,
405 Mcasp_SerializerNum_2,
406 Mcasp_SerializerNum_3,
407 Mcasp_SerializerNum_4,
408 Mcasp_SerializerNum_5,
409 Mcasp_SerializerNum_6,
410 Mcasp_SerializerNum_7 }, /* serializer index for DAC0 */
411 &mcaspXmtSetupDAC,
412 TRUE,
413 Mcasp_OpMode_TDM,
414 Mcasp_WordLength_32, /* word width */
415 NULL,
416 0,
417 NULL,
418 GblErr,
419 2, /* number of TDM channels */
420 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
421 TRUE,
422 1, /* hwFifoEventDMARatio */
423 TRUE, /* isDataPacked */
424 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
425 };
427 /* McAsp channel parameters for transmit - DAC1 */
428 Mcasp_ChanParams mcaspTx1ChanParam =
429 {
430 0x0001, /* number of serializers */
431 {Mcasp_SerializerNum_4}, /* serializer index for DAC0 */
432 &mcaspXmtSetupDAC,
433 TRUE,
434 Mcasp_OpMode_TDM,
435 Mcasp_WordLength_32, /* word width */
436 NULL,
437 0,
438 NULL,
439 GblErr,
440 2, /* number of TDM channels */
441 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
442 TRUE,
443 1, /* hwFifoEventDMARatio */
444 TRUE, /* isDataPacked */
445 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
446 };
449 /**
450 * \brief Function called by McASP driver in case of error
451 *
452 * \return None
453 */
454 void GblErr(Mcasp_errCbStatus arg)
455 {
456 gblErrFlag = 1;
457 }
460 /* DAC default configuration parameters */
461 DacConfig DAC_Cfg =
462 {
463 AUD_DAC_AMUTE_CTRL_DAC_DISABLE_CMD, /* Amute event */
464 0, /* Amute control */
465 AUD_DAC_SAMPLING_MODE_AUTO, /* Sampling mode */
466 AUD_DAC_DATA_FORMAT_I2S, /* Data format */
467 0, /* Soft mute control */
468 AUD_DAC_ATTENUATION_WIDE_RANGE, /* Attenuation mode */
469 AUD_DAC_DEEMP_DISABLE, /* De-emph control */
470 100 /* Volume */
471 };
473 /**
474 * \brief Configures audio DAC module
475 *
476 * \return none
477 */
478 void configAudioDAC(void)
479 {
480 Aud_STATUS status;
482 aud_delay(10000);
484 /* Initialize Audio DAC module */
485 status = audioDacConfig(AUD_DAC_DEVICE_ALL, &DAC_Cfg);
486 if(status != Aud_EOK)
487 {
488 //platform_write("Audio DAC Configuration Failed!\n");
489 //testRet(1);
490 }
491 }
492 #if 0
493 /**
494 * \brief Configures McASP module and creates the channel
495 * for audio Tx and Rx
496 *
497 * \return Aud_EOK on Success or error code
498 */
499 Aud_STATUS mcaspAudioConfig(void)
500 {
501 int32_t status;
503 hMcaspDevTx = NULL;
504 hMcaspDevRx = NULL;
505 hMcaspTxChan = NULL;
506 hMcaspRxChan = NULL;
508 /* Initialize McASP Tx and Rx parameters */
509 mcaspTxParams = Mcasp_PARAMS;
510 mcaspRxParams = Mcasp_PARAMS;
512 mcaspTxParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x23; // not used
513 mcaspTxParams.mcaspHwSetup.rx.clk.clkSetupClk = 0x23; // not used
514 mcaspRxParams.mcaspHwSetup.rx.clk.clkSetupClk = 0x23;
515 mcaspRxParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x63; // Asynchronous. Separate clock and frame sync used by transmit and receive sections.
517 #ifndef INPUT_SPDIF
518 mcaspRxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Special case, since for HDMI input - mcasp0 is both Rx & Tx
519 mcaspRxParams.mcaspHwSetup.glb.amute = 0x2; // this to ensure one doesn't overwrite the other (rx/tx)
520 mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
521 mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
522 #else
523 mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
524 mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
525 #endif
527 /* Set the HW interrupt number */
528 //mcaspTxParams.hwiNumber = 8;
529 //mcaspRxParams.hwiNumber = 8;
531 /* Initialize eDMA handle */
532 #ifdef INPUT_SPDIF
533 mcaspRxChanParam.edmaHandle = hEdma1;
534 #else
535 mcaspRxChanParam.edmaHandle = hEdma0;
536 #endif
538 mcaspTx0ChanParam.edmaHandle = hEdma0;
539 mcaspTx1ChanParam.edmaHandle = hEdma0;
541 #ifdef INPUT_SPDIF
542 /* Bind McASP0 for Tx */
543 status = mcaspBindDev(&hMcaspDevTx, CSL_MCASP_0, &mcaspTxParams);
544 if((status != MCASP_COMPLETED) || (hMcaspDevTx == NULL))
545 {
546 //IFPRINT(platform_write("mcaspBindDev for Tx Failed\n"));
547 return (Aud_EFAIL);
548 }
550 /* Bind McASP2 for Rx */
551 status = mcaspBindDev(&hMcaspDevRx, CSL_MCASP_2, &mcaspRxParams);
552 if((status != MCASP_COMPLETED) || (hMcaspDevRx == NULL))
553 {
554 //IFPRINT(platform_write("mcaspBindDev for Rx Failed\n"));
555 return (Aud_EFAIL);
556 }
558 #else /* HDMI or HDMI_STEREO */
559 /* Bind McASP0 for Rx and Tx */
560 status = mcaspBindDev(&hMcaspDevRx, CSL_MCASP_0, &mcaspRxParams);
561 if((status != MCASP_COMPLETED) || (hMcaspDevRx == NULL))
562 {
563 //IFPRINT(platform_write("mcaspBindDev for Rx Failed\n"));
564 return (Aud_EFAIL);
565 }
567 hMcaspDevTx = hMcaspDevRx;
568 #endif
570 /* Create McASP channel for Tx */
571 status = mcaspCreateChan(&hMcaspTxChan, hMcaspDevTx,
572 MCASP_OUTPUT,
573 #ifdef AUDIO_DAC0_TEST
574 &mcaspTx0ChanParam,
575 #else
576 &mcaspTx1ChanParam,
577 #endif
578 #ifdef IO_LOOPBACK_TEST
579 mcaspAppCallbackTx, NULL);
580 #else
581 asopMcaspCallback, NULL);
582 #endif
584 if((status != MCASP_COMPLETED) || (hMcaspTxChan == NULL))
585 {
586 //IFPRINT(platform_write("mcaspCreateChan for Tx Failed\n"));
587 return (Aud_EFAIL);
588 }
590 /* Create McASP channel for Rx */
591 status = mcaspCreateChan(&hMcaspRxChan, hMcaspDevRx,
592 MCASP_INPUT,
593 &mcaspRxChanParam,
594 #ifdef IO_LOOPBACK_TEST
595 mcaspAppCallbackRx, NULL);
596 #else
597 asipMcaspCallback, NULL);
598 #endif
600 if((status != MCASP_COMPLETED) || (hMcaspRxChan == NULL))
601 {
602 //IFPRINT(platform_write("mcaspCreateChan for Rx Failed\n"));
603 return (Aud_EFAIL);
604 }
606 return (Aud_EOK);
607 } /* mcaspAudioConfig */
610 Aud_STATUS mcaspRx(void)
611 {
613 }
615 Aud_STATUS mcaspRxDeInit(void)
616 {
617 mcaspDeleteChan(hMcaspRxChan);
618 hMcaspRxChan = NULL;
620 mcaspUnBindDev(hMcaspDevRx);
621 hMcaspDevRx = NULL;
623 return (Aud_EOK);
624 }
626 Aud_STATUS mcaspChanReset(Ptr hMcaspDev, Ptr hMcaspChan)
627 {
628 if(hMcaspChan != NULL) {
629 mcaspDeleteChan(hMcaspChan);
630 }
631 }
633 Aud_STATUS mcaspRxReset(void)
634 {
635 if(hMcaspRxChan != NULL) {
636 mcaspDeleteChan(hMcaspRxChan);
637 hMcaspRxChan = NULL;
638 }
640 return (Aud_EOK);
641 }
643 Aud_STATUS mcaspRxCreate(void)
644 {
645 int32_t status;
647 /* Create McASP channel for Rx */
648 status = mcaspCreateChan(&hMcaspRxChan, hMcaspDevRx,
649 MCASP_INPUT,
650 &mcaspRxChanParam,
651 #ifdef IO_LOOPBACK_TEST
652 mcaspAppCallbackRx, NULL);
653 #else
654 asipMcaspCallback, NULL);
655 #endif
657 if((status != MCASP_COMPLETED) || (hMcaspRxChan == NULL))
658 {
659 //IFPRINT(platform_write("mcaspCreateChan for Rx Failed\n"));
660 return (Aud_EFAIL);
661 }
663 return (Aud_EOK);
664 }
666 Aud_STATUS mcaspTxReset(void)
667 {
668 if(hMcaspTxChan != NULL) {
669 mcaspDeleteChan(hMcaspTxChan);
670 hMcaspTxChan = NULL;
671 }
673 return (Aud_EOK);
674 }
676 Aud_STATUS mcaspTxCreate(void)
677 {
678 int32_t status;
680 /* Create McASP channel for Tx */
681 status = mcaspCreateChan(&hMcaspTxChan, hMcaspDevTx,
682 MCASP_OUTPUT,
683 &mcaspTx0ChanParam,
684 #ifdef IO_LOOPBACK_TEST
685 mcaspAppCallbackTx, NULL);
686 #else
687 asopMcaspCallback, NULL);
688 #endif
689 if((status != MCASP_COMPLETED) || (hMcaspTxChan == NULL))
690 {
691 //IFPRINT(platform_write("mcaspCreateChan for Tx Failed\n"));
692 return (Aud_EFAIL);
693 }
695 return (Aud_EOK);
696 }
697 #endif
700 Aud_STATUS mcaspRecfgWordWidth(Ptr hMcaspChan, uint16_t wordWidth)
701 {
702 Mcasp_ChanParams chanParams;
703 int32_t status;
705 chanParams.wordWidth = wordWidth; //to do: change mcaspControlChan to have wordWidth as the parameter instead of chanParams!!
707 status = mcaspControlChan(hMcaspChan, Mcasp_IOCTL_CHAN_PARAMS_WORD_WIDTH, &chanParams);
709 if((status != MCASP_COMPLETED)) {
710 return (Aud_EFAIL);
711 }
712 else {
713 return (Aud_EOK);
714 }
715 } /* mcaspRecfgWordWidth */
717 /*======================================================================================
718 * This function checks if McASP Rx overruns or Tx underruns
719 *====================================================================================*/
720 int mcaspCheckOverUnderRun(Ptr mcaspChanHandle)
721 {
722 Mcasp_errCbStatus mcaspErrStat;
724 mcaspControlChan(mcaspChanHandle, Mcasp_IOCTL_CHAN_QUERY_ERROR_STATS, &mcaspErrStat);
726 return (mcaspErrStat.isRcvOvrRunOrTxUndRunErr);
727 }
730 /** McASP LLD configuration parameters for all input and output interfaces */
731 mcaspLLDconfig LLDconfigRxDIR = // for SAP_D10_RX_DIR
732 {
733 &mcaspRcvSetupDIR,
734 &mcaspRxChanParamDIR,
735 0x23,
736 0x63, // Asynchronous. Separate clock and frame sync used by transmit and receive sections.
737 0x0,
738 0x2,
739 CSL_MCASP_2,
740 MCASP_INPUT,
741 asipMcaspCallback,
742 NULL,
743 NULL
744 };
746 mcaspLLDconfig LLDconfigRxADC = // for SAP_D10_RX_ADC_44100HZ, SAP_D10_RX_ADC_88200HZ
747 {
748 &mcaspRcvSetupADC,
749 &mcaspRxChanParamADC,
750 0x23,
751 0x63,
752 0x0,
753 0x2,
754 CSL_MCASP_1,
755 MCASP_INPUT,
756 asipMcaspCallback,
757 NULL,
758 NULL
759 };
761 mcaspLLDconfig LLDconfigRxADC6ch = // for SAP_D10_RX_ADC_6CH_44100HZ, SAP_D10_RX_ADC_6CH_88200HZ
762 {
763 &mcaspRcvSetupADC,
764 &mcaspRxChanParamADC6ch,
765 0x23,
766 0x63,
767 0x0,
768 0x2,
769 CSL_MCASP_1,
770 MCASP_INPUT,
771 asipMcaspCallback,
772 NULL,
773 NULL,
774 };
776 mcaspLLDconfig LLDconfigRxADCStereo = // for SAP_D10_RX_ADC_STEREO_44100HZ, SAP_D10_RX_ADC_STEREO_88200HZ
777 {
778 &mcaspRcvSetupADC,
779 &mcaspRxChanParamADCStereo,
780 0x23,
781 0x63,
782 0x0,
783 0x2,
784 CSL_MCASP_1,
785 MCASP_INPUT,
786 asipMcaspCallback,
787 NULL,
788 NULL
789 };
791 mcaspLLDconfig LLDconfigRxHDMIStereo = // for SAP_D10_RX_HDMI_STEREO
792 {
793 &mcaspRcvSetupDIR,
794 &mcaspRxChanParamHDMIStereo,
795 0x23,
796 0x63,
797 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for DIR/HDMI
798 0x2,
799 CSL_MCASP_0,
800 MCASP_INPUT,
801 asipMcaspCallback,
802 NULL,
803 NULL
804 };
806 mcaspLLDconfig LLDconfigRxHDMI = // for SAP_D10_RX_HDMI
807 {
808 &mcaspRcvSetupDIR,
809 &mcaspRxChanParamHDMI,
810 0x23,
811 0x63,
812 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for DIR/HDMI
813 0x2,
814 CSL_MCASP_0,
815 MCASP_INPUT,
816 asipMcaspCallback,
817 NULL,
818 NULL
819 };
821 /*
822 mcaspLLDconfig LLDconfigTxDIT = // for SAP_D10_TX_DIT
823 {
824 &mcaspXmtSetupDIT,
825 &mcaspTx0ChanParamDIT,
826 NULL,
827 NULL,
828 CSL_MCASP_2
829 };
830 */
832 mcaspLLDconfig LLDconfigTxDAC = // for SAP_D10_TX_DAC
833 {
834 &mcaspXmtSetupDAC,
835 &mcaspTx0ChanParamDAC,
836 0x23,
837 0x63,
838 0x02000000, // Set Amute pin as output for Tx channel
839 0x2,
840 CSL_MCASP_0,
841 MCASP_OUTPUT,
842 asopMcaspCallback,
843 NULL,
844 NULL
845 };
847 mcaspLLDconfig LLDconfigTxDACSlave = // for SAP_D10_TX_DAC_SLAVE
848 {
849 &mcaspXmtSetupDACSlave,
850 &mcaspTx0ChanParamDAC,
851 0x23,
852 0x63,
853 0x02000000,
854 0x2,
855 CSL_MCASP_0,
856 MCASP_OUTPUT,
857 asopMcaspCallback,
858 NULL,
859 NULL
860 };
862 mcaspLLDconfig LLDconfigTxDACStereo = // for SAP_D10_TX_STEREO_DAC
863 {
864 &mcaspXmtSetupDAC,
865 &mcaspTx0ChanParamDACStereo,
866 0x23,
867 0x63,
868 0x02000000,
869 0x2,
870 CSL_MCASP_0,
871 MCASP_OUTPUT,
872 asopMcaspCallback,
873 NULL,
874 NULL
875 };
877 mcaspLLDconfig LLDconfigTxDACStereoSlave = // for SAP_D10_TX_STEREO_DAC_SLAVE
878 {
879 &mcaspXmtSetupDACSlave,
880 &mcaspTx0ChanParamDACStereo,
881 0x23,
882 0x63,
883 0x02000000,
884 0x2,
885 CSL_MCASP_0,
886 MCASP_OUTPUT,
887 asopMcaspCallback,
888 NULL,
889 NULL
890 };
892 mcaspLLDconfig LLDconfigTxDAC12ch = // for SAP_D10_TX_DAC_12CH
893 {
894 &mcaspXmtSetupDAC,
895 &mcaspTx0ChanParamDAC12ch,
896 0x23,
897 0x63,
898 0x02000000,
899 0x2,
900 CSL_MCASP_0,
901 MCASP_OUTPUT,
902 asopMcaspCallback,
903 NULL,
904 NULL
905 };
907 mcaspLLDconfig LLDconfigTxDAC16ch = // for SAP_D10_TX_DAC_16CH
908 {
909 &mcaspXmtSetupDAC,
910 &mcaspTx0ChanParamDAC16ch,
911 0x23,
912 0x63,
913 0x02000000,
914 0x2,
915 CSL_MCASP_0,
916 MCASP_OUTPUT,
917 asopMcaspCallback,
918 NULL,
919 NULL
920 };
923 /**
924 * \brief Create a channel of McASP LLD and return the handle.
925 *
926 * \return Aud_EOK on Success or error code
927 */
928 Aud_STATUS mcasplldChanCreate(mcaspLLDconfig *lldCfg, Ptr *pChanHandle)
929 {
930 int32_t status;
932 if(mcaspDevHandles[lldCfg->mcaspPort] == NULL) {
933 /* Initialize McASP parameters */
934 mcaspParams = Mcasp_PARAMS; // Mcasp_PARAMS defined in McASP LLD
936 mcaspParams.mcaspHwSetup.rx.clk.clkSetupClk = lldCfg->clkSetupClkRx;
937 mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk = lldCfg->clkSetupClkTx;
938 mcaspParams.mcaspHwSetup.glb.pdir |= lldCfg->pdirAmute;
939 mcaspParams.mcaspHwSetup.glb.amute = lldCfg->amute;
941 status = mcaspBindDev(&mcaspDevHandles[lldCfg->mcaspPort], lldCfg->mcaspPort, &mcaspParams);
942 if((status != MCASP_COMPLETED) || (mcaspDevHandles[lldCfg->mcaspPort] == NULL)) {
943 return (Aud_EFAIL);
944 }
945 }
947 lldCfg->hMcaspDev = mcaspDevHandles[lldCfg->mcaspPort];
949 lldCfg->mcaspChanParams->mcaspSetup = lldCfg->mcaspSetupData;
950 if(lldCfg->mcaspPort == CSL_MCASP_0) {
951 lldCfg->mcaspChanParams->edmaHandle = hEdma0;
952 }
953 else {
954 lldCfg->mcaspChanParams->edmaHandle = hEdma1;
955 }
957 /* Create McASP channel */
958 *pChanHandle = NULL;
959 status = mcaspCreateChan(pChanHandle, lldCfg->hMcaspDev,
960 lldCfg->chanMode, lldCfg->mcaspChanParams,
961 lldCfg->cbFxn, NULL);
963 if((status != MCASP_COMPLETED) || (*pChanHandle == NULL))
964 {
965 //IFPRINT(platform_write("mcaspCreateChan for Tx Failed\n"));
966 return (Aud_EFAIL);
967 }
969 return (Aud_EOK);
970 } /* mcasplldChanCreate */
972 /* Nothing past this point */