74a2fdcbd784d6f3732e888d44e357866c697d3a
[processor-sdk/performance-audio-sr.git] / pasdk / test_dsp / application / itopo / evmk2g / mcasp_cfg.c
1 /*
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file mcasp_config.c
36 *
37 * \brief Configures McASP module
38 *
39 */
41 #include "mcasp_cfg.h"
42 #include "ioConfig.h"
44 #define AUDIO_DAC0_TEST
46 /* McASP device handles - one for each McASP port. */
47 Ptr mcaspDevHandles[NUM_MCASP_PORTS] = {NULL, NULL, NULL};
49 /* McASP parameters needed by mcaspBindDev */
50 Mcasp_Params mcaspParams;
52 /* Error flag */
53 uint32_t gblErrFlag = 0;
54 Error_Block eb;
56 void GblErr(Mcasp_errCbStatus arg);
58 /* Handle to eDMA */
59 extern EDMA3_DRV_Handle hEdma0;
60 extern EDMA3_DRV_Handle hEdma1;
62 /* External function declarations */
63 extern void McaspDevice_init(void);
64 extern signed char* getGlobalAddr(signed char* addr);
66 #ifdef IO_LOOPBACK_TEST
67 extern void mcaspAppCallbackRx(void* arg, MCASP_Packet *mcasp_packet);
68 extern void mcaspAppCallbackTx(void* arg, MCASP_Packet *mcasp_packet);
69 #else
70 extern void asipMcaspCallback(void* arg, MCASP_Packet *mcasp_packet);
71 extern void asopMcaspCallback(void* arg, MCASP_Packet *mcasp_packet);
72 #endif
75 /* McASP HW setup for receive (ADC) */
76 Mcasp_HwSetupData mcaspRcvSetupADC = {
77 /* .rmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
78 /* .rfmt = */ 0x0001C0F0, /*
79 * 0 bit delay from framesync
80 * MSB first
81 * No extra bit padding
82 * Padding bit (ignore)
83 * slot Size is 32
84 * Reads from DMA port
85 * NO rotation
86 */
87 /* .afsrctl = */ 0X00000112, /* I2S mode - 2 slot TDM
88 * Frame sync is one word
89 * Internally generated frame sync
90 * Rising edge is start of frame
91 */
92 /* .rtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */
93 /* .rintctl = */ 0x00000000, /* sync error and overrun error */
94 /* .rstat = */ 0x000001FF, /* reset any existing status bits */
95 /* .revtctl = */ 0x00000000, /* DMA request is enabled */
96 {
97 /* .aclkrctl = */ 0x000000A7, // Receiver samples data on the rising edge of the serial clock
98 // Internal receive clock source from output of programmable bit clock divider
99 // Receive bit clock divide ratio = 8
100 /* .ahclkrctl = */ 0x00008000, // Internal receive high-frequency clock source from output of programmable high clock divider.
101 // Falling edge. AHCLKR is inverted before programmable bit clock divider.
102 /* .rclkchk = */ 0x00000000
103 }
104 };
106 /* McASP HW setup for receive (S/PDIF or HDMI)*/
107 Mcasp_HwSetupData mcaspRcvSetupDIR = {
108 MCASP_DIR_RMASK, /* .rmask: 0xFFFFFFFF */
109 MCASP_DIR_RFMT, /* .rfmt: 0x000180F0 */
110 MCASP_DIR_AFSRCTL, /* .afsrctl: 0x00000111 */
111 MCASP_DIR_RTDM, /* .rtdm: 0x00000003 */
112 MCASP_DIR_RINTCTL, /* .rintctl: 0x00000000 */
113 MCASP_DIR_RSTAT, /* .rstat: 0x000001FF */
114 MCASP_DIR_REVTCTL, /* .revtctl */
115 {
116 MCASP_DIR_ACLKRCTL, /* .aclkrctl: 0x00000080 */ // Receiver samples data on the rising edge of the serial clock
117 // External receive clock source from ACLKR pin.
118 // Receive bit clock divide ratio = 1
119 MCASP_DIR_AHCLKRCTL, /* .ahclkrctl: 0x00000000 */
120 MCASP_DIR_RCLKCHK /* .rclkchk: 0x00000000 */
121 }
122 };
124 /* McASP HW setup for transmit (DAC) */
125 Mcasp_HwSetupData mcaspXmtSetupDAC = {
126 /* .xmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
127 /* .xfmt = */ 0x000180F0, /*
128 * 1 bit delay from framesync
129 * MSB first
130 * No extra bit padding
131 * Padding bit (ignore)
132 * slot Size is 32
133 * Reads from DMA port
134 * NO rotation
135 */
136 // /* .afsxctl = */ 0x00000112, /* I2S mode - 2 slot TDM
137 // * Frame sync is one word
138 // * Rising edge is start of frame
139 // * Internally generated frame sync
140 // */
141 /* .afsxctl = */ 0x00000113, /* I2S mode - 2 slot TDM
142 * Frame sync is one word
143 * Falling edge is start of frame
144 * Internally generated frame sync
145 */
146 /* .xtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */
147 /* .xintctl = */ 0x00000000, /* sync error,overrun error,clK error */
148 /* .xstat = */ 0x000001FF, /* reset any existing status bits */
149 /* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */
150 {
151 /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2 --> works for 48khz PCM but not for DDP
152 // /* .aclkxctl = */ 0X000000E7, // Transmit bit clock divide ratio = 8 --> working for Dolby/DTS 48khz but not for PCM
153 // /* .aclkxctl = */ 0X000000E3, // Transmit bit clock divide ratio = 4 --> Dolby/DTS 96khz
154 // /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2 --> Dolby/DTS 192khz
155 /* .ahclkxctl = */ 0x00004000,
156 /* .xclkchk = */ 0x00000000
157 },
158 };
160 /* McASP HW setup for transmit (DAC slave) */
161 Mcasp_HwSetupData mcaspXmtSetupDACSlave = {
162 /* .xmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
163 /* .xfmt = */ 0x000180F0, /*
164 * 0 bit delay from framesync
165 * MSB first
166 * No extra bit padding
167 * Padding bit (ignore)
168 * slot Size is 32
169 * Reads from DMA port
170 * NO rotation
171 */
172 /* .afsxctl = */ 0x00000113, /* I2S mode - 2 slot TDM
173 * Frame sync is one word
174 * Rising edge is start of frame
175 * Internally generated frame sync
176 */
177 /* .xtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */
178 /* .xintctl = */ 0x00000000, /* sync error,overrun error,clK error */
179 /* .xstat = */ 0x000001FF, /* reset any existing status bits */
180 /* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */
181 {
182 /* .aclkxctl = */ 0X000000A7,
183 /* .ahclkxctl = */ 0x0000C000,
184 /* .xclkchk = */ 0x00000000
185 },
186 };
188 /* McASP channel parameters for ADC input */
189 Mcasp_ChanParams mcaspRxChanParamADC =
190 {
191 0x0004, /* number of serializers */
192 {Mcasp_SerializerNum_0,
193 Mcasp_SerializerNum_1,
194 Mcasp_SerializerNum_2,
195 Mcasp_SerializerNum_3 }, /* serializer index */
196 &mcaspRcvSetupADC,
197 TRUE, /* isDmaDriven */
198 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
199 Mcasp_WordLength_32, /* wordWidth */
200 NULL, /* void * userLoopJobBuffer */
201 0, /* userLoopJobLength */
202 NULL, /* edmaHandle */
203 GblErr,
204 2, /* number of TDM channels */
205 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
206 TRUE, /* enableHwFifo */
207 1, /* hwFifoEventDMARatio */
208 TRUE, /* isDataPacked */
209 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
210 };
212 /* McASP channel parameters for ADC 6 channel input */
213 Mcasp_ChanParams mcaspRxChanParamADC6ch =
214 {
215 0x0003, /* number of serializers */
216 {Mcasp_SerializerNum_0,
217 Mcasp_SerializerNum_1,
218 Mcasp_SerializerNum_2}, /* serializer index */
219 &mcaspRcvSetupADC,
220 TRUE,
221 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
222 Mcasp_WordLength_32,
223 NULL,
224 0,
225 NULL,
226 GblErr,
227 2, /* number of TDM channels */
228 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
229 TRUE, /* enableHwFifo */
230 1, /* hwFifoEventDMARatio */
231 TRUE, /* isDataPacked */
232 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
233 };
235 /* McASP channel parameters for ADC stereo input */
236 Mcasp_ChanParams mcaspRxChanParamADCStereo =
237 {
238 0x0001, /* number of serializers */
239 {Mcasp_SerializerNum_0}, /* serializer index */
240 &mcaspRcvSetupADC,
241 TRUE,
242 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
243 Mcasp_WordLength_32,
244 NULL,
245 0,
246 NULL,
247 GblErr,
248 2, /* number of TDM channels */
249 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
250 TRUE, /* enableHwFifo */
251 1, /* hwFifoEventDMARatio */
252 TRUE, /* isDataPacked */
253 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
254 };
256 /* McAsp channel parameters for DIR input */
257 Mcasp_ChanParams mcaspRxChanParamDIR =
258 {
259 0x0001, /* Number of serializers */
260 {Mcasp_SerializerNum_5}, /* Serializer index */
261 &mcaspRcvSetupDIR,
262 TRUE,
263 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
264 Mcasp_WordLength_16, /* 16-bit by default */
265 NULL,
266 0,
267 NULL,
268 GblErr,
269 2, /* number of TDM channels */
270 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
271 TRUE,
272 1, /* hwFifoEventDMARatio */
273 TRUE, /* isDataPacked */
274 Mcasp_WordBitsSelect_MSB /* wordBitsSelect */
275 };
277 /* McASP LLD channel parameters for HDMI input with 4XI2S:
278 * When slot size of McASP is configured to 32-bit, HDMI data always come to 16 MSBs of the slot
279 * and the 16 LSBs are filled with 0's. This is the nature of HDMI and I2S.
280 * For PCM data, we want all 32 bits in the slot to be transferred to the input buffer:
281 * - wordWidth = Mcasp_WordLength_32
282 * - isDataPacked = 1,
283 * - wordBitsSelect having no effect since wordWidth = slot size
284 * For bit stream, we want only 16 MSBs in the slot to be transferred to the input buffer:
285 * - wordWidth = Mcasp_WordLength_16
286 * - isDataPacked = 1,
287 * - wordBitsSelect = Mcasp_WordBitsSelect_MSB
288 */
289 Mcasp_ChanParams mcaspRxChanParamHDMI =
290 {
291 0x0004, /* number of serializers */
292 {Mcasp_SerializerNum_12,
293 Mcasp_SerializerNum_13,
294 Mcasp_SerializerNum_14,
295 Mcasp_SerializerNum_15 }, /* serializer index */
296 &mcaspRcvSetupDIR,
297 TRUE,
298 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
299 Mcasp_WordLength_16, /* 16-bit word length, MSB or LSB of slot to be transfered, depending on wordBitsSelect */
300 NULL,
301 0,
302 NULL,
303 GblErr,
304 2, /* number of TDM channels */
305 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
306 TRUE, /* enableHwFifo */
307 1, /* hwFifoEventDMARatio */
308 TRUE, /* isDataPacked, only transfer the selected bits of slot, based on wordWidth and wordBitsSelect */
309 Mcasp_WordBitsSelect_MSB /* wordBitsSelect, only matters if wordWidth < slot size */
310 };
312 /* McAsp channel parameters for HDMI stereo input with 1XI2S */
313 Mcasp_ChanParams mcaspRxChanParamHDMIStereo =
314 {
315 0x0001, /* Number of serializers */
316 {Mcasp_SerializerNum_12}, /* Serializer index */
317 &mcaspRcvSetupDIR,
318 TRUE,
319 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
320 Mcasp_WordLength_16, /* 16-bit by default */
321 NULL,
322 0,
323 NULL,
324 GblErr,
325 2, /* number of TDM channels */
326 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
327 TRUE, /* enableHwFifo */
328 1, /* hwFifoEventDMARatio */
329 TRUE, /* isDataPacked */
330 Mcasp_WordBitsSelect_MSB /* wordBitsSelect */
331 };
333 /* McAsp channel parameters for DAC output - DAC0 */
334 Mcasp_ChanParams mcaspTx0ChanParamDAC =
335 {
336 0x0004, /* number of serializers */
337 {Mcasp_SerializerNum_0,
338 Mcasp_SerializerNum_1,
339 Mcasp_SerializerNum_2,
340 Mcasp_SerializerNum_3 }, /* serializer index for DAC0 */
341 &mcaspXmtSetupDAC,
342 TRUE,
343 Mcasp_OpMode_TDM,
344 Mcasp_WordLength_32, /* word width */
345 NULL,
346 0,
347 NULL,
348 GblErr,
349 2, /* number of TDM channels */
350 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
351 TRUE,
352 1, /* hwFifoEventDMARatio */
353 TRUE, /* isDataPacked */
354 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
355 };
357 /* McAsp channel parameters for DAC stereo output - DAC0 */
358 Mcasp_ChanParams mcaspTx0ChanParamDACStereo =
359 {
360 0x0001, /* number of serializers */
361 {Mcasp_SerializerNum_0}, /* serializer index for DAC0 */
362 &mcaspXmtSetupDAC,
363 TRUE,
364 Mcasp_OpMode_TDM,
365 Mcasp_WordLength_32, /* word width */
366 NULL,
367 0,
368 NULL,
369 GblErr,
370 2, /* number of TDM channels */
371 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
372 TRUE,
373 1, /* hwFifoEventDMARatio */
374 TRUE, /* isDataPacked */
375 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
376 };
378 /* McAsp channel parameters for DAC 12 channel output */
379 Mcasp_ChanParams mcaspTx0ChanParamDAC12ch =
380 {
381 0x0006, /* number of serializers */
382 {Mcasp_SerializerNum_0,
383 Mcasp_SerializerNum_1,
384 Mcasp_SerializerNum_2,
385 Mcasp_SerializerNum_3,
386 Mcasp_SerializerNum_4,
387 Mcasp_SerializerNum_5 }, /* serializer index for DAC0 */
388 &mcaspXmtSetupDAC,
389 TRUE,
390 Mcasp_OpMode_TDM,
391 Mcasp_WordLength_32, /* word width */
392 NULL,
393 0,
394 NULL,
395 GblErr,
396 2, /* number of TDM channels */
397 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
398 TRUE,
399 1, /* hwFifoEventDMARatio */
400 TRUE, /* isDataPacked */
401 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
402 };
404 /* McAsp channel parameters for DAC 16 channel output */
405 Mcasp_ChanParams mcaspTx0ChanParamDAC16ch =
406 {
407 0x0008, /* number of serializers */
408 {Mcasp_SerializerNum_0,
409 Mcasp_SerializerNum_1,
410 Mcasp_SerializerNum_2,
411 Mcasp_SerializerNum_3,
412 Mcasp_SerializerNum_4,
413 Mcasp_SerializerNum_5,
414 Mcasp_SerializerNum_6,
415 Mcasp_SerializerNum_7 }, /* serializer index for DAC0 */
416 &mcaspXmtSetupDAC,
417 TRUE,
418 Mcasp_OpMode_TDM,
419 Mcasp_WordLength_32, /* word width */
420 NULL,
421 0,
422 NULL,
423 GblErr,
424 2, /* number of TDM channels */
425 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
426 TRUE,
427 1, /* hwFifoEventDMARatio */
428 TRUE, /* isDataPacked */
429 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
430 };
432 /* McAsp channel parameters for transmit - DAC1 */
433 Mcasp_ChanParams mcaspTx1ChanParam =
434 {
435 0x0001, /* number of serializers */
436 {Mcasp_SerializerNum_4}, /* serializer index for DAC0 */
437 &mcaspXmtSetupDAC,
438 TRUE,
439 Mcasp_OpMode_TDM,
440 Mcasp_WordLength_32, /* word width */
441 NULL,
442 0,
443 NULL,
444 GblErr,
445 2, /* number of TDM channels */
446 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
447 TRUE,
448 1, /* hwFifoEventDMARatio */
449 TRUE, /* isDataPacked */
450 Mcasp_WordBitsSelect_LSB /* wordBitsSelect */
451 };
454 /**
455 * \brief Function called by McASP driver in case of error
456 *
457 * \return None
458 */
459 void GblErr(Mcasp_errCbStatus arg)
460 {
461 gblErrFlag = 1;
462 }
465 /* DAC default configuration parameters */
466 DacConfig DAC_Cfg =
467 {
468 AUD_DAC_AMUTE_CTRL_DAC_DISABLE_CMD, /* Amute event */
469 0, /* Amute control */
470 AUD_DAC_SAMPLING_MODE_AUTO, /* Sampling mode */
471 AUD_DAC_DATA_FORMAT_I2S, /* Data format */
472 0, /* Soft mute control */
473 AUD_DAC_ATTENUATION_WIDE_RANGE, /* Attenuation mode */
474 AUD_DAC_DEEMP_DISABLE, /* De-emph control */
475 100 /* Volume */
476 };
478 /**
479 * \brief Configures audio DAC module
480 *
481 * \return none
482 */
483 void configAudioDAC(void)
484 {
485 Aud_STATUS status;
487 aud_delay(10000);
489 /* Initialize Audio DAC module */
490 status = audioDacConfig(AUD_DAC_DEVICE_ALL, &DAC_Cfg);
491 if(status != Aud_EOK)
492 {
493 //platform_write("Audio DAC Configuration Failed!\n");
494 //testRet(1);
495 }
496 }
497 #if 0
498 /**
499 * \brief Configures McASP module and creates the channel
500 * for audio Tx and Rx
501 *
502 * \return Aud_EOK on Success or error code
503 */
504 Aud_STATUS mcaspAudioConfig(void)
505 {
506 int32_t status;
508 hMcaspDevTx = NULL;
509 hMcaspDevRx = NULL;
510 hMcaspTxChan = NULL;
511 hMcaspRxChan = NULL;
513 /* Initialize McASP Tx and Rx parameters */
514 mcaspTxParams = Mcasp_PARAMS;
515 mcaspRxParams = Mcasp_PARAMS;
517 mcaspTxParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x23; // not used
518 mcaspTxParams.mcaspHwSetup.rx.clk.clkSetupClk = 0x23; // not used
519 mcaspRxParams.mcaspHwSetup.rx.clk.clkSetupClk = 0x23;
520 mcaspRxParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x63; // Asynchronous. Separate clock and frame sync used by transmit and receive sections.
522 #ifndef INPUT_SPDIF
523 mcaspRxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Special case, since for HDMI input - mcasp0 is both Rx & Tx
524 mcaspRxParams.mcaspHwSetup.glb.amute = 0x2; // this to ensure one doesn't overwrite the other (rx/tx)
525 mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
526 mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
527 #else
528 mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
529 mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
530 #endif
532 /* Set the HW interrupt number */
533 //mcaspTxParams.hwiNumber = 8;
534 //mcaspRxParams.hwiNumber = 8;
536 /* Initialize eDMA handle */
537 #ifdef INPUT_SPDIF
538 mcaspRxChanParam.edmaHandle = hEdma1;
539 #else
540 mcaspRxChanParam.edmaHandle = hEdma0;
541 #endif
543 mcaspTx0ChanParam.edmaHandle = hEdma0;
544 mcaspTx1ChanParam.edmaHandle = hEdma0;
546 #ifdef INPUT_SPDIF
547 /* Bind McASP0 for Tx */
548 status = mcaspBindDev(&hMcaspDevTx, CSL_MCASP_0, &mcaspTxParams);
549 if((status != MCASP_COMPLETED) || (hMcaspDevTx == NULL))
550 {
551 //IFPRINT(platform_write("mcaspBindDev for Tx Failed\n"));
552 return (Aud_EFAIL);
553 }
555 /* Bind McASP2 for Rx */
556 status = mcaspBindDev(&hMcaspDevRx, CSL_MCASP_2, &mcaspRxParams);
557 if((status != MCASP_COMPLETED) || (hMcaspDevRx == NULL))
558 {
559 //IFPRINT(platform_write("mcaspBindDev for Rx Failed\n"));
560 return (Aud_EFAIL);
561 }
563 #else /* HDMI or HDMI_STEREO */
564 /* Bind McASP0 for Rx and Tx */
565 status = mcaspBindDev(&hMcaspDevRx, CSL_MCASP_0, &mcaspRxParams);
566 if((status != MCASP_COMPLETED) || (hMcaspDevRx == NULL))
567 {
568 //IFPRINT(platform_write("mcaspBindDev for Rx Failed\n"));
569 return (Aud_EFAIL);
570 }
572 hMcaspDevTx = hMcaspDevRx;
573 #endif
575 /* Create McASP channel for Tx */
576 status = mcaspCreateChan(&hMcaspTxChan, hMcaspDevTx,
577 MCASP_OUTPUT,
578 #ifdef AUDIO_DAC0_TEST
579 &mcaspTx0ChanParam,
580 #else
581 &mcaspTx1ChanParam,
582 #endif
583 #ifdef IO_LOOPBACK_TEST
584 mcaspAppCallbackTx, NULL);
585 #else
586 asopMcaspCallback, NULL);
587 #endif
589 if((status != MCASP_COMPLETED) || (hMcaspTxChan == NULL))
590 {
591 //IFPRINT(platform_write("mcaspCreateChan for Tx Failed\n"));
592 return (Aud_EFAIL);
593 }
595 /* Create McASP channel for Rx */
596 status = mcaspCreateChan(&hMcaspRxChan, hMcaspDevRx,
597 MCASP_INPUT,
598 &mcaspRxChanParam,
599 #ifdef IO_LOOPBACK_TEST
600 mcaspAppCallbackRx, NULL);
601 #else
602 asipMcaspCallback, NULL);
603 #endif
605 if((status != MCASP_COMPLETED) || (hMcaspRxChan == NULL))
606 {
607 //IFPRINT(platform_write("mcaspCreateChan for Rx Failed\n"));
608 return (Aud_EFAIL);
609 }
611 return (Aud_EOK);
612 } /* mcaspAudioConfig */
615 Aud_STATUS mcaspRx(void)
616 {
618 }
620 Aud_STATUS mcaspRxDeInit(void)
621 {
622 mcaspDeleteChan(hMcaspRxChan);
623 hMcaspRxChan = NULL;
625 mcaspUnBindDev(hMcaspDevRx);
626 hMcaspDevRx = NULL;
628 return (Aud_EOK);
629 }
631 Aud_STATUS mcaspChanReset(Ptr hMcaspDev, Ptr hMcaspChan)
632 {
633 if(hMcaspChan != NULL) {
634 mcaspDeleteChan(hMcaspChan);
635 }
636 }
638 Aud_STATUS mcaspRxReset(void)
639 {
640 if(hMcaspRxChan != NULL) {
641 mcaspDeleteChan(hMcaspRxChan);
642 hMcaspRxChan = NULL;
643 }
645 return (Aud_EOK);
646 }
648 Aud_STATUS mcaspRxCreate(void)
649 {
650 int32_t status;
652 /* Create McASP channel for Rx */
653 status = mcaspCreateChan(&hMcaspRxChan, hMcaspDevRx,
654 MCASP_INPUT,
655 &mcaspRxChanParam,
656 #ifdef IO_LOOPBACK_TEST
657 mcaspAppCallbackRx, NULL);
658 #else
659 asipMcaspCallback, NULL);
660 #endif
662 if((status != MCASP_COMPLETED) || (hMcaspRxChan == NULL))
663 {
664 //IFPRINT(platform_write("mcaspCreateChan for Rx Failed\n"));
665 return (Aud_EFAIL);
666 }
668 return (Aud_EOK);
669 }
671 Aud_STATUS mcaspTxReset(void)
672 {
673 if(hMcaspTxChan != NULL) {
674 mcaspDeleteChan(hMcaspTxChan);
675 hMcaspTxChan = NULL;
676 }
678 return (Aud_EOK);
679 }
681 Aud_STATUS mcaspTxCreate(void)
682 {
683 int32_t status;
685 /* Create McASP channel for Tx */
686 status = mcaspCreateChan(&hMcaspTxChan, hMcaspDevTx,
687 MCASP_OUTPUT,
688 &mcaspTx0ChanParam,
689 #ifdef IO_LOOPBACK_TEST
690 mcaspAppCallbackTx, NULL);
691 #else
692 asopMcaspCallback, NULL);
693 #endif
694 if((status != MCASP_COMPLETED) || (hMcaspTxChan == NULL))
695 {
696 //IFPRINT(platform_write("mcaspCreateChan for Tx Failed\n"));
697 return (Aud_EFAIL);
698 }
700 return (Aud_EOK);
701 }
702 #endif
705 Aud_STATUS mcaspRecfgWordWidth(Ptr hMcaspChan, uint16_t wordWidth)
706 {
707 Mcasp_ChanParams chanParams;
708 int32_t status;
710 chanParams.wordWidth = wordWidth; //to do: change mcaspControlChan to have wordWidth as the parameter instead of chanParams!!
712 status = mcaspControlChan(hMcaspChan, Mcasp_IOCTL_CHAN_PARAMS_WORD_WIDTH, &chanParams);
714 if((status != MCASP_COMPLETED)) {
715 return (Aud_EFAIL);
716 }
717 else {
718 return (Aud_EOK);
719 }
720 } /* mcaspRecfgWordWidth */
722 /*======================================================================================
723 * This function checks if McASP Rx overruns or Tx underruns
724 *====================================================================================*/
725 int mcaspCheckOverUnderRun(Ptr mcaspChanHandle)
726 {
727 Mcasp_errCbStatus mcaspErrStat;
729 mcaspControlChan(mcaspChanHandle, Mcasp_IOCTL_CHAN_QUERY_ERROR_STATS, &mcaspErrStat);
731 return (mcaspErrStat.isRcvOvrRunOrTxUndRunErr);
732 }
735 /** McASP LLD configuration parameters for all input and output interfaces */
736 mcaspLLDconfig LLDconfigRxDIR = // for SAP_D10_RX_DIR
737 {
738 &mcaspRcvSetupDIR,
739 &mcaspRxChanParamDIR,
740 0x23,
741 0x63, // Asynchronous. Separate clock and frame sync used by transmit and receive sections.
742 0x0,
743 0x2,
744 CSL_MCASP_2,
745 MCASP_INPUT,
746 asipMcaspCallback,
747 NULL,
748 NULL
749 };
751 mcaspLLDconfig LLDconfigRxADC = // for SAP_D10_RX_ADC_44100HZ, SAP_D10_RX_ADC_88200HZ
752 {
753 &mcaspRcvSetupADC,
754 &mcaspRxChanParamADC,
755 0x23,
756 0x63,
757 0x0,
758 0x2,
759 CSL_MCASP_1,
760 MCASP_INPUT,
761 asipMcaspCallback,
762 NULL,
763 NULL
764 };
766 mcaspLLDconfig LLDconfigRxADC6ch = // for SAP_D10_RX_ADC_6CH_44100HZ, SAP_D10_RX_ADC_6CH_88200HZ
767 {
768 &mcaspRcvSetupADC,
769 &mcaspRxChanParamADC6ch,
770 0x23,
771 0x63,
772 0x0,
773 0x2,
774 CSL_MCASP_1,
775 MCASP_INPUT,
776 asipMcaspCallback,
777 NULL,
778 NULL,
779 };
781 mcaspLLDconfig LLDconfigRxADCStereo = // for SAP_D10_RX_ADC_STEREO_44100HZ, SAP_D10_RX_ADC_STEREO_88200HZ
782 {
783 &mcaspRcvSetupADC,
784 &mcaspRxChanParamADCStereo,
785 0x23,
786 0x63,
787 0x0,
788 0x2,
789 CSL_MCASP_1,
790 MCASP_INPUT,
791 asipMcaspCallback,
792 NULL,
793 NULL
794 };
796 mcaspLLDconfig LLDconfigRxHDMIStereo = // for SAP_D10_RX_HDMI_STEREO
797 {
798 &mcaspRcvSetupDIR,
799 &mcaspRxChanParamHDMIStereo,
800 0x23,
801 0x63,
802 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for HDMI
803 0x2,
804 CSL_MCASP_0,
805 MCASP_INPUT,
806 asipMcaspCallback,
807 NULL,
808 NULL
809 };
811 mcaspLLDconfig LLDconfigRxHDMI = // for SAP_D10_RX_HDMI
812 {
813 &mcaspRcvSetupDIR,
814 &mcaspRxChanParamHDMI,
815 0x23,
816 0x63,
817 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for HDMI
818 0x2,
819 CSL_MCASP_0,
820 MCASP_INPUT,
821 asipMcaspCallback,
822 NULL,
823 NULL
824 };
826 /*
827 mcaspLLDconfig LLDconfigTxDIT = // for SAP_D10_TX_DIT
828 {
829 &mcaspXmtSetupDIT,
830 &mcaspTx0ChanParamDIT,
831 NULL,
832 NULL,
833 CSL_MCASP_2
834 };
835 */
837 mcaspLLDconfig LLDconfigTxDAC = // for SAP_D10_TX_DAC
838 {
839 &mcaspXmtSetupDAC,
840 &mcaspTx0ChanParamDAC,
841 0x23,
842 0x63,
843 0x02000000, // Set Amute pin as output for Tx channel
844 0x2,
845 CSL_MCASP_0,
846 MCASP_OUTPUT,
847 asopMcaspCallback,
848 NULL,
849 NULL
850 };
852 mcaspLLDconfig LLDconfigTxDACSlave = // for SAP_D10_TX_DAC_SLAVE
853 {
854 &mcaspXmtSetupDACSlave,
855 &mcaspTx0ChanParamDAC,
856 0x23,
857 0x63,
858 0x02000000,
859 0x2,
860 CSL_MCASP_0,
861 MCASP_OUTPUT,
862 asopMcaspCallback,
863 NULL,
864 NULL
865 };
867 mcaspLLDconfig LLDconfigTxDACStereo = // for SAP_D10_TX_STEREO_DAC
868 {
869 &mcaspXmtSetupDAC,
870 &mcaspTx0ChanParamDACStereo,
871 0x23,
872 0x63,
873 0x02000000,
874 0x2,
875 CSL_MCASP_0,
876 MCASP_OUTPUT,
877 asopMcaspCallback,
878 NULL,
879 NULL
880 };
882 mcaspLLDconfig LLDconfigTxDACStereoSlave = // for SAP_D10_TX_STEREO_DAC_SLAVE
883 {
884 &mcaspXmtSetupDACSlave,
885 &mcaspTx0ChanParamDACStereo,
886 0x23,
887 0x63,
888 0x02000000,
889 0x2,
890 CSL_MCASP_0,
891 MCASP_OUTPUT,
892 asopMcaspCallback,
893 NULL,
894 NULL
895 };
897 mcaspLLDconfig LLDconfigTxDAC12ch = // for SAP_D10_TX_DAC_12CH
898 {
899 &mcaspXmtSetupDAC,
900 &mcaspTx0ChanParamDAC12ch,
901 0x23,
902 0x63,
903 0x02000000,
904 0x2,
905 CSL_MCASP_0,
906 MCASP_OUTPUT,
907 asopMcaspCallback,
908 NULL,
909 NULL
910 };
912 mcaspLLDconfig LLDconfigTxDAC16ch = // for SAP_D10_TX_DAC_16CH
913 {
914 &mcaspXmtSetupDAC,
915 &mcaspTx0ChanParamDAC16ch,
916 0x23,
917 0x63,
918 0x02000000,
919 0x2,
920 CSL_MCASP_0,
921 MCASP_OUTPUT,
922 asopMcaspCallback,
923 NULL,
924 NULL
925 };
928 /**
929 * \brief Create a channel of McASP LLD and return the handle.
930 *
931 * \return Aud_EOK on Success or error code
932 */
933 Aud_STATUS mcasplldChanCreate(mcaspLLDconfig *lldCfg, Ptr *pChanHandle)
934 {
935 int32_t status;
937 if(mcaspDevHandles[lldCfg->mcaspPort] == NULL) {
938 /* Initialize McASP parameters */
939 mcaspParams = Mcasp_PARAMS; // Mcasp_PARAMS defined in McASP LLD
941 mcaspParams.mcaspHwSetup.rx.clk.clkSetupClk = lldCfg->clkSetupClkRx;
942 mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk = lldCfg->clkSetupClkTx;
943 mcaspParams.mcaspHwSetup.glb.pdir |= lldCfg->pdirAmute;
944 mcaspParams.mcaspHwSetup.glb.amute = lldCfg->amute;
946 status = mcaspBindDev(&mcaspDevHandles[lldCfg->mcaspPort], lldCfg->mcaspPort, &mcaspParams);
947 if((status != MCASP_COMPLETED) || (mcaspDevHandles[lldCfg->mcaspPort] == NULL)) {
948 return (Aud_EFAIL);
949 }
950 }
952 lldCfg->hMcaspDev = mcaspDevHandles[lldCfg->mcaspPort];
954 lldCfg->mcaspChanParams->mcaspSetup = lldCfg->mcaspSetupData;
955 if(lldCfg->mcaspPort == CSL_MCASP_0) {
956 lldCfg->mcaspChanParams->edmaHandle = hEdma0;
957 }
958 else {
959 lldCfg->mcaspChanParams->edmaHandle = hEdma1;
960 }
962 /* Create McASP channel */
963 *pChanHandle = NULL;
964 status = mcaspCreateChan(pChanHandle, lldCfg->hMcaspDev,
965 lldCfg->chanMode, lldCfg->mcaspChanParams,
966 lldCfg->cbFxn, NULL);
968 if((status != MCASP_COMPLETED) || (*pChanHandle == NULL))
969 {
970 //IFPRINT(platform_write("mcaspCreateChan for Tx Failed\n"));
971 return (Aud_EFAIL);
972 }
974 return (Aud_EOK);
975 } /* mcasplldChanCreate */
978 /* Nothing past this point */