5cb33ef1679045534541050c415dd195479eb476
[processor-sdk/performance-audio-sr.git] / pasdk / test_dsp / application / itopo / evmk2g / mcasp_cfg.h
1 /*
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file mcasp_config.h
36 *
37 * \brief McASP configuration header file
38 *
39 */
41 #ifndef _MCASP_CONFIG_H_
42 #define _MCASP_CONFIG_H_
44 #include <xdc/std.h>
45 #include <xdc/runtime/Memory.h>
46 #include <xdc/runtime/IHeap.h>
47 #include <xdc/runtime/Error.h>
48 #include <xdc/runtime/Log.h>
49 #include <xdc/runtime/System.h>
51 #include <ti/sysbios/io/GIO.h>
52 #include <ti/sysbios/io/IOM.h>
53 #include <ti/sysbios/heaps/HeapMem.h>
54 #include <ti/sysbios/BIOS.h>
55 #include <ti/sysbios/knl/Semaphore.h>
56 #include <ti/sdo/edma3/drv/edma3_drv.h>
57 #include <ti/sysbios/knl/Task.h>
58 #include <ti/sysbios/hal/Cache.h>
59 #include <ti/sysbios/family/c64p/Hwi.h>
61 #include <stdio.h>
63 #include <mcasp_drv.h>
65 #include "audio_dc_cfg.h"
66 #include "edma_cfg.h"
68 /**
69 * \brief McASP configurations for Rx - DIR
70 */
71 /** Receive format unit bit mask register defult value */
72 #define MCASP_DIR_RMASK (0xFFFFFFFF)
74 /** Receive bit stream format register defult value */
75 #define MCASP_DIR_RFMT ( ( 1 << 16) /* RDATDLY: Transmit with 1 bit delay */ \
76 | ( 1 << 15) /* RXRVRS : MSB first */ \
77 | ( 0 << 13) /* RPAD : Pad extra bits with 0 */ \
78 | (15 << 4) /* RSSZ : 32-bit slot size */ \
79 | ( 0 << 3) /* RBUSSEL: Reads from edma port */ \
80 | ( 0 << 0)) /* RROT : No rotation */
82 /** Receive frame sync control register defult value */
83 #define MCASP_DIR_AFSRCTL ( (2 << 7) /* RMOD : 2-slot TDM */ \
84 | (1 << 4) /* FRWID: Single word frame sync */ \
85 | (0 << 1) /* FSRM : Externally-generated rx frame sync */ \
86 | (1 << 0)) /* FSRP : Start on falling edge */
88 /** Receive TDM time slot 0-31 register defult value */
89 #define MCASP_DIR_RTDM (0x00000003)
91 /** Receive interrupt control register defult value */
92 #define MCASP_DIR_RINTCTL (0x00000000)
94 /** Receive status register defult value */
95 #define MCASP_DIR_RSTAT (0x000001FF)
97 /** Receive DMA event control register defult value */
98 #define MCASP_DIR_REVTCTL (0x00000000)
100 /** Receive clock control register defult value */
101 #define MCASP_DIR_ACLKRCTL ( (1 << 7) /* CLKRP : RX on raising edge */ \
102 | (0 << 5) /* CLKRM : Externally generated ACLK */ \
103 | (0 << 0)) /* CLKRDIV: NA */
105 /** Receive high-frequency clock control register defult value */
106 #define MCASP_DIR_AHCLKRCTL ( (0 << 15) /* HCLKRM : Clock from AHCLKR pin */ \
107 | (0 << 14) /* HCLKRP : Falling edge */ \
108 | (0x400 << 0)) /* HCLKRDIV: AHCLKR = AUXCLK / 1 */
110 /** Receive clock check control register defult value */
111 #define MCASP_DIR_RCLKCHK (0x00000000)
113 /**
114 * \brief Configures McASP module and creates the channel
115 * for audio Tx and Rx
116 *
117 * \return Platform_EOK on Success or error code
118 */
119 Audk2g_STATUS mcaspAudioConfig(void);
121 Audk2g_STATUS mcaspTxCreate(void);
122 Audk2g_STATUS mcaspTxReset(void);
123 Audk2g_STATUS mcaspRxCreate(void);
124 Audk2g_STATUS mcaspRxReset(void);
126 #endif /* _MCASP_CONFIG_H_ */