fb4f2c7214370beb0408093097cf59735207fdfd
[processor-sdk/performance-audio-sr.git] / pasdk / test_dsp / application / itopo / evmk2g / sample_k2g_int_reg.c
2 /*
3 Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
4 All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
36 /*
37 * sample_k2g_int_reg.c
38 *
39 * Platform specific interrupt registration and un-registration routines.
40 */
42 #include <ti/sysbios/knl/Semaphore.h>
43 #include <ti/sysbios/hal/Hwi.h>
44 #include <ti/sysbios/family/c64p/EventCombiner.h>
45 #include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
47 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
49 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
50 extern unsigned int ccErrorInt[];
51 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
52 extern unsigned int numEdma3Tc[];
54 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
55 {
56 &lisrEdma3TC0ErrHandler0,
57 &lisrEdma3TC1ErrHandler0,
58 &lisrEdma3TC2ErrHandler0,
59 &lisrEdma3TC3ErrHandler0,
60 &lisrEdma3TC4ErrHandler0,
61 &lisrEdma3TC5ErrHandler0,
62 &lisrEdma3TC6ErrHandler0,
63 &lisrEdma3TC7ErrHandler0,
64 };
65 #if 0
66 unsigned int hwiInterrupt = 8;
68 /* Host interrupts for transfer completion */
69 //unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
70 unsigned int ccXferHostInt[3][4] = {
71 {32, 24u, 40u, 56u},
72 {9u, 25u, 41u, 57u},
73 {10u, 26u, 42u, 58u},
74 };
75 unsigned int edma3ErrHostInt[3][4] = {
76 {33, 27u, 43u, 59u},
77 {12u, 28u, 44u, 60u},
78 {13u, 29u, 45u, 61u},
79 };
82 extern unsigned int dsp_num;
84 /** To Register the ISRs with the underlying OS, if required */
85 void registerEdma3Interrupts (unsigned int edma3Id)
86 {
87 static UInt32 cookie = 0;
88 Int eventId = 0; /* GEM event id */
89 unsigned int numTc = 0;
91 /* Disabling the global interrupts */
92 cookie = Hwi_disable();
94 /* Transfer completion ISR */
95 #if 1
96 CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
97 lisrEdma3ComplHandler0,
98 edma3Id,
99 TRUE);
100 CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],
101 ccXferHostInt[edma3Id][dsp_num]);
102 CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
103 #else
104 // Map system interrupt 15 to host interrupt 8
105 CpIntc_mapSysIntToHostInt(0, 136, 6);
107 // Plug the function for event #15
108 CpIntc_dispatchPlug(136, lisrEdma3ComplHandler0,edma3Id,TRUE);
110 // Enable host interrupt #8
111 CpIntc_enableHostInt(0,6); // enable host interrupt 8
112 #endif
113 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
114 eventId = 0x30;
115 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
116 ccXferHostInt[edma3Id][dsp_num], TRUE);
117 EventCombiner_enableEvent(eventId);
119 /* CC Error ISR */
120 CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
121 edma3Id, TRUE);
122 CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id],
123 edma3ErrHostInt[edma3Id][dsp_num]);
124 /* TC Error ISR */
125 while (numTc < numEdma3Tc[edma3Id])
126 {
127 CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
128 (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
129 edma3Id, TRUE);
130 CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc],
131 edma3ErrHostInt[edma3Id][dsp_num]);
132 numTc++;
133 }
134 /* Enable the host interrupt which is common for both CC and TC error */
135 CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
136 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
137 eventId = 0x31;
138 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
139 edma3ErrHostInt[edma3Id][dsp_num], TRUE);
140 EventCombiner_enableEvent(eventId);
142 Hwi_enableInterrupt(hwiInterrupt);
144 /* enable the 'global' switch */
145 CpIntc_enableAllHostInts(0);
146 {
147 Hwi_Params params;
148 CpIntc_mapSysIntToHostInt(0, 0x88, 32); // I picked host int 32 for CPINTC #0. CPINTC #1 is for cores 4-7
149 CpIntc_dispatchPlug(0x88, lisrEdma3ComplHandler0, 0, TRUE); // the 'arg' parameter could be anything, doesn't have to be 149
150 CpIntc_enableHostInt(0, 32); // CPINT #0 is for cores 0-3, CPINTC #1 is for cores 4-7
151 eventId = CpIntc_getEventId(32); // this should return the GEM event 21 (This was a bug fixed in 6.32.04)
152 eventId = 0x30;
153 Hwi_Params_init(¶ms);
154 params.arg = 32; // required to be the host interrupt #
155 params.eventId = eventId;
156 params.enableInt = TRUE;
157 Hwi_create(6, &CpIntc_dispatch, ¶ms, NULL); // create ISR to handle this event in Hwi vector 4
159 }
161 /* Restore interrupts */
162 Hwi_restore(cookie);
163 }
165 /** To Unregister the ISRs with the underlying OS, if previously registered. */
166 void unregisterEdma3Interrupts (unsigned int edma3Id)
167 {
168 static UInt32 cookie = 0;
169 Int eventId = 0; /* GEM event id */
171 /* Disabling the global interrupts */
172 cookie = Hwi_disable();
174 /* Transfer completion ISR */
175 CpIntc_disableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
176 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
177 EventCombiner_disableEvent(eventId);
179 /* CC/TC Error ISR */
180 CpIntc_disableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
181 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
182 EventCombiner_disableEvent(eventId);
184 /* Restore interrupts */
185 Hwi_restore(cookie);
186 }
188 #else
189 /** To Register the ISRs with the underlying OS, if required. */
190 void registerEdma3Interrupts (unsigned int edma3Id)
191 {
192 static UInt32 cookie = 0;
193 //unsigned int numTc = 0;
195 /* Disabling the global interrupts */
196 cookie = Hwi_disable();
198 if(edma3Id == 0)
199 {
200 /* Enable the Xfer Completion Event Interrupt */
201 EventCombiner_dispatchPlug(6,
202 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
203 edma3Id, 1);
204 EventCombiner_enableEvent(6);
205 }
206 else if(edma3Id == 1)
207 {
208 /* Enable the Xfer Completion Event Interrupt */
209 EventCombiner_dispatchPlug(7,
210 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
211 edma3Id, 1);
212 EventCombiner_enableEvent(7);
213 }
216 /**
217 * Enabling the HWI_ID.
218 * EDMA3 interrupts (transfer completion, CC error etc.)
219 * correspond to different ECM events (SoC specific). These ECM events come
220 * under ECM block XXX (handling those specific ECM events). Normally, block
221 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
222 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
223 * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
224 * mapped HWI_INT YYY, one should use the corresponding bitmask in the
225 * API C64_enableIER(), in which the YYY bit is SET.
226 */
227 Hwi_enableInterrupt(7);
229 /* Restore interrupts */
230 Hwi_restore(cookie);
231 }
233 /** To Unregister the ISRs with the underlying OS, if previously registered. */
234 void unregisterEdma3Interrupts (unsigned int edma3Id)
235 {
236 static UInt32 cookie = 0;
237 unsigned int numTc = 0;
239 /* Disabling the global interrupts */
240 cookie = Hwi_disable();
242 /* Disable the Xfer Completion Event Interrupt */
243 EventCombiner_disableEvent(ccXferCompInt[edma3Id][0]);
245 /* Disable the CC Error Event Interrupt */
246 EventCombiner_disableEvent(ccErrorInt[edma3Id]);
248 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
249 while (numTc < numEdma3Tc[edma3Id])
250 {
251 EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
252 numTc++;
253 }
255 /* Restore interrupts */
256 Hwi_restore(cookie);
257 }
258 #endif