[processor-sdk/performance-audio-sr.git] / pasdk / test_dsp / application / itopo / evmk2g / sap_d10.c
2 /*
3 Copyright (c) 2017, Texas Instruments Incorporated - http://www.ti.com/
4 All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
36 //
37 // I/O device configuration data structure definitions D10 (DA10x EVM).
40 // -----------------------------------------------------------------------------
41 // This file contains the necessary configurations and functions for
42 // using the DA10x Audio DC card in the PA environment. In particular, the
43 // SAP configurations are referenced in the pa(i/y)-evmda10x-io.c files
44 // for use in IOS (Input/Output Switching) shortcuts. Each configuration
45 // contains settings appropriate to the various devices on the DA10x-AudioDC;
46 // the DIR, DACs, ADCs, and DIT output. Also each configuration points to
47 // a common control function (D10_sapControl), which handles the various
48 // requests made by the PA framework.
50 // A note about clocking. There are three different master clocks
51 // available corresponding to the three primary input choices: HDMI, DIR and ADC.
52 //
53 // DIR:
54 // . 512fs @ <= 48kHz
55 // . 256fs @ > 48kHz & <=96 kHz
56 // . 128fs @ > 96kHz
57 // ADC:
58 // . 768fs @ 32kHz
59 // . 512fs @ 48kHz
60 // . 256fs @ 96kHz
61 //
62 // This faciliates the logic used for the McASP transmit sections TX0 (DAC) and
63 // TX2 (DIT) which divide the master clock down to generate bit and frame clocks.
65 // -----------------------------------------------------------------------------
66 // Includes
68 #include <sap_d10.h>
69 #include <audio_dc_cfg.h>
70 #include "vproccmds_a.h"
71 #include "evmc66x_gpio.h" // in "${PDK_INSTALL_PATH}/ti/addon/audk2g/include"
73 #include "dbgBenchmark.h" // PCM high-sampling rate + SRC + CAR benchmarking
74 #include "mcasp_cfg.h"
76 // -----------------------------------------------------------------------------
77 // Local function declarations
79 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg);
80 static inline XDAS_Int32 initD10 (DEV2_Handle device) ;
81 static XDAS_Int32 clockMuxTx (int sel, int force);
82 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut);
83 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX);
85 void HSR4_readStatus (PAF_SIO_InputStatus *pStatus);
86 unsigned int HDMIGpioGetState (void);
88 /** GPIO number for I2S Header HSR4's ~HMINT pin - GPIO port 0 */
89 #define AUDK2G_AUDIO_HSR_HMINTz_GPIO (105) // missing from audio addon
91 /** GPIO number for I2S Header HSR4's ~RESET pin - GPIO port 0 */
92 #define AUDK2G_AUDIO_HSR_RESETz_GPIO (104) // missing from audio addon
94 // -----------------------------------------------------------------------------
95 // State machine variables and defines
97 // flag to facilitate one time initialization of DA10x Audio hardware
98 // 0 ==> not initialized, 1 ==> initialized
99 static char initDone = 0;
101 // input status
102 static PAF_SIO_InputStatus primaryStatus =
103 {
104 0, // lock
105 PAF_IEC_AUDIOMODE_UNKNOWN, // nonaudio
106 PAF_IEC_PREEMPHASIS_UNKNOWN, // emphasis
107 PAF_SAMPLERATE_UNKNOWN, // sampleRateMeasured
108 PAF_SAMPLERATE_UNKNOWN, // sampleRateData
109 0,0,0, // unused
110 };
113 // The McASP outputs (both for DAC and DIT) receive a high speed clock
114 // and in turn generate a bit and frame clock. The needed clock divider
115 // values are kept here for easy lookup.
116 unsigned char *pClkxDiv = NULL;
118 static const unsigned char clkxDivDIR[PAF_SAMPLERATE_N] =
119 {
120 0x2, //PAF_SAMPLERATE_UNKNOWN
121 0x8, //PAF_SAMPLERATE_NONE
122 0x8, //PAF_SAMPLERATE_32000HZ
123 0x2, //PAF_SAMPLERATE_44100HZ
124 0x2, //PAF_SAMPLERATE_48000HZ
125 0x4, //PAF_SAMPLERATE_88200HZ
126 0x2, //PAF_SAMPLERATE_96000HZ
127 0x2, //PAF_SAMPLERATE_192000HZ
128 0x4, //PAF_SAMPLERATE_64000HZ
129 0x2, //PAF_SAMPLERATE_128000HZ
130 0x2, //PAF_SAMPLERATE_176400HZ
131 0x8, //PAF_SAMPLERATE_8000HZ
132 0x8, //PAF_SAMPLERATE_11025HZ
133 0x8, //PAF_SAMPLERATE_12000HZ
134 0x8, //PAF_SAMPLERATE_16000HZ
135 0x8, //PAF_SAMPLERATE_22050HZ
136 0x8, //PAF_SAMPLERATE_24000HZ
137 };
140 static const unsigned char clkxDivADC[PAF_SAMPLERATE_N] =
141 {
142 0x8, //PAF_SAMPLERATE_UNKNOWN
143 0x8, //PAF_SAMPLERATE_NONE
144 0xC, //PAF_SAMPLERATE_32000HZ
145 0x8, //PAF_SAMPLERATE_44100HZ
146 0x8, //PAF_SAMPLERATE_48000HZ
147 0x4, //PAF_SAMPLERATE_88200HZ
148 0x4, //PAF_SAMPLERATE_96000HZ
149 0x2, //PAF_SAMPLERATE_192000HZ
150 0x4, //PAF_SAMPLERATE_64000HZ
151 0x2, //PAF_SAMPLERATE_128000HZ
152 0x2, //PAF_SAMPLERATE_176400HZ
153 0x8, //PAF_SAMPLERATE_8000HZ
154 0x8, //PAF_SAMPLERATE_11025HZ
155 0x8, //PAF_SAMPLERATE_12000HZ
156 0x8, //PAF_SAMPLERATE_16000HZ
157 0x8, //PAF_SAMPLERATE_22050HZ
158 0x8, //PAF_SAMPLERATE_24000HZ
159 };
161 static const unsigned char clkxDivHDMI[PAF_SAMPLERATE_N] =
162 {
163 0x2, //PAF_SAMPLERATE_UNKNOWN
164 0x2, //PAF_SAMPLERATE_NONE
165 0x8, //PAF_SAMPLERATE_32000HZ
166 0x2, //PAF_SAMPLERATE_44100HZ
167 0x2, //PAF_SAMPLERATE_48000HZ
168 0x2, //PAF_SAMPLERATE_88200HZ
169 0x2, //PAF_SAMPLERATE_96000HZ
170 0x2, //PAF_SAMPLERATE_192000HZ
171 0x4, //PAF_SAMPLERATE_64000HZ
172 0x2, //PAF_SAMPLERATE_128000HZ
173 0x2, //PAF_SAMPLERATE_176400HZ
174 0x8, //PAF_SAMPLERATE_8000HZ
175 0x8, //PAF_SAMPLERATE_11025HZ
176 0x8, //PAF_SAMPLERATE_12000HZ
177 0x8, //PAF_SAMPLERATE_16000HZ
178 0x8, //PAF_SAMPLERATE_22050HZ
179 0x8, //PAF_SAMPLERATE_24000HZ
180 };
182 // The ADCs, when operating as the master input, can only
183 // generate a limited set of audio sample rates since the clock
184 // is derived from AUXCLK which is the oscillator connected to the DSP.
185 // This table faciliates the access and definition of these rates.
186 static const Uint16 oscRateTable[8] =
187 {
188 PAF_SAMPLERATE_UNKNOWN, // 0
189 PAF_SAMPLERATE_32000HZ,
190 PAF_SAMPLERATE_44100HZ, // D10_RATE_44_1KHZ
191 PAF_SAMPLERATE_48000HZ,
192 PAF_SAMPLERATE_88200HZ, // D10_RATE_88_2KHZ
193 PAF_SAMPLERATE_96000HZ,
194 PAF_SAMPLERATE_176400HZ, // D10_RATE_176_4KHZ
195 PAF_SAMPLERATE_192000HZ
196 };
198 static const Uint16 RateTable_hdmi[8] =
199 {
200 PAF_SAMPLERATE_UNKNOWN, // HSDIO_AudioFreq_RESERVED
201 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
202 PAF_SAMPLERATE_44100HZ, // HSDIO_AudioFreq_44_1K
203 PAF_SAMPLERATE_48000HZ, // HSDIO_AudioFreq_48K
204 PAF_SAMPLERATE_88200HZ, // HSDIO_AudioFreq_88_2K
205 PAF_SAMPLERATE_96000HZ, // HSDIO_AudioFreq_96_4K
206 PAF_SAMPLERATE_176400HZ, // HSDIO_AudioFreq_176_4K
207 PAF_SAMPLERATE_192000HZ // HSDIO_AudioFreq_192K
208 };
210 static const Uint16 RateTable_spdif[4] =
211 {
212 PAF_SAMPLERATE_44100HZ, // AudioFreq_44_1K
213 PAF_SAMPLERATE_48000HZ, // AudioFreq_48K
214 PAF_SAMPLERATE_UNKNOWN, // AudioFreq_RESERVED
215 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
216 };
219 // base mcasp addresses for easy lookup
220 static volatile Uint32 * mcaspAddr[_MCASP_PORT_CNT] =
221 {
222 (volatile Uint32 *) _MCASP_BASE_PORT0,
223 (volatile Uint32 *) _MCASP_BASE_PORT1,
224 (volatile Uint32 *) _MCASP_BASE_PORT2
225 };
227 // The DA10x HW is configured for the DAC's mute lines to be operated based
228 // on McASP0's AMUTE (out) line. This is the hard mute.
229 static inline void dacHardMute (void) {
230 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
231 mcasp0[_MCASP_PDOUT_OFFSET] |= _MCASP_PDOUT_AMUTE_MASK;
232 }
233 static inline void dacHardUnMute (void) {
234 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
235 mcasp0[_MCASP_PDOUT_OFFSET] &= ~_MCASP_PDOUT_AMUTE_MASK;
236 mcasp0[_MCASP_AMUTE_OFFSET] |= MCASP_AMUTE_MUTEN_ERRLOW;
237 }
239 // How should the PCM18x DAC's soft mute functionality be used here?
240 // i.e, as different from the hard mute? need to review.
241 static inline void dacSoftMute (void) {
242 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
243 mcasp0[6] = 0x000 ;
244 mcasp0[6] = 0x400 ;
245 }
246 static inline void dacSoftUnMute (void) {
247 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
248 mcasp0[6] = 0x000 ;
249 mcasp0[6] = 0x400 ;
250 }
252 // -----------------------------------------------------------------------------
253 // McASP Input Configuration Definitions
255 static const MCASP_ConfigRcv rxConfigDIR = // This is used for both DIR and HDMI?? Yes. Same digital format.
256 {
257 // The receive format unit bit mask register (RMASK) determines which bits
258 // of the received data are masked off and padded with a known value before
259 // being read by the CPU or DMA.
260 MCASP_RMASK_OF(0xFFFFFFFF), // Don't mask any bits. 0).??
261 // The receive bit stream format register (RFMT) configures the receive data format.
262 MCASP_RFMT_RMK( // 0x0001C0F0
263 MCASP_RFMT_RDATDLY_1BIT, // 17-16: Receive bit delay. Standard I2S configuraiton. MSB first, 1 bit delay.
264 MCASP_RFMT_RRVRS_MSBFIRST, // 15: Receive serial bitstream order.
265 MCASP_RFMT_RPAD_RPBIT, // 14-13: Pad value for extra bits in slot not belonging to the word. N/A because RMASK is 0xFFFFFFFF and no bits need padding.
266 MCASP_RFMT_RPBIT_OF(0), // 12-8: RPBIT value determines which bit is used to pad the extra bits. This field only applies when RPAD = 2h. N/A same reason as above.
267 MCASP_RFMT_RSSZ_32BITS, // 7-4: Receive slot size. Value is 15.
268 MCASP_RFMT_RBUSEL_DAT, // 3: Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port.
269 MCASP_RFMT_RROT_NONE), // 2-0: Right-rotation value for receive rotate right format unit.
270 // The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR).
271 MCASP_AFSRCTL_RMK( // 0x00000111
272 MCASP_AFSRCTL_RMOD_OF(2), // 15-7: Receive frame sync mode select bits. 2 - 2-slot TDM (I2S mode)
273 MCASP_AFSRCTL_FRWID_WORD, // 4: Receive frame sync width. 1 - Single word
274 MCASP_AFSRCTL_FSRM_EXTERNAL, // 1: Receive frame sync generation select bit. 0 - Externally-generated receive frame sync
275 MCASP_AFSRCTL_FSRP_ACTIVELOW), // 0: Receive frame sync polarity select bit. 1 - A falling edge indicates the beginning of a frame.
276 // The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator.
277 MCASP_ACLKRCTL_RMK( // 0x00000080
278 MCASP_ACLKRCTL_CLKRP_RISING, // 7: Receive bitstream clock polarity select bit. 1 - rising edge. Different from PDK 1.0.1 platform audio test (falling edge)??
279 MCASP_ACLKRCTL_CLKRM_EXTERNAL, // 5: Receive bit clock source bit.
280 MCASP_ACLKRCTL_CLKRDIV_DEFAULT), // 4-0: Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR
281 // The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator.
282 MCASP_AHCLKRCTL_RMK( // 0x00000000
283 MCASP_AHCLKRCTL_HCLKRM_EXTERNAL, // 15: Receive high-frequency clock source bit.
284 MCASP_AHCLKRCTL_HCLKRP_RISING, // 14: Receive bitstream high-frequency clock polarity select bit. 0 - Rising edge.
285 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT), // 11-0: Receive high-frequency clock divide ratio bits. 0 - Divide by 1.
286 // The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active
287 MCASP_RTDM_OF(3), // 0x00000003: time slots 0 and 1 are active
288 // The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT).
289 MCASP_RINTCTL_DEFAULT, // 0x00000000
290 // The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit.
291 MCASP_RCLKCHK_DEFAULT // 0x00000000
292 };
294 static const MCASP_ConfigRcv rxConfigADC =
295 {
296 MCASP_RMASK_OF(0xFFFFFFFF),
297 MCASP_RFMT_RMK(
298 MCASP_RFMT_RDATDLY_1BIT,
299 MCASP_RFMT_RRVRS_MSBFIRST,
300 MCASP_RFMT_RPAD_RPBIT,
301 MCASP_RFMT_RPBIT_OF(0),
302 MCASP_RFMT_RSSZ_32BITS,
303 MCASP_RFMT_RBUSEL_DAT,
304 MCASP_RFMT_RROT_NONE),
305 MCASP_AFSRCTL_RMK(
306 MCASP_AFSRCTL_RMOD_OF(2),
307 MCASP_AFSRCTL_FRWID_WORD,
308 MCASP_AFSRCTL_FSRM_INTERNAL, // internal
309 MCASP_AFSRCTL_FSRP_ACTIVEHIGH), // active high
310 MCASP_ACLKRCTL_RMK(
311 MCASP_ACLKRCTL_CLKRP_RISING,
312 MCASP_ACLKRCTL_CLKRM_INTERNAL, //
313 MCASP_ACLKXCTL_CLKXDIV_OF(7)), //
314 MCASP_AHCLKRCTL_RMK(
315 MCASP_AHCLKRCTL_HCLKRM_INTERNAL, //
316 MCASP_AHCLKRCTL_HCLKRP_RISING,
317 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
318 MCASP_RTDM_OF(3),
319 MCASP_RINTCTL_DEFAULT,
320 MCASP_RCLKCHK_DEFAULT
321 };
323 // -----------------------------------------------------------------------------
324 // McASP Output Configuration Definitions
326 static const MCASP_ConfigXmt txConfigDAC =
327 {
328 MCASP_XMASK_OF(0xFFFFFFFF),
329 MCASP_XFMT_RMK(
330 MCASP_XFMT_XDATDLY_1BIT,
331 MCASP_XFMT_XRVRS_MSBFIRST,
332 MCASP_XFMT_XPAD_ZERO,
333 MCASP_XFMT_XPBIT_DEFAULT,
334 MCASP_XFMT_XSSZ_32BITS,
335 MCASP_XFMT_XBUSEL_DAT,
336 MCASP_XFMT_XROT_NONE),
337 MCASP_AFSXCTL_RMK(
338 MCASP_AFSXCTL_XMOD_OF(2),
339 MCASP_AFSXCTL_FXWID_WORD,
340 MCASP_AFSXCTL_FSXM_INTERNAL,
341 MCASP_AFSXCTL_FSXP_ACTIVELOW),
342 MCASP_ACLKXCTL_RMK(
343 MCASP_ACLKXCTL_CLKXP_FALLING,
344 MCASP_ACLKXCTL_ASYNC_ASYNC,
345 MCASP_ACLKXCTL_CLKXM_INTERNAL,
346 MCASP_ACLKXCTL_CLKXDIV_DEFAULT),
347 MCASP_AHCLKXCTL_RMK(
348 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
349 MCASP_AHCLKXCTL_HCLKXP_FALLING,
350 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
351 MCASP_XTDM_OF(3),
352 MCASP_XINTCTL_DEFAULT,
353 MCASP_XCLKCHK_DEFAULT
354 };
356 static const MCASP_ConfigXmt txConfigDACSlave =
357 {
358 MCASP_XMASK_OF(0xFFFFFFFF),
359 MCASP_XFMT_RMK(
360 MCASP_XFMT_XDATDLY_1BIT,
361 MCASP_XFMT_XRVRS_MSBFIRST,
362 MCASP_XFMT_XPAD_ZERO,
363 MCASP_XFMT_XPBIT_DEFAULT,
364 MCASP_XFMT_XSSZ_32BITS,
365 MCASP_XFMT_XBUSEL_DAT,
366 MCASP_XFMT_XROT_NONE),
367 MCASP_AFSXCTL_RMK(
368 MCASP_AFSXCTL_XMOD_OF(2),
369 MCASP_AFSXCTL_FXWID_WORD,
370 MCASP_AFSXCTL_FSXM_INTERNAL,
371 MCASP_AFSXCTL_FSXP_ACTIVELOW),
372 MCASP_ACLKXCTL_RMK(
373 MCASP_ACLKXCTL_CLKXP_FALLING,
374 MCASP_ACLKXCTL_ASYNC_ASYNC,
375 MCASP_ACLKXCTL_CLKXM_INTERNAL,
376 MCASP_ACLKXCTL_CLKXDIV_OF(1)),
377 MCASP_AHCLKXCTL_RMK(
378 MCASP_AHCLKXCTL_HCLKXM_INTERNAL,
379 MCASP_AHCLKXCTL_HCLKXP_FALLING,
380 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
381 MCASP_XTDM_OF(3),
382 MCASP_XINTCTL_DEFAULT,
383 MCASP_XCLKCHK_DEFAULT
384 };
386 static const MCASP_ConfigXmt txConfigDIT =
387 {
388 MCASP_XMASK_OF(0x00FFFFFF),
389 MCASP_XFMT_RMK(
390 MCASP_XFMT_XDATDLY_1BIT,
391 MCASP_XFMT_XRVRS_LSBFIRST,
392 MCASP_XFMT_XPAD_DEFAULT,
393 MCASP_XFMT_XPBIT_DEFAULT,
394 MCASP_XFMT_XSSZ_32BITS,
395 MCASP_XFMT_XBUSEL_DAT,
396 MCASP_XFMT_XROT_NONE),
397 MCASP_AFSXCTL_RMK(
398 MCASP_AFSXCTL_XMOD_OF(0x180),
399 MCASP_AFSXCTL_FXWID_BIT,
400 MCASP_AFSXCTL_FSXM_INTERNAL,
401 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
402 MCASP_ACLKXCTL_RMK(
403 MCASP_ACLKXCTL_CLKXP_FALLING,
404 MCASP_ACLKXCTL_ASYNC_ASYNC,
405 MCASP_ACLKXCTL_CLKXM_INTERNAL,
406 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
407 MCASP_AHCLKXCTL_RMK(
408 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
409 MCASP_AHCLKXCTL_HCLKXP_FALLING,
410 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
411 MCASP_XTDM_OF(0xFFFFFFFF),
412 MCASP_XINTCTL_DEFAULT,
413 MCASP_XCLKCHK_DEFAULT
414 };
416 #if 0
417 static const MCASP_ConfigXmt txConfigDIT_16bit =
418 {
419 MCASP_XMASK_OF(0x0000FFFF),
420 MCASP_XFMT_RMK(
421 MCASP_XFMT_XDATDLY_1BIT,
422 MCASP_XFMT_XRVRS_LSBFIRST,
423 MCASP_XFMT_XPAD_DEFAULT,
424 MCASP_XFMT_XPBIT_DEFAULT,
425 MCASP_XFMT_XSSZ_32BITS,
426 MCASP_XFMT_XBUSEL_DAT,
427 MCASP_XFMT_XROT_24BITS),
428 MCASP_AFSXCTL_RMK(
429 MCASP_AFSXCTL_XMOD_OF(0x180),
430 MCASP_AFSXCTL_FXWID_BIT,
431 MCASP_AFSXCTL_FSXM_INTERNAL,
432 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
433 MCASP_ACLKXCTL_RMK(
434 MCASP_ACLKXCTL_CLKXP_FALLING,
435 MCASP_ACLKXCTL_ASYNC_ASYNC,
436 MCASP_ACLKXCTL_CLKXM_INTERNAL,
437 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
438 MCASP_AHCLKXCTL_RMK(
439 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
440 MCASP_AHCLKXCTL_HCLKXP_FALLING,
441 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
442 MCASP_XTDM_OF(0xFFFFFFFF),
443 MCASP_XINTCTL_DEFAULT,
444 MCASP_XCLKCHK_DEFAULT
445 };
446 #endif
448 // -----------------------------------------------------------------------------
449 // DAP Input Parameter Definitions
451 const SAP_D10_Rx_Params SAP_D10_RX_DIR =
452 {
453 sizeof (SAP_D10_Rx_Params), // size
454 "SAP", // name
455 MCASP_DEV2, // moduleNum --> mcasp #
456 (Void *)&rxConfigDIR, // pConfig
457 4, // wordSize (unused)
458 24, // precision (unused)
459 D10_sapControl, // control
460 0x00000020, // pinMask
461 (D10_MCLK_DIR << D10_MCLK_SHIFT), // mode
462 0,0 // unused[2]
463 };
465 const SAP_D10_Rx_Params SAP_D10_RX_ADC_44100HZ =
466 {
467 sizeof (SAP_D10_Rx_Params), // size
468 "SAP", // name
469 MCASP_DEV1, // moduleNum --> mcasp #
470 (Void *)&rxConfigADC, // pConfig
471 4, // wordSize (unused)
472 24, // precision (unused)
473 D10_sapControl, // control
474 0xE000000F, // pinMask
475 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
476 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
477 0,0 // unused[2]
478 };
480 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_44100HZ =
481 {
482 sizeof (SAP_D10_Rx_Params), // size
483 "SAP", // name
484 MCASP_DEV1, // moduleNum --> mcasp #
485 (Void *)&rxConfigADC, // pConfig
486 -1, // wordSize (unused)
487 -1, // precision (unused)
488 D10_sapControl, // control
489 0xE0000007, // pinMask
490 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
491 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
492 0,0 // unused[2]
493 };
495 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_44100HZ =
496 {
497 sizeof (SAP_D10_Rx_Params), // size
498 "SAP", // name
499 MCASP_DEV1, // moduleNum --> mcasp #
500 (Void *)&rxConfigADC, // pConfig
501 -1, // wordSize (unused)
502 -1, // precision (unused)
503 D10_sapControl, // control
504 0xE0000001, // pinMask
505 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
506 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
507 0,0 // unused[2]
508 };
510 const SAP_D10_Rx_Params SAP_D10_RX_ADC_88200HZ =
511 {
512 sizeof (SAP_D10_Rx_Params), // size
513 "SAP", // name
514 MCASP_DEV1, // moduleNum --> mcasp #
515 (Void *)&rxConfigADC, // pConfig
516 -1, // wordSize (unused)
517 -1, // precision (unused)
518 D10_sapControl, // control
519 0xE000000F, // pinMask
520 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
521 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
522 0,0 // unused[2]
523 };
525 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_88200HZ =
526 {
527 sizeof (SAP_D10_Rx_Params), // size
528 "SAP", // name
529 MCASP_DEV1, // moduleNum --> mcasp #
530 (Void *)&rxConfigADC, // pConfig
531 -1, // wordSize (unused)
532 -1, // precision (unused)
533 D10_sapControl, // control
534 0xE0000007, // pinMask
535 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
536 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
537 0,0 // unused[2]
538 };
540 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_88200HZ =
541 {
542 sizeof (SAP_D10_Rx_Params), // size
543 "SAP", // name
544 MCASP_DEV1, // moduleNum --> mcasp #
545 (Void *)&rxConfigADC, // pConfig
546 -1, // wordSize (unused)
547 -1, // precision (unused)
548 D10_sapControl, // control
549 0xE0000001, // pinMask
550 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
551 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
552 0,0 // unused[2]
553 };
556 const SAP_D10_Rx_Params SAP_D10_RX_HDMI_STEREO =
557 {
558 sizeof (SAP_D10_Rx_Params), // size
559 "SAP", // name
560 MCASP_DEV0, // moduleNum --> mcasp #
561 //(Void *)&rxConfigDIR, // pConfig
562 (Void *)&LLDconfigRxHDMIStereo, // pConfig
563 4, // wordSize (unused)
564 -1, // precision (unused)
565 D10_sapControl, // control
566 0x00001000, // pinMask
567 (D10_MODE_HDMI << D10_MODE_SHIFT) |
568 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
569 0,0 // unused[2]
570 };
572 const SAP_D10_Rx_Params SAP_D10_RX_HDMI =
573 {
574 sizeof (SAP_D10_Rx_Params), // size
575 "SAP", // name
576 MCASP_DEV0, // moduleNum --> mcasp #
577 // (Void *)&rxConfigDIR, // pConfig
578 (Void *)&LLDconfigRxHDMI,
579 4, // wordSize (unused)
580 -1, // precision (unused)
581 D10_sapControl, // control
582 0x0000F000, // pinMask
583 (D10_MODE_HDMI << D10_MODE_SHIFT) |
584 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
585 0,0 // unused[2]
586 };
588 // -----------------------------------------------------------------------------
589 // SAP Output Parameter Definitions
591 const SAP_D10_Tx_Params SAP_D10_TX_DAC =
592 {
593 sizeof (SAP_D10_Tx_Params), // size
594 "SAP", // name
595 MCASP_DEV0, // moduleNum --> mcasp #
596 //(Void *)&txConfigDAC, // pConfig
597 (Void *)&LLDconfigTxDAC,
598 4, // wordSize (in bytes)
599 24, // precision (in bits)
600 D10_sapControl, // control
601 0x1600000F, // pinMask
602 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
603 0,0,0 // unused[3]
604 };
606 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC =
607 {
608 sizeof (SAP_D10_Tx_Params), // size
609 "SAP", // name
610 MCASP_DEV0, // moduleNum --> mcasp #
611 (Void *)&txConfigDAC, // pConfig
612 4, // wordSize (in bytes)
613 24, // precision (in bits)
614 D10_sapControl, // control
615 0x16000001, // pinMask
616 0, // mode
617 0,0,0 // unused[3]
618 };
620 const SAP_D10_Tx_Params SAP_D10_TX_DIT =
621 {
622 sizeof (SAP_D10_Tx_Params), // size
623 "SAP", // name
624 MCASP_DEV2, // moduleNum --> mcasp #
625 (Void *) &txConfigDIT, // pConfig
626 3, // wordSize (in bytes)
627 24, // precision (in bits)
628 D10_sapControl, // control
629 0x1C000001, // pinMask
630 0, // mode
631 0,0,0 // unused[3]
632 };
634 const SAP_D10_Tx_Params SAP_D10_TX_DAC_SLAVE =
635 {
636 sizeof (SAP_D10_Tx_Params), // size
637 "SAP", // name
638 MCASP_DEV0, // moduleNum --> mcasp #
639 (Void *)&txConfigDACSlave, // pConfig
640 4, // wordSize (in bytes)
641 24, // precision (in bits)
642 D10_sapControl, // control
643 0x1E00000F, // pinMask
644 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
645 0,0,0 // unused[3]
646 };
648 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC_SLAVE =
649 {
650 sizeof (SAP_D10_Tx_Params), // size
651 "SAP", // name
652 MCASP_DEV0, // moduleNum --> mcasp #
653 (Void *)&txConfigDAC, // pConfig
654 4, // wordSize (in bytes)
655 24, // precision (in bits)
656 D10_sapControl, // control
657 0x16000001, // pinMask
658 0, // mode
659 0,0,0 // unused[3]
660 };
662 const SAP_D10_Tx_Params SAP_D10_TX_DAC_12CH =
663 {
664 sizeof (SAP_D10_Tx_Params), // size
665 "SAP", // name
666 MCASP_DEV0, // moduleNum --> mcasp #
667 (Void *)&txConfigDAC, // pConfig
668 4, // wordSize (in bytes)
669 24, // precision (in bits)
670 D10_sapControl, // control
671 0x1600003F, // pinMask
672 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
673 0,0,0 // unused[3]
674 };
676 const SAP_D10_Tx_Params SAP_D10_TX_DAC_16CH =
677 {
678 sizeof (SAP_D10_Tx_Params), // size
679 "SAP", // name
680 MCASP_DEV0, // moduleNum --> mcasp #
681 (Void *)&txConfigDAC, // pConfig
682 4, // wordSize (in bytes)
683 24, // precision (in bits)
684 D10_sapControl, // control
685 0x160000FF, // pinMask
686 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
687 0,0,0 // unused[3]
688 };
691 // -----------------------------------------------------------------------------
692 // One time initialization of the DA10x audio hardware.
694 /* DAC default configuration parameters */
695 DacConfig dacCfg =
696 {
697 AUDK2G_DAC_AMUTE_CTRL_SCKI_LOST, /* Amute event */
698 0, /* Amute control */
699 AUDK2G_DAC_SAMPLING_MODE_SINGLE_RATE, /* Sampling mode */
700 AUDK2G_DAC_DATA_FORMAT_I2S, /* Data format */
701 0, /* Soft mute control */
702 AUDK2G_DAC_ATTENUATION_WIDE_RANGE, /* Attenuation mode */
703 AUDK2G_DAC_DEEMP_44KHZ, /* De-emph control */
704 100 /* Volume */
705 };
706 /* ADC default configuration parameters */
707 AdcConfig adcCfg =
708 {
709 90, /* ADC gain */
710 AUDK2G_ADC_INL_SE_VINL1, /* Left input mux for ADC1L */
711 AUDK2G_ADC_INL_SE_VINL2, /* Left input mux for ADC2L */
712 AUDK2G_ADC_INR_SE_VINR1, /* Right input mux for ADC1R */
713 AUDK2G_ADC_INR_SE_VINR2, /* Right input mux for ADC2R */
714 AUDK2G_ADC_RX_WLEN_24BIT, /* ADC word length */
715 AUDK2G_ADC_DATA_FORMAT_I2S, /* ADC data format */
716 0
717 };
719 Audk2g_STATUS setAudioDacConfig(void)
720 {
721 Audk2g_STATUS status;
723 /* Initialize Audio DAC module */
724 status = audioDacConfig(AUDK2G_DAC_DEVICE_ALL, &dacCfg); // defined in sap\audio_dc_cfg.c
725 if (status)
726 Log_info0("SAP_D10: Audio DAC Configuration Failed!!!\n");
727 return status;
729 }
731 // Configure GPIO for HSR HDMI signaling. This needs to be added to audk2g_AudioInit()
732 // in ti\addon\audk2g\src\audk2g.c.
733 Audk2g_STATUS audk2g_AudioInit_Extra()
734 {
735 /* Configure GPIO for HSR HDMI Signaling - GPIO0 104 (~RESET) & 105 (~HMINT) */
736 audk2g_pinMuxSetMode(114, AUDK2G_PADCONFIG_MUX_MODE_QUATERNARY);
737 audk2g_gpioSetDirection(AUDK2G_GPIO_PORT_0, AUDK2G_AUDIO_HSR_HMINTz_GPIO, AUDK2G_GPIO_IN);
739 audk2g_pinMuxSetMode(113, AUDK2G_PADCONFIG_MUX_MODE_QUATERNARY);
740 audk2g_gpioSetDirection(AUDK2G_GPIO_PORT_0, AUDK2G_AUDIO_HSR_RESETz_GPIO, AUDK2G_GPIO_OUT);
741 audk2g_gpioSetOutput(AUDK2G_GPIO_PORT_0, AUDK2G_AUDIO_HSR_RESETz_GPIO);
743 return Audk2g_EOK;
744 }
746 static inline XDAS_Int32 initD10 (DEV2_Handle device)
747 {
748 Audk2g_STATUS status = Audk2g_EOK;
750 /* Initialize common audio configurations */
751 status = audk2g_AudioInit(); // defined in in ti\addon\audk2g\src\audk2g.c
752 if(status != Audk2g_EOK)
753 {
754 Log_info0("audk2g_AudioInit Failed!\n");
755 return status;
756 }
757 else
758 Log_info0("audk2g_AudioInit Passed!\n");
760 status = (Audk2g_STATUS)audk2g_AudioInit_Extra();
761 if(status != Audk2g_EOK)
762 {
763 Log_info0("audk2g_AudioInit_Extra Failed!\n");
764 return status;
765 }
766 else
767 Log_info0("audk2g_AudioInit_Extra Passed!\n");
769 /* Initialize Audio ADC module */
770 status = audioAdcConfig(AUDK2G_ADC_DEVICE_ALL, &adcCfg);
771 if(status != Audk2g_EOK)
772 {
773 Log_info0("Audio ADC Configuration Failed!\n");
774 return status;
775 }
776 else
777 Log_info0("Audio ADC Configuration Passed!\n");
779 /* Setup DIR 9001 for SPDIF input operation */
780 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
781 status = audioDirConfig();
782 if(status != Audk2g_EOK)
783 {
784 Log_info0("Audio DIR Init Failed!\n");
785 return status;
786 }
787 else
788 Log_info0("Audio DIR Init Passed!\n");
790 #if 1
791 /* Setup HSR41 for HDMI input operation */
792 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
793 /* Initialize the HDMI Card */
794 while(HDMIGpioGetState());
795 status = audioHDMIConfig();
796 if(status != Audk2g_EOK)
797 {
798 Log_info0("Audio HDMI Init Failed!\n");
799 return status;
800 }
801 else
802 Log_info0("Audio HDMI Init Passed!\n");
803 #endif
805 status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_DIR);
806 audk2g_delay(50000); // Without delay between these 2 calls system aborts.
807 status = setAudioDacConfig();
809 Log_info1("Leaving initD10 with status = %d", status);
811 return status;
813 } //initD10
815 // -----------------------------------------------------------------------------
816 // The McASP TX section is *only* used as a master clock mux.
817 // Mux functionality is achieved by selecting either external high
818 // speed clocks (DIR/HDMI) or the internal AUXCLK (Audio_OSC). This is divided down
819 // output via ACLKX0 which is connected to the high speed input
820 // of TX0 (DAC) and TX2 (DIT).
821 static XDAS_Int32 clockMuxTx (int sel, int force)
822 {
823 Audk2g_STATUS status = 0;
824 // select clkxDiv table
825 if (sel == D10_MCLK_DIR)
826 {
827 status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_DIR);
828 pClkxDiv = (unsigned char *) clkxDivDIR;
829 }
830 else if (sel == D10_MCLK_HDMI)
831 {
832 status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_I2S);
833 pClkxDiv = (unsigned char *) clkxDivHDMI;
834 }
835 else if (sel == D10_MCLK_OSC)
836 {
837 status = audk2g_AudioSelectClkSrc((Audk2gAudioClkSrc)AUDK2G_AUDIO_CLK_SRC_OSC);
838 pClkxDiv = (unsigned char *) clkxDivADC;
839 }
840 Log_info1("SAP_D10: Inside clockMuxTx with sel = %d", sel);
842 audk2g_delay(20000);
844 return status;
845 } //clockMuxTx
848 // -----------------------------------------------------------------------------
849 // This function returns the input status of the specified device.
850 // This is called once when the device is opened
851 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter
852 // (PAF_SIO_CONTROL_GET_INPUT_STATUS).
853 int gHmint_ctr = 0, gNonAudio = 0, gLockStatus=0, gPrevAudio=0, gPrevLock=0;
854 int gSync_ctr, gLock_ctr, gAudioErr_ctr, gNonAudio_ctr = 0;
856 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut)
857 {
858 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
859 //volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
860 //volatile Uint32 *mcasp1 = (volatile Uint32 *) _MCASP_BASE_PORT1;
861 //volatile Uint32 *mcasp2 = (volatile Uint32 *) _MCASP_BASE_PORT2;
863 //Platform_STATUS status;
865 static int PrevSampRate = 0;
866 int RateHdmi =0;
868 /* Mode & MCLK info embedded statically in the Rx IO definition for SPDIF Input */
869 if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_DIR) &
870 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD))
871 {
872 pStatusIn->lock = !(audk2g_AudioDirGetClkStatus());
873 pStatusIn->nonaudio = !(audk2g_AudioDirGetAudioStatus());
874 pStatusIn->emphasis = audk2g_AudioDirGetEmphStatus();
875 pStatusIn->sampleRateMeasured = RateTable_spdif[audk2g_AudioDirGetFsOut()];
876 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
877 PrevSampRate = pStatusIn->sampleRateMeasured;
879 // GJ: Is this needed? Probably not.
880 // GJ: Mute Control during input-change seemingly intended.
881 //mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
882 //mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
884 }
885 /* Mode & MCLK info embedded statically in the Rx IO definition for ANALOG/ADC Input */
886 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_OSC) &
887 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD)) {
888 int adcRate = (pParams->d10rx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
890 pStatusIn->lock = 1;
891 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
892 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
893 pStatusIn->sampleRateMeasured = oscRateTable[adcRate];
894 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
896 }
897 /* Mode & MCLK info embedded statically in the Rx IO definition for HDMI */
898 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_HDMI) &
899 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_HDMI))
900 {
902 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
904 #ifndef ___ENABLE_BENCHMARK_PCMHSR_SRC_CAR_ //TODO: For all the cases it works.
905 //
906 // Input interface rate hard-coded to 192 kHz to avoid I2C transactions.
907 // Temporary fix works for EC3 and MLP/MAT formats.
908 //
909 pStatusIn->lock = 1;
910 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
911 /*RateHdmi = HSDIO_AudioFreq_192K;
912 pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
913 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured; */
914 if(!HDMIGpioGetState())
915 {
916 clear_hdmi_hmint();
917 gHmint_ctr++;
919 RateHdmi=read_hdmi_samprate();
920 pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
921 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
922 PrevSampRate = pStatusIn->sampleRateMeasured;
923 }
924 else
925 {
926 pStatusIn->sampleRateMeasured = PrevSampRate;
927 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
928 }
929 #else // _ENABLE_BENCHMARK_PCMHSR_SRC_CAR_
930 //
931 // Need to update input interface rate by consulting HSR4 over I2C for benchmarking configuration.
932 //
933 if(!HDMIGpioGetState())
934 {
935 clear_hdmi_hmint();
936 gHmint_ctr++;
938 RateHdmi=read_hdmi_samprate();
939 pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
940 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
941 PrevSampRate = pStatusIn->sampleRateMeasured;
942 /*
943 switch(read_hdmi_errstatus())
944 {
945 case HSDIO_AudioErr_NO_ERROR:
946 {
947 gPrevLock=pStatusIn->lock;
948 gPrevAudio=pStatusIn->nonaudio;
949 pStatusIn->lock = 1;
950 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
951 break;
952 }
953 case HSDIO_AudioErr_AUDIO_NO_PLL_LOCK:
954 {
955 gLock_ctr++;
956 pStatusIn->lock = 0;
957 //pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
958 break;
959 }
960 case HSDIO_AudioErr_AUDIO_NO_AUDIO:
961 {
962 gAudioErr_ctr++;
963 //pStatusIn->lock = 1;
964 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_NONAUDIO;
965 break;
966 }
967 default:
968 while(1); // Control shouldn't be here.
969 }
971 if(HSDIO_AudioMClk_128X != read_hdmi_clockstatus())
972 {
973 gLock_ctr++;
974 pStatusIn->lock = 0;
975 }
976 else if (HSDIO_AudioPresent_HAS_AUDIO != read_hdmi_audiostatus())
977 {
978 gNonAudio_ctr++;
979 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_NONAUDIO;
980 }*/
982 }
983 else
984 {
985 pStatusIn->sampleRateMeasured = PrevSampRate;
986 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
987 }
988 #endif // _ENABLE_BENCHMARK_PCMHSR_SRC_CAR_
989 }
991 else
992 return -1; // Control shouldn't be here!
994 gNonAudio=pStatusIn->nonaudio;
995 gLockStatus=pStatusIn->lock;
997 // update another status if requested
998 if (pStatusOut)
999 *pStatusOut = *pStatusIn;
1001 return 0;
1002 } //manageInput
1005 // -----------------------------------------------------------------------------
1006 // This function configures the McASP TX clock dividers based on the
1007 // master clock rate. This is called once when the device is opened
1008 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter (PAF_SIO_CONTROL_SET_RATEX).
1010 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX)
1011 {
1012 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
1013 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
1014 Uint32 divider;
1017 if (!pClkxDiv)
1018 return SIO2_EINVAL;
1020 // set clock divider
1021 if (rateX < .354)
1022 rateX = 0.25;
1023 else if (rateX < .707)
1024 rateX = 0.50;
1025 else if (rateX < 1.6)
1026 rateX = 1.00;
1027 else if (rateX < 2.828)
1028 rateX = 2.00;
1029 else
1030 rateX = 4.00;
1031 // if asynchronous then force clock change (assumes osc master)
1032 /*if (pParams->d10tx.mode & D10_SYNC_MASK) {
1033 int dacRate = (pParams->d10tx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
1034 divider = pClkxDiv[oscRateTable[dacRate]];
1035 }
1036 else*/
1037 divider = pClkxDiv[pStatusIn->sampleRateMeasured];
1038 divider /= rateX;
1040 Log_info3("SAP_D10: Inside manageOutput with divider = %d, rateX = %f & input_rate = %d", divider, rateX, pStatusIn->sampleRateMeasured);
1042 // DIT requires 2x clock
1043 if ((mcasp[_MCASP_AFSXCTL_OFFSET] & _MCASP_AFSXCTL_XMOD_MASK) ==
1044 (MCASP_AFSXCTL_XMOD_OF(0x180) << _MCASP_AFSXCTL_XMOD_SHIFT)) {
1045 if (divider < 2)
1046 return (SIO2_EINVAL);
1047 divider >>= 1;
1048 }
1050 mcasp[_MCASP_ACLKXCTL_OFFSET] =
1051 (mcasp[_MCASP_ACLKXCTL_OFFSET] & ~_MCASP_ACLKXCTL_CLKXDIV_MASK) |
1052 (MCASP_ACLKXCTL_CLKXDIV_OF(divider-1) << _MCASP_ACLKXCTL_CLKXDIV_SHIFT);
1053 return 0;
1054 } //manageOutput
1056 // -----------------------------------------------------------------------------
1057 // This function is called by the peripheral driver (DAP) in response to
1058 // various SIO_ctrl() calls made by the framework.
1060 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg)
1061 {
1062 const SAP_D10_Rx_Params *pDapD10RxParams = (const SAP_D10_Rx_Params *)pParams;
1063 const SAP_D10_Tx_Params *pDapD10TxParams = (const SAP_D10_Tx_Params *)pParams;
1064 //Platform_STATUS status;
1066 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
1067 XDAS_Int32 result = 0;
1069 // perform one time hardware initialization
1070 if (!initDone) {
1071 result = initD10 (device);
1072 if (result)
1073 return result;
1074 initDone = 1;
1075 }
1077 switch (code) {
1079 // .............................................................................
1080 // This case provides a regular entry point for managing the specified
1081 // input device. Nominally, this is used to provide lock and sample rate
1082 // status to the framework.
1084 case PAF_SIO_CONTROL_GET_INPUT_STATUS:
1085 if (device->mode != DEV2_INPUT)
1086 return SIO2_EINVAL;
1088 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1089 break;
1091 // .............................................................................
1092 // This case provides a regular entry point for managing the specified
1093 // output device. Nominally this is used to change the output clock dividers
1094 // in the case of double rate output (e.g. DTS 96/24).
1096 case PAF_SIO_CONTROL_SET_RATEX:
1097 // Support only output rate control, for now
1098 if (device->mode != DEV2_OUTPUT)
1099 return (SIO2_EINVAL);
1101 // configure clock divider (bit and frame clocks)
1102 manageOutput (device, pDapD10TxParams, *((float *) arg));
1103 break;
1105 // .............................................................................
1106 // This case is called once when the device is opened/allocated by the framework.
1107 // Here, for both input and output, this allows for configuring all needed
1108 // clocks for proper operation.
1110 case PAF_SIO_CONTROL_OPEN:
1111 if (device->mode == DEV2_INPUT) {
1113 // determine the master clock based on the mode element of the
1114 // parameter configuration.
1115 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
1116 manageInput (device, pDapD10RxParams, NULL);
1118 // select appropriate master clock (but dont force)
1120 clockMuxTx (sel, -1);
1122 }
1123 else {
1125 // Since DAC is a slave to the chosen input, operate the clksel switch appropriately
1126 // Also, this is a create-time (i.e, CTRL_OPEN) only call & not appropriate under
1127 // the periodic manage_output calls.
1128 int sel = (pDapD10TxParams->d10tx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
1129 clockMuxTx (sel, -1);
1130 audk2g_delay(50000); // GJ REVISIT: Without delay between Tx McASP & DAC configs, system aborts.
1131 setAudioDacConfig();
1132 dacHardUnMute ();
1134 // configure clock divider (bit and frame clocks)
1135 manageOutput (device, pDapD10TxParams, 1.0);
1136 }
1137 break;
1139 // .............................................................................
1140 // This case is called once when the device is closed/freed by the framework.
1142 case PAF_SIO_CONTROL_CLOSE:
1143 // If TX0 then signal it is no longer in use by the DACs and
1144 // configure manually to generate ADC clocks. Also hard mute
1145 // the DACs since they are not in use.
1146 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0)) {
1148 dacHardMute ();
1150 // if async then clear forced clock mux
1151 // if asynchronous then force clock change
1152 if (pDapD10TxParams->d10tx.mode & D10_SYNC_MASK)
1153 clockMuxTx (0, 0);
1154 }
1155 break;
1157 // .............................................................................
1158 // These cases are called as appropriate by the framework when there is
1159 // valid output data (UNMUTE) or no valid output (MUTE).
1161 case PAF_SIO_CONTROL_MUTE:
1162 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1163 dacSoftMute ();
1164 break;
1166 case PAF_SIO_CONTROL_UNMUTE:
1167 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1168 dacSoftUnMute ();
1169 break;
1171 // .............................................................................
1172 // This case is called when the device is idled.
1173 // There is no specific handling -- but needed to avoid error return.
1175 case PAF_SIO_CONTROL_IDLE:
1176 break;
1178 // .............................................................................
1179 // Called from the IDL Loop to allow for clock management and the like
1180 // The call is protected by a TSK_disable and HWI_disable so it is safe
1181 // to read/write shared resources.
1183 case PAF_SIO_CONTROL_WATCHDOG:
1184 // call manageInput in case the sample rate has changed resulting
1185 // in no output clocks which may have blocked the audio processing
1186 // thread. This call will reconfigure the AK4588 and restart the clocks.
1187 if (device->mode == DEV2_INPUT)
1188 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1189 break;
1191 // .............................................................................
1192 // Called from DOB_issue to allow for different values of the channel status
1193 // fields of the SPDIF output.
1195 case PAF_SIO_CONTROL_SET_DITSTATUS:
1196 // No action necessary.
1197 break;
1199 case PAF_SIO_CONTROL_SET_WORDSIZE:
1200 if(((pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) != D10_MCLK_OSC)
1201 {
1202 if ((device->mode == DEV2_INPUT) && (arg == 2))
1203 {
1204 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=2");
1205 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_16BITS;
1206 }
1207 else if ((device->mode == DEV2_INPUT) && (arg == 4))
1208 {
1209 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=4");
1210 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_NONE;
1211 }
1212 }
1213 break;
1214 // .............................................................................
1215 // Any other cases are not handled and return an error.
1217 default:
1218 return SIO2_EINVAL;
1219 }
1221 return result;
1222 } //D10_sapControl
1224 // -----------------------------------------------------------------------------
1227 unsigned int HDMIGpioGetState (void) {
1228 return(audk2g_gpioReadInput(AUDK2G_GPIO_PORT_0, AUDK2G_AUDIO_HSR_HMINTz_GPIO));
1229 }
1231 void setD10ClkMux(UInt16 mode)
1232 {
1233 int sel = (mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
1235 // select appropriate master clock
1236 clockMuxTx (sel, 0);
1237 }
1239 XDAS_Int32 D10_init(void *pD10Params)
1240 {
1241 XDAS_Int32 result = 0;
1242 SAP_D10_Rx_Params *pD10RxParams;
1244 // perform one time hardware initialization
1245 if (!initDone) {
1246 result = initD10 (NULL);
1247 if (result) {
1248 return result;
1249 }
1250 initDone = 1;
1251 }
1253 pD10RxParams = (SAP_D10_Rx_Params *)pD10Params;
1254 setD10ClkMux(pD10RxParams->d10rx.mode);
1256 return result;
1257 }
1259 XDAS_Int32 D10_RxControl(const void *pD10RxParams,
1260 XDAS_Int32 code, XDAS_Int32 arg)
1261 {
1262 XDAS_Int32 result = 0;
1264 switch (code) {
1265 case PAF_SIO_CONTROL_GET_INPUT_STATUS:
1266 manageInput(NULL, (const SAP_D10_Rx_Params *)pD10RxParams,
1267 (PAF_SIO_InputStatus *)arg);
1268 break;
1270 default:
1271 break;
1272 }
1274 return result;
1275 }
1277 // EOF