[processor-sdk/performance-audio-sr.git] / pasdk / test_dsp / application / itopo / evmk2g / sap_d10.c
2 /*
3 Copyright (c) 2017, Texas Instruments Incorporated - http://www.ti.com/
4 All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
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12 *
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17 *
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21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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34 */
36 //
37 // I/O device configuration data structure definitions D10 (DA10x EVM).
40 // -----------------------------------------------------------------------------
41 // This file contains the necessary configurations and functions for
42 // using the DA10x Audio DC card in the PA environment. In particular, the
43 // SAP configurations are referenced in the pa(i/y)-evmda10x-io.c files
44 // for use in IOS (Input/Output Switching) shortcuts. Each configuration
45 // contains settings appropriate to the various devices on the DA10x-AudioDC;
46 // the DIR, DACs, ADCs, and DIT output. Also each configuration points to
47 // a common control function (D10_sapControl), which handles the various
48 // requests made by the PA framework.
50 // A note about clocking. There are three different master clocks
51 // available corresponding to the three primary input choices: HDMI, DIR and ADC.
52 //
53 // DIR:
54 // . 512fs @ <= 48kHz
55 // . 256fs @ > 48kHz & <=96 kHz
56 // . 128fs @ > 96kHz
57 // ADC:
58 // . 768fs @ 32kHz
59 // . 512fs @ 48kHz
60 // . 256fs @ 96kHz
61 //
62 // This faciliates the logic used for the McASP transmit sections TX0 (DAC) and
63 // TX2 (DIT) which divide the master clock down to generate bit and frame clocks.
65 // -----------------------------------------------------------------------------
66 // Includes
68 #include <sap_d10.h>
69 #include <audio_dc_cfg.h>
70 #include "vproccmds_a.h"
71 #include "evmc66x_gpio.h" // in "${PDK_INSTALL_PATH}/ti/addon/audk2g/include"
73 #include "dbgBenchmark.h" // PCM high-sampling rate + SRC + CAR benchmarking
76 // -----------------------------------------------------------------------------
77 // Local function declarations
79 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg);
80 static inline XDAS_Int32 initD10 (DEV2_Handle device) ;
81 static XDAS_Int32 clockMuxTx (int sel, int force);
82 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut);
83 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX);
85 void HSR4_readStatus (PAF_SIO_InputStatus *pStatus);
86 unsigned int HDMIGpioGetState (void);
88 /** GPIO number for I2S Header HSR4's ~HMINT pin - GPIO port 0 */
89 #define AUDK2G_AUDIO_HSR_HMINTz_GPIO (105) // missing from audio addon
91 /** GPIO number for I2S Header HSR4's ~RESET pin - GPIO port 0 */
92 #define AUDK2G_AUDIO_HSR_RESETz_GPIO (104) // missing from audio addon
94 // -----------------------------------------------------------------------------
95 // State machine variables and defines
97 // flag to facilitate one time initialization of DA10x Audio hardware
98 // 0 ==> not initialized, 1 ==> initialized
99 static char initDone = 0;
101 // input status
102 static PAF_SIO_InputStatus primaryStatus =
103 {
104 0, // lock
105 PAF_IEC_AUDIOMODE_UNKNOWN, // nonaudio
106 PAF_IEC_PREEMPHASIS_UNKNOWN, // emphasis
107 PAF_SAMPLERATE_UNKNOWN, // sampleRateMeasured
108 PAF_SAMPLERATE_UNKNOWN, // sampleRateData
109 0,0,0, // unused
110 };
113 // The McASP outputs (both for DAC and DIT) receive a high speed clock
114 // and in turn generate a bit and frame clock. The needed clock divider
115 // values are kept here for easy lookup.
116 unsigned char *pClkxDiv = NULL;
118 static const unsigned char clkxDivDIR[PAF_SAMPLERATE_N] =
119 {
120 0x2, //PAF_SAMPLERATE_UNKNOWN
121 0x8, //PAF_SAMPLERATE_NONE
122 0x8, //PAF_SAMPLERATE_32000HZ
123 0x2, //PAF_SAMPLERATE_44100HZ
124 0x2, //PAF_SAMPLERATE_48000HZ
125 0x4, //PAF_SAMPLERATE_88200HZ
126 0x2, //PAF_SAMPLERATE_96000HZ
127 0x2, //PAF_SAMPLERATE_192000HZ
128 0x4, //PAF_SAMPLERATE_64000HZ
129 0x2, //PAF_SAMPLERATE_128000HZ
130 0x2, //PAF_SAMPLERATE_176400HZ
131 0x8, //PAF_SAMPLERATE_8000HZ
132 0x8, //PAF_SAMPLERATE_11025HZ
133 0x8, //PAF_SAMPLERATE_12000HZ
134 0x8, //PAF_SAMPLERATE_16000HZ
135 0x8, //PAF_SAMPLERATE_22050HZ
136 0x8, //PAF_SAMPLERATE_24000HZ
137 };
140 static const unsigned char clkxDivADC[PAF_SAMPLERATE_N] =
141 {
142 0x8, //PAF_SAMPLERATE_UNKNOWN
143 0x8, //PAF_SAMPLERATE_NONE
144 0xC, //PAF_SAMPLERATE_32000HZ
145 0x8, //PAF_SAMPLERATE_44100HZ
146 0x8, //PAF_SAMPLERATE_48000HZ
147 0x4, //PAF_SAMPLERATE_88200HZ
148 0x4, //PAF_SAMPLERATE_96000HZ
149 0x2, //PAF_SAMPLERATE_192000HZ
150 0x4, //PAF_SAMPLERATE_64000HZ
151 0x2, //PAF_SAMPLERATE_128000HZ
152 0x2, //PAF_SAMPLERATE_176400HZ
153 0x8, //PAF_SAMPLERATE_8000HZ
154 0x8, //PAF_SAMPLERATE_11025HZ
155 0x8, //PAF_SAMPLERATE_12000HZ
156 0x8, //PAF_SAMPLERATE_16000HZ
157 0x8, //PAF_SAMPLERATE_22050HZ
158 0x8, //PAF_SAMPLERATE_24000HZ
159 };
161 static const unsigned char clkxDivHDMI[PAF_SAMPLERATE_N] =
162 {
163 0x2, //PAF_SAMPLERATE_UNKNOWN
164 0x2, //PAF_SAMPLERATE_NONE
165 0x8, //PAF_SAMPLERATE_32000HZ
166 0x2, //PAF_SAMPLERATE_44100HZ
167 0x2, //PAF_SAMPLERATE_48000HZ
168 0x2, //PAF_SAMPLERATE_88200HZ
169 0x2, //PAF_SAMPLERATE_96000HZ
170 0x2, //PAF_SAMPLERATE_192000HZ
171 0x4, //PAF_SAMPLERATE_64000HZ
172 0x2, //PAF_SAMPLERATE_128000HZ
173 0x2, //PAF_SAMPLERATE_176400HZ
174 0x8, //PAF_SAMPLERATE_8000HZ
175 0x8, //PAF_SAMPLERATE_11025HZ
176 0x8, //PAF_SAMPLERATE_12000HZ
177 0x8, //PAF_SAMPLERATE_16000HZ
178 0x8, //PAF_SAMPLERATE_22050HZ
179 0x8, //PAF_SAMPLERATE_24000HZ
180 };
182 // The ADCs, when operating as the master input, can only
183 // generate a limited set of audio sample rates since the clock
184 // is derived from AUXCLK which is the oscillator connected to the DSP.
185 // This table faciliates the access and definition of these rates.
186 static const Uint16 oscRateTable[8] =
187 {
188 PAF_SAMPLERATE_UNKNOWN, // 0
189 PAF_SAMPLERATE_32000HZ,
190 PAF_SAMPLERATE_44100HZ, // D10_RATE_44_1KHZ
191 PAF_SAMPLERATE_48000HZ,
192 PAF_SAMPLERATE_88200HZ, // D10_RATE_88_2KHZ
193 PAF_SAMPLERATE_96000HZ,
194 PAF_SAMPLERATE_176400HZ, // D10_RATE_176_4KHZ
195 PAF_SAMPLERATE_192000HZ
196 };
198 static const Uint16 RateTable_hdmi[8] =
199 {
200 PAF_SAMPLERATE_UNKNOWN, // HSDIO_AudioFreq_RESERVED
201 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
202 PAF_SAMPLERATE_44100HZ, // HSDIO_AudioFreq_44_1K
203 PAF_SAMPLERATE_48000HZ, // HSDIO_AudioFreq_48K
204 PAF_SAMPLERATE_88200HZ, // HSDIO_AudioFreq_88_2K
205 PAF_SAMPLERATE_96000HZ, // HSDIO_AudioFreq_96_4K
206 PAF_SAMPLERATE_176400HZ, // HSDIO_AudioFreq_176_4K
207 PAF_SAMPLERATE_192000HZ // HSDIO_AudioFreq_192K
208 };
210 static const Uint16 RateTable_spdif[4] =
211 {
212 PAF_SAMPLERATE_44100HZ, // AudioFreq_44_1K
213 PAF_SAMPLERATE_48000HZ, // AudioFreq_48K
214 PAF_SAMPLERATE_UNKNOWN, // AudioFreq_RESERVED
215 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
216 };
219 // base mcasp addresses for easy lookup
220 static volatile Uint32 * mcaspAddr[_MCASP_PORT_CNT] =
221 {
222 (volatile Uint32 *) _MCASP_BASE_PORT0,
223 (volatile Uint32 *) _MCASP_BASE_PORT1,
224 (volatile Uint32 *) _MCASP_BASE_PORT2
225 };
227 // The DA10x HW is configured for the DAC's mute lines to be operated based
228 // on McASP0's AMUTE (out) line. This is the hard mute.
229 static inline void dacHardMute (void) {
230 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
231 mcasp0[_MCASP_PDOUT_OFFSET] |= _MCASP_PDOUT_AMUTE_MASK;
232 }
233 static inline void dacHardUnMute (void) {
234 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
235 mcasp0[_MCASP_PDOUT_OFFSET] &= ~_MCASP_PDOUT_AMUTE_MASK;
236 mcasp0[_MCASP_AMUTE_OFFSET] |= MCASP_AMUTE_MUTEN_ERRLOW;
237 }
239 // How should the PCM18x DAC's soft mute functionality be used here?
240 // i.e, as different from the hard mute? need to review.
241 static inline void dacSoftMute (void) {
242 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
243 mcasp0[6] = 0x000 ;
244 mcasp0[6] = 0x400 ;
245 }
246 static inline void dacSoftUnMute (void) {
247 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
248 mcasp0[6] = 0x000 ;
249 mcasp0[6] = 0x400 ;
250 }
252 // -----------------------------------------------------------------------------
253 // McASP Input Configuration Definitions
255 static const MCASP_ConfigRcv rxConfigDIR =
256 {
257 MCASP_RMASK_OF(0xFFFFFFFF),
258 MCASP_RFMT_RMK(
259 MCASP_RFMT_RDATDLY_1BIT,
260 MCASP_RFMT_RRVRS_MSBFIRST,
261 MCASP_RFMT_RPAD_RPBIT,
262 MCASP_RFMT_RPBIT_OF(0),
263 MCASP_RFMT_RSSZ_32BITS,
264 MCASP_RFMT_RBUSEL_DAT,
265 MCASP_RFMT_RROT_NONE),
266 MCASP_AFSRCTL_RMK(
267 MCASP_AFSRCTL_RMOD_OF(2),
268 MCASP_AFSRCTL_FRWID_WORD,
269 MCASP_AFSRCTL_FSRM_EXTERNAL,
270 MCASP_AFSRCTL_FSRP_ACTIVELOW),
271 MCASP_ACLKRCTL_RMK(
272 MCASP_ACLKRCTL_CLKRP_RISING,
273 MCASP_ACLKRCTL_CLKRM_EXTERNAL,
274 MCASP_ACLKRCTL_CLKRDIV_DEFAULT),
275 MCASP_AHCLKRCTL_RMK(
276 MCASP_AHCLKRCTL_HCLKRM_EXTERNAL,
277 MCASP_AHCLKRCTL_HCLKRP_RISING,
278 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
279 MCASP_RTDM_OF(3),
280 MCASP_RINTCTL_DEFAULT,
281 MCASP_RCLKCHK_DEFAULT
282 };
284 static const MCASP_ConfigRcv rxConfigADC =
285 {
286 MCASP_RMASK_OF(0xFFFFFFFF),
287 MCASP_RFMT_RMK(
288 MCASP_RFMT_RDATDLY_1BIT,
289 MCASP_RFMT_RRVRS_MSBFIRST,
290 MCASP_RFMT_RPAD_RPBIT,
291 MCASP_RFMT_RPBIT_OF(0),
292 MCASP_RFMT_RSSZ_32BITS,
293 MCASP_RFMT_RBUSEL_DAT,
294 MCASP_RFMT_RROT_NONE),
295 MCASP_AFSRCTL_RMK(
296 MCASP_AFSRCTL_RMOD_OF(2),
297 MCASP_AFSRCTL_FRWID_WORD,
298 MCASP_AFSRCTL_FSRM_INTERNAL,
299 MCASP_AFSRCTL_FSRP_ACTIVEHIGH),
300 MCASP_ACLKRCTL_RMK(
301 MCASP_ACLKRCTL_CLKRP_RISING,
302 MCASP_ACLKRCTL_CLKRM_INTERNAL,
303 MCASP_ACLKXCTL_CLKXDIV_OF(7)),
304 MCASP_AHCLKRCTL_RMK(
305 MCASP_AHCLKRCTL_HCLKRM_INTERNAL,
306 MCASP_AHCLKRCTL_HCLKRP_RISING,
307 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
308 MCASP_RTDM_OF(3),
309 MCASP_RINTCTL_DEFAULT,
310 MCASP_RCLKCHK_DEFAULT
311 };
313 // -----------------------------------------------------------------------------
314 // McASP Output Configuration Definitions
316 static const MCASP_ConfigXmt txConfigDAC =
317 {
318 MCASP_XMASK_OF(0xFFFFFFFF),
319 MCASP_XFMT_RMK(
320 MCASP_XFMT_XDATDLY_1BIT,
321 MCASP_XFMT_XRVRS_MSBFIRST,
322 MCASP_XFMT_XPAD_ZERO,
323 MCASP_XFMT_XPBIT_DEFAULT,
324 MCASP_XFMT_XSSZ_32BITS,
325 MCASP_XFMT_XBUSEL_DAT,
326 MCASP_XFMT_XROT_NONE),
327 MCASP_AFSXCTL_RMK(
328 MCASP_AFSXCTL_XMOD_OF(2),
329 MCASP_AFSXCTL_FXWID_WORD,
330 MCASP_AFSXCTL_FSXM_INTERNAL,
331 MCASP_AFSXCTL_FSXP_ACTIVELOW),
332 MCASP_ACLKXCTL_RMK(
333 MCASP_ACLKXCTL_CLKXP_FALLING,
334 MCASP_ACLKXCTL_ASYNC_ASYNC,
335 MCASP_ACLKXCTL_CLKXM_INTERNAL,
336 MCASP_ACLKXCTL_CLKXDIV_DEFAULT),
337 MCASP_AHCLKXCTL_RMK(
338 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
339 MCASP_AHCLKXCTL_HCLKXP_FALLING,
340 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
341 MCASP_XTDM_OF(3),
342 MCASP_XINTCTL_DEFAULT,
343 MCASP_XCLKCHK_DEFAULT
344 };
346 static const MCASP_ConfigXmt txConfigDACSlave =
347 {
348 MCASP_XMASK_OF(0xFFFFFFFF),
349 MCASP_XFMT_RMK(
350 MCASP_XFMT_XDATDLY_1BIT,
351 MCASP_XFMT_XRVRS_MSBFIRST,
352 MCASP_XFMT_XPAD_ZERO,
353 MCASP_XFMT_XPBIT_DEFAULT,
354 MCASP_XFMT_XSSZ_32BITS,
355 MCASP_XFMT_XBUSEL_DAT,
356 MCASP_XFMT_XROT_NONE),
357 MCASP_AFSXCTL_RMK(
358 MCASP_AFSXCTL_XMOD_OF(2),
359 MCASP_AFSXCTL_FXWID_WORD,
360 MCASP_AFSXCTL_FSXM_INTERNAL,
361 MCASP_AFSXCTL_FSXP_ACTIVELOW),
362 MCASP_ACLKXCTL_RMK(
363 MCASP_ACLKXCTL_CLKXP_FALLING,
364 MCASP_ACLKXCTL_ASYNC_ASYNC,
365 MCASP_ACLKXCTL_CLKXM_INTERNAL,
366 MCASP_ACLKXCTL_CLKXDIV_OF(1)),
367 MCASP_AHCLKXCTL_RMK(
368 MCASP_AHCLKXCTL_HCLKXM_INTERNAL,
369 MCASP_AHCLKXCTL_HCLKXP_FALLING,
370 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
371 MCASP_XTDM_OF(3),
372 MCASP_XINTCTL_DEFAULT,
373 MCASP_XCLKCHK_DEFAULT
374 };
376 static const MCASP_ConfigXmt txConfigDIT =
377 {
378 MCASP_XMASK_OF(0x00FFFFFF),
379 MCASP_XFMT_RMK(
380 MCASP_XFMT_XDATDLY_1BIT,
381 MCASP_XFMT_XRVRS_LSBFIRST,
382 MCASP_XFMT_XPAD_DEFAULT,
383 MCASP_XFMT_XPBIT_DEFAULT,
384 MCASP_XFMT_XSSZ_32BITS,
385 MCASP_XFMT_XBUSEL_DAT,
386 MCASP_XFMT_XROT_NONE),
387 MCASP_AFSXCTL_RMK(
388 MCASP_AFSXCTL_XMOD_OF(0x180),
389 MCASP_AFSXCTL_FXWID_BIT,
390 MCASP_AFSXCTL_FSXM_INTERNAL,
391 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
392 MCASP_ACLKXCTL_RMK(
393 MCASP_ACLKXCTL_CLKXP_FALLING,
394 MCASP_ACLKXCTL_ASYNC_ASYNC,
395 MCASP_ACLKXCTL_CLKXM_INTERNAL,
396 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
397 MCASP_AHCLKXCTL_RMK(
398 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
399 MCASP_AHCLKXCTL_HCLKXP_FALLING,
400 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
401 MCASP_XTDM_OF(0xFFFFFFFF),
402 MCASP_XINTCTL_DEFAULT,
403 MCASP_XCLKCHK_DEFAULT
404 };
406 #if 0
407 static const MCASP_ConfigXmt txConfigDIT_16bit =
408 {
409 MCASP_XMASK_OF(0x0000FFFF),
410 MCASP_XFMT_RMK(
411 MCASP_XFMT_XDATDLY_1BIT,
412 MCASP_XFMT_XRVRS_LSBFIRST,
413 MCASP_XFMT_XPAD_DEFAULT,
414 MCASP_XFMT_XPBIT_DEFAULT,
415 MCASP_XFMT_XSSZ_32BITS,
416 MCASP_XFMT_XBUSEL_DAT,
417 MCASP_XFMT_XROT_24BITS),
418 MCASP_AFSXCTL_RMK(
419 MCASP_AFSXCTL_XMOD_OF(0x180),
420 MCASP_AFSXCTL_FXWID_BIT,
421 MCASP_AFSXCTL_FSXM_INTERNAL,
422 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
423 MCASP_ACLKXCTL_RMK(
424 MCASP_ACLKXCTL_CLKXP_FALLING,
425 MCASP_ACLKXCTL_ASYNC_ASYNC,
426 MCASP_ACLKXCTL_CLKXM_INTERNAL,
427 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
428 MCASP_AHCLKXCTL_RMK(
429 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
430 MCASP_AHCLKXCTL_HCLKXP_FALLING,
431 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
432 MCASP_XTDM_OF(0xFFFFFFFF),
433 MCASP_XINTCTL_DEFAULT,
434 MCASP_XCLKCHK_DEFAULT
435 };
436 #endif
438 // -----------------------------------------------------------------------------
439 // DAP Input Parameter Definitions
441 const SAP_D10_Rx_Params SAP_D10_RX_DIR =
442 {
443 sizeof (SAP_D10_Rx_Params), // size
444 "SAP", // name
445 MCASP_DEV2, // moduleNum --> mcasp #
446 (Void *)&rxConfigDIR, // pConfig
447 4, // wordSize (unused)
448 24, // precision (unused)
449 D10_sapControl, // control
450 0x00000020, // pinMask
451 (D10_MCLK_DIR << D10_MCLK_SHIFT), // mode
452 0,0 // unused[2]
453 };
455 const SAP_D10_Rx_Params SAP_D10_RX_ADC_44100HZ =
456 {
457 sizeof (SAP_D10_Rx_Params), // size
458 "SAP", // name
459 MCASP_DEV1, // moduleNum --> mcasp #
460 (Void *)&rxConfigADC, // pConfig
461 4, // wordSize (unused)
462 24, // precision (unused)
463 D10_sapControl, // control
464 0xE000000F, // pinMask
465 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
466 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
467 0,0 // unused[2]
468 };
470 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_44100HZ =
471 {
472 sizeof (SAP_D10_Rx_Params), // size
473 "SAP", // name
474 MCASP_DEV1, // moduleNum --> mcasp #
475 (Void *)&rxConfigADC, // pConfig
476 -1, // wordSize (unused)
477 -1, // precision (unused)
478 D10_sapControl, // control
479 0xE0000007, // pinMask
480 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
481 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
482 0,0 // unused[2]
483 };
485 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_44100HZ =
486 {
487 sizeof (SAP_D10_Rx_Params), // size
488 "SAP", // name
489 MCASP_DEV1, // moduleNum --> mcasp #
490 (Void *)&rxConfigADC, // pConfig
491 -1, // wordSize (unused)
492 -1, // precision (unused)
493 D10_sapControl, // control
494 0xE0000001, // pinMask
495 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
496 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
497 0,0 // unused[2]
498 };
500 const SAP_D10_Rx_Params SAP_D10_RX_ADC_88200HZ =
501 {
502 sizeof (SAP_D10_Rx_Params), // size
503 "SAP", // name
504 MCASP_DEV1, // moduleNum --> mcasp #
505 (Void *)&rxConfigADC, // pConfig
506 -1, // wordSize (unused)
507 -1, // precision (unused)
508 D10_sapControl, // control
509 0xE000000F, // pinMask
510 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
511 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
512 0,0 // unused[2]
513 };
515 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_88200HZ =
516 {
517 sizeof (SAP_D10_Rx_Params), // size
518 "SAP", // name
519 MCASP_DEV1, // moduleNum --> mcasp #
520 (Void *)&rxConfigADC, // pConfig
521 -1, // wordSize (unused)
522 -1, // precision (unused)
523 D10_sapControl, // control
524 0xE0000007, // pinMask
525 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
526 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
527 0,0 // unused[2]
528 };
530 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_88200HZ =
531 {
532 sizeof (SAP_D10_Rx_Params), // size
533 "SAP", // name
534 MCASP_DEV1, // moduleNum --> mcasp #
535 (Void *)&rxConfigADC, // pConfig
536 -1, // wordSize (unused)
537 -1, // precision (unused)
538 D10_sapControl, // control
539 0xE0000001, // pinMask
540 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
541 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
542 0,0 // unused[2]
543 };
546 const SAP_D10_Rx_Params SAP_D10_RX_HDMI_STEREO =
547 {
548 sizeof (SAP_D10_Rx_Params), // size
549 "SAP", // name
550 MCASP_DEV0, // moduleNum --> mcasp #
551 (Void *)&rxConfigDIR, // pConfig
552 4, // wordSize (unused)
553 -1, // precision (unused)
554 D10_sapControl, // control
555 0x00001000, // pinMask
556 (D10_MODE_HDMI << D10_MODE_SHIFT) |
557 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
558 0,0 // unused[2]
559 };
561 const SAP_D10_Rx_Params SAP_D10_RX_HDMI =
562 {
563 sizeof (SAP_D10_Rx_Params), // size
564 "SAP", // name
565 MCASP_DEV0, // moduleNum --> mcasp #
566 (Void *)&rxConfigDIR, // pConfig
567 4, // wordSize (unused)
568 -1, // precision (unused)
569 D10_sapControl, // control
570 0x0000F000, // pinMask
571 (D10_MODE_HDMI << D10_MODE_SHIFT) |
572 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
573 0,0 // unused[2]
574 };
576 // -----------------------------------------------------------------------------
577 // SAP Output Parameter Definitions
579 const SAP_D10_Tx_Params SAP_D10_TX_DAC =
580 {
581 sizeof (SAP_D10_Tx_Params), // size
582 "SAP", // name
583 MCASP_DEV0, // moduleNum --> mcasp #
584 (Void *)&txConfigDAC, // pConfig
585 4, // wordSize (in bytes)
586 24, // precision (in bits)
587 D10_sapControl, // control
588 0x1600000F, // pinMask
589 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
590 0,0,0 // unused[3]
591 };
593 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC =
594 {
595 sizeof (SAP_D10_Tx_Params), // size
596 "SAP", // name
597 MCASP_DEV0, // moduleNum --> mcasp #
598 (Void *)&txConfigDAC, // pConfig
599 4, // wordSize (in bytes)
600 24, // precision (in bits)
601 D10_sapControl, // control
602 0x16000001, // pinMask
603 0, // mode
604 0,0,0 // unused[3]
605 };
607 const SAP_D10_Tx_Params SAP_D10_TX_DIT =
608 {
609 sizeof (SAP_D10_Tx_Params), // size
610 "SAP", // name
611 MCASP_DEV2, // moduleNum --> mcasp #
612 (Void *) &txConfigDIT, // pConfig
613 3, // wordSize (in bytes)
614 24, // precision (in bits)
615 D10_sapControl, // control
616 0x1C000001, // pinMask
617 0, // mode
618 0,0,0 // unused[3]
619 };
621 const SAP_D10_Tx_Params SAP_D10_TX_DAC_SLAVE =
622 {
623 sizeof (SAP_D10_Tx_Params), // size
624 "SAP", // name
625 MCASP_DEV0, // moduleNum --> mcasp #
626 (Void *)&txConfigDACSlave, // pConfig
627 4, // wordSize (in bytes)
628 24, // precision (in bits)
629 D10_sapControl, // control
630 0x1E00000F, // pinMask
631 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
632 0,0,0 // unused[3]
633 };
635 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC_SLAVE =
636 {
637 sizeof (SAP_D10_Tx_Params), // size
638 "SAP", // name
639 MCASP_DEV0, // moduleNum --> mcasp #
640 (Void *)&txConfigDAC, // pConfig
641 4, // wordSize (in bytes)
642 24, // precision (in bits)
643 D10_sapControl, // control
644 0x16000001, // pinMask
645 0, // mode
646 0,0,0 // unused[3]
647 };
649 const SAP_D10_Tx_Params SAP_D10_TX_DAC_12CH =
650 {
651 sizeof (SAP_D10_Tx_Params), // size
652 "SAP", // name
653 MCASP_DEV0, // moduleNum --> mcasp #
654 (Void *)&txConfigDAC, // pConfig
655 4, // wordSize (in bytes)
656 24, // precision (in bits)
657 D10_sapControl, // control
658 0x1600003F, // pinMask
659 0, // mode
660 0,0,0 // unused[3]
661 };
663 const SAP_D10_Tx_Params SAP_D10_TX_DAC_16CH =
664 {
665 sizeof (SAP_D10_Tx_Params), // size
666 "SAP", // name
667 MCASP_DEV0, // moduleNum --> mcasp #
668 (Void *)&txConfigDAC, // pConfig
669 4, // wordSize (in bytes)
670 24, // precision (in bits)
671 D10_sapControl, // control
672 0x160000FF, // pinMask
673 0, // mode
674 0,0,0 // unused[3]
675 };
678 // -----------------------------------------------------------------------------
679 // One time initialization of the DA10x audio hardware.
681 /* DAC default configuration parameters */
682 DacConfig dacCfg =
683 {
684 AUDK2G_DAC_AMUTE_CTRL_SCKI_LOST, /* Amute event */
685 0, /* Amute control */
686 AUDK2G_DAC_SAMPLING_MODE_SINGLE_RATE, /* Sampling mode */
687 AUDK2G_DAC_DATA_FORMAT_I2S, /* Data format */
688 0, /* Soft mute control */
689 AUDK2G_DAC_ATTENUATION_WIDE_RANGE, /* Attenuation mode */
690 AUDK2G_DAC_DEEMP_44KHZ, /* De-emph control */
691 100 /* Volume */
692 };
693 /* ADC default configuration parameters */
694 AdcConfig adcCfg =
695 {
696 90, /* ADC gain */
697 AUDK2G_ADC_INL_SE_VINL1, /* Left input mux for ADC1L */
698 AUDK2G_ADC_INL_SE_VINL2, /* Left input mux for ADC2L */
699 AUDK2G_ADC_INR_SE_VINR1, /* Right input mux for ADC1R */
700 AUDK2G_ADC_INR_SE_VINR2, /* Right input mux for ADC2R */
701 AUDK2G_ADC_RX_WLEN_24BIT, /* ADC word length */
702 AUDK2G_ADC_DATA_FORMAT_I2S, /* ADC data format */
703 0
704 };
706 Audk2g_STATUS setAudioDacConfig(void)
707 {
708 Audk2g_STATUS status;
710 /* Initialize Audio DAC module */
711 status = audioDacConfig(AUDK2G_DAC_DEVICE_ALL, &dacCfg); // defined in sap\audio_dc_cfg.c
712 if (status)
713 Log_info0("SAP_D10: Audio DAC Configuration Failed!!!\n");
714 return status;
716 }
718 // Configure GPIO for HSR HDMI signaling. This needs to be added to audk2g_AudioInit()
719 // in ti\addon\audk2g\src\audk2g.c.
720 Audk2g_STATUS audk2g_AudioInit_Extra()
721 {
722 /* Configure GPIO for HSR HDMI Signaling - GPIO0 104 (~RESET) & 105 (~HMINT) */
723 audk2g_pinMuxSetMode(114, AUDK2G_PADCONFIG_MUX_MODE_QUATERNARY);
724 audk2g_gpioSetDirection(AUDK2G_GPIO_PORT_0, AUDK2G_AUDIO_HSR_HMINTz_GPIO, AUDK2G_GPIO_IN);
726 audk2g_pinMuxSetMode(113, AUDK2G_PADCONFIG_MUX_MODE_QUATERNARY);
727 audk2g_gpioSetDirection(AUDK2G_GPIO_PORT_0, AUDK2G_AUDIO_HSR_RESETz_GPIO, AUDK2G_GPIO_OUT);
728 audk2g_gpioSetOutput(AUDK2G_GPIO_PORT_0, AUDK2G_AUDIO_HSR_RESETz_GPIO);
730 return Audk2g_EOK;
731 }
733 static inline XDAS_Int32 initD10 (DEV2_Handle device)
734 {
735 Audk2g_STATUS status = Audk2g_EOK;
737 /* Initialize common audio configurations */
738 status = audk2g_AudioInit(); // defined in in ti\addon\audk2g\src\audk2g.c
739 if(status != Audk2g_EOK)
740 {
741 Log_info0("audk2g_AudioInit Failed!\n");
742 return status;
743 }
744 else
745 Log_info0("audk2g_AudioInit Passed!\n");
747 status = (Audk2g_STATUS)audk2g_AudioInit_Extra();
748 if(status != Audk2g_EOK)
749 {
750 Log_info0("audk2g_AudioInit_Extra Failed!\n");
751 return status;
752 }
753 else
754 Log_info0("audk2g_AudioInit_Extra Passed!\n");
756 /* Initialize Audio ADC module */
757 status = audioAdcConfig(AUDK2G_ADC_DEVICE_ALL, &adcCfg);
758 if(status != Audk2g_EOK)
759 {
760 Log_info0("Audio ADC Configuration Failed!\n");
761 return status;
762 }
763 else
764 Log_info0("Audio ADC Configuration Passed!\n");
766 /* Setup DIR 9001 for SPDIF input operation */
767 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
768 status = audioDirConfig();
769 if(status != Audk2g_EOK)
770 {
771 Log_info0("Audio DIR Init Failed!\n");
772 return status;
773 }
774 else
775 Log_info0("Audio DIR Init Passed!\n");
777 #if 1
778 /* Setup HSR41 for HDMI input operation */
779 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
780 /* Initialize the HDMI Card */
781 while(HDMIGpioGetState());
782 status = audioHDMIConfig();
783 if(status != Audk2g_EOK)
784 {
785 Log_info0("Audio HDMI Init Failed!\n");
786 return status;
787 }
788 else
789 Log_info0("Audio HDMI Init Passed!\n");
790 #endif
792 status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_DIR);
793 audk2g_delay(50000); // Without delay between these 2 calls system aborts.
794 status = setAudioDacConfig();
796 Log_info1("Leaving initD10 with status = %d", status);
798 return status;
800 } //initD10
802 // -----------------------------------------------------------------------------
803 // The McASP TX section is *only* used as a master clock mux.
804 // Mux functionality is achieved by selecting either external high
805 // speed clocks (DIR/HDMI) or the internal AUXCLK (Audio_OSC). This is divided down
806 // output via ACLKX0 which is connected to the high speed input
807 // of TX0 (DAC) and TX2 (DIT).
808 #define AUDK2G_AUDIO_CLK_SRC_OSC (AUDK2G_AUDIO_CLK_SRC_I2S+1) //temporary, to add AUDK2G_AUDIO_CLK_SRC_OSC to audk2g_audio.h
810 static XDAS_Int32 clockMuxTx (int sel, int force)
811 {
812 Audk2g_STATUS status = 0;
813 // select clkxDiv table
814 if (sel == D10_MCLK_DIR)
815 {
816 status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_DIR);
817 pClkxDiv = (unsigned char *) clkxDivDIR;
818 }
819 else if (sel == D10_MCLK_HDMI)
820 {
821 status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_I2S);
822 pClkxDiv = (unsigned char *) clkxDivHDMI;
823 }
824 else if (sel == D10_MCLK_OSC)
825 {
826 status = audk2g_AudioSelectClkSrc((Audk2gAudioClkSrc)AUDK2G_AUDIO_CLK_SRC_OSC);
827 pClkxDiv = (unsigned char *) clkxDivADC;
828 }
829 Log_info1("SAP_D10: Inside clockMuxTx with sel = %d", sel);
831 audk2g_delay(20000);
833 return status;
834 } //clockMuxTx
837 // -----------------------------------------------------------------------------
838 // This function returns the input status of the specified device.
839 // This is called once when the device is opened
840 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter
841 // (PAF_SIO_CONTROL_GET_INPUT_STATUS).
842 int gHmint_ctr = 0, gNonAudio = 0, gLockStatus=0, gPrevAudio=0, gPrevLock=0;
843 int gSync_ctr, gLock_ctr, gAudioErr_ctr, gNonAudio_ctr = 0;
845 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut)
846 {
847 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
848 //volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
849 //volatile Uint32 *mcasp1 = (volatile Uint32 *) _MCASP_BASE_PORT1;
850 //volatile Uint32 *mcasp2 = (volatile Uint32 *) _MCASP_BASE_PORT2;
852 //Platform_STATUS status;
854 static int PrevSampRate = 0;
855 int RateHdmi =0;
857 /* Mode & MCLK info embedded statically in the Rx IO definition for SPDIF Input */
858 if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_DIR) &
859 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD))
860 {
861 pStatusIn->lock = !(audk2g_AudioDirGetClkStatus());
862 pStatusIn->nonaudio = !(audk2g_AudioDirGetAudioStatus());
863 pStatusIn->emphasis = audk2g_AudioDirGetEmphStatus();
864 pStatusIn->sampleRateMeasured = RateTable_spdif[audk2g_AudioDirGetFsOut()];
865 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
866 PrevSampRate = pStatusIn->sampleRateMeasured;
868 // GJ: Is this needed? Probably not.
869 // GJ: Mute Control during input-change seemingly intended.
870 //mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
871 //mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
873 }
874 /* Mode & MCLK info embedded statically in the Rx IO definition for ANALOG/ADC Input */
875 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_OSC) &
876 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD)) {
877 int adcRate = (pParams->d10rx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
879 pStatusIn->lock = 1;
880 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
881 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
882 pStatusIn->sampleRateMeasured = oscRateTable[adcRate];
883 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
885 }
886 /* Mode & MCLK info embedded statically in the Rx IO definition for HDMI */
887 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_HDMI) &
888 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_HDMI))
889 {
891 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
893 #ifndef ___ENABLE_BENCHMARK_PCMHSR_SRC_CAR_ //TODO: For all the cases it works.
894 //
895 // Input interface rate hard-coded to 192 kHz to avoid I2C transactions.
896 // Temporary fix works for EC3 and MLP/MAT formats.
897 //
898 pStatusIn->lock = 1;
899 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
900 /*RateHdmi = HSDIO_AudioFreq_192K;
901 pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
902 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured; */
903 if(!HDMIGpioGetState())
904 {
905 clear_hdmi_hmint();
906 gHmint_ctr++;
908 RateHdmi=read_hdmi_samprate();
909 pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
910 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
911 PrevSampRate = pStatusIn->sampleRateMeasured;
912 }
913 else
914 {
915 pStatusIn->sampleRateMeasured = PrevSampRate;
916 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
917 }
918 #else // _ENABLE_BENCHMARK_PCMHSR_SRC_CAR_
919 //
920 // Need to update input interface rate by consulting HSR4 over I2C for benchmarking configuration.
921 //
922 if(!HDMIGpioGetState())
923 {
924 clear_hdmi_hmint();
925 gHmint_ctr++;
927 RateHdmi=read_hdmi_samprate();
928 pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
929 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
930 PrevSampRate = pStatusIn->sampleRateMeasured;
931 /*
932 switch(read_hdmi_errstatus())
933 {
934 case HSDIO_AudioErr_NO_ERROR:
935 {
936 gPrevLock=pStatusIn->lock;
937 gPrevAudio=pStatusIn->nonaudio;
938 pStatusIn->lock = 1;
939 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
940 break;
941 }
942 case HSDIO_AudioErr_AUDIO_NO_PLL_LOCK:
943 {
944 gLock_ctr++;
945 pStatusIn->lock = 0;
946 //pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
947 break;
948 }
949 case HSDIO_AudioErr_AUDIO_NO_AUDIO:
950 {
951 gAudioErr_ctr++;
952 //pStatusIn->lock = 1;
953 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_NONAUDIO;
954 break;
955 }
956 default:
957 while(1); // Control shouldn't be here.
958 }
960 if(HSDIO_AudioMClk_128X != read_hdmi_clockstatus())
961 {
962 gLock_ctr++;
963 pStatusIn->lock = 0;
964 }
965 else if (HSDIO_AudioPresent_HAS_AUDIO != read_hdmi_audiostatus())
966 {
967 gNonAudio_ctr++;
968 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_NONAUDIO;
969 }*/
971 }
972 else
973 {
974 pStatusIn->sampleRateMeasured = PrevSampRate;
975 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
976 }
977 #endif // _ENABLE_BENCHMARK_PCMHSR_SRC_CAR_
978 }
980 else
981 return -1; // Control shouldn't be here!
983 gNonAudio=pStatusIn->nonaudio;
984 gLockStatus=pStatusIn->lock;
986 // update another status if requested
987 if (pStatusOut)
988 *pStatusOut = *pStatusIn;
990 return 0;
991 } //manageInput
994 // -----------------------------------------------------------------------------
995 // This function configures the McASP TX clock dividers based on the
996 // master clock rate. This is called once when the device is opened
997 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter (PAF_SIO_CONTROL_SET_RATEX).
999 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX)
1000 {
1001 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
1002 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
1003 Uint32 divider;
1006 if (!pClkxDiv)
1007 return SIO2_EINVAL;
1009 // set clock divider
1010 if (rateX < .354)
1011 rateX = 0.25;
1012 else if (rateX < .707)
1013 rateX = 0.50;
1014 else if (rateX < 1.6)
1015 rateX = 1.00;
1016 else if (rateX < 2.828)
1017 rateX = 2.00;
1018 else
1019 rateX = 4.00;
1020 // if asynchronous then force clock change (assumes osc master)
1021 /*if (pParams->d10tx.mode & D10_SYNC_MASK) {
1022 int dacRate = (pParams->d10tx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
1023 divider = pClkxDiv[oscRateTable[dacRate]];
1024 }
1025 else*/
1026 divider = pClkxDiv[pStatusIn->sampleRateMeasured];
1027 divider /= rateX;
1029 Log_info3("SAP_D10: Inside manageOutput with divider = %d, rateX = %f & input_rate = %d", divider, rateX, pStatusIn->sampleRateMeasured);
1031 // DIT requires 2x clock
1032 if ((mcasp[_MCASP_AFSXCTL_OFFSET] & _MCASP_AFSXCTL_XMOD_MASK) ==
1033 (MCASP_AFSXCTL_XMOD_OF(0x180) << _MCASP_AFSXCTL_XMOD_SHIFT)) {
1034 if (divider < 2)
1035 return (SIO2_EINVAL);
1036 divider >>= 1;
1037 }
1039 mcasp[_MCASP_ACLKXCTL_OFFSET] =
1040 (mcasp[_MCASP_ACLKXCTL_OFFSET] & ~_MCASP_ACLKXCTL_CLKXDIV_MASK) |
1041 (MCASP_ACLKXCTL_CLKXDIV_OF(divider-1) << _MCASP_ACLKXCTL_CLKXDIV_SHIFT);
1042 return 0;
1043 } //manageOutput
1045 // -----------------------------------------------------------------------------
1046 // This function is called by the peripheral driver (DAP) in response to
1047 // various SIO_ctrl() calls made by the framework.
1049 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg)
1050 {
1051 const SAP_D10_Rx_Params *pDapD10RxParams = (const SAP_D10_Rx_Params *)pParams;
1052 const SAP_D10_Tx_Params *pDapD10TxParams = (const SAP_D10_Tx_Params *)pParams;
1053 //Platform_STATUS status;
1055 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
1056 XDAS_Int32 result = 0;
1058 // perform one time hardware initialization
1059 if (!initDone) {
1060 result = initD10 (device);
1061 if (result)
1062 return result;
1063 initDone = 1;
1064 }
1066 switch (code) {
1068 // .............................................................................
1069 // This case provides a regular entry point for managing the specified
1070 // input device. Nominally, this is used to provide lock and sample rate
1071 // status to the framework.
1073 case PAF_SIO_CONTROL_GET_INPUT_STATUS:
1074 if (device->mode != DEV2_INPUT)
1075 return SIO2_EINVAL;
1077 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1078 break;
1080 // .............................................................................
1081 // This case provides a regular entry point for managing the specified
1082 // output device. Nominally this is used to change the output clock dividers
1083 // in the case of double rate output (e.g. DTS 96/24).
1085 case PAF_SIO_CONTROL_SET_RATEX:
1086 // Support only output rate control, for now
1087 if (device->mode != DEV2_OUTPUT)
1088 return (SIO2_EINVAL);
1090 // configure clock divider (bit and frame clocks)
1091 manageOutput (device, pDapD10TxParams, *((float *) arg));
1092 break;
1094 // .............................................................................
1095 // This case is called once when the device is opened/allocated by the framework.
1096 // Here, for both input and output, this allows for configuring all needed
1097 // clocks for proper operation.
1099 case PAF_SIO_CONTROL_OPEN:
1100 if (device->mode == DEV2_INPUT) {
1102 // determine the master clock based on the mode element of the
1103 // parameter configuration.
1104 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
1105 manageInput (device, pDapD10RxParams, NULL);
1107 // select appropriate master clock (but dont force)
1109 clockMuxTx (sel, -1);
1111 }
1112 else {
1114 // Since DAC is a slave to the chosen input, operate the clksel switch appropriately
1115 // Also, this is a create-time (i.e, CTRL_OPEN) only call & not appropriate under
1116 // the periodic manage_output calls.
1117 int sel = (pDapD10TxParams->d10tx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
1118 clockMuxTx (sel, -1);
1119 audk2g_delay(50000); // GJ REVISIT: Without delay between Tx McASP & DAC configs, system aborts.
1120 setAudioDacConfig();
1121 dacHardUnMute ();
1123 // configure clock divider (bit and frame clocks)
1124 manageOutput (device, pDapD10TxParams, 1.0);
1125 }
1126 break;
1128 // .............................................................................
1129 // This case is called once when the device is closed/freed by the framework.
1131 case PAF_SIO_CONTROL_CLOSE:
1132 // If TX0 then signal it is no longer in use by the DACs and
1133 // configure manually to generate ADC clocks. Also hard mute
1134 // the DACs since they are not in use.
1135 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0)) {
1137 dacHardMute ();
1139 // if async then clear forced clock mux
1140 // if asynchronous then force clock change
1141 if (pDapD10TxParams->d10tx.mode & D10_SYNC_MASK)
1142 clockMuxTx (0, 0);
1143 }
1144 break;
1146 // .............................................................................
1147 // These cases are called as appropriate by the framework when there is
1148 // valid output data (UNMUTE) or no valid output (MUTE).
1150 case PAF_SIO_CONTROL_MUTE:
1151 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1152 dacSoftMute ();
1153 break;
1155 case PAF_SIO_CONTROL_UNMUTE:
1156 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1157 dacSoftUnMute ();
1158 break;
1160 // .............................................................................
1161 // This case is called when the device is idled.
1162 // There is no specific handling -- but needed to avoid error return.
1164 case PAF_SIO_CONTROL_IDLE:
1165 break;
1167 // .............................................................................
1168 // Called from the IDL Loop to allow for clock management and the like
1169 // The call is protected by a TSK_disable and HWI_disable so it is safe
1170 // to read/write shared resources.
1172 case PAF_SIO_CONTROL_WATCHDOG:
1173 // call manageInput in case the sample rate has changed resulting
1174 // in no output clocks which may have blocked the audio processing
1175 // thread. This call will reconfigure the AK4588 and restart the clocks.
1176 if (device->mode == DEV2_INPUT)
1177 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1178 break;
1180 // .............................................................................
1181 // Called from DOB_issue to allow for different values of the channel status
1182 // fields of the SPDIF output.
1184 case PAF_SIO_CONTROL_SET_DITSTATUS:
1185 // No action necessary.
1186 break;
1188 case PAF_SIO_CONTROL_SET_WORDSIZE:
1189 if(((pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) != D10_MCLK_OSC)
1190 {
1191 if ((device->mode == DEV2_INPUT) && (arg == 2))
1192 {
1193 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=2");
1194 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_16BITS;
1195 }
1196 else if ((device->mode == DEV2_INPUT) && (arg == 4))
1197 {
1198 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=4");
1199 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_NONE;
1200 }
1201 }
1202 break;
1203 // .............................................................................
1204 // Any other cases are not handled and return an error.
1206 default:
1207 return SIO2_EINVAL;
1208 }
1210 return result;
1211 } //D10_sapControl
1213 // -----------------------------------------------------------------------------
1216 unsigned int HDMIGpioGetState (void) {
1217 return(audk2g_gpioReadInput(AUDK2G_GPIO_PORT_0, AUDK2G_AUDIO_HSR_HMINTz_GPIO));
1218 }
1220 // EOF