2 /*
3 Copyright (c) 2017, Texas Instruments Incorporated - http://www.ti.com/
4 All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
36 /**
37 * \file audio_dc_config.c
38 *
39 * \brief Configures Audio daughter card HW modules
40 *
41 */
43 #include "audio_dc_cfg.h"
44 #include "vproccmds_a.h"
45 #include <stdarg.h>
46 #include "string.h"
47 #include <xdc/runtime/Log.h>
50 Platform_STATUS audioHDMIConfig(void);
52 #define HSR4_I2C_ADDR 0x5D
53 #define HSR4_I2C_PORT_NUM I2C_PORT_1
55 Int16 DA10x_I2C_init();
56 Int16 DA10x_I2C_close();
57 void DA10x_waitusec( Uint32);
58 Int16 DA10x_I2C_reset();
59 Int16 DA10x_I2C_write( Uint16, Uint8*, Uint16);
60 Int16 DA10x_I2C_read( Uint16, Uint8*, Uint16);
61 /* ------------------------------------------------------------------------ *
62 * Prototypes *
63 * ------------------------------------------------------------------------ */
65 /**
66 * \brief Initializes ADC module
67 *
68 * This function initializes and configures the ADC modules
69 * on audio daughter card
70 *
71 * \param devId [IN] ADC Device Id
72 * \param config [IN] ADC configuration parameters
73 *
74 * \return Platform_EOK on Success or error code
75 */
76 Platform_STATUS audioAdcConfig(AdcDevId devId, AdcConfig *config)
77 {
78 Platform_STATUS status;
80 if(config == NULL)
81 {
82 IFPRINT(platform_write("Invalid Inputs\n"));
83 return (Platform_EINVALID);
84 }
86 /* Initialize all the HW instances of ADC */
87 status = platformAudioAdcInit(devId);
88 if(status != Platform_EOK)
89 {
90 IFPRINT(platform_write("audioAdcConfig : platformaudioAdcConfig Failed\n"));
91 return (status);
92 }
94 /* Set ADC channel gain */
95 status = platformAudioAdcSetGain(devId, ADC_CH_ALL, config->gain);
96 if(status != Platform_EOK)
97 {
98 IFPRINT(platform_write("audioAdcConfig : platformAudioAdcSetGain Failed\n"));
99 return (status);
100 }
102 /* Configure Left input mux for ADC1L */
103 status = platformAudioAdcSetLeftInputMux(devId, ADC_CH1_LEFT,
104 config->adc1LMux);
105 if(status != Platform_EOK)
106 {
107 IFPRINT(platform_write("audioAdcConfig : platformAudioAdcSetLeftInputMux Failed\n"));
108 return (status);
109 }
111 /* Configure Left input mux for ADC2L*/
112 status = platformAudioAdcSetLeftInputMux(devId, ADC_CH2_LEFT,
113 config->adc2LMux);
114 if(status != Platform_EOK)
115 {
116 IFPRINT(platform_write("audioAdcConfig : platformAudioAdcSetLeftInputMux Failed\n"));
117 return (status);
118 }
120 /* Configure Right input mux for ADC1R */
121 status = platformAudioAdcSetRightInputMux(devId, ADC_CH1_RIGHT,
122 config->adc1RMux);
123 if(status != Platform_EOK)
124 {
125 IFPRINT(platform_write("audioAdcConfig : platformAudioAdcSetRightInputMux Failed\n"));
126 return (status);
127 }
129 /* Configure Right input mux for ADC2R */
130 status = platformAudioAdcSetRightInputMux(devId, ADC_CH2_RIGHT,
131 config->adc2RMux);
132 if(status != Platform_EOK)
133 {
134 IFPRINT(platform_write("audioAdcConfig : platformAudioAdcSetRightInputMux Failed\n"));
135 return (status);
136 }
138 /* Configure audio data format */
139 status = platformAudioAdcDataConfig(devId, config->wlen, config->format);
140 if(status != Platform_EOK)
141 {
142 IFPRINT(platform_write("audioAdcConfig : platformAudioAdcDataConfig Failed\n"));
143 return (status);
144 }
146 /* Configure all the interrupts */
147 status = platformAudioAdcConfigIntr(devId, ADC_INTR_ALL,
148 config->intEnable);
149 if(status != Platform_EOK)
150 {
151 IFPRINT(platform_write("audioAdcConfig : platformAudioAdcConfigIntr Failed\n"));
152 return (status);
153 }
155 return (status);
156 }
158 /**
159 * \brief Initializes DAC module
160 *
161 * This function initializes and configures the DAC modules
162 * on audio daughter card
163 *
164 * \param devId [IN] DAC Device Id
165 * \param config [IN] DAC configuration parameters
166 *
167 * \return Platform_EOK on Success or error code
168 */
169 Platform_STATUS audioDacConfig(DacDevId devId, DacConfig *config)
170 {
171 Platform_STATUS status;
173 if(config == NULL)
174 {
175 IFPRINT(platform_write("Invalid Inputs\n"));
176 return (Platform_EINVALID);
177 }
179 /* Initialize Audio DAC */
180 status = platformAudioDacInit(devId);
181 if(status != Platform_EOK)
182 {
183 IFPRINT(platform_write("audioDacConfig : platformaudioDacConfig Failed\n"));
184 return (status);
185 }
187 /* Configure AMUTE control event */
188 status = platformAudioDacAmuteCtrl(devId, config->amuteCtrl,
189 config->amuteEnable);
190 if(status != Platform_EOK)
191 {
192 IFPRINT(platform_write("audioDacConfig : platformAudioDacAmuteCtrl Failed\n"));
193 return (status);
194 }
196 /* Set sampling mode */
197 status = platformAudioDacSetSamplingMode(devId, config->samplingMode);
198 if(status != Platform_EOK)
199 {
200 IFPRINT(platform_write("audioDacConfig : platformAudioDacSetSamplingMode Failed\n"));
201 return (status);
202 }
204 /* Set data format */
205 status = platformAudioDacSetDataFormat(devId, config->dataFormat);
206 if(status != Platform_EOK)
207 {
208 IFPRINT(platform_write("audioDacConfig : platformAudioDacSetDataFormat Failed\n"));
209 return (status);
210 }
212 /* Enable soft mute control */
213 status = platformAudioDacSoftMuteCtrl(devId, DAC_CHAN_ALL,
214 config->softMuteEnable);
215 if(status != Platform_EOK)
216 {
217 IFPRINT(platform_write("audioDacConfig : platformAudioDacSoftMuteCtrl Failed\n"));
218 return (status);
219 }
221 /* Set attenuation mode */
222 status = platformAudioDacSetAttnMode(devId, config->attnMode);
223 if(status != Platform_EOK)
224 {
225 IFPRINT(platform_write("audioDacConfig : platformAudioDacSetAttnMode Failed\n"));
226 return (status);
227 }
229 /* Set De-emphasis control */
230 status = platformAudioDacDeempCtrl(devId, config->deempCtrl);
231 if(status != Platform_EOK)
232 {
233 IFPRINT(platform_write("audioDacConfig : platformAudioDacDeempCtrl Failed\n"));
234 return (status);
235 }
237 /* Set DAC volume */
238 status = platformAudioDacSetVolume(devId, DAC_CHAN_ALL, config->volume);
239 if(status != Platform_EOK)
240 {
241 IFPRINT(platform_write("audioDacConfig : platformAudioDacSetVolume Failed\n"));
242 return (status);
243 }
245 return (status);
246 }
248 /**
249 * \brief Initializes DIR module
250 *
251 * This function initializes and configures the DIR modules
252 * on audio daughter card
253 *
254 * \return Platform_EOK on Success or error code
255 */
256 Platform_STATUS audioDirConfig(void)
257 {
258 Platform_STATUS status;
259 int8_t fsout;
260 #ifdef CHECK_ERROR_STATUS
261 uint32_t timeout;
262 #endif
264 status = platformAudioDirInit();
265 if(status != Platform_EOK)
266 {
267 IFPRINT(platform_write("audioDirConfig : Audio DIR Configuration Failed!\n"));
268 return (status);
269 }
271 #ifdef CHECK_ERROR_STATUS
272 /* DIR should be in PLL mode.
273 Wait for ERROR signal to be low as DIR is configured for
274 AUTO mode */
275 timeout = ERROR_STATUS_WAIT_TIMEOUT;
276 while (timeout)
277 {
278 if(!platformAudioDirGetErrStatus())
279 {
280 IFPRINT(platform_write("audioDirConfig : DIR in PLL Mode\n"));
281 break;
282 }
284 IFPRINT(platform_write("audioDirConfig : Waiting for DIR to Enter PLL Mode...\n"));
285 platform_delay(10);
286 timeout--;
287 }
289 if(!timeout)
290 {
291 IFPRINT(platform_write("audioDirConfig : DIR is not in PLL Mode!!\n"));
292 return (Platform_EFAIL);
293 }
294 #endif
296 fsout = platformAudioDirGetFsOut();
297 if(fsout == 2)
298 {
299 IFPRINT(platform_write("audioDirConfig : Out of Range Sampling Frequency\n"));
300 }
301 else if(fsout == 0)
302 {
303 IFPRINT(platform_write("audioDirConfig : Calculated Sampling Frequency Output is 43 kHz\9645.2 kHz\n"));
304 }
305 else if(fsout == 1)
306 {
307 IFPRINT(platform_write("audioDirConfig : Calculated Sampling Frequency Output is 46.8 kHz\9649.2 kHz\n"));
308 }
309 else if(fsout == 3)
310 {
311 IFPRINT(platform_write("audioDirConfig : Calculated Sampling Frequency Output is 31.2 kHz\9632.8 kHz\n"));
312 }
313 else
314 {
315 IFPRINT(platform_write("audioDirConfig : Error in Reading FSOUT status \n"));
316 status = Platform_EFAIL;
317 }
319 return (status);
320 }
322 int alpha_i2c_write(unsigned short, ...);
323 void set_audio_desc(unsigned char ,unsigned char ,unsigned char ,unsigned char ,unsigned char );
324 void hrptredid();
325 void hdmi128();
328 int gret_val=0;
329 int gI2cWrite_errCnt=0;
330 int alpha_i2c_write(unsigned short var1, ...)
331 {
332 unsigned short alpha_type,length,temp_var;
333 int i,offset,ret_val;
334 unsigned char cmd[50];
335 char *s;
336 va_list argp;
337 va_start(argp, var1);
339 alpha_type = var1>> 8;
340 switch(alpha_type)
341 {
342 case 0xca:
343 case 0xc2:
344 case 0xc3:
345 case 0xc4:
346 length = 4;
347 break;
348 case 0xcb:
349 length = 6;
350 break;
351 case 0xcc:
352 length = 8;
353 break;
354 case 0xcd:
355 case 0xc5:
356 length= 8; // temporary - data starts after 8 bytes
357 break;
358 }
360 cmd[0]=length;
361 temp_var=var1;
362 for(i=0;i<length-2;i+=2) // convert to bytes as per protocol
363 {
364 cmd[i+1]= temp_var & 0xff;
365 cmd[i+2]= temp_var >> 8;
366 temp_var=va_arg(argp, short);
367 }
368 cmd[i+1]= temp_var & 0xff;
369 cmd[i+2]= temp_var >> 8;
372 if(alpha_type == 0xcd) // special processing for variable length
373 {
374 offset=9;
375 s = va_arg(argp, char *); // remaining data is in form of string
376 length = temp_var; // last short indicates data length
377 cmd[0]+=length;
378 for(i=offset;i<offset+length;i++)
379 cmd[i]=s[i-offset];
380 }
381 va_end(argp);
383 #define DA10x_I2C 1
385 #ifdef DA10x_I2C
386 do
387 {
388 ret_val = DA10x_I2C_write(HSR4_I2C_ADDR, cmd, cmd[0]+1);
390 if(ret_val !=I2C_RET_OK)
391 {
392 gret_val++;
393 gI2cWrite_errCnt++;
394 DA10x_I2C_reset();
395 }
396 }while(ret_val !=I2C_RET_OK);
398 #else
399 do
400 {
401 ret_val = i2cWrite(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR, cmd, cmd[0]+1, I2C_RELEASE_BUS);
402 if(ret_val !=I2C_RET_OK)
403 {
404 gret_val++;
405 gI2cWrite_errCnt++;
406 i2cConfig(HSR4_I2C_PORT_NUM);
407 }
408 }while(ret_val !=I2C_RET_OK);
409 ret_val = i2cWrite(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR, cmd, cmd[0]+1, I2C_RELEASE_BUS);
410 if(ret_val !=I2C_RET_OK)
411 gret_val++;
412 #endif
414 return ret_val;
415 }
417 void set_audio_desc(unsigned char var1,unsigned char var2,unsigned char var3,unsigned char var4,unsigned char var5)
418 {
419 int ret_val=I2C_RET_OK;
421 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_FORMAT(var1, var2));}while (ret_val !=I2C_RET_OK);
422 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_NUM_CHANNELS(var1, var3));}while (ret_val !=I2C_RET_OK);
423 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_SAMPLE_RATES(var1, var4));}while (ret_val !=I2C_RET_OK);
424 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_MISC(var1, var5));}while (ret_val !=I2C_RET_OK);
425 }
427 int gI2Ccnt=0;
429 // Program HDMI CEA / EDID values, as necessary.
430 void hrptredid()
431 {
432 int ret_val=I2C_RET_OK;
434 /*do{
435 platform_delay(10);
436 ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK(0xFF));
437 if (ret_val !=I2C_RET_OK)
438 {
439 gI2Ccnt++;
440 #ifdef DA10x_I2C
441 DA10x_I2C_reset();
442 #else
443 i2cConfig(HSR4_I2C_PORT_NUM);
444 #endif
445 }
447 }while (ret_val !=I2C_RET_OK); */
448 do{ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK(0xFF));}while (ret_val !=I2C_RET_OK);
449 platform_delay(10);
450 do{ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK_2(0x7));}while (ret_val !=I2C_RET_OK);
452 set_audio_desc(0,1,2,0x7f,7); // PCM 2 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4 KHz, 192 KHz, 16bit, 20bit, 24bit
453 set_audio_desc(1,1,8,0x7f,7); // PCM 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4 KHz, 192 KHz, 16bit, 20bit, 24bit
454 set_audio_desc(2,2,6,0x7,80); // AC3 6 channel, 32kHz, 44.1kHz, 48kHz, 640kHz max bit rate
455 set_audio_desc(3,10,8,0x07,1); // Dolby Digital Plus, 8 channel, 32kHz, 44.1kHz, 48kHz, codec specific:1
456 set_audio_desc(4,12,8,0x7F,1); // MAT(MPL)(Dolby TrueHD), 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz,
457 // 176.4kHz, 192kHz, codec specific:1
458 set_audio_desc(5,7,6,0x1E,192); // DTS 6 channel, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 1,536kHz max bit rate
459 set_audio_desc(6,7,8,0x6,192); // DTS 8 channel, 44.1kHz, 48kHz, 1,536kHz max bit rate
460 set_audio_desc(7,11,8,0x7F,3); // DTS-HD, 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz,
461 // last byte is 3 for DTS:X, 1 otherwise.
462 set_audio_desc(8,11,8,0x7F,1); // DTS-HD, 8 channel - same as above, but last byte = 1
463 set_audio_desc(9,0,0,0,0);
464 set_audio_desc(10,0,0,0,0);
465 set_audio_desc(11,0,0,0,0); //AAC LC (5,6,6,0x1f,192);
466 set_audio_desc(12,0,0,0,0);
467 set_audio_desc(13,0,0,0,0);
468 set_audio_desc(14,0,0,0,0);
469 set_audio_desc(15,0,0,0,0);
470 set_audio_desc(16,0,0,0,0);
471 set_audio_desc(17,0,0,0,0);
472 set_audio_desc(18,0,0,0,0);
473 set_audio_desc(19,0,0,0,0);
474 platform_delay(10);
475 do{ret_val=alpha_i2c_write(HSDIO_EDID_GO);}while (ret_val !=I2C_RET_OK);
476 }
478 // Configure the HOST port of HSR41 for EXTRACT mode of operation.
479 // Note: HDMI Tx/Out Port's state is not cared for, at all.
480 void hdmi128()
481 {
482 int ret_val=I2C_RET_OK;
484 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_CHANGE_msk));}while (ret_val !=I2C_RET_OK);
485 //platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_MUTE_msk));}while (ret_val !=I2C_RET_OK);
486 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_AUDIO_MCLK_TO_HOST(HSDIO_AudioMClk_128X));}while (ret_val !=I2C_RET_OK);
487 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_AUDIO_UNMUTE_DELAY_TO_HOST(HSDIO_AudioUnMuteDelay_NO_DELAY));}while (ret_val !=I2C_RET_OK);
488 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_AUDIO_FORMAT_TO_HOST(HSDIO_AudioFmt_I2S));}while (ret_val !=I2C_RET_OK);
489 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_IMPLEMENT_AUDIO_TO_HOST_CMDS);}while (ret_val !=I2C_RET_OK);
490 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_AUDIO_ROUTING(HSDIO_AudioRouting_HSDIOIN_NOOUT));}while (ret_val !=I2C_RET_OK);
491 platform_delay(10);do{ret_val=alpha_i2c_write(HSDIO_SYS_CFG_GO);}while (ret_val !=I2C_RET_OK);
492 }
494 //
495 // Fetch Video Sync Status from HSR41
496 unsigned int read_hdmi_videosyncstatus()
497 {
498 unsigned char data[50];
499 Uint8 length;
500 int ret_val=0;
502 ret_val=alpha_i2c_write(HSDIO_INPUT_SYNC_STS);
503 #ifdef DA10x_I2C
504 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
505 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
506 #else
507 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
508 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
509 #endif
510 if(!ret_val) ret_val= data[2]; // 1-byte / indicates error status
512 return ret_val;
513 }
515 //
516 // Fetch Audio Present Status from HSR41
517 unsigned int read_hdmi_audiostatus()
518 {
519 unsigned char data[50];
520 Uint8 length;
521 int ret_val=0;
523 ret_val=alpha_i2c_write(HSDIO_AUDIO_INPUT_PRESENT_STS);
524 #ifdef DA10x_I2C
525 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
526 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
527 #else
528 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
529 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
530 #endif
531 if(!ret_val) ret_val= data[2]; // 1-byte / indicates error status
533 return ret_val;
534 }
536 // Fetch Clock Status from HSR41
537 unsigned int read_hdmi_clockstatus()
538 {
539 unsigned char data[50];
540 Uint8 length;
541 int ret_val=0;
543 ret_val=alpha_i2c_write(HSDIO_GET_AUDIO_MCLK_TO_HOST);
544 #ifdef DA10x_I2C
545 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
546 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
547 #else
548 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
549 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
550 #endif
551 if(!ret_val) ret_val= data[2]; // 1-byte / indicates clock status
553 return ret_val;
554 }
556 // Fetch Error Status from HSR41
557 unsigned int read_hdmi_errstatus()
558 {
559 unsigned char data[50];
560 Uint8 length;
561 int ret_val=0;
563 ret_val=alpha_i2c_write(HSDIO_AUDIO_INPUT_ERROR_STS);
564 #ifdef DA10x_I2C
565 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
566 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
567 #else
568 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
569 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
570 #endif
571 if(!ret_val) ret_val= data[2]; // 1-byte / indicates error status
573 return ret_val;
574 }
576 void clear_hdmi_hmint()
577 {
578 int ret_val=0;
580 ret_val=alpha_i2c_write(HSDIO_ALERT_STS); //clear the interrupt on ~HMINT by reading the Alert Status register
582 if(ret_val)
583 while(1); // Control shouldn't be here
585 return;
586 }
588 unsigned int read_hdmi_samprate()
589 {
590 unsigned char data[50];
591 Uint8 length;
592 int ret_val=7;
594 Log_info0("Audio DC CFG: Entered read_hdmi_samprate");
595 ret_val=alpha_i2c_write(HSDIO_AUDIO_INPUT_FREQ_STS);
597 #ifdef DA10x_I2C
598 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
599 if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
600 #else
601 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
602 if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
603 #endif
605 Log_info0("Audio DC CFG: Leaving read_hdmi_samprate");
607 if(!ret_val) ret_val= data[2]; // indicates sample rate
608 else
609 ret_val = 0;
611 return ret_val;
612 }
615 Platform_STATUS audioHDMIConfig(void)
616 {
617 Platform_STATUS status = Platform_EOK;
619 DA10x_I2C_init();
620 hrptredid();
622 hdmi128();
624 //while((HSDIO_InSync_SYNC_DETECTED != read_hdmi_videosyncstatus()) || (HSDIO_AudioMClk_128X != read_hdmi_clockstatus()));// || (HSDIO_AudioPresent_HAS_AUDIO != read_hdmi_audiostatus()));
625 while((HSDIO_InSync_SYNC_DETECTED != read_hdmi_videosyncstatus()));
626 //while((HSDIO_AudioMClk_128X != read_hdmi_clockstatus()) || (HSDIO_AudioErr_NO_ERROR != read_hdmi_errstatus()));
628 return (status);
629 }
631 /* ------------------------------------------------------------------------ *
632 * *
633 * DA10x_wait( delay ) *
634 * *
635 * Wait in a software loop for 'x' delay *
636 * *
637 * ------------------------------------------------------------------------ */
638 void DA10x_wait( Uint32 delay )
639 {
640 volatile Uint32 i;
641 for ( i = 0 ; i < delay ; i++ ){ };
642 }
644 /* ------------------------------------------------------------------------ *
645 * *
646 * DA10x_waitusec( usec ) *
647 * *
648 * Wait in a software loop for 'x' microseconds *
649 * *
650 * ------------------------------------------------------------------------ */
651 void DA10x_waitusec( Uint32 usec )
652 {
653 DA10x_wait( usec * 3 );
654 }
655 Int32 i2c_timeout = 0x10000;
657 /* ------------------------------------------------------------------------ *
658 * *
659 * _I2C_init( ) *
660 * *
661 * Enable and initalize the I2C module *
662 * The I2C clk is set to run at 400 (384) KHz *
663 * *
664 * ------------------------------------------------------------------------ */
665 Int16 DA10x_I2C_init()
666 {
667 I2C_ICMDR = 0; // Reset I2C
668 I2C_ICPSC = 9; // Prescale to get 10MHz I2C internal
669 I2C_ICCLKL = 7; // Config clk LOW for 400kHz
670 I2C_ICCLKH = 7; // Config clk HIGH for 400kHz
671 I2C_ICMDR |= ICMDR_IRS; // Release I2C from reset
672 return 0;
673 }
675 /* ------------------------------------------------------------------------ *
676 * *
677 * _I2C_close( ) *
678 * *
679 * ------------------------------------------------------------------------ */
680 Int16 DA10x_I2C_close()
681 {
682 I2C_ICMDR = 0; // Reset I2C
683 return 0;
684 }
686 /* ------------------------------------------------------------------------ *
687 * *
688 * _I2C_reset( ) *
689 * *
690 * ------------------------------------------------------------------------ */
691 Int16 DA10x_I2C_reset( )
692 {
693 DA10x_I2C_close( );
694 DA10x_I2C_init( );
695 return 0;
696 }
698 /* ------------------------------------------------------------------------ *
699 * *
700 * _I2C_write( i2c_addr, data, len ) *
701 * *
702 * I2C write in Master mode *
703 * *
704 * i2c_addr <- I2C slave address *
705 * data <- I2C data ptr *
706 * len <- # of bytes to write *
707 * *
708 * ------------------------------------------------------------------------ */
709 Int16 DA10x_I2C_write( Uint16 i2c_addr, Uint8* data, Uint16 len )
710 {
711 Int32 timeout, i;
712 Int32 oldMask;
715 I2C_ICCNT = len; // Set length
716 I2C_ICSAR = i2c_addr; // Set I2C slave address
717 I2C_ICMDR = ICMDR_STT // Set for Master Write
718 | ICMDR_TRX
719 | ICMDR_MST
720 | ICMDR_IRS
721 | ICMDR_FREE;
723 DA10x_wait( 10 ); // Short delay
725 for ( i = 0 ; i < len ; i++ )
726 {
728 I2C_ICDXR = data[i]; // Write
730 timeout = i2c_timeout;
731 do
732 {
733 DA10x_wait( 10);
734 if ( timeout-- < 0 )
735 {
736 DA10x_I2C_reset( );
737 return -1;
738 }
739 } while ( ( I2C_ICSTR & ICSTR_ICXRDY ) == 0 );// Wait for Tx Ready
741 }
743 I2C_ICMDR |= ICMDR_STP; // Generate STOP
745 return 0;
747 }
749 /* ------------------------------------------------------------------------ *
750 * *
751 * _I2C_read( i2c_addr, data, len ) *
752 * *
753 * I2C read in Master mode *
754 * *
755 * i2c_addr <- I2C slave address *
756 * data <- I2C data ptr *
757 * len <- # of bytes to write *
758 * *
759 * Returns: 0: PASS *
760 * -1: FAIL Timeout *
761 * *
762 * ------------------------------------------------------------------------ */
763 Int16 DA10x_I2C_read( Uint16 i2c_addr, Uint8* data, Uint16 len )
764 {
765 Int32 timeout, i;
767 I2C_ICCNT = len; // Set length
768 I2C_ICSAR = i2c_addr; // Set I2C slave address
769 I2C_ICMDR = ICMDR_STT // Set for Master Read
770 | ICMDR_MST
771 | ICMDR_IRS
772 | ICMDR_FREE;
774 DA10x_wait( 10 ); // Short delay
776 for ( i = 0 ; i < len ; i++ )
777 {
778 timeout = i2c_timeout;
780 /* Wait for Rx Ready */
781 do
782 {
783 DA10x_wait( 10 );
784 if ( timeout-- < 0 )
785 {
786 DA10x_I2C_reset( );
787 return -1;
788 }
789 } while ( ( I2C_ICSTR & ICSTR_ICRRDY ) == 0 );// Wait for Rx Ready
791 data[i] = I2C_ICDRR; // Read
793 }
795 I2C_ICMDR |= ICMDR_STP; // Generate STOP
797 return 0;
798 }
802 /* Nothing past this point */