2 /*
3 Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/
4 All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
36 /*
37 * sample_k2g_cfg.c
38 *
39 * Platform specific EDMA3 hardware related information like number of transfer
40 * controllers, various interrupt ids etc. It is used while interrupts
41 * enabling / disabling. It needs to be ported for different SoCs.
42 *
43 */
45 #include <ti/sdo/edma3/rm/edma3_rm.h>
47 /* Number of EDMA3 controllers present in the system */
48 #define NUM_EDMA3_INSTANCES 2u
49 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
51 /* Number of DSPs present in the system */
52 #define NUM_DSPS 1u
53 //const unsigned int numDsps = NUM_DSPS;
55 #define CGEM_REG_START (0x01800000)
58 extern cregister volatile unsigned int DNUM;
60 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
63 /* Determine the processor id by reading DNUM register. */
64 unsigned short determineProcId()
65 {
66 volatile unsigned int *addr;
67 unsigned int core_no;
69 /* Identify the core number */
70 addr = (unsigned int *)(CGEM_REG_START+0x40000);
71 core_no = ((*addr) & 0x000F0000)>>16;
73 return core_no;
74 }
76 signed char* getGlobalAddr(signed char* addr)
77 {
78 if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
79 {
80 return (addr); /* The address is already a global address */
81 }
83 return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
84 }
85 /** Whether global configuration required for EDMA3 or not.
86 * This configuration should be done only once for the EDMA3 hardware by
87 * any one of the masters (i.e. DSPs).
88 * It can be changed depending on the use-case.
89 */
90 unsigned int gblCfgReqdArray [NUM_DSPS] = {
91 0, /* DSP#0 is Master, will do the global init */
93 };
95 unsigned short isGblConfigRequired(unsigned int dspNum)
96 {
97 return gblCfgReqdArray[dspNum];
98 }
100 /* Semaphore handles */
101 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL};
104 /* Variable which will be used internally for referring number of Event Queues. */
105 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 2u};
107 /* Variable which will be used internally for referring number of TCs. */
108 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 2u};
110 /**
111 * Variable which will be used internally for referring transfer completion
112 * interrupt. Completion interrupts for all the shadow regions and all the
113 * EDMA3 controllers are captured since it is a multi-DSP platform.
114 */
115 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
116 {
117 0x88, 0x89, 0x8a, 0x8b,
118 0x8c, 0x8d, 0x8e, 0x8f,
119 },
120 {
121 0x90, 0x91, 0x92, 0x93,
122 0x94, 0x95, 0x96, 0x97,
123 },
124 };
126 /**
127 * Variable which will be used internally for referring channel controller's
128 * error interrupt.
129 */
130 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {0x99, 0x9c};
132 /**
133 * Variable which will be used internally for referring transfer controllers'
134 * error interrupts.
135 */
136 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
137 {
138 0xA0,0xA1, 0u, 0u,
139 0u, 0u, 0u, 0u,
140 },
141 {
142 0xA4, 0xA5, 0u, 0u,
143 0u, 0u, 0u, 0u,
144 },
145 };
147 /* Driver Object Initialization Configuration */
148 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
149 {
150 {
151 /* EDMA3 INSTANCE# 0 */
152 /** Total number of DMA Channels supported by the EDMA3 Controller */
153 64u,
154 /** Total number of QDMA Channels supported by the EDMA3 Controller */
155 8u,
156 /** Total number of TCCs supported by the EDMA3 Controller */
157 64u,
158 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
159 512u,
160 /** Total number of Event Queues in the EDMA3 Controller */
161 2u,
162 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
163 2u,
164 /** Number of Regions on this EDMA3 controller */
165 8u,
167 /**
168 * \brief Channel mapping existence
169 * A value of 0 (No channel mapping) implies that there is fixed association
170 * for a channel number to a parameter entry number or, in other words,
171 * PaRAM entry n corresponds to channel n.
172 */
173 1u,
175 /** Existence of memory protection feature */
176 1u,
178 /** Global Register Region of CC Registers */
179 (void *)0x02700000u,
180 /** Transfer Controller (TC) Registers */
181 {
182 (void *)0x02760000u,
183 (void *)0x02768000u,
184 (void *)NULL,
185 (void *)NULL,
186 (void *)NULL,
187 (void *)NULL,
188 (void *)NULL,
189 (void *)NULL
190 },
191 /** Interrupt no. for Transfer Completion */
192 0x88,
193 /** Interrupt no. for CC Error */
194 0x99,
195 /** Interrupt no. for TCs Error */
196 {
197 0xA0,
198 0xA1,
199 0u,
200 0u,
201 0u,
202 0u,
203 0u,
204 0u,
205 },
207 /**
208 * \brief EDMA3 TC priority setting
209 *
210 * User can program the priority of the Event Queues
211 * at a system-wide level. This means that the user can set the
212 * priority of an IO initiated by either of the TCs (Transfer Controllers)
213 * relative to IO initiated by the other bus masters on the
214 * device (ARM, DSP, USB, etc)
215 */
216 {
217 0u,
218 1u,
219 0u,
220 0u,
221 0u,
222 0u,
223 0u,
224 0u
225 },
226 /**
227 * \brief To Configure the Threshold level of number of events
228 * that can be queued up in the Event queues. EDMA3CC error register
229 * (CCERR) will indicate whether or not at any instant of time the
230 * number of events queued up in any of the event queues exceeds
231 * or equals the threshold/watermark value that is set
232 * in the queue watermark threshold register (QWMTHRA).
233 */
234 {
235 16u,
236 16u,
237 0u,
238 0u,
239 0u,
240 0u,
241 0u,
242 0u
243 },
245 /**
246 * \brief To Configure the Default Burst Size (DBS) of TCs.
247 * An optimally-sized command is defined by the transfer controller
248 * default burst size (DBS). Different TCs can have different
249 * DBS values. It is defined in Bytes.
250 */
251 {
252 128u,
253 128u,
254 0u,
255 0u,
256 0u,
257 0u,
258 0u,
259 0u
260 },
262 /**
263 * \brief Mapping from each DMA channel to a Parameter RAM set,
264 * if it exists, otherwise of no use.
265 */
266 {
267 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
268 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
269 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
270 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
271 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
272 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
273 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
274 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
275 },
277 /**
278 * \brief Mapping from each DMA channel to a TCC. This specific
279 * TCC code will be returned when the transfer is completed
280 * on the mapped channel.
281 */
282 {
283 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
284 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
285 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 18u, 19u, 20u, 21u, 22u, 23u,
286 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
287 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
288 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
289 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
290 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
291 },
293 /**
294 * \brief Mapping of DMA channels to Hardware Events from
295 * various peripherals, which use EDMA for data transfer.
296 * All channels need not be mapped, some can be free also.
297 */
298 {
299 0x03033333u,
300 0x0000000Fu
301 }
302 },
304 {
305 /* EDMA3 INSTANCE# 1 */
306 /** Total number of DMA Channels supported by the EDMA3 Controller */
307 64u,
308 /** Total number of QDMA Channels supported by the EDMA3 Controller */
309 8u,
310 /** Total number of TCCs supported by the EDMA3 Controller */
311 64u,
312 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
313 512u,
314 /** Total number of Event Queues in the EDMA3 Controller */
315 2u,
316 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
317 2u,
318 /** Number of Regions on this EDMA3 controller */
319 8u,
321 /**
322 * \brief Channel mapping existence
323 * A value of 0 (No channel mapping) implies that there is fixed association
324 * for a channel number to a parameter entry number or, in other words,
325 * PaRAM entry n corresponds to channel n.
326 */
327 1u,
329 /** Existence of memory protection feature */
330 1u,
332 /** Global Register Region of CC Registers */
333 (void *)0x02728000U,
334 /** Transfer Controller (TC) Registers */
335 {
336 (void *)0x027b0000U,
337 (void *)0x027b8000U,
338 (void *)NULL,
339 (void *)NULL,
340 (void *)NULL,
341 (void *)NULL,
342 (void *)NULL,
343 (void *)NULL
344 },
345 /** Interrupt no. for Transfer Completion */
346 0x90,
347 /** Interrupt no. for CC Error */
348 0x9C,
349 /** Interrupt no. for TCs Error */
350 {
351 0xA4,
352 0xA5,
353 0u,
354 0u,
355 0u,
356 0u,
357 0u,
358 0u,
359 },
361 /**
362 * \brief EDMA3 TC priority setting
363 *
364 * User can program the priority of the Event Queues
365 * at a system-wide level. This means that the user can set the
366 * priority of an IO initiated by either of the TCs (Transfer Controllers)
367 * relative to IO initiated by the other bus masters on the
368 * device (ARM, DSP, USB, etc)
369 */
370 {
371 0u,
372 1u,
373 2u,
374 3u,
375 0u,
376 0u,
377 0u,
378 0u
379 },
380 /**
381 * \brief To Configure the Threshold level of number of events
382 * that can be queued up in the Event queues. EDMA3CC error register
383 * (CCERR) will indicate whether or not at any instant of time the
384 * number of events queued up in any of the event queues exceeds
385 * or equals the threshold/watermark value that is set
386 * in the queue watermark threshold register (QWMTHRA).
387 */
388 {
389 16u,
390 16u,
391 16u,
392 16u,
393 0u,
394 0u,
395 0u,
396 0u
397 },
399 /**
400 * \brief To Configure the Default Burst Size (DBS) of TCs.
401 * An optimally-sized command is defined by the transfer controller
402 * default burst size (DBS). Different TCs can have different
403 * DBS values. It is defined in Bytes.
404 */
405 {
406 64u,
407 64u,
408 64u,
409 64u,
410 0u,
411 0u,
412 0u,
413 0u
414 },
416 /**
417 * \brief Mapping from each DMA channel to a Parameter RAM set,
418 * if it exists, otherwise of no use.
419 */
420 {
421 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
422 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
423 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
424 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
425 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
426 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
427 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
428 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
429 },
431 /**
432 * \brief Mapping from each DMA channel to a TCC. This specific
433 * TCC code will be returned when the transfer is completed
434 * on the mapped channel.
435 */
436 {
437 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
438 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
439 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
440 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
441 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
442 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
443 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
444 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
445 },
447 /**
448 * \brief Mapping of DMA channels to Hardware Events from
449 * various peripherals, which use EDMA for data transfer.
450 * All channels need not be mapped, some can be free also.
451 */
452 {
453 0x3FFF3FFFu,
454 0x3FFF3FFFu
455 }
456 },
458 };
460 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
461 {
462 /* EDMA3 INSTANCE# 0 */
463 {
464 /* Resources owned/reserved by region 0 */
465 {
466 /* ownPaRAMSets */
467 /* 31 0 63 32 95 64 127 96 */
468 {0xFFFF000Fu, 0x00000FFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
469 /* 159 128 191 160 223 192 255 224 */
470 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
471 /* 287 256 319 288 351 320 383 352 */
472 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
473 /* 415 384 447 416 479 448 511 480 */
474 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
476 /* ownDmaChannels */
477 /* 31 0 63 32 */
478 {0x0f03000Fu, 0x0000000Fu},
480 /* ownQdmaChannels */
481 /* 31 0 */
482 {0x00000003u},
484 /* ownTccs */
485 /* 31 0 63 32 */
486 {0x0f03000Fu, 0x0000000Fu},
488 /* resvdPaRAMSets */
489 /* 31 0 63 32 95 64 127 96 */
490 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
491 /* 159 128 191 160 223 192 255 224 */
492 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
493 /* 287 256 319 288 351 320 383 352 */
494 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
495 /* 415 384 447 416 479 448 511 480 */
496 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
498 /* resvdDmaChannels */
499 /* 31 0 */
500 {0x00000000u, 0x00000000u},
502 /* resvdQdmaChannels */
503 /* 31 0 */
504 {0x00000000u},
506 /* resvdTccs */
507 /* 31 0 */
508 {0x00000000u, 0xFFF00000u},
509 },
511 /* Resources owned/reserved by region 1 */
512 {
513 /* ownPaRAMSets */
514 /* 31 0 63 32 95 64 127 96 */
515 {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
516 /* 159 128 191 160 223 192 255 224 */
517 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
518 /* 287 256 319 288 351 320 383 352 */
519 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
520 /* 415 384 447 416 479 448 511 480 */
521 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
523 /* ownDmaChannels */
524 /* 31 0 63 32 */
525 {0x000000F0u, 0x00000000u},
527 /* ownQdmaChannels */
528 /* 31 0 */
529 {0x0000000Cu},
531 /* ownTccs */
532 /* 31 0 63 32 */
533 {0x000000F0u, 0x00000000u},
535 /* resvdPaRAMSets */
536 /* 31 0 63 32 95 64 127 96 */
537 {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
538 /* 159 128 191 160 223 192 255 224 */
539 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
540 /* 287 256 319 288 351 320 383 352 */
541 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
542 /* 415 384 447 416 479 448 511 480 */
543 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
545 /* resvdDmaChannels */
546 /* 31 0 63 32 */
547 {0x00000030u, 0x00000000u},
549 /* resvdQdmaChannels */
550 /* 31 0 */
551 {0x00000000u},
553 /* resvdTccs */
554 /* 31 0 63 32 */
555 {0x00000030u, 0x00000000u},
556 },
558 /* Resources owned/reserved by region 2 */
559 {
560 /* ownPaRAMSets */
561 /* 31 0 63 32 95 64 127 96 */
562 {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,
563 /* 159 128 191 160 223 192 255 224 */
564 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
565 /* 287 256 319 288 351 320 383 352 */
566 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
567 /* 415 384 447 416 479 448 511 480 */
568 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
570 /* ownDmaChannels */
571 /* 31 0 63 32 */
572 {0x00000F00u, 0x00000000u},
574 /* ownQdmaChannels */
575 /* 31 0 */
576 {0x00000030u},
578 /* ownTccs */
579 /* 31 0 63 32 */
580 {0x00000F00u, 0x00000000u},
582 /* resvdPaRAMSets */
583 /* 31 0 63 32 95 64 127 96 */
584 {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
585 /* 159 128 191 160 223 192 255 224 */
586 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
587 /* 287 256 319 288 351 320 383 352 */
588 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
589 /* 415 384 447 416 479 448 511 480 */
590 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
592 /* resvdDmaChannels */
593 /* 31 0 63 32 */
594 {0x00000300u, 0x00000000u},
596 /* resvdQdmaChannels */
597 /* 31 0 */
598 {0x00000000u},
600 /* resvdTccs */
601 /* 31 0 63 32 */
602 {0x00000300u, 0x00000000u},
603 },
605 /* Resources owned/reserved by region 3 */
606 {
607 /* ownPaRAMSets */
608 /* 31 0 63 32 95 64 127 96 */
609 {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,
610 /* 159 128 191 160 223 192 255 224 */
611 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
612 /* 287 256 319 288 351 320 383 352 */
613 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
614 /* 415 384 447 416 479 448 511 480 */
615 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
617 /* ownDmaChannels */
618 /* 31 0 63 32 */
619 {0x0000F000u, 0x00000000u},
621 /* ownQdmaChannels */
622 /* 31 0 */
623 {0x000000C0u},
625 /* ownTccs */
626 /* 31 0 63 32 */
627 {0x0000F000u, 0x00000000u},
629 /* resvdPaRAMSets */
630 /* 31 0 63 32 95 64 127 96 */
631 {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
632 /* 159 128 191 160 223 192 255 224 */
633 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
634 /* 287 256 319 288 351 320 383 352 */
635 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
636 /* 415 384 447 416 479 448 511 480 */
637 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
639 /* resvdDmaChannels */
640 /* 31 0 63 32 */
641 {0x00003000u, 0x00000000u},
643 /* resvdQdmaChannels */
644 /* 31 0 */
645 {0x00000000u},
647 /* resvdTccs */
648 /* 31 0 63 32 */
649 {0x00003000u, 0x00000000u},
650 },
652 /* Resources owned/reserved by region 4 */
653 {
654 /* ownPaRAMSets */
655 /* 31 0 63 32 95 64 127 96 */
656 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
657 /* 159 128 191 160 223 192 255 224 */
658 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
659 /* 287 256 319 288 351 320 383 352 */
660 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
661 /* 415 384 447 416 479 448 511 480 */
662 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
664 /* ownDmaChannels */
665 /* 31 0 63 32 */
666 {0x00000000u, 0x00000000u},
668 /* ownQdmaChannels */
669 /* 31 0 */
670 {0x00000000u},
672 /* ownTccs */
673 /* 31 0 63 32 */
674 {0x00000000u, 0x00000000u},
676 /* resvdPaRAMSets */
677 /* 31 0 63 32 95 64 127 96 */
678 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
679 /* 159 128 191 160 223 192 255 224 */
680 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
681 /* 287 256 319 288 351 320 383 352 */
682 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
683 /* 415 384 447 416 479 448 511 480 */
684 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
686 /* resvdDmaChannels */
687 /* 31 0 63 32 */
688 {0x00000000u, 0x00000000u},
690 /* resvdQdmaChannels */
691 /* 31 0 */
692 {0x00000000u},
694 /* resvdTccs */
695 /* 31 0 63 32 */
696 {0x00000000u, 0x00000000u},
697 },
699 /* Resources owned/reserved by region 5 */
700 {
701 /* ownPaRAMSets */
702 /* 31 0 63 32 95 64 127 96 */
703 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
704 /* 159 128 191 160 223 192 255 224 */
705 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
706 /* 287 256 319 288 351 320 383 352 */
707 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
708 /* 415 384 447 416 479 448 511 480 */
709 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
711 /* ownDmaChannels */
712 /* 31 0 63 32 */
713 {0x00000000u, 0x00000000u},
715 /* ownQdmaChannels */
716 /* 31 0 */
717 {0x00000000u},
719 /* ownTccs */
720 /* 31 0 63 32 */
721 {0x00000000u, 0x00000000u},
723 /* resvdPaRAMSets */
724 /* 31 0 63 32 95 64 127 96 */
725 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
726 /* 159 128 191 160 223 192 255 224 */
727 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
728 /* 287 256 319 288 351 320 383 352 */
729 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
730 /* 415 384 447 416 479 448 511 480 */
731 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
733 /* resvdDmaChannels */
734 /* 31 0 63 32 */
735 {0x00000000u, 0x00000000u},
737 /* resvdQdmaChannels */
738 /* 31 0 */
739 {0x00000000u},
741 /* resvdTccs */
742 /* 31 0 63 32 */
743 {0x00000000u, 0x00000000u},
744 },
746 /* Resources owned/reserved by region 6 */
747 {
748 /* ownPaRAMSets */
749 /* 31 0 63 32 95 64 127 96 */
750 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
751 /* 159 128 191 160 223 192 255 224 */
752 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
753 /* 287 256 319 288 351 320 383 352 */
754 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
755 /* 415 384 447 416 479 448 511 480 */
756 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
758 /* ownDmaChannels */
759 /* 31 0 63 32 */
760 {0x00000000u, 0x00000000u},
762 /* ownQdmaChannels */
763 /* 31 0 */
764 {0x00000000u},
766 /* ownTccs */
767 /* 31 0 63 32 */
768 {0x00000000u, 0x00000000u},
770 /* resvdPaRAMSets */
771 /* 31 0 63 32 95 64 127 96 */
772 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
773 /* 159 128 191 160 223 192 255 224 */
774 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
775 /* 287 256 319 288 351 320 383 352 */
776 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
777 /* 415 384 447 416 479 448 511 480 */
778 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
780 /* resvdDmaChannels */
781 /* 31 0 63 32 */
782 {0x00000000u, 0x00000000u},
784 /* resvdQdmaChannels */
785 /* 31 0 */
786 {0x00000000u},
788 /* resvdTccs */
789 /* 31 0 63 32 */
790 {0x00000000u, 0x00000000u},
791 },
793 /* Resources owned/reserved by region 7 */
794 {
795 /* ownPaRAMSets */
796 /* 31 0 63 32 95 64 127 96 */
797 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
798 /* 159 128 191 160 223 192 255 224 */
799 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
800 /* 287 256 319 288 351 320 383 352 */
801 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
802 /* 415 384 447 416 479 448 511 480 */
803 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
805 /* ownDmaChannels */
806 /* 31 0 63 32 */
807 {0x00000000u, 0x00000000u},
809 /* ownQdmaChannels */
810 /* 31 0 */
811 {0x00000000u},
813 /* ownTccs */
814 /* 31 0 63 32 */
815 {0x00000000u, 0x00000000u},
817 /* resvdPaRAMSets */
818 /* 31 0 63 32 95 64 127 96 */
819 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
820 /* 159 128 191 160 223 192 255 224 */
821 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
822 /* 287 256 319 288 351 320 383 352 */
823 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
824 /* 415 384 447 416 479 448 511 480 */
825 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
827 /* resvdDmaChannels */
828 /* 31 0 63 32 */
829 {0x00000000u, 0x00000000u},
831 /* resvdQdmaChannels */
832 /* 31 0 */
833 {0x00000000u},
835 /* resvdTccs */
836 /* 31 0 63 32 */
837 {0x00000000u, 0x00000000u},
838 },
839 },
841 /* EDMA3 INSTANCE# 1 */
842 {
843 /* Resources owned/reserved by region 0 */
844 {
845 /* ownPaRAMSets */
846 /* 31 0 63 32 95 64 127 96 */
847 {0x0000FFFFu, 0x000F0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
848 /* 159 128 191 160 223 192 255 224 */
849 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
850 /* 287 256 319 288 351 320 383 352 */
851 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
852 /* 415 384 447 416 479 448 511 480 */
853 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
855 /* ownDmaChannels */
856 /* 31 0 63 32 */
857 {0x0000FFFFu, 0x000F0000u},
859 /* ownQdmaChannels */
860 /* 31 0 */
861 {0x00000003u},
863 /* ownTccs */
864 /* 31 0 63 32 */
865 {0x0000FFFFu, 0x000F0000u},
867 /* resvdPaRAMSets */
868 /* 31 0 63 32 95 64 127 96 */
869 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
870 /* 159 128 191 160 223 192 255 224 */
871 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
872 /* 287 256 319 288 351 320 383 352 */
873 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
874 /* 415 384 447 416 479 448 511 480 */
875 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
877 /* resvdDmaChannels */
878 /* 31 0 63 32 */
879 {0x00003FFFu, 0x00000000u},
881 /* resvdQdmaChannels */
882 /* 31 0 */
883 {0x00000000u},
885 /* resvdTccs */
886 /* 31 0 63 32 */
887 {0x00003FFFu, 0x00000000u},
888 },
890 /* Resources owned/reserved by region 1 */
891 {
892 /* ownPaRAMSets */
893 /* 31 0 63 32 95 64 127 96 */
894 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
895 /* 159 128 191 160 223 192 255 224 */
896 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
897 /* 287 256 319 288 351 320 383 352 */
898 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
899 /* 415 384 447 416 479 448 511 480 */
900 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
902 /* ownDmaChannels */
903 /* 31 0 63 32 */
904 {0xFFFF0000u, 0x00000000u},
906 /* ownQdmaChannels */
907 /* 31 0 */
908 {0x0000000Cu},
910 /* ownTccs */
911 /* 31 0 63 32 */
912 {0xFFFF0000u, 0x00000000u},
914 /* resvdPaRAMSets */
915 /* 31 0 63 32 95 64 127 96 */
916 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
917 /* 159 128 191 160 223 192 255 224 */
918 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
919 /* 287 256 319 288 351 320 383 352 */
920 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
921 /* 415 384 447 416 479 448 511 480 */
922 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
924 /* resvdDmaChannels */
925 /* 31 0 63 32 */
926 {0x3FFF0000u, 0x00000000u},
928 /* resvdQdmaChannels */
929 /* 31 0 */
930 {0x00000000u},
932 /* resvdTccs */
933 /* 31 0 63 32 */
934 {0x3FFF0000u, 0x00000000u},
935 },
937 /* Resources owned/reserved by region 2 */
938 {
939 /* ownPaRAMSets */
940 /* 31 0 63 32 95 64 127 96 */
941 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
942 /* 159 128 191 160 223 192 255 224 */
943 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
944 /* 287 256 319 288 351 320 383 352 */
945 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
946 /* 415 384 447 416 479 448 511 480 */
947 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
949 /* ownDmaChannels */
950 /* 31 0 63 32 */
951 {0x00000000u, 0x0000FFFFu},
953 /* ownQdmaChannels */
954 /* 31 0 */
955 {0x00000030u},
957 /* ownTccs */
958 /* 31 0 63 32 */
959 {0x00000000u, 0x0000FFFFu},
961 /* resvdPaRAMSets */
962 /* 31 0 63 32 95 64 127 96 */
963 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
964 /* 159 128 191 160 223 192 255 224 */
965 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
966 /* 287 256 319 288 351 320 383 352 */
967 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
968 /* 415 384 447 416 479 448 511 480 */
969 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
971 /* resvdDmaChannels */
972 /* 31 0 63 32 */
973 {0x00000000u, 0x00003FFFu},
975 /* resvdQdmaChannels */
976 /* 31 0 */
977 {0x00000000u},
979 /* resvdTccs */
980 /* 31 0 63 32 */
981 {0x00000000u, 0x00003FFFu},
982 },
984 /* Resources owned/reserved by region 3 */
985 {
986 /* ownPaRAMSets */
987 /* 31 0 63 32 95 64 127 96 */
988 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
989 /* 159 128 191 160 223 192 255 224 */
990 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
991 /* 287 256 319 288 351 320 383 352 */
992 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
993 /* 415 384 447 416 479 448 511 480 */
994 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
996 /* ownDmaChannels */
997 /* 31 0 63 32 */
998 {0x00000000u, 0xFFFF0000u},
1000 /* ownQdmaChannels */
1001 /* 31 0 */
1002 {0x000000C0u},
1004 /* ownTccs */
1005 /* 31 0 63 32 */
1006 {0x00000000u, 0xFFFF0000u},
1008 /* resvdPaRAMSets */
1009 /* 31 0 63 32 95 64 127 96 */
1010 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
1011 /* 159 128 191 160 223 192 255 224 */
1012 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1013 /* 287 256 319 288 351 320 383 352 */
1014 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1015 /* 415 384 447 416 479 448 511 480 */
1016 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1018 /* resvdDmaChannels */
1019 /* 31 0 63 32 */
1020 {0x00000000u, 0x3FFF0000u},
1022 /* resvdQdmaChannels */
1023 /* 31 0 */
1024 {0x00000000u},
1026 /* resvdTccs */
1027 /* 31 0 63 32 */
1028 {0x00000000u, 0x3FFF0000u},
1029 },
1031 /* Resources owned/reserved by region 4 */
1032 {
1033 /* ownPaRAMSets */
1034 /* 31 0 63 32 95 64 127 96 */
1035 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1036 /* 159 128 191 160 223 192 255 224 */
1037 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1038 /* 287 256 319 288 351 320 383 352 */
1039 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1040 /* 415 384 447 416 479 448 511 480 */
1041 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1043 /* ownDmaChannels */
1044 /* 31 0 63 32 */
1045 {0x00000000u, 0x00000000u},
1047 /* ownQdmaChannels */
1048 /* 31 0 */
1049 {0x00000000u},
1051 /* ownTccs */
1052 /* 31 0 63 32 */
1053 {0x00000000u, 0x00000000u},
1055 /* resvdPaRAMSets */
1056 /* 31 0 63 32 95 64 127 96 */
1057 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1058 /* 159 128 191 160 223 192 255 224 */
1059 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1060 /* 287 256 319 288 351 320 383 352 */
1061 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1062 /* 415 384 447 416 479 448 511 480 */
1063 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1065 /* resvdDmaChannels */
1066 /* 31 0 63 32 */
1067 {0x00000000u, 0x00000000u},
1069 /* resvdQdmaChannels */
1070 /* 31 0 */
1071 {0x00000000u},
1073 /* resvdTccs */
1074 /* 31 0 63 32 */
1075 {0x00000000u, 0x00000000u},
1076 },
1078 /* Resources owned/reserved by region 5 */
1079 {
1080 /* ownPaRAMSets */
1081 /* 31 0 63 32 95 64 127 96 */
1082 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1083 /* 159 128 191 160 223 192 255 224 */
1084 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1085 /* 287 256 319 288 351 320 383 352 */
1086 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1087 /* 415 384 447 416 479 448 511 480 */
1088 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1090 /* ownDmaChannels */
1091 /* 31 0 63 32 */
1092 {0x00000000u, 0x00000000u},
1094 /* ownQdmaChannels */
1095 /* 31 0 */
1096 {0x00000000u},
1098 /* ownTccs */
1099 /* 31 0 63 32 */
1100 {0x00000000u, 0x00000000u},
1102 /* resvdPaRAMSets */
1103 /* 31 0 63 32 95 64 127 96 */
1104 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1105 /* 159 128 191 160 223 192 255 224 */
1106 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1107 /* 287 256 319 288 351 320 383 352 */
1108 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1109 /* 415 384 447 416 479 448 511 480 */
1110 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1112 /* resvdDmaChannels */
1113 /* 31 0 63 32 */
1114 {0x00000000u, 0x00000000u},
1116 /* resvdQdmaChannels */
1117 /* 31 0 */
1118 {0x00000000u},
1120 /* resvdTccs */
1121 /* 31 0 63 32 */
1122 {0x00000000u, 0x00000000u},
1123 },
1125 /* Resources owned/reserved by region 6 */
1126 {
1127 /* ownPaRAMSets */
1128 /* 31 0 63 32 95 64 127 96 */
1129 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1130 /* 159 128 191 160 223 192 255 224 */
1131 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1132 /* 287 256 319 288 351 320 383 352 */
1133 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1134 /* 415 384 447 416 479 448 511 480 */
1135 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1137 /* ownDmaChannels */
1138 /* 31 0 63 32 */
1139 {0x00000000u, 0x00000000u},
1141 /* ownQdmaChannels */
1142 /* 31 0 */
1143 {0x00000000u},
1145 /* ownTccs */
1146 /* 31 0 63 32 */
1147 {0x00000000u, 0x00000000u},
1149 /* resvdPaRAMSets */
1150 /* 31 0 63 32 95 64 127 96 */
1151 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1152 /* 159 128 191 160 223 192 255 224 */
1153 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1154 /* 287 256 319 288 351 320 383 352 */
1155 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1156 /* 415 384 447 416 479 448 511 480 */
1157 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1159 /* resvdDmaChannels */
1160 /* 31 0 63 32 */
1161 {0x00000000u, 0x00000000u},
1163 /* resvdQdmaChannels */
1164 /* 31 0 */
1165 {0x00000000u},
1167 /* resvdTccs */
1168 /* 31 0 63 32 */
1169 {0x00000000u, 0x00000000u},
1170 },
1172 /* Resources owned/reserved by region 7 */
1173 {
1174 /* ownPaRAMSets */
1175 /* 31 0 63 32 95 64 127 96 */
1176 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1177 /* 159 128 191 160 223 192 255 224 */
1178 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1179 /* 287 256 319 288 351 320 383 352 */
1180 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1181 /* 415 384 447 416 479 448 511 480 */
1182 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1184 /* ownDmaChannels */
1185 /* 31 0 63 32 */
1186 {0x00000000u, 0x00000000u},
1188 /* ownQdmaChannels */
1189 /* 31 0 */
1190 {0x00000000u},
1192 /* ownTccs */
1193 /* 31 0 63 32 */
1194 {0x00000000u, 0x00000000u},
1196 /* resvdPaRAMSets */
1197 /* 31 0 63 32 95 64 127 96 */
1198 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1199 /* 159 128 191 160 223 192 255 224 */
1200 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1201 /* 287 256 319 288 351 320 383 352 */
1202 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1203 /* 415 384 447 416 479 448 511 480 */
1204 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1206 /* resvdDmaChannels */
1207 /* 31 0 63 32 */
1208 {0x00000000u, 0x00000000u},
1210 /* resvdQdmaChannels */
1211 /* 31 0 */
1212 {0x00000000u},
1214 /* resvdTccs */
1215 /* 31 0 63 32 */
1216 {0x00000000u, 0x00000000u},
1217 },
1218 },
1220 };
1222 /* End of File */