084fe013485530c638c7e2b866c972cab7aeda1a
2 /*
3 Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/
4 All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
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12 *
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14 * notice, this list of conditions and the following disclaimer in the
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17 *
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20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 *
34 */
36 //
37 // I/O device configuration data structure definitions D10 (DA10x EVM).
40 // -----------------------------------------------------------------------------
41 // This file contains the necessary configurations and functions for
42 // using the DA10x Audio DC card in the PA environment. In particular, the
43 // SAP configurations are referenced in the pa(i/y)-evmda10x-io.c files
44 // for use in IOS (Input/Output Switching) shortcuts. Each configuration
45 // contains settings appropriate to the various devices on the DA10x-AudioDC;
46 // the DIR, DACs, ADCs, and DIT output. Also each configuration points to
47 // a common control function (D10_sapControl), which handles the various
48 // requests made by the PA framework.
50 // A note about clocking. There are two different master clocks
51 // available corresponding to the two primary input choices, DIR and ADC.
52 //
53 // DIR:
54 // . 512fs @ <= 48kHz
55 // . 256fs @ > 48kHz & <=96 kHz
56 // . 128fs @ > 96kHz
57 // ADC:
58 // . 768fs @ 32kHz
59 // . 512fs @ 48kHz
60 // . 256fs @ 96kHz
61 //
62 // This faciliates the logic used for the McASP transmit sections TX0 (DAC) and
63 // TX2 (DIT) which divide the master clock down to generate bit and frame clocks.
65 // -----------------------------------------------------------------------------
66 // Includes
68 #include <sap_d10.h>
69 #include <audio_dc_cfg.h>
70 #include "vproccmds_a.h"
72 #include "dbgBenchmark.h" // PCM high-sampling rate + SRC + CAR benchmarking
75 // -----------------------------------------------------------------------------
76 // Local function declarations
78 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg);
79 static inline XDAS_Int32 initD10 (DEV2_Handle device) ;
80 static XDAS_Int32 clockMuxTx (int sel, int force);
81 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut);
82 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX);
84 void HSR4_readStatus (PAF_SIO_InputStatus *pStatus);
85 unsigned int HDMIGpioGetState (void);
86 // -----------------------------------------------------------------------------
87 // State machine variables and defines
89 // flag to facilitate one time initialization of DA10x Audio hardware
90 // 0 ==> not initialized, 1 ==> initialized
91 static char initDone = 0;
93 // input status
94 static PAF_SIO_InputStatus primaryStatus =
95 {
96 0, // lock
97 PAF_IEC_AUDIOMODE_UNKNOWN, // nonaudio
98 PAF_IEC_PREEMPHASIS_UNKNOWN, // emphasis
99 PAF_SAMPLERATE_UNKNOWN, // sampleRateMeasured
100 PAF_SAMPLERATE_UNKNOWN, // sampleRateData
101 0,0,0, // unused
102 };
105 // The McASP outputs (both for DAC and DIT) receive a high speed clock
106 // and in turn generate a bit and frame clock. The needed clock divider
107 // values are kept here for easy lookup.
108 unsigned char *pClkxDiv = NULL;
110 static const unsigned char clkxDivDIR[PAF_SAMPLERATE_N] =
111 {
112 0x2, //PAF_SAMPLERATE_UNKNOWN
113 0x8, //PAF_SAMPLERATE_NONE
114 0x8, //PAF_SAMPLERATE_32000HZ
115 0x2, //PAF_SAMPLERATE_44100HZ
116 0x2, //PAF_SAMPLERATE_48000HZ
117 0x4, //PAF_SAMPLERATE_88200HZ
118 0x2, //PAF_SAMPLERATE_96000HZ
119 0x2, //PAF_SAMPLERATE_192000HZ
120 0x4, //PAF_SAMPLERATE_64000HZ
121 0x2, //PAF_SAMPLERATE_128000HZ
122 0x2, //PAF_SAMPLERATE_176400HZ
123 0x8, //PAF_SAMPLERATE_8000HZ
124 0x8, //PAF_SAMPLERATE_11025HZ
125 0x8, //PAF_SAMPLERATE_12000HZ
126 0x8, //PAF_SAMPLERATE_16000HZ
127 0x8, //PAF_SAMPLERATE_22050HZ
128 0x8, //PAF_SAMPLERATE_24000HZ
129 };
132 static const unsigned char clkxDivADC[PAF_SAMPLERATE_N] =
133 {
134 0x8, //PAF_SAMPLERATE_UNKNOWN
135 0x8, //PAF_SAMPLERATE_NONE
136 0xC, //PAF_SAMPLERATE_32000HZ
137 0x8, //PAF_SAMPLERATE_44100HZ
138 0x8, //PAF_SAMPLERATE_48000HZ
139 0x4, //PAF_SAMPLERATE_88200HZ
140 0x4, //PAF_SAMPLERATE_96000HZ
141 0x2, //PAF_SAMPLERATE_192000HZ
142 0x4, //PAF_SAMPLERATE_64000HZ
143 0x2, //PAF_SAMPLERATE_128000HZ
144 0x2, //PAF_SAMPLERATE_176400HZ
145 0x8, //PAF_SAMPLERATE_8000HZ
146 0x8, //PAF_SAMPLERATE_11025HZ
147 0x8, //PAF_SAMPLERATE_12000HZ
148 0x8, //PAF_SAMPLERATE_16000HZ
149 0x8, //PAF_SAMPLERATE_22050HZ
150 0x8, //PAF_SAMPLERATE_24000HZ
151 };
153 static const unsigned char clkxDivHDMI[PAF_SAMPLERATE_N] =
154 {
155 0x2, //PAF_SAMPLERATE_UNKNOWN
156 0x2, //PAF_SAMPLERATE_NONE
157 0x8, //PAF_SAMPLERATE_32000HZ
158 0x2, //PAF_SAMPLERATE_44100HZ
159 0x2, //PAF_SAMPLERATE_48000HZ
160 0x4, //PAF_SAMPLERATE_88200HZ
161 0x1, //PAF_SAMPLERATE_96000HZ
162 0x2, //PAF_SAMPLERATE_192000HZ
163 0x4, //PAF_SAMPLERATE_64000HZ
164 0x2, //PAF_SAMPLERATE_128000HZ
165 0x2, //PAF_SAMPLERATE_176400HZ
166 0x8, //PAF_SAMPLERATE_8000HZ
167 0x8, //PAF_SAMPLERATE_11025HZ
168 0x8, //PAF_SAMPLERATE_12000HZ
169 0x8, //PAF_SAMPLERATE_16000HZ
170 0x8, //PAF_SAMPLERATE_22050HZ
171 0x8, //PAF_SAMPLERATE_24000HZ
172 };
174 // The ADCs, when operating as the master input, can only
175 // generate a limited set of audio sample rates since the clock
176 // is derived from AUXCLK which is the oscillator connected to the DSP.
177 // This table faciliates the access and definition of these rates.
178 static const Uint16 oscRateTable[8] =
179 {
180 PAF_SAMPLERATE_UNKNOWN, // 0
181 PAF_SAMPLERATE_32000HZ,
182 PAF_SAMPLERATE_44100HZ, // D10_RATE_44_1KHZ
183 PAF_SAMPLERATE_48000HZ,
184 PAF_SAMPLERATE_88200HZ, // D10_RATE_88_2KHZ
185 PAF_SAMPLERATE_96000HZ,
186 PAF_SAMPLERATE_176400HZ, // D10_RATE_176_4KHZ
187 PAF_SAMPLERATE_192000HZ
188 };
190 static const Uint16 RateTable_hdmi[8] =
191 {
192 PAF_SAMPLERATE_UNKNOWN, // HSDIO_AudioFreq_RESERVED
193 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
194 PAF_SAMPLERATE_44100HZ, // HSDIO_AudioFreq_44_1K
195 PAF_SAMPLERATE_48000HZ, // HSDIO_AudioFreq_48K
196 PAF_SAMPLERATE_88200HZ, // HSDIO_AudioFreq_88_2K
197 PAF_SAMPLERATE_96000HZ, // HSDIO_AudioFreq_96_4K
198 PAF_SAMPLERATE_176400HZ, // HSDIO_AudioFreq_176_4K
199 PAF_SAMPLERATE_192000HZ // HSDIO_AudioFreq_192K
200 };
202 static const Uint16 RateTable_spdif[4] =
203 {
204 PAF_SAMPLERATE_44100HZ, // AudioFreq_44_1K
205 PAF_SAMPLERATE_48000HZ, // AudioFreq_48K
206 PAF_SAMPLERATE_UNKNOWN, // AudioFreq_RESERVED
207 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
208 };
211 // base mcasp addresses for easy lookup
212 static volatile Uint32 * mcaspAddr[_MCASP_PORT_CNT] =
213 {
214 (volatile Uint32 *) _MCASP_BASE_PORT0,
215 (volatile Uint32 *) _MCASP_BASE_PORT1,
216 (volatile Uint32 *) _MCASP_BASE_PORT2
217 };
219 // The DA10x HW is configured for the DAC's mute lines to be operated based
220 // on McASP0's AMUTE (out) line. This is the hard mute.
221 static inline void dacHardMute (void) {
222 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
223 mcasp0[_MCASP_PDOUT_OFFSET] |= _MCASP_PDOUT_AMUTE_MASK;
224 }
225 static inline void dacHardUnMute (void) {
226 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
227 mcasp0[_MCASP_PDOUT_OFFSET] &= ~_MCASP_PDOUT_AMUTE_MASK;
228 mcasp0[_MCASP_AMUTE_OFFSET] |= MCASP_AMUTE_MUTEN_ERRLOW;
229 }
231 // How should the PCM18x DAC's soft mute functionality be used here?
232 // i.e, as different from the hard mute? need to review.
233 static inline void dacSoftMute (void) {
234 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
235 mcasp0[6] = 0x000 ;
236 mcasp0[6] = 0x400 ;
237 }
238 static inline void dacSoftUnMute (void) {
239 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
240 mcasp0[6] = 0x000 ;
241 mcasp0[6] = 0x400 ;
242 }
244 // -----------------------------------------------------------------------------
245 // McASP Input Configuration Definitions
247 static const MCASP_ConfigRcv rxConfigDIR =
248 {
249 MCASP_RMASK_OF(0xFFFFFFFF),
250 MCASP_RFMT_RMK(
251 MCASP_RFMT_RDATDLY_1BIT,
252 MCASP_RFMT_RRVRS_MSBFIRST,
253 MCASP_RFMT_RPAD_RPBIT,
254 MCASP_RFMT_RPBIT_OF(0),
255 MCASP_RFMT_RSSZ_32BITS,
256 MCASP_RFMT_RBUSEL_DAT,
257 MCASP_RFMT_RROT_NONE),
258 MCASP_AFSRCTL_RMK(
259 MCASP_AFSRCTL_RMOD_OF(2),
260 MCASP_AFSRCTL_FRWID_WORD,
261 MCASP_AFSRCTL_FSRM_EXTERNAL,
262 MCASP_AFSRCTL_FSRP_ACTIVELOW),
263 MCASP_ACLKRCTL_RMK(
264 MCASP_ACLKRCTL_CLKRP_RISING,
265 MCASP_ACLKRCTL_CLKRM_EXTERNAL,
266 MCASP_ACLKRCTL_CLKRDIV_DEFAULT),
267 MCASP_AHCLKRCTL_RMK(
268 MCASP_AHCLKRCTL_HCLKRM_EXTERNAL,
269 MCASP_AHCLKRCTL_HCLKRP_RISING,
270 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
271 MCASP_RTDM_OF(3),
272 MCASP_RINTCTL_DEFAULT,
273 MCASP_RCLKCHK_DEFAULT
274 };
276 static const MCASP_ConfigRcv rxConfigADC =
277 {
278 MCASP_RMASK_OF(0xFFFFFFFF),
279 MCASP_RFMT_RMK(
280 MCASP_RFMT_RDATDLY_1BIT,
281 MCASP_RFMT_RRVRS_MSBFIRST,
282 MCASP_RFMT_RPAD_RPBIT,
283 MCASP_RFMT_RPBIT_OF(0),
284 MCASP_RFMT_RSSZ_32BITS,
285 MCASP_RFMT_RBUSEL_DAT,
286 MCASP_RFMT_RROT_NONE),
287 MCASP_AFSRCTL_RMK(
288 MCASP_AFSRCTL_RMOD_OF(2),
289 MCASP_AFSRCTL_FRWID_WORD,
290 MCASP_AFSRCTL_FSRM_INTERNAL,
291 MCASP_AFSRCTL_FSRP_ACTIVEHIGH),
292 MCASP_ACLKRCTL_RMK(
293 MCASP_ACLKRCTL_CLKRP_RISING,
294 MCASP_ACLKRCTL_CLKRM_INTERNAL,
295 MCASP_ACLKXCTL_CLKXDIV_OF(7)),
296 MCASP_AHCLKRCTL_RMK(
297 MCASP_AHCLKRCTL_HCLKRM_INTERNAL,
298 MCASP_AHCLKRCTL_HCLKRP_RISING,
299 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
300 MCASP_RTDM_OF(3),
301 MCASP_RINTCTL_DEFAULT,
302 MCASP_RCLKCHK_DEFAULT
303 };
305 // -----------------------------------------------------------------------------
306 // McASP Output Configuration Definitions
308 static const MCASP_ConfigXmt txConfigDAC =
309 {
310 MCASP_XMASK_OF(0xFFFFFFFF),
311 MCASP_XFMT_RMK(
312 MCASP_XFMT_XDATDLY_1BIT,
313 MCASP_XFMT_XRVRS_MSBFIRST,
314 MCASP_XFMT_XPAD_ZERO,
315 MCASP_XFMT_XPBIT_DEFAULT,
316 MCASP_XFMT_XSSZ_32BITS,
317 MCASP_XFMT_XBUSEL_DAT,
318 MCASP_XFMT_XROT_NONE),
319 MCASP_AFSXCTL_RMK(
320 MCASP_AFSXCTL_XMOD_OF(2),
321 MCASP_AFSXCTL_FXWID_WORD,
322 MCASP_AFSXCTL_FSXM_INTERNAL,
323 MCASP_AFSXCTL_FSXP_ACTIVELOW),
324 MCASP_ACLKXCTL_RMK(
325 MCASP_ACLKXCTL_CLKXP_FALLING,
326 MCASP_ACLKXCTL_ASYNC_ASYNC,
327 MCASP_ACLKXCTL_CLKXM_INTERNAL,
328 MCASP_ACLKXCTL_CLKXDIV_DEFAULT),
329 MCASP_AHCLKXCTL_RMK(
330 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
331 MCASP_AHCLKXCTL_HCLKXP_FALLING,
332 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
333 MCASP_XTDM_OF(3),
334 MCASP_XINTCTL_DEFAULT,
335 MCASP_XCLKCHK_DEFAULT
336 };
338 static const MCASP_ConfigXmt txConfigDACSlave =
339 {
340 MCASP_XMASK_OF(0xFFFFFFFF),
341 MCASP_XFMT_RMK(
342 MCASP_XFMT_XDATDLY_1BIT,
343 MCASP_XFMT_XRVRS_MSBFIRST,
344 MCASP_XFMT_XPAD_ZERO,
345 MCASP_XFMT_XPBIT_DEFAULT,
346 MCASP_XFMT_XSSZ_32BITS,
347 MCASP_XFMT_XBUSEL_DAT,
348 MCASP_XFMT_XROT_NONE),
349 MCASP_AFSXCTL_RMK(
350 MCASP_AFSXCTL_XMOD_OF(2),
351 MCASP_AFSXCTL_FXWID_WORD,
352 MCASP_AFSXCTL_FSXM_INTERNAL,
353 MCASP_AFSXCTL_FSXP_ACTIVELOW),
354 MCASP_ACLKXCTL_RMK(
355 MCASP_ACLKXCTL_CLKXP_FALLING,
356 MCASP_ACLKXCTL_ASYNC_ASYNC,
357 MCASP_ACLKXCTL_CLKXM_INTERNAL,
358 MCASP_ACLKXCTL_CLKXDIV_OF(1)),
359 MCASP_AHCLKXCTL_RMK(
360 MCASP_AHCLKXCTL_HCLKXM_INTERNAL,
361 MCASP_AHCLKXCTL_HCLKXP_FALLING,
362 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
363 MCASP_XTDM_OF(3),
364 MCASP_XINTCTL_DEFAULT,
365 MCASP_XCLKCHK_DEFAULT
366 };
368 static const MCASP_ConfigXmt txConfigDIT =
369 {
370 MCASP_XMASK_OF(0x00FFFFFF),
371 MCASP_XFMT_RMK(
372 MCASP_XFMT_XDATDLY_1BIT,
373 MCASP_XFMT_XRVRS_LSBFIRST,
374 MCASP_XFMT_XPAD_DEFAULT,
375 MCASP_XFMT_XPBIT_DEFAULT,
376 MCASP_XFMT_XSSZ_32BITS,
377 MCASP_XFMT_XBUSEL_DAT,
378 MCASP_XFMT_XROT_NONE),
379 MCASP_AFSXCTL_RMK(
380 MCASP_AFSXCTL_XMOD_OF(0x180),
381 MCASP_AFSXCTL_FXWID_BIT,
382 MCASP_AFSXCTL_FSXM_INTERNAL,
383 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
384 MCASP_ACLKXCTL_RMK(
385 MCASP_ACLKXCTL_CLKXP_FALLING,
386 MCASP_ACLKXCTL_ASYNC_ASYNC,
387 MCASP_ACLKXCTL_CLKXM_INTERNAL,
388 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
389 MCASP_AHCLKXCTL_RMK(
390 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
391 MCASP_AHCLKXCTL_HCLKXP_FALLING,
392 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
393 MCASP_XTDM_OF(0xFFFFFFFF),
394 MCASP_XINTCTL_DEFAULT,
395 MCASP_XCLKCHK_DEFAULT
396 };
398 #if 0
399 static const MCASP_ConfigXmt txConfigDIT_16bit =
400 {
401 MCASP_XMASK_OF(0x0000FFFF),
402 MCASP_XFMT_RMK(
403 MCASP_XFMT_XDATDLY_1BIT,
404 MCASP_XFMT_XRVRS_LSBFIRST,
405 MCASP_XFMT_XPAD_DEFAULT,
406 MCASP_XFMT_XPBIT_DEFAULT,
407 MCASP_XFMT_XSSZ_32BITS,
408 MCASP_XFMT_XBUSEL_DAT,
409 MCASP_XFMT_XROT_24BITS),
410 MCASP_AFSXCTL_RMK(
411 MCASP_AFSXCTL_XMOD_OF(0x180),
412 MCASP_AFSXCTL_FXWID_BIT,
413 MCASP_AFSXCTL_FSXM_INTERNAL,
414 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
415 MCASP_ACLKXCTL_RMK(
416 MCASP_ACLKXCTL_CLKXP_FALLING,
417 MCASP_ACLKXCTL_ASYNC_ASYNC,
418 MCASP_ACLKXCTL_CLKXM_INTERNAL,
419 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
420 MCASP_AHCLKXCTL_RMK(
421 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
422 MCASP_AHCLKXCTL_HCLKXP_FALLING,
423 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
424 MCASP_XTDM_OF(0xFFFFFFFF),
425 MCASP_XINTCTL_DEFAULT,
426 MCASP_XCLKCHK_DEFAULT
427 };
428 #endif
430 // -----------------------------------------------------------------------------
431 // DAP Input Parameter Definitions
433 const SAP_D10_Rx_Params SAP_D10_RX_DIR =
434 {
435 sizeof (SAP_D10_Rx_Params), // size
436 "SAP", // name
437 MCASP_DEV2, // moduleNum --> mcasp #
438 (Void *)&rxConfigDIR, // pConfig
439 4, // wordSize (unused)
440 24, // precision (unused)
441 D10_sapControl, // control
442 0x00000020, // pinMask
443 (D10_MCLK_DIR << D10_MCLK_SHIFT), // mode
444 0,0 // unused[2]
445 };
447 const SAP_D10_Rx_Params SAP_D10_RX_ADC_44100HZ =
448 {
449 sizeof (SAP_D10_Rx_Params), // size
450 "SAP", // name
451 MCASP_DEV1, // moduleNum --> mcasp #
452 (Void *)&rxConfigADC, // pConfig
453 4, // wordSize (unused)
454 24, // precision (unused)
455 D10_sapControl, // control
456 0xE000000F, // pinMask
457 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
458 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
459 0,0 // unused[2]
460 };
462 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_44100HZ =
463 {
464 sizeof (SAP_D10_Rx_Params), // size
465 "SAP", // name
466 MCASP_DEV1, // moduleNum --> mcasp #
467 (Void *)&rxConfigADC, // pConfig
468 -1, // wordSize (unused)
469 -1, // precision (unused)
470 D10_sapControl, // control
471 0xE0000007, // pinMask
472 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
473 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
474 0,0 // unused[2]
475 };
477 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_44100HZ =
478 {
479 sizeof (SAP_D10_Rx_Params), // size
480 "SAP", // name
481 MCASP_DEV1, // moduleNum --> mcasp #
482 (Void *)&rxConfigADC, // pConfig
483 -1, // wordSize (unused)
484 -1, // precision (unused)
485 D10_sapControl, // control
486 0xE0000001, // pinMask
487 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
488 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
489 0,0 // unused[2]
490 };
492 const SAP_D10_Rx_Params SAP_D10_RX_ADC_88200HZ =
493 {
494 sizeof (SAP_D10_Rx_Params), // size
495 "SAP", // name
496 MCASP_DEV1, // moduleNum --> mcasp #
497 (Void *)&rxConfigADC, // pConfig
498 -1, // wordSize (unused)
499 -1, // precision (unused)
500 D10_sapControl, // control
501 0xE000000F, // pinMask
502 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
503 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
504 0,0 // unused[2]
505 };
507 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_88200HZ =
508 {
509 sizeof (SAP_D10_Rx_Params), // size
510 "SAP", // name
511 MCASP_DEV1, // moduleNum --> mcasp #
512 (Void *)&rxConfigADC, // pConfig
513 -1, // wordSize (unused)
514 -1, // precision (unused)
515 D10_sapControl, // control
516 0xE0000007, // pinMask
517 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
518 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
519 0,0 // unused[2]
520 };
522 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_88200HZ =
523 {
524 sizeof (SAP_D10_Rx_Params), // size
525 "SAP", // name
526 MCASP_DEV1, // moduleNum --> mcasp #
527 (Void *)&rxConfigADC, // pConfig
528 -1, // wordSize (unused)
529 -1, // precision (unused)
530 D10_sapControl, // control
531 0xE0000001, // pinMask
532 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
533 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
534 0,0 // unused[2]
535 };
538 const SAP_D10_Rx_Params SAP_D10_RX_HDMI_STEREO =
539 {
540 sizeof (SAP_D10_Rx_Params), // size
541 "SAP", // name
542 MCASP_DEV0, // moduleNum --> mcasp #
543 (Void *)&rxConfigDIR, // pConfig
544 4, // wordSize (unused)
545 -1, // precision (unused)
546 D10_sapControl, // control
547 0x00001000, // pinMask
548 (D10_MODE_HDMI << D10_MODE_SHIFT) |
549 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
550 0,0 // unused[2]
551 };
553 const SAP_D10_Rx_Params SAP_D10_RX_HDMI =
554 {
555 sizeof (SAP_D10_Rx_Params), // size
556 "SAP", // name
557 MCASP_DEV0, // moduleNum --> mcasp #
558 (Void *)&rxConfigDIR, // pConfig
559 4, // wordSize (unused)
560 -1, // precision (unused)
561 D10_sapControl, // control
562 0xE000F000, // pinMask
563 (D10_MODE_HDMI << D10_MODE_SHIFT) |
564 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
565 0,0 // unused[2]
566 };
568 // -----------------------------------------------------------------------------
569 // SAP Output Parameter Definitions
571 const SAP_D10_Tx_Params SAP_D10_TX_DAC =
572 {
573 sizeof (SAP_D10_Tx_Params), // size
574 "SAP", // name
575 MCASP_DEV0, // moduleNum --> mcasp #
576 (Void *)&txConfigDAC, // pConfig
577 4, // wordSize (in bytes)
578 24, // precision (in bits)
579 D10_sapControl, // control
580 0x1600000F, // pinMask
581 0, // mode
582 0,0,0 // unused[3]
583 };
585 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC =
586 {
587 sizeof (SAP_D10_Tx_Params), // size
588 "SAP", // name
589 MCASP_DEV0, // moduleNum --> mcasp #
590 (Void *)&txConfigDAC, // pConfig
591 4, // wordSize (in bytes)
592 24, // precision (in bits)
593 D10_sapControl, // control
594 0x16000001, // pinMask
595 0, // mode
596 0,0,0 // unused[3]
597 };
599 const SAP_D10_Tx_Params SAP_D10_TX_DIT =
600 {
601 sizeof (SAP_D10_Tx_Params), // size
602 "SAP", // name
603 MCASP_DEV2, // moduleNum --> mcasp #
604 (Void *) &txConfigDIT, // pConfig
605 3, // wordSize (in bytes)
606 24, // precision (in bits)
607 D10_sapControl, // control
608 0x1C000001, // pinMask
609 0, // mode
610 0,0,0 // unused[3]
611 };
613 const SAP_D10_Tx_Params SAP_D10_TX_DAC_SLAVE =
614 {
615 sizeof (SAP_D10_Tx_Params), // size
616 "SAP", // name
617 MCASP_DEV0, // moduleNum --> mcasp #
618 (Void *)&txConfigDACSlave, // pConfig
619 4, // wordSize (in bytes)
620 24, // precision (in bits)
621 D10_sapControl, // control
622 0x1E00000F, // pinMask
623 0, // mode
624 0,0,0 // unused[3]
625 };
627 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC_SLAVE =
628 {
629 sizeof (SAP_D10_Tx_Params), // size
630 "SAP", // name
631 MCASP_DEV0, // moduleNum --> mcasp #
632 (Void *)&txConfigDAC, // pConfig
633 4, // wordSize (in bytes)
634 24, // precision (in bits)
635 D10_sapControl, // control
636 0x16000001, // pinMask
637 0, // mode
638 0,0,0 // unused[3]
639 };
641 const SAP_D10_Tx_Params SAP_D10_TX_DAC_12CH =
642 {
643 sizeof (SAP_D10_Tx_Params), // size
644 "SAP", // name
645 MCASP_DEV0, // moduleNum --> mcasp #
646 (Void *)&txConfigDAC, // pConfig
647 4, // wordSize (in bytes)
648 24, // precision (in bits)
649 D10_sapControl, // control
650 0x1600003F, // pinMask
651 0, // mode
652 0,0,0 // unused[3]
653 };
655 const SAP_D10_Tx_Params SAP_D10_TX_DAC_16CH =
656 {
657 sizeof (SAP_D10_Tx_Params), // size
658 "SAP", // name
659 MCASP_DEV0, // moduleNum --> mcasp #
660 (Void *)&txConfigDAC, // pConfig
661 4, // wordSize (in bytes)
662 24, // precision (in bits)
663 D10_sapControl, // control
664 0x160000FF, // pinMask
665 0, // mode
666 0,0,0 // unused[3]
667 };
670 // -----------------------------------------------------------------------------
671 // One time initialization of the DA10x audio hardware.
673 /* DAC default configuration parameters */
674 DacConfig dacCfg =
675 {
676 DAC_AMUTE_CTRL_SCKI_LOST, /* Amute event */
677 0, /* Amute control */
678 DAC_SAMPLING_MODE_SINGLE_RATE, /* Sampling mode */
679 DAC_DATA_FORMAT_I2S, /* Data format */
680 0, /* Soft mute control */
681 DAC_ATTENUATION_WIDE_RANGE, /* Attenuation mode */
682 DAC_DEEMP_44KHZ, /* De-emph control */
683 100 /* Volume */
684 };
685 /* ADC default configuration parameters */
686 AdcConfig adcCfg =
687 {
688 90, /* ADC gain */
689 ADC_INL_SE_VINL1, /* Left input mux for ADC1L */
690 ADC_INL_SE_VINL2, /* Left input mux for ADC2L */
691 ADC_INR_SE_VINR1, /* Right input mux for ADC1R */
692 ADC_INR_SE_VINR2, /* Right input mux for ADC2R */
693 ADC_RX_WLEN_24BIT, /* ADC word length */
694 ADC_DATA_FORMAT_I2S, /* ADC data format */
695 0
696 };
698 Platform_STATUS setAudioDacConfig(void)
699 {
700 Platform_STATUS status;
702 /* Initialize Audio DAC module */
703 status = audioDacConfig(DAC_DEVICE_ALL, &dacCfg);
704 if (status)
705 Log_info0("SAP_D10: Audio DAC Configuration Failed!!!\n");
706 return status;
708 }
710 static inline XDAS_Int32 initD10 (DEV2_Handle device)
711 {
712 Platform_STATUS status = Platform_EOK;
714 /* Initialize common audio configurations */
715 status = platformAudioInit();
716 if(status != Platform_EOK)
717 {
718 System_printf("Audio Init Failed!\n");
719 return status;
720 }
722 /* Initialize Audio ADC module */
723 status = audioAdcConfig(ADC_DEVICE_ALL, &adcCfg);
724 if(status != Platform_EOK)
725 {
726 platform_write("Audio ADC Configuration Failed!\n");
727 return status;
728 }
730 /* Setup DIR 9001 for SPDIF input operation */
731 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
732 status = audioDirConfig();
733 if(status != Platform_EOK)
734 {
735 Log_info0("Audio DIR Init Failed!\n");
736 return status;
737 }
739 #if 1
740 /* Setup HSR41 for HDMI input operation */
741 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
742 /* Initialize the HDMI Card */
743 while(HDMIGpioGetState());
744 status = audioHDMIConfig();
745 if(status != Platform_EOK)
746 {
747 Log_info0("Audio HDMI Init Failed!\n");
748 return status;
749 }
750 #endif
752 // This is needed because DAC configuration needs some default clocking.
753 // We start with S/PDIF, because it's onboard the Audio DC & has its own crystal.
754 // HDMI is an add-on board & Audio OSC would need AUX clocking - both unfit for "default".
755 // ADCs default clock is not available to clock the DAC with.
756 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
758 platform_delay(5000); // Without delay between these 2 calls system aborts.
760 status = setAudioDacConfig();
762 return status;
764 } //initD10
766 // -----------------------------------------------------------------------------
767 // The McASP TX section is *only* used as a master clock mux.
768 // Mux functionality is achieved by selecting either external high
769 // speed clocks (DIR/HDMI) or the internal AUXCLK (Audio_OSC). This is divided down
770 // output via ACLKX0 which is connected to the high speed input
771 // of TX0 (DAC) and TX2 (DIT).
773 static XDAS_Int32 clockMuxTx (int sel, int force)
774 {
775 Platform_STATUS status = 0;
776 // select clkxDiv table
777 if (sel == D10_MCLK_DIR)
778 {
779 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
780 pClkxDiv = (unsigned char *) clkxDivDIR;
781 }
782 else if (sel == D10_MCLK_HDMI)
783 {
784 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
785 pClkxDiv = (unsigned char *) clkxDivHDMI;
786 }
787 else if (sel == D10_MCLK_OSC)
788 {
789 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_OSC);
790 pClkxDiv = (unsigned char *) clkxDivADC;
791 }
793 platform_delay(20000);
795 return status;
796 } //clockMuxTx
799 // -----------------------------------------------------------------------------
800 // This function returns the input status of the specified device.
801 // This is called once when the device is opened
802 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter
803 // (PAF_SIO_CONTROL_GET_INPUT_STATUS).
804 int gHmint_ctr = 0, gNonAudio = 0, gLockStatus=0, gPrevAudio=0, gPrevLock=0;
805 int gSync_ctr, gLock_ctr, gAudioErr_ctr, gNonAudio_ctr = 0;
807 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut)
808 {
809 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
810 //volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
811 //volatile Uint32 *mcasp1 = (volatile Uint32 *) _MCASP_BASE_PORT1;
812 //volatile Uint32 *mcasp2 = (volatile Uint32 *) _MCASP_BASE_PORT2;
814 //Platform_STATUS status;
816 static int PrevSampRate = 0;
817 int RateHdmi =0;
819 /* Mode & MCLK info embedded statically in the Rx IO definition for SPDIF Input */
820 if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_DIR) &
821 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD))
822 {
823 pStatusIn->lock = !(platformAudioDirGetClkStatus());
824 pStatusIn->nonaudio = !(platformAudioDirGetAudioStatus());
825 pStatusIn->emphasis = platformAudioDirGetEmphStatus();
826 pStatusIn->sampleRateMeasured = RateTable_spdif[platformAudioDirGetFsOut()];
827 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
828 PrevSampRate = pStatusIn->sampleRateMeasured;
830 // GJ: Is this needed? Probably not.
831 // GJ: Mute Control during input-change seemingly intended.
832 //mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
833 //mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
835 }
836 /* Mode & MCLK info embedded statically in the Rx IO definition for ANALOG/ADC Input */
837 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_OSC) &
838 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD)) {
839 int adcRate = (pParams->d10rx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
841 pStatusIn->lock = 1;
842 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
843 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
844 pStatusIn->sampleRateMeasured = oscRateTable[adcRate];
845 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
847 }
848 /* Mode & MCLK info embedded statically in the Rx IO definition for HDMI */
849 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_HDMI) &
850 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_HDMI))
851 {
853 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
855 #ifndef _ENABLE_BENCHMARK_PCMHSR_SRC_CAR_
856 //
857 // Input interface rate hard-coded to 192 kHz to avoid I2C transactions.
858 // Temporary fix works for EC3 and MLP/MAT formats.
859 //
860 pStatusIn->lock = 1;
861 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
862 RateHdmi = PAF_SAMPLERATE_192000HZ;
863 pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
864 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
866 #else // _ENABLE_BENCHMARK_PCMHSR_SRC_CAR_
867 //
868 // Need to update input interface rate by consulting HSR4 over I2C for benchmarking configuration.
869 //
870 if(!HDMIGpioGetState())
871 {
872 clear_hdmi_hmint();
873 gHmint_ctr++;
875 RateHdmi=read_hdmi_samprate();
876 pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
877 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
878 PrevSampRate = pStatusIn->sampleRateMeasured;
880 switch(read_hdmi_errstatus())
881 {
882 case HSDIO_AudioErr_NO_ERROR:
883 {
884 gPrevLock=pStatusIn->lock;
885 gPrevAudio=pStatusIn->nonaudio;
886 pStatusIn->lock = 1;
887 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
888 break;
889 }
890 case HSDIO_AudioErr_AUDIO_NO_PLL_LOCK:
891 {
892 gLock_ctr++;
893 pStatusIn->lock = 0;
894 //pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
895 break;
896 }
897 case HSDIO_AudioErr_AUDIO_NO_AUDIO:
898 {
899 gAudioErr_ctr++;
900 //pStatusIn->lock = 1;
901 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_NONAUDIO;
902 break;
903 }
904 default:
905 while(1); // Control shouldn't be here.
906 }
908 if(HSDIO_AudioMClk_128X != read_hdmi_clockstatus())
909 {
910 gLock_ctr++;
911 pStatusIn->lock = 0;
912 }
913 else if (HSDIO_AudioPresent_HAS_AUDIO != read_hdmi_audiostatus())
914 {
915 gNonAudio_ctr++;
916 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_NONAUDIO;
917 }
918 }
919 else
920 {
921 pStatusIn->sampleRateMeasured = PrevSampRate;
922 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
923 }
924 #endif // _ENABLE_BENCHMARK_PCMHSR_SRC_CAR_
925 }
927 else
928 return -1; // Control shouldn't be here!
930 gNonAudio=pStatusIn->nonaudio;
931 gLockStatus=pStatusIn->lock;
933 // update another status if requested
934 if (pStatusOut)
935 *pStatusOut = *pStatusIn;
937 return 0;
938 } //manageInput
941 // -----------------------------------------------------------------------------
942 // This function configures the McASP TX clock dividers based on the
943 // master clock rate. This is called once when the device is opened
944 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter (PAF_SIO_CONTROL_SET_RATEX).
946 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX)
947 {
948 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
949 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
950 Uint32 divider;
953 if (!pClkxDiv)
954 return SIO2_EINVAL;
956 // set clock divider
957 if (rateX < .354)
958 rateX = 0.25;
959 else if (rateX < .707)
960 rateX = 0.50;
961 else if (rateX < 1.6)
962 rateX = 1.00;
963 else if (rateX < 2.828)
964 rateX = 2.00;
965 else
966 rateX = 4.00;
967 // if asynchronous then force clock change (assumes osc master)
968 if (pParams->d10tx.mode & D10_SYNC_MASK) {
969 int dacRate = (pParams->d10tx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
970 divider = pClkxDiv[oscRateTable[dacRate]];
971 }
972 else
973 divider = pClkxDiv[pStatusIn->sampleRateMeasured];
974 divider /= rateX;
976 Log_info2("SAP_D10: Inside manageOutput with divider = %d, rateX = %f", divider, rateX);
978 // DIT requires 2x clock
979 if ((mcasp[_MCASP_AFSXCTL_OFFSET] & _MCASP_AFSXCTL_XMOD_MASK) ==
980 (MCASP_AFSXCTL_XMOD_OF(0x180) << _MCASP_AFSXCTL_XMOD_SHIFT)) {
981 if (divider < 2)
982 return (SIO2_EINVAL);
983 divider >>= 1;
984 }
986 mcasp[_MCASP_ACLKXCTL_OFFSET] =
987 (mcasp[_MCASP_ACLKXCTL_OFFSET] & ~_MCASP_ACLKXCTL_CLKXDIV_MASK) |
988 (MCASP_ACLKXCTL_CLKXDIV_OF(divider-1) << _MCASP_ACLKXCTL_CLKXDIV_SHIFT);
989 return 0;
990 } //manageOutput
992 // -----------------------------------------------------------------------------
993 // This function is called by the peripheral driver (DAP) in response to
994 // various SIO_ctrl() calls made by the framework.
996 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg)
997 {
998 const SAP_D10_Rx_Params *pDapD10RxParams = (const SAP_D10_Rx_Params *)pParams;
999 const SAP_D10_Tx_Params *pDapD10TxParams = (const SAP_D10_Tx_Params *)pParams;
1000 //Platform_STATUS status;
1002 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
1003 XDAS_Int32 result = 0;
1005 // perform one time hardware initialization
1006 if (!initDone) {
1007 result = initD10 (device);
1008 if (result)
1009 return result;
1010 initDone = 1;
1011 }
1013 switch (code) {
1015 // .............................................................................
1016 // This case provides a regular entry point for managing the specified
1017 // input device. Nominally, this is used to provide lock and sample rate
1018 // status to the framework.
1020 case PAF_SIO_CONTROL_GET_INPUT_STATUS:
1021 if (device->mode != DEV2_INPUT)
1022 return SIO2_EINVAL;
1024 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1025 break;
1027 // .............................................................................
1028 // This case provides a regular entry point for managing the specified
1029 // output device. Nominally this is used to change the output clock dividers
1030 // in the case of double rate output (e.g. DTS 96/24).
1032 case PAF_SIO_CONTROL_SET_RATEX:
1033 // Support only output rate control, for now
1034 if (device->mode != DEV2_OUTPUT)
1035 return (SIO2_EINVAL);
1037 // configure clock divider (bit and frame clocks)
1038 manageOutput (device, pDapD10TxParams, *((float *) arg));
1039 break;
1041 // .............................................................................
1042 // This case is called once when the device is opened/allocated by the framework.
1043 // Here, for both input and output, this allows for configuring all needed
1044 // clocks for proper operation.
1046 case PAF_SIO_CONTROL_OPEN:
1047 if (device->mode == DEV2_INPUT) {
1049 // determine the master clock based on the mode element of the
1050 // parameter configuration.
1051 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
1052 manageInput (device, pDapD10RxParams, NULL);
1054 // select appropriate master clock (but dont force)
1056 clockMuxTx (sel, -1);
1058 }
1059 else {
1061 // Since DAC is a slave to the chosen input, operate the clksel switch appropriately
1062 // Also, this is a create-time (i.e, CTRL_OPEN) only call & not appropriate under
1063 // the periodic manage_output calls.
1064 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
1065 clockMuxTx (sel, -1);
1066 platform_delay(5000); // GJ REVISIT: Without delay between Tx McASP & DAC configs, system aborts.
1067 setAudioDacConfig();
1068 dacHardUnMute ();
1070 // configure clock divider (bit and frame clocks)
1071 manageOutput (device, pDapD10TxParams, 1.0);
1072 }
1073 break;
1075 // .............................................................................
1076 // This case is called once when the device is closed/freed by the framework.
1078 case PAF_SIO_CONTROL_CLOSE:
1079 // If TX0 then signal it is no longer in use by the DACs and
1080 // configure manually to generate ADC clocks. Also hard mute
1081 // the DACs since they are not in use.
1082 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0)) {
1084 dacHardMute ();
1086 // if async then clear forced clock mux
1087 // if asynchronous then force clock change
1088 if (pDapD10TxParams->d10tx.mode & D10_SYNC_MASK)
1089 clockMuxTx (0, 0);
1090 }
1091 break;
1093 // .............................................................................
1094 // These cases are called as appropriate by the framework when there is
1095 // valid output data (UNMUTE) or no valid output (MUTE).
1097 case PAF_SIO_CONTROL_MUTE:
1098 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1099 dacSoftMute ();
1100 break;
1102 case PAF_SIO_CONTROL_UNMUTE:
1103 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1104 dacSoftUnMute ();
1105 break;
1107 // .............................................................................
1108 // This case is called when the device is idled.
1109 // There is no specific handling -- but needed to avoid error return.
1111 case PAF_SIO_CONTROL_IDLE:
1112 break;
1114 // .............................................................................
1115 // Called from the IDL Loop to allow for clock management and the like
1116 // The call is protected by a TSK_disable and HWI_disable so it is safe
1117 // to read/write shared resources.
1119 case PAF_SIO_CONTROL_WATCHDOG:
1120 // call manageInput in case the sample rate has changed resulting
1121 // in no output clocks which may have blocked the audio processing
1122 // thread. This call will reconfigure the AK4588 and restart the clocks.
1123 if (device->mode == DEV2_INPUT)
1124 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1125 break;
1127 // .............................................................................
1128 // Called from DOB_issue to allow for different values of the channel status
1129 // fields of the SPDIF output.
1131 case PAF_SIO_CONTROL_SET_DITSTATUS:
1132 // No action necessary.
1133 break;
1135 case PAF_SIO_CONTROL_SET_WORDSIZE:
1136 if(((pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) != D10_MCLK_OSC)
1137 {
1138 if ((device->mode == DEV2_INPUT) && (arg == 2))
1139 {
1140 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=2");
1141 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_16BITS;
1142 }
1143 else if ((device->mode == DEV2_INPUT) && (arg == 4))
1144 {
1145 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=4");
1146 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_NONE;
1147 }
1148 }
1149 break;
1150 // .............................................................................
1151 // Any other cases are not handled and return an error.
1153 default:
1154 return SIO2_EINVAL;
1155 }
1157 return result;
1158 } //D10_sapControl
1160 // -----------------------------------------------------------------------------
1163 unsigned int HDMIGpioGetState (void) {
1164 return(gpioReadInput(GPIO_PORT_0, PLATFORM_AUDIO_HSR_HMINTz_GPIO));
1165 }
1167 // EOF