2 /*
3 Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/
4 All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
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11 * notice, this list of conditions and the following disclaimer.
12 *
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14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
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19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 *
34 */
36 //
37 // I/O device configuration data structure definitions D10 (DA10x EVM).
40 // -----------------------------------------------------------------------------
41 // This file contains the necessary configurations and functions for
42 // using the DA10x Audio DC card in the PA environment. In particular, the
43 // SAP configurations are referenced in the pa(i/y)-evmda10x-io.c files
44 // for use in IOS (Input/Output Switching) shortcuts. Each configuration
45 // contains settings appropriate to the various devices on the DA10x-AudioDC;
46 // the DIR, DACs, ADCs, and DIT output. Also each configuration points to
47 // a common control function (D10_sapControl), which handles the various
48 // requests made by the PA framework.
50 // A note about clocking. There are two different master clocks
51 // available corresponding to the two primary input choices, DIR and ADC.
52 //
53 // DIR:
54 // . 512fs @ <= 48kHz
55 // . 256fs @ > 48kHz & <=96 kHz
56 // . 128fs @ > 96kHz
57 // ADC:
58 // . 768fs @ 32kHz
59 // . 512fs @ 48kHz
60 // . 256fs @ 96kHz
61 //
62 // This faciliates the logic used for the McASP transmit sections TX0 (DAC) and
63 // TX2 (DIT) which divide the master clock down to generate bit and frame clocks.
65 // -----------------------------------------------------------------------------
66 // Includes
68 #include <sap_d10.h>
69 #include <audio_dc_cfg.h>
70 #include "vproccmds_a.h"
72 // -----------------------------------------------------------------------------
73 // Local function declarations
75 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg);
76 static inline XDAS_Int32 initD10 (DEV2_Handle device) ;
77 static XDAS_Int32 clockMuxTx (int sel, int force);
78 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut);
79 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX);
81 void HSR4_readStatus (PAF_SIO_InputStatus *pStatus);
82 unsigned int HDMIGpioGetState (void);
83 // -----------------------------------------------------------------------------
84 // State machine variables and defines
86 // flag to facilitate one time initialization of DA10x Audio hardware
87 // 0 ==> not initialized, 1 ==> initialized
88 static char initDone = 0;
90 // input status
91 static PAF_SIO_InputStatus primaryStatus =
92 {
93 0, // lock
94 PAF_IEC_AUDIOMODE_UNKNOWN, // nonaudio
95 PAF_IEC_PREEMPHASIS_UNKNOWN, // emphasis
96 PAF_SAMPLERATE_UNKNOWN, // sampleRateMeasured
97 PAF_SAMPLERATE_UNKNOWN, // sampleRateData
98 0,0,0, // unused
99 };
102 // The McASP outputs (both for DAC and DIT) receive a high speed clock
103 // and in turn generate a bit and frame clock. The needed clock divider
104 // values are kept here for easy lookup.
105 unsigned char *pClkxDiv = NULL;
107 static const unsigned char clkxDivDIR[PAF_SAMPLERATE_N] =
108 {
109 0x2, //PAF_SAMPLERATE_UNKNOWN
110 0x8, //PAF_SAMPLERATE_NONE
111 0x8, //PAF_SAMPLERATE_32000HZ
112 0x2, //PAF_SAMPLERATE_44100HZ
113 0x2, //PAF_SAMPLERATE_48000HZ
114 0x4, //PAF_SAMPLERATE_88200HZ
115 0x2, //PAF_SAMPLERATE_96000HZ
116 0x2, //PAF_SAMPLERATE_192000HZ
117 0x4, //PAF_SAMPLERATE_64000HZ
118 0x2, //PAF_SAMPLERATE_128000HZ
119 0x2, //PAF_SAMPLERATE_176400HZ
120 0x8, //PAF_SAMPLERATE_8000HZ
121 0x8, //PAF_SAMPLERATE_11025HZ
122 0x8, //PAF_SAMPLERATE_12000HZ
123 0x8, //PAF_SAMPLERATE_16000HZ
124 0x8, //PAF_SAMPLERATE_22050HZ
125 0x8, //PAF_SAMPLERATE_24000HZ
126 };
129 static const unsigned char clkxDivADC[PAF_SAMPLERATE_N] =
130 {
131 0x8, //PAF_SAMPLERATE_UNKNOWN
132 0x8, //PAF_SAMPLERATE_NONE
133 0xC, //PAF_SAMPLERATE_32000HZ
134 0x8, //PAF_SAMPLERATE_44100HZ
135 0x8, //PAF_SAMPLERATE_48000HZ
136 0x4, //PAF_SAMPLERATE_88200HZ
137 0x4, //PAF_SAMPLERATE_96000HZ
138 0x2, //PAF_SAMPLERATE_192000HZ
139 0x4, //PAF_SAMPLERATE_64000HZ
140 0x2, //PAF_SAMPLERATE_128000HZ
141 0x2, //PAF_SAMPLERATE_176400HZ
142 0x8, //PAF_SAMPLERATE_8000HZ
143 0x8, //PAF_SAMPLERATE_11025HZ
144 0x8, //PAF_SAMPLERATE_12000HZ
145 0x8, //PAF_SAMPLERATE_16000HZ
146 0x8, //PAF_SAMPLERATE_22050HZ
147 0x8, //PAF_SAMPLERATE_24000HZ
148 };
150 static const unsigned char clkxDivHDMI[PAF_SAMPLERATE_N] =
151 {
152 0x2, //PAF_SAMPLERATE_UNKNOWN
153 0x2, //PAF_SAMPLERATE_NONE
154 0x8, //PAF_SAMPLERATE_32000HZ
155 0x2, //PAF_SAMPLERATE_44100HZ
156 0x2, //PAF_SAMPLERATE_48000HZ
157 0x4, //PAF_SAMPLERATE_88200HZ
158 0x4, //PAF_SAMPLERATE_96000HZ
159 0x2, //PAF_SAMPLERATE_192000HZ
160 0x4, //PAF_SAMPLERATE_64000HZ
161 0x2, //PAF_SAMPLERATE_128000HZ
162 0x2, //PAF_SAMPLERATE_176400HZ
163 0x8, //PAF_SAMPLERATE_8000HZ
164 0x8, //PAF_SAMPLERATE_11025HZ
165 0x8, //PAF_SAMPLERATE_12000HZ
166 0x8, //PAF_SAMPLERATE_16000HZ
167 0x8, //PAF_SAMPLERATE_22050HZ
168 0x8, //PAF_SAMPLERATE_24000HZ
169 };
171 // The ADCs, when operating as the master input, can only
172 // generate a limited set of audio sample rates since the clock
173 // is derived from AUXCLK which is the oscillator connected to the DSP.
174 // This table faciliates the access and definition of these rates.
175 static const Uint16 oscRateTable[8] =
176 {
177 PAF_SAMPLERATE_UNKNOWN, // 0
178 PAF_SAMPLERATE_32000HZ,
179 PAF_SAMPLERATE_44100HZ, // D10_RATE_44_1KHZ
180 PAF_SAMPLERATE_48000HZ,
181 PAF_SAMPLERATE_88200HZ, // D10_RATE_88_2KHZ
182 PAF_SAMPLERATE_96000HZ,
183 PAF_SAMPLERATE_176400HZ, // D10_RATE_176_4KHZ
184 PAF_SAMPLERATE_192000HZ
185 };
187 static const Uint16 RateTable_hdmi[8] =
188 {
189 PAF_SAMPLERATE_UNKNOWN, // HSDIO_AudioFreq_RESERVED
190 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
191 PAF_SAMPLERATE_44100HZ, // HSDIO_AudioFreq_44_1K
192 PAF_SAMPLERATE_48000HZ, // HSDIO_AudioFreq_48K
193 PAF_SAMPLERATE_88200HZ, // HSDIO_AudioFreq_88_2K
194 PAF_SAMPLERATE_96000HZ, // HSDIO_AudioFreq_96_4K
195 PAF_SAMPLERATE_176400HZ, // HSDIO_AudioFreq_176_4K
196 PAF_SAMPLERATE_192000HZ // HSDIO_AudioFreq_192K
197 };
199 static const Uint16 RateTable_spdif[4] =
200 {
201 PAF_SAMPLERATE_44100HZ, // AudioFreq_44_1K
202 PAF_SAMPLERATE_48000HZ, // AudioFreq_48K
203 PAF_SAMPLERATE_UNKNOWN, // AudioFreq_RESERVED
204 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
205 };
208 // base mcasp addresses for easy lookup
209 static volatile Uint32 * mcaspAddr[_MCASP_PORT_CNT] =
210 {
211 (volatile Uint32 *) _MCASP_BASE_PORT0,
212 (volatile Uint32 *) _MCASP_BASE_PORT1,
213 (volatile Uint32 *) _MCASP_BASE_PORT2
214 };
216 // The DA10x HW is configured for the DAC's mute lines to be operated based
217 // on McASP0's AMUTE (out) line. This is the hard mute.
218 static inline void dacHardMute (void) {
219 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
220 mcasp0[_MCASP_PDOUT_OFFSET] |= _MCASP_PDOUT_AMUTE_MASK;
221 }
222 static inline void dacHardUnMute (void) {
223 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
224 mcasp0[_MCASP_PDOUT_OFFSET] &= ~_MCASP_PDOUT_AMUTE_MASK;
225 mcasp0[_MCASP_AMUTE_OFFSET] |= MCASP_AMUTE_MUTEN_ERRLOW;
226 }
228 // How should the PCM18x DAC's soft mute functionality be used here?
229 // i.e, as different from the hard mute? need to review.
230 static inline void dacSoftMute (void) {
231 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
232 mcasp0[6] = 0x000 ;
233 mcasp0[6] = 0x400 ;
234 }
235 static inline void dacSoftUnMute (void) {
236 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
237 mcasp0[6] = 0x000 ;
238 mcasp0[6] = 0x400 ;
239 }
241 // -----------------------------------------------------------------------------
242 // McASP Input Configuration Definitions
244 static const MCASP_ConfigRcv rxConfigDIR =
245 {
246 MCASP_RMASK_OF(0xFFFFFFFF),
247 MCASP_RFMT_RMK(
248 MCASP_RFMT_RDATDLY_1BIT,
249 MCASP_RFMT_RRVRS_MSBFIRST,
250 MCASP_RFMT_RPAD_RPBIT,
251 MCASP_RFMT_RPBIT_OF(0),
252 MCASP_RFMT_RSSZ_32BITS,
253 MCASP_RFMT_RBUSEL_DAT,
254 MCASP_RFMT_RROT_NONE),
255 MCASP_AFSRCTL_RMK(
256 MCASP_AFSRCTL_RMOD_OF(2),
257 MCASP_AFSRCTL_FRWID_WORD,
258 MCASP_AFSRCTL_FSRM_EXTERNAL,
259 MCASP_AFSRCTL_FSRP_ACTIVELOW),
260 MCASP_ACLKRCTL_RMK(
261 MCASP_ACLKRCTL_CLKRP_RISING,
262 MCASP_ACLKRCTL_CLKRM_EXTERNAL,
263 MCASP_ACLKRCTL_CLKRDIV_DEFAULT),
264 MCASP_AHCLKRCTL_RMK(
265 MCASP_AHCLKRCTL_HCLKRM_EXTERNAL,
266 MCASP_AHCLKRCTL_HCLKRP_RISING,
267 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
268 MCASP_RTDM_OF(3),
269 MCASP_RINTCTL_DEFAULT,
270 MCASP_RCLKCHK_DEFAULT
271 };
273 static const MCASP_ConfigRcv rxConfigADC =
274 {
275 MCASP_RMASK_OF(0xFFFFFFFF),
276 MCASP_RFMT_RMK(
277 MCASP_RFMT_RDATDLY_1BIT,
278 MCASP_RFMT_RRVRS_MSBFIRST,
279 MCASP_RFMT_RPAD_RPBIT,
280 MCASP_RFMT_RPBIT_OF(0),
281 MCASP_RFMT_RSSZ_32BITS,
282 MCASP_RFMT_RBUSEL_DAT,
283 MCASP_RFMT_RROT_NONE),
284 MCASP_AFSRCTL_RMK(
285 MCASP_AFSRCTL_RMOD_OF(2),
286 MCASP_AFSRCTL_FRWID_WORD,
287 MCASP_AFSRCTL_FSRM_INTERNAL,
288 MCASP_AFSRCTL_FSRP_ACTIVEHIGH),
289 MCASP_ACLKRCTL_RMK(
290 MCASP_ACLKRCTL_CLKRP_RISING,
291 MCASP_ACLKRCTL_CLKRM_INTERNAL,
292 MCASP_ACLKXCTL_CLKXDIV_OF(7)),
293 MCASP_AHCLKRCTL_RMK(
294 MCASP_AHCLKRCTL_HCLKRM_INTERNAL,
295 MCASP_AHCLKRCTL_HCLKRP_RISING,
296 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
297 MCASP_RTDM_OF(3),
298 MCASP_RINTCTL_DEFAULT,
299 MCASP_RCLKCHK_DEFAULT
300 };
302 // -----------------------------------------------------------------------------
303 // McASP Output Configuration Definitions
305 static const MCASP_ConfigXmt txConfigDAC =
306 {
307 MCASP_XMASK_OF(0xFFFFFFFF),
308 MCASP_XFMT_RMK(
309 MCASP_XFMT_XDATDLY_1BIT,
310 MCASP_XFMT_XRVRS_MSBFIRST,
311 MCASP_XFMT_XPAD_ZERO,
312 MCASP_XFMT_XPBIT_DEFAULT,
313 MCASP_XFMT_XSSZ_32BITS,
314 MCASP_XFMT_XBUSEL_DAT,
315 MCASP_XFMT_XROT_NONE),
316 MCASP_AFSXCTL_RMK(
317 MCASP_AFSXCTL_XMOD_OF(2),
318 MCASP_AFSXCTL_FXWID_WORD,
319 MCASP_AFSXCTL_FSXM_INTERNAL,
320 MCASP_AFSXCTL_FSXP_ACTIVELOW),
321 MCASP_ACLKXCTL_RMK(
322 MCASP_ACLKXCTL_CLKXP_FALLING,
323 MCASP_ACLKXCTL_ASYNC_ASYNC,
324 MCASP_ACLKXCTL_CLKXM_INTERNAL,
325 MCASP_ACLKXCTL_CLKXDIV_DEFAULT),
326 MCASP_AHCLKXCTL_RMK(
327 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
328 MCASP_AHCLKXCTL_HCLKXP_FALLING,
329 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
330 MCASP_XTDM_OF(3),
331 MCASP_XINTCTL_DEFAULT,
332 MCASP_XCLKCHK_DEFAULT
333 };
335 static const MCASP_ConfigXmt txConfigDACSlave =
336 {
337 MCASP_XMASK_OF(0xFFFFFFFF),
338 MCASP_XFMT_RMK(
339 MCASP_XFMT_XDATDLY_1BIT,
340 MCASP_XFMT_XRVRS_MSBFIRST,
341 MCASP_XFMT_XPAD_ZERO,
342 MCASP_XFMT_XPBIT_DEFAULT,
343 MCASP_XFMT_XSSZ_32BITS,
344 MCASP_XFMT_XBUSEL_DAT,
345 MCASP_XFMT_XROT_NONE),
346 MCASP_AFSXCTL_RMK(
347 MCASP_AFSXCTL_XMOD_OF(2),
348 MCASP_AFSXCTL_FXWID_WORD,
349 MCASP_AFSXCTL_FSXM_INTERNAL,
350 MCASP_AFSXCTL_FSXP_ACTIVELOW),
351 MCASP_ACLKXCTL_RMK(
352 MCASP_ACLKXCTL_CLKXP_FALLING,
353 MCASP_ACLKXCTL_ASYNC_ASYNC,
354 MCASP_ACLKXCTL_CLKXM_INTERNAL,
355 MCASP_ACLKXCTL_CLKXDIV_OF(1)),
356 MCASP_AHCLKXCTL_RMK(
357 MCASP_AHCLKXCTL_HCLKXM_INTERNAL,
358 MCASP_AHCLKXCTL_HCLKXP_FALLING,
359 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
360 MCASP_XTDM_OF(3),
361 MCASP_XINTCTL_DEFAULT,
362 MCASP_XCLKCHK_DEFAULT
363 };
365 static const MCASP_ConfigXmt txConfigDIT =
366 {
367 MCASP_XMASK_OF(0x00FFFFFF),
368 MCASP_XFMT_RMK(
369 MCASP_XFMT_XDATDLY_1BIT,
370 MCASP_XFMT_XRVRS_LSBFIRST,
371 MCASP_XFMT_XPAD_DEFAULT,
372 MCASP_XFMT_XPBIT_DEFAULT,
373 MCASP_XFMT_XSSZ_32BITS,
374 MCASP_XFMT_XBUSEL_DAT,
375 MCASP_XFMT_XROT_NONE),
376 MCASP_AFSXCTL_RMK(
377 MCASP_AFSXCTL_XMOD_OF(0x180),
378 MCASP_AFSXCTL_FXWID_BIT,
379 MCASP_AFSXCTL_FSXM_INTERNAL,
380 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
381 MCASP_ACLKXCTL_RMK(
382 MCASP_ACLKXCTL_CLKXP_FALLING,
383 MCASP_ACLKXCTL_ASYNC_ASYNC,
384 MCASP_ACLKXCTL_CLKXM_INTERNAL,
385 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
386 MCASP_AHCLKXCTL_RMK(
387 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
388 MCASP_AHCLKXCTL_HCLKXP_FALLING,
389 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
390 MCASP_XTDM_OF(0xFFFFFFFF),
391 MCASP_XINTCTL_DEFAULT,
392 MCASP_XCLKCHK_DEFAULT
393 };
395 #if 0
396 static const MCASP_ConfigXmt txConfigDIT_16bit =
397 {
398 MCASP_XMASK_OF(0x0000FFFF),
399 MCASP_XFMT_RMK(
400 MCASP_XFMT_XDATDLY_1BIT,
401 MCASP_XFMT_XRVRS_LSBFIRST,
402 MCASP_XFMT_XPAD_DEFAULT,
403 MCASP_XFMT_XPBIT_DEFAULT,
404 MCASP_XFMT_XSSZ_32BITS,
405 MCASP_XFMT_XBUSEL_DAT,
406 MCASP_XFMT_XROT_24BITS),
407 MCASP_AFSXCTL_RMK(
408 MCASP_AFSXCTL_XMOD_OF(0x180),
409 MCASP_AFSXCTL_FXWID_BIT,
410 MCASP_AFSXCTL_FSXM_INTERNAL,
411 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
412 MCASP_ACLKXCTL_RMK(
413 MCASP_ACLKXCTL_CLKXP_FALLING,
414 MCASP_ACLKXCTL_ASYNC_ASYNC,
415 MCASP_ACLKXCTL_CLKXM_INTERNAL,
416 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
417 MCASP_AHCLKXCTL_RMK(
418 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
419 MCASP_AHCLKXCTL_HCLKXP_FALLING,
420 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
421 MCASP_XTDM_OF(0xFFFFFFFF),
422 MCASP_XINTCTL_DEFAULT,
423 MCASP_XCLKCHK_DEFAULT
424 };
425 #endif
427 // -----------------------------------------------------------------------------
428 // DAP Input Parameter Definitions
430 const SAP_D10_Rx_Params SAP_D10_RX_DIR =
431 {
432 sizeof (SAP_D10_Rx_Params), // size
433 "SAP", // name
434 MCASP_DEV2, // moduleNum --> mcasp #
435 (Void *)&rxConfigDIR, // pConfig
436 4, // wordSize (unused)
437 24, // precision (unused)
438 D10_sapControl, // control
439 0x00000020, // pinMask
440 (D10_MCLK_DIR << D10_MCLK_SHIFT), // mode
441 0,0 // unused[2]
442 };
444 const SAP_D10_Rx_Params SAP_D10_RX_ADC_44100HZ =
445 {
446 sizeof (SAP_D10_Rx_Params), // size
447 "SAP", // name
448 MCASP_DEV1, // moduleNum --> mcasp #
449 (Void *)&rxConfigADC, // pConfig
450 4, // wordSize (unused)
451 24, // precision (unused)
452 D10_sapControl, // control
453 0xE000000F, // pinMask
454 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
455 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
456 0,0 // unused[2]
457 };
459 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_44100HZ =
460 {
461 sizeof (SAP_D10_Rx_Params), // size
462 "SAP", // name
463 MCASP_DEV1, // moduleNum --> mcasp #
464 (Void *)&rxConfigADC, // pConfig
465 -1, // wordSize (unused)
466 -1, // precision (unused)
467 D10_sapControl, // control
468 0xE0000007, // pinMask
469 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
470 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
471 0,0 // unused[2]
472 };
474 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_44100HZ =
475 {
476 sizeof (SAP_D10_Rx_Params), // size
477 "SAP", // name
478 MCASP_DEV1, // moduleNum --> mcasp #
479 (Void *)&rxConfigADC, // pConfig
480 -1, // wordSize (unused)
481 -1, // precision (unused)
482 D10_sapControl, // control
483 0xE0000001, // pinMask
484 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
485 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
486 0,0 // unused[2]
487 };
489 const SAP_D10_Rx_Params SAP_D10_RX_ADC_88200HZ =
490 {
491 sizeof (SAP_D10_Rx_Params), // size
492 "SAP", // name
493 MCASP_DEV1, // moduleNum --> mcasp #
494 (Void *)&rxConfigADC, // pConfig
495 -1, // wordSize (unused)
496 -1, // precision (unused)
497 D10_sapControl, // control
498 0xE000000F, // pinMask
499 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
500 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
501 0,0 // unused[2]
502 };
504 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_88200HZ =
505 {
506 sizeof (SAP_D10_Rx_Params), // size
507 "SAP", // name
508 MCASP_DEV1, // moduleNum --> mcasp #
509 (Void *)&rxConfigADC, // pConfig
510 -1, // wordSize (unused)
511 -1, // precision (unused)
512 D10_sapControl, // control
513 0xE0000007, // pinMask
514 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
515 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
516 0,0 // unused[2]
517 };
519 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_88200HZ =
520 {
521 sizeof (SAP_D10_Rx_Params), // size
522 "SAP", // name
523 MCASP_DEV1, // moduleNum --> mcasp #
524 (Void *)&rxConfigADC, // pConfig
525 -1, // wordSize (unused)
526 -1, // precision (unused)
527 D10_sapControl, // control
528 0xE0000001, // pinMask
529 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
530 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
531 0,0 // unused[2]
532 };
535 const SAP_D10_Rx_Params SAP_D10_RX_HDMI_STEREO =
536 {
537 sizeof (SAP_D10_Rx_Params), // size
538 "SAP", // name
539 MCASP_DEV0, // moduleNum --> mcasp #
540 (Void *)&rxConfigDIR, // pConfig
541 4, // wordSize (unused)
542 -1, // precision (unused)
543 D10_sapControl, // control
544 0x00001000, // pinMask
545 (D10_MODE_HDMI << D10_MODE_SHIFT) |
546 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
547 0,0 // unused[2]
548 };
550 const SAP_D10_Rx_Params SAP_D10_RX_HDMI =
551 {
552 sizeof (SAP_D10_Rx_Params), // size
553 "SAP", // name
554 MCASP_DEV0, // moduleNum --> mcasp #
555 (Void *)&rxConfigDIR, // pConfig
556 4, // wordSize (unused)
557 -1, // precision (unused)
558 D10_sapControl, // control
559 0xE000F000, // pinMask
560 (D10_MODE_HDMI << D10_MODE_SHIFT) |
561 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
562 0,0 // unused[2]
563 };
565 // -----------------------------------------------------------------------------
566 // SAP Output Parameter Definitions
568 const SAP_D10_Tx_Params SAP_D10_TX_DAC =
569 {
570 sizeof (SAP_D10_Tx_Params), // size
571 "SAP", // name
572 MCASP_DEV0, // moduleNum --> mcasp #
573 (Void *)&txConfigDAC, // pConfig
574 4, // wordSize (in bytes)
575 24, // precision (in bits)
576 D10_sapControl, // control
577 0x1600000F, // pinMask
578 0, // mode
579 0,0,0 // unused[3]
580 };
582 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC =
583 {
584 sizeof (SAP_D10_Tx_Params), // size
585 "SAP", // name
586 MCASP_DEV0, // moduleNum --> mcasp #
587 (Void *)&txConfigDAC, // pConfig
588 4, // wordSize (in bytes)
589 24, // precision (in bits)
590 D10_sapControl, // control
591 0x16000001, // pinMask
592 0, // mode
593 0,0,0 // unused[3]
594 };
596 const SAP_D10_Tx_Params SAP_D10_TX_DIT =
597 {
598 sizeof (SAP_D10_Tx_Params), // size
599 "SAP", // name
600 MCASP_DEV2, // moduleNum --> mcasp #
601 (Void *) &txConfigDIT, // pConfig
602 3, // wordSize (in bytes)
603 24, // precision (in bits)
604 D10_sapControl, // control
605 0x1C000001, // pinMask
606 0, // mode
607 0,0,0 // unused[3]
608 };
610 const SAP_D10_Tx_Params SAP_D10_TX_DAC_SLAVE =
611 {
612 sizeof (SAP_D10_Tx_Params), // size
613 "SAP", // name
614 MCASP_DEV0, // moduleNum --> mcasp #
615 (Void *)&txConfigDACSlave, // pConfig
616 4, // wordSize (in bytes)
617 24, // precision (in bits)
618 D10_sapControl, // control
619 0x1E00000F, // pinMask
620 0, // mode
621 0,0,0 // unused[3]
622 };
624 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC_SLAVE =
625 {
626 sizeof (SAP_D10_Tx_Params), // size
627 "SAP", // name
628 MCASP_DEV0, // moduleNum --> mcasp #
629 (Void *)&txConfigDAC, // pConfig
630 4, // wordSize (in bytes)
631 24, // precision (in bits)
632 D10_sapControl, // control
633 0x16000001, // pinMask
634 0, // mode
635 0,0,0 // unused[3]
636 };
638 const SAP_D10_Tx_Params SAP_D10_TX_DAC_12CH =
639 {
640 sizeof (SAP_D10_Tx_Params), // size
641 "SAP", // name
642 MCASP_DEV0, // moduleNum --> mcasp #
643 (Void *)&txConfigDAC, // pConfig
644 4, // wordSize (in bytes)
645 24, // precision (in bits)
646 D10_sapControl, // control
647 0x1600003F, // pinMask
648 0, // mode
649 0,0,0 // unused[3]
650 };
652 const SAP_D10_Tx_Params SAP_D10_TX_DAC_16CH =
653 {
654 sizeof (SAP_D10_Tx_Params), // size
655 "SAP", // name
656 MCASP_DEV0, // moduleNum --> mcasp #
657 (Void *)&txConfigDAC, // pConfig
658 4, // wordSize (in bytes)
659 24, // precision (in bits)
660 D10_sapControl, // control
661 0x160000FF, // pinMask
662 0, // mode
663 0,0,0 // unused[3]
664 };
667 // -----------------------------------------------------------------------------
668 // One time initialization of the DA10x audio hardware.
670 /* DAC default configuration parameters */
671 DacConfig dacCfg =
672 {
673 DAC_AMUTE_CTRL_SCKI_LOST, /* Amute event */
674 0, /* Amute control */
675 DAC_SAMPLING_MODE_SINGLE_RATE, /* Sampling mode */
676 DAC_DATA_FORMAT_I2S, /* Data format */
677 0, /* Soft mute control */
678 DAC_ATTENUATION_WIDE_RANGE, /* Attenuation mode */
679 DAC_DEEMP_44KHZ, /* De-emph control */
680 100 /* Volume */
681 };
682 /* ADC default configuration parameters */
683 AdcConfig adcCfg =
684 {
685 90, /* ADC gain */
686 ADC_INL_SE_VINL1, /* Left input mux for ADC1L */
687 ADC_INL_SE_VINL2, /* Left input mux for ADC2L */
688 ADC_INR_SE_VINR1, /* Right input mux for ADC1R */
689 ADC_INR_SE_VINR2, /* Right input mux for ADC2R */
690 ADC_RX_WLEN_24BIT, /* ADC word length */
691 ADC_DATA_FORMAT_I2S, /* ADC data format */
692 0
693 };
695 Platform_STATUS setAudioDacConfig(void)
696 {
697 Platform_STATUS status;
699 /* Initialize Audio DAC module */
700 status = audioDacConfig(DAC_DEVICE_ALL, &dacCfg);
701 if (status)
702 Log_info0("SAP_D10: Audio DAC Configuration Failed!!!\n");
703 return status;
705 }
707 static inline XDAS_Int32 initD10 (DEV2_Handle device)
708 {
709 Platform_STATUS status = Platform_EOK;
711 /* Initialize common audio configurations */
712 status = platformAudioInit();
713 if(status != Platform_EOK)
714 {
715 System_printf("Audio Init Failed!\n");
716 return status;
717 }
719 /* Initialize Audio ADC module */
720 status = audioAdcConfig(ADC_DEVICE_ALL, &adcCfg);
721 if(status != Platform_EOK)
722 {
723 platform_write("Audio ADC Configuration Failed!\n");
724 return status;
725 }
727 /* Setup DIR 9001 for SPDIF input operation */
728 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
729 status = audioDirConfig();
730 if(status != Platform_EOK)
731 {
732 Log_info0("Audio DIR Init Failed!\n");
733 return status;
734 }
736 #if 1
737 /* Setup HSR41 for HDMI input operation */
738 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
739 /* Initialize the HDMI Card */
740 while(HDMIGpioGetState());
741 status = audioHDMIConfig();
742 if(status != Platform_EOK)
743 {
744 Log_info0("Audio HDMI Init Failed!\n");
745 return status;
746 }
747 #endif
749 // This is needed because DAC configuration needs some default clocking.
750 // We start with S/PDIF, because it's onboard the Audio DC & has its own crystal.
751 // HDMI is an add-on board & Audio OSC would need AUX clocking - both unfit for "default".
752 // ADCs default clock is not available to clock the DAC with.
753 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
755 platform_delay(5000); // Without delay between these 2 calls system aborts.
757 status = setAudioDacConfig();
759 return status;
761 } //initD10
763 // -----------------------------------------------------------------------------
764 // The McASP TX section is *only* used as a master clock mux.
765 // Mux functionality is achieved by selecting either external high
766 // speed clocks (DIR/HDMI) or the internal AUXCLK (Audio_OSC). This is divided down
767 // output via ACLKX0 which is connected to the high speed input
768 // of TX0 (DAC) and TX2 (DIT).
770 static XDAS_Int32 clockMuxTx (int sel, int force)
771 {
772 Platform_STATUS status = 0;
773 // select clkxDiv table
774 if (sel == D10_MCLK_DIR)
775 {
776 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
777 pClkxDiv = (unsigned char *) clkxDivDIR;
778 }
779 else if (sel == D10_MCLK_HDMI)
780 {
781 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
782 pClkxDiv = (unsigned char *) clkxDivHDMI;
783 }
784 else if (sel == D10_MCLK_OSC)
785 {
786 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_OSC);
787 pClkxDiv = (unsigned char *) clkxDivADC;
788 }
790 platform_delay(20000);
792 return status;
793 } //clockMuxTx
796 // -----------------------------------------------------------------------------
797 // This function returns the input status of the specified device.
798 // This is called once when the device is opened
799 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter
800 // (PAF_SIO_CONTROL_GET_INPUT_STATUS).
801 int gHmint_ctr = 0, gNonAudio = 0, gLockStatus=0, gPrevAudio=0, gPrevLock=0;
802 int gSync_ctr, gLock_ctr, gAudioErr_ctr, gNonAudio_ctr = 0;
804 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut)
805 {
806 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
807 //volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
808 //volatile Uint32 *mcasp1 = (volatile Uint32 *) _MCASP_BASE_PORT1;
809 //volatile Uint32 *mcasp2 = (volatile Uint32 *) _MCASP_BASE_PORT2;
811 //Platform_STATUS status;
813 static int PrevSampRate = 0;
814 int RateHdmi =0;
816 /* Mode & MCLK info embedded statically in the Rx IO definition for SPDIF Input */
817 if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_DIR) &
818 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD))
819 {
820 pStatusIn->lock = !(platformAudioDirGetClkStatus());
821 pStatusIn->nonaudio = !(platformAudioDirGetAudioStatus());
822 pStatusIn->emphasis = platformAudioDirGetEmphStatus();
823 pStatusIn->sampleRateMeasured = RateTable_spdif[platformAudioDirGetFsOut()];
824 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
825 PrevSampRate = pStatusIn->sampleRateMeasured;
827 // GJ: Is this needed? Probably not.
828 // GJ: Mute Control during input-change seemingly intended.
829 //mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
830 //mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
832 }
833 /* Mode & MCLK info embedded statically in the Rx IO definition for ANALOG/ADC Input */
834 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_OSC) &
835 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD)) {
836 int adcRate = (pParams->d10rx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
838 pStatusIn->lock = 1;
839 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
840 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
841 pStatusIn->sampleRateMeasured = oscRateTable[adcRate];
842 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
844 }
845 /* Mode & MCLK info embedded statically in the Rx IO definition for HDMI */
846 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_HDMI) &
847 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_HDMI))
848 {
850 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
851 //pStatusIn->lock = 1;
852 //pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
854 if(!HDMIGpioGetState())
855 {
856 clear_hdmi_hmint();
857 gHmint_ctr++;
859 RateHdmi=read_hdmi_samprate();
860 pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
861 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
862 PrevSampRate = pStatusIn->sampleRateMeasured;
864 switch(read_hdmi_errstatus())
865 {
866 case HSDIO_AudioErr_NO_ERROR:
867 {
868 gPrevLock=pStatusIn->lock;
869 gPrevAudio=pStatusIn->nonaudio;
870 pStatusIn->lock = 1;
871 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
872 break;
873 }
874 case HSDIO_AudioErr_AUDIO_NO_PLL_LOCK:
875 {
876 gLock_ctr++;
877 pStatusIn->lock = 0;
878 //pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
879 break;
880 }
881 case HSDIO_AudioErr_AUDIO_NO_AUDIO:
882 {
883 gAudioErr_ctr++;
884 //pStatusIn->lock = 1;
885 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_NONAUDIO;
886 break;
887 }
888 default:
889 while(1); // Control shouldn't be here.
890 }
892 if(HSDIO_AudioMClk_128X != read_hdmi_clockstatus())
893 {
894 gLock_ctr++;
895 pStatusIn->lock = 0;
896 }
897 else if (HSDIO_AudioPresent_HAS_AUDIO != read_hdmi_audiostatus())
898 {
899 gNonAudio_ctr++;
900 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_NONAUDIO;
901 }
904 }
905 else
906 {
907 pStatusIn->sampleRateMeasured = PrevSampRate;
908 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
909 }
910 }
912 else
913 return -1; // Control shouldn't be here!
915 gNonAudio=pStatusIn->nonaudio;
916 gLockStatus=pStatusIn->lock;
918 // update another status if requested
919 if (pStatusOut)
920 *pStatusOut = *pStatusIn;
922 return 0;
923 } //manageInput
926 // -----------------------------------------------------------------------------
927 // This function configures the McASP TX clock dividers based on the
928 // master clock rate. This is called once when the device is opened
929 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter (PAF_SIO_CONTROL_SET_RATEX).
931 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX)
932 {
933 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
934 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
935 Uint32 divider;
938 if (!pClkxDiv)
939 return SIO2_EINVAL;
941 // set clock divider
942 if (rateX < .354)
943 rateX = 0.25;
944 else if (rateX < .707)
945 rateX = 0.50;
946 else if (rateX < 1.6)
947 rateX = 1.00;
948 else if (rateX < 2.828)
949 rateX = 2.00;
950 else
951 rateX = 4.00;
952 // if asynchronous then force clock change (assumes osc master)
953 if (pParams->d10tx.mode & D10_SYNC_MASK) {
954 int dacRate = (pParams->d10tx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
955 divider = pClkxDiv[oscRateTable[dacRate]];
956 }
957 else
958 divider = pClkxDiv[pStatusIn->sampleRateMeasured];
959 divider /= rateX;
961 Log_info2("SAP_D10: Inside manageOutput with divider = %d, rateX = %f", divider, rateX);
963 // DIT requires 2x clock
964 if ((mcasp[_MCASP_AFSXCTL_OFFSET] & _MCASP_AFSXCTL_XMOD_MASK) ==
965 (MCASP_AFSXCTL_XMOD_OF(0x180) << _MCASP_AFSXCTL_XMOD_SHIFT)) {
966 if (divider < 2)
967 return (SIO2_EINVAL);
968 divider >>= 1;
969 }
971 mcasp[_MCASP_ACLKXCTL_OFFSET] =
972 (mcasp[_MCASP_ACLKXCTL_OFFSET] & ~_MCASP_ACLKXCTL_CLKXDIV_MASK) |
973 (MCASP_ACLKXCTL_CLKXDIV_OF(divider-1) << _MCASP_ACLKXCTL_CLKXDIV_SHIFT);
974 return 0;
975 } //manageOutput
977 // -----------------------------------------------------------------------------
978 // This function is called by the peripheral driver (DAP) in response to
979 // various SIO_ctrl() calls made by the framework.
981 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg)
982 {
983 const SAP_D10_Rx_Params *pDapD10RxParams = (const SAP_D10_Rx_Params *)pParams;
984 const SAP_D10_Tx_Params *pDapD10TxParams = (const SAP_D10_Tx_Params *)pParams;
985 //Platform_STATUS status;
987 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
988 XDAS_Int32 result = 0;
990 // perform one time hardware initialization
991 if (!initDone) {
992 result = initD10 (device);
993 if (result)
994 return result;
995 initDone = 1;
996 }
998 switch (code) {
1000 // .............................................................................
1001 // This case provides a regular entry point for managing the specified
1002 // input device. Nominally, this is used to provide lock and sample rate
1003 // status to the framework.
1005 case PAF_SIO_CONTROL_GET_INPUT_STATUS:
1006 if (device->mode != DEV2_INPUT)
1007 return SIO2_EINVAL;
1009 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1010 break;
1012 // .............................................................................
1013 // This case provides a regular entry point for managing the specified
1014 // output device. Nominally this is used to change the output clock dividers
1015 // in the case of double rate output (e.g. DTS 96/24).
1017 case PAF_SIO_CONTROL_SET_RATEX:
1018 // Support only output rate control, for now
1019 if (device->mode != DEV2_OUTPUT)
1020 return (SIO2_EINVAL);
1022 // configure clock divider (bit and frame clocks)
1023 manageOutput (device, pDapD10TxParams, *((float *) arg));
1024 break;
1026 // .............................................................................
1027 // This case is called once when the device is opened/allocated by the framework.
1028 // Here, for both input and output, this allows for configuring all needed
1029 // clocks for proper operation.
1031 case PAF_SIO_CONTROL_OPEN:
1032 if (device->mode == DEV2_INPUT) {
1034 // determine the master clock based on the mode element of the
1035 // parameter configuration.
1036 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
1037 manageInput (device, pDapD10RxParams, NULL);
1039 // select appropriate master clock (but dont force)
1041 clockMuxTx (sel, -1);
1043 }
1044 else {
1046 // Since DAC is a slave to the chosen input, operate the clksel switch appropriately
1047 // Also, this is a create-time (i.e, CTRL_OPEN) only call & not appropriate under
1048 // the periodic manage_output calls.
1049 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
1050 clockMuxTx (sel, -1);
1051 platform_delay(5000); // GJ REVISIT: Without delay between Tx McASP & DAC configs, system aborts.
1052 setAudioDacConfig();
1053 dacHardUnMute ();
1055 // configure clock divider (bit and frame clocks)
1056 manageOutput (device, pDapD10TxParams, 1.0);
1057 }
1058 break;
1060 // .............................................................................
1061 // This case is called once when the device is closed/freed by the framework.
1063 case PAF_SIO_CONTROL_CLOSE:
1064 // If TX0 then signal it is no longer in use by the DACs and
1065 // configure manually to generate ADC clocks. Also hard mute
1066 // the DACs since they are not in use.
1067 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0)) {
1069 dacHardMute ();
1071 // if async then clear forced clock mux
1072 // if asynchronous then force clock change
1073 if (pDapD10TxParams->d10tx.mode & D10_SYNC_MASK)
1074 clockMuxTx (0, 0);
1075 }
1076 break;
1078 // .............................................................................
1079 // These cases are called as appropriate by the framework when there is
1080 // valid output data (UNMUTE) or no valid output (MUTE).
1082 case PAF_SIO_CONTROL_MUTE:
1083 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1084 dacSoftMute ();
1085 break;
1087 case PAF_SIO_CONTROL_UNMUTE:
1088 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1089 dacSoftUnMute ();
1090 break;
1092 // .............................................................................
1093 // This case is called when the device is idled.
1094 // There is no specific handling -- but needed to avoid error return.
1096 case PAF_SIO_CONTROL_IDLE:
1097 break;
1099 // .............................................................................
1100 // Called from the IDL Loop to allow for clock management and the like
1101 // The call is protected by a TSK_disable and HWI_disable so it is safe
1102 // to read/write shared resources.
1104 case PAF_SIO_CONTROL_WATCHDOG:
1105 // call manageInput in case the sample rate has changed resulting
1106 // in no output clocks which may have blocked the audio processing
1107 // thread. This call will reconfigure the AK4588 and restart the clocks.
1108 if (device->mode == DEV2_INPUT)
1109 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1110 break;
1112 // .............................................................................
1113 // Called from DOB_issue to allow for different values of the channel status
1114 // fields of the SPDIF output.
1116 case PAF_SIO_CONTROL_SET_DITSTATUS:
1117 // No action necessary.
1118 break;
1120 case PAF_SIO_CONTROL_SET_WORDSIZE:
1121 if(((pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) != D10_MCLK_OSC)
1122 {
1123 if ((device->mode == DEV2_INPUT) && (arg == 2))
1124 {
1125 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=2");
1126 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_16BITS;
1127 }
1128 else if ((device->mode == DEV2_INPUT) && (arg == 4))
1129 {
1130 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=4");
1131 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_NONE;
1132 }
1133 }
1134 break;
1135 // .............................................................................
1136 // Any other cases are not handled and return an error.
1138 default:
1139 return SIO2_EINVAL;
1140 }
1142 return result;
1143 } //D10_sapControl
1145 // -----------------------------------------------------------------------------
1148 unsigned int HDMIGpioGetState (void) {
1149 return(gpioReadInput(GPIO_PORT_0, PLATFORM_AUDIO_HSR_HMINTz_GPIO));
1150 }
1152 // EOF