pdk_k2g_1_0_1/packages/ti/board/src/evmAM572x/evmAM572x_clock.c

   1 /******************************************************************************
   2  * Copyright (c) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  *  Redistribution and use in source and binary forms, with or without
   5  *  modification, are permitted provided that the following conditions
   6  *  are met:
   7  *
   8  *    Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  *
  11  *    Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the
  14  *    distribution.
  15  *
  16  *    Neither the name of Texas Instruments Incorporated nor the names of
  17  *    its contributors may be used to endorse or promote products derived
  18  *    from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  *****************************************************************************/
  33
  34 #include "board_internal.h"
  35
  36 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
  37 Board_STATUS Board_moduleClockInit()
  38 {
  39     CSL_cam_cm_coreRegs *camCmReg =
  40         (CSL_cam_cm_coreRegs *) CSL_MPU_CAM_CM_CORE_REGS;
  41     CSL_l4per_cm_core_componentRegs *l4PerCmReg =
  42         (CSL_l4per_cm_core_componentRegs *) CSL_MPU_L4PER_CM_CORE_REGS;
  43     CSL_l3init_cm_coreRegs *l3InitCmReg =
  44         (CSL_l3init_cm_coreRegs *) CSL_MPU_L3INIT_CM_CORE_REGS;
  45     CSL_core_cm_coreRegs *coreCmReg =
  46         (CSL_core_cm_coreRegs *) CSL_MPU_CORE_CM_CORE_REGS;
  47     CSL_coreaon_cm_coreRegs *coreAonCmReg =
  48         (CSL_coreaon_cm_coreRegs *) CSL_MPU_COREAON_CM_CORE_REGS;
  49     CSL_dss_cm_coreRegs *dssCmReg =
  50         (CSL_dss_cm_coreRegs *) CSL_MPU_DSS_CM_CORE_REGS;
  51     CSL_ipu_cm_core_aonRegs *ipuCmReg =
  52         (CSL_ipu_cm_core_aonRegs *) CSL_MPU_IPU_CM_CORE_AON_REGS;
  53     CSL_rtc_cm_core_aonRegs *rtcCmReg =
  54         (CSL_rtc_cm_core_aonRegs *) CSL_MPU_RTC_CM_CORE_AON_REGS;
  55     CSL_vpe_cm_core_aonRegs *vpeCmReg =
  56         (CSL_vpe_cm_core_aonRegs *) CSL_MPU_VPE_CM_CORE_AON_REGS;
  57     CSL_wkupaon_cmRegs *wkupAonCmReg =
  58         (CSL_wkupaon_cmRegs *) CSL_MPU_WKUPAON_CM_REGS;
  59     CSL_mpu_cm_core_aonRegs *mpuCmReg =
  60         (CSL_mpu_cm_core_aonRegs *) CSL_MPU_MPU_CM_CORE_AON_REGS;
  61     CSL_dsp1_cm_core_aonRegs *dsp1CmReg =
  62         (CSL_dsp1_cm_core_aonRegs *) CSL_MPU_DSP1_CM_CORE_AON_REGS;
  63     CSL_dsp2_cm_core_aonRegs *dsp2CmReg =
  64         (CSL_dsp2_cm_core_aonRegs *) CSL_MPU_DSP2_CM_CORE_AON_REGS;
  65     CSL_iva_cm_coreRegs *ivaCmReg =
  66         (CSL_iva_cm_coreRegs *) CSL_MPU_IVA_CM_CORE_REGS;
  67
  68     /* PRCM clock domain state setting functions */
  69     CSL_FINST(camCmReg->CM_CAM_CLKSTCTRL_REG,
  70         CAM_CM_CORE_CM_CAM_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
  71 /*
  72     while(CSL_CAM_CM_CORE_CM_CAM_CLKSTCTRL_REG_CLKACTIVITY_VIP1_GCLK_ACT !=
  73        CSL_FEXT(camCmReg->CM_CAM_CLKSTCTRL_REG,
  74         CAM_CM_CORE_CM_CAM_CLKSTCTRL_REG_CLKACTIVITY_VIP1_GCLK));
  75 */
  76
  77     CSL_FINST(l4PerCmReg->CM_L4PER_CLKSTCTRL_REG,
  78         L4PER_CM_CORE_COMPONENT_CM_L4PER_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
  79
  80     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_CLKSTCTRL_REG_CLKACTIVITY_L4PER_L3_GICLK_ACT !=
  81        CSL_FEXT(l4PerCmReg->CM_L4PER_CLKSTCTRL_REG,
  82         L4PER_CM_CORE_COMPONENT_CM_L4PER_CLKSTCTRL_REG_CLKACTIVITY_L4PER_L3_GICLK));
  83
  84     CSL_FINST(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
  85         L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
  86 /*
  87     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK_ACT !=
  88        CSL_FEXT(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
  89         L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK));
  90 */
  91
  92     CSL_FINST(l4PerCmReg->CM_L4PER3_CLKSTCTRL_REG,
  93         L4PER_CM_CORE_COMPONENT_CM_L4PER3_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
  94
  95     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER3_CLKSTCTRL_REG_CLKACTIVITY_L4PER3_L3_GICLK_ACT !=
  96        CSL_FEXT(l4PerCmReg->CM_L4PER3_CLKSTCTRL_REG,
  97         L4PER_CM_CORE_COMPONENT_CM_L4PER3_CLKSTCTRL_REG_CLKACTIVITY_L4PER3_L3_GICLK));
  98
  99     CSL_FINST(l3InitCmReg->CM_L3INIT_CLKSTCTRL_REG,
 100         L3INIT_CM_CORE_CM_L3INIT_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 101
 102     while(CSL_L3INIT_CM_CORE_CM_L3INIT_CLKSTCTRL_REG_CLKACTIVITY_L3INIT_L3_GICLK_ACT !=
 103        CSL_FEXT(l3InitCmReg->CM_L3INIT_CLKSTCTRL_REG,
 104         L3INIT_CM_CORE_CM_L3INIT_CLKSTCTRL_REG_CLKACTIVITY_L3INIT_L3_GICLK));
 105
 106     CSL_FINST(l3InitCmReg->CM_GMAC_CLKSTCTRL_REG,
 107         L3INIT_CM_CORE_CM_GMAC_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 108 /*
 109     while(CSL_L3INIT_CM_CORE_CM_GMAC_CLKSTCTRL_REG_CLKACTIVITY_GMII_250MHZ_CLK_ACT !=
 110        CSL_FEXT(l3InitCmReg->CM_GMAC_CLKSTCTRL_REG,
 111         L3INIT_CM_CORE_CM_GMAC_CLKSTCTRL_REG_CLKACTIVITY_GMII_250MHZ_CLK));
 112 */
 113
 114     CSL_FINST(coreCmReg->CM_EMIF_CLKSTCTRL_REG,
 115         CORE_CM_CORE_CM_EMIF_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 116
 117     while(CSL_CORE_CM_CORE_CM_EMIF_CLKSTCTRL_REG_CLKACTIVITY_EMIF_L3_GICLK_ACT !=
 118        CSL_FEXT(coreCmReg->CM_EMIF_CLKSTCTRL_REG,
 119         CORE_CM_CORE_CM_EMIF_CLKSTCTRL_REG_CLKACTIVITY_EMIF_L3_GICLK));
 120
 121     CSL_FINST(coreCmReg->CM_L4CFG_CLKSTCTRL_REG,
 122         CORE_CM_CORE_CM_L4CFG_CLKSTCTRL_REG_CLKTRCTRL, RESERVED_2);
 123
 124     while(CSL_CORE_CM_CORE_CM_L4CFG_CLKSTCTRL_REG_CLKACTIVITY_L4CFG_L4_GICLK_ACT !=
 125        CSL_FEXT(coreCmReg->CM_L4CFG_CLKSTCTRL_REG,
 126         CORE_CM_CORE_CM_L4CFG_CLKSTCTRL_REG_CLKACTIVITY_L4CFG_L4_GICLK));
 127
 128     CSL_FINST(coreCmReg->CM_DMA_CLKSTCTRL_REG,
 129         CORE_CM_CORE_CM_DMA_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 130
 131     while(CSL_CORE_CM_CORE_CM_DMA_CLKSTCTRL_REG_CLKACTIVITY_DMA_L3_GICLK_ACT !=
 132        CSL_FEXT(coreCmReg->CM_DMA_CLKSTCTRL_REG,
 133         CORE_CM_CORE_CM_DMA_CLKSTCTRL_REG_CLKACTIVITY_DMA_L3_GICLK));
 134
 135     CSL_FINST(coreCmReg->CM_L3MAIN1_CLKSTCTRL_REG,
 136         CORE_CM_CORE_CM_L3MAIN1_CLKSTCTRL_REG_CLKTRCTRL, RESERVED_2);
 137
 138     while(CSL_CORE_CM_CORE_CM_L3MAIN1_CLKSTCTRL_REG_CLKACTIVITY_L3MAIN1_L3_GICLK_ACT !=
 139        CSL_FEXT(coreCmReg->CM_L3MAIN1_CLKSTCTRL_REG,
 140         CORE_CM_CORE_CM_L3MAIN1_CLKSTCTRL_REG_CLKACTIVITY_L3MAIN1_L3_GICLK));
 141
 142     CSL_FINST(coreCmReg->CM_IPU2_CLKSTCTRL_REG,
 143         CORE_CM_CORE_CM_IPU2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 144 /*
 145     while(CSL_CORE_CM_CORE_CM_IPU2_CLKSTCTRL_REG_CLKACTIVITY_IPU2_GFCLK_ACT !=
 146        CSL_FEXT(coreCmReg->CM_IPU2_CLKSTCTRL_REG,
 147         CORE_CM_CORE_CM_IPU2_CLKSTCTRL_REG_CLKACTIVITY_IPU2_GFCLK));
 148 */
 149
 150     CSL_FINST(coreAonCmReg->CM_COREAON_CLKSTCTRL_REG,
 151         COREAON_CM_CORE_CM_COREAON_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 152 /*
 153     while(CSL_COREAON_CM_CORE_CM_COREAON_CLKSTCTRL_REG_CLKACTIVITY_COREAON_L4_GICLK_ACT !=
 154        CSL_FEXT(coreAonCmReg->CM_COREAON_CLKSTCTRL_REG,
 155         COREAON_CM_CORE_CM_COREAON_CLKSTCTRL_REG_CLKACTIVITY_COREAON_L4_GICLK));
 156 */
 157
 158     CSL_FINST(dssCmReg->CM_DSS_CLKSTCTRL_REG,
 159         DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 160 /*
 161     while(CSL_DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK_ACT !=
 162        CSL_FEXT(dssCmReg->CM_DSS_CLKSTCTRL_REG,
 163         DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK));
 164 */
 165
 166     CSL_FINST(ipuCmReg->CM_IPU1_CLKSTCTRL_REG,
 167         IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 168 /*
 169     while(CSL_IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKACTIVITY_IPU1_GFCLK_ACT !=
 170        CSL_FEXT(ipuCmReg->CM_IPU1_CLKSTCTRL_REG,
 171         IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKACTIVITY_IPU1_GFCLK));
 172 */
 173
 174     CSL_FINST(ipuCmReg->CM_IPU_CLKSTCTRL_REG,
 175         IPU_CM_CORE_AON_CM_IPU_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 176 /*
 177     while(CSL_IPU_CM_CORE_AON_CM_IPU_CLKSTCTRL_REG_CLKACTIVITY_IPU_L3_GICLK_ACT !=
 178        CSL_FEXT(ipuCmReg->CM_IPU_CLKSTCTRL_REG,
 179         IPU_CM_CORE_AON_CM_IPU_CLKSTCTRL_REG_CLKACTIVITY_IPU_L3_GICLK));
 180 */
 181
 182     CSL_FINST(rtcCmReg->CM_RTC_CLKSTCTRL_REG,
 183         RTC_CM_CORE_AON_CM_RTC_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 184 /*
 185     while(CSL_RTC_CM_CORE_AON_CM_RTC_CLKSTCTRL_REG_CLKACTIVITY_RTC_L4_GICLK_ACT !=
 186        CSL_FEXT(rtcCmReg->CM_RTC_CLKSTCTRL_REG,
 187         RTC_CM_CORE_AON_CM_RTC_CLKSTCTRL_REG_CLKACTIVITY_RTC_L4_GICLK));
 188 */
 189
 190     CSL_FINST(vpeCmReg->CM_VPE_CLKSTCTRL_REG,
 191         VPE_CM_CORE_AON_CM_VPE_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 192 /*
 193     while(CSL_VPE_CM_CORE_AON_CM_VPE_CLKSTCTRL_REG_CLKACTIVITY_VPE_GCLK_ACT !=
 194        CSL_FEXT(vpeCmReg->CM_VPE_CLKSTCTRL_REG,
 195         VPE_CM_CORE_AON_CM_VPE_CLKSTCTRL_REG_CLKACTIVITY_VPE_GCLK));
 196 */
 197
 198     CSL_FINST(wkupAonCmReg->CM_WKUPAON_CLKSTCTRL_REG,
 199         WKUPAON_CM_CM_WKUPAON_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 200 /*
 201     while(CSL_WKUPAON_CM_CM_WKUPAON_CLKSTCTRL_REG_CLKACTIVITY_SYS_CLK_ACT !=
 202        CSL_FEXT(wkupAonCmReg->CM_WKUPAON_CLKSTCTRL_REG,
 203         WKUPAON_CM_CM_WKUPAON_CLKSTCTRL_REG_CLKACTIVITY_SYS_CLK));
 204 */
 205
 206     CSL_FINST(mpuCmReg->CM_MPU_CLKSTCTRL_REG,
 207         MPU_CM_CORE_AON_CM_MPU_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 208 /*
 209     while(CSL_MPU_CM_CORE_AON_CM_MPU_CLKSTCTRL_REG_CLKACTIVITY_MPU_GCLK_ACT !=
 210        CSL_FEXT(mpuCmReg->CM_MPU_CLKSTCTRL_REG,
 211         MPU_CM_CORE_AON_CM_MPU_CLKSTCTRL_REG_CLKACTIVITY_MPU_GCLK));
 212 */
 213
 214     CSL_FINST(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
 215         DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 216 /*
 217     while(CSL_DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK_ACT !=
 218        CSL_FEXT(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
 219         DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK));
 220 */
 221
 222     CSL_FINST(dsp2CmReg->CM_DSP2_CLKSTCTRL_REG,
 223         DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 224 /*
 225     while(CSL_DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKACTIVITY_DSP2_GFCLK_ACT !=
 226        CSL_FEXT(dsp2CmReg->CM_DSP2_CLKSTCTRL_REG,
 227         DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKACTIVITY_DSP2_GFCLK));
 228 */
 229
 230     CSL_FINST(ivaCmReg->CM_IVA_CLKSTCTRL_REG,
 231         IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
 232 /*
 233     while(CSL_IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKACTIVITY_IVA_GCLK_ACT !=
 234        CSL_FEXT(ivaCmReg->CM_IVA_CLKSTCTRL_REG,
 235         IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKACTIVITY_IVA_GCLK));
 236 */
 237
 238     /* PRCM Generic module mode setting functions */
 239
 240     CSL_FINST(camCmReg->CM_CAM_VIP1_CLKCTRL_REG,
 241         CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_MODULEMODE, AUTO);
 242
 243     while(CSL_CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_IDLEST_FUNC !=
 244        CSL_FEXT(camCmReg->CM_CAM_VIP1_CLKCTRL_REG,
 245         CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_IDLEST));
 246
 247     CSL_FINST(camCmReg->CM_CAM_VIP2_CLKCTRL_REG,
 248         CAM_CM_CORE_CM_CAM_VIP2_CLKCTRL_REG_MODULEMODE, AUTO);
 249
 250     while(CSL_CAM_CM_CORE_CM_CAM_VIP2_CLKCTRL_REG_IDLEST_FUNC !=
 251        CSL_FEXT(camCmReg->CM_CAM_VIP2_CLKCTRL_REG,
 252         CAM_CM_CORE_CM_CAM_VIP2_CLKCTRL_REG_IDLEST));
 253
 254     CSL_FINST(camCmReg->CM_CAM_VIP3_CLKCTRL_REG,
 255         CAM_CM_CORE_CM_CAM_VIP3_CLKCTRL_REG_MODULEMODE, AUTO);
 256
 257     while(CSL_CAM_CM_CORE_CM_CAM_VIP3_CLKCTRL_REG_IDLEST_FUNC !=
 258        CSL_FEXT(camCmReg->CM_CAM_VIP3_CLKCTRL_REG,
 259         CAM_CM_CORE_CM_CAM_VIP3_CLKCTRL_REG_IDLEST));
 260
 261     CSL_FINST(coreCmReg->CM_DMA_DMA_SYSTEM_CLKCTRL_REG,
 262         CORE_CM_CORE_CM_DMA_DMA_SYSTEM_CLKCTRL_REG_MODULEMODE, AUTO);
 263
 264     while(CSL_CORE_CM_CORE_CM_DMA_DMA_SYSTEM_CLKCTRL_REG_IDLEST_FUNC !=
 265        CSL_FEXT(coreCmReg->CM_DMA_DMA_SYSTEM_CLKCTRL_REG,
 266         CORE_CM_CORE_CM_DMA_DMA_SYSTEM_CLKCTRL_REG_IDLEST));
 267
 268     CSL_FINST(coreCmReg->CM_EMIF_DMM_CLKCTRL_REG,
 269         CORE_CM_CORE_CM_EMIF_DMM_CLKCTRL_REG_MODULEMODE, AUTO);
 270
 271     while(CSL_CORE_CM_CORE_CM_EMIF_DMM_CLKCTRL_REG_IDLEST_FUNC !=
 272        CSL_FEXT(coreCmReg->CM_EMIF_DMM_CLKCTRL_REG,
 273         CORE_CM_CORE_CM_EMIF_DMM_CLKCTRL_REG_IDLEST));
 274
 275     CSL_FINST(coreCmReg->CM_EMIF_EMIF1_CLKCTRL_REG,
 276         CORE_CM_CORE_CM_EMIF_EMIF1_CLKCTRL_REG_MODULEMODE, AUTO);
 277
 278     while(CSL_CORE_CM_CORE_CM_EMIF_EMIF1_CLKCTRL_REG_IDLEST_FUNC !=
 279        CSL_FEXT(coreCmReg->CM_EMIF_EMIF1_CLKCTRL_REG,
 280         CORE_CM_CORE_CM_EMIF_EMIF1_CLKCTRL_REG_IDLEST));
 281
 282     CSL_FINST(coreCmReg->CM_EMIF_EMIF2_CLKCTRL_REG,
 283         CORE_CM_CORE_CM_EMIF_EMIF2_CLKCTRL_REG_MODULEMODE, AUTO);
 284
 285     while(CSL_CORE_CM_CORE_CM_EMIF_EMIF2_CLKCTRL_REG_IDLEST_FUNC !=
 286        CSL_FEXT(coreCmReg->CM_EMIF_EMIF2_CLKCTRL_REG,
 287         CORE_CM_CORE_CM_EMIF_EMIF2_CLKCTRL_REG_IDLEST));
 288
 289     CSL_FINST(coreCmReg->CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG,
 290         CORE_CM_CORE_CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG_MODULEMODE, AUTO);
 291
 292     while(CSL_CORE_CM_CORE_CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG_IDLEST_FUNC !=
 293        CSL_FEXT(coreCmReg->CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG,
 294         CORE_CM_CORE_CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG_IDLEST));
 295
 296     CSL_FINST(coreCmReg->CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG,
 297         CORE_CM_CORE_CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG_MODULEMODE, AUTO);
 298
 299     while(CSL_CORE_CM_CORE_CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG_IDLEST_FUNC !=
 300        CSL_FEXT(coreCmReg->CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG,
 301         CORE_CM_CORE_CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG_IDLEST));
 302
 303     CSL_FINST(coreCmReg->CM_L3MAIN1_GPMC_CLKCTRL_REG,
 304         CORE_CM_CORE_CM_L3MAIN1_GPMC_CLKCTRL_REG_MODULEMODE, AUTO);
 305
 306     while(CSL_CORE_CM_CORE_CM_L3MAIN1_GPMC_CLKCTRL_REG_IDLEST_FUNC !=
 307        CSL_FEXT(coreCmReg->CM_L3MAIN1_GPMC_CLKCTRL_REG,
 308         CORE_CM_CORE_CM_L3MAIN1_GPMC_CLKCTRL_REG_IDLEST));
 309
 310     CSL_FINST(coreCmReg->CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG,
 311         CORE_CM_CORE_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG_MODULEMODE, AUTO);
 312
 313     while(CSL_CORE_CM_CORE_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG_IDLEST_FUNC !=
 314        CSL_FEXT(coreCmReg->CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG,
 315         CORE_CM_CORE_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG_IDLEST));
 316
 317     CSL_FINST(coreCmReg->CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG,
 318         CORE_CM_CORE_CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG_MODULEMODE, AUTO);
 319
 320     while(CSL_CORE_CM_CORE_CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG_IDLEST_FUNC !=
 321        CSL_FEXT(coreCmReg->CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG,
 322         CORE_CM_CORE_CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG_IDLEST));
 323
 324     CSL_FINST(coreCmReg->CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG,
 325         CORE_CM_CORE_CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG_MODULEMODE, AUTO);
 326
 327     while(CSL_CORE_CM_CORE_CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG_IDLEST_FUNC !=
 328        CSL_FEXT(coreCmReg->CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG,
 329         CORE_CM_CORE_CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG_IDLEST));
 330
 331     CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG,
 332         CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG_MODULEMODE, AUTO);
 333
 334     while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG_IDLEST_FUNC !=
 335        CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG,
 336         CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG_IDLEST));
 337
 338     CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG,
 339         CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG_MODULEMODE, AUTO);
 340
 341     while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG_IDLEST_FUNC !=
 342        CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG,
 343         CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG_IDLEST));
 344
 345     CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG,
 346         CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG_MODULEMODE, AUTO);
 347
 348     while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG_IDLEST_FUNC !=
 349        CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG,
 350         CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG_IDLEST));
 351
 352     CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG,
 353         CORE_CM_CORE_CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG_MODULEMODE, AUTO);
 354
 355     while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG_IDLEST_FUNC !=
 356        CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG,
 357         CORE_CM_CORE_CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG_IDLEST));
 358
 359     CSL_FINST(coreCmReg->CM_L3MAIN1_TPCC_CLKCTRL_REG,
 360         CORE_CM_CORE_CM_L3MAIN1_TPCC_CLKCTRL_REG_MODULEMODE, AUTO);
 361
 362     while(CSL_CORE_CM_CORE_CM_L3MAIN1_TPCC_CLKCTRL_REG_IDLEST_FUNC !=
 363        CSL_FEXT(coreCmReg->CM_L3MAIN1_TPCC_CLKCTRL_REG,
 364         CORE_CM_CORE_CM_L3MAIN1_TPCC_CLKCTRL_REG_IDLEST));
 365
 366     CSL_FINST(coreCmReg->CM_L3MAIN1_TPTC1_CLKCTRL_REG,
 367         CORE_CM_CORE_CM_L3MAIN1_TPTC1_CLKCTRL_REG_MODULEMODE, AUTO);
 368
 369     while(CSL_CORE_CM_CORE_CM_L3MAIN1_TPTC1_CLKCTRL_REG_IDLEST_FUNC !=
 370        CSL_FEXT(coreCmReg->CM_L3MAIN1_TPTC1_CLKCTRL_REG,
 371         CORE_CM_CORE_CM_L3MAIN1_TPTC1_CLKCTRL_REG_IDLEST));
 372
 373     CSL_FINST(coreCmReg->CM_L3MAIN1_TPTC2_CLKCTRL_REG,
 374         CORE_CM_CORE_CM_L3MAIN1_TPTC2_CLKCTRL_REG_MODULEMODE, AUTO);
 375
 376     while(CSL_CORE_CM_CORE_CM_L3MAIN1_TPTC2_CLKCTRL_REG_IDLEST_FUNC !=
 377        CSL_FEXT(coreCmReg->CM_L3MAIN1_TPTC2_CLKCTRL_REG,
 378         CORE_CM_CORE_CM_L3MAIN1_TPTC2_CLKCTRL_REG_IDLEST));
 379
 380 // TODO: Check if enabled or AUTO
 381     CSL_FINS(coreCmReg->CM_L3MAIN1_VCP1_CLKCTRL_REG,
 382         CORE_CM_CORE_CM_L3MAIN1_VCP1_CLKCTRL_REG_MODULEMODE, 2U);
 383
 384     while(CSL_CORE_CM_CORE_CM_L3MAIN1_VCP1_CLKCTRL_REG_IDLEST_FUNC !=
 385        CSL_FEXT(coreCmReg->CM_L3MAIN1_VCP1_CLKCTRL_REG,
 386         CORE_CM_CORE_CM_L3MAIN1_VCP1_CLKCTRL_REG_IDLEST));
 387
 388     CSL_FINS(coreCmReg->CM_L3MAIN1_VCP2_CLKCTRL_REG,
 389         CORE_CM_CORE_CM_L3MAIN1_VCP2_CLKCTRL_REG_MODULEMODE, 2U);
 390
 391     while(CSL_CORE_CM_CORE_CM_L3MAIN1_VCP2_CLKCTRL_REG_IDLEST_FUNC !=
 392        CSL_FEXT(coreCmReg->CM_L3MAIN1_VCP2_CLKCTRL_REG,
 393         CORE_CM_CORE_CM_L3MAIN1_VCP2_CLKCTRL_REG_IDLEST));
 394
 395     CSL_FINST(coreCmReg->CM_L4CFG_L4_CFG_CLKCTRL_REG,
 396         CORE_CM_CORE_CM_L4CFG_L4_CFG_CLKCTRL_REG_MODULEMODE, AUTO);
 397
 398     while(CSL_CORE_CM_CORE_CM_L4CFG_L4_CFG_CLKCTRL_REG_IDLEST_FUNC !=
 399        CSL_FEXT(coreCmReg->CM_L4CFG_L4_CFG_CLKCTRL_REG,
 400         CORE_CM_CORE_CM_L4CFG_L4_CFG_CLKCTRL_REG_IDLEST));
 401
 402     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX1_CLKCTRL_REG,
 403         CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_MODULEMODE, AUTO);
 404
 405     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST_FUNC !=
 406        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX1_CLKCTRL_REG,
 407         CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST));
 408
 409     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX10_CLKCTRL_REG,
 410         CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_MODULEMODE, AUTO);
 411
 412     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST_FUNC !=
 413        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX10_CLKCTRL_REG,
 414         CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST));
 415
 416     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX11_CLKCTRL_REG,
 417         CORE_CM_CORE_CM_L4CFG_MAILBOX11_CLKCTRL_REG_MODULEMODE, AUTO);
 418
 419     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX11_CLKCTRL_REG_IDLEST_FUNC !=
 420        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX11_CLKCTRL_REG,
 421         CORE_CM_CORE_CM_L4CFG_MAILBOX11_CLKCTRL_REG_IDLEST));
 422
 423     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX12_CLKCTRL_REG,
 424         CORE_CM_CORE_CM_L4CFG_MAILBOX12_CLKCTRL_REG_MODULEMODE, AUTO);
 425
 426     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX12_CLKCTRL_REG_IDLEST_FUNC !=
 427        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX12_CLKCTRL_REG,
 428         CORE_CM_CORE_CM_L4CFG_MAILBOX12_CLKCTRL_REG_IDLEST));
 429
 430     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX13_CLKCTRL_REG,
 431         CORE_CM_CORE_CM_L4CFG_MAILBOX13_CLKCTRL_REG_MODULEMODE, AUTO);
 432
 433     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX13_CLKCTRL_REG_IDLEST_FUNC !=
 434        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX13_CLKCTRL_REG,
 435         CORE_CM_CORE_CM_L4CFG_MAILBOX13_CLKCTRL_REG_IDLEST));
 436
 437     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX2_CLKCTRL_REG,
 438         CORE_CM_CORE_CM_L4CFG_MAILBOX2_CLKCTRL_REG_MODULEMODE, AUTO);
 439
 440     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX2_CLKCTRL_REG_IDLEST_FUNC !=
 441        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX2_CLKCTRL_REG,
 442         CORE_CM_CORE_CM_L4CFG_MAILBOX2_CLKCTRL_REG_IDLEST));
 443
 444     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX3_CLKCTRL_REG,
 445         CORE_CM_CORE_CM_L4CFG_MAILBOX3_CLKCTRL_REG_MODULEMODE, AUTO);
 446
 447     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX3_CLKCTRL_REG_IDLEST_FUNC !=
 448        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX3_CLKCTRL_REG,
 449         CORE_CM_CORE_CM_L4CFG_MAILBOX3_CLKCTRL_REG_IDLEST));
 450
 451     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX4_CLKCTRL_REG,
 452         CORE_CM_CORE_CM_L4CFG_MAILBOX4_CLKCTRL_REG_MODULEMODE, AUTO);
 453
 454     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX4_CLKCTRL_REG_IDLEST_FUNC !=
 455        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX4_CLKCTRL_REG,
 456         CORE_CM_CORE_CM_L4CFG_MAILBOX4_CLKCTRL_REG_IDLEST));
 457
 458     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX5_CLKCTRL_REG,
 459         CORE_CM_CORE_CM_L4CFG_MAILBOX5_CLKCTRL_REG_MODULEMODE, AUTO);
 460
 461     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX5_CLKCTRL_REG_IDLEST_FUNC !=
 462        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX5_CLKCTRL_REG,
 463         CORE_CM_CORE_CM_L4CFG_MAILBOX5_CLKCTRL_REG_IDLEST));
 464
 465     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX6_CLKCTRL_REG,
 466         CORE_CM_CORE_CM_L4CFG_MAILBOX6_CLKCTRL_REG_MODULEMODE, AUTO);
 467
 468     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX6_CLKCTRL_REG_IDLEST_FUNC !=
 469        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX6_CLKCTRL_REG,
 470         CORE_CM_CORE_CM_L4CFG_MAILBOX6_CLKCTRL_REG_IDLEST));
 471
 472     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX7_CLKCTRL_REG,
 473         CORE_CM_CORE_CM_L4CFG_MAILBOX7_CLKCTRL_REG_MODULEMODE, AUTO);
 474
 475     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX7_CLKCTRL_REG_IDLEST_FUNC !=
 476        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX7_CLKCTRL_REG,
 477         CORE_CM_CORE_CM_L4CFG_MAILBOX7_CLKCTRL_REG_IDLEST));
 478
 479     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX8_CLKCTRL_REG,
 480         CORE_CM_CORE_CM_L4CFG_MAILBOX8_CLKCTRL_REG_MODULEMODE, AUTO);
 481
 482     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX8_CLKCTRL_REG_IDLEST_FUNC !=
 483        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX8_CLKCTRL_REG,
 484         CORE_CM_CORE_CM_L4CFG_MAILBOX8_CLKCTRL_REG_IDLEST));
 485
 486     CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX9_CLKCTRL_REG,
 487         CORE_CM_CORE_CM_L4CFG_MAILBOX9_CLKCTRL_REG_MODULEMODE, AUTO);
 488
 489     while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX9_CLKCTRL_REG_IDLEST_FUNC !=
 490        CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX9_CLKCTRL_REG,
 491         CORE_CM_CORE_CM_L4CFG_MAILBOX9_CLKCTRL_REG_IDLEST));
 492
 493     CSL_FINST(coreCmReg->CM_L4CFG_SPINLOCK_CLKCTRL_REG,
 494         CORE_CM_CORE_CM_L4CFG_SPINLOCK_CLKCTRL_REG_MODULEMODE, AUTO);
 495
 496     while(CSL_CORE_CM_CORE_CM_L4CFG_SPINLOCK_CLKCTRL_REG_IDLEST_FUNC !=
 497        CSL_FEXT(coreCmReg->CM_L4CFG_SPINLOCK_CLKCTRL_REG,
 498         CORE_CM_CORE_CM_L4CFG_SPINLOCK_CLKCTRL_REG_IDLEST));
 499
 500     CSL_FINST(ipuCmReg->CM_IPU_TIMER5_CLKCTRL_REG,
 501         IPU_CM_CORE_AON_CM_IPU_TIMER5_CLKCTRL_REG_MODULEMODE, ENABLE);
 502
 503     while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER5_CLKCTRL_REG_IDLEST_FUNC !=
 504        CSL_FEXT(ipuCmReg->CM_IPU_TIMER5_CLKCTRL_REG,
 505         IPU_CM_CORE_AON_CM_IPU_TIMER5_CLKCTRL_REG_IDLEST));
 506
 507     CSL_FINST(ipuCmReg->CM_IPU_TIMER6_CLKCTRL_REG,
 508         IPU_CM_CORE_AON_CM_IPU_TIMER6_CLKCTRL_REG_MODULEMODE, ENABLE);
 509
 510     while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER6_CLKCTRL_REG_IDLEST_FUNC !=
 511        CSL_FEXT(ipuCmReg->CM_IPU_TIMER6_CLKCTRL_REG,
 512         IPU_CM_CORE_AON_CM_IPU_TIMER6_CLKCTRL_REG_IDLEST));
 513
 514     CSL_FINST(ipuCmReg->CM_IPU_TIMER7_CLKCTRL_REG,
 515         IPU_CM_CORE_AON_CM_IPU_TIMER7_CLKCTRL_REG_MODULEMODE, ENABLE);
 516
 517     while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER7_CLKCTRL_REG_IDLEST_FUNC !=
 518        CSL_FEXT(ipuCmReg->CM_IPU_TIMER7_CLKCTRL_REG,
 519         IPU_CM_CORE_AON_CM_IPU_TIMER7_CLKCTRL_REG_IDLEST));
 520
 521     CSL_FINST(ipuCmReg->CM_IPU_TIMER8_CLKCTRL_REG,
 522         IPU_CM_CORE_AON_CM_IPU_TIMER8_CLKCTRL_REG_MODULEMODE, ENABLE);
 523
 524     while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER8_CLKCTRL_REG_IDLEST_FUNC !=
 525        CSL_FEXT(ipuCmReg->CM_IPU_TIMER8_CLKCTRL_REG,
 526         IPU_CM_CORE_AON_CM_IPU_TIMER8_CLKCTRL_REG_IDLEST));
 527
 528     CSL_FINST(l3InitCmReg->CM_L3INIT_MMC1_CLKCTRL_REG,
 529         L3INIT_CM_CORE_CM_L3INIT_MMC1_CLKCTRL_REG_MODULEMODE, ENABLED);
 530
 531     while(CSL_L3INIT_CM_CORE_CM_L3INIT_MMC1_CLKCTRL_REG_IDLEST_FUNC !=
 532        CSL_FEXT(l3InitCmReg->CM_L3INIT_MMC1_CLKCTRL_REG,
 533         L3INIT_CM_CORE_CM_L3INIT_MMC1_CLKCTRL_REG_IDLEST));
 534
 535     CSL_FINST(l3InitCmReg->CM_L3INIT_MMC2_CLKCTRL_REG,
 536         L3INIT_CM_CORE_CM_L3INIT_MMC2_CLKCTRL_REG_MODULEMODE, ENABLED);
 537
 538     while(CSL_L3INIT_CM_CORE_CM_L3INIT_MMC2_CLKCTRL_REG_IDLEST_FUNC !=
 539        CSL_FEXT(l3InitCmReg->CM_L3INIT_MMC2_CLKCTRL_REG,
 540         L3INIT_CM_CORE_CM_L3INIT_MMC2_CLKCTRL_REG_IDLEST));
 541
 542     CSL_FINST(l3InitCmReg->CM_GMAC_GMAC_CLKCTRL_REG,
 543         L3INIT_CM_CORE_CM_GMAC_GMAC_CLKCTRL_REG_MODULEMODE, ENABLED);
 544
 545     while(CSL_L3INIT_CM_CORE_CM_GMAC_GMAC_CLKCTRL_REG_IDLEST_FUNC !=
 546        CSL_FEXT(l3InitCmReg->CM_GMAC_GMAC_CLKCTRL_REG,
 547         L3INIT_CM_CORE_CM_GMAC_GMAC_CLKCTRL_REG_IDLEST));
 548
 549     CSL_FINST(l4PerCmReg->CM_L4PER2_L4_PER2_CLKCTRL_REG,
 550         L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_MODULEMODE, AUTO);
 551
 552     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST_FUNC !=
 553        CSL_FEXT(l4PerCmReg->CM_L4PER2_L4_PER2_CLKCTRL_REG,
 554         L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST));
 555
 556     CSL_FINST(l4PerCmReg->CM_L4PER3_L4_PER3_CLKCTRL_REG,
 557         L4PER_CM_CORE_COMPONENT_CM_L4PER3_L4_PER3_CLKCTRL_REG_MODULEMODE, AUTO);
 558
 559     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER3_L4_PER3_CLKCTRL_REG_IDLEST_FUNC !=
 560        CSL_FEXT(l4PerCmReg->CM_L4PER3_L4_PER3_CLKCTRL_REG,
 561         L4PER_CM_CORE_COMPONENT_CM_L4PER3_L4_PER3_CLKCTRL_REG_IDLEST));
 562
 563     CSL_FINST(l4PerCmReg->CM_L4PER_GPIO2_CLKCTRL_REG,
 564         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG_MODULEMODE, AUTO);
 565
 566     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG_IDLEST_FUNC !=
 567        CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO2_CLKCTRL_REG,
 568         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG_IDLEST));
 569
 570     CSL_FINST(l4PerCmReg->CM_L4PER_GPIO3_CLKCTRL_REG,
 571         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG_MODULEMODE, AUTO);
 572
 573     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG_IDLEST_FUNC !=
 574        CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO3_CLKCTRL_REG,
 575         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG_IDLEST));
 576
 577     CSL_FINST(l4PerCmReg->CM_L4PER_GPIO4_CLKCTRL_REG,
 578         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG_MODULEMODE, AUTO);
 579
 580     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG_IDLEST_FUNC !=
 581        CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO4_CLKCTRL_REG,
 582         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG_IDLEST));
 583
 584     CSL_FINST(l4PerCmReg->CM_L4PER_GPIO5_CLKCTRL_REG,
 585         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO5_CLKCTRL_REG_MODULEMODE, AUTO);
 586
 587     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO5_CLKCTRL_REG_IDLEST_FUNC !=
 588        CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO5_CLKCTRL_REG,
 589         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO5_CLKCTRL_REG_IDLEST));
 590
 591     CSL_FINST(l4PerCmReg->CM_L4PER_GPIO6_CLKCTRL_REG,
 592         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO6_CLKCTRL_REG_MODULEMODE, AUTO);
 593
 594     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO6_CLKCTRL_REG_IDLEST_FUNC !=
 595        CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO6_CLKCTRL_REG,
 596         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO6_CLKCTRL_REG_IDLEST));
 597
 598     CSL_FINST(l4PerCmReg->CM_L4PER_GPIO7_CLKCTRL_REG,
 599         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO7_CLKCTRL_REG_MODULEMODE, AUTO);
 600
 601     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO7_CLKCTRL_REG_IDLEST_FUNC !=
 602        CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO7_CLKCTRL_REG,
 603         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO7_CLKCTRL_REG_IDLEST));
 604
 605     CSL_FINST(l4PerCmReg->CM_L4PER_GPIO8_CLKCTRL_REG,
 606         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO8_CLKCTRL_REG_MODULEMODE, AUTO);
 607
 608     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO8_CLKCTRL_REG_IDLEST_FUNC !=
 609        CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO8_CLKCTRL_REG,
 610         L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO8_CLKCTRL_REG_IDLEST));
 611
 612     CSL_FINST(l4PerCmReg->CM_L4PER_I2C1_CLKCTRL_REG,
 613         L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C1_CLKCTRL_REG_MODULEMODE, ENABLE);
 614
 615     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C1_CLKCTRL_REG_IDLEST_FUNC !=
 616        CSL_FEXT(l4PerCmReg->CM_L4PER_I2C1_CLKCTRL_REG,
 617         L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C1_CLKCTRL_REG_IDLEST));
 618
 619     CSL_FINST(l4PerCmReg->CM_L4PER_I2C2_CLKCTRL_REG,
 620         L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C2_CLKCTRL_REG_MODULEMODE, ENABLE);
 621
 622     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C2_CLKCTRL_REG_IDLEST_FUNC !=
 623        CSL_FEXT(l4PerCmReg->CM_L4PER_I2C2_CLKCTRL_REG,
 624         L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C2_CLKCTRL_REG_IDLEST));
 625
 626     CSL_FINST(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG,
 627         L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_MODULEMODE, ENABLE);
 628
 629     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST_FUNC !=
 630        CSL_FEXT(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG,
 631         L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST));
 632
 633     CSL_FINST(l4PerCmReg->CM_L4PER_I2C4_CLKCTRL_REG,
 634         L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C4_CLKCTRL_REG_MODULEMODE, ENABLE);
 635
 636     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C4_CLKCTRL_REG_IDLEST_FUNC !=
 637        CSL_FEXT(l4PerCmReg->CM_L4PER_I2C4_CLKCTRL_REG,
 638         L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C4_CLKCTRL_REG_IDLEST));
 639
 640     CSL_FINST(l4PerCmReg->CM_L4PER_L4_PER1_CLKCTRL_REG,
 641         L4PER_CM_CORE_COMPONENT_CM_L4PER_L4_PER1_CLKCTRL_REG_MODULEMODE, AUTO);
 642
 643     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_L4_PER1_CLKCTRL_REG_IDLEST_FUNC !=
 644        CSL_FEXT(l4PerCmReg->CM_L4PER_L4_PER1_CLKCTRL_REG,
 645         L4PER_CM_CORE_COMPONENT_CM_L4PER_L4_PER1_CLKCTRL_REG_IDLEST));
 646
 647     CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI1_CLKCTRL_REG,
 648         L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_MODULEMODE, ENABLE);
 649
 650     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_IDLEST_FUNC !=
 651        CSL_FEXT(l4PerCmReg->CM_L4PER_MCSPI1_CLKCTRL_REG,
 652         L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_IDLEST));
 653
 654     CSL_FINST(l4PerCmReg->CM_L4PER_MMC3_CLKCTRL_REG,
 655         L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC3_CLKCTRL_REG_MODULEMODE, ENABLE);
 656
 657     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC3_CLKCTRL_REG_IDLEST_FUNC !=
 658        CSL_FEXT(l4PerCmReg->CM_L4PER_MMC3_CLKCTRL_REG,
 659         L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC3_CLKCTRL_REG_IDLEST));
 660
 661     CSL_FINST(l4PerCmReg->CM_L4PER_MMC4_CLKCTRL_REG,
 662         L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC4_CLKCTRL_REG_MODULEMODE, ENABLE);
 663
 664     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC4_CLKCTRL_REG_IDLEST_FUNC !=
 665        CSL_FEXT(l4PerCmReg->CM_L4PER_MMC4_CLKCTRL_REG,
 666         L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC4_CLKCTRL_REG_IDLEST));
 667
 668     CSL_FINST(l4PerCmReg->CM_L4PER_TIMER10_CLKCTRL_REG,
 669         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER10_CLKCTRL_REG_MODULEMODE, ENABLE);
 670
 671     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER10_CLKCTRL_REG_IDLEST_FUNC !=
 672        CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER10_CLKCTRL_REG,
 673         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER10_CLKCTRL_REG_IDLEST));
 674
 675     CSL_FINST(l4PerCmReg->CM_L4PER_TIMER11_CLKCTRL_REG,
 676         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_MODULEMODE, ENABLE);
 677
 678     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST_FUNC !=
 679        CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER11_CLKCTRL_REG,
 680         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST));
 681
 682     CSL_FINST(l4PerCmReg->CM_L4PER_TIMER2_CLKCTRL_REG,
 683         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_MODULEMODE, ENABLE);
 684
 685     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST_FUNC !=
 686        CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER2_CLKCTRL_REG,
 687         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST));
 688
 689     CSL_FINST(l4PerCmReg->CM_L4PER_TIMER3_CLKCTRL_REG,
 690         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER3_CLKCTRL_REG_MODULEMODE, ENABLE);
 691
 692     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER3_CLKCTRL_REG_IDLEST_FUNC !=
 693        CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER3_CLKCTRL_REG,
 694         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER3_CLKCTRL_REG_IDLEST));
 695
 696     CSL_FINST(l4PerCmReg->CM_L4PER_TIMER4_CLKCTRL_REG,
 697         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_MODULEMODE, ENABLE);
 698
 699     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_IDLEST_FUNC !=
 700        CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER4_CLKCTRL_REG,
 701         RTC_CM_CORE_AON_CM_RTC_RTCSS_CLKCTRL_REG_IDLEST));
 702
 703     CSL_FINST(l4PerCmReg->CM_L4PER_TIMER9_CLKCTRL_REG,
 704         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_MODULEMODE, ENABLE);
 705
 706     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_IDLEST_FUNC !=
 707        CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER9_CLKCTRL_REG,
 708         L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_IDLEST));
 709
 710     CSL_FINST(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
 711         L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_MODULEMODE, ENABLED);
 712
 713     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_IDLEST_FUNC !=
 714        CSL_FEXT(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
 715         L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_IDLEST));
 716
 717     CSL_FINST(l4PerCmReg->CM_L4PER_UART1_CLKCTRL_REG,
 718         L4PER_CM_CORE_COMPONENT_CM_L4PER_UART1_CLKCTRL_REG_MODULEMODE, ENABLE);
 719
 720     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART1_CLKCTRL_REG_IDLEST_FUNC !=
 721        CSL_FEXT(l4PerCmReg->CM_L4PER_UART1_CLKCTRL_REG,
 722         L4PER_CM_CORE_COMPONENT_CM_L4PER_UART1_CLKCTRL_REG_IDLEST));
 723
 724     CSL_FINST(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
 725         L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_MODULEMODE, ENABLE);
 726
 727     while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST_FUNC !=
 728        CSL_FEXT(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
 729         L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST));
 730
 731     CSL_FINS(mpuCmReg->CM_MPU_MPU_CLKCTRL_REG,
 732         MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_MODULEMODE, 2U);
 733
 734     while(CSL_MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_IDLEST_FUNC !=
 735        CSL_FEXT(mpuCmReg->CM_MPU_MPU_CLKCTRL_REG,
 736         MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_IDLEST));
 737
 738     CSL_FINST(vpeCmReg->CM_VPE_VPE_CLKCTRL_REG,
 739         VPE_CM_CORE_AON_CM_VPE_VPE_CLKCTRL_REG_MODULEMODE, AUTO);
 740
 741     while(CSL_VPE_CM_CORE_AON_CM_VPE_VPE_CLKCTRL_REG_IDLEST_FUNC !=
 742        CSL_FEXT(vpeCmReg->CM_VPE_VPE_CLKCTRL_REG,
 743         VPE_CM_CORE_AON_CM_VPE_VPE_CLKCTRL_REG_IDLEST));
 744
 745     CSL_FINST(wkupAonCmReg->CM_WKUPAON_GPIO1_CLKCTRL_REG,
 746         WKUPAON_CM_CM_WKUPAON_GPIO1_CLKCTRL_REG_MODULEMODE, AUTO);
 747
 748     while(CSL_WKUPAON_CM_CM_WKUPAON_GPIO1_CLKCTRL_REG_IDLEST_FUNC !=
 749        CSL_FEXT(wkupAonCmReg->CM_WKUPAON_GPIO1_CLKCTRL_REG,
 750         WKUPAON_CM_CM_WKUPAON_GPIO1_CLKCTRL_REG_IDLEST));
 751
 752     CSL_FINST(wkupAonCmReg->CM_WKUPAON_TIMER1_CLKCTRL_REG,
 753         WKUPAON_CM_CM_WKUPAON_TIMER1_CLKCTRL_REG_MODULEMODE, ENABLE);
 754
 755     while(CSL_WKUPAON_CM_CM_WKUPAON_TIMER1_CLKCTRL_REG_IDLEST_FUNC !=
 756        CSL_FEXT(wkupAonCmReg->CM_WKUPAON_TIMER1_CLKCTRL_REG,
 757         WKUPAON_CM_CM_WKUPAON_TIMER1_CLKCTRL_REG_IDLEST));
 758
 759     CSL_FINS(wkupAonCmReg->CM_WKUPAON_TIMER12_CLKCTRL_REG,
 760         WKUPAON_CM_CM_WKUPAON_TIMER12_CLKCTRL_REG_MODULEMODE, 2U);
 761
 762     while(CSL_WKUPAON_CM_CM_WKUPAON_TIMER12_CLKCTRL_REG_IDLEST_FUNC !=
 763        CSL_FEXT(wkupAonCmReg->CM_WKUPAON_TIMER12_CLKCTRL_REG,
 764         WKUPAON_CM_CM_WKUPAON_TIMER12_CLKCTRL_REG_IDLEST));
 765
 766     CSL_FINS(wkupAonCmReg->CM_WKUPAON_WD_TIMER1_CLKCTRL_REG,
 767         WKUPAON_CM_CM_WKUPAON_WD_TIMER1_CLKCTRL_REG_MODULEMODE, 2U);
 768
 769     while(CSL_WKUPAON_CM_CM_WKUPAON_WD_TIMER1_CLKCTRL_REG_IDLEST_FUNC !=
 770        CSL_FEXT(wkupAonCmReg->CM_WKUPAON_WD_TIMER1_CLKCTRL_REG,
 771         WKUPAON_CM_CM_WKUPAON_WD_TIMER1_CLKCTRL_REG_IDLEST));
 772
 773     CSL_FINST(wkupAonCmReg->CM_WKUPAON_WD_TIMER2_CLKCTRL_REG,
 774         WKUPAON_CM_CM_WKUPAON_WD_TIMER2_CLKCTRL_REG_MODULEMODE, ENABLE);
 775
 776     while(CSL_WKUPAON_CM_CM_WKUPAON_WD_TIMER2_CLKCTRL_REG_IDLEST_FUNC !=
 777        CSL_FEXT(wkupAonCmReg->CM_WKUPAON_WD_TIMER2_CLKCTRL_REG,
 778         WKUPAON_CM_CM_WKUPAON_WD_TIMER2_CLKCTRL_REG_IDLEST));
 779
 780     /* PRCM Specialized module mode setting functions */
 781     CSL_FINST(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG,
 782         IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_MODULEMODE, AUTO);
 783
 784     while(CSL_IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST_DISABLE ==
 785        CSL_FEXT(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG,
 786         IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST));
 787
 788     CSL_FINST(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG,
 789         IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_MODULEMODE, AUTO);
 790
 791     while(CSL_IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST_DISABLE ==
 792        CSL_FEXT(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG,
 793         IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST));
 794
 795     CSL_FINST(coreCmReg->CM_IPU2_IPU2_CLKCTRL_REG,
 796         CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_MODULEMODE, AUTO);
 797
 798     while(CSL_CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_IDLEST_DISABLE ==
 799        CSL_FEXT(coreCmReg->CM_IPU2_IPU2_CLKCTRL_REG,
 800         CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_IDLEST));
 801
 802     CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,
 803         DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_MODULEMODE, ENABLED);
 804 /*
 805     while(CSL_DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST_FUNC !=
 806        CSL_FEXT(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,
 807         DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST));
 808 */
 809
 810     CSL_FINST(ipuCmReg->CM_IPU1_IPU1_CLKCTRL_REG,
 811         IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_MODULEMODE, AUTO);
 812 /*
 813     while(CSL_IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_IDLEST_FUNC !=
 814        CSL_FEXT(ipuCmReg->CM_IPU1_IPU1_CLKCTRL_REG,
 815         IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_IDLEST));
 816 */
 817     l4PerCmReg->CM_L4PER_GPIO2_CLKCTRL_REG |= (
 818         (CM_L4PER_GPIO2_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO2_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
 819         (CM_L4PER_GPIO2_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO2_CLKCTRL_MODULEMODE_SHIFT));
 820
 821     l4PerCmReg->CM_L4PER_GPIO3_CLKCTRL_REG |= (
 822         (CM_L4PER_GPIO3_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO3_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
 823         (CM_L4PER_GPIO3_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO3_CLKCTRL_MODULEMODE_SHIFT));
 824
 825     l4PerCmReg->CM_L4PER_GPIO4_CLKCTRL_REG |= (
 826         (CM_L4PER_GPIO4_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO4_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
 827         (CM_L4PER_GPIO4_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO4_CLKCTRL_MODULEMODE_SHIFT));
 828
 829     l4PerCmReg->CM_L4PER_GPIO5_CLKCTRL_REG |= (
 830         (CM_L4PER_GPIO5_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO5_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
 831         (CM_L4PER_GPIO5_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO5_CLKCTRL_MODULEMODE_SHIFT));
 832
 833     l4PerCmReg->CM_L4PER_GPIO6_CLKCTRL_REG |= (
 834         (CM_L4PER_GPIO6_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO6_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
 835         (CM_L4PER_GPIO6_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO6_CLKCTRL_MODULEMODE_SHIFT));
 836
 837     l4PerCmReg->CM_L4PER_GPIO7_CLKCTRL_REG |= (
 838         (CM_L4PER_GPIO7_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO7_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
 839         (CM_L4PER_GPIO7_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO7_CLKCTRL_MODULEMODE_SHIFT));
 840
 841     l4PerCmReg->CM_L4PER_GPIO8_CLKCTRL_REG |= (
 842         (CM_L4PER_GPIO8_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO8_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
 843         (CM_L4PER_GPIO8_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO8_CLKCTRL_MODULEMODE_SHIFT));
 844
 845         return BOARD_SOK;
 846 }