[processor-sdk/performance-audio-sr.git] / pdk_k2g_1_0_1 / packages / ti / board / src / evmK2H / include / board_pll.h
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34 #ifndef EVM_K2H_PLL_H
35 #define EVM_K2H_PLL_H
37 /** \brief Keystone Main/PA/ARM PLL control registers */
39 /* Main/ARM/PA/DDR3 PLLC0 Register Bits */
40 #define PLL_BWADJ_LO_SMASK CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_MASK
41 #define PLL_BWADJ_LO_SHIFT CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_SHIFT
42 #define PLL_BWADJ_LO_MASK (PLL_BWADJ_LO_SMASK >> PLL_BWADJ_LO_SHIFT)
43 #define PLL_CLKOD_SMASK CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MASK
44 #define PLL_CLKOD_SHIFT CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_SHIFT
45 #define PLL_CLKOD_MASK (CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MASK >> PLL_CLKOD_SHIFT)
46 #define PLLM_MULT_HI_SMASK CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_MASK
47 #define PLL_MULT_SHIFT CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_SHIFT
48 #define PLL_DIV_MASK CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_MASK
50 /* Main/ARM/PA PLLC1 Register Bits */
51 #define PLL_BWADJ_HI_MASK CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_MASK
52 #define PLL_PLLRST CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_MASK
53 #define PLLCTL_ENSAT CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_MASK
54 #define MAIN_ENSAT_OFFSET CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_SHIFT
55 #define PA_PLL_SEL CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_MASK
57 /** \brief PLL controller registers */
59 /* PLLC Register Base address */
60 #define PLLCTL_REGS_BASE_ADDR CSL_PLLC_REGS
62 /* PLLC PLLCTL Register Bits */
63 #define PLLCTL_PLLENSRC CSL_PLLC_PLLCTL_PLLENSRC_MASK
64 #define PLLCTL_PLLRST CSL_PLLC_PLLCTL_PLLRST_MASK
65 #define PLLCTL_PLLPWRDN CSL_PLLC_PLLCTL_PLLPWRDN_MASK
66 #define PLLCTL_PLLEN CSL_PLLC_PLLCTL_PLLEN_MASK
68 /* PLLC SECCTL Register Bits */
69 #define PLLCTL_BYPASS CSL_PLLC_SECCTL_BYPASS_MASK
71 /* PLLC PLLM Bits */
72 #define PLLM_MULT_LO_MASK CSL_PLLC_PLLM_PLLM_MASK
74 /* PLLC PLLDIV Bits */
75 #define PLLDIV_ENABLE CSL_PLLC_PLLDIV1_3_DNEN_MASK
76 #define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0)
77 #define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0)
78 #define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1)
79 #define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4)
80 #define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17)
82 /* PLLC PLLCMD Bits */
83 #define PLLSTAT_GO CSL_PLLC_PLLCMD_GOSET_MASK
85 /* Keystone II Chip misc 1 register */
86 #define KS2_CHIP_MISC1 (CSL_BOOT_CFG_REGS + 0xc7c)
87 #define KS2_ARM_PLL_EN CSL_BOOTCFG_CHIP_MISC1_TETRIS_PLL_ENABLE_MASK
89 #endif /* EVM_K2H_PLL_H */