[processor-sdk/performance-audio-sr.git] / pdk_k2g_1_0_1 / packages / ti / board / src / idkAM572x / idkAM572x_pinmux.c
1 /**
2 * @file idkm572x_pinmux.c
3 *
4 * @brief
5 * This is the pin configuration for EVM AM572x.
6 *
7 * \par
8 * ============================================================================
9 * @n (C) Copyright 2009-2015, Texas Instruments, Inc.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 * \par
40 */
42 #include <ti/csl/cslr_device.h>
43 #include <ti/drv/mmcsd/soc/MMCSD_v1.h>
44 #include "board_internal.h"
45 #include "idkam572x_pinmux.h"
46 #include "iodelay_config.h"
48 #define IO_DELAY
49 #define IO_DELAY_STACK_SIZE 64
50 extern void Board_ioStack(void *sp, void (fn)(const boardPadDelayCfg_t *pPadCfgData, uint32_t padArraySize), const boardPadDelayCfg_t *pPadCfgData, uint32_t padArraySize);
52 /**
53 * \brief Temporary stack used for IO delay code
54 */
55 #if defined(_TMS320C6X)
56 #pragma DATA_SECTION (ioStack, "BOARD_IO_DELAY_DATA");
57 far uint32_t ioStack[IO_DELAY_STACK_SIZE];
58 #elif defined(__TI_ARM_V7M4__)
59 #pragma DATA_SECTION (ioStack, "BOARD_IO_DELAY_DATA");
60 uint32_t ioStack[IO_DELAY_STACK_SIZE];
61 #else
62 uint32_t ioStack[IO_DELAY_STACK_SIZE] __attribute__((section("BOARD_IO_DELAY_DATA")));
63 #endif
65 #if !defined(__TI_ARM_V7M4__)
66 #if defined(_TMS320C6X)
67 #pragma CODE_SECTION (boardPadGetSize, "BOARD_IO_DELAY_CODE");
68 mmcBoardPadCfgTable_t* boardGetPinmuxCfg(mmcBoardPadCfgTable_t *ptr, int32_t mode);
69 #else
70 mmcBoardPadCfgTable_t* boardGetPinmuxCfg(mmcBoardPadCfgTable_t *ptr, int32_t mode)
71 __attribute__((section("BOARD_IO_DELAY_CODE")));
72 #endif
73 #endif
75 #define HW_WR_REG32(addr, data) *(unsigned int*)(addr) =(unsigned int)(data)
77 #define CSL_MPU_CORE_PAD_IO_REGISTERS_REGS (0x4a003400U)
78 #define CTRL_CORE_PAD_GPMC_A13 (0x74U) //QSPI_RTCLK
79 #define CTRL_CORE_PAD_GPMC_A14 (0x78U) //QSPI_D3
80 #define CTRL_CORE_PAD_GPMC_A15 (0x7CU) //QSPI_D2
81 #define CTRL_CORE_PAD_GPMC_A16 (0x80U) //QSPI_D0
82 #define CTRL_CORE_PAD_GPMC_A17 (0x84U) //QSPI_D1
83 #define CTRL_CORE_PAD_GPMC_A18 (0x88U) //QSPI_CLK
84 #define CTRL_CORE_PAD_GPMC_CS2 (0xB8U) //QSPI_CSn
85 #define CTRL_CORE_PAD_GPMC_CS3 (0xBCU) //QSPI_CSn
86 #define CTRL_CORE_PAD_GPMC_A3 (0x4CU) //QSPI_CSn
87 #define CTRL_CORE_PAD_GPMC_A4 (0x50U) //QSPI_CSn
89 #define CTRL_CORE_PAD_GPMC_A14_PULLUP_RX_MODE_1 (0x00060001U)
90 #define CTRL_CORE_PAD_GPMC_A15_PULLUP_RX_MODE_1 (0x00060001U)
91 #define CTRL_CORE_PAD_GPMC_A16_PULLUP_RX_MODE_1 (0x00060001U)
92 #define CTRL_CORE_PAD_GPMC_A17_PULLUP_RX_MODE_1 (0x00060001U)
93 #define CTRL_CORE_PAD_GPMC_A18_PULLUP_MODE_1 (0x00020001U)
94 #define CTRL_CORE_PAD_GPMC_CS2_PULLUP_MODE_1 (0x00020001U)
95 #define CTRL_CORE_PAD_GPMC_A13_PULLUP_MODE_1 (0x00020001U)
96 #define CTRL_CORE_PAD_GPMC_CS3_PULLUP_MODE_1 (0x00020001U)
97 #define CTRL_CORE_PAD_GPMC_A3_PULLUP_MODE_1 (0x00020001U)
98 #define CTRL_CORE_PAD_GPMC_A4_PULLUP_MODE_1 (0x00020001U)
100 #define CTRL_CORE_PAD_VIN1A_D15 (0x130U) //GPIO3_19
101 #define CTRL_CORE_PAD_VIN1A_D15_PILLUP (0x20000 | 0x0E)
103 #define CTRL_CORE_PAD_MCASP4_ACLKX (0x334U) //SPI3_SCLK
104 #define CTRL_CORE_PAD_MCASP4_FSX (0x338U) //SPI3_D1
105 #define CTRL_CORE_PAD_MCASP4_AXR1 (0x340U) //SPI3_CS0
107 #define CTRL_CORE_PAD_MCSPI2_SCLK (0x3C0U) //SPI2_SCLK
108 #define CTRL_CORE_PAD_MCSPI2_D1 (0x3C4U) //SPI2_D1
109 #define CTRL_CORE_PAD_MCSPI2_D0 (0x3C8U) //SPI2_D0
110 #define CTRL_CORE_PAD_MCSPI2_CS0 (0x3CCU) //SPI2_CS0
112 #define CTRL_CORE_PAD_MCASP4_ACLKX_PUPDD_RX_MODE 0xc0002 //(0x00040003U)
113 #define CTRL_CORE_PAD_MCASP4_FSX_PUPDD_RX_MODE 0xc0002 //(0x00040003U)
114 #define CTRL_CORE_PAD_MCASP4_AXR1_PUPDD_RX_MODE 0x60002 //(0x00040003U)
116 extern const boardPadDelayCfg_t pad[];
118 void PinmuxQSPIConfig();
120 void PinmuxI2cConfig (Uint32 instNum)
121 {
122 Uint32 regVal = 0U;
124 switch(instNum)
125 {
126 case 1:
127 regVal = 0U;
128 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C1_SDA_I2C1_SDA_WAKEUPENABLE, DISABLE);
129 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C1_SDA_I2C1_SDA_INPUTENABLE, ENABLE);
130 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C1_SDA_I2C1_SDA_PULLTYPESELECT, PULL_UP);
131 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C1_SDA_I2C1_SDA_PULLUDENABLE, ENABLE);
132 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_I2C1_SDA = regVal;
134 regVal = 0U;
135 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C1_SCL_I2C1_SCL_WAKEUPENABLE, DISABLE);
136 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C1_SCL_I2C1_SCL_INPUTENABLE, ENABLE);
137 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C1_SCL_I2C1_SCL_PULLTYPESELECT, PULL_UP);
138 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C1_SCL_I2C1_SCL_PULLUDENABLE, ENABLE);
139 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_I2C1_SCL = regVal;
140 break;
142 case 3:
143 regVal = 0U;
144 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SDA_I2C3_SDA_WAKEUPENABLE, DISABLE);
145 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SDA_I2C3_SDA_INPUTENABLE, ENABLE);
146 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SDA_I2C3_SDA_PULLTYPESELECT, PULL_UP);
147 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SDA_I2C3_SDA_PULLUDENABLE, ENABLE);
148 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SDA_I2C3_SDA_MUXMODE, 0U);
149 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_I2C3_SDA = regVal;
151 regVal = 0U;
152 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SCL_I2C3_SCL_WAKEUPENABLE, DISABLE);
153 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SCL_I2C3_SCL_INPUTENABLE, ENABLE);
154 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SCL_I2C3_SCL_PULLTYPESELECT, PULL_UP);
155 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SCL_I2C3_SCL_PULLUDENABLE, ENABLE);
156 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_I2C3_SCL_I2C3_SCL_MUXMODE, 0U);
157 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_I2C3_SCL = regVal;
158 break;
160 case 5:
161 regVal = 0U;
162 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_WAKEUPENABLE, DISABLE);
163 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_INPUTENABLE, ENABLE);
164 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_PULLTYPESELECT, PULL_UP);
165 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_PULLUDENABLE, ENABLE);
166 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_MUXMODE, 0U);
167 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_MODESELECT, MUX_MODE);
168 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_DELAYMODE, 0U);
169 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_MUXMODE, 10U);
170 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR0 = regVal;
172 regVal = 0U;
173 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_WAKEUPENABLE, DISABLE);
174 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_INPUTENABLE, ENABLE);
175 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_PULLTYPESELECT, PULL_UP);
176 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_PULLUDENABLE, ENABLE);
177 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_MUXMODE, 0U);
178 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_MODESELECT, MUX_MODE);
179 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_DELAYMODE, 0U);
180 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_MUXMODE, 10U);
181 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR1 = regVal;
182 break;
184 default:
185 break;
186 }
187 }
189 void PinmuxMmcConfig (Uint32 instNum)
190 {
191 Uint32 regVal = 0U;
193 switch(instNum)
194 {
195 case 1:
196 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CLK_MMC1_CLK_WAKEUPENABLE, DISABLE);
197 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CLK_MMC1_CLK_ACTIVE, 1U);
198 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CLK_MMC1_CLK_PULLTYPESELECT, PULL_DOWN);
199 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CLK_MMC1_CLK_PULLUDENABLE, ENABLE);
200 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CLK_MMC1_CLK_MODESELECT, MUX_MODE);
201 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CLK_MMC1_CLK_DELAYMODE, 0U);
202 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CLK_MMC1_CLK_MUXMODE, 0U);
203 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC1_CLK = regVal;
205 regVal = 0U;
206 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CMD_MMC1_CMD_WAKEUPENABLE, DISABLE);
207 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CMD_MMC1_CMD_ACTIVE, 1U);
208 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CMD_MMC1_CMD_PULLTYPESELECT, PULL_UP);
209 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CMD_MMC1_CMD_PULLUDENABLE, ENABLE);
210 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CMD_MMC1_CMD_MODESELECT, MUX_MODE);
211 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CMD_MMC1_CMD_DELAYMODE, 0U);
212 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_CMD_MMC1_CMD_MUXMODE, 0U);
213 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC1_CMD = regVal;
215 regVal = 0U;
216 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT0_MMC1_DAT0_WAKEUPENABLE, DISABLE);
217 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT0_MMC1_DAT0_ACTIVE, 1U);
218 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT0_MMC1_DAT0_PULLTYPESELECT, PULL_UP);
219 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT0_MMC1_DAT0_PULLUDENABLE, ENABLE);
220 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT0_MMC1_DAT0_MODESELECT, MUX_MODE);
221 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT0_MMC1_DAT0_DELAYMODE, 0U);
222 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT0_MMC1_DAT0_MUXMODE, 0U);
223 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC1_DAT0 = regVal;
225 regVal = 0U;
226 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT1_MMC1_DAT1_WAKEUPENABLE, DISABLE);
227 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT1_MMC1_DAT1_ACTIVE, 1U);
228 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT1_MMC1_DAT1_PULLTYPESELECT, PULL_UP);
229 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT1_MMC1_DAT1_PULLUDENABLE, ENABLE);
230 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT1_MMC1_DAT1_MODESELECT, MUX_MODE);
231 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT1_MMC1_DAT1_DELAYMODE, 0U);
232 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT1_MMC1_DAT1_MUXMODE, 0U);
233 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC1_DAT1 = regVal;
235 regVal = 0U;
236 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT2_MMC1_DAT2_WAKEUPENABLE, DISABLE);
237 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT2_MMC1_DAT2_ACTIVE, 1U);
238 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT2_MMC1_DAT2_PULLTYPESELECT, PULL_UP);
239 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT2_MMC1_DAT2_PULLUDENABLE, ENABLE);
240 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT2_MMC1_DAT2_MODESELECT, MUX_MODE);
241 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT2_MMC1_DAT2_DELAYMODE, 0U);
242 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT2_MMC1_DAT2_MUXMODE, 0U);
243 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC1_DAT2 = regVal;
245 regVal = 0U;
246 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT3_MMC1_DAT3_WAKEUPENABLE, DISABLE);
247 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT3_MMC1_DAT3_ACTIVE, 1U);
248 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT3_MMC1_DAT3_PULLTYPESELECT, PULL_UP);
249 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT3_MMC1_DAT3_PULLUDENABLE, ENABLE);
250 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT3_MMC1_DAT3_MODESELECT, MUX_MODE);
251 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT3_MMC1_DAT3_DELAYMODE, 0U);
252 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_DAT3_MMC1_DAT3_MUXMODE, 0U);
253 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC1_DAT3 = regVal;
255 regVal = 0U;
256 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_SDCD_MMC1_SDCD_WAKEUPENABLE, DISABLE);
257 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_SDCD_MMC1_SDCD_SLEWCONTROL, SLOW_SLEW);
258 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_SDCD_MMC1_SDCD_INPUTENABLE, ENABLE);
259 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_SDCD_MMC1_SDCD_PULLTYPESELECT, PULL_UP);
260 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_SDCD_MMC1_SDCD_PULLUDENABLE, DISABLE);
261 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_SDCD_MMC1_SDCD_MODESELECT, MUX_MODE);
262 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_SDCD_MMC1_SDCD_DELAYMODE, 0U);
263 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC1_SDCD_MMC1_SDCD_MUXMODE, 14U);
264 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC1_SDCD = regVal;
265 break;
267 case 2:
268 regVal = 0U;
269 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A23_GPMC_A23_WAKEUPENABLE, DISABLE);
270 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A23_GPMC_A23_SLEWCONTROL, FAST_SLEW);
271 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A23_GPMC_A23_INPUTENABLE, ENABLE);
272 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A23_GPMC_A23_PULLTYPESELECT, PULL_DOWN);
273 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A23_GPMC_A23_PULLUDENABLE, DISABLE);
274 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A23_GPMC_A23_MODESELECT, MUX_MODE);
275 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A23_GPMC_A23_DELAYMODE, 0U);
276 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A23_GPMC_A23_MUXMODE, 1U);
277 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A23 = regVal;
279 regVal = 0U;
280 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_CS1_GPMC_CS1_WAKEUPENABLE, DISABLE);
281 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_CS1_GPMC_CS1_SLEWCONTROL, FAST_SLEW);
282 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_CS1_GPMC_CS1_INPUTENABLE, ENABLE);
283 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_CS1_GPMC_CS1_PULLTYPESELECT, PULL_UP);
284 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_CS1_GPMC_CS1_PULLUDENABLE, DISABLE);
285 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_CS1_GPMC_CS1_MODESELECT, MUX_MODE);
286 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_CS1_GPMC_CS1_DELAYMODE, 0U);
287 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_CS1_GPMC_CS1_MUXMODE, 1U);
288 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_CS1 = regVal;
290 regVal = 0U;
291 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A24_GPMC_A24_WAKEUPENABLE, DISABLE);
292 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A24_GPMC_A24_SLEWCONTROL, FAST_SLEW);
293 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A24_GPMC_A24_INPUTENABLE, ENABLE);
294 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A24_GPMC_A24_PULLTYPESELECT, PULL_UP);
295 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A24_GPMC_A24_PULLUDENABLE, DISABLE);
296 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A24_GPMC_A24_MODESELECT, MUX_MODE);
297 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A24_GPMC_A24_DELAYMODE, 0U);
298 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A24_GPMC_A24_MUXMODE, 1U);
299 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A24 = regVal;
301 regVal = 0U;
302 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A25_GPMC_A25_WAKEUPENABLE, DISABLE);
303 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A25_GPMC_A25_SLEWCONTROL, FAST_SLEW);
304 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A25_GPMC_A25_INPUTENABLE, ENABLE);
305 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A25_GPMC_A25_PULLTYPESELECT, PULL_UP);
306 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A25_GPMC_A25_PULLUDENABLE, DISABLE);
307 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A25_GPMC_A25_MODESELECT, MUX_MODE);
308 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A25_GPMC_A25_DELAYMODE, 0U);
309 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A25_GPMC_A25_MUXMODE, 1U);
310 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A25 = regVal;
312 regVal = 0U;
313 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A26_GPMC_A26_WAKEUPENABLE, DISABLE);
314 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A26_GPMC_A26_SLEWCONTROL, FAST_SLEW);
315 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A26_GPMC_A26_INPUTENABLE, ENABLE);
316 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A26_GPMC_A26_PULLTYPESELECT, PULL_UP);
317 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A26_GPMC_A26_PULLUDENABLE, DISABLE);
318 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A26_GPMC_A26_MODESELECT, MUX_MODE);
319 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A26_GPMC_A26_DELAYMODE, 0U);
320 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A26_GPMC_A26_MUXMODE, 1U);
321 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A26 = regVal;
323 regVal = 0U;
324 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A27_GPMC_A27_WAKEUPENABLE, DISABLE);
325 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A27_GPMC_A27_SLEWCONTROL, FAST_SLEW);
326 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A27_GPMC_A27_INPUTENABLE, ENABLE);
327 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A27_GPMC_A27_PULLTYPESELECT, PULL_UP);
328 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A27_GPMC_A27_PULLUDENABLE, DISABLE);
329 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A27_GPMC_A27_MODESELECT, MUX_MODE);
330 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A27_GPMC_A27_DELAYMODE, 0U);
331 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A27_GPMC_A27_MUXMODE, 1U);
332 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A27 = regVal;
334 regVal = 0U;
335 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A19_GPMC_A19_WAKEUPENABLE, DISABLE);
336 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A19_GPMC_A19_SLEWCONTROL, FAST_SLEW);
337 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A19_GPMC_A19_INPUTENABLE, ENABLE);
338 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A19_GPMC_A19_PULLTYPESELECT, PULL_UP);
339 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A19_GPMC_A19_PULLUDENABLE, DISABLE);
340 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A19_GPMC_A19_MODESELECT, MUX_MODE);
341 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A19_GPMC_A19_DELAYMODE, 0U);
342 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A19_GPMC_A19_MUXMODE, 1U);
343 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A19 = regVal;
345 regVal = 0U;
346 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A20_GPMC_A20_WAKEUPENABLE, DISABLE);
347 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A20_GPMC_A20_SLEWCONTROL, FAST_SLEW);
348 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A20_GPMC_A20_INPUTENABLE, ENABLE);
349 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A20_GPMC_A20_PULLTYPESELECT, PULL_UP);
350 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A20_GPMC_A20_PULLUDENABLE, DISABLE);
351 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A20_GPMC_A20_MODESELECT, MUX_MODE);
352 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A20_GPMC_A20_DELAYMODE, 0U);
353 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A20_GPMC_A20_MUXMODE, 1U);
354 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A20 = regVal;
356 regVal = 0U;
357 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A21_GPMC_A21_WAKEUPENABLE, DISABLE);
358 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A21_GPMC_A21_SLEWCONTROL, FAST_SLEW);
359 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A21_GPMC_A21_INPUTENABLE, ENABLE);
360 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A21_GPMC_A21_PULLTYPESELECT, PULL_UP);
361 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A21_GPMC_A21_PULLUDENABLE, DISABLE);
362 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A21_GPMC_A21_MODESELECT, MUX_MODE);
363 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A21_GPMC_A21_DELAYMODE, 0U);
364 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A21_GPMC_A21_MUXMODE, 1U);
365 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A21 = regVal;
367 regVal = 0U;
368 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A22_GPMC_A22_WAKEUPENABLE, DISABLE);
369 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A22_GPMC_A22_SLEWCONTROL, FAST_SLEW);
370 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A22_GPMC_A22_INPUTENABLE, ENABLE);
371 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A22_GPMC_A22_PULLTYPESELECT, PULL_UP);
372 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A22_GPMC_A22_PULLUDENABLE, DISABLE);
373 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A22_GPMC_A22_MODESELECT, MUX_MODE);
374 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A22_GPMC_A22_DELAYMODE, 0U);
375 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A22_GPMC_A22_MUXMODE, 1U);
376 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A22 = regVal;
378 regVal = 0U;
379 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VOUT1_FLD_VOUT1_FLD_WAKEUPENABLE, DISABLE);
380 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VOUT1_FLD_VOUT1_FLD_SLEWCONTROL, SLOW_SLEW);
381 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VOUT1_FLD_VOUT1_FLD_INPUTENABLE, DISABLE);
382 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VOUT1_FLD_VOUT1_FLD_PULLTYPESELECT, PULL_UP);
383 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VOUT1_FLD_VOUT1_FLD_PULLUDENABLE, DISABLE);
384 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VOUT1_FLD_VOUT1_FLD_MODESELECT, MUX_MODE);
385 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VOUT1_FLD_VOUT1_FLD_DELAYMODE, 0U);
386 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VOUT1_FLD_VOUT1_FLD_MUXMODE, 15U);
387 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VOUT1_FLD = regVal;
388 break;
390 case 3:
391 regVal = 0U;
392 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_WAKEUPENABLE, DISABLE);
393 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_INPUTENABLE, ENABLE);
394 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_PULLTYPESELECT, PULL_DOWN);
395 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_PULLUDENABLE, ENABLE);
396 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_MODESELECT, MUX_MODE);
397 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_DELAYMODE, 0U);
398 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_MUXMODE, 0U);
399 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_CLK = regVal;
401 regVal = 0U;
402 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_WAKEUPENABLE, DISABLE);
403 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_INPUTENABLE, ENABLE);
404 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_PULLTYPESELECT, PULL_UP);
405 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_PULLUDENABLE, ENABLE);
406 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_MODESELECT, MUX_MODE);
407 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_DELAYMODE, 0U);
408 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_MUXMODE, 0U);
409 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_CMD = regVal;
411 regVal = 0U;
412 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_WAKEUPENABLE, DISABLE);
413 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_INPUTENABLE, ENABLE);
414 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_PULLTYPESELECT, PULL_UP);
415 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_PULLUDENABLE, ENABLE);
416 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_MODESELECT, MUX_MODE);
417 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_DELAYMODE, 0U);
418 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_MUXMODE, 0U);
419 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT0 = regVal;
421 regVal = 0U;
422 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_WAKEUPENABLE, DISABLE);
423 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_INPUTENABLE, ENABLE);
424 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_PULLTYPESELECT, PULL_UP);
425 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_PULLUDENABLE, ENABLE);
426 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_MODESELECT, MUX_MODE);
427 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_DELAYMODE, 0U);
428 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_MUXMODE, 0U);
429 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT1 = regVal;
431 regVal = 0U;
432 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_WAKEUPENABLE, DISABLE);
433 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_INPUTENABLE, ENABLE);
434 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_PULLTYPESELECT, PULL_UP);
435 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_PULLUDENABLE, ENABLE);
436 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_MODESELECT, MUX_MODE);
437 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_DELAYMODE, 0U);
438 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_MUXMODE, 0U);
439 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT2 = regVal;
441 regVal = 0U;
442 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_WAKEUPENABLE, DISABLE);
443 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_INPUTENABLE, ENABLE);
444 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_PULLTYPESELECT, PULL_UP);
445 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_PULLUDENABLE, ENABLE);
446 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_MODESELECT, MUX_MODE);
447 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_DELAYMODE, 0U);
448 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_MUXMODE, 0U);
449 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT3 = regVal;
450 break;
452 default:
453 break;
454 }
455 }
457 void PinmuxUartConfig (instNum)
458 {
459 Uint32 regVal = 0U;
461 switch(instNum)
462 {
464 case 1:
465 regVal = 0U;
466 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_RXD_UART1_RXD_WAKEUPENABLE, DISABLE);
467 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_RXD_UART1_RXD_SLEWCONTROL, SLOW_SLEW);
468 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_RXD_UART1_RXD_INPUTENABLE, ENABLE);
469 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_RXD_UART1_RXD_PULLTYPESELECT, PULL_UP);
470 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_RXD_UART1_RXD_PULLUDENABLE, DISABLE);
471 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_RXD_UART1_RXD_MODESELECT, MUX_MODE);
472 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_RXD_UART1_RXD_DELAYMODE, 0U);
473 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_RXD_UART1_RXD_MUXMODE, 0U);
474 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART1_RXD = regVal;
476 regVal = 0U;
477 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_TXD_UART1_TXD_WAKEUPENABLE, DISABLE);
478 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_TXD_UART1_TXD_SLEWCONTROL, SLOW_SLEW);
479 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_TXD_UART1_TXD_INPUTENABLE, ENABLE);
480 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_TXD_UART1_TXD_PULLTYPESELECT, PULL_UP);
481 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_TXD_UART1_TXD_PULLUDENABLE, DISABLE);
482 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_TXD_UART1_TXD_MODESELECT, MUX_MODE);
483 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_TXD_UART1_TXD_DELAYMODE, 0U);
484 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_TXD_UART1_TXD_MUXMODE, 0U);
485 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART1_TXD = regVal;
486 break;
488 case 3:
489 regVal = 0U;
490 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_WAKEUPENABLE, DISABLE);
491 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_SLEWCONTROL, SLOW_SLEW);
492 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_INPUTENABLE, ENABLE);
493 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_PULLTYPESELECT, PULL_UP);
494 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_PULLUDENABLE, DISABLE);
495 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_MODESELECT, MUX_MODE);
496 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_DELAYMODE, 0U);
497 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_MUXMODE, 1U);
498 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART2_RTSN = regVal;
500 regVal = 0U;
501 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_WAKEUPENABLE, DISABLE);
502 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_SLEWCONTROL, SLOW_SLEW);
503 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_INPUTENABLE, ENABLE);
504 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_PULLTYPESELECT, PULL_UP);
505 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_PULLUDENABLE, DISABLE);
506 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_MODESELECT, MUX_MODE);
507 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_DELAYMODE, 0U);
508 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_MUXMODE, 2U);
509 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART2_CTSN = regVal;
510 break;
512 default:
513 break;
514 }
515 }
517 void PinmuxPruIcssConfig (void)
518 {
519 Uint32 regVal = 0U;
521 #if 0
522 /***************************************************************************************************
523 * pru1 eth 0: Not wired for default IDK
524 ****************************************************************************************************/
526 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D10_VIN2A_D10_WAKEUPENABLE, DISABLE);
527 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D10_VIN2A_D10_SLEWCONTROL, SLOW_SLEW);
528 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D10_VIN2A_D10_INPUTENABLE, ENABLE);
529 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D10_VIN2A_D10_PULLTYPESELECT, PULL_UP);
530 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D10_VIN2A_D10_PULLUDENABLE, ENABLE);
531 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D10_VIN2A_D10_MODESELECT, MUX_MODE);
532 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D10_VIN2A_D10_DELAYMODE, 0U);
533 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D10_VIN2A_D10_MUXMODE,11U);
534 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D10 = regVal;
536 regVal = 0U;
537 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D11_VIN2A_D11_WAKEUPENABLE, DISABLE);
538 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D11_VIN2A_D11_SLEWCONTROL, SLOW_SLEW);
539 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D11_VIN2A_D11_INPUTENABLE, ENABLE);
540 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D11_VIN2A_D11_PULLTYPESELECT, PULL_UP);
541 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D11_VIN2A_D11_PULLUDENABLE, ENABLE);
542 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D11_VIN2A_D11_MODESELECT, MUX_MODE);
543 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D11_VIN2A_D11_DELAYMODE, 0U);
544 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D11_VIN2A_D11_MUXMODE, 11U);
545 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D11 = regVal;
547 regVal = 0U;
548 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_WAKEUPENABLE, DISABLE);
549 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_SLEWCONTROL, SLOW_SLEW);
550 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_INPUTENABLE, ENABLE);
551 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_PULLTYPESELECT, PULL_UP);
552 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_PULLUDENABLE, ENABLE);
553 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_MODESELECT, MUX_MODE);
554 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_DELAYMODE, 0U);
555 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_MUXMODE, 11U);
556 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXC = regVal;
558 regVal = 0U;
559 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_WAKEUPENABLE, DISABLE);
560 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_SLEWCONTROL, SLOW_SLEW);
561 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_INPUTENABLE, DISABLE);
562 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_PULLTYPESELECT, PULL_UP);
563 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_PULLUDENABLE, ENABLE);
564 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_MODESELECT, MUX_MODE);
565 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_DELAYMODE, 0U);
566 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_MUXMODE, 11U);
567 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXD2 = regVal;
569 regVal = 0U;
570 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_WAKEUPENABLE, DISABLE);
571 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_SLEWCONTROL, SLOW_SLEW);
572 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_INPUTENABLE, DISABLE);
573 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_PULLTYPESELECT, PULL_UP);
574 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_PULLUDENABLE, ENABLE);
575 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_MODESELECT, MUX_MODE);
576 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_DELAYMODE, 0U);
577 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_MUXMODE, 11U);
578 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXD0 = regVal;
580 regVal = 0U;
581 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_WAKEUPENABLE, DISABLE);
582 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_SLEWCONTROL, SLOW_SLEW);
583 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_INPUTENABLE, DISABLE);
584 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_PULLTYPESELECT, PULL_UP);
585 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_PULLUDENABLE, ENABLE);
586 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_MODESELECT, MUX_MODE);
587 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_DELAYMODE, 0U);
588 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_MUXMODE, 11U);
589 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXD3 = regVal;
591 regVal = 0U;
592 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_WAKEUPENABLE, DISABLE);
593 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_SLEWCONTROL, SLOW_SLEW);
594 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_INPUTENABLE, DISABLE);
595 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_PULLTYPESELECT, PULL_UP);
596 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_PULLUDENABLE, ENABLE);
597 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_MODESELECT, MUX_MODE);
598 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_DELAYMODE, 0U);
599 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_MUXMODE, 11U);
600 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXCTL = regVal;
602 regVal = 0U;
603 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_WAKEUPENABLE, DISABLE);
604 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_SLEWCONTROL, SLOW_SLEW);
605 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_INPUTENABLE, ENABLE);
606 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_PULLTYPESELECT, PULL_UP);
607 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_PULLUDENABLE, ENABLE);
608 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_MODESELECT, MUX_MODE);
609 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_DELAYMODE, 0U);
610 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_MUXMODE, 11U);
611 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART3_TXD = regVal;
613 regVal = 0U;
614 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_WAKEUPENABLE, DISABLE);
615 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_SLEWCONTROL, SLOW_SLEW);
616 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_INPUTENABLE, ENABLE);
617 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_PULLTYPESELECT, PULL_UP);
618 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_PULLUDENABLE, ENABLE);
619 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_MODESELECT, MUX_MODE);
620 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_DELAYMODE, 0U);
621 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_MUXMODE, 11U);
622 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART3_RXD = regVal;
624 regVal = 0U;
625 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_WAKEUPENABLE, DISABLE);
626 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_SLEWCONTROL, SLOW_SLEW);
627 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_INPUTENABLE, ENABLE);
628 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_PULLTYPESELECT, PULL_UP);
629 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_PULLUDENABLE, ENABLE);
630 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_MODESELECT, MUX_MODE);
631 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_DELAYMODE, 0U);
632 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_MUXMODE, 11U);
633 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXD2 = regVal;
635 regVal = 0U;
636 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_WAKEUPENABLE, DISABLE);
637 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_SLEWCONTROL, SLOW_SLEW);
638 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_INPUTENABLE, ENABLE);
639 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_PULLTYPESELECT, PULL_UP);
640 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_PULLUDENABLE, ENABLE);
641 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_MODESELECT, MUX_MODE);
642 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_DELAYMODE, 0U);
643 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_MUXMODE, 11U);
644 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXD0 = regVal;
646 regVal = 0U;
647 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_WAKEUPENABLE, DISABLE);
648 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_SLEWCONTROL, SLOW_SLEW);
649 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_INPUTENABLE, ENABLE);
650 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_PULLTYPESELECT, PULL_UP);
651 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_PULLUDENABLE, ENABLE);
652 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_MODESELECT, MUX_MODE);
653 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_DELAYMODE, 0U);
654 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_MUXMODE, 11U);
655 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXD1 = regVal;
657 regVal = 0U;
658 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_WAKEUPENABLE, DISABLE);
659 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_SLEWCONTROL, SLOW_SLEW);
660 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_INPUTENABLE, ENABLE);
661 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_PULLTYPESELECT, PULL_UP);
662 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_PULLUDENABLE, ENABLE);
663 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_MODESELECT, MUX_MODE);
664 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_DELAYMODE, 0U);
665 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_MUXMODE, 11U);
666 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXCTL = regVal;
668 regVal = 0U;
669 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_WAKEUPENABLE, DISABLE);
670 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_SLEWCONTROL, SLOW_SLEW);
671 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_INPUTENABLE, ENABLE);
672 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_PULLTYPESELECT, PULL_UP);
673 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_PULLUDENABLE, ENABLE);
674 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_MODESELECT, MUX_MODE);
675 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_DELAYMODE, 0U);
676 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_MUXMODE, 11U);
677 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXC = regVal;
679 regVal = 0U;
680 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_WAKEUPENABLE, DISABLE);
681 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_SLEWCONTROL, SLOW_SLEW);
682 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_INPUTENABLE, ENABLE);
683 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_PULLTYPESELECT, PULL_UP);
684 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_PULLUDENABLE, ENABLE);
685 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_MODESELECT, MUX_MODE);
686 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_DELAYMODE, 0U);
687 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_MUXMODE, 11U);
688 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXD3 = regVal;
690 regVal = 0U;
691 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_MCLK_MDIO_MCLK_MUXMODE, 0xFU);
692 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MDIO_MCLK = regVal;
694 regVal = 0U;
695 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_WAKEUPENABLE, DISABLE);
696 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_SLEWCONTROL, SLOW_SLEW);
697 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_INPUTENABLE, ENABLE);
698 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_PULLTYPESELECT, PULL_UP);
699 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_PULLUDENABLE, ENABLE);
700 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_MODESELECT, MUX_MODE);
701 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_DELAYMODE, 0U);
702 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_MUXMODE, 0xffU);
703 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MDIO_D = regVal;
706 /***************************************************************************************************
707 * pru1 eth 1 Not wired for default IDK
708 ****************************************************************************************************/
709 regVal = 0U;
710 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D6_VIN2A_D6_WAKEUPENABLE, DISABLE);
711 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D6_VIN2A_D6_SLEWCONTROL, SLOW_SLEW);
712 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D6_VIN2A_D6_INPUTENABLE, ENABLE);
713 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D6_VIN2A_D6_PULLTYPESELECT, PULL_UP);
714 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D6_VIN2A_D6_PULLUDENABLE, ENABLE);
715 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D6_VIN2A_D6_MODESELECT, MUX_MODE);
716 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D6_VIN2A_D6_DELAYMODE, 0U);
717 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D6_VIN2A_D6_MUXMODE, 11U);
718 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D6 = regVal;
721 regVal = 0U;
722 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D7_VIN2A_D7_WAKEUPENABLE, DISABLE);
723 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D7_VIN2A_D7_SLEWCONTROL, SLOW_SLEW);
724 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D7_VIN2A_D7_INPUTENABLE, DISABLE);
725 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D7_VIN2A_D7_PULLTYPESELECT, PULL_UP);
726 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D7_VIN2A_D7_PULLUDENABLE, ENABLE);
727 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D7_VIN2A_D7_MODESELECT, MUX_MODE);
728 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D7_VIN2A_D7_DELAYMODE, 0U);
729 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D7_VIN2A_D7_MUXMODE, 11U);
730 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D7 = regVal;
733 regVal = 0U;
734 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_WAKEUPENABLE, DISABLE);
735 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_SLEWCONTROL, SLOW_SLEW);
736 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_INPUTENABLE, DISABLE);
737 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_PULLTYPESELECT, PULL_UP);
738 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_PULLUDENABLE, ENABLE);
739 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_MODESELECT, MUX_MODE);
740 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_DELAYMODE, 0U);
741 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_MUXMODE, 11U);
742 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D13 = regVal;
745 regVal = 0U;
746 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_WAKEUPENABLE, DISABLE);
747 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_SLEWCONTROL, SLOW_SLEW);
748 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_INPUTENABLE, DISABLE);
749 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_PULLTYPESELECT, PULL_UP);
750 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_PULLUDENABLE, ENABLE);
751 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_MODESELECT, MUX_MODE);
752 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_DELAYMODE, 0U);
753 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_MUXMODE, 11U);
754 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D12 = regVal;
756 regVal = 0U;
757 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D9_VIN2A_D9_WAKEUPENABLE, DISABLE);
758 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D9_VIN2A_D9_SLEWCONTROL, SLOW_SLEW);
759 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D9_VIN2A_D9_INPUTENABLE, DISABLE);
760 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D9_VIN2A_D9_PULLTYPESELECT, PULL_UP);
761 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D9_VIN2A_D9_PULLUDENABLE, ENABLE);
762 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D9_VIN2A_D9_MODESELECT, MUX_MODE);
763 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D9_VIN2A_D9_DELAYMODE, 0U);
764 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D9_VIN2A_D9_MUXMODE, 11U);
765 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D9 = regVal;
768 regVal = 0U;
769 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D8_VIN2A_D8_WAKEUPENABLE, DISABLE);
770 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D8_VIN2A_D8_SLEWCONTROL, SLOW_SLEW);
771 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D8_VIN2A_D8_INPUTENABLE, DISABLE);
772 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D8_VIN2A_D8_PULLTYPESELECT, PULL_UP);
773 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D8_VIN2A_D8_PULLUDENABLE, ENABLE);
774 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D8_VIN2A_D8_MODESELECT, MUX_MODE);
775 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D8_VIN2A_D8_DELAYMODE, 0U);
776 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D8_VIN2A_D8_MUXMODE, 11U);
777 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D8 = regVal;
779 regVal = 0U;
780 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_WAKEUPENABLE, DISABLE);
781 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_SLEWCONTROL, SLOW_SLEW);
782 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_INPUTENABLE, ENABLE);
783 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_PULLTYPESELECT, PULL_UP);
784 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_PULLUDENABLE, ENABLE);
785 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_MODESELECT, MUX_MODE);
786 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_DELAYMODE, 0U);
787 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_MUXMODE, 11U);
788 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D14 = regVal;
790 regVal = 0U;
791 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_WAKEUPENABLE, DISABLE);
792 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_SLEWCONTROL, SLOW_SLEW);
793 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_INPUTENABLE, ENABLE);
794 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_PULLTYPESELECT, PULL_UP);
795 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_PULLUDENABLE, ENABLE);
796 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_MODESELECT, MUX_MODE);
797 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_DELAYMODE, 0U);
798 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_MUXMODE, 11U);
799 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D15 = regVal;
802 regVal = 0U;
803 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_WAKEUPENABLE, DISABLE);
804 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_SLEWCONTROL, SLOW_SLEW);
805 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_INPUTENABLE, ENABLE);
806 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_PULLTYPESELECT, PULL_UP);
807 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_PULLUDENABLE, ENABLE);
808 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_MODESELECT, MUX_MODE);
809 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_DELAYMODE, 0U);
810 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_MUXMODE, 11U);
811 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D20 = regVal;
813 regVal = 0U;
814 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_WAKEUPENABLE, DISABLE);
815 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_SLEWCONTROL, SLOW_SLEW);
816 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_INPUTENABLE, ENABLE);
817 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_PULLTYPESELECT, PULL_UP);
818 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_PULLUDENABLE, ENABLE);
819 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_MODESELECT, MUX_MODE);
820 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_DELAYMODE, 0U);
821 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_MUXMODE, 11U);
822 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D19 = regVal;
825 regVal = 0U;
826 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_WAKEUPENABLE, DISABLE);
827 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_SLEWCONTROL, SLOW_SLEW);
828 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_INPUTENABLE, ENABLE);
829 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_PULLTYPESELECT, PULL_UP);
830 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_PULLUDENABLE, ENABLE);
831 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_MODESELECT, MUX_MODE);
832 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_DELAYMODE, 0U);
833 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_MUXMODE, 11U);
834 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D18 = regVal;
836 regVal = 0U;
837 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_WAKEUPENABLE, DISABLE);
838 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_SLEWCONTROL, SLOW_SLEW);
839 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_INPUTENABLE, ENABLE);
840 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_PULLTYPESELECT, PULL_UP);
841 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_PULLUDENABLE, ENABLE);
842 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_MODESELECT, MUX_MODE);
843 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_DELAYMODE, 0U);
844 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_MUXMODE, 11U);
845 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D17 = regVal;
847 regVal = 0U;
848 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_WAKEUPENABLE, DISABLE);
849 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_SLEWCONTROL, SLOW_SLEW);
850 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_INPUTENABLE, ENABLE);
851 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_PULLTYPESELECT, PULL_UP);
852 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_PULLUDENABLE, ENABLE);
853 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_MODESELECT, MUX_MODE);
854 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_DELAYMODE, 0U);
855 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_MUXMODE, 11U);
856 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D16 = regVal;
859 regVal = 0U;
860 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_WAKEUPENABLE, DISABLE);
861 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_SLEWCONTROL, SLOW_SLEW);
862 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_INPUTENABLE, ENABLE);
863 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_PULLTYPESELECT, PULL_UP);
864 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_PULLUDENABLE, ENABLE);
865 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_MODESELECT, MUX_MODE);
866 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_DELAYMODE, 0U);
867 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_MUXMODE, 11U);
868 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D23 = regVal;
870 regVal = 0U;
871 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D22_VIN2A_D22_MUXMODE, 0xFU);
872 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D22 = regVal;
874 regVal = 0U;
875 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_WAKEUPENABLE, DISABLE);
876 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_SLEWCONTROL, SLOW_SLEW);
877 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_INPUTENABLE, ENABLE);
878 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_PULLTYPESELECT, PULL_UP);
879 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_PULLUDENABLE, ENABLE);
880 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_MODESELECT, MUX_MODE);
881 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_DELAYMODE, 0U);
882 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_MUXMODE, 0xff);
883 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D21 = regVal;
884 #endif
886 /***************************************************************************************************
887 * pru2 eth 0
888 ****************************************************************************************************/
889 regVal = 0U;
890 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_ACLKX_MCASP1_ACLKX_WAKEUPENABLE, DISABLE);
891 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_ACLKX_MCASP1_ACLKX_SLEWCONTROL, SLOW_SLEW);
892 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_ACLKX_MCASP1_ACLKX_INPUTENABLE, ENABLE);
893 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_ACLKX_MCASP1_ACLKX_PULLTYPESELECT, PULL_UP);
894 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_ACLKX_MCASP1_ACLKX_PULLUDENABLE, ENABLE);
895 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_ACLKX_MCASP1_ACLKX_MODESELECT, MUX_MODE);
896 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_ACLKX_MCASP1_ACLKX_DELAYMODE, 0U);
897 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_ACLKX_MCASP1_ACLKX_MUXMODE, 11U);
898 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_ACLKX = regVal;
900 regVal = 0U;
901 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_FSX_MCASP1_FSX_WAKEUPENABLE, DISABLE);
902 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_FSX_MCASP1_FSX_SLEWCONTROL, SLOW_SLEW);
903 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_FSX_MCASP1_FSX_INPUTENABLE, ENABLE);
904 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_FSX_MCASP1_FSX_PULLTYPESELECT, PULL_UP);
905 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_FSX_MCASP1_FSX_PULLUDENABLE, ENABLE);
906 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_FSX_MCASP1_FSX_MODESELECT, MUX_MODE);
907 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_FSX_MCASP1_FSX_DELAYMODE, 0U);
908 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_FSX_MCASP1_FSX_MUXMODE, 11U);
909 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_FSX = regVal;
912 regVal = 0U;
913 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_WAKEUPENABLE, DISABLE);
914 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_SLEWCONTROL, SLOW_SLEW);
915 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_INPUTENABLE, ENABLE);
916 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_PULLTYPESELECT, PULL_UP);
917 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_PULLUDENABLE, ENABLE);
918 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_MODESELECT, MUX_MODE);
919 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_DELAYMODE, 0U);
920 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR1_MCASP1_AXR1_MUXMODE, 11U);
921 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR1 = regVal;
924 regVal = 0U;
925 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR8_MCASP1_AXR8_WAKEUPENABLE, DISABLE);
926 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR8_MCASP1_AXR8_SLEWCONTROL, SLOW_SLEW);
927 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR8_MCASP1_AXR8_INPUTENABLE, DISABLE);
928 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR8_MCASP1_AXR8_PULLTYPESELECT, PULL_UP);
929 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR8_MCASP1_AXR8_PULLUDENABLE, ENABLE);
930 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR8_MCASP1_AXR8_MODESELECT, MUX_MODE);
931 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR8_MCASP1_AXR8_DELAYMODE, 0U);
932 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR8_MCASP1_AXR8_MUXMODE, 11U);
933 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR8 = regVal;
935 regVal = 0U;
936 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR12_MCASP1_AXR12_WAKEUPENABLE, DISABLE);
937 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR12_MCASP1_AXR12_SLEWCONTROL, SLOW_SLEW);
938 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR12_MCASP1_AXR12_INPUTENABLE, DISABLE);
939 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR12_MCASP1_AXR12_PULLTYPESELECT, PULL_UP);
940 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR12_MCASP1_AXR12_PULLUDENABLE, ENABLE);
941 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR12_MCASP1_AXR12_MODESELECT, MUX_MODE);
942 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR12_MCASP1_AXR12_DELAYMODE, 0U);
943 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR12_MCASP1_AXR12_MUXMODE, 11U);
944 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR12 = regVal;
947 regVal = 0U;
948 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR11_MCASP1_AXR11_WAKEUPENABLE, DISABLE);
949 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR11_MCASP1_AXR11_SLEWCONTROL, SLOW_SLEW);
950 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR11_MCASP1_AXR11_INPUTENABLE, DISABLE);
951 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR11_MCASP1_AXR11_PULLTYPESELECT, PULL_UP);
952 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR11_MCASP1_AXR11_PULLUDENABLE, ENABLE);
953 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR11_MCASP1_AXR11_MODESELECT, MUX_MODE);
954 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR11_MCASP1_AXR11_DELAYMODE, 0U);
955 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR11_MCASP1_AXR11_MUXMODE, 11U);
956 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR11 = regVal;
958 regVal = 0U;
959 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR10_MCASP1_AXR10_WAKEUPENABLE, DISABLE);
960 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR10_MCASP1_AXR10_SLEWCONTROL, SLOW_SLEW);
961 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR10_MCASP1_AXR10_INPUTENABLE, DISABLE);
962 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR10_MCASP1_AXR10_PULLTYPESELECT, PULL_UP);
963 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR10_MCASP1_AXR10_PULLUDENABLE, ENABLE);
964 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR10_MCASP1_AXR10_MODESELECT, MUX_MODE);
965 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR10_MCASP1_AXR10_DELAYMODE, 0U);
966 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR10_MCASP1_AXR10_MUXMODE, 11U);
967 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR10 = regVal;
969 regVal = 0U;
970 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR9_MCASP1_AXR9_WAKEUPENABLE, DISABLE);
971 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR9_MCASP1_AXR9_SLEWCONTROL, SLOW_SLEW);
972 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR9_MCASP1_AXR9_INPUTENABLE, DISABLE);
973 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR9_MCASP1_AXR9_PULLTYPESELECT, PULL_UP);
974 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR9_MCASP1_AXR9_PULLUDENABLE, ENABLE);
975 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR9_MCASP1_AXR9_MODESELECT, MUX_MODE);
976 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR9_MCASP1_AXR9_DELAYMODE, 0U);
977 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR9_MCASP1_AXR9_MUXMODE, 11U);
978 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR9 = regVal;
981 regVal = 0U;
982 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR13_MCASP1_AXR13_WAKEUPENABLE, DISABLE);
983 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR13_MCASP1_AXR13_SLEWCONTROL, SLOW_SLEW);
984 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR13_MCASP1_AXR13_INPUTENABLE, ENABLE);
985 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR13_MCASP1_AXR13_PULLTYPESELECT, PULL_UP);
986 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR13_MCASP1_AXR13_PULLUDENABLE, ENABLE);
987 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR13_MCASP1_AXR13_MODESELECT, MUX_MODE);
988 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR13_MCASP1_AXR13_DELAYMODE, 0U);
989 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR13_MCASP1_AXR13_MUXMODE, 11U);
990 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR13 = regVal;
992 regVal = 0U;
993 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR14_MCASP1_AXR14_WAKEUPENABLE, DISABLE);
994 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR14_MCASP1_AXR14_SLEWCONTROL, SLOW_SLEW);
995 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR14_MCASP1_AXR14_INPUTENABLE, ENABLE);
996 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR14_MCASP1_AXR14_PULLTYPESELECT, PULL_UP);
997 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR14_MCASP1_AXR14_PULLUDENABLE, ENABLE);
998 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR14_MCASP1_AXR14_MODESELECT, MUX_MODE);
999 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR14_MCASP1_AXR14_DELAYMODE, 0U);
1000 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR14_MCASP1_AXR14_MUXMODE, 11U);
1001 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR14 = regVal;
1003 regVal = 0U;
1004 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_WAKEUPENABLE, DISABLE);
1005 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_SLEWCONTROL, SLOW_SLEW);
1006 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_INPUTENABLE, ENABLE);
1007 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_PULLTYPESELECT, PULL_UP);
1008 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_PULLUDENABLE, ENABLE);
1009 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_MODESELECT, MUX_MODE);
1010 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_DELAYMODE, 0U);
1011 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0_MCASP1_AXR0_MUXMODE, 11U);
1012 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR0 = regVal;
1014 regVal = 0U;
1015 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR2_MCASP2_AXR2_WAKEUPENABLE, DISABLE);
1016 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR2_MCASP2_AXR2_SLEWCONTROL, SLOW_SLEW);
1017 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR2_MCASP2_AXR2_INPUTENABLE, ENABLE);
1018 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR2_MCASP2_AXR2_PULLTYPESELECT, PULL_UP);
1019 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR2_MCASP2_AXR2_PULLUDENABLE, ENABLE);
1020 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR2_MCASP2_AXR2_MODESELECT, MUX_MODE);
1021 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR2_MCASP2_AXR2_DELAYMODE, 0U);
1022 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR2_MCASP2_AXR2_MUXMODE, 11U);
1023 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP2_AXR2 = regVal;
1025 regVal = 0U;
1026 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX_MCASP2_FSX_WAKEUPENABLE, DISABLE);
1027 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX_MCASP2_FSX_SLEWCONTROL, SLOW_SLEW);
1028 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX_MCASP2_FSX_INPUTENABLE, ENABLE);
1029 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX_MCASP2_FSX_PULLTYPESELECT, PULL_UP);
1030 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX_MCASP2_FSX_PULLUDENABLE, ENABLE);
1031 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX_MCASP2_FSX_MODESELECT, MUX_MODE);
1032 CSL_FINS(regVal,CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX_MCASP2_FSX_DELAYMODE, 0U);
1033 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_FSX_MCASP2_FSX_MUXMODE, 11U);
1034 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP2_FSX = regVal;
1038 regVal = 0U;
1039 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_WAKEUPENABLE, DISABLE);
1040 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_SLEWCONTROL, SLOW_SLEW);
1041 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_INPUTENABLE, ENABLE);
1042 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_PULLTYPESELECT, PULL_UP);
1043 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_PULLUDENABLE, ENABLE);
1044 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_MODESELECT, MUX_MODE);
1045 CSL_FINS(regVal,CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_DELAYMODE, 0U);
1046 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_ACLKX_MCASP2_ACLKX_MUXMODE, 11U);
1047 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP2_ACLKX = regVal;
1050 regVal = 0U;
1051 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_WAKEUPENABLE, DISABLE);
1052 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_SLEWCONTROL, SLOW_SLEW);
1053 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_INPUTENABLE, ENABLE);
1054 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_PULLTYPESELECT, PULL_UP);
1055 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_PULLUDENABLE, ENABLE);
1056 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_MODESELECT, MUX_MODE);
1057 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_DELAYMODE, 0U);
1058 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR15_MCASP1_AXR15_MUXMODE, 11U);
1059 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR15 = regVal;
1063 regVal = 0U;
1064 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_WAKEUPENABLE, DISABLE);
1065 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_SLEWCONTROL, SLOW_SLEW);
1066 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_INPUTENABLE, ENABLE);
1067 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_PULLTYPESELECT, PULL_UP);
1068 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_PULLUDENABLE, ENABLE);
1069 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_MODESELECT, MUX_MODE);
1070 CSL_FINS(regVal,CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_DELAYMODE, 0U);
1071 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_MUXMODE, 11U);
1072 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP3_ACLKX = regVal;
1074 regVal = 0U;
1076 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_FSX_MCASP3_FSX_MUXMODE, 0xFU);
1077 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP3_FSX = regVal;
1079 regVal = 0U;
1080 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR3_MCASP1_AXR3_MUXMODE, 0xFU);
1081 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR3 = regVal;
1084 /***************************************************************************************************
1085 * pru2 eth 1
1086 ****************************************************************************************************/
1087 regVal = 0U;
1088 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_10_GPIO6_10_WAKEUPENABLE, DISABLE);
1089 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_10_GPIO6_10_SLEWCONTROL, SLOW_SLEW);
1090 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_10_GPIO6_10_INPUTENABLE, ENABLE);
1091 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_10_GPIO6_10_PULLTYPESELECT, PULL_UP);
1092 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_10_GPIO6_10_PULLUDENABLE, ENABLE);
1093 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_10_GPIO6_10_MODESELECT, MUX_MODE);
1094 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_10_GPIO6_10_DELAYMODE, 0U);
1095 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_10_GPIO6_10_MUXMODE, 11U);
1096 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPIO6_10 = regVal;
1098 regVal = 0U;
1099 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_11_GPIO6_11_WAKEUPENABLE, DISABLE);
1100 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_11_GPIO6_11_SLEWCONTROL, SLOW_SLEW);
1101 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_11_GPIO6_11_INPUTENABLE, DISABLE);
1102 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_11_GPIO6_11_PULLTYPESELECT, PULL_UP);
1103 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_11_GPIO6_11_PULLUDENABLE, ENABLE);
1104 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_11_GPIO6_11_MODESELECT, MUX_MODE);
1105 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_11_GPIO6_11_DELAYMODE, 0U);
1106 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPIO6_11_GPIO6_11_MUXMODE, 11U);
1107 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPIO6_11 = regVal;
1110 regVal = 0U;
1111 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_WAKEUPENABLE, DISABLE);
1112 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_SLEWCONTROL, SLOW_SLEW);
1113 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_INPUTENABLE, DISABLE);
1114 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_PULLTYPESELECT, PULL_UP);
1115 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_PULLUDENABLE, ENABLE);
1116 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_MODESELECT, MUX_MODE);
1117 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_DELAYMODE, 0U);
1118 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT1_MMC3_DAT1_MUXMODE, 11U);
1119 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT1 = regVal;
1121 regVal = 0U;
1122 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_WAKEUPENABLE, DISABLE);
1123 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_SLEWCONTROL, SLOW_SLEW);
1124 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_INPUTENABLE, DISABLE);
1125 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_PULLTYPESELECT, PULL_UP);
1126 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_PULLUDENABLE, ENABLE);
1127 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_MODESELECT, MUX_MODE);
1128 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_DELAYMODE, 0U);
1129 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT0_MMC3_DAT0_MUXMODE, 11U);
1130 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT0 = regVal;
1132 regVal = 0U;
1133 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_WAKEUPENABLE, DISABLE);
1134 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_SLEWCONTROL, SLOW_SLEW);
1135 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_INPUTENABLE, DISABLE);
1136 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_PULLTYPESELECT, PULL_UP);
1137 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_PULLUDENABLE, ENABLE);
1138 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_MODESELECT, MUX_MODE);
1139 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_DELAYMODE, 0U);
1140 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CMD_MMC3_CMD_MUXMODE, 11U);
1141 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_CMD = regVal;
1144 regVal = 0U;
1145 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_WAKEUPENABLE, DISABLE);
1146 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_SLEWCONTROL, SLOW_SLEW);
1147 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_INPUTENABLE, DISABLE);
1148 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_PULLTYPESELECT, PULL_UP);
1149 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_PULLUDENABLE, ENABLE);
1150 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_MODESELECT, MUX_MODE);
1151 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_DELAYMODE, 0U);
1152 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_CLK_MMC3_CLK_MUXMODE, 11U);
1153 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_CLK = regVal;
1156 regVal = 0U;
1157 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_WAKEUPENABLE, DISABLE);
1158 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_SLEWCONTROL, SLOW_SLEW);
1159 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_INPUTENABLE, ENABLE);
1160 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_PULLTYPESELECT, PULL_UP);
1161 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_PULLUDENABLE, ENABLE);
1162 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_MODESELECT, MUX_MODE);
1163 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_DELAYMODE, 0U);
1164 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT2_MMC3_DAT2_MUXMODE, 11U);
1165 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT2 = regVal;
1167 regVal = 0U;
1168 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_WAKEUPENABLE, DISABLE);
1169 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_SLEWCONTROL, SLOW_SLEW);
1170 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_INPUTENABLE, ENABLE);
1171 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_PULLTYPESELECT, PULL_UP);
1172 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_PULLUDENABLE, ENABLE);
1173 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_MODESELECT, MUX_MODE);
1174 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_DELAYMODE, 0U);
1175 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT3_MMC3_DAT3_MUXMODE, 11U);
1176 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT3 = regVal;
1178 regVal = 0U;
1179 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_WAKEUPENABLE, DISABLE);
1180 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_SLEWCONTROL, SLOW_SLEW);
1181 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_INPUTENABLE, ENABLE);
1182 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_PULLTYPESELECT, PULL_UP);
1183 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_PULLUDENABLE, ENABLE);
1184 CSL_FINST(regVal,CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_MODESELECT, MUX_MODE);
1185 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_DELAYMODE, 0U);
1186 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_MUXMODE, 11U);
1187 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP3_AXR0 = regVal;
1189 regVal = 0U;
1190 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT7_MMC3_DAT7_WAKEUPENABLE, DISABLE);
1191 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT7_MMC3_DAT7_SLEWCONTROL, SLOW_SLEW);
1192 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT7_MMC3_DAT7_INPUTENABLE, ENABLE);
1193 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT7_MMC3_DAT7_PULLTYPESELECT, PULL_UP);
1194 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT7_MMC3_DAT7_PULLUDENABLE, ENABLE);
1195 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT7_MMC3_DAT7_MODESELECT, MUX_MODE);
1196 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT7_MMC3_DAT7_DELAYMODE, 0U);
1197 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT7_MMC3_DAT7_MUXMODE, 11U);
1198 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT7 = regVal;
1200 regVal = 0U;
1201 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT6_MMC3_DAT6_WAKEUPENABLE, DISABLE);
1202 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT6_MMC3_DAT6_SLEWCONTROL, SLOW_SLEW);
1203 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT6_MMC3_DAT6_INPUTENABLE, ENABLE);
1204 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT6_MMC3_DAT6_PULLTYPESELECT, PULL_UP);
1205 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT6_MMC3_DAT6_PULLUDENABLE, ENABLE);
1206 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT6_MMC3_DAT6_MODESELECT, MUX_MODE);
1207 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT6_MMC3_DAT6_DELAYMODE, 0U);
1208 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT6_MMC3_DAT6_MUXMODE, 11U);
1209 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT6 = regVal;
1212 regVal = 0U;
1213 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT5_MMC3_DAT5_WAKEUPENABLE, DISABLE);
1214 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT5_MMC3_DAT5_SLEWCONTROL, SLOW_SLEW);
1215 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT5_MMC3_DAT5_INPUTENABLE, ENABLE);
1216 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT5_MMC3_DAT5_PULLTYPESELECT, PULL_UP);
1217 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT5_MMC3_DAT5_PULLUDENABLE, ENABLE);
1218 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT5_MMC3_DAT5_MODESELECT, MUX_MODE);
1219 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT5_MMC3_DAT5_DELAYMODE, 0U);
1220 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT5_MMC3_DAT5_MUXMODE, 11U);
1221 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT5 = regVal;
1223 regVal = 0U;
1224 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT4_MMC3_DAT4_WAKEUPENABLE, DISABLE);
1225 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT4_MMC3_DAT4_SLEWCONTROL, SLOW_SLEW);
1226 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT4_MMC3_DAT4_INPUTENABLE, ENABLE);
1227 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT4_MMC3_DAT4_PULLTYPESELECT, PULL_UP);
1228 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT4_MMC3_DAT4_PULLUDENABLE, ENABLE);
1229 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT4_MMC3_DAT4_MODESELECT, MUX_MODE);
1230 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT4_MMC3_DAT4_DELAYMODE, 0U);
1231 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MMC3_DAT4_MMC3_DAT4_MUXMODE, 11U);
1232 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MMC3_DAT4 = regVal;
1235 regVal = 0U;
1236 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK1_XREF_CLK1_WAKEUPENABLE, DISABLE);
1237 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK1_XREF_CLK1_SLEWCONTROL, SLOW_SLEW);
1238 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK1_XREF_CLK1_INPUTENABLE, ENABLE);
1239 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK1_XREF_CLK1_PULLTYPESELECT, PULL_UP);
1240 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK1_XREF_CLK1_PULLUDENABLE, ENABLE);
1241 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK1_XREF_CLK1_MODESELECT, MUX_MODE);
1242 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK1_XREF_CLK1_DELAYMODE, 0U);
1243 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK1_XREF_CLK1_MUXMODE, 11U);
1244 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_XREF_CLK1 = regVal;
1246 regVal = 0U;
1247 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_MUXMODE, 0xFU);
1248 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_XREF_CLK0 = regVal;
1251 regVal = 0U;
1252 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR1_MCASP3_AXR1_MUXMODE, 0xFU);
1253 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP3_AXR1 = regVal;
1255 }
1256 void PinmuxCpswConfig (void)
1257 {
1258 Uint32 regVal = 0U;
1260 regVal = 0U;
1261 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_MCLK_MDIO_MCLK_WAKEUPENABLE, DISABLE);
1262 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_MCLK_MDIO_MCLK_SLEWCONTROL, SLOW_SLEW);
1263 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_MCLK_MDIO_MCLK_INPUTENABLE, DISABLE);
1264 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_MCLK_MDIO_MCLK_PULLTYPESELECT, PULL_UP);
1265 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_MCLK_MDIO_MCLK_PULLUDENABLE, ENABLE);
1266 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_MCLK_MDIO_MCLK_MODESELECT, MUX_MODE);
1267 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_MCLK_MDIO_MCLK_DELAYMODE, 0U);
1268 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_MCLK_MDIO_MCLK_MUXMODE, 0U);
1269 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MDIO_MCLK = regVal;
1271 regVal = 0U;
1272 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_WAKEUPENABLE, DISABLE);
1273 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_SLEWCONTROL, SLOW_SLEW);
1274 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_INPUTENABLE, ENABLE);
1275 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_PULLTYPESELECT, PULL_UP);
1276 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_PULLUDENABLE, ENABLE);
1277 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_MODESELECT, MUX_MODE);
1278 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_DELAYMODE, 0U);
1279 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MDIO_D_MDIO_D_MUXMODE, 0U);
1280 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MDIO_D = regVal;
1282 regVal = 0U;
1283 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_WAKEUPENABLE, DISABLE);
1284 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_SLEWCONTROL, SLOW_SLEW);
1285 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_INPUTENABLE, DISABLE);
1286 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_PULLTYPESELECT, PULL_DOWN);
1287 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_PULLUDENABLE, ENABLE);
1288 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_MODESELECT, MUX_MODE);
1289 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_DELAYMODE, 0U);
1290 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXC_RGMII0_TXC_MUXMODE, 0U);
1291 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXC = regVal;
1293 regVal = 0U;
1294 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_WAKEUPENABLE, DISABLE);
1295 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_SLEWCONTROL, SLOW_SLEW);
1296 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_INPUTENABLE, DISABLE);
1297 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_PULLTYPESELECT, PULL_DOWN);
1298 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_PULLUDENABLE, ENABLE);
1299 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_MODESELECT, MUX_MODE);
1300 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_DELAYMODE, 0U);
1301 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXCTL_RGMII0_TXCTL_MUXMODE, 0U);
1302 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXCTL = regVal;
1304 regVal = 0U;
1305 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_WAKEUPENABLE, DISABLE);
1306 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_SLEWCONTROL, SLOW_SLEW);
1307 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_INPUTENABLE, DISABLE);
1308 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_PULLTYPESELECT, PULL_DOWN);
1309 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_PULLUDENABLE, ENABLE);
1310 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_MODESELECT, MUX_MODE);
1311 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_DELAYMODE, 0U);
1312 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD0_RGMII0_TXD0_MUXMODE, 0U);
1313 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXD0 = regVal;
1315 regVal = 0U;
1316 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_WAKEUPENABLE, DISABLE);
1317 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_SLEWCONTROL, SLOW_SLEW);
1318 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_INPUTENABLE, DISABLE);
1319 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_PULLTYPESELECT, PULL_DOWN);
1320 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_PULLUDENABLE, ENABLE);
1321 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_MODESELECT, MUX_MODE);
1322 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_DELAYMODE, 0U);
1323 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD1_RGMII0_TXD1_MUXMODE, 0U);
1324 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXD1 = regVal;
1326 regVal = 0U;
1327 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_WAKEUPENABLE, DISABLE);
1328 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_SLEWCONTROL, SLOW_SLEW);
1329 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_INPUTENABLE, DISABLE);
1330 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_PULLTYPESELECT, PULL_DOWN);
1331 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_PULLUDENABLE, ENABLE);
1332 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_MODESELECT, MUX_MODE);
1333 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_DELAYMODE, 0U);
1334 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD2_RGMII0_TXD2_MUXMODE, 0U);
1335 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXD2 = regVal;
1337 regVal = 0U;
1338 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_WAKEUPENABLE, DISABLE);
1339 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_SLEWCONTROL, SLOW_SLEW);
1340 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_INPUTENABLE, DISABLE);
1341 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_PULLTYPESELECT, PULL_DOWN);
1342 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_PULLUDENABLE, ENABLE);
1343 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_MODESELECT, MUX_MODE);
1344 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_DELAYMODE, 0U);
1345 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_TXD3_RGMII0_TXD3_MUXMODE, 0U);
1346 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_TXD3 = regVal;
1348 regVal = 0U;
1349 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_WAKEUPENABLE, DISABLE);
1350 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_SLEWCONTROL, SLOW_SLEW);
1351 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_INPUTENABLE, ENABLE);
1352 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_PULLTYPESELECT, PULL_DOWN);
1353 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_PULLUDENABLE, ENABLE);
1354 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_MODESELECT, MUX_MODE);
1355 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_DELAYMODE, 0U);
1356 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXC_RGMII0_RXC_MUXMODE, 0U);
1357 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXC = regVal;
1359 regVal = 0U;
1360 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_WAKEUPENABLE, DISABLE);
1361 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_SLEWCONTROL, SLOW_SLEW);
1362 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_INPUTENABLE, ENABLE);
1363 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_PULLTYPESELECT, PULL_DOWN);
1364 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_PULLUDENABLE, ENABLE);
1365 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_MODESELECT, MUX_MODE);
1366 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_DELAYMODE, 0U);
1367 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXCTL_RGMII0_RXCTL_MUXMODE, 0U);
1368 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXCTL = regVal;
1370 regVal = 0U;
1371 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_WAKEUPENABLE, DISABLE);
1372 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_SLEWCONTROL, SLOW_SLEW);
1373 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_INPUTENABLE, ENABLE);
1374 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_PULLTYPESELECT, PULL_DOWN);
1375 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_PULLUDENABLE, ENABLE);
1376 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_MODESELECT, MUX_MODE);
1377 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_DELAYMODE, 0U);
1378 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD0_RGMII0_RXD0_MUXMODE, 0U);
1379 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXD0 = regVal;
1381 regVal = 0U;
1382 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD1_RGMII0_RXD1_WAKEUPENABLE, DISABLE);
1383 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD1_RGMII0_RXD1_SLEWCONTROL, SLOW_SLEW);
1384 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD1_RGMII0_RXD1_INPUTENABLE, ENABLE);
1385 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD1_RGMII0_RXD1_PULLTYPESELECT, PULL_DOWN);
1386 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD1_RGMII0_RXD1_PULLUDENABLE, ENABLE);
1387 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD1_RGMII0_RXD1_MODESELECT, MUX_MODE);
1388 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD1_RGMII0_RXD1_DELAYMODE, 0U);
1389 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD1_RGMII0_RXD1_MUXMODE, 0U);
1390 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXD1 = regVal;
1392 regVal = 0U;
1393 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_WAKEUPENABLE, DISABLE);
1394 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_SLEWCONTROL, SLOW_SLEW);
1395 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_INPUTENABLE, ENABLE);
1396 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_PULLTYPESELECT, PULL_DOWN);
1397 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_PULLUDENABLE, ENABLE);
1398 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_MODESELECT, MUX_MODE);
1399 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_DELAYMODE, 0U);
1400 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD2_RGMII0_RXD2_MUXMODE, 0U);
1401 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXD2 = regVal;
1403 regVal = 0U;
1404 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_WAKEUPENABLE, DISABLE);
1405 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_SLEWCONTROL, SLOW_SLEW);
1406 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_INPUTENABLE, ENABLE);
1407 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_PULLTYPESELECT, PULL_DOWN);
1408 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_PULLUDENABLE, ENABLE);
1409 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_MODESELECT, MUX_MODE);
1410 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_DELAYMODE, 0U);
1411 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_RGMII0_RXD3_RGMII0_RXD3_MUXMODE, 0U);
1412 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_RGMII0_RXD3 = regVal;
1414 regVal = 0U;
1415 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_WAKEUPENABLE, DISABLE);
1416 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_SLEWCONTROL, SLOW_SLEW);
1417 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_INPUTENABLE, DISABLE);
1418 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_PULLTYPESELECT, PULL_DOWN);
1419 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_PULLUDENABLE, ENABLE);
1420 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_MODESELECT, MUX_MODE);
1421 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_DELAYMODE, 0U);
1422 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D12_VIN2A_D12_MUXMODE, 3U);
1423 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D12 = regVal;
1425 regVal = 0U;
1426 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_WAKEUPENABLE, DISABLE);
1427 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_SLEWCONTROL, SLOW_SLEW);
1428 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_INPUTENABLE, DISABLE);
1429 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_PULLTYPESELECT, PULL_DOWN);
1430 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_PULLUDENABLE, ENABLE);
1431 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_MODESELECT, MUX_MODE);
1432 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_DELAYMODE, 0U);
1433 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D13_VIN2A_D13_MUXMODE, 3U);
1434 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D13 = regVal;
1436 regVal = 0U;
1437 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_WAKEUPENABLE, DISABLE);
1438 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_SLEWCONTROL, SLOW_SLEW);
1439 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_INPUTENABLE, DISABLE);
1440 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_PULLTYPESELECT, PULL_DOWN);
1441 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_PULLUDENABLE, ENABLE);
1442 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_MODESELECT, MUX_MODE);
1443 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_DELAYMODE, 0U);
1444 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D17_VIN2A_D17_MUXMODE, 3U);
1445 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D17 = regVal;
1447 regVal = 0U;
1448 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_WAKEUPENABLE, DISABLE);
1449 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_SLEWCONTROL, SLOW_SLEW);
1450 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_INPUTENABLE, DISABLE);
1451 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_PULLTYPESELECT, PULL_DOWN);
1452 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_PULLUDENABLE, ENABLE);
1453 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_MODESELECT, MUX_MODE);
1454 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_DELAYMODE, 0U);
1455 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D16_VIN2A_D16_MUXMODE, 3U);
1456 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D16 = regVal;
1458 regVal = 0U;
1459 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_WAKEUPENABLE, DISABLE);
1460 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_SLEWCONTROL, SLOW_SLEW);
1461 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_INPUTENABLE, DISABLE);
1462 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_PULLTYPESELECT, PULL_DOWN);
1463 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_PULLUDENABLE, ENABLE);
1464 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_MODESELECT, MUX_MODE);
1465 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_DELAYMODE, 0U);
1466 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D15_VIN2A_D15_MUXMODE, 3U);
1467 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D15 = regVal;
1469 regVal = 0U;
1470 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_WAKEUPENABLE, DISABLE);
1471 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_SLEWCONTROL, SLOW_SLEW);
1472 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_INPUTENABLE, DISABLE);
1473 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_PULLTYPESELECT, PULL_DOWN);
1474 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_PULLUDENABLE, ENABLE);
1475 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_MODESELECT, MUX_MODE);
1476 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_DELAYMODE, 0U);
1477 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D14_VIN2A_D14_MUXMODE, 3U);
1478 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D14 = regVal;
1480 regVal = 0U;
1481 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_WAKEUPENABLE, DISABLE);
1482 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_SLEWCONTROL, SLOW_SLEW);
1483 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_INPUTENABLE, ENABLE);
1484 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_PULLTYPESELECT, PULL_DOWN);
1485 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_PULLUDENABLE, ENABLE);
1486 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_MODESELECT, MUX_MODE);
1487 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_DELAYMODE, 0U);
1488 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D18_VIN2A_D18_MUXMODE, 3U);
1489 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D18 = regVal;
1491 regVal = 0U;
1492 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_WAKEUPENABLE, DISABLE);
1493 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_SLEWCONTROL, SLOW_SLEW);
1494 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_INPUTENABLE, ENABLE);
1495 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_PULLTYPESELECT, PULL_DOWN);
1496 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_PULLUDENABLE, ENABLE);
1497 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_MODESELECT, MUX_MODE);
1498 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_DELAYMODE, 0U);
1499 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D19_VIN2A_D19_MUXMODE, 3U);
1500 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D19 = regVal;
1502 regVal = 0U;
1503 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_WAKEUPENABLE, DISABLE);
1504 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_SLEWCONTROL, SLOW_SLEW);
1505 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_INPUTENABLE, ENABLE);
1506 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_PULLTYPESELECT, PULL_DOWN);
1507 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_PULLUDENABLE, ENABLE);
1508 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_MODESELECT, MUX_MODE);
1509 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_DELAYMODE, 0U);
1510 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D23_VIN2A_D23_MUXMODE, 3U);
1511 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D23 = regVal;
1513 regVal = 0U;
1514 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D22_VIN2A_D22_WAKEUPENABLE, DISABLE);
1515 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D22_VIN2A_D22_SLEWCONTROL, SLOW_SLEW);
1516 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D22_VIN2A_D22_INPUTENABLE, ENABLE);
1517 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D22_VIN2A_D22_PULLTYPESELECT, PULL_DOWN);
1518 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D22_VIN2A_D22_PULLUDENABLE, ENABLE);
1519 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D22_VIN2A_D22_MODESELECT, MUX_MODE);
1520 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D22_VIN2A_D22_DELAYMODE, 0U);
1521 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D22_VIN2A_D22_MUXMODE, 3U);
1522 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D22 = regVal;
1524 regVal = 0U;
1525 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_WAKEUPENABLE, DISABLE);
1526 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_SLEWCONTROL, SLOW_SLEW);
1527 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_INPUTENABLE, ENABLE);
1528 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_PULLTYPESELECT, PULL_DOWN);
1529 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_PULLUDENABLE, ENABLE);
1530 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_MODESELECT, MUX_MODE);
1531 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_DELAYMODE, 0U);
1532 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D21_VIN2A_D21_MUXMODE, 3U);
1533 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D21 = regVal;
1535 regVal = 0U;
1536 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_WAKEUPENABLE, DISABLE);
1537 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_SLEWCONTROL, SLOW_SLEW);
1538 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_INPUTENABLE, ENABLE);
1539 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_PULLTYPESELECT, PULL_DOWN);
1540 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_PULLUDENABLE, ENABLE);
1541 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_MODESELECT, MUX_MODE);
1542 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_DELAYMODE, 0U);
1543 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D20_VIN2A_D20_MUXMODE, 3U);
1544 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D20 = regVal;
1545 }
1547 void PinmuxGpioLedConfig (int alpha)
1548 {
1549 Uint32 regVal = 0U;
1551 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK2_XREF_CLK2_MUXMODE, 0xEU);
1552 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_XREF_CLK2 = regVal;
1554 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_MUXMODE, 0xEU);
1555 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN1A_D5 = regVal;
1557 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR4_MCASP2_AXR4_MUXMODE, 0xEU);
1558 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP2_AXR4 = regVal;
1560 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR5_MCASP2_AXR5_MUXMODE, 0xEU);
1561 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP2_AXR5 = regVal;
1563 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR6_MCASP2_AXR6_MUXMODE, 0xEU);
1564 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP2_AXR6 = regVal;
1566 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_MCASP2_AXR7_MCASP2_AXR7_MUXMODE, 0xEU);
1567 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP2_AXR7 = regVal;
1569 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_SPI1_D0_SPI1_D0_MUXMODE, 0xEU);
1570 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_SPI1_D0 = regVal;
1572 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_SPI1_D1_SPI1_D1_MUXMODE, 0xEU);
1573 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_SPI1_D1 = regVal;
1575 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_SPI1_CS0_SPI1_CS0_MUXMODE, 0xEU);
1576 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_SPI1_CS0 = regVal;
1578 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_SPI1_CS1_SPI1_CS1_MUXMODE, 0xEU);
1579 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_SPI1_CS1 = regVal;
1581 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN1A_D13_VIN1A_D13_MUXMODE, 0xEU);
1582 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN1A_D13 = regVal;
1584 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN1A_D14_VIN1A_D14_MUXMODE, 0xEU);
1585 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN1A_D14 = regVal;
1587 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_VSYNC0_VIN2A_VSYNC0_MUXMODE, 0xEU);
1588 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_VSYNC0 = regVal;
1590 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D3_VIN2A_D3_MUXMODE, 0xEU);
1591 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D3 = regVal;
1593 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D4_VIN2A_D4_MUXMODE, 0xEU);
1594 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D4 = regVal;
1596 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D5_VIN2A_D5_MUXMODE, 0xEU);
1597 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D5 = regVal;
1598 if (alpha)
1599 {
1600 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_MUXMODE, 0xEU);
1601 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART2_RTSN = regVal;
1603 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_MUXMODE, 0xEU);
1604 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART2_CTSN = regVal;
1605 }
1606 else
1607 {
1608 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_TXD_UART1_TXD_MUXMODE, 0xEU);
1609 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART1_TXD = regVal;
1611 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART1_RXD_UART1_RXD_MUXMODE, 0xEU);
1612 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART1_RXD = regVal;
1613 }
1614 }
1616 void PinmuxGpioHapticsConfig(void)
1617 {
1618 Uint32 regVal = 0U;
1620 CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_SPI1_SCLK_SPI1_SCLK_PULLTYPESELECT, PULL_UP);
1621 CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_SPI1_SCLK_SPI1_SCLK_MUXMODE, 0xEU);
1622 ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_SPI1_SCLK = regVal;
1624 }
1626 void PinmuxQSPIConfig()
1627 {
1628 /* QSPI_RTCLK */
1629 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_A13),
1630 (0x00060001));
1632 /* QSPI_D3 */
1633 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_A14),
1634 (CTRL_CORE_PAD_GPMC_A14_PULLUP_RX_MODE_1));
1636 /* QSPI_D2 */
1637 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_A15),
1638 (CTRL_CORE_PAD_GPMC_A15_PULLUP_RX_MODE_1));
1640 /* QSPI_D0 */
1641 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_A16),
1642 (CTRL_CORE_PAD_GPMC_A16_PULLUP_RX_MODE_1));
1644 /* QSPI_D1 */
1645 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_A17),
1646 (CTRL_CORE_PAD_GPMC_A17_PULLUP_RX_MODE_1));
1648 /* QSPI_CLK */
1649 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_A18),
1650 (0x00060001));
1652 /* QSPI_CSn */
1653 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_CS2),
1654 (0x00060001));
1656 /* QSPI_CSn */
1657 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_CS3),
1658 (CTRL_CORE_PAD_GPMC_CS3_PULLUP_MODE_1));
1660 /* QSPI_CLK */
1661 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_A3),
1662 (CTRL_CORE_PAD_GPMC_A3_PULLUP_MODE_1));
1664 /* QSPI_CLK */
1665 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_GPMC_A4),
1666 (CTRL_CORE_PAD_GPMC_A4_PULLUP_MODE_1));
1667 }
1669 void PinmuxMCSPIConfig()
1670 {
1671 /* GPIO3_19 */
1672 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_VIN1A_D15),
1673 (CTRL_CORE_PAD_VIN1A_D15_PILLUP));
1675 /* SPI3_SCLK */
1676 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_MCASP4_ACLKX),
1677 (CTRL_CORE_PAD_MCASP4_ACLKX_PUPDD_RX_MODE));
1679 /* SPI3_D1 */
1680 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_MCASP4_FSX),
1681 (CTRL_CORE_PAD_MCASP4_FSX_PUPDD_RX_MODE));
1683 /* SPI3_CS0 */
1684 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_MCASP4_AXR1),
1685 (CTRL_CORE_PAD_MCASP4_AXR1_PUPDD_RX_MODE));
1688 /* SPI2_SCLK */
1689 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_MCSPI2_SCLK),
1690 0x00050000);
1692 /* SPI2_D0 */
1693 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_MCSPI2_D0),
1694 0x00050000);
1696 /* SPI2_D1 */
1697 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_MCSPI2_D1),
1698 0x00060000);
1700 /* SPI2_CS0 */
1701 HW_WR_REG32((CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + CTRL_CORE_PAD_MCSPI2_CS0),
1702 0x00060000);
1703 }
1705 void ManualPinmux()
1706 {
1707 PinmuxQSPIConfig();
1708 PinmuxMCSPIConfig();
1709 PinmuxI2cConfig(1U);
1710 PinmuxI2cConfig(3U);
1711 PinmuxI2cConfig(5U);
1712 PinmuxMmcConfig(1U);
1713 PinmuxMmcConfig(2U);
1714 PinmuxMmcConfig(3U);
1715 PinmuxGpioHapticsConfig();
1716 PinmuxCpswConfig();
1717 PinmuxPruIcssConfig();
1718 }
1720 Board_STATUS Board_pinmuxConfig ()
1721 {
1722 Board_IDInfo id;
1723 Board_STATUS ret;
1724 uint32_t size;
1725 ret = Board_getIDInfo(&id);
1726 if (ret != BOARD_SOK)
1727 {
1728 return ret;
1729 }
1730 /* Check if version is 1.0 or 1.1 */
1731 if ((id.version[0] == '1' && id.version[2] == '0') ||
1732 (id.version[0] == '1' && id.version[2] == '1'))
1733 {
1734 PinmuxUartConfig(1U);
1735 PinmuxGpioLedConfig(1);
1736 ManualPinmux();
1737 }
1738 else
1739 {
1740 #if defined(NO_IO_DELAY) || defined(__TI_ARM_V7M4__)
1741 PinmuxUartConfig(3U);
1742 PinmuxGpioLedConfig(0);
1743 ManualPinmux();
1744 #elif defined(IO_DELAY)
1746 /* Check to make sure IO Delay stack and functions are in local memory */
1747 if (((uint32_t) &ioStack >= 0x80000000) || ((uint32_t)BoardCtrlPadIoDelayConfig >= 0x80000000))
1748 return BOARD_PINMUX_BAD_MEM_REGION;
1750 size = boardPadGetSize();
1752 #if defined(_TMS320C6X)
1753 Board_ioStack(ioStack+IO_DELAY_STACK_SIZE, BoardCtrlPadIoDelayConfig, pad, size);
1754 #else
1755 asm("STR r13, [%0]\n"::"r"(&ioStack[IO_DELAY_STACK_SIZE-1]));
1756 asm("MOV r13, %0\n"::"r"(&ioStack[IO_DELAY_STACK_SIZE-2]));
1757 /* Configure the pinmux and virtual/manual timing modes for all pads. */
1758 BoardCtrlPadIoDelayConfig(pad, size);
1759 asm("MOV r13, %0\n"::"r"(ioStack[IO_DELAY_STACK_SIZE-1]));
1760 #endif /* End of IO Delay config with relocation */
1762 #endif /* End of NO_IO_DELAY/IO_DELAY check */
1763 }
1765 return BOARD_SOK;
1766 }
1768 int32_t BoardMmcCtrlPadConfig(int32_t mode, uint32_t instance)
1769 {
1770 #if !defined(__TI_ARM_V7M4__)
1771 mmcBoardPadCfgTable_t *pinmuxCfgTbl = NULL;
1772 mmcBoardPadCfgTable_t *ctrlPadCfg = NULL;
1774 /* Get the pointer to the table containing the MMC runtime config table */
1775 pinmuxCfgTbl = BoardGetMmcCtrlPadPinmuxTable(instance);
1777 /* Get the pointer to the MMC configuration mode pin mux configuration */
1778 ctrlPadCfg = boardGetPinmuxCfg(pinmuxCfgTbl, mode);
1780 if(ctrlPadCfg != NULL)
1781 {
1782 /* Check to make sure IO Delay stack and functions are in local memory */
1783 if (((uint32_t) &ioStack >= 0x80000000) || ((uint32_t)BoardCtrlPadIoDelayConfig >= 0x80000000))
1784 return BOARD_PINMUX_BAD_MEM_REGION;
1786 #if defined(_TMS320C6X)
1787 Board_ioStack(ioStack+IO_DELAY_STACK_SIZE, BoardCtrlPadIoDelayConfig, ctrlPadCfg->mmcPadCfg, ctrlPadCfg->noPins);
1788 #else
1789 asm("STR r13, [%0]\n"::"r"(&ioStack[IO_DELAY_STACK_SIZE-1]));
1790 asm("MOV r13, %0\n"::"r"(&ioStack[IO_DELAY_STACK_SIZE-2]));
1791 /* Configure the pinmux and virtual/manual timing modes for all pads. */
1792 BoardCtrlPadIoDelayConfig(ctrlPadCfg->mmcPadCfg, ctrlPadCfg->noPins);
1793 asm("MOV r13, %0\n"::"r"(ioStack[IO_DELAY_STACK_SIZE-1]));
1794 #endif /* End of IO Delay config with relocation */
1795 }
1796 else
1797 {
1798 return BOARD_PINMUX_INVALID_MODE;
1799 }
1800 #endif
1802 return BOARD_SOK;
1803 }
1805 mmcBoardPadCfgTable_t * boardGetPinmuxCfg(mmcBoardPadCfgTable_t *ptr, int32_t mode)
1806 {
1807 mmcBoardPadCfgTable_t *padCfg = NULL;
1809 while(ptr->mmcMode != MMC_MODE_INVALID)
1810 {
1811 if((mode == ptr->mmcMode) && (ptr->mmcPadCfg != NULL))
1812 {
1813 padCfg = ptr;
1814 break;
1815 }
1816 ptr++;
1817 }
1819 return padCfg;
1820 }
1822 MMCSD_Error MMCSD_iodelayFxn (uint32_t instanceNum,
1823 MMCSD_v1_IodelayParams *iodelayParams)
1824 {
1825 Int32 mmcMode = MMC_MODE_INVALID;
1827 switch (instanceNum)
1828 {
1829 case 1:
1830 if ((MMCSD_LOOPBACK_ANY == iodelayParams->loopBackType) ||
1831 (MMCSD_LOOPBACK_PAD == iodelayParams->loopBackType))
1832 {
1833 if (MMCSD_TRANSPEED_DEFAULT == iodelayParams->transferSpeed)
1834 {
1835 mmcMode = MMC1_DEFAULT_PLB;
1836 }
1837 else if(MMCSD_TRANSPEED_HS == iodelayParams->transferSpeed)
1838 {
1839 mmcMode = MMC1_HS_PLB;
1840 }
1841 else if(MMCSD_TRANSPEED_SDR12 == iodelayParams->transferSpeed)
1842 {
1843 mmcMode = MMC1_SDR12_PLB;
1844 }
1845 else if(MMCSD_TRANSPEED_SDR50 == iodelayParams->transferSpeed)
1846 {
1847 mmcMode = MMC1_SDR50_PLB;
1848 }
1849 else if(MMCSD_TRANSPEED_DDR50 == iodelayParams->transferSpeed)
1850 {
1851 mmcMode = MMC1_DDR50_PLB;
1852 }
1853 else if(MMCSD_TRANSPEED_SDR104 == iodelayParams->transferSpeed)
1854 {
1855 mmcMode = MMC1_SDR104;
1856 }
1857 }
1858 if (MMCSD_LOOPBACK_INTERNAL == iodelayParams->loopBackType)
1859 {
1860 if(MMCSD_TRANSPEED_DDR50 == iodelayParams->transferSpeed)
1861 {
1862 mmcMode = MMC1_DDR50_ILB;
1863 }
1864 else if(MMCSD_TRANSPEED_DEFAULT == iodelayParams->transferSpeed)
1865 {
1866 mmcMode = MMC1_DS_ILB;
1867 }
1868 else if(MMCSD_TRANSPEED_HS == iodelayParams->transferSpeed)
1869 {
1870 mmcMode = MMC1_HS_ILB;
1871 }
1872 else if(MMCSD_TRANSPEED_SDR12 == iodelayParams->transferSpeed)
1873 {
1874 mmcMode = MMC1_SDR12_ILB;
1875 }
1876 else if(MMCSD_TRANSPEED_SDR25 == iodelayParams->transferSpeed)
1877 {
1878 mmcMode = MMC1_SDR25_ILB;
1879 }
1880 else if(MMCSD_TRANSPEED_SDR50 == iodelayParams->transferSpeed)
1881 {
1882 mmcMode = MMC1_SDR50_ILB;
1883 }
1884 }
1885 break;
1887 case 2:
1888 if ((MMCSD_LOOPBACK_ANY == iodelayParams->loopBackType) ||
1889 (MMCSD_LOOPBACK_PAD == iodelayParams->loopBackType))
1890 {
1891 if (MMCSD_TRANSPEED_DEFAULT == iodelayParams->transferSpeed)
1892 {
1893 mmcMode = MMC2_DEFAULT_STD_PLB;
1894 }
1895 else if(MMCSD_TRANSPEED_HS == iodelayParams->transferSpeed)
1896 {
1897 mmcMode = MMC2_DEFAULT_HS_PLB;
1898 }
1899 else if(MMCSD_TRANSPEED_HS200 == iodelayParams->transferSpeed)
1900 {
1901 mmcMode = MMC2_HS200;
1902 }
1903 }
1904 if (MMCSD_LOOPBACK_INTERNAL == iodelayParams->loopBackType)
1905 {
1906 mmcMode = MMC2_DDR_ILB;
1907 }
1908 else
1909 {
1910 mmcMode = MMC2_DDR_PLB;
1911 }
1912 break;
1914 case 3:
1915 if (MMCSD_TRANSPEED_DEFAULT == iodelayParams->transferSpeed)
1916 {
1917 mmcMode = MMC3_DEFAULT;
1918 }
1919 else if(MMCSD_TRANSPEED_HS == iodelayParams->transferSpeed)
1920 {
1921 mmcMode = MMC3_HS;
1922 }
1923 else if(MMCSD_TRANSPEED_SDR12 == iodelayParams->transferSpeed)
1924 {
1925 mmcMode = MMC3_SDR12;
1926 }
1927 else if(MMCSD_TRANSPEED_SDR25 == iodelayParams->transferSpeed)
1928 {
1929 mmcMode = MMC3_SDR25;
1930 }
1931 else if(MMCSD_TRANSPEED_DDR50 == iodelayParams->transferSpeed)
1932 {
1933 mmcMode = MMC3_SDR50;
1934 }
1935 break;
1937 case 4:
1938 if (MMCSD_TRANSPEED_DEFAULT == iodelayParams->transferSpeed)
1939 {
1940 mmcMode = MMC4_DEFAULT;
1941 }
1942 else if(MMCSD_TRANSPEED_HS == iodelayParams->transferSpeed)
1943 {
1944 mmcMode = MMC4_HS;
1945 }
1946 else if(MMCSD_TRANSPEED_SDR12 == iodelayParams->transferSpeed)
1947 {
1948 mmcMode = MMC4_SDR12;
1949 }
1950 else if(MMCSD_TRANSPEED_SDR25 == iodelayParams->transferSpeed)
1951 {
1952 mmcMode = MMC4_SDR25;
1953 }
1954 break;
1956 default:
1957 break;
1958 }
1960 if (MMC_MODE_INVALID != mmcMode)
1961 {
1962 BoardMmcCtrlPadConfig(mmcMode, instanceNum);
1963 }
1965 return MMCSD_OK;
1966 }