[processor-sdk/performance-audio-sr.git] / pdk_k2g_1_0_1 / packages / ti / csl / arch / c66x / interrupt.h
1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 #ifndef INTERRUPT_H
35 #define INTERRUPT_H
37 /* ========================================================================== */
38 /* Include Files */
39 /* ========================================================================== */
40 #include <stdint.h>
42 #ifdef __cplusplus
43 extern "C"
44 {
45 #endif
47 /* ========================================================================== */
48 /* Macros & Typedefs */
49 /* ========================================================================== */
50 #define C64
52 #define INTH_INT_ID_EVT0 0
53 #define INTH_INT_ID_EVT1 1
54 #define INTH_INT_ID_EVT2 2
55 #define INTH_INT_ID_EVT3 3
57 #define INTH_INT_ID_EMU_DTDMA 9
59 #define INTH_INT_ID_EMU_RDTXRX 11
60 #define INTH_INT_ID_EMU_RDTXTX 12
61 #define INTH_INT_ID_IDMAINT0 13
62 #define INTH_INT_ID_IDMAINT1 14
63 #define INTH_INT_ID_SDINT0 15 /* IRQOQN */
64 #define INTH_INT_ID_SPIINT0 16 /* SINTERRUPTN */
65 #define INTH_INT_ID_VCPINT 17 /* vcp_int */
66 #define INTH_INT_ID_ELM_IRQ 18 /* ELM_IRQ */
67 #define INTH_INT_ID_ELM 18 /* ELM_IRQ */
68 #define INTH_INT_ID_IDEINTR 19 /* PATA ide_int */
69 #define INTH_INT_ID_EDMACOMPINT 20 /* tpcc_int_pend_n[0] */
70 #define INTH_INT_ID_EDMAERRINT 21 /* tpcc_errint_pend_n */
71 #define INTH_INT_ID_TCERRINT0 22 /* tptc_errint_pend_n */
72 #define INTH_INT_ID_ISS_IRQ4 23 /* iss_irq[4] */
73 #define INTH_INT_ID_TPPMBOXINT 24 /*
74 *
75 * TPPSS_MAIL_U0_INTR_PEND_N
76 */
77 #define INTH_INT_ID_TPPDMAPKT 25 /*
78 *
79 * TPPSS_DMAPC0_INTR_PEND_N
80 */
81 #define INTH_INT_ID_TPPDMABS 26 /*
82 *
83 * TPPSS_DMABS0_INTR_PEND_N
84 */
85 #define HOST_TPPSS_DMABS0_INTRNUM 26 /*
86 *
87 * TPPSS_DMABS0_INTR_PEND_N
88 */
89 #define INTH_INT_ID_TCERRINT1 27 /* tptc_lerrint_po */
90 #define INTH_INT_ID_TCERRINT2 28 /* tptc_lerrint_po */
91 #define INTH_INT_ID_TCERRINT3 29 /* tptc_lerrint_po */
92 #define INTH_INT_ID_SDINT1 30 /* IRQOQN */
93 #define INTH_INT_ID_SDINT2 31 /* IRQOQN */
94 #define INTH_INT_ID_3PGSWRXTHR0 32 /*
95 *
96 * c0_rx_thresh_intr_pend
97 */
98 #define INTH_INT_ID_3PGSWRXINT0 33 /* c0_rx_intr_pend */
99 #define INTH_INT_ID_3PGSWTXINT0 34 /* c0_tx_intr_pend */
100 #define INTH_INT_ID_3PGSWMISC0 35 /* c0_misc_intr_pend */
101 #define INTH_INT_ID_PCIINTA 36 /*
102 *
103 * pcie_int_i_intr_pend_n0
104 */
105 #define INTH_INT_ID_PCIINTB 37 /*
106 *
107 * pcie_int_i_intr_pend_n1
108 */
109 #define INTH_INT_ID_PCIINTC 38 /*
110 *
111 * pcie_int_i_intr_pend_n2
112 */
113 #define INTH_INT_ID_PCIINTD 39 /*
114 *
115 * pcie_int_i_intr_pend_n3
116 */
117 #define INTH_INT_ID_HDDSS 40 /* intr0_intr_pend_n */
118 #define INTH_INT_ID_HDMIINT 41 /* intro_intr_pend_n */
119 #define INTH_INT_ID_SATAINT 42 /* intrq_pend_n */
120 #define INTH_INT_ID_GFXINT 43 /* THALIAIRQ */
121 #define INTH_INT_ID_SECURESS_PUBLIC_INT 44 /*
122 *
123 * nss_pub_top_intr_pending
124 */
125 #define INTH_INT_ID_SECURESS_MBINT 45 /*
126 *
127 **nss_swi_pub_top_intr_pending
128 */
129 #define INTH_INT_ID_FDIFINT 46 /* FDIF_IRQ3 */
130 #define INTH_INT_ID_WDINT 47 /* PO_INT_REQ */
131 #define INTH_INT_ID_TINT0 48 /* POINTR_PEND */
132 #define INTH_INT_ID_TINT1 49 /* POINTR_PEND */
133 #define INTH_INT_ID_TINT2 50 /* POINTR_PEND */
134 #define INTH_INT_ID_TINT3 51 /* POINTR_PEND */
135 #define INTH_INT_ID_TINT4 52 /* POINTR_PEND */
136 #define INTH_INT_ID_TINT5 53 /* POINTR_PEND */
137 #define INTH_INT_ID_TINT6 54 /* POINTR_PEND */
138 #define INTH_INT_ID_TINT7 55 /* POINTR_PEND */
139 #define INTH_INT_ID_MBINT 56 /* mail_u0_irq */
140 #define INTH_INT_ID_GPIOINT3A 57 /* POINTRPEND1 */
141 #define INTH_INT_ID_I2CINT0 58 /* POINTRPEND */
142 #define INTH_INT_ID_I2CINT1 59 /* POINTRPEND */
143 #define INTH_INT_ID_UARTINT0 60 /* uart0_nirq */
144 #define INTH_INT_ID_UARTINT1 61 /* uart1_nirq */
145 #define INTH_INT_ID_UARTINT2 62 /* uart2_nirq */
146 #define INTH_INT_ID_GPIOINT3B 63 /* POINTRPEND2 */
147 #define INTH_INT_ID_GPIOINT0A 64 /* POINTRPEND0 */
148 #define INTH_INT_ID_GPIOINT0B 65 /* POINTRPEND0 */
149 #define INTH_INT_ID_GPIOINT1A 66 /* POINTRPEND1 */
150 #define INTH_INT_ID_GPIOINT1B 67 /* POINTRPEND1 */
151 #define INTH_INT_ID_GPIOINT2A 68 /* POINTRPEND1 */
152 #define INTH_INT_ID_GPIOINT2B 69 /* POINTRPEND2 */
153 #define INTH_INT_ID_MCATXINT0 70 /* mcasp_t_intr_pend */
154 #define INTH_INT_ID_MCARXINT0 71 /* mcasp_r_intr_pend */
155 #define INTH_INT_ID_MCATXINT1 72 /* mcasp_t_intr_pend */
156 #define INTH_INT_ID_MCARXINT1 73 /* mcasp_r_intr_pend */
157 #define INTH_INT_ID_MCATXINT2 74 /* mcasp_t_intr_pend */
158 #define INTH_INT_ID_MCARXINT2 75 /* mcasp_r_intr_pend */
159 #define INTH_INT_ID_MCBSPINT 76 /* PORCOMMONIRQ */
160 #define INTH_INT_ID_UARTINT3 77 /* uart3_nirq */
161 #define INTH_INT_ID_UARTINT4 78 /* uart4_nirq */
162 #define INTH_INT_ID_UARTINT5 79 /* uart5_nirq */
163 #define INTH_INT_ID_MCATXINT3 80 /* mcasp_x_intr_pend */
164 #define INTH_INT_ID_MCARXINT3 81 /* mcasp_r_intr_pend */
165 #define INTH_INT_ID_MCATXINT4 82 /* mcasp_x_intr_pend */
166 #define INTH_INT_ID_MCARXINT4 83 /* mcasp_r_intr_pend */
167 #define INTH_INT_ID_MCATXINT5 84 /* mcasp_x_intr_pend */
168 #define INTH_INT_ID_MCARXINT5 85 /* mcasp_r_intr_pend */
169 #define INTH_INT_ID_SPIINT1 86 /* SINTERRUPTN */
170 #define INTH_INT_ID_SPIINT2 87 /* SINTERRUPTN */
171 #define INTH_INT_ID_SPIINT3 88 /* SINTERRUPTN */
172 #define INTH_INT_ID_I2CINT2 89 /* POINTRPEND */
173 #define INTH_INT_ID_IVA0CONT1SYNC 90 /*
174 *
175 * IVA_HD0_POSYNCINTRPEDN1
176 */
177 #define INTH_INT_ID_IVA0CONT2SYNC 91 /*
178 *
179 * IVA_HD0_POSYNCINTRPEDN2
180 */
181 #define INTH_INT_ID_I2CINT3 92 /* POINTRPEND */
182 #define INTH_INT_ID_MCMMUINT 93 /* POMMUHOSTINTTR */
183 #define INTH_INT_ID_IVA0MBOXINT 94 /* IVA_HD0_POMBINTRPEND0 */
184 #define INTH_INT_ID_GPMCINT 95 /* gpmc_sinterrupt */
185 #define INTH_INT_ID_INTERR 96 /* */
186 #define INTH_INT_ID_EMC_IDMAERR 97 /* */
187 #define INTH_INT_ID_PBISTINTERR 98 /* */
189 #define INTH_INT_ID_EFINTA 100 /* */
190 #define INTH_INT_ID_EFINTB 101 /* */
192 #define INTH_INT_ID_PMC_ED 113 /* */
194 #define INTH_INT_ID_UMCED1 116 /* */
195 #define INTH_INT_ID_UMCED2 117 /* */
196 #define INTH_INT_ID_PDC_INT 118 /* */
197 #define INTH_INT_ID_SYS_CMPA 119 /* */
198 #define INTH_INT_ID_PMC_CMPA 120 /* */
199 #define INTH_INT_ID_PMC_DMPA 121 /* */
200 #define INTH_INT_ID_DMC_CMPA 122 /* */
201 #define INTH_INT_ID_DMC_DMPA 123 /* */
202 #define INTH_INT_ID_UMCCMPA 124 /* */
203 #define INTH_INT_ID_UMCDMPA 125 /* */
204 #define INTH_INT_ID_EMC_CMPA 126 /* */
205 #define INTH_INT_ID_EMC_BUSERR 127 /* */
207 /* GEM Crossbar Mapping */
209 #define INTH_INT_ID_DCAN0_INT0 15 /* dcan_int0 */
210 #define INTH_INT_ID_DCAN0_INT1 16 /* dcan_int1 */
211 #define INTH_INT_ID_DCAN0_PARIT 17 /* dcan_parity_int */
212 #define INTH_INT_ID_DCAN1_INT0 18 /* dcan_int0 */
213 #define INTH_INT_ID_DCAN1_INT1 19 /* dcan_int1 */
214 #define INTH_INT_ID_DCAN1_PARIT 20 /* dcan_parity_int */
215 #define INTH_INT_ID_MLB_SYS_INT0 21 /* MLB_SYS_INT0 */
216 #define INTH_INT_ID_MLB_SYS_INT1 22 /* MLB_SYS_INT1 */
217 #define INTH_INT_ID_MLB_INT 23 /* MLB_INT */
218 #define INTH_INT_ID_SEC_EVNT 24 /* security_events_irq
219 */
220 #define INTH_INT_ID_L3DEBUG 25 /* l3_dbg_irq */
221 #define INTH_INT_ID_L3APPINT 26 /* l3_app_irq */
222 #define INTH_INT_ID_EDMAMPERR 27 /* tpcc_mpint_pend_n */
223 #define INTH_INT_ID_TINT8 28 /* POINTR_PEND */
224 #define INTH_INT_ID_WDINT0 29 /* PO_INT_REQ */
225 #define INTH_INT_ID_USBSSINT 30 /* usbss_intr_pend */
226 #define INTH_INT_ID_USBINT0 31 /* usb0_intr_pend */
227 #define INTH_INT_ID_USBINT1 32 /* usb1_intr_pend */
228 #define INTH_INT_ID_RTCINT 33 /* timer_intr_pend */
229 #define INTH_INT_ID_RTC_ALARM 34 /* alarm_intr_pend */
230 #define INTH_INT_ID_SMCDINT0 35 /* icc_irq0 */
231 #define INTH_INT_ID_SMCDINT1 36 /* icc_irq1 */
232 #define INTH_INT_ID_DDRERR0 37 /* mem_err_intr_pend_n
233 */
234 #define INTH_INT_ID_DDRERR1 38 /* mem_err_intr_pend_n
235 */
236 #define INTH_DEFAULT_INTERRUPT_KIND (INTH_TYPE_IRQ)
237 #define INTH_DEFAULT_PRIORITY 0
239 /* ========================================================================== */
240 /* Function Declarations */
241 /* ========================================================================== */
242 /*
243 * \brief function pointer to interrupt handlers
244 * A function pointer to interrupt handlers. The functions should
245 * be defined in the following format:
246 *
247 * \param None
248 *
249 * \return None.
250 *
251 **/
252 typedef void (*IntrFuncPtr)(void *handle);
254 /**
255 * \brief This API is used to initialize the interrupt controller. This API
256 * shall be called before using the interrupt controller.
257 *
258 * \param None
259 *
260 * \return None.
261 *
262 **/
263 void Intc_Init(void);
265 /**
266 * \brief Registers an interrupt Handler in the interrupt vector table for
267 * system interrupts.
268 *
269 * \param intrNum - Interrupt Number
270 * \param fnHandler - Function pointer to the ISR
271 * \param fun_arg - Argument to the ISR
272 *
273 * Note: When the interrupt occurs for the sytem interrupt number indicated,
274 * the control goes to the ISR given as the parameter.
275 *
276 * \return None.
277 **/
278 void Intc_IntRegister(uint16_t intrNum, IntrFuncPtr fptr, void *fun_arg);
280 /**
281 * \brief Unregisters an interrupt
282 *
283 * \param intrNum - Interrupt Number
284 *
285 * Note: Once an interrupt is unregistered it will enter infinite loop once
286 * an interrupt occurs
287 *
288 * \return None.
289 **/
290 void Intc_IntUnregister(uint16_t intrNum);
292 /**
293 * \brief This API enables the system interrupt in INTC. However, for
294 * the interrupt generation, make sure that the interrupt is
295 * enabled at the peripheral level also.
296 *
297 * \param intrNum - Interrupt number
298 *
299 * \return None.
300 *
301 **/
302 void Intc_SystemEnable(uint16_t intrNum);
304 /**
305 * \brief This API disables the system interrupt in INTC.
306 *
307 * \param intrNum - Interrupt number
308 *
309 * \return None.
310 *
311 **/
312 void Intc_SystemDisable(uint16_t intrNum);
314 /**
315 * \brief Restore the processor IER status if status is not equal to 0.
316 * else enables all the bits in IER.
317 * This does not affect the set of interrupts enabled/disabled
318 * in the INTC.
319 *
320 * \param The status returned by the Intc_IntDisable function.
321 *
322 * \return None
323 *
324 **/
325 void Intc_IntEnable(uint32_t status);
326 /**
327 * \brief Read and save the status and Disables the bits in IER .
328 * Prevents the processor to respond to interrupts.
329 *
330 * \param None
331 *
332 * \return Current status of IER
333 *
334 **/
335 uint32_t Intc_IntDisable(void);
337 /**
338 * \brief This API assigns a priority to an interrupt
339 *
340 * \param intrNum - Interrupt number
341 * \param priority - Interrupt priority level
342 * \param hostIntRoute - The host interrupt IRQ/FIQ to which the interrupt
343 * is to be routed.
344 * 'priority' can take any value from 0 to 127, 0 being the highest and
345 * 127 being the lowest priority.
346 *
347 * \return None.
348 *
349 **/
350 void Intc_IntPrioritySet(uint16_t intrNum, uint16_t priority,
351 uint8_t hostIntRoute);
353 #ifdef __cplusplus
354 }
355 #endif
357 #endif /* __INTH_H */
359 /* Nothing past this point */
360 /********************************* End of file ******************************/