1 /**
2 * @file csl_cpsw_Aux.h
3 *
4 * @brief
5 * API Auxilary header file for Ethernet switch module CSL.
6 *
7 * Contains the different control command and status query functions definations
8 *
9 * \par
10 * ============================================================================
11 * @n (C) Copyright 2009-2014, Texas Instruments, Inc.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 *
20 * Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the
23 * distribution.
24 *
25 * Neither the name of Texas Instruments Incorporated nor the names of
26 * its contributors may be used to endorse or promote products derived
27 * from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 */
43 #ifndef _CSL_CPSW_AUX_H_
44 #define _CSL_CPSW_AUX_H_
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
50 #include <ti/csl/cslr.h>
51 #include <ti/csl/tistdtypes.h>
53 #include <ti/csl/soc.h>
55 /** ============================================================================
56 *
57 * @defgroup CSL_CPSW_API Ethernet switch submodule (CPSW)
58 * @ingroup CSL_CPSW_API
59 *
60 * @section Introduction
61 *
62 * @subsection xxx Overview
63 *
64 * @subsection References
65 * -# Ethernet Media Access Controller User Guide
66 * ============================================================================
67 */
68 /**
69 @defgroup CSL_CPSW_SYMBOL CPSW Symbols Defined
70 @ingroup CSL_CPSW_API
71 */
72 /**
73 @defgroup CSL_CPSW_DATASTRUCT CPSW Data Structures
74 @ingroup CSL_CPSW_API
75 */
76 /**
77 @defgroup CSL_CPSW_FUNCTION CPSW Functions
78 @ingroup CSL_CPSW_API
79 */
80 /**
81 @defgroup CSL_CPSW_ENUM CPSW Enumerated Data Types
82 @ingroup CSL_CPSW_API
83 */
85 /**
86 @addtogroup CSL_CPSW_SYMBOL
87 @{
88 */
90 /**
91 @}
92 */
94 /** @addtogroup CSL_CPSW_DATASTRUCT
95 @{ */
97 /** @brief ALE control register configuration definitions */
99 /** Enable Broadcast/Multicast rate limit */
100 #define CSL_CPSW_ALECONTROL_RATELIMIT_EN (1 << 0u)
102 /** MAC auhorization mode enable */
103 #define CSL_CPSW_ALECONTROL_AUTHMODE_EN (1 << 1u)
105 /** VLAN Aware Mode enable */
106 #define CSL_CPSW_ALECONTROL_VLANAWARE_EN (1 << 2u)
108 /** Tx rate limit enable */
109 #define CSL_CPSW_ALECONTROL_RATELIMIT_TX_EN (1 << 3u)
111 /** OUI deny enable */
112 #define CSL_CPSW_ALECONTROL_OUIDENY_EN (1 << 5u)
114 /** VID0 mode enable */
115 #define CSL_CPSW_ALECONTROL_VID0MODE_EN (1 << 6u)
117 /** Learn no VID enable */
118 #define CSL_CPSW_ALECONTROL_LEARN_NO_VID_EN (1 << 7u)
120 /** Age out now enable */
121 #define CSL_CPSW_ALECONTROL_AGEOUT_NOW_EN (1 << 29u)
123 /** Clear table enable */
124 #define CSL_CPSW_ALECONTROL_CLRTABLE_EN (1 << 30u)
126 /** ALE enable */
127 #define CSL_CPSW_ALECONTROL_ALE_EN (1 << 31u)
129 /** @brief Port Mask definitions */
131 /** Port 0 Enable */
132 #define CSL_CPSW_PORTMASK_PORT0_EN (1 << 0u)
134 /** Port 1 Enable */
135 #define CSL_CPSW_PORTMASK_PORT1_EN (1 << 1u)
137 /** Port 2 Enable */
138 #define CSL_CPSW_PORTMASK_PORT2_EN (1 << 2u)
140 /** Port 3 Enable */
141 #define CSL_CPSW_PORTMASK_PORT3_EN (1 << 3u)
143 /** Port 4 Enable */
144 #define CSL_CPSW_PORTMASK_PORT4_EN (1 << 4u)
146 /** Port 5 Enable */
147 #define CSL_CPSW_PORTMASK_PORT5_EN (1 << 5u)
149 /** Port 6 Enable */
150 #define CSL_CPSW_PORTMASK_PORT6_EN (1 << 6u)
152 /** Port 7 Enable */
153 #define CSL_CPSW_PORTMASK_PORT7_EN (1 << 7u)
157 /** @brief
158 *
159 * Holds the Time sync submodule's version info.
160 */
161 typedef struct {
162 /** Minor version value */
163 Uint32 minorVer;
165 /** Major version value */
166 Uint32 majorVer;
168 /** RTL version value */
169 Uint32 rtlVer;
171 /** Identification value */
172 Uint32 id;
173 } CSL_CPSW_VERSION;
175 /** @brief
176 *
177 * Holds CPSW control register contents.
178 */
179 typedef struct {
180 /** FIFO loopback mode */
181 Uint32 fifoLb;
183 /** Vlan aware mode */
184 Uint32 vlanAware;
186 /** Port 0 Enable */
187 Uint32 p0Enable;
189 /** Port 0 Pass Priority Tagged */
190 Uint32 p0PassPriTag;
192 /** Port 1 Pass Priority Tagged */
193 Uint32 p1PassPriTag;
195 /** Port 2 Pass Priority Tagged */
196 Uint32 p2PassPriTag;
198 /** Port 3 Pass Priority Tagged */
199 Uint32 p3PassPriTag;
201 /** Port 4 Pass Priority Tagged */
202 Uint32 p4PassPriTag;
204 /** Port 5 Pass Priority Tagged */
205 Uint32 p5PassPriTag;
207 /** Port 6 Pass Priority Tagged */
208 Uint32 p6PassPriTag;
210 /** Port 7 Pass Priority Tagged */
211 Uint32 p7PassPriTag;
213 /** Port 8 Pass Priority Tagged */
214 Uint32 p8PassPriTag;
216 /** Port 0 Transmit CRC remove */
217 Uint32 p0TxCrcRemove;
219 /** Port 0 Receive Short Packet Pad
220 0 - short packets are dropped
221 1 - short packets are padded to 64-bytes (with pad and added CRC)
222 if the CRC is not passed in. Short packets are dropped if the CRC is
223 passed (in the Info0 word).
224 */
225 Uint32 p0RxPad;
227 /** Port 0 Pass Received CRC errors */
228 Uint32 p0RxPassCrcErr;
230 /** Energy Efficient Ethernet enable */
231 Uint32 eeeEnable;
233 } CSL_CPSW_CONTROL;
235 /** @brief
236 *
237 * Holds Priority type register contents.
238 */
239 typedef struct {
240 /** Escalate priority load value */
241 Uint32 escPriLdVal;
243 /** Port 0 Priority type escalate */
244 Uint32 p0PtypeEsc;
246 /** Port 1 Priority type escalate */
247 Uint32 p1PtypeEsc;
249 /** Port 2 Priority type escalate */
250 Uint32 p2PtypeEsc;
252 /** Port 3 Priority type escalate */
253 Uint32 p3PtypeEsc;
255 /** Port 4 Priority type escalate */
256 Uint32 p4PtypeEsc;
258 /** Port 5 Priority type escalate */
259 Uint32 p5PtypeEsc;
261 /** Port 6 Priority type escalate */
262 Uint32 p6PtypeEsc;
264 /** Port 7 Priority type escalate */
265 Uint32 p7PtypeEsc;
267 /** Port 8 Priority type escalate */
268 Uint32 p8PtypeEsc;
270 } CSL_CPSW_PTYPE;
272 /** @brief
273 *
274 * Holds flow control register contents.
275 */
276 typedef struct {
277 /** Port 0 flow control enable */
278 Uint32 p0FlowEnable;
280 /** Port 1 flow control enable */
281 Uint32 p1FlowEnable;
283 /** Port 2 flow control enable */
284 Uint32 p2FlowEnable;
286 /** Port 3 flow control enable */
287 Uint32 p3FlowEnable;
289 /** Port 4 flow control enable */
290 Uint32 p4FlowEnable;
292 /** Port 5 flow control enable */
293 Uint32 p5FlowEnable;
295 /** Port 6 flow control enable */
296 Uint32 p6FlowEnable;
298 /** Port 7 flow control enable */
299 Uint32 p7FlowEnable;
301 /** Port 8 flow control enable */
302 Uint32 p8FlowEnable;
304 } CSL_CPSW_FLOWCNTL;
306 /** @brief
307 *
308 * Holds the ALE submodule's version info.
309 */
310 typedef struct {
311 /** Minor version value */
312 Uint32 minorVer;
314 /** Major version value */
315 Uint32 majorVer;
317 /** RTL version value */
318 Uint32 rtlVer;
320 /** Identification value */
321 Uint32 id;
322 } CSL_CPSW_ALE_VERSION;
324 /** @brief
325 *
326 * Defines ALE port states
327 */
328 typedef enum {
329 ALE_PORTSTATE_DISABLED = 0,
330 ALE_PORTSTATE_BLOCKED,
331 ALE_PORTSTATE_LEARN,
332 ALE_PORTSTATE_FORWARD
333 } CSL_CPSW_ALE_PORTSTATE;
335 /** @brief
336 *
337 * Holds the ALE Port control register info.
338 */
339 typedef struct {
340 /** Port state */
341 CSL_CPSW_ALE_PORTSTATE portState;
343 /** Drop non-VLAN tagged ingress packets? */
344 Uint32 dropUntaggedEnable;
346 /** VLAN ID Ingress check enable */
347 Uint32 vidIngressCheckEnable;
349 /** No learn mode enable */
350 Uint32 noLearnModeEnable;
352 /** No Source Address Update enable */
353 Uint32 noSaUpdateEnable;
355 /** MAC only mode enable:
356 * When set allows the port to be treated like
357 * a Mac port for the host. All traffic received
358 * is sent only to the host. The host must direct
359 * traffic to this port as the lookup engine will
360 * not send traffic to ports with macOnlyEnable
361 * and noLearnModeEnable is set.
362 * If macOnlyEnable is set and noLearnModeEnable
363 * is not set, the host can send non-directed packets
364 * to a lookup destination with macOnlyEnable set.
365 * It is also possible that the host can broadcast
366 * to all ports including Mac Only ports in this mode.
367 */
368 Uint32 macOnlyEnable;
370 /** Disable MAC Authorization Mode for this port
371 * @note: This field is only valid when CPSW
372 * MAC authentication is enabled.
373 */
374 Uint32 macAuthDisable;
376 /** Mac Only Copy All Frames:
377 * Set: A Mac Only port will transfer all received
378 * good frames to the host.
379 * Clear: A Mac Only port will transfer packets to
380 * the host based on ALE destination address
381 * lookup operation.
382 */
383 Uint32 macOnlyCafEnable;
385 /** Multicast packet rate limit */
386 Uint32 mcastLimit;
388 /** Broadcast packet rate limit */
389 Uint32 bcastLimit;
390 } CSL_CPSW_ALE_PORTCONTROL;
392 /** @brief
393 *
394 * Defines ALE Table Entry types
395 */
396 typedef enum {
397 ALE_ENTRYTYPE_FREE = 0,
398 ALE_ENTRYTYPE_ADDRESS,
399 ALE_ENTRYTYPE_VLAN,
400 ALE_ENTRYTYPE_VLANADDRESS
401 } CSL_CPSW_ALE_ENTRYTYPE;
403 /** @brief
404 *
405 * ALE Table entry type: MAC ADDRESS
406 */
407 #define ALE_ENTRYTYPE_MAC_ADDR ALE_ENTRYTYPE_ADDRESS
409 /** @brief
410 *
411 * ALE Table entry type: POLICER ENTRY
412 */
413 #define ALE_ENTRYTYPE_POLICER ALE_ENTRYTYPE_VLAN
415 /** @brief
416 *
417 * Defines ALE Unicast types
418 */
419 typedef enum {
420 ALE_UCASTTYPE_UCAST_NOAGE = 0,
421 ALE_UCASTTYPE_UCAST_AGENOTOUCH,
422 ALE_UCASTTYPE_UCAST_OUI,
423 ALE_UCASTTYPE_UCAST_AGETOUCH
424 } CSL_CPSW_ALE_UCASTTYPE;
426 /** @brief
427 *
428 * Defines ALE Address types
429 */
430 typedef enum {
431 ALE_ADDRTYPE_UCAST = 0,
432 ALE_ADDRTYPE_MCAST,
433 ALE_ADDRTYPE_OUI
434 } CSL_CPSW_ALE_ADDRTYPE;
437 /** @brief
438 *
439 * Defines ALE Policer Entry types
440 */
441 typedef enum {
442 ALE_POLICER_ENTRYTYPE_VLAN = 0, /** VLAN or Inner VLAN */
443 ALE_POLICER_ENTRYTYPE_OVLAN, /** Outer VLAN */
444 ALE_POLICER_ENTRYTYPE_ETHERTYPE, /** Ethertype */
445 ALE_POLICER_ENTRYTYPE_IPV4, /** IPv4 address */
446 ALE_POLICER_ENTRYTYPE_IPV6 /** IPv6 address */
447 } CSL_CPSW_ALE_POLICER_ENTRYTYPE;
449 /** @brief
450 *
451 * Holds the ALE Multicast Address Table entry
452 * configuration.
453 */
454 typedef struct {
455 /** Multicast address */
456 Uint8 macAddress [6];
458 /** Multicast forward state */
459 Uint32 mcastFwdState;
461 /** Supervisory bit enable? */
462 Uint32 superEnable;
464 /** Port Mask. */
465 Uint32 portMask;
466 } CSL_CPSW_ALE_MCASTADDR_ENTRY;
468 /** @brief
469 *
470 * Holds the ALE VLAN/Multicast Address Table entry
471 * configuration.
472 */
473 typedef struct {
474 /** Multicast address */
475 Uint8 macAddress [6];
477 /** VLAN Id */
478 Uint32 vlanId;
480 /** Multicast forward state */
481 Uint32 mcastFwdState;
483 /** Supervisory bit enable? */
484 Uint32 superEnable;
486 /** Port Mask. */
487 Uint32 portMask;
488 } CSL_CPSW_ALE_VLANMCASTADDR_ENTRY;
490 /** @brief
491 *
492 * Holds the ALE Unicast Address Table entry
493 * configuration.
494 */
495 typedef struct {
496 /** Unicast address */
497 Uint8 macAddress [6];
499 /** Unicast type */
500 CSL_CPSW_ALE_UCASTTYPE ucastType;
502 /** Secure bit enable? */
503 Uint32 secureEnable;
505 /** Block bit enable? */
506 Uint32 blockEnable;
508 /** Port Number to forward matching packets to. */
509 Uint32 portNumber;
510 } CSL_CPSW_ALE_UNICASTADDR_ENTRY;
512 /** @brief
513 *
514 * Holds the ALE OUI Unicast Address Table entry
515 * configuration.
516 */
517 typedef struct {
518 /** OUI Unicast address */
519 Uint8 ouiAddress [3];
521 /** Unicast type */
522 CSL_CPSW_ALE_UCASTTYPE ucastType;
523 } CSL_CPSW_ALE_OUIADDR_ENTRY;
525 /** @brief
526 *
527 * Holds the ALE VLAN Unicast Address Table entry
528 * configuration.
529 */
530 typedef struct {
531 /** Unicast address */
532 Uint8 macAddress [6];
534 /** VLAN Id */
535 Uint32 vlanId;
537 /** Unicast type */
538 CSL_CPSW_ALE_UCASTTYPE ucastType;
540 /** Secure bit enable? */
541 Uint32 secureEnable;
543 /** Block bit enable? */
544 Uint32 blockEnable;
546 /** Port Number to forward matching packets to. */
547 Uint32 portNumber;
548 } CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY;
550 /** @brief
551 *
552 * Holds the ALE (Inner) VLAN Table entry configuration.
553 */
554 typedef struct {
555 /** VLAN Id */
556 Uint32 vlanId;
558 /** VLAN member list */
559 Uint32 vlanMemList;
561 /** Unregistered Multicast Flood mask */
562 Uint32 unRegMcastFloodMask;
564 /** Registered Multicast Flood mask */
565 Uint32 regMcastFloodMask;
567 /** Force Untagged Packet Egress. */
568 Uint32 forceUntaggedEgress;
569 } CSL_CPSW_ALE_VLAN_ENTRY;
571 /** @brief
572 *
573 * Holds the ALE Outer VLAN Table entry configuration.
574 */
575 typedef struct {
576 /** VLAN Id */
577 Uint32 vlanId;
579 } CSL_CPSW_ALE_OUTER_VLAN_ENTRY;
581 /** @brief
582 *
583 * Holds the ALE Ethertype Table entry configuration.
584 */
585 typedef struct {
586 /** Ethernet Type */
587 Uint32 ethertype;
589 } CSL_CPSW_ALE_ETHERTYPE_ENTRY;
592 /** @brief
593 *
594 * Holds the ALE IPv4 Address Table entry
595 * configuration.
596 */
597 typedef struct {
598 /** IPv4 address */
599 Uint8 address [4];
601 } CSL_CPSW_ALE_IPv4_ENTRY;
603 /** @brief
604 *
605 * Holds the ALE IPv6 Address Table entry
606 * configuration.
607 */
608 typedef struct {
609 /** IPv6 address */
610 Uint8 address [16];
612 } CSL_CPSW_ALE_IPv6_ENTRY;
614 #if defined(SOC_K2K)
616 #include <ti/csl/src/ip/cpsw/V0/csl_cpswAux.h>
618 #elif defined(SOC_K2H)
620 #include <ti/csl/src/ip/cpsw/V0/csl_cpswAux.h>
622 #elif defined(SOC_K2E)
624 #include <ti/csl/src/ip/cpsw/V1/csl_cpswAux.h>
626 #elif defined(SOC_K2L)
628 #include <ti/csl/src/ip/cpsw/V1/csl_cpswAux.h>
630 #elif defined(SOC_K2G)
632 #include <ti/csl/src/ip/cpsw/V2/csl_cpswAux.h>
634 #elif defined(SOC_AM572x) || defined(SOC_AM571x)
636 #include <ti/csl/src/ip/cpsw/V3/csl_cpswAux.h>
638 #elif defined(SOC_C6678)
640 #include <ti/csl/src/ip/cpsw/V4/csl_cpswAux.h>
642 #endif /* SOC_XXXXX */
645 /**
646 @}
647 */
649 #ifdef __cplusplus
650 }
651 #endif
653 #endif
655 /**
656 @}
657 */