1 /*
2 * cslr_dfe_cb.h
3 *
4 * This file contains the macros for Register Chip Support Library (CSL) which
5 * can be used for operations on the respective underlying hardware/peripheral
6 *
7 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the
20 * distribution.
21 *
22 * Neither the name of Texas Instruments Incorporated nor the names of
23 * its contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 */
40 /* The file is auto generated at 11:02:54 08/16/13 (Rev 1.71)*/
42 #ifndef __CSLR_DFE_CB_H__
43 #define __CSLR_DFE_CB_H__
45 #include <ti/csl/cslr.h>
46 #include <ti/csl/tistdtypes.h>
48 /**************************************************************************\
49 * Register Overlay Structure
50 \**************************************************************************/
52 typedef struct
53 {
54 /* Addr: h(0), d(0) */
55 volatile Uint32 rsvd0[128];
56 /* Addr: h(200), d(512) */
57 volatile Uint32 cb_arm;
58 /* Addr: h(204), d(516) */
59 volatile Uint32 bus_ctrl_reset;
60 /* Addr: h(208), d(520) */
61 volatile Uint32 cb_buffer_mode;
62 /* Addr: h(20C), d(524) */
63 volatile Uint32 dpda_read_skipchunk;
64 /* Addr: h(210), d(528) */
65 volatile Uint32 cba_setting;
66 /* Addr: h(214), d(532) */
67 volatile Uint32 cba_dly;
68 /* Addr: h(218), d(536) */
69 volatile Uint32 cbb_setting;
70 /* Addr: h(21C), d(540) */
71 volatile Uint32 cbb_dly;
72 /* Addr: h(220), d(544) */
73 volatile Uint32 cbc_setting;
74 /* Addr: h(224), d(548) */
75 volatile Uint32 cbc_dly;
76 /* Addr: h(228), d(552) */
77 volatile Uint32 cbd_setting;
78 /* Addr: h(22C), d(556) */
79 volatile Uint32 cbd_dly;
80 /* Addr: h(230), d(560) */
81 volatile Uint32 rate_mode;
82 /* Addr: h(234), d(564) */
83 volatile Uint32 node0_config;
84 /* Addr: h(238), d(568) */
85 volatile Uint32 node0_fsf_fsfm;
86 /* Addr: h(23C), d(572) */
87 volatile Uint32 node1_config;
88 /* Addr: h(240), d(576) */
89 volatile Uint32 node1_fsf_fsfm;
90 /* Addr: h(244), d(580) */
91 volatile Uint32 node2_config;
92 /* Addr: h(248), d(584) */
93 volatile Uint32 node2_fsf_fsfm;
94 /* Addr: h(24C), d(588) */
95 volatile Uint32 node3_config;
96 /* Addr: h(250), d(592) */
97 volatile Uint32 node3_fsf_fsfm;
98 /* Addr: h(254), d(596) */
99 volatile Uint32 node4_config;
100 /* Addr: h(258), d(600) */
101 volatile Uint32 node4_fsf_fsfm;
102 /* Addr: h(25C), d(604) */
103 volatile Uint32 node5_config;
104 /* Addr: h(260), d(608) */
105 volatile Uint32 node5_fsf_fsfm;
106 /* Addr: h(264), d(612) */
107 volatile Uint32 node6_config;
108 /* Addr: h(268), d(616) */
109 volatile Uint32 node6_fsf_fsfm;
110 /* Addr: h(26C), d(620) */
111 volatile Uint32 node7_config;
112 /* Addr: h(270), d(624) */
113 volatile Uint32 node7_fsf_fsfm;
114 /* Addr: h(274), d(628) */
115 volatile Uint32 node8_config;
116 /* Addr: h(278), d(632) */
117 volatile Uint32 node8_fsf_fsfm;
118 /* Addr: h(27C), d(636) */
119 volatile Uint32 frac_cnt;
120 /* Addr: h(280), d(640) */
121 volatile Uint32 initial_fractional_phase_ctrl;
122 /* Addr: h(284), d(644) */
123 volatile Uint32 done_frac_cnt;
124 /* Addr: h(288), d(648) */
125 volatile Uint32 buf_ab_done_addr;
126 /* Addr: h(28C), d(652) */
127 volatile Uint32 buf_cd_done_addr;
128 /* Addr: h(290), d(656) */
129 volatile Uint32 cba_done_length_cnt;
130 /* Addr: h(294), d(660) */
131 volatile Uint32 cbb_done_length_cnt;
132 /* Addr: h(298), d(664) */
133 volatile Uint32 cbc_done_length_cnt;
134 /* Addr: h(29C), d(668) */
135 volatile Uint32 cbd_done_length_cnt;
136 /* Addr: h(2A0), d(672) */
137 volatile Uint32 cb_c_multi_capture_ctrl;
138 /* Addr: h(2A4), d(676) */
139 volatile Uint32 cb_c_multicap_timer1;
140 /* Addr: h(2A8), d(680) */
141 volatile Uint32 cb_c_multicap_timer2;
142 /* Addr: h(2AC), d(684) */
143 volatile Uint32 cb_c_multicap_timer3;
144 /* Addr: h(2B0), d(688) */
145 volatile Uint32 cb_c_multicap_timer4;
146 /* Addr: h(2B4), d(692) */
147 volatile Uint32 cb_c_multicap_timer5;
148 /* Addr: h(2B8), d(696) */
149 volatile Uint32 cb_c_multicap_timer6;
150 /* Addr: h(2BC), d(700) */
151 volatile Uint32 cb_c_multicap_timer7;
152 /* Addr: h(2C0), d(704) */
153 volatile Uint32 cb_c_multicap_timer8;
154 /* Addr: h(2C4), d(708) */
155 volatile Uint32 chunk1_done_addr;
156 /* Addr: h(2C8), d(712) */
157 volatile Uint32 chunk2_done_addr;
158 /* Addr: h(2CC), d(716) */
159 volatile Uint32 chunk3_done_addr;
160 /* Addr: h(2D0), d(720) */
161 volatile Uint32 chunk4_done_addr;
162 /* Addr: h(2D4), d(724) */
163 volatile Uint32 chunk5_done_addr;
164 /* Addr: h(2D8), d(728) */
165 volatile Uint32 chunk6_done_addr;
166 /* Addr: h(2DC), d(732) */
167 volatile Uint32 chunk7_done_addr;
168 /* Addr: h(2E0), d(736) */
169 volatile Uint32 chunk8_done_addr;
170 /* Addr: h(2E4), d(740) */
171 volatile Uint32 trigger_monitor_setting;
172 /* Addr: h(2E8), d(744) */
173 volatile Uint32 trigger_monitor_a_config;
174 /* Addr: h(2EC), d(748) */
175 volatile Uint32 trigger_monitor_a_fsf_fsfm;
176 /* Addr: h(2F0), d(752) */
177 volatile Uint32 trigger_monitor_b_config;
178 /* Addr: h(2F4), d(756) */
179 volatile Uint32 trigger_monitor_b_fsf_fsfm;
180 /* Addr: h(2F8), d(760) */
181 volatile Uint32 triga_blk0_length;
182 /* Addr: h(2FC), d(764) */
183 volatile Uint32 triga_blk0_t1;
184 /* Addr: h(300), d(768) */
185 volatile Uint32 triga_blk0_t2;
186 /* Addr: h(304), d(772) */
187 volatile Uint32 triga_blk1_length;
188 /* Addr: h(308), d(776) */
189 volatile Uint32 triga_blk1_t1;
190 /* Addr: h(30C), d(780) */
191 volatile Uint32 triga_blk1_t2;
192 /* Addr: h(310), d(784) */
193 volatile Uint32 trigb_blk0_length;
194 /* Addr: h(314), d(788) */
195 volatile Uint32 trigb_blk0_t1;
196 /* Addr: h(318), d(792) */
197 volatile Uint32 trigb_blk0_t2;
198 /* Addr: h(31C), d(796) */
199 volatile Uint32 trigb_blk1_length;
200 /* Addr: h(320), d(800) */
201 volatile Uint32 trigb_blk1_t1;
202 /* Addr: h(324), d(804) */
203 volatile Uint32 trigb_blk1_t2;
204 /* Addr: h(328), d(808) */
205 volatile Uint32 trigger_monitor_decoder;
206 /* Addr: h(32C), d(812) */
207 volatile Uint32 gsg_mode;
208 /* Addr: h(330), d(816) */
209 volatile Uint32 gsg0_delayfromsync;
210 /* Addr: h(334), d(820) */
211 volatile Uint32 gsg0_timer1;
212 /* Addr: h(338), d(824) */
213 volatile Uint32 gsg0_timer2;
214 /* Addr: h(33C), d(828) */
215 volatile Uint32 gsg0_timer3;
216 /* Addr: h(340), d(832) */
217 volatile Uint32 gsg0_timer4;
218 /* Addr: h(344), d(836) */
219 volatile Uint32 gsg0_timer5;
220 /* Addr: h(348), d(840) */
221 volatile Uint32 gsg1_delayfromsync;
222 /* Addr: h(34C), d(844) */
223 volatile Uint32 gsg1_timer1;
224 /* Addr: h(350), d(848) */
225 volatile Uint32 gsg1_timer2;
226 /* Addr: h(354), d(852) */
227 volatile Uint32 gsg1_timer3;
228 /* Addr: h(358), d(856) */
229 volatile Uint32 gsg1_timer4;
230 /* Addr: h(35C), d(860) */
231 volatile Uint32 gsg1_timer5;
232 /* Addr: h(360), d(864) */
233 volatile Uint32 gsg2_delayfromsync;
234 /* Addr: h(364), d(868) */
235 volatile Uint32 gsg2_timer1;
236 /* Addr: h(368), d(872) */
237 volatile Uint32 gsg2_timer2;
238 /* Addr: h(36C), d(876) */
239 volatile Uint32 gsg2_timer3;
240 /* Addr: h(370), d(880) */
241 volatile Uint32 gsg2_timer4;
242 /* Addr: h(374), d(884) */
243 volatile Uint32 gsg2_timer5;
244 /* Addr: h(378), d(888) */
245 volatile Uint32 gsg3_delayfromsync;
246 /* Addr: h(37C), d(892) */
247 volatile Uint32 gsg3_timer1;
248 /* Addr: h(380), d(896) */
249 volatile Uint32 gsg3_timer2;
250 /* Addr: h(384), d(900) */
251 volatile Uint32 gsg3_timer3;
252 /* Addr: h(388), d(904) */
253 volatile Uint32 gsg3_timer4;
254 /* Addr: h(38C), d(908) */
255 volatile Uint32 gsg3_timer5;
256 /* Addr: h(390), d(912) */
257 volatile Uint32 gsg4_delayfromsync;
258 /* Addr: h(394), d(916) */
259 volatile Uint32 gsg4_timer1;
260 /* Addr: h(398), d(920) */
261 volatile Uint32 gsg4_timer2;
262 /* Addr: h(39C), d(924) */
263 volatile Uint32 gsg4_timer3;
264 /* Addr: h(3A0), d(928) */
265 volatile Uint32 gsg4_timer4;
266 /* Addr: h(3A4), d(932) */
267 volatile Uint32 gsg4_timer5;
268 /* Addr: h(3A8), d(936) */
269 volatile Uint32 gsg5_delayfromsync;
270 /* Addr: h(3AC), d(940) */
271 volatile Uint32 gsg5_timer1;
272 /* Addr: h(3B0), d(944) */
273 volatile Uint32 gsg5_timer2;
274 /* Addr: h(3B4), d(948) */
275 volatile Uint32 gsg5_timer3;
276 /* Addr: h(3B8), d(952) */
277 volatile Uint32 gsg5_timer4;
278 /* Addr: h(3BC), d(956) */
279 volatile Uint32 gsg5_timer5;
280 /* Addr: h(3C0), d(960) */
281 volatile Uint32 rsvd1[1];
282 /* Addr: h(3C4), d(964) */
283 volatile Uint32 gsg_ssel;
284 /* Addr: h(3C8), d(968) */
285 volatile Uint32 gsg_seq_sel_part1;
286 /* Addr: h(3CC), d(972) */
287 volatile Uint32 gsg_seq_sel_part2;
288 /* Addr: h(3D0), d(976) */
289 volatile Uint32 silent_detect_setting;
290 /* Addr: h(3D4), d(980) */
291 volatile Uint32 cb_f_chunk_selection;
292 /* Addr: h(3D8), d(984) */
293 volatile Uint32 cb_f_broken_chain_detection;
294 /* Addr: h(3DC), d(988) */
295 volatile Uint32 cb_f_maxrefpower_ant0_1;
296 /* Addr: h(3E0), d(992) */
297 volatile Uint32 cb_f_maxrefpower_ant2_3;
298 /* Addr: h(3E4), d(996) */
299 volatile Uint32 cb_f_deltapowerinlinear;
300 /* Addr: h(3E8), d(1000) */
301 volatile Uint32 cb_f_badbuffer_detection_en;
302 /* Addr: h(3EC), d(1004) */
303 volatile Uint32 power_monitor_sync_dly_ant0;
304 /* Addr: h(3F0), d(1008) */
305 volatile Uint32 power_monitor_sync_dly_ant1;
306 /* Addr: h(3F4), d(1012) */
307 volatile Uint32 power_monitor_sync_dly_ant2;
308 /* Addr: h(3F8), d(1016) */
309 volatile Uint32 power_monitor_sync_dly_ant3;
310 /* Addr: h(3FC), d(1020) */
311 volatile Uint32 power_monitor_intg_pd_ant0;
312 /* Addr: h(400), d(1024) */
313 volatile Uint32 power_monitor_intg_pd_ant1;
314 /* Addr: h(404), d(1028) */
315 volatile Uint32 power_monitor_intg_pd_ant2;
316 /* Addr: h(408), d(1032) */
317 volatile Uint32 power_monitor_intg_pd_ant3;
318 /* Addr: h(40C), d(1036) */
319 volatile Uint32 power_monitor_config_ant0;
320 /* Addr: h(410), d(1040) */
321 volatile Uint32 power_monitor_ant0_fsf_fsfm;
322 /* Addr: h(414), d(1044) */
323 volatile Uint32 power_monitor_config_ant1;
324 /* Addr: h(418), d(1048) */
325 volatile Uint32 power_monitor_ant1_fsf_fsfm;
326 /* Addr: h(41C), d(1052) */
327 volatile Uint32 power_monitor_config_ant2;
328 /* Addr: h(420), d(1056) */
329 volatile Uint32 power_monitor_ant2_fsf_fsfm;
330 /* Addr: h(424), d(1060) */
331 volatile Uint32 power_monitor_config_ant3;
332 /* Addr: h(428), d(1064) */
333 volatile Uint32 power_monitor_ant3_fsf_fsfm;
334 /* Addr: h(42C), d(1068) */
335 volatile Uint32 power_monitor_node_sel;
336 /* Addr: h(430), d(1072) */
337 volatile Uint32 cb_sourcing_control;
338 /* Addr: h(434), d(1076) */
339 volatile Uint32 cb_time_step;
340 /* Addr: h(438), d(1080) */
341 volatile Uint32 cb_reset_int;
342 /* Addr: h(43C), d(1084) */
343 volatile Uint32 cb_tdd_period;
344 /* Addr: h(440), d(1088) */
345 volatile Uint32 cb_tdd_on_0;
346 /* Addr: h(444), d(1092) */
347 volatile Uint32 cb_tdd_off_0;
348 /* Addr: h(448), d(1096) */
349 volatile Uint32 cb_tdd_on_1;
350 /* Addr: h(44C), d(1100) */
351 volatile Uint32 cb_tdd_off_1;
352 /* Addr: h(450), d(1104) */
353 volatile Uint32 inits;
354 /* Addr: h(454), d(1108) */
355 volatile Uint32 cb_sync_select_part1;
356 /* Addr: h(458), d(1112) */
357 volatile Uint32 cb_sync_select_part2;
358 /* Addr: h(45C), d(1116) */
359 volatile Uint32 cb_sync_select_part3;
360 /* Addr: h(460), d(1120) */
361 volatile Uint32 cb_src_node_control;
362 /* Addr: h(464), d(1124) */
363 volatile Uint32 buffer_full_flag;
364 /* Addr: h(468), d(1128) */
365 volatile Uint32 triga_blk0_outpwr;
366 /* Addr: h(46C), d(1132) */
367 volatile Uint32 triga_blk1_outpwr;
368 /* Addr: h(470), d(1136) */
369 volatile Uint32 trigb_blk0_outpwr;
370 /* Addr: h(474), d(1140) */
371 volatile Uint32 trigb_blk1_outpwr;
372 /* Addr: h(478), d(1144) */
373 volatile Uint32 cb_ref_fb_latency_ant0;
374 /* Addr: h(47C), d(1148) */
375 volatile Uint32 cb_ref_fb_latency_ant1;
376 /* Addr: h(480), d(1152) */
377 volatile Uint32 cb_ref_fb_latency_ant2;
378 /* Addr: h(484), d(1156) */
379 volatile Uint32 cb_ref_fb_latency_ant3;
380 /* Addr: h(488), d(1160) */
381 volatile Uint32 cb_sync_select_part4;
382 /* Addr: h(48C), d(1164) */
383 volatile Uint32 cba_chunk1_2_done_addr;
384 /* Addr: h(490), d(1168) */
385 volatile Uint32 cba_chunk3_4_done_addr;
386 /* Addr: h(494), d(1172) */
387 volatile Uint32 cba_chunk5_6_done_addr;
388 /* Addr: h(498), d(1176) */
389 volatile Uint32 cba_chunk7_8_done_addr;
390 /* Addr: h(49C), d(1180) */
391 volatile Uint32 cbb_chunk1_2_done_addr;
392 /* Addr: h(4A0), d(1184) */
393 volatile Uint32 cbb_chunk3_4_done_addr;
394 /* Addr: h(4A4), d(1188) */
395 volatile Uint32 cbb_chunk5_6_done_addr;
396 /* Addr: h(4A8), d(1192) */
397 volatile Uint32 cbb_chunk7_8_done_addr;
398 /* Addr: h(4AC), d(1196) */
399 volatile Uint32 cbc_chunk1_2_done_addr;
400 /* Addr: h(4B0), d(1200) */
401 volatile Uint32 cbc_chunk3_4_done_addr;
402 /* Addr: h(4B4), d(1204) */
403 volatile Uint32 cbc_chunk5_6_done_addr;
404 /* Addr: h(4B8), d(1208) */
405 volatile Uint32 cbc_chunk7_8_done_addr;
406 /* Addr: h(4BC), d(1212) */
407 volatile Uint32 cbd_chunk1_2_done_addr;
408 /* Addr: h(4C0), d(1216) */
409 volatile Uint32 cbd_chunk3_4_done_addr;
410 /* Addr: h(4C4), d(1220) */
411 volatile Uint32 cbd_chunk5_6_done_addr;
412 /* Addr: h(4C8), d(1224) */
413 volatile Uint32 cbd_chunk7_8_done_addr;
414 /* Addr: h(4CC), d(1228) */
415 volatile Uint32 rsvd2[65229];
416 /* Addr: h(40000), d(262144) */
417 volatile Uint32 capture_buffer_a_16msb[8192];
418 /* Addr: h(48000), d(294912) */
419 volatile Uint32 capture_buffer_b_16msb[8192];
420 /* Addr: h(50000), d(327680) */
421 volatile Uint32 capture_buffer_c_16msb[8192];
422 /* Addr: h(58000), d(360448) */
423 volatile Uint32 capture_buffer_d_16msb[8192];
424 /* Addr: h(60000), d(393216) */
425 volatile Uint32 capture_buffer_a_2lsb[8192];
426 /* Addr: h(68000), d(425984) */
427 volatile Uint32 capture_buffer_b_2lsb[8192];
428 /* Addr: h(70000), d(458752) */
429 volatile Uint32 capture_buffer_c_2lsb[8192];
430 /* Addr: h(78000), d(491520) */
431 volatile Uint32 capture_buffer_d_2lsb[8192];
432 } CSL_DFE_CB_REGS;
434 /**************************************************************************\
435 * Field Definition Macros
436 \**************************************************************************/
438 /* CB_ARM */
439 typedef struct
440 {
441 #ifdef _BIG_ENDIAN
442 Uint32 rsvd1 : 26;
443 Uint32 cb_f_capture_done : 1;
444 Uint32 cb_f_sync_arm : 1;
445 Uint32 rsvd0 : 2;
446 Uint32 cb_c_capture_done : 1;
447 Uint32 cb_c_sync_arm : 1;
448 #else
449 Uint32 cb_c_sync_arm : 1;
450 Uint32 cb_c_capture_done : 1;
451 Uint32 rsvd0 : 2;
452 Uint32 cb_f_sync_arm : 1;
453 Uint32 cb_f_capture_done : 1;
454 Uint32 rsvd1 : 26;
455 #endif
456 } CSL_DFE_CB_CB_ARM_REG;
458 /* arm control to cb_c_start_sync. It must be armed(set to 1) for cbc to start looking at sync. Once sync is detected, sync_arm will go back to 0 */
459 #define CSL_DFE_CB_CB_ARM_REG_CB_C_SYNC_ARM_MASK (0x00000001u)
460 #define CSL_DFE_CB_CB_ARM_REG_CB_C_SYNC_ARM_SHIFT (0x00000000u)
461 #define CSL_DFE_CB_CB_ARM_REG_CB_C_SYNC_ARM_RESETVAL (0x00000000u)
463 /* When capture is done, it will bring this signal low. Similar signal to sync_arm. If the user sets it to 1 before capture starts, the chip will bring the signal to 0 when the capture is done. */
464 #define CSL_DFE_CB_CB_ARM_REG_CB_C_CAPTURE_DONE_MASK (0x00000002u)
465 #define CSL_DFE_CB_CB_ARM_REG_CB_C_CAPTURE_DONE_SHIFT (0x00000001u)
466 #define CSL_DFE_CB_CB_ARM_REG_CB_C_CAPTURE_DONE_RESETVAL (0x00000000u)
468 /* arm control to cb_f_start_sync. It must be armed(set to 1) for cbf to start looking at sync. Once sync is detected, sync_arm will go back to 0 */
469 #define CSL_DFE_CB_CB_ARM_REG_CB_F_SYNC_ARM_MASK (0x00000010u)
470 #define CSL_DFE_CB_CB_ARM_REG_CB_F_SYNC_ARM_SHIFT (0x00000004u)
471 #define CSL_DFE_CB_CB_ARM_REG_CB_F_SYNC_ARM_RESETVAL (0x00000000u)
473 /* When capture is done, it will bring this signal low. Similar signal to sync_arm. If the user sets it to 1 before capture starts, the chip will bring the signal to 0 when the capture is done. */
474 #define CSL_DFE_CB_CB_ARM_REG_CB_F_CAPTURE_DONE_MASK (0x00000020u)
475 #define CSL_DFE_CB_CB_ARM_REG_CB_F_CAPTURE_DONE_SHIFT (0x00000005u)
476 #define CSL_DFE_CB_CB_ARM_REG_CB_F_CAPTURE_DONE_RESETVAL (0x00000000u)
478 #define CSL_DFE_CB_CB_ARM_REG_ADDR (0x00000200u)
479 #define CSL_DFE_CB_CB_ARM_REG_RESETVAL (0x00000000u)
481 /* BUS_CTRL_RESET */
482 typedef struct
483 {
484 #ifdef _BIG_ENDIAN
485 Uint32 rsvd4 : 8;
486 Uint32 dpd_mode : 4;
487 Uint32 cb_f_force_done_reset : 1;
488 Uint32 cb_f_subsample_fb : 1;
489 Uint32 cb_c_force_done_reset : 1;
490 Uint32 cb_c_force_arm_reset : 1;
491 Uint32 rsvd3 : 3;
492 Uint32 dsp_ctrl : 1;
493 Uint32 rsvd2 : 3;
494 Uint32 iq_swap : 1;
495 Uint32 rsvd1 : 3;
496 Uint32 tbus_sel : 1;
497 Uint32 rsvd0 : 3;
498 Uint32 nogating : 1;
499 #else
500 Uint32 nogating : 1;
501 Uint32 rsvd0 : 3;
502 Uint32 tbus_sel : 1;
503 Uint32 rsvd1 : 3;
504 Uint32 iq_swap : 1;
505 Uint32 rsvd2 : 3;
506 Uint32 dsp_ctrl : 1;
507 Uint32 rsvd3 : 3;
508 Uint32 cb_c_force_arm_reset : 1;
509 Uint32 cb_c_force_done_reset : 1;
510 Uint32 cb_f_subsample_fb : 1;
511 Uint32 cb_f_force_done_reset : 1;
512 Uint32 dpd_mode : 4;
513 Uint32 rsvd4 : 8;
514 #endif
515 } CSL_DFE_CB_BUS_CTRL_RESET_REG;
517 /* No gating mode: */
518 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_NOGATING_MASK (0x00000001u)
519 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_NOGATING_SHIFT (0x00000000u)
520 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_NOGATING_RESETVAL (0x00000000u)
522 /* 0 = capture the 36 MSB's of 38-bit testbus */
523 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_TBUS_SEL_MASK (0x00000010u)
524 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_TBUS_SEL_SHIFT (0x00000004u)
525 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_TBUS_SEL_RESETVAL (0x00000000u)
527 /* if set to '1', swap the I, Q data when put them onto mpurd bus. */
528 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_IQ_SWAP_MASK (0x00000100u)
529 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_IQ_SWAP_SHIFT (0x00000008u)
530 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_IQ_SWAP_RESETVAL (0x00000000u)
532 /* When this bit is set to '0', capture buffer will not listen to arbiter, DSP will control the start and stop of capture buffer. Otherwise, capture buffer receives all commands from arbiter. */
533 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_DSP_CTRL_MASK (0x00001000u)
534 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_DSP_CTRL_SHIFT (0x0000000Cu)
535 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_DSP_CTRL_RESETVAL (0x00000000u)
537 /* force cb_c_sync_arm register into asynchronuous reset */
538 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_C_FORCE_ARM_RESET_MASK (0x00010000u)
539 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_C_FORCE_ARM_RESET_SHIFT (0x00000010u)
540 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_C_FORCE_ARM_RESET_RESETVAL (0x00000000u)
542 /* force cb_c_capture_ done register into asynchronuous reset */
543 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_C_FORCE_DONE_RESET_MASK (0x00020000u)
544 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_C_FORCE_DONE_RESET_SHIFT (0x00000011u)
545 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_C_FORCE_DONE_RESET_RESETVAL (0x00000000u)
547 /* It only matters when we do CB-F capture. If fb signal is subsampled (by 2) relative to reference signal, then cb-f chunk size of fb signal is 256 and need to manipulate the memory write address to handle this since the sample cnt output from 'chunksel' is 0~511: */
548 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_F_SUBSAMPLE_FB_MASK (0x00040000u)
549 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_F_SUBSAMPLE_FB_SHIFT (0x00000012u)
550 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_F_SUBSAMPLE_FB_RESETVAL (0x00000000u)
552 /* force cb_f_capture_ done register into asynchronuous reset */
553 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_F_FORCE_DONE_RESET_MASK (0x00080000u)
554 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_F_FORCE_DONE_RESET_SHIFT (0x00000013u)
555 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_CB_F_FORCE_DONE_RESET_RESETVAL (0x00000000u)
557 /* The DPD mode information combined with 'antenna[2:0]' from arbiter will be used to program I/Q_bus_sel for cb-f capture of reference signal: */
558 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_DPD_MODE_MASK (0x00F00000u)
559 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_DPD_MODE_SHIFT (0x00000014u)
560 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_DPD_MODE_RESETVAL (0x00000000u)
562 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_ADDR (0x00000204u)
563 #define CSL_DFE_CB_BUS_CTRL_RESET_REG_RESETVAL (0x00000000u)
565 /* CB_BUFFER_MODE */
566 typedef struct
567 {
568 #ifdef _BIG_ENDIAN
569 Uint32 rsvd3 : 17;
570 Uint32 cbd_mode : 3;
571 Uint32 rsvd2 : 1;
572 Uint32 cbc_mode : 3;
573 Uint32 rsvd1 : 1;
574 Uint32 cbb_mode : 3;
575 Uint32 rsvd0 : 1;
576 Uint32 cba_mode : 3;
577 #else
578 Uint32 cba_mode : 3;
579 Uint32 rsvd0 : 1;
580 Uint32 cbb_mode : 3;
581 Uint32 rsvd1 : 1;
582 Uint32 cbc_mode : 3;
583 Uint32 rsvd2 : 1;
584 Uint32 cbd_mode : 3;
585 Uint32 rsvd3 : 17;
586 #endif
587 } CSL_DFE_CB_CB_BUFFER_MODE_REG;
589 /* capture buffer operation mode: */
590 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBA_MODE_MASK (0x00000007u)
591 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBA_MODE_SHIFT (0x00000000u)
592 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBA_MODE_RESETVAL (0x00000000u)
594 /* same as cba_mode */
595 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBB_MODE_MASK (0x00000070u)
596 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBB_MODE_SHIFT (0x00000004u)
597 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBB_MODE_RESETVAL (0x00000000u)
599 /* same as cba_mode */
600 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBC_MODE_MASK (0x00000700u)
601 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBC_MODE_SHIFT (0x00000008u)
602 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBC_MODE_RESETVAL (0x00000000u)
604 /* same as cba_mode */
605 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBD_MODE_MASK (0x00007000u)
606 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBD_MODE_SHIFT (0x0000000Cu)
607 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_CBD_MODE_RESETVAL (0x00000000u)
609 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_ADDR (0x00000208u)
610 #define CSL_DFE_CB_CB_BUFFER_MODE_REG_RESETVAL (0x00000000u)
612 /* DPDA_READ_SKIPCHUNK */
613 typedef struct
614 {
615 #ifdef _BIG_ENDIAN
616 Uint32 rsvd0 : 20;
617 Uint32 spare_bits : 10;
618 Uint32 readfb_skipchunk : 1;
619 Uint32 readref_skipchunk : 1;
620 #else
621 Uint32 readref_skipchunk : 1;
622 Uint32 readfb_skipchunk : 1;
623 Uint32 spare_bits : 10;
624 Uint32 rsvd0 : 20;
625 #endif
626 } CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG;
628 /* When this bit is set to '1', cb will skip the two last (useless) chunks when dpda reads (cb-f) reference data. Otherwise, cb will send out reference data continuously based on read address from dpda. */
629 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_READREF_SKIPCHUNK_MASK (0x00000001u)
630 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_READREF_SKIPCHUNK_SHIFT (0x00000000u)
631 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_READREF_SKIPCHUNK_RESETVAL (0x00000000u)
633 /* When this bit is set to '1', cb will skip the two last (useless) chunks when dpda reads (cb-f) feedback data. Otherwise, cb will send out feedback data continuously based on read address from dpda. */
634 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_READFB_SKIPCHUNK_MASK (0x00000002u)
635 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_READFB_SKIPCHUNK_SHIFT (0x00000001u)
636 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_READFB_SKIPCHUNK_RESETVAL (0x00000000u)
638 /* spear bits reserved for future use */
639 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_SPARE_BITS_MASK (0x00000FFCu)
640 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_SPARE_BITS_SHIFT (0x00000002u)
641 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_SPARE_BITS_RESETVAL (0x00000000u)
643 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_ADDR (0x0000020Cu)
644 #define CSL_DFE_CB_DPDA_READ_SKIPCHUNK_REG_RESETVAL (0x00000000u)
646 /* CBA_SETTING */
647 typedef struct
648 {
649 #ifdef _BIG_ENDIAN
650 Uint32 rsvd3 : 15;
651 Uint32 cba_not_used : 1;
652 Uint32 rsvd2 : 2;
653 Uint32 cba_ref_or_fb : 2;
654 Uint32 rsvd1 : 3;
655 Uint32 cba_bus_sel : 1;
656 Uint32 cba_sel : 4;
657 Uint32 rsvd0 : 4;
658 #else
659 Uint32 rsvd0 : 4;
660 Uint32 cba_sel : 4;
661 Uint32 cba_bus_sel : 1;
662 Uint32 rsvd1 : 3;
663 Uint32 cba_ref_or_fb : 2;
664 Uint32 rsvd2 : 2;
665 Uint32 cba_not_used : 1;
666 Uint32 rsvd3 : 15;
667 #endif
668 } CSL_DFE_CB_CBA_SETTING_REG;
670 /* capture node select: */
671 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_SEL_MASK (0x000000F0u)
672 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_SEL_SHIFT (0x00000004u)
673 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_SEL_RESETVAL (0x00000000u)
675 /* In 1x mode, when each buffer only captures two data buses, 'cba_bus_sel' determines which two buses to be captured at the selected node specified by 'cba_sel': */
676 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_BUS_SEL_MASK (0x00000100u)
677 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_BUS_SEL_SHIFT (0x00000008u)
678 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_BUS_SEL_RESETVAL (0x00000000u)
680 /* Indicate whehter capture buffer A is capturing reference signal or feedback signal, which it is doing cb-c or cb-f: */
681 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_REF_OR_FB_MASK (0x00003000u)
682 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_REF_OR_FB_SHIFT (0x0000000Cu)
683 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_REF_OR_FB_RESETVAL (0x00000000u)
685 /* 0 = capture buffer A is used for capture. Capture buffer A has to be done before 'cb_interrupt' is issued */
686 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_NOT_USED_MASK (0x00010000u)
687 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_NOT_USED_SHIFT (0x00000010u)
688 #define CSL_DFE_CB_CBA_SETTING_REG_CBA_NOT_USED_RESETVAL (0x00000000u)
690 #define CSL_DFE_CB_CBA_SETTING_REG_ADDR (0x00000210u)
691 #define CSL_DFE_CB_CBA_SETTING_REG_RESETVAL (0x00000000u)
693 /* CBA_DLY */
694 typedef struct
695 {
696 #ifdef _BIG_ENDIAN
697 Uint32 cba_dly : 32;
698 #else
699 Uint32 cba_dly : 32;
700 #endif
701 } CSL_DFE_CB_CBA_DLY_REG;
703 /* Capture buffer delay from sync (or 'trigger_stop' in trigger mode) to stop capturing, can also be used to accommodate the latency between reference signal and feedback signal unless in multicapture mode, then we have to use 'cba_start_delay'. */
704 #define CSL_DFE_CB_CBA_DLY_REG_CBA_DLY_MASK (0xFFFFFFFFu)
705 #define CSL_DFE_CB_CBA_DLY_REG_CBA_DLY_SHIFT (0x00000000u)
706 #define CSL_DFE_CB_CBA_DLY_REG_CBA_DLY_RESETVAL (0x00000000u)
708 #define CSL_DFE_CB_CBA_DLY_REG_ADDR (0x00000214u)
709 #define CSL_DFE_CB_CBA_DLY_REG_RESETVAL (0x00000000u)
711 /* CBB_SETTING */
712 typedef struct
713 {
714 #ifdef _BIG_ENDIAN
715 Uint32 rsvd3 : 15;
716 Uint32 cbb_not_used : 1;
717 Uint32 rsvd2 : 2;
718 Uint32 cbb_ref_or_fb : 2;
719 Uint32 rsvd1 : 3;
720 Uint32 cbb_bus_sel : 1;
721 Uint32 cbb_sel : 4;
722 Uint32 rsvd0 : 4;
723 #else
724 Uint32 rsvd0 : 4;
725 Uint32 cbb_sel : 4;
726 Uint32 cbb_bus_sel : 1;
727 Uint32 rsvd1 : 3;
728 Uint32 cbb_ref_or_fb : 2;
729 Uint32 rsvd2 : 2;
730 Uint32 cbb_not_used : 1;
731 Uint32 rsvd3 : 15;
732 #endif
733 } CSL_DFE_CB_CBB_SETTING_REG;
735 /* same as cba_sel */
736 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_SEL_MASK (0x000000F0u)
737 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_SEL_SHIFT (0x00000004u)
738 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_SEL_RESETVAL (0x00000000u)
740 /* same as cba_bus_sel */
741 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_BUS_SEL_MASK (0x00000100u)
742 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_BUS_SEL_SHIFT (0x00000008u)
743 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_BUS_SEL_RESETVAL (0x00000000u)
745 /* same as cba_ref_or_fb */
746 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_REF_OR_FB_MASK (0x00003000u)
747 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_REF_OR_FB_SHIFT (0x0000000Cu)
748 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_REF_OR_FB_RESETVAL (0x00000000u)
750 /* 0 = capture buffer B is used for capture. Capture buffer B has to be done before 'cb_interrupt' is issued */
751 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_NOT_USED_MASK (0x00010000u)
752 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_NOT_USED_SHIFT (0x00000010u)
753 #define CSL_DFE_CB_CBB_SETTING_REG_CBB_NOT_USED_RESETVAL (0x00000000u)
755 #define CSL_DFE_CB_CBB_SETTING_REG_ADDR (0x00000218u)
756 #define CSL_DFE_CB_CBB_SETTING_REG_RESETVAL (0x00000000u)
758 /* CBB_DLY */
759 typedef struct
760 {
761 #ifdef _BIG_ENDIAN
762 Uint32 cbb_dly : 32;
763 #else
764 Uint32 cbb_dly : 32;
765 #endif
766 } CSL_DFE_CB_CBB_DLY_REG;
768 /* same as cba_dly */
769 #define CSL_DFE_CB_CBB_DLY_REG_CBB_DLY_MASK (0xFFFFFFFFu)
770 #define CSL_DFE_CB_CBB_DLY_REG_CBB_DLY_SHIFT (0x00000000u)
771 #define CSL_DFE_CB_CBB_DLY_REG_CBB_DLY_RESETVAL (0x00000000u)
773 #define CSL_DFE_CB_CBB_DLY_REG_ADDR (0x0000021Cu)
774 #define CSL_DFE_CB_CBB_DLY_REG_RESETVAL (0x00000000u)
776 /* CBC_SETTING */
777 typedef struct
778 {
779 #ifdef _BIG_ENDIAN
780 Uint32 rsvd3 : 15;
781 Uint32 cbc_not_used : 1;
782 Uint32 rsvd2 : 2;
783 Uint32 cbc_ref_or_fb : 2;
784 Uint32 rsvd1 : 3;
785 Uint32 cbc_bus_sel : 1;
786 Uint32 cbc_sel : 4;
787 Uint32 rsvd0 : 4;
788 #else
789 Uint32 rsvd0 : 4;
790 Uint32 cbc_sel : 4;
791 Uint32 cbc_bus_sel : 1;
792 Uint32 rsvd1 : 3;
793 Uint32 cbc_ref_or_fb : 2;
794 Uint32 rsvd2 : 2;
795 Uint32 cbc_not_used : 1;
796 Uint32 rsvd3 : 15;
797 #endif
798 } CSL_DFE_CB_CBC_SETTING_REG;
800 /* same as cba_sel */
801 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_SEL_MASK (0x000000F0u)
802 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_SEL_SHIFT (0x00000004u)
803 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_SEL_RESETVAL (0x00000000u)
805 /* same as cba_bus_sel */
806 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_BUS_SEL_MASK (0x00000100u)
807 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_BUS_SEL_SHIFT (0x00000008u)
808 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_BUS_SEL_RESETVAL (0x00000000u)
810 /* same as cba_ref_or_fb */
811 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_REF_OR_FB_MASK (0x00003000u)
812 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_REF_OR_FB_SHIFT (0x0000000Cu)
813 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_REF_OR_FB_RESETVAL (0x00000000u)
815 /* 0 = capture buffer C is used for capture. Capture buffer C has to be done before 'cb_interrupt' is issued */
816 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_NOT_USED_MASK (0x00010000u)
817 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_NOT_USED_SHIFT (0x00000010u)
818 #define CSL_DFE_CB_CBC_SETTING_REG_CBC_NOT_USED_RESETVAL (0x00000000u)
820 #define CSL_DFE_CB_CBC_SETTING_REG_ADDR (0x00000220u)
821 #define CSL_DFE_CB_CBC_SETTING_REG_RESETVAL (0x00000000u)
823 /* CBC_DLY */
824 typedef struct
825 {
826 #ifdef _BIG_ENDIAN
827 Uint32 cbc_dly : 32;
828 #else
829 Uint32 cbc_dly : 32;
830 #endif
831 } CSL_DFE_CB_CBC_DLY_REG;
833 /* same as cba_dly */
834 #define CSL_DFE_CB_CBC_DLY_REG_CBC_DLY_MASK (0xFFFFFFFFu)
835 #define CSL_DFE_CB_CBC_DLY_REG_CBC_DLY_SHIFT (0x00000000u)
836 #define CSL_DFE_CB_CBC_DLY_REG_CBC_DLY_RESETVAL (0x00000000u)
838 #define CSL_DFE_CB_CBC_DLY_REG_ADDR (0x00000224u)
839 #define CSL_DFE_CB_CBC_DLY_REG_RESETVAL (0x00000000u)
841 /* CBD_SETTING */
842 typedef struct
843 {
844 #ifdef _BIG_ENDIAN
845 Uint32 rsvd3 : 15;
846 Uint32 cbd_not_used : 1;
847 Uint32 rsvd2 : 2;
848 Uint32 cbd_ref_or_fb : 2;
849 Uint32 rsvd1 : 3;
850 Uint32 cbd_bus_sel : 1;
851 Uint32 cbd_sel : 4;
852 Uint32 rsvd0 : 4;
853 #else
854 Uint32 rsvd0 : 4;
855 Uint32 cbd_sel : 4;
856 Uint32 cbd_bus_sel : 1;
857 Uint32 rsvd1 : 3;
858 Uint32 cbd_ref_or_fb : 2;
859 Uint32 rsvd2 : 2;
860 Uint32 cbd_not_used : 1;
861 Uint32 rsvd3 : 15;
862 #endif
863 } CSL_DFE_CB_CBD_SETTING_REG;
865 /* same as cba_sel */
866 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_SEL_MASK (0x000000F0u)
867 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_SEL_SHIFT (0x00000004u)
868 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_SEL_RESETVAL (0x00000000u)
870 /* same as cba_bus_sel */
871 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_BUS_SEL_MASK (0x00000100u)
872 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_BUS_SEL_SHIFT (0x00000008u)
873 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_BUS_SEL_RESETVAL (0x00000000u)
875 /* same as cba_ref_or_fb */
876 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_REF_OR_FB_MASK (0x00003000u)
877 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_REF_OR_FB_SHIFT (0x0000000Cu)
878 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_REF_OR_FB_RESETVAL (0x00000000u)
880 /* 0 = capture buffer D is used for capture. Capture buffer D has to be done before 'cb_interrupt' is issued */
881 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_NOT_USED_MASK (0x00010000u)
882 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_NOT_USED_SHIFT (0x00000010u)
883 #define CSL_DFE_CB_CBD_SETTING_REG_CBD_NOT_USED_RESETVAL (0x00000000u)
885 #define CSL_DFE_CB_CBD_SETTING_REG_ADDR (0x00000228u)
886 #define CSL_DFE_CB_CBD_SETTING_REG_RESETVAL (0x00000000u)
888 /* CBD_DLY */
889 typedef struct
890 {
891 #ifdef _BIG_ENDIAN
892 Uint32 cbd_dly : 32;
893 #else
894 Uint32 cbd_dly : 32;
895 #endif
896 } CSL_DFE_CB_CBD_DLY_REG;
898 /* same as cba_dly */
899 #define CSL_DFE_CB_CBD_DLY_REG_CBD_DLY_MASK (0xFFFFFFFFu)
900 #define CSL_DFE_CB_CBD_DLY_REG_CBD_DLY_SHIFT (0x00000000u)
901 #define CSL_DFE_CB_CBD_DLY_REG_CBD_DLY_RESETVAL (0x00000000u)
903 #define CSL_DFE_CB_CBD_DLY_REG_ADDR (0x0000022Cu)
904 #define CSL_DFE_CB_CBD_DLY_REG_RESETVAL (0x00000000u)
906 /* RATE_MODE */
907 typedef struct
908 {
909 #ifdef _BIG_ENDIAN
910 Uint32 rsvd0 : 28;
911 Uint32 cbd_rate_mode : 1;
912 Uint32 cbc_rate_mode : 1;
913 Uint32 cbb_rate_mode : 1;
914 Uint32 cba_rate_mode : 1;
915 #else
916 Uint32 cba_rate_mode : 1;
917 Uint32 cbb_rate_mode : 1;
918 Uint32 cbc_rate_mode : 1;
919 Uint32 cbd_rate_mode : 1;
920 Uint32 rsvd0 : 28;
921 #endif
922 } CSL_DFE_CB_RATE_MODE_REG;
924 /* 0 = 1s/1c mode, can capture up to two selected data buses */
925 #define CSL_DFE_CB_RATE_MODE_REG_CBA_RATE_MODE_MASK (0x00000001u)
926 #define CSL_DFE_CB_RATE_MODE_REG_CBA_RATE_MODE_SHIFT (0x00000000u)
927 #define CSL_DFE_CB_RATE_MODE_REG_CBA_RATE_MODE_RESETVAL (0x00000000u)
929 /* same as cba_rate_mode */
930 #define CSL_DFE_CB_RATE_MODE_REG_CBB_RATE_MODE_MASK (0x00000002u)
931 #define CSL_DFE_CB_RATE_MODE_REG_CBB_RATE_MODE_SHIFT (0x00000001u)
932 #define CSL_DFE_CB_RATE_MODE_REG_CBB_RATE_MODE_RESETVAL (0x00000000u)
934 /* same as cba_rate_mode */
935 #define CSL_DFE_CB_RATE_MODE_REG_CBC_RATE_MODE_MASK (0x00000004u)
936 #define CSL_DFE_CB_RATE_MODE_REG_CBC_RATE_MODE_SHIFT (0x00000002u)
937 #define CSL_DFE_CB_RATE_MODE_REG_CBC_RATE_MODE_RESETVAL (0x00000000u)
939 /* same as cba_rate_mode */
940 #define CSL_DFE_CB_RATE_MODE_REG_CBD_RATE_MODE_MASK (0x00000008u)
941 #define CSL_DFE_CB_RATE_MODE_REG_CBD_RATE_MODE_SHIFT (0x00000003u)
942 #define CSL_DFE_CB_RATE_MODE_REG_CBD_RATE_MODE_RESETVAL (0x00000000u)
944 #define CSL_DFE_CB_RATE_MODE_REG_ADDR (0x00000230u)
945 #define CSL_DFE_CB_RATE_MODE_REG_RESETVAL (0x00000000u)
947 /* NODE0_CONFIG */
948 typedef struct
949 {
950 #ifdef _BIG_ENDIAN
951 Uint32 rsvd7 : 1;
952 Uint32 node0_q1fsdly : 3;
953 Uint32 rsvd6 : 1;
954 Uint32 node0_i1fsdly : 3;
955 Uint32 rsvd5 : 1;
956 Uint32 node0_q0fsdly : 3;
957 Uint32 rsvd4 : 1;
958 Uint32 node0_i0fsdly : 3;
959 Uint32 rsvd3 : 1;
960 Uint32 node0_q1bus_sel : 3;
961 Uint32 rsvd2 : 1;
962 Uint32 node0_i1bus_sel : 3;
963 Uint32 rsvd1 : 1;
964 Uint32 node0_q0bus_sel : 3;
965 Uint32 rsvd0 : 1;
966 Uint32 node0_i0bus_sel : 3;
967 #else
968 Uint32 node0_i0bus_sel : 3;
969 Uint32 rsvd0 : 1;
970 Uint32 node0_q0bus_sel : 3;
971 Uint32 rsvd1 : 1;
972 Uint32 node0_i1bus_sel : 3;
973 Uint32 rsvd2 : 1;
974 Uint32 node0_q1bus_sel : 3;
975 Uint32 rsvd3 : 1;
976 Uint32 node0_i0fsdly : 3;
977 Uint32 rsvd4 : 1;
978 Uint32 node0_q0fsdly : 3;
979 Uint32 rsvd5 : 1;
980 Uint32 node0_i1fsdly : 3;
981 Uint32 rsvd6 : 1;
982 Uint32 node0_q1fsdly : 3;
983 Uint32 rsvd7 : 1;
984 #endif
985 } CSL_DFE_CB_NODE0_CONFIG_REG;
987 /* choose between bus0 ~bus7 for I0 data, if total number of buses at a capture node is less than 8, then some buses will be duplicated. */
988 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I0BUS_SEL_MASK (0x00000007u)
989 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I0BUS_SEL_SHIFT (0x00000000u)
990 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I0BUS_SEL_RESETVAL (0x00000000u)
992 /* choose between bus0 ~bus7 for Q0 data. */
993 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q0BUS_SEL_MASK (0x00000070u)
994 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q0BUS_SEL_SHIFT (0x00000004u)
995 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q0BUS_SEL_RESETVAL (0x00000000u)
997 /* choose between bus0 ~bus7 for I1 data. Only matters in 2s/1c mode or in multiband case. */
998 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I1BUS_SEL_MASK (0x00000700u)
999 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I1BUS_SEL_SHIFT (0x00000008u)
1000 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I1BUS_SEL_RESETVAL (0x00000000u)
1002 /* choose between bus0 ~bus7 for Q1 data. Only matters in 2s/1c mode or in multiband case. */
1003 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q1BUS_SEL_MASK (0x00007000u)
1004 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q1BUS_SEL_SHIFT (0x0000000Cu)
1005 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q1BUS_SEL_RESETVAL (0x00000000u)
1007 /* I0 data delay locaton relative to frame start on the corresponding selected bus. */
1008 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I0FSDLY_MASK (0x00070000u)
1009 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I0FSDLY_SHIFT (0x00000010u)
1010 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I0FSDLY_RESETVAL (0x00000000u)
1012 /* Q0 data delay locaton relative to frame start on the corresponding selected bus. */
1013 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q0FSDLY_MASK (0x00700000u)
1014 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q0FSDLY_SHIFT (0x00000014u)
1015 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q0FSDLY_RESETVAL (0x00000000u)
1017 /* I1 data delay locaton relative to frame start on the corresponding selected bus. */
1018 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I1FSDLY_MASK (0x07000000u)
1019 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I1FSDLY_SHIFT (0x00000018u)
1020 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_I1FSDLY_RESETVAL (0x00000000u)
1022 /* Q1 data delay locaton relative to frame start on the corresponding selected bus. */
1023 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q1FSDLY_MASK (0x70000000u)
1024 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q1FSDLY_SHIFT (0x0000001Cu)
1025 #define CSL_DFE_CB_NODE0_CONFIG_REG_NODE0_Q1FSDLY_RESETVAL (0x00000000u)
1027 #define CSL_DFE_CB_NODE0_CONFIG_REG_ADDR (0x00000234u)
1028 #define CSL_DFE_CB_NODE0_CONFIG_REG_RESETVAL (0x00000000u)
1030 /* NODE0_FSF_FSFM */
1031 typedef struct
1032 {
1033 #ifdef _BIG_ENDIAN
1034 Uint32 rsvd0 : 28;
1035 Uint32 node0_fsfm : 2;
1036 Uint32 node0_fsf : 2;
1037 #else
1038 Uint32 node0_fsf : 2;
1039 Uint32 node0_fsfm : 2;
1040 Uint32 rsvd0 : 28;
1041 #endif
1042 } CSL_DFE_CB_NODE0_FSF_FSFM_REG;
1044 /* frame strobe format; need to program the 2-bit combination of */
1045 #define CSL_DFE_CB_NODE0_FSF_FSFM_REG_NODE0_FSF_MASK (0x00000003u)
1046 #define CSL_DFE_CB_NODE0_FSF_FSFM_REG_NODE0_FSF_SHIFT (0x00000000u)
1047 #define CSL_DFE_CB_NODE0_FSF_FSFM_REG_NODE0_FSF_RESETVAL (0x00000000u)
1049 /* frame strobe format mask; program a 0 in bit locations where it is desired to mask out those bits in the 'frame strobe format'. */
1050 #define CSL_DFE_CB_NODE0_FSF_FSFM_REG_NODE0_FSFM_MASK (0x0000000Cu)
1051 #define CSL_DFE_CB_NODE0_FSF_FSFM_REG_NODE0_FSFM_SHIFT (0x00000002u)
1052 #define CSL_DFE_CB_NODE0_FSF_FSFM_REG_NODE0_FSFM_RESETVAL (0x00000000u)
1054 #define CSL_DFE_CB_NODE0_FSF_FSFM_REG_ADDR (0x00000238u)
1055 #define CSL_DFE_CB_NODE0_FSF_FSFM_REG_RESETVAL (0x00000000u)
1057 /* NODE1_CONFIG */
1058 typedef struct
1059 {
1060 #ifdef _BIG_ENDIAN
1061 Uint32 rsvd7 : 1;
1062 Uint32 node1_q1fsdly : 3;
1063 Uint32 rsvd6 : 1;
1064 Uint32 node1_i1fsdly : 3;
1065 Uint32 rsvd5 : 1;
1066 Uint32 node1_q0fsdly : 3;
1067 Uint32 rsvd4 : 1;
1068 Uint32 node1_i0fsdly : 3;
1069 Uint32 rsvd3 : 1;
1070 Uint32 node1_q1bus_sel : 3;
1071 Uint32 rsvd2 : 1;
1072 Uint32 node1_i1bus_sel : 3;
1073 Uint32 rsvd1 : 1;
1074 Uint32 node1_q0bus_sel : 3;
1075 Uint32 rsvd0 : 1;
1076 Uint32 node1_i0bus_sel : 3;
1077 #else
1078 Uint32 node1_i0bus_sel : 3;
1079 Uint32 rsvd0 : 1;
1080 Uint32 node1_q0bus_sel : 3;
1081 Uint32 rsvd1 : 1;
1082 Uint32 node1_i1bus_sel : 3;
1083 Uint32 rsvd2 : 1;
1084 Uint32 node1_q1bus_sel : 3;
1085 Uint32 rsvd3 : 1;
1086 Uint32 node1_i0fsdly : 3;
1087 Uint32 rsvd4 : 1;
1088 Uint32 node1_q0fsdly : 3;
1089 Uint32 rsvd5 : 1;
1090 Uint32 node1_i1fsdly : 3;
1091 Uint32 rsvd6 : 1;
1092 Uint32 node1_q1fsdly : 3;
1093 Uint32 rsvd7 : 1;
1094 #endif
1095 } CSL_DFE_CB_NODE1_CONFIG_REG;
1097 /* see definition of corresponding register for node0. */
1098 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I0BUS_SEL_MASK (0x00000007u)
1099 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I0BUS_SEL_SHIFT (0x00000000u)
1100 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I0BUS_SEL_RESETVAL (0x00000000u)
1102 /* see definition of corresponding register for node0. */
1103 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q0BUS_SEL_MASK (0x00000070u)
1104 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q0BUS_SEL_SHIFT (0x00000004u)
1105 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q0BUS_SEL_RESETVAL (0x00000000u)
1107 /* see definition of corresponding register for node0. */
1108 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I1BUS_SEL_MASK (0x00000700u)
1109 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I1BUS_SEL_SHIFT (0x00000008u)
1110 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I1BUS_SEL_RESETVAL (0x00000000u)
1112 /* see definition of corresponding register for node0. */
1113 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q1BUS_SEL_MASK (0x00007000u)
1114 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q1BUS_SEL_SHIFT (0x0000000Cu)
1115 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q1BUS_SEL_RESETVAL (0x00000000u)
1117 /* see definition of corresponding register for node0. */
1118 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I0FSDLY_MASK (0x00070000u)
1119 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I0FSDLY_SHIFT (0x00000010u)
1120 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I0FSDLY_RESETVAL (0x00000000u)
1122 /* see definition of corresponding register for node0. */
1123 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q0FSDLY_MASK (0x00700000u)
1124 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q0FSDLY_SHIFT (0x00000014u)
1125 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q0FSDLY_RESETVAL (0x00000000u)
1127 /* see definition of corresponding register for node0. */
1128 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I1FSDLY_MASK (0x07000000u)
1129 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I1FSDLY_SHIFT (0x00000018u)
1130 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_I1FSDLY_RESETVAL (0x00000000u)
1132 /* see definition of corresponding register for node0. */
1133 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q1FSDLY_MASK (0x70000000u)
1134 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q1FSDLY_SHIFT (0x0000001Cu)
1135 #define CSL_DFE_CB_NODE1_CONFIG_REG_NODE1_Q1FSDLY_RESETVAL (0x00000000u)
1137 #define CSL_DFE_CB_NODE1_CONFIG_REG_ADDR (0x0000023Cu)
1138 #define CSL_DFE_CB_NODE1_CONFIG_REG_RESETVAL (0x00000000u)
1140 /* NODE1_FSF_FSFM */
1141 typedef struct
1142 {
1143 #ifdef _BIG_ENDIAN
1144 Uint32 rsvd0 : 28;
1145 Uint32 node1_fsfm : 2;
1146 Uint32 node1_fsf : 2;
1147 #else
1148 Uint32 node1_fsf : 2;
1149 Uint32 node1_fsfm : 2;
1150 Uint32 rsvd0 : 28;
1151 #endif
1152 } CSL_DFE_CB_NODE1_FSF_FSFM_REG;
1154 /* see definition of corresponding register for node0. */
1155 #define CSL_DFE_CB_NODE1_FSF_FSFM_REG_NODE1_FSF_MASK (0x00000003u)
1156 #define CSL_DFE_CB_NODE1_FSF_FSFM_REG_NODE1_FSF_SHIFT (0x00000000u)
1157 #define CSL_DFE_CB_NODE1_FSF_FSFM_REG_NODE1_FSF_RESETVAL (0x00000000u)
1159 /* see definition of corresponding register for node0. */
1160 #define CSL_DFE_CB_NODE1_FSF_FSFM_REG_NODE1_FSFM_MASK (0x0000000Cu)
1161 #define CSL_DFE_CB_NODE1_FSF_FSFM_REG_NODE1_FSFM_SHIFT (0x00000002u)
1162 #define CSL_DFE_CB_NODE1_FSF_FSFM_REG_NODE1_FSFM_RESETVAL (0x00000000u)
1164 #define CSL_DFE_CB_NODE1_FSF_FSFM_REG_ADDR (0x00000240u)
1165 #define CSL_DFE_CB_NODE1_FSF_FSFM_REG_RESETVAL (0x00000000u)
1167 /* NODE2_CONFIG */
1168 typedef struct
1169 {
1170 #ifdef _BIG_ENDIAN
1171 Uint32 rsvd7 : 1;
1172 Uint32 node2_q1fsdly : 3;
1173 Uint32 rsvd6 : 1;
1174 Uint32 node2_i1fsdly : 3;
1175 Uint32 rsvd5 : 1;
1176 Uint32 node2_q0fsdly : 3;
1177 Uint32 rsvd4 : 1;
1178 Uint32 node2_i0fsdly : 3;
1179 Uint32 rsvd3 : 1;
1180 Uint32 node2_q1bus_sel : 3;
1181 Uint32 rsvd2 : 1;
1182 Uint32 node2_i1bus_sel : 3;
1183 Uint32 rsvd1 : 1;
1184 Uint32 node2_q0bus_sel : 3;
1185 Uint32 rsvd0 : 1;
1186 Uint32 node2_i0bus_sel : 3;
1187 #else
1188 Uint32 node2_i0bus_sel : 3;
1189 Uint32 rsvd0 : 1;
1190 Uint32 node2_q0bus_sel : 3;
1191 Uint32 rsvd1 : 1;
1192 Uint32 node2_i1bus_sel : 3;
1193 Uint32 rsvd2 : 1;
1194 Uint32 node2_q1bus_sel : 3;
1195 Uint32 rsvd3 : 1;
1196 Uint32 node2_i0fsdly : 3;
1197 Uint32 rsvd4 : 1;
1198 Uint32 node2_q0fsdly : 3;
1199 Uint32 rsvd5 : 1;
1200 Uint32 node2_i1fsdly : 3;
1201 Uint32 rsvd6 : 1;
1202 Uint32 node2_q1fsdly : 3;
1203 Uint32 rsvd7 : 1;
1204 #endif
1205 } CSL_DFE_CB_NODE2_CONFIG_REG;
1207 /* see definition of corresponding register for node0. */
1208 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I0BUS_SEL_MASK (0x00000007u)
1209 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I0BUS_SEL_SHIFT (0x00000000u)
1210 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I0BUS_SEL_RESETVAL (0x00000000u)
1212 /* see definition of corresponding register for node0. */
1213 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q0BUS_SEL_MASK (0x00000070u)
1214 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q0BUS_SEL_SHIFT (0x00000004u)
1215 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q0BUS_SEL_RESETVAL (0x00000000u)
1217 /* see definition of corresponding register for node0. */
1218 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I1BUS_SEL_MASK (0x00000700u)
1219 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I1BUS_SEL_SHIFT (0x00000008u)
1220 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I1BUS_SEL_RESETVAL (0x00000000u)
1222 /* see definition of corresponding register for node0. */
1223 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q1BUS_SEL_MASK (0x00007000u)
1224 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q1BUS_SEL_SHIFT (0x0000000Cu)
1225 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q1BUS_SEL_RESETVAL (0x00000000u)
1227 /* see definition of corresponding register for node0. */
1228 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I0FSDLY_MASK (0x00070000u)
1229 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I0FSDLY_SHIFT (0x00000010u)
1230 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I0FSDLY_RESETVAL (0x00000000u)
1232 /* see definition of corresponding register for node0. */
1233 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q0FSDLY_MASK (0x00700000u)
1234 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q0FSDLY_SHIFT (0x00000014u)
1235 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q0FSDLY_RESETVAL (0x00000000u)
1237 /* see definition of corresponding register for node0. */
1238 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I1FSDLY_MASK (0x07000000u)
1239 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I1FSDLY_SHIFT (0x00000018u)
1240 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_I1FSDLY_RESETVAL (0x00000000u)
1242 /* see definition of corresponding register for node0. */
1243 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q1FSDLY_MASK (0x70000000u)
1244 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q1FSDLY_SHIFT (0x0000001Cu)
1245 #define CSL_DFE_CB_NODE2_CONFIG_REG_NODE2_Q1FSDLY_RESETVAL (0x00000000u)
1247 #define CSL_DFE_CB_NODE2_CONFIG_REG_ADDR (0x00000244u)
1248 #define CSL_DFE_CB_NODE2_CONFIG_REG_RESETVAL (0x00000000u)
1250 /* NODE2_FSF_FSFM */
1251 typedef struct
1252 {
1253 #ifdef _BIG_ENDIAN
1254 Uint32 rsvd0 : 28;
1255 Uint32 node2_fsfm : 2;
1256 Uint32 node2_fsf : 2;
1257 #else
1258 Uint32 node2_fsf : 2;
1259 Uint32 node2_fsfm : 2;
1260 Uint32 rsvd0 : 28;
1261 #endif
1262 } CSL_DFE_CB_NODE2_FSF_FSFM_REG;
1264 /* see definition of corresponding register for node0. */
1265 #define CSL_DFE_CB_NODE2_FSF_FSFM_REG_NODE2_FSF_MASK (0x00000003u)
1266 #define CSL_DFE_CB_NODE2_FSF_FSFM_REG_NODE2_FSF_SHIFT (0x00000000u)
1267 #define CSL_DFE_CB_NODE2_FSF_FSFM_REG_NODE2_FSF_RESETVAL (0x00000000u)
1269 /* see definition of corresponding register for node0. */
1270 #define CSL_DFE_CB_NODE2_FSF_FSFM_REG_NODE2_FSFM_MASK (0x0000000Cu)
1271 #define CSL_DFE_CB_NODE2_FSF_FSFM_REG_NODE2_FSFM_SHIFT (0x00000002u)
1272 #define CSL_DFE_CB_NODE2_FSF_FSFM_REG_NODE2_FSFM_RESETVAL (0x00000000u)
1274 #define CSL_DFE_CB_NODE2_FSF_FSFM_REG_ADDR (0x00000248u)
1275 #define CSL_DFE_CB_NODE2_FSF_FSFM_REG_RESETVAL (0x00000000u)
1277 /* NODE3_CONFIG */
1278 typedef struct
1279 {
1280 #ifdef _BIG_ENDIAN
1281 Uint32 rsvd7 : 1;
1282 Uint32 node3_q1fsdly : 3;
1283 Uint32 rsvd6 : 1;
1284 Uint32 node3_i1fsdly : 3;
1285 Uint32 rsvd5 : 1;
1286 Uint32 node3_q0fsdly : 3;
1287 Uint32 rsvd4 : 1;
1288 Uint32 node3_i0fsdly : 3;
1289 Uint32 rsvd3 : 1;
1290 Uint32 node3_q1bus_sel : 3;
1291 Uint32 rsvd2 : 1;
1292 Uint32 node3_i1bus_sel : 3;
1293 Uint32 rsvd1 : 1;
1294 Uint32 node3_q0bus_sel : 3;
1295 Uint32 rsvd0 : 1;
1296 Uint32 node3_i0bus_sel : 3;
1297 #else
1298 Uint32 node3_i0bus_sel : 3;
1299 Uint32 rsvd0 : 1;
1300 Uint32 node3_q0bus_sel : 3;
1301 Uint32 rsvd1 : 1;
1302 Uint32 node3_i1bus_sel : 3;
1303 Uint32 rsvd2 : 1;
1304 Uint32 node3_q1bus_sel : 3;
1305 Uint32 rsvd3 : 1;
1306 Uint32 node3_i0fsdly : 3;
1307 Uint32 rsvd4 : 1;
1308 Uint32 node3_q0fsdly : 3;
1309 Uint32 rsvd5 : 1;
1310 Uint32 node3_i1fsdly : 3;
1311 Uint32 rsvd6 : 1;
1312 Uint32 node3_q1fsdly : 3;
1313 Uint32 rsvd7 : 1;
1314 #endif
1315 } CSL_DFE_CB_NODE3_CONFIG_REG;
1317 /* see definition of corresponding register for node0. */
1318 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I0BUS_SEL_MASK (0x00000007u)
1319 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I0BUS_SEL_SHIFT (0x00000000u)
1320 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I0BUS_SEL_RESETVAL (0x00000000u)
1322 /* see definition of corresponding register for node0. */
1323 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q0BUS_SEL_MASK (0x00000070u)
1324 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q0BUS_SEL_SHIFT (0x00000004u)
1325 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q0BUS_SEL_RESETVAL (0x00000000u)
1327 /* see definition of corresponding register for node0. */
1328 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I1BUS_SEL_MASK (0x00000700u)
1329 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I1BUS_SEL_SHIFT (0x00000008u)
1330 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I1BUS_SEL_RESETVAL (0x00000000u)
1332 /* see definition of corresponding register for node0. */
1333 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q1BUS_SEL_MASK (0x00007000u)
1334 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q1BUS_SEL_SHIFT (0x0000000Cu)
1335 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q1BUS_SEL_RESETVAL (0x00000000u)
1337 /* see definition of corresponding register for node0. */
1338 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I0FSDLY_MASK (0x00070000u)
1339 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I0FSDLY_SHIFT (0x00000010u)
1340 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I0FSDLY_RESETVAL (0x00000000u)
1342 /* see definition of corresponding register for node0. */
1343 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q0FSDLY_MASK (0x00700000u)
1344 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q0FSDLY_SHIFT (0x00000014u)
1345 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q0FSDLY_RESETVAL (0x00000000u)
1347 /* see definition of corresponding register for node0. */
1348 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I1FSDLY_MASK (0x07000000u)
1349 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I1FSDLY_SHIFT (0x00000018u)
1350 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_I1FSDLY_RESETVAL (0x00000000u)
1352 /* see definition of corresponding register for node0. */
1353 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q1FSDLY_MASK (0x70000000u)
1354 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q1FSDLY_SHIFT (0x0000001Cu)
1355 #define CSL_DFE_CB_NODE3_CONFIG_REG_NODE3_Q1FSDLY_RESETVAL (0x00000000u)
1357 #define CSL_DFE_CB_NODE3_CONFIG_REG_ADDR (0x0000024Cu)
1358 #define CSL_DFE_CB_NODE3_CONFIG_REG_RESETVAL (0x00000000u)
1360 /* NODE3_FSF_FSFM */
1361 typedef struct
1362 {
1363 #ifdef _BIG_ENDIAN
1364 Uint32 rsvd0 : 28;
1365 Uint32 node3_fsfm : 2;
1366 Uint32 node3_fsf : 2;
1367 #else
1368 Uint32 node3_fsf : 2;
1369 Uint32 node3_fsfm : 2;
1370 Uint32 rsvd0 : 28;
1371 #endif
1372 } CSL_DFE_CB_NODE3_FSF_FSFM_REG;
1374 /* see definition of corresponding register for node0. */
1375 #define CSL_DFE_CB_NODE3_FSF_FSFM_REG_NODE3_FSF_MASK (0x00000003u)
1376 #define CSL_DFE_CB_NODE3_FSF_FSFM_REG_NODE3_FSF_SHIFT (0x00000000u)
1377 #define CSL_DFE_CB_NODE3_FSF_FSFM_REG_NODE3_FSF_RESETVAL (0x00000000u)
1379 /* see definition of corresponding register for node0. */
1380 #define CSL_DFE_CB_NODE3_FSF_FSFM_REG_NODE3_FSFM_MASK (0x0000000Cu)
1381 #define CSL_DFE_CB_NODE3_FSF_FSFM_REG_NODE3_FSFM_SHIFT (0x00000002u)
1382 #define CSL_DFE_CB_NODE3_FSF_FSFM_REG_NODE3_FSFM_RESETVAL (0x00000000u)
1384 #define CSL_DFE_CB_NODE3_FSF_FSFM_REG_ADDR (0x00000250u)
1385 #define CSL_DFE_CB_NODE3_FSF_FSFM_REG_RESETVAL (0x00000000u)
1387 /* NODE4_CONFIG */
1388 typedef struct
1389 {
1390 #ifdef _BIG_ENDIAN
1391 Uint32 rsvd7 : 1;
1392 Uint32 node4_q1fsdly : 3;
1393 Uint32 rsvd6 : 1;
1394 Uint32 node4_i1fsdly : 3;
1395 Uint32 rsvd5 : 1;
1396 Uint32 node4_q0fsdly : 3;
1397 Uint32 rsvd4 : 1;
1398 Uint32 node4_i0fsdly : 3;
1399 Uint32 rsvd3 : 1;
1400 Uint32 node4_q1bus_sel : 3;
1401 Uint32 rsvd2 : 1;
1402 Uint32 node4_i1bus_sel : 3;
1403 Uint32 rsvd1 : 1;
1404 Uint32 node4_q0bus_sel : 3;
1405 Uint32 rsvd0 : 1;
1406 Uint32 node4_i0bus_sel : 3;
1407 #else
1408 Uint32 node4_i0bus_sel : 3;
1409 Uint32 rsvd0 : 1;
1410 Uint32 node4_q0bus_sel : 3;
1411 Uint32 rsvd1 : 1;
1412 Uint32 node4_i1bus_sel : 3;
1413 Uint32 rsvd2 : 1;
1414 Uint32 node4_q1bus_sel : 3;
1415 Uint32 rsvd3 : 1;
1416 Uint32 node4_i0fsdly : 3;
1417 Uint32 rsvd4 : 1;
1418 Uint32 node4_q0fsdly : 3;
1419 Uint32 rsvd5 : 1;
1420 Uint32 node4_i1fsdly : 3;
1421 Uint32 rsvd6 : 1;
1422 Uint32 node4_q1fsdly : 3;
1423 Uint32 rsvd7 : 1;
1424 #endif
1425 } CSL_DFE_CB_NODE4_CONFIG_REG;
1427 /* see definition of corresponding register for node0. */
1428 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I0BUS_SEL_MASK (0x00000007u)
1429 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I0BUS_SEL_SHIFT (0x00000000u)
1430 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I0BUS_SEL_RESETVAL (0x00000000u)
1432 /* see definition of corresponding register for node0. */
1433 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q0BUS_SEL_MASK (0x00000070u)
1434 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q0BUS_SEL_SHIFT (0x00000004u)
1435 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q0BUS_SEL_RESETVAL (0x00000000u)
1437 /* see definition of corresponding register for node0. */
1438 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I1BUS_SEL_MASK (0x00000700u)
1439 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I1BUS_SEL_SHIFT (0x00000008u)
1440 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I1BUS_SEL_RESETVAL (0x00000000u)
1442 /* see definition of corresponding register for node0. */
1443 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q1BUS_SEL_MASK (0x00007000u)
1444 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q1BUS_SEL_SHIFT (0x0000000Cu)
1445 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q1BUS_SEL_RESETVAL (0x00000000u)
1447 /* see definition of corresponding register for node0. */
1448 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I0FSDLY_MASK (0x00070000u)
1449 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I0FSDLY_SHIFT (0x00000010u)
1450 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I0FSDLY_RESETVAL (0x00000000u)
1452 /* see definition of corresponding register for node0. */
1453 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q0FSDLY_MASK (0x00700000u)
1454 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q0FSDLY_SHIFT (0x00000014u)
1455 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q0FSDLY_RESETVAL (0x00000000u)
1457 /* see definition of corresponding register for node0. */
1458 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I1FSDLY_MASK (0x07000000u)
1459 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I1FSDLY_SHIFT (0x00000018u)
1460 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_I1FSDLY_RESETVAL (0x00000000u)
1462 /* see definition of corresponding register for node0. */
1463 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q1FSDLY_MASK (0x70000000u)
1464 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q1FSDLY_SHIFT (0x0000001Cu)
1465 #define CSL_DFE_CB_NODE4_CONFIG_REG_NODE4_Q1FSDLY_RESETVAL (0x00000000u)
1467 #define CSL_DFE_CB_NODE4_CONFIG_REG_ADDR (0x00000254u)
1468 #define CSL_DFE_CB_NODE4_CONFIG_REG_RESETVAL (0x00000000u)
1470 /* NODE4_FSF_FSFM */
1471 typedef struct
1472 {
1473 #ifdef _BIG_ENDIAN
1474 Uint32 rsvd0 : 28;
1475 Uint32 node4_fsfm : 2;
1476 Uint32 node4_fsf : 2;
1477 #else
1478 Uint32 node4_fsf : 2;
1479 Uint32 node4_fsfm : 2;
1480 Uint32 rsvd0 : 28;
1481 #endif
1482 } CSL_DFE_CB_NODE4_FSF_FSFM_REG;
1484 /* see definition of corresponding register for node0. */
1485 #define CSL_DFE_CB_NODE4_FSF_FSFM_REG_NODE4_FSF_MASK (0x00000003u)
1486 #define CSL_DFE_CB_NODE4_FSF_FSFM_REG_NODE4_FSF_SHIFT (0x00000000u)
1487 #define CSL_DFE_CB_NODE4_FSF_FSFM_REG_NODE4_FSF_RESETVAL (0x00000000u)
1489 /* see definition of corresponding register for node0. */
1490 #define CSL_DFE_CB_NODE4_FSF_FSFM_REG_NODE4_FSFM_MASK (0x0000000Cu)
1491 #define CSL_DFE_CB_NODE4_FSF_FSFM_REG_NODE4_FSFM_SHIFT (0x00000002u)
1492 #define CSL_DFE_CB_NODE4_FSF_FSFM_REG_NODE4_FSFM_RESETVAL (0x00000000u)
1494 #define CSL_DFE_CB_NODE4_FSF_FSFM_REG_ADDR (0x00000258u)
1495 #define CSL_DFE_CB_NODE4_FSF_FSFM_REG_RESETVAL (0x00000000u)
1497 /* NODE5_CONFIG */
1498 typedef struct
1499 {
1500 #ifdef _BIG_ENDIAN
1501 Uint32 rsvd7 : 1;
1502 Uint32 node5_q1fsdly : 3;
1503 Uint32 rsvd6 : 1;
1504 Uint32 node5_i1fsdly : 3;
1505 Uint32 rsvd5 : 1;
1506 Uint32 node5_q0fsdly : 3;
1507 Uint32 rsvd4 : 1;
1508 Uint32 node5_i0fsdly : 3;
1509 Uint32 rsvd3 : 1;
1510 Uint32 node5_q1bus_sel : 3;
1511 Uint32 rsvd2 : 1;
1512 Uint32 node5_i1bus_sel : 3;
1513 Uint32 rsvd1 : 1;
1514 Uint32 node5_q0bus_sel : 3;
1515 Uint32 rsvd0 : 1;
1516 Uint32 node5_i0bus_sel : 3;
1517 #else
1518 Uint32 node5_i0bus_sel : 3;
1519 Uint32 rsvd0 : 1;
1520 Uint32 node5_q0bus_sel : 3;
1521 Uint32 rsvd1 : 1;
1522 Uint32 node5_i1bus_sel : 3;
1523 Uint32 rsvd2 : 1;
1524 Uint32 node5_q1bus_sel : 3;
1525 Uint32 rsvd3 : 1;
1526 Uint32 node5_i0fsdly : 3;
1527 Uint32 rsvd4 : 1;
1528 Uint32 node5_q0fsdly : 3;
1529 Uint32 rsvd5 : 1;
1530 Uint32 node5_i1fsdly : 3;
1531 Uint32 rsvd6 : 1;
1532 Uint32 node5_q1fsdly : 3;
1533 Uint32 rsvd7 : 1;
1534 #endif
1535 } CSL_DFE_CB_NODE5_CONFIG_REG;
1537 /* see definition of corresponding register for node0. */
1538 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I0BUS_SEL_MASK (0x00000007u)
1539 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I0BUS_SEL_SHIFT (0x00000000u)
1540 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I0BUS_SEL_RESETVAL (0x00000000u)
1542 /* see definition of corresponding register for node0. */
1543 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q0BUS_SEL_MASK (0x00000070u)
1544 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q0BUS_SEL_SHIFT (0x00000004u)
1545 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q0BUS_SEL_RESETVAL (0x00000000u)
1547 /* see definition of corresponding register for node0. */
1548 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I1BUS_SEL_MASK (0x00000700u)
1549 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I1BUS_SEL_SHIFT (0x00000008u)
1550 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I1BUS_SEL_RESETVAL (0x00000000u)
1552 /* see definition of corresponding register for node0. */
1553 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q1BUS_SEL_MASK (0x00007000u)
1554 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q1BUS_SEL_SHIFT (0x0000000Cu)
1555 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q1BUS_SEL_RESETVAL (0x00000000u)
1557 /* see definition of corresponding register for node0. */
1558 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I0FSDLY_MASK (0x00070000u)
1559 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I0FSDLY_SHIFT (0x00000010u)
1560 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I0FSDLY_RESETVAL (0x00000000u)
1562 /* see definition of corresponding register for node0. */
1563 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q0FSDLY_MASK (0x00700000u)
1564 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q0FSDLY_SHIFT (0x00000014u)
1565 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q0FSDLY_RESETVAL (0x00000000u)
1567 /* see definition of corresponding register for node0. */
1568 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I1FSDLY_MASK (0x07000000u)
1569 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I1FSDLY_SHIFT (0x00000018u)
1570 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_I1FSDLY_RESETVAL (0x00000000u)
1572 /* see definition of corresponding register for node0. */
1573 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q1FSDLY_MASK (0x70000000u)
1574 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q1FSDLY_SHIFT (0x0000001Cu)
1575 #define CSL_DFE_CB_NODE5_CONFIG_REG_NODE5_Q1FSDLY_RESETVAL (0x00000000u)
1577 #define CSL_DFE_CB_NODE5_CONFIG_REG_ADDR (0x0000025Cu)
1578 #define CSL_DFE_CB_NODE5_CONFIG_REG_RESETVAL (0x00000000u)
1580 /* NODE5_FSF_FSFM */
1581 typedef struct
1582 {
1583 #ifdef _BIG_ENDIAN
1584 Uint32 rsvd0 : 28;
1585 Uint32 node5_fsfm : 2;
1586 Uint32 node5_fsf : 2;
1587 #else
1588 Uint32 node5_fsf : 2;
1589 Uint32 node5_fsfm : 2;
1590 Uint32 rsvd0 : 28;
1591 #endif
1592 } CSL_DFE_CB_NODE5_FSF_FSFM_REG;
1594 /* see definition of corresponding register for node0. */
1595 #define CSL_DFE_CB_NODE5_FSF_FSFM_REG_NODE5_FSF_MASK (0x00000003u)
1596 #define CSL_DFE_CB_NODE5_FSF_FSFM_REG_NODE5_FSF_SHIFT (0x00000000u)
1597 #define CSL_DFE_CB_NODE5_FSF_FSFM_REG_NODE5_FSF_RESETVAL (0x00000000u)
1599 /* see definition of corresponding register for node0. */
1600 #define CSL_DFE_CB_NODE5_FSF_FSFM_REG_NODE5_FSFM_MASK (0x0000000Cu)
1601 #define CSL_DFE_CB_NODE5_FSF_FSFM_REG_NODE5_FSFM_SHIFT (0x00000002u)
1602 #define CSL_DFE_CB_NODE5_FSF_FSFM_REG_NODE5_FSFM_RESETVAL (0x00000000u)
1604 #define CSL_DFE_CB_NODE5_FSF_FSFM_REG_ADDR (0x00000260u)
1605 #define CSL_DFE_CB_NODE5_FSF_FSFM_REG_RESETVAL (0x00000000u)
1607 /* NODE6_CONFIG */
1608 typedef struct
1609 {
1610 #ifdef _BIG_ENDIAN
1611 Uint32 rsvd7 : 1;
1612 Uint32 node6_q1fsdly : 3;
1613 Uint32 rsvd6 : 1;
1614 Uint32 node6_i1fsdly : 3;
1615 Uint32 rsvd5 : 1;
1616 Uint32 node6_q0fsdly : 3;
1617 Uint32 rsvd4 : 1;
1618 Uint32 node6_i0fsdly : 3;
1619 Uint32 rsvd3 : 1;
1620 Uint32 node6_q1bus_sel : 3;
1621 Uint32 rsvd2 : 1;
1622 Uint32 node6_i1bus_sel : 3;
1623 Uint32 rsvd1 : 1;
1624 Uint32 node6_q0bus_sel : 3;
1625 Uint32 rsvd0 : 1;
1626 Uint32 node6_i0bus_sel : 3;
1627 #else
1628 Uint32 node6_i0bus_sel : 3;
1629 Uint32 rsvd0 : 1;
1630 Uint32 node6_q0bus_sel : 3;
1631 Uint32 rsvd1 : 1;
1632 Uint32 node6_i1bus_sel : 3;
1633 Uint32 rsvd2 : 1;
1634 Uint32 node6_q1bus_sel : 3;
1635 Uint32 rsvd3 : 1;
1636 Uint32 node6_i0fsdly : 3;
1637 Uint32 rsvd4 : 1;
1638 Uint32 node6_q0fsdly : 3;
1639 Uint32 rsvd5 : 1;
1640 Uint32 node6_i1fsdly : 3;
1641 Uint32 rsvd6 : 1;
1642 Uint32 node6_q1fsdly : 3;
1643 Uint32 rsvd7 : 1;
1644 #endif
1645 } CSL_DFE_CB_NODE6_CONFIG_REG;
1647 /* see definition of corresponding register for node0. */
1648 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I0BUS_SEL_MASK (0x00000007u)
1649 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I0BUS_SEL_SHIFT (0x00000000u)
1650 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I0BUS_SEL_RESETVAL (0x00000000u)
1652 /* see definition of corresponding register for node0. */
1653 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q0BUS_SEL_MASK (0x00000070u)
1654 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q0BUS_SEL_SHIFT (0x00000004u)
1655 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q0BUS_SEL_RESETVAL (0x00000000u)
1657 /* see definition of corresponding register for node0. */
1658 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I1BUS_SEL_MASK (0x00000700u)
1659 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I1BUS_SEL_SHIFT (0x00000008u)
1660 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I1BUS_SEL_RESETVAL (0x00000000u)
1662 /* see definition of corresponding register for node0. */
1663 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q1BUS_SEL_MASK (0x00007000u)
1664 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q1BUS_SEL_SHIFT (0x0000000Cu)
1665 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q1BUS_SEL_RESETVAL (0x00000000u)
1667 /* see definition of corresponding register for node0. */
1668 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I0FSDLY_MASK (0x00070000u)
1669 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I0FSDLY_SHIFT (0x00000010u)
1670 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I0FSDLY_RESETVAL (0x00000000u)
1672 /* see definition of corresponding register for node0. */
1673 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q0FSDLY_MASK (0x00700000u)
1674 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q0FSDLY_SHIFT (0x00000014u)
1675 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q0FSDLY_RESETVAL (0x00000000u)
1677 /* see definition of corresponding register for node0. */
1678 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I1FSDLY_MASK (0x07000000u)
1679 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I1FSDLY_SHIFT (0x00000018u)
1680 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_I1FSDLY_RESETVAL (0x00000000u)
1682 /* see definition of corresponding register for node0. */
1683 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q1FSDLY_MASK (0x70000000u)
1684 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q1FSDLY_SHIFT (0x0000001Cu)
1685 #define CSL_DFE_CB_NODE6_CONFIG_REG_NODE6_Q1FSDLY_RESETVAL (0x00000000u)
1687 #define CSL_DFE_CB_NODE6_CONFIG_REG_ADDR (0x00000264u)
1688 #define CSL_DFE_CB_NODE6_CONFIG_REG_RESETVAL (0x00000000u)
1690 /* NODE6_FSF_FSFM */
1691 typedef struct
1692 {
1693 #ifdef _BIG_ENDIAN
1694 Uint32 rsvd0 : 28;
1695 Uint32 node6_fsfm : 2;
1696 Uint32 node6_fsf : 2;
1697 #else
1698 Uint32 node6_fsf : 2;
1699 Uint32 node6_fsfm : 2;
1700 Uint32 rsvd0 : 28;
1701 #endif
1702 } CSL_DFE_CB_NODE6_FSF_FSFM_REG;
1704 /* see definition of corresponding register for node0. */
1705 #define CSL_DFE_CB_NODE6_FSF_FSFM_REG_NODE6_FSF_MASK (0x00000003u)
1706 #define CSL_DFE_CB_NODE6_FSF_FSFM_REG_NODE6_FSF_SHIFT (0x00000000u)
1707 #define CSL_DFE_CB_NODE6_FSF_FSFM_REG_NODE6_FSF_RESETVAL (0x00000000u)
1709 /* see definition of corresponding register for node0. */
1710 #define CSL_DFE_CB_NODE6_FSF_FSFM_REG_NODE6_FSFM_MASK (0x0000000Cu)
1711 #define CSL_DFE_CB_NODE6_FSF_FSFM_REG_NODE6_FSFM_SHIFT (0x00000002u)
1712 #define CSL_DFE_CB_NODE6_FSF_FSFM_REG_NODE6_FSFM_RESETVAL (0x00000000u)
1714 #define CSL_DFE_CB_NODE6_FSF_FSFM_REG_ADDR (0x00000268u)
1715 #define CSL_DFE_CB_NODE6_FSF_FSFM_REG_RESETVAL (0x00000000u)
1717 /* NODE7_CONFIG */
1718 typedef struct
1719 {
1720 #ifdef _BIG_ENDIAN
1721 Uint32 rsvd7 : 1;
1722 Uint32 node7_q1fsdly : 3;
1723 Uint32 rsvd6 : 1;
1724 Uint32 node7_i1fsdly : 3;
1725 Uint32 rsvd5 : 1;
1726 Uint32 node7_q0fsdly : 3;
1727 Uint32 rsvd4 : 1;
1728 Uint32 node7_i0fsdly : 3;
1729 Uint32 rsvd3 : 1;
1730 Uint32 node7_q1bus_sel : 3;
1731 Uint32 rsvd2 : 1;
1732 Uint32 node7_i1bus_sel : 3;
1733 Uint32 rsvd1 : 1;
1734 Uint32 node7_q0bus_sel : 3;
1735 Uint32 rsvd0 : 1;
1736 Uint32 node7_i0bus_sel : 3;
1737 #else
1738 Uint32 node7_i0bus_sel : 3;
1739 Uint32 rsvd0 : 1;
1740 Uint32 node7_q0bus_sel : 3;
1741 Uint32 rsvd1 : 1;
1742 Uint32 node7_i1bus_sel : 3;
1743 Uint32 rsvd2 : 1;
1744 Uint32 node7_q1bus_sel : 3;
1745 Uint32 rsvd3 : 1;
1746 Uint32 node7_i0fsdly : 3;
1747 Uint32 rsvd4 : 1;
1748 Uint32 node7_q0fsdly : 3;
1749 Uint32 rsvd5 : 1;
1750 Uint32 node7_i1fsdly : 3;
1751 Uint32 rsvd6 : 1;
1752 Uint32 node7_q1fsdly : 3;
1753 Uint32 rsvd7 : 1;
1754 #endif
1755 } CSL_DFE_CB_NODE7_CONFIG_REG;
1757 /* see definition of corresponding register for node0. */
1758 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I0BUS_SEL_MASK (0x00000007u)
1759 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I0BUS_SEL_SHIFT (0x00000000u)
1760 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I0BUS_SEL_RESETVAL (0x00000000u)
1762 /* see definition of corresponding register for node0. */
1763 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q0BUS_SEL_MASK (0x00000070u)
1764 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q0BUS_SEL_SHIFT (0x00000004u)
1765 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q0BUS_SEL_RESETVAL (0x00000000u)
1767 /* see definition of corresponding register for node0. */
1768 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I1BUS_SEL_MASK (0x00000700u)
1769 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I1BUS_SEL_SHIFT (0x00000008u)
1770 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I1BUS_SEL_RESETVAL (0x00000000u)
1772 /* see definition of corresponding register for node0. */
1773 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q1BUS_SEL_MASK (0x00007000u)
1774 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q1BUS_SEL_SHIFT (0x0000000Cu)
1775 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q1BUS_SEL_RESETVAL (0x00000000u)
1777 /* see definition of corresponding register for node0. */
1778 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I0FSDLY_MASK (0x00070000u)
1779 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I0FSDLY_SHIFT (0x00000010u)
1780 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I0FSDLY_RESETVAL (0x00000000u)
1782 /* see definition of corresponding register for node0. */
1783 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q0FSDLY_MASK (0x00700000u)
1784 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q0FSDLY_SHIFT (0x00000014u)
1785 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q0FSDLY_RESETVAL (0x00000000u)
1787 /* see definition of corresponding register for node0. */
1788 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I1FSDLY_MASK (0x07000000u)
1789 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I1FSDLY_SHIFT (0x00000018u)
1790 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_I1FSDLY_RESETVAL (0x00000000u)
1792 /* see definition of corresponding register for node0. */
1793 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q1FSDLY_MASK (0x70000000u)
1794 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q1FSDLY_SHIFT (0x0000001Cu)
1795 #define CSL_DFE_CB_NODE7_CONFIG_REG_NODE7_Q1FSDLY_RESETVAL (0x00000000u)
1797 #define CSL_DFE_CB_NODE7_CONFIG_REG_ADDR (0x0000026Cu)
1798 #define CSL_DFE_CB_NODE7_CONFIG_REG_RESETVAL (0x00000000u)
1800 /* NODE7_FSF_FSFM */
1801 typedef struct
1802 {
1803 #ifdef _BIG_ENDIAN
1804 Uint32 rsvd0 : 28;
1805 Uint32 node7_fsfm : 2;
1806 Uint32 node7_fsf : 2;
1807 #else
1808 Uint32 node7_fsf : 2;
1809 Uint32 node7_fsfm : 2;
1810 Uint32 rsvd0 : 28;
1811 #endif
1812 } CSL_DFE_CB_NODE7_FSF_FSFM_REG;
1814 /* see definition of corresponding register for node0. */
1815 #define CSL_DFE_CB_NODE7_FSF_FSFM_REG_NODE7_FSF_MASK (0x00000003u)
1816 #define CSL_DFE_CB_NODE7_FSF_FSFM_REG_NODE7_FSF_SHIFT (0x00000000u)
1817 #define CSL_DFE_CB_NODE7_FSF_FSFM_REG_NODE7_FSF_RESETVAL (0x00000000u)
1819 /* see definition of corresponding register for node0. */
1820 #define CSL_DFE_CB_NODE7_FSF_FSFM_REG_NODE7_FSFM_MASK (0x0000000Cu)
1821 #define CSL_DFE_CB_NODE7_FSF_FSFM_REG_NODE7_FSFM_SHIFT (0x00000002u)
1822 #define CSL_DFE_CB_NODE7_FSF_FSFM_REG_NODE7_FSFM_RESETVAL (0x00000000u)
1824 #define CSL_DFE_CB_NODE7_FSF_FSFM_REG_ADDR (0x00000270u)
1825 #define CSL_DFE_CB_NODE7_FSF_FSFM_REG_RESETVAL (0x00000000u)
1827 /* NODE8_CONFIG */
1828 typedef struct
1829 {
1830 #ifdef _BIG_ENDIAN
1831 Uint32 rsvd7 : 1;
1832 Uint32 node8_q1fsdly : 3;
1833 Uint32 rsvd6 : 1;
1834 Uint32 node8_i1fsdly : 3;
1835 Uint32 rsvd5 : 1;
1836 Uint32 node8_q0fsdly : 3;
1837 Uint32 rsvd4 : 1;
1838 Uint32 node8_i0fsdly : 3;
1839 Uint32 rsvd3 : 1;
1840 Uint32 node8_q1bus_sel : 3;
1841 Uint32 rsvd2 : 1;
1842 Uint32 node8_i1bus_sel : 3;
1843 Uint32 rsvd1 : 1;
1844 Uint32 node8_q0bus_sel : 3;
1845 Uint32 rsvd0 : 1;
1846 Uint32 node8_i0bus_sel : 3;
1847 #else
1848 Uint32 node8_i0bus_sel : 3;
1849 Uint32 rsvd0 : 1;
1850 Uint32 node8_q0bus_sel : 3;
1851 Uint32 rsvd1 : 1;
1852 Uint32 node8_i1bus_sel : 3;
1853 Uint32 rsvd2 : 1;
1854 Uint32 node8_q1bus_sel : 3;
1855 Uint32 rsvd3 : 1;
1856 Uint32 node8_i0fsdly : 3;
1857 Uint32 rsvd4 : 1;
1858 Uint32 node8_q0fsdly : 3;
1859 Uint32 rsvd5 : 1;
1860 Uint32 node8_i1fsdly : 3;
1861 Uint32 rsvd6 : 1;
1862 Uint32 node8_q1fsdly : 3;
1863 Uint32 rsvd7 : 1;
1864 #endif
1865 } CSL_DFE_CB_NODE8_CONFIG_REG;
1867 /* see definition of corresponding register for node0. */
1868 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I0BUS_SEL_MASK (0x00000007u)
1869 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I0BUS_SEL_SHIFT (0x00000000u)
1870 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I0BUS_SEL_RESETVAL (0x00000000u)
1872 /* see definition of corresponding register for node0. */
1873 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q0BUS_SEL_MASK (0x00000070u)
1874 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q0BUS_SEL_SHIFT (0x00000004u)
1875 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q0BUS_SEL_RESETVAL (0x00000000u)
1877 /* see definition of corresponding register for node0. */
1878 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I1BUS_SEL_MASK (0x00000700u)
1879 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I1BUS_SEL_SHIFT (0x00000008u)
1880 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I1BUS_SEL_RESETVAL (0x00000000u)
1882 /* see definition of corresponding register for node0. */
1883 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q1BUS_SEL_MASK (0x00007000u)
1884 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q1BUS_SEL_SHIFT (0x0000000Cu)
1885 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q1BUS_SEL_RESETVAL (0x00000000u)
1887 /* see definition of corresponding register for node0. */
1888 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I0FSDLY_MASK (0x00070000u)
1889 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I0FSDLY_SHIFT (0x00000010u)
1890 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I0FSDLY_RESETVAL (0x00000000u)
1892 /* see definition of corresponding register for node0. */
1893 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q0FSDLY_MASK (0x00700000u)
1894 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q0FSDLY_SHIFT (0x00000014u)
1895 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q0FSDLY_RESETVAL (0x00000000u)
1897 /* see definition of corresponding register for node0. */
1898 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I1FSDLY_MASK (0x07000000u)
1899 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I1FSDLY_SHIFT (0x00000018u)
1900 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_I1FSDLY_RESETVAL (0x00000000u)
1902 /* see definition of corresponding register for node0. */
1903 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q1FSDLY_MASK (0x70000000u)
1904 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q1FSDLY_SHIFT (0x0000001Cu)
1905 #define CSL_DFE_CB_NODE8_CONFIG_REG_NODE8_Q1FSDLY_RESETVAL (0x00000000u)
1907 #define CSL_DFE_CB_NODE8_CONFIG_REG_ADDR (0x00000274u)
1908 #define CSL_DFE_CB_NODE8_CONFIG_REG_RESETVAL (0x00000000u)
1910 /* NODE8_FSF_FSFM */
1911 typedef struct
1912 {
1913 #ifdef _BIG_ENDIAN
1914 Uint32 rsvd0 : 28;
1915 Uint32 node8_fsfm : 2;
1916 Uint32 node8_fsf : 2;
1917 #else
1918 Uint32 node8_fsf : 2;
1919 Uint32 node8_fsfm : 2;
1920 Uint32 rsvd0 : 28;
1921 #endif
1922 } CSL_DFE_CB_NODE8_FSF_FSFM_REG;
1924 /* see definition of corresponding register for node0. */
1925 #define CSL_DFE_CB_NODE8_FSF_FSFM_REG_NODE8_FSF_MASK (0x00000003u)
1926 #define CSL_DFE_CB_NODE8_FSF_FSFM_REG_NODE8_FSF_SHIFT (0x00000000u)
1927 #define CSL_DFE_CB_NODE8_FSF_FSFM_REG_NODE8_FSF_RESETVAL (0x00000000u)
1929 /* see definition of corresponding register for node0. */
1930 #define CSL_DFE_CB_NODE8_FSF_FSFM_REG_NODE8_FSFM_MASK (0x0000000Cu)
1931 #define CSL_DFE_CB_NODE8_FSF_FSFM_REG_NODE8_FSFM_SHIFT (0x00000002u)
1932 #define CSL_DFE_CB_NODE8_FSF_FSFM_REG_NODE8_FSFM_RESETVAL (0x00000000u)
1934 #define CSL_DFE_CB_NODE8_FSF_FSFM_REG_ADDR (0x00000278u)
1935 #define CSL_DFE_CB_NODE8_FSF_FSFM_REG_RESETVAL (0x00000000u)
1937 /* FRAC_CNT */
1938 typedef struct
1939 {
1940 #ifdef _BIG_ENDIAN
1941 Uint32 rsvd0 : 16;
1942 Uint32 cbd_frac_cnt : 4;
1943 Uint32 cbc_frac_cnt : 4;
1944 Uint32 cbb_frac_cnt : 4;
1945 Uint32 cba_frac_cnt : 4;
1946 #else
1947 Uint32 cba_frac_cnt : 4;
1948 Uint32 cbb_frac_cnt : 4;
1949 Uint32 cbc_frac_cnt : 4;
1950 Uint32 cbd_frac_cnt : 4;
1951 Uint32 rsvd0 : 16;
1952 #endif
1953 } CSL_DFE_CB_FRAC_CNT_REG;
1955 /* capture buffer A fractional counter length minus 1; range 0-15; value depends on the relative sampling rates for different buffers, e.g. if reference signal is captured in buffer A and has sample rate 100 MS/sec and feedback signal is captured in buffer B and has sample rate of (3/5)*100 MS/sec, then the */
1956 #define CSL_DFE_CB_FRAC_CNT_REG_CBA_FRAC_CNT_MASK (0x0000000Fu)
1957 #define CSL_DFE_CB_FRAC_CNT_REG_CBA_FRAC_CNT_SHIFT (0x00000000u)
1958 #define CSL_DFE_CB_FRAC_CNT_REG_CBA_FRAC_CNT_RESETVAL (0x00000000u)
1960 /* see definition of 'cba_frac_cnt' */
1961 #define CSL_DFE_CB_FRAC_CNT_REG_CBB_FRAC_CNT_MASK (0x000000F0u)
1962 #define CSL_DFE_CB_FRAC_CNT_REG_CBB_FRAC_CNT_SHIFT (0x00000004u)
1963 #define CSL_DFE_CB_FRAC_CNT_REG_CBB_FRAC_CNT_RESETVAL (0x00000000u)
1965 /* see definition of 'cba_frac_cnt' */
1966 #define CSL_DFE_CB_FRAC_CNT_REG_CBC_FRAC_CNT_MASK (0x00000F00u)
1967 #define CSL_DFE_CB_FRAC_CNT_REG_CBC_FRAC_CNT_SHIFT (0x00000008u)
1968 #define CSL_DFE_CB_FRAC_CNT_REG_CBC_FRAC_CNT_RESETVAL (0x00000000u)
1970 /* see definition of 'cba_frac_cnt' */
1971 #define CSL_DFE_CB_FRAC_CNT_REG_CBD_FRAC_CNT_MASK (0x0000F000u)
1972 #define CSL_DFE_CB_FRAC_CNT_REG_CBD_FRAC_CNT_SHIFT (0x0000000Cu)
1973 #define CSL_DFE_CB_FRAC_CNT_REG_CBD_FRAC_CNT_RESETVAL (0x00000000u)
1975 #define CSL_DFE_CB_FRAC_CNT_REG_ADDR (0x0000027Cu)
1976 #define CSL_DFE_CB_FRAC_CNT_REG_RESETVAL (0x00000000u)
1978 /* INITIAL_FRACTIONAL_PHASE_CTRL */
1979 typedef struct
1980 {
1981 #ifdef _BIG_ENDIAN
1982 Uint32 rsvd1 : 24;
1983 Uint32 init_frac_phase : 4;
1984 Uint32 rsvd0 : 3;
1985 Uint32 init_frac_phase_en : 1;
1986 #else
1987 Uint32 init_frac_phase_en : 1;
1988 Uint32 rsvd0 : 3;
1989 Uint32 init_frac_phase : 4;
1990 Uint32 rsvd1 : 24;
1991 #endif
1992 } CSL_DFE_CB_INITIAL_FRACTIONAL_PHASE_CTRL_REG;
1994 /* may delay the stop of the capture for a few samples in order to make sure each captured chunk of reference signal starts with certain fractional phase specified by 'init_frac_phase': */
1995 #define CSL_DFE_CB_INITIAL_FRACTIONAL_PHASE_CTRL_REG_INIT_FRAC_PHASE_EN_MASK (0x00000001u)
1996 #define CSL_DFE_CB_INITIAL_FRACTIONAL_PHASE_CTRL_REG_INIT_FRAC_PHASE_EN_SHIFT (0x00000000u)
1997 #define CSL_DFE_CB_INITIAL_FRACTIONAL_PHASE_CTRL_REG_INIT_FRAC_PHASE_EN_RESETVAL (0x00000000u)
1999 /* When 'init_frac_phase_en' is set, 'init_frac_phase' can be used to adjust the fractional phase of the first captured reference sampe */
2000 #define CSL_DFE_CB_INITIAL_FRACTIONAL_PHASE_CTRL_REG_INIT_FRAC_PHASE_MASK (0x000000F0u)
2001 #define CSL_DFE_CB_INITIAL_FRACTIONAL_PHASE_CTRL_REG_INIT_FRAC_PHASE_SHIFT (0x00000004u)
2002 #define CSL_DFE_CB_INITIAL_FRACTIONAL_PHASE_CTRL_REG_INIT_FRAC_PHASE_RESETVAL (0x00000000u)
2004 #define CSL_DFE_CB_INITIAL_FRACTIONAL_PHASE_CTRL_REG_ADDR (0x00000280u)
2005 #define CSL_DFE_CB_INITIAL_FRACTIONAL_PHASE_CTRL_REG_RESETVAL (0x00000000u)
2007 /* DONE_FRAC_CNT */
2008 typedef struct
2009 {
2010 #ifdef _BIG_ENDIAN
2011 Uint32 rsvd0 : 16;
2012 Uint32 cbd_done_frac_cnt : 4;
2013 Uint32 cbc_done_frac_cnt : 4;
2014 Uint32 cbb_done_frac_cnt : 4;
2015 Uint32 cba_done_frac_cnt : 4;
2016 #else
2017 Uint32 cba_done_frac_cnt : 4;
2018 Uint32 cbb_done_frac_cnt : 4;
2019 Uint32 cbc_done_frac_cnt : 4;
2020 Uint32 cbd_done_frac_cnt : 4;
2021 Uint32 rsvd0 : 16;
2022 #endif
2023 } CSL_DFE_CB_DONE_FRAC_CNT_REG;
2025 /* capture buffer A finished capture fractional counter value; number to track fractional phase between different buffers; will report the phase that was associated with the most recent capture in cba (e.g. if */
2026 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBA_DONE_FRAC_CNT_MASK (0x0000000Fu)
2027 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBA_DONE_FRAC_CNT_SHIFT (0x00000000u)
2028 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBA_DONE_FRAC_CNT_RESETVAL (0x00000000u)
2030 /* similar to cba_done_frac_cnt */
2031 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBB_DONE_FRAC_CNT_MASK (0x000000F0u)
2032 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBB_DONE_FRAC_CNT_SHIFT (0x00000004u)
2033 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBB_DONE_FRAC_CNT_RESETVAL (0x00000000u)
2035 /* similar to cba_done_frac_cnt */
2036 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBC_DONE_FRAC_CNT_MASK (0x00000F00u)
2037 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBC_DONE_FRAC_CNT_SHIFT (0x00000008u)
2038 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBC_DONE_FRAC_CNT_RESETVAL (0x00000000u)
2040 /* similar to cba_done_frac_cnt */
2041 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBD_DONE_FRAC_CNT_MASK (0x0000F000u)
2042 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBD_DONE_FRAC_CNT_SHIFT (0x0000000Cu)
2043 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_CBD_DONE_FRAC_CNT_RESETVAL (0x00000000u)
2045 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_ADDR (0x00000284u)
2046 #define CSL_DFE_CB_DONE_FRAC_CNT_REG_RESETVAL (0x00000000u)
2048 /* BUF_AB_DONE_ADDR */
2049 typedef struct
2050 {
2051 #ifdef _BIG_ENDIAN
2052 Uint32 cbb_done_addr : 16;
2053 Uint32 cba_done_addr : 16;
2054 #else
2055 Uint32 cba_done_addr : 16;
2056 Uint32 cbb_done_addr : 16;
2057 #endif
2058 } CSL_DFE_CB_BUF_AB_DONE_ADDR_REG;
2060 /* capture buffer A finished capture location + 1 */
2061 #define CSL_DFE_CB_BUF_AB_DONE_ADDR_REG_CBA_DONE_ADDR_MASK (0x0000FFFFu)
2062 #define CSL_DFE_CB_BUF_AB_DONE_ADDR_REG_CBA_DONE_ADDR_SHIFT (0x00000000u)
2063 #define CSL_DFE_CB_BUF_AB_DONE_ADDR_REG_CBA_DONE_ADDR_RESETVAL (0x00000000u)
2065 /* capture buffer B finished capture location + 1 */
2066 #define CSL_DFE_CB_BUF_AB_DONE_ADDR_REG_CBB_DONE_ADDR_MASK (0xFFFF0000u)
2067 #define CSL_DFE_CB_BUF_AB_DONE_ADDR_REG_CBB_DONE_ADDR_SHIFT (0x00000010u)
2068 #define CSL_DFE_CB_BUF_AB_DONE_ADDR_REG_CBB_DONE_ADDR_RESETVAL (0x00000000u)
2070 #define CSL_DFE_CB_BUF_AB_DONE_ADDR_REG_ADDR (0x00000288u)
2071 #define CSL_DFE_CB_BUF_AB_DONE_ADDR_REG_RESETVAL (0x00000000u)
2073 /* BUF_CD_DONE_ADDR */
2074 typedef struct
2075 {
2076 #ifdef _BIG_ENDIAN
2077 Uint32 cbd_done_addr : 16;
2078 Uint32 cbc_done_addr : 16;
2079 #else
2080 Uint32 cbc_done_addr : 16;
2081 Uint32 cbd_done_addr : 16;
2082 #endif
2083 } CSL_DFE_CB_BUF_CD_DONE_ADDR_REG;
2085 /* capture buffer C finished capture location + 1 */
2086 #define CSL_DFE_CB_BUF_CD_DONE_ADDR_REG_CBC_DONE_ADDR_MASK (0x0000FFFFu)
2087 #define CSL_DFE_CB_BUF_CD_DONE_ADDR_REG_CBC_DONE_ADDR_SHIFT (0x00000000u)
2088 #define CSL_DFE_CB_BUF_CD_DONE_ADDR_REG_CBC_DONE_ADDR_RESETVAL (0x00000000u)
2090 /* capture buffer D finished capture location + 1 */
2091 #define CSL_DFE_CB_BUF_CD_DONE_ADDR_REG_CBD_DONE_ADDR_MASK (0xFFFF0000u)
2092 #define CSL_DFE_CB_BUF_CD_DONE_ADDR_REG_CBD_DONE_ADDR_SHIFT (0x00000010u)
2093 #define CSL_DFE_CB_BUF_CD_DONE_ADDR_REG_CBD_DONE_ADDR_RESETVAL (0x00000000u)
2095 #define CSL_DFE_CB_BUF_CD_DONE_ADDR_REG_ADDR (0x0000028Cu)
2096 #define CSL_DFE_CB_BUF_CD_DONE_ADDR_REG_RESETVAL (0x00000000u)
2098 /* CBA_DONE_LENGTH_CNT */
2099 typedef struct
2100 {
2101 #ifdef _BIG_ENDIAN
2102 Uint32 cba_done_length_cnt : 32;
2103 #else
2104 Uint32 cba_done_length_cnt : 32;
2105 #endif
2106 } CSL_DFE_CB_CBA_DONE_LENGTH_CNT_REG;
2108 /* number of samples from capture buffer A length counter sync to end of data capture */
2109 #define CSL_DFE_CB_CBA_DONE_LENGTH_CNT_REG_CBA_DONE_LENGTH_CNT_MASK (0xFFFFFFFFu)
2110 #define CSL_DFE_CB_CBA_DONE_LENGTH_CNT_REG_CBA_DONE_LENGTH_CNT_SHIFT (0x00000000u)
2111 #define CSL_DFE_CB_CBA_DONE_LENGTH_CNT_REG_CBA_DONE_LENGTH_CNT_RESETVAL (0x00000000u)
2113 #define CSL_DFE_CB_CBA_DONE_LENGTH_CNT_REG_ADDR (0x00000290u)
2114 #define CSL_DFE_CB_CBA_DONE_LENGTH_CNT_REG_RESETVAL (0x00000000u)
2116 /* CBB_DONE_LENGTH_CNT */
2117 typedef struct
2118 {
2119 #ifdef _BIG_ENDIAN
2120 Uint32 cbb_done_length_cnt : 32;
2121 #else
2122 Uint32 cbb_done_length_cnt : 32;
2123 #endif
2124 } CSL_DFE_CB_CBB_DONE_LENGTH_CNT_REG;
2126 /* similar to cba_done_length_cnt */
2127 #define CSL_DFE_CB_CBB_DONE_LENGTH_CNT_REG_CBB_DONE_LENGTH_CNT_MASK (0xFFFFFFFFu)
2128 #define CSL_DFE_CB_CBB_DONE_LENGTH_CNT_REG_CBB_DONE_LENGTH_CNT_SHIFT (0x00000000u)
2129 #define CSL_DFE_CB_CBB_DONE_LENGTH_CNT_REG_CBB_DONE_LENGTH_CNT_RESETVAL (0x00000000u)
2131 #define CSL_DFE_CB_CBB_DONE_LENGTH_CNT_REG_ADDR (0x00000294u)
2132 #define CSL_DFE_CB_CBB_DONE_LENGTH_CNT_REG_RESETVAL (0x00000000u)
2134 /* CBC_DONE_LENGTH_CNT */
2135 typedef struct
2136 {
2137 #ifdef _BIG_ENDIAN
2138 Uint32 cbc_done_length_cnt : 32;
2139 #else
2140 Uint32 cbc_done_length_cnt : 32;
2141 #endif
2142 } CSL_DFE_CB_CBC_DONE_LENGTH_CNT_REG;
2144 /* similar to cba_done_length_cnt */
2145 #define CSL_DFE_CB_CBC_DONE_LENGTH_CNT_REG_CBC_DONE_LENGTH_CNT_MASK (0xFFFFFFFFu)
2146 #define CSL_DFE_CB_CBC_DONE_LENGTH_CNT_REG_CBC_DONE_LENGTH_CNT_SHIFT (0x00000000u)
2147 #define CSL_DFE_CB_CBC_DONE_LENGTH_CNT_REG_CBC_DONE_LENGTH_CNT_RESETVAL (0x00000000u)
2149 #define CSL_DFE_CB_CBC_DONE_LENGTH_CNT_REG_ADDR (0x00000298u)
2150 #define CSL_DFE_CB_CBC_DONE_LENGTH_CNT_REG_RESETVAL (0x00000000u)
2152 /* CBD_DONE_LENGTH_CNT */
2153 typedef struct
2154 {
2155 #ifdef _BIG_ENDIAN
2156 Uint32 cbd_done_length_cnt : 32;
2157 #else
2158 Uint32 cbd_done_length_cnt : 32;
2159 #endif
2160 } CSL_DFE_CB_CBD_DONE_LENGTH_CNT_REG;
2162 /* similar to cba_done_length_cnt */
2163 #define CSL_DFE_CB_CBD_DONE_LENGTH_CNT_REG_CBD_DONE_LENGTH_CNT_MASK (0xFFFFFFFFu)
2164 #define CSL_DFE_CB_CBD_DONE_LENGTH_CNT_REG_CBD_DONE_LENGTH_CNT_SHIFT (0x00000000u)
2165 #define CSL_DFE_CB_CBD_DONE_LENGTH_CNT_REG_CBD_DONE_LENGTH_CNT_RESETVAL (0x00000000u)
2167 #define CSL_DFE_CB_CBD_DONE_LENGTH_CNT_REG_ADDR (0x0000029Cu)
2168 #define CSL_DFE_CB_CBD_DONE_LENGTH_CNT_REG_RESETVAL (0x00000000u)
2170 /* CB_C_MULTI_CAPTURE_CTRL */
2171 typedef struct
2172 {
2173 #ifdef _BIG_ENDIAN
2174 Uint32 rsvd1 : 11;
2175 Uint32 cb_c_chunk_size : 13;
2176 Uint32 cb_c_num_captures : 4;
2177 Uint32 rsvd0 : 3;
2178 Uint32 cb_c_multi_capture : 1;
2179 #else
2180 Uint32 cb_c_multi_capture : 1;
2181 Uint32 rsvd0 : 3;
2182 Uint32 cb_c_num_captures : 4;
2183 Uint32 cb_c_chunk_size : 13;
2184 Uint32 rsvd1 : 11;
2185 #endif
2186 } CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG;
2188 /* multiple capture enable: */
2189 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_CB_C_MULTI_CAPTURE_MASK (0x00000001u)
2190 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_CB_C_MULTI_CAPTURE_SHIFT (0x00000000u)
2191 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_CB_C_MULTI_CAPTURE_RESETVAL (0x00000000u)
2193 /* Number of captures upon one capture request (only matters when mult_capture = 1), max value is 8. */
2194 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_CB_C_NUM_CAPTURES_MASK (0x000000F0u)
2195 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_CB_C_NUM_CAPTURES_SHIFT (0x00000004u)
2196 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_CB_C_NUM_CAPTURES_RESETVAL (0x00000000u)
2198 /* valid chunk size must be power of 2, range from 1024 to 8192 */
2199 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_CB_C_CHUNK_SIZE_MASK (0x001FFF00u)
2200 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_CB_C_CHUNK_SIZE_SHIFT (0x00000008u)
2201 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_CB_C_CHUNK_SIZE_RESETVAL (0x00000000u)
2203 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_ADDR (0x000002A0u)
2204 #define CSL_DFE_CB_CB_C_MULTI_CAPTURE_CTRL_REG_RESETVAL (0x00000000u)
2206 /* CB_C_MULTICAP_TIMER1 */
2207 typedef struct
2208 {
2209 #ifdef _BIG_ENDIAN
2210 Uint32 rsvd0 : 8;
2211 Uint32 cb_c_multicap_timer1 : 24;
2212 #else
2213 Uint32 cb_c_multicap_timer1 : 24;
2214 Uint32 rsvd0 : 8;
2215 #endif
2216 } CSL_DFE_CB_CB_C_MULTICAP_TIMER1_REG;
2218 /* Delay from 'trigger' to start capturing the first chunk in samples. */
2219 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER1_REG_CB_C_MULTICAP_TIMER1_MASK (0x00FFFFFFu)
2220 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER1_REG_CB_C_MULTICAP_TIMER1_SHIFT (0x00000000u)
2221 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER1_REG_CB_C_MULTICAP_TIMER1_RESETVAL (0x00000000u)
2223 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER1_REG_ADDR (0x000002A4u)
2224 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER1_REG_RESETVAL (0x00000000u)
2226 /* CB_C_MULTICAP_TIMER2 */
2227 typedef struct
2228 {
2229 #ifdef _BIG_ENDIAN
2230 Uint32 rsvd0 : 8;
2231 Uint32 cb_c_multicap_timer2 : 24;
2232 #else
2233 Uint32 cb_c_multicap_timer2 : 24;
2234 Uint32 rsvd0 : 8;
2235 #endif
2236 } CSL_DFE_CB_CB_C_MULTICAP_TIMER2_REG;
2238 /* Delay from 'trigger' to start capturing the second chunk in samples. (Make sure that 'timer2' is greater than 'timer1 + cb_c_chunk_size') */
2239 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER2_REG_CB_C_MULTICAP_TIMER2_MASK (0x00FFFFFFu)
2240 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER2_REG_CB_C_MULTICAP_TIMER2_SHIFT (0x00000000u)
2241 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER2_REG_CB_C_MULTICAP_TIMER2_RESETVAL (0x00000000u)
2243 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER2_REG_ADDR (0x000002A8u)
2244 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER2_REG_RESETVAL (0x00000000u)
2246 /* CB_C_MULTICAP_TIMER3 */
2247 typedef struct
2248 {
2249 #ifdef _BIG_ENDIAN
2250 Uint32 rsvd0 : 8;
2251 Uint32 cb_c_multicap_timer3 : 24;
2252 #else
2253 Uint32 cb_c_multicap_timer3 : 24;
2254 Uint32 rsvd0 : 8;
2255 #endif
2256 } CSL_DFE_CB_CB_C_MULTICAP_TIMER3_REG;
2258 /* see description of 'cb_c_multicap_timer1' */
2259 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER3_REG_CB_C_MULTICAP_TIMER3_MASK (0x00FFFFFFu)
2260 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER3_REG_CB_C_MULTICAP_TIMER3_SHIFT (0x00000000u)
2261 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER3_REG_CB_C_MULTICAP_TIMER3_RESETVAL (0x00000000u)
2263 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER3_REG_ADDR (0x000002ACu)
2264 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER3_REG_RESETVAL (0x00000000u)
2266 /* CB_C_MULTICAP_TIMER4 */
2267 typedef struct
2268 {
2269 #ifdef _BIG_ENDIAN
2270 Uint32 rsvd0 : 8;
2271 Uint32 cb_c_multicap_timer4 : 24;
2272 #else
2273 Uint32 cb_c_multicap_timer4 : 24;
2274 Uint32 rsvd0 : 8;
2275 #endif
2276 } CSL_DFE_CB_CB_C_MULTICAP_TIMER4_REG;
2278 /* see description of 'cb_c_multicap_timer1' */
2279 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER4_REG_CB_C_MULTICAP_TIMER4_MASK (0x00FFFFFFu)
2280 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER4_REG_CB_C_MULTICAP_TIMER4_SHIFT (0x00000000u)
2281 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER4_REG_CB_C_MULTICAP_TIMER4_RESETVAL (0x00000000u)
2283 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER4_REG_ADDR (0x000002B0u)
2284 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER4_REG_RESETVAL (0x00000000u)
2286 /* CB_C_MULTICAP_TIMER5 */
2287 typedef struct
2288 {
2289 #ifdef _BIG_ENDIAN
2290 Uint32 rsvd0 : 8;
2291 Uint32 cb_c_multicap_timer5 : 24;
2292 #else
2293 Uint32 cb_c_multicap_timer5 : 24;
2294 Uint32 rsvd0 : 8;
2295 #endif
2296 } CSL_DFE_CB_CB_C_MULTICAP_TIMER5_REG;
2298 /* see description of 'cb_c_multicap_timer1' */
2299 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER5_REG_CB_C_MULTICAP_TIMER5_MASK (0x00FFFFFFu)
2300 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER5_REG_CB_C_MULTICAP_TIMER5_SHIFT (0x00000000u)
2301 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER5_REG_CB_C_MULTICAP_TIMER5_RESETVAL (0x00000000u)
2303 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER5_REG_ADDR (0x000002B4u)
2304 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER5_REG_RESETVAL (0x00000000u)
2306 /* CB_C_MULTICAP_TIMER6 */
2307 typedef struct
2308 {
2309 #ifdef _BIG_ENDIAN
2310 Uint32 rsvd0 : 8;
2311 Uint32 cb_c_multicap_timer6 : 24;
2312 #else
2313 Uint32 cb_c_multicap_timer6 : 24;
2314 Uint32 rsvd0 : 8;
2315 #endif
2316 } CSL_DFE_CB_CB_C_MULTICAP_TIMER6_REG;
2318 /* see description of 'cb_c_multicap_timer1' */
2319 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER6_REG_CB_C_MULTICAP_TIMER6_MASK (0x00FFFFFFu)
2320 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER6_REG_CB_C_MULTICAP_TIMER6_SHIFT (0x00000000u)
2321 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER6_REG_CB_C_MULTICAP_TIMER6_RESETVAL (0x00000000u)
2323 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER6_REG_ADDR (0x000002B8u)
2324 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER6_REG_RESETVAL (0x00000000u)
2326 /* CB_C_MULTICAP_TIMER7 */
2327 typedef struct
2328 {
2329 #ifdef _BIG_ENDIAN
2330 Uint32 rsvd0 : 8;
2331 Uint32 cb_c_multicap_timer7 : 24;
2332 #else
2333 Uint32 cb_c_multicap_timer7 : 24;
2334 Uint32 rsvd0 : 8;
2335 #endif
2336 } CSL_DFE_CB_CB_C_MULTICAP_TIMER7_REG;
2338 /* see description of 'cb_c_multicap_timer1' */
2339 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER7_REG_CB_C_MULTICAP_TIMER7_MASK (0x00FFFFFFu)
2340 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER7_REG_CB_C_MULTICAP_TIMER7_SHIFT (0x00000000u)
2341 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER7_REG_CB_C_MULTICAP_TIMER7_RESETVAL (0x00000000u)
2343 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER7_REG_ADDR (0x000002BCu)
2344 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER7_REG_RESETVAL (0x00000000u)
2346 /* CB_C_MULTICAP_TIMER8 */
2347 typedef struct
2348 {
2349 #ifdef _BIG_ENDIAN
2350 Uint32 rsvd0 : 8;
2351 Uint32 cb_c_multicap_timer8 : 24;
2352 #else
2353 Uint32 cb_c_multicap_timer8 : 24;
2354 Uint32 rsvd0 : 8;
2355 #endif
2356 } CSL_DFE_CB_CB_C_MULTICAP_TIMER8_REG;
2358 /* see description of 'cb_c_multicap_timer1' */
2359 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER8_REG_CB_C_MULTICAP_TIMER8_MASK (0x00FFFFFFu)
2360 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER8_REG_CB_C_MULTICAP_TIMER8_SHIFT (0x00000000u)
2361 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER8_REG_CB_C_MULTICAP_TIMER8_RESETVAL (0x00000000u)
2363 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER8_REG_ADDR (0x000002C0u)
2364 #define CSL_DFE_CB_CB_C_MULTICAP_TIMER8_REG_RESETVAL (0x00000000u)
2366 /* CHUNK1_DONE_ADDR */
2367 typedef struct
2368 {
2369 #ifdef _BIG_ENDIAN
2370 Uint32 rsvd1 : 3;
2371 Uint32 fb_chunk1_done_addr : 13;
2372 Uint32 rsvd0 : 3;
2373 Uint32 ref_chunk1_done_addr : 13;
2374 #else
2375 Uint32 ref_chunk1_done_addr : 13;
2376 Uint32 rsvd0 : 3;
2377 Uint32 fb_chunk1_done_addr : 13;
2378 Uint32 rsvd1 : 3;
2379 #endif
2380 } CSL_DFE_CB_CHUNK1_DONE_ADDR_REG;
2382 /* In sharing mode and trigger mode, each section of cb-c buffer (of size chunk size) is a circular buffer, this register indicates where the capture stoped when capture chunk 1 of reference signal */
2383 #define CSL_DFE_CB_CHUNK1_DONE_ADDR_REG_REF_CHUNK1_DONE_ADDR_MASK (0x00001FFFu)
2384 #define CSL_DFE_CB_CHUNK1_DONE_ADDR_REG_REF_CHUNK1_DONE_ADDR_SHIFT (0x00000000u)
2385 #define CSL_DFE_CB_CHUNK1_DONE_ADDR_REG_REF_CHUNK1_DONE_ADDR_RESETVAL (0x00000000u)
2387 /* In sharing mode and trigger mode, each section of cb-c buffer (of size chunk size) is a circular buffer, this register indicates where the capture stoped when capture chunk 1 of feedback signal */
2388 #define CSL_DFE_CB_CHUNK1_DONE_ADDR_REG_FB_CHUNK1_DONE_ADDR_MASK (0x1FFF0000u)
2389 #define CSL_DFE_CB_CHUNK1_DONE_ADDR_REG_FB_CHUNK1_DONE_ADDR_SHIFT (0x00000010u)
2390 #define CSL_DFE_CB_CHUNK1_DONE_ADDR_REG_FB_CHUNK1_DONE_ADDR_RESETVAL (0x00000000u)
2392 #define CSL_DFE_CB_CHUNK1_DONE_ADDR_REG_ADDR (0x000002C4u)
2393 #define CSL_DFE_CB_CHUNK1_DONE_ADDR_REG_RESETVAL (0x00000000u)
2395 /* CHUNK2_DONE_ADDR */
2396 typedef struct
2397 {
2398 #ifdef _BIG_ENDIAN
2399 Uint32 rsvd1 : 3;
2400 Uint32 fb_chunk2_done_addr : 13;
2401 Uint32 rsvd0 : 3;
2402 Uint32 ref_chunk2_done_addr : 13;
2403 #else
2404 Uint32 ref_chunk2_done_addr : 13;
2405 Uint32 rsvd0 : 3;
2406 Uint32 fb_chunk2_done_addr : 13;
2407 Uint32 rsvd1 : 3;
2408 #endif
2409 } CSL_DFE_CB_CHUNK2_DONE_ADDR_REG;
2411 /* similar to 'ref_chunk1_done_addr' */
2412 #define CSL_DFE_CB_CHUNK2_DONE_ADDR_REG_REF_CHUNK2_DONE_ADDR_MASK (0x00001FFFu)
2413 #define CSL_DFE_CB_CHUNK2_DONE_ADDR_REG_REF_CHUNK2_DONE_ADDR_SHIFT (0x00000000u)
2414 #define CSL_DFE_CB_CHUNK2_DONE_ADDR_REG_REF_CHUNK2_DONE_ADDR_RESETVAL (0x00000000u)
2416 /* similar to 'fb_chunk1_done_addr' */
2417 #define CSL_DFE_CB_CHUNK2_DONE_ADDR_REG_FB_CHUNK2_DONE_ADDR_MASK (0x1FFF0000u)
2418 #define CSL_DFE_CB_CHUNK2_DONE_ADDR_REG_FB_CHUNK2_DONE_ADDR_SHIFT (0x00000010u)
2419 #define CSL_DFE_CB_CHUNK2_DONE_ADDR_REG_FB_CHUNK2_DONE_ADDR_RESETVAL (0x00000000u)
2421 #define CSL_DFE_CB_CHUNK2_DONE_ADDR_REG_ADDR (0x000002C8u)
2422 #define CSL_DFE_CB_CHUNK2_DONE_ADDR_REG_RESETVAL (0x00000000u)
2424 /* CHUNK3_DONE_ADDR */
2425 typedef struct
2426 {
2427 #ifdef _BIG_ENDIAN
2428 Uint32 rsvd1 : 3;
2429 Uint32 fb_chunk3_done_addr : 13;
2430 Uint32 rsvd0 : 3;
2431 Uint32 ref_chunk3_done_addr : 13;
2432 #else
2433 Uint32 ref_chunk3_done_addr : 13;
2434 Uint32 rsvd0 : 3;
2435 Uint32 fb_chunk3_done_addr : 13;
2436 Uint32 rsvd1 : 3;
2437 #endif
2438 } CSL_DFE_CB_CHUNK3_DONE_ADDR_REG;
2440 /* similar to 'ref_chunk1_done_addr' */
2441 #define CSL_DFE_CB_CHUNK3_DONE_ADDR_REG_REF_CHUNK3_DONE_ADDR_MASK (0x00001FFFu)
2442 #define CSL_DFE_CB_CHUNK3_DONE_ADDR_REG_REF_CHUNK3_DONE_ADDR_SHIFT (0x00000000u)
2443 #define CSL_DFE_CB_CHUNK3_DONE_ADDR_REG_REF_CHUNK3_DONE_ADDR_RESETVAL (0x00000000u)
2445 /* similar to 'fb_chunk1_done_addr' */
2446 #define CSL_DFE_CB_CHUNK3_DONE_ADDR_REG_FB_CHUNK3_DONE_ADDR_MASK (0x1FFF0000u)
2447 #define CSL_DFE_CB_CHUNK3_DONE_ADDR_REG_FB_CHUNK3_DONE_ADDR_SHIFT (0x00000010u)
2448 #define CSL_DFE_CB_CHUNK3_DONE_ADDR_REG_FB_CHUNK3_DONE_ADDR_RESETVAL (0x00000000u)
2450 #define CSL_DFE_CB_CHUNK3_DONE_ADDR_REG_ADDR (0x000002CCu)
2451 #define CSL_DFE_CB_CHUNK3_DONE_ADDR_REG_RESETVAL (0x00000000u)
2453 /* CHUNK4_DONE_ADDR */
2454 typedef struct
2455 {
2456 #ifdef _BIG_ENDIAN
2457 Uint32 rsvd1 : 3;
2458 Uint32 fb_chunk4_done_addr : 13;
2459 Uint32 rsvd0 : 3;
2460 Uint32 ref_chunk4_done_addr : 13;
2461 #else
2462 Uint32 ref_chunk4_done_addr : 13;
2463 Uint32 rsvd0 : 3;
2464 Uint32 fb_chunk4_done_addr : 13;
2465 Uint32 rsvd1 : 3;
2466 #endif
2467 } CSL_DFE_CB_CHUNK4_DONE_ADDR_REG;
2469 /* similar to 'ref_chunk1_done_addr' */
2470 #define CSL_DFE_CB_CHUNK4_DONE_ADDR_REG_REF_CHUNK4_DONE_ADDR_MASK (0x00001FFFu)
2471 #define CSL_DFE_CB_CHUNK4_DONE_ADDR_REG_REF_CHUNK4_DONE_ADDR_SHIFT (0x00000000u)
2472 #define CSL_DFE_CB_CHUNK4_DONE_ADDR_REG_REF_CHUNK4_DONE_ADDR_RESETVAL (0x00000000u)
2474 /* similar to 'fb_chunk1_done_addr' */
2475 #define CSL_DFE_CB_CHUNK4_DONE_ADDR_REG_FB_CHUNK4_DONE_ADDR_MASK (0x1FFF0000u)
2476 #define CSL_DFE_CB_CHUNK4_DONE_ADDR_REG_FB_CHUNK4_DONE_ADDR_SHIFT (0x00000010u)
2477 #define CSL_DFE_CB_CHUNK4_DONE_ADDR_REG_FB_CHUNK4_DONE_ADDR_RESETVAL (0x00000000u)
2479 #define CSL_DFE_CB_CHUNK4_DONE_ADDR_REG_ADDR (0x000002D0u)
2480 #define CSL_DFE_CB_CHUNK4_DONE_ADDR_REG_RESETVAL (0x00000000u)
2482 /* CHUNK5_DONE_ADDR */
2483 typedef struct
2484 {
2485 #ifdef _BIG_ENDIAN
2486 Uint32 rsvd1 : 3;
2487 Uint32 fb_chunk5_done_addr : 13;
2488 Uint32 rsvd0 : 3;
2489 Uint32 ref_chunk5_done_addr : 13;
2490 #else
2491 Uint32 ref_chunk5_done_addr : 13;
2492 Uint32 rsvd0 : 3;
2493 Uint32 fb_chunk5_done_addr : 13;
2494 Uint32 rsvd1 : 3;
2495 #endif
2496 } CSL_DFE_CB_CHUNK5_DONE_ADDR_REG;
2498 /* similar to 'ref_chunk1_done_addr' */
2499 #define CSL_DFE_CB_CHUNK5_DONE_ADDR_REG_REF_CHUNK5_DONE_ADDR_MASK (0x00001FFFu)
2500 #define CSL_DFE_CB_CHUNK5_DONE_ADDR_REG_REF_CHUNK5_DONE_ADDR_SHIFT (0x00000000u)
2501 #define CSL_DFE_CB_CHUNK5_DONE_ADDR_REG_REF_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
2503 /* similar to 'fb_chunk1_done_addr' */
2504 #define CSL_DFE_CB_CHUNK5_DONE_ADDR_REG_FB_CHUNK5_DONE_ADDR_MASK (0x1FFF0000u)
2505 #define CSL_DFE_CB_CHUNK5_DONE_ADDR_REG_FB_CHUNK5_DONE_ADDR_SHIFT (0x00000010u)
2506 #define CSL_DFE_CB_CHUNK5_DONE_ADDR_REG_FB_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
2508 #define CSL_DFE_CB_CHUNK5_DONE_ADDR_REG_ADDR (0x000002D4u)
2509 #define CSL_DFE_CB_CHUNK5_DONE_ADDR_REG_RESETVAL (0x00000000u)
2511 /* CHUNK6_DONE_ADDR */
2512 typedef struct
2513 {
2514 #ifdef _BIG_ENDIAN
2515 Uint32 rsvd1 : 3;
2516 Uint32 fb_chunk6_done_addr : 13;
2517 Uint32 rsvd0 : 3;
2518 Uint32 ref_chunk6_done_addr : 13;
2519 #else
2520 Uint32 ref_chunk6_done_addr : 13;
2521 Uint32 rsvd0 : 3;
2522 Uint32 fb_chunk6_done_addr : 13;
2523 Uint32 rsvd1 : 3;
2524 #endif
2525 } CSL_DFE_CB_CHUNK6_DONE_ADDR_REG;
2527 /* similar to 'ref_chunk1_done_addr' */
2528 #define CSL_DFE_CB_CHUNK6_DONE_ADDR_REG_REF_CHUNK6_DONE_ADDR_MASK (0x00001FFFu)
2529 #define CSL_DFE_CB_CHUNK6_DONE_ADDR_REG_REF_CHUNK6_DONE_ADDR_SHIFT (0x00000000u)
2530 #define CSL_DFE_CB_CHUNK6_DONE_ADDR_REG_REF_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
2532 /* similar to 'fb_chunk1_done_addr' */
2533 #define CSL_DFE_CB_CHUNK6_DONE_ADDR_REG_FB_CHUNK6_DONE_ADDR_MASK (0x1FFF0000u)
2534 #define CSL_DFE_CB_CHUNK6_DONE_ADDR_REG_FB_CHUNK6_DONE_ADDR_SHIFT (0x00000010u)
2535 #define CSL_DFE_CB_CHUNK6_DONE_ADDR_REG_FB_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
2537 #define CSL_DFE_CB_CHUNK6_DONE_ADDR_REG_ADDR (0x000002D8u)
2538 #define CSL_DFE_CB_CHUNK6_DONE_ADDR_REG_RESETVAL (0x00000000u)
2540 /* CHUNK7_DONE_ADDR */
2541 typedef struct
2542 {
2543 #ifdef _BIG_ENDIAN
2544 Uint32 rsvd1 : 3;
2545 Uint32 fb_chunk7_done_addr : 13;
2546 Uint32 rsvd0 : 3;
2547 Uint32 ref_chunk7_done_addr : 13;
2548 #else
2549 Uint32 ref_chunk7_done_addr : 13;
2550 Uint32 rsvd0 : 3;
2551 Uint32 fb_chunk7_done_addr : 13;
2552 Uint32 rsvd1 : 3;
2553 #endif
2554 } CSL_DFE_CB_CHUNK7_DONE_ADDR_REG;
2556 /* similar to 'ref_chunk1_done_addr' */
2557 #define CSL_DFE_CB_CHUNK7_DONE_ADDR_REG_REF_CHUNK7_DONE_ADDR_MASK (0x00001FFFu)
2558 #define CSL_DFE_CB_CHUNK7_DONE_ADDR_REG_REF_CHUNK7_DONE_ADDR_SHIFT (0x00000000u)
2559 #define CSL_DFE_CB_CHUNK7_DONE_ADDR_REG_REF_CHUNK7_DONE_ADDR_RESETVAL (0x00000000u)
2561 /* similar to 'fb_chunk1_done_addr' */
2562 #define CSL_DFE_CB_CHUNK7_DONE_ADDR_REG_FB_CHUNK7_DONE_ADDR_MASK (0x1FFF0000u)
2563 #define CSL_DFE_CB_CHUNK7_DONE_ADDR_REG_FB_CHUNK7_DONE_ADDR_SHIFT (0x00000010u)
2564 #define CSL_DFE_CB_CHUNK7_DONE_ADDR_REG_FB_CHUNK7_DONE_ADDR_RESETVAL (0x00000000u)
2566 #define CSL_DFE_CB_CHUNK7_DONE_ADDR_REG_ADDR (0x000002DCu)
2567 #define CSL_DFE_CB_CHUNK7_DONE_ADDR_REG_RESETVAL (0x00000000u)
2569 /* CHUNK8_DONE_ADDR */
2570 typedef struct
2571 {
2572 #ifdef _BIG_ENDIAN
2573 Uint32 rsvd1 : 3;
2574 Uint32 fb_chunk8_done_addr : 13;
2575 Uint32 rsvd0 : 3;
2576 Uint32 ref_chunk8_done_addr : 13;
2577 #else
2578 Uint32 ref_chunk8_done_addr : 13;
2579 Uint32 rsvd0 : 3;
2580 Uint32 fb_chunk8_done_addr : 13;
2581 Uint32 rsvd1 : 3;
2582 #endif
2583 } CSL_DFE_CB_CHUNK8_DONE_ADDR_REG;
2585 /* similar to 'ref_chunk1_done_addr' */
2586 #define CSL_DFE_CB_CHUNK8_DONE_ADDR_REG_REF_CHUNK8_DONE_ADDR_MASK (0x00001FFFu)
2587 #define CSL_DFE_CB_CHUNK8_DONE_ADDR_REG_REF_CHUNK8_DONE_ADDR_SHIFT (0x00000000u)
2588 #define CSL_DFE_CB_CHUNK8_DONE_ADDR_REG_REF_CHUNK8_DONE_ADDR_RESETVAL (0x00000000u)
2590 /* similar to 'fb_chunk1_done_addr' */
2591 #define CSL_DFE_CB_CHUNK8_DONE_ADDR_REG_FB_CHUNK8_DONE_ADDR_MASK (0x1FFF0000u)
2592 #define CSL_DFE_CB_CHUNK8_DONE_ADDR_REG_FB_CHUNK8_DONE_ADDR_SHIFT (0x00000010u)
2593 #define CSL_DFE_CB_CHUNK8_DONE_ADDR_REG_FB_CHUNK8_DONE_ADDR_RESETVAL (0x00000000u)
2595 #define CSL_DFE_CB_CHUNK8_DONE_ADDR_REG_ADDR (0x000002E0u)
2596 #define CSL_DFE_CB_CHUNK8_DONE_ADDR_REG_RESETVAL (0x00000000u)
2598 /* TRIGGER_MONITOR_SETTING */
2599 typedef struct
2600 {
2601 #ifdef _BIG_ENDIAN
2602 Uint32 rsvd1 : 12;
2603 Uint32 trigb_blk1_ioc : 1;
2604 Uint32 trigb_blk0_ioc : 1;
2605 Uint32 triga_blk1_ioc : 1;
2606 Uint32 triga_blk0_ioc : 1;
2607 Uint32 trigb_blk1_magsqd_sel : 1;
2608 Uint32 trigb_blk0_magsqd_sel : 1;
2609 Uint32 triga_blk1_magsqd_sel : 1;
2610 Uint32 triga_blk0_magsqd_sel : 1;
2611 Uint32 rsvd0 : 2;
2612 Uint32 trigb_multiband : 1;
2613 Uint32 triga_multiband : 1;
2614 Uint32 trigb_sel : 4;
2615 Uint32 triga_sel : 4;
2616 #else
2617 Uint32 triga_sel : 4;
2618 Uint32 trigb_sel : 4;
2619 Uint32 triga_multiband : 1;
2620 Uint32 trigb_multiband : 1;
2621 Uint32 rsvd0 : 2;
2622 Uint32 triga_blk0_magsqd_sel : 1;
2623 Uint32 triga_blk1_magsqd_sel : 1;
2624 Uint32 trigb_blk0_magsqd_sel : 1;
2625 Uint32 trigb_blk1_magsqd_sel : 1;
2626 Uint32 triga_blk0_ioc : 1;
2627 Uint32 triga_blk1_ioc : 1;
2628 Uint32 trigb_blk0_ioc : 1;
2629 Uint32 trigb_blk1_ioc : 1;
2630 Uint32 rsvd1 : 12;
2631 #endif
2632 } CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG;
2634 /* node selection for trigger moniter A */
2635 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_SEL_MASK (0x0000000Fu)
2636 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_SEL_SHIFT (0x00000000u)
2637 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_SEL_RESETVAL (0x00000000u)
2639 /* node selection for trigger moniter B */
2640 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_SEL_MASK (0x000000F0u)
2641 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_SEL_SHIFT (0x00000004u)
2642 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_SEL_RESETVAL (0x00000000u)
2644 /* when set to '1', trigger moniter block will moniter all four data buses, i.e. I0, Q0, I1, Q1, of the selected node. (I0, Q0) and (I1, Q1) are complex signal for two different sub-bands. */
2645 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_MULTIBAND_MASK (0x00000100u)
2646 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_MULTIBAND_SHIFT (0x00000008u)
2647 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_MULTIBAND_RESETVAL (0x00000000u)
2649 /* when set to '1', trigger moniter block will moniter all four data buses, i.e. I0, Q0, I1, Q1, of the selected node. (I0, Q0) and (I1, Q1) are complex signal for two different sub-bands. */
2650 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_MULTIBAND_MASK (0x00000200u)
2651 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_MULTIBAND_SHIFT (0x00000009u)
2652 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_MULTIBAND_RESETVAL (0x00000000u)
2654 /* trigger A block 0 magnitude or magnitude square select: 1 magsqd, 0 mag */
2655 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK0_MAGSQD_SEL_MASK (0x00001000u)
2656 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK0_MAGSQD_SEL_SHIFT (0x0000000Cu)
2657 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK0_MAGSQD_SEL_RESETVAL (0x00000000u)
2659 /* trigger A block 1 magnitude or magnitude square select: 1 magsqd, 0 mag */
2660 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK1_MAGSQD_SEL_MASK (0x00002000u)
2661 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK1_MAGSQD_SEL_SHIFT (0x0000000Du)
2662 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK1_MAGSQD_SEL_RESETVAL (0x00000000u)
2664 /* trigger B block 0 magnitude or magnitude square select: 1 magsqd, 0 mag */
2665 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK0_MAGSQD_SEL_MASK (0x00004000u)
2666 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK0_MAGSQD_SEL_SHIFT (0x0000000Eu)
2667 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK0_MAGSQD_SEL_RESETVAL (0x00000000u)
2669 /* trigger B block 1 magnitude or magnitude square select: 1 magsqd, 0 mag */
2670 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK1_MAGSQD_SEL_MASK (0x00008000u)
2671 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK1_MAGSQD_SEL_SHIFT (0x0000000Fu)
2672 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK1_MAGSQD_SEL_RESETVAL (0x00000000u)
2674 /* trigger A block 0 integrator counter select: 1 integrator; 0 counter */
2675 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK0_IOC_MASK (0x00010000u)
2676 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK0_IOC_SHIFT (0x00000010u)
2677 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK0_IOC_RESETVAL (0x00000000u)
2679 /* trigger A block 1 integrator counter select: 1 integrator; 0 counter */
2680 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK1_IOC_MASK (0x00020000u)
2681 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK1_IOC_SHIFT (0x00000011u)
2682 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGA_BLK1_IOC_RESETVAL (0x00000000u)
2684 /* trigger B block 0 integrator counter select: 1 integrator; 0 counter */
2685 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK0_IOC_MASK (0x00040000u)
2686 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK0_IOC_SHIFT (0x00000012u)
2687 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK0_IOC_RESETVAL (0x00000000u)
2689 /* trigger B block 1 integrator counter select: 1 integrator; 0 counter */
2690 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK1_IOC_MASK (0x00080000u)
2691 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK1_IOC_SHIFT (0x00000013u)
2692 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_TRIGB_BLK1_IOC_RESETVAL (0x00000000u)
2694 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_ADDR (0x000002E4u)
2695 #define CSL_DFE_CB_TRIGGER_MONITOR_SETTING_REG_RESETVAL (0x00000000u)
2697 /* TRIGGER_MONITOR_A_CONFIG */
2698 typedef struct
2699 {
2700 #ifdef _BIG_ENDIAN
2701 Uint32 rsvd7 : 1;
2702 Uint32 triga_q1fsdly : 3;
2703 Uint32 rsvd6 : 1;
2704 Uint32 triga_i1fsdly : 3;
2705 Uint32 rsvd5 : 1;
2706 Uint32 triga_q0fsdly : 3;
2707 Uint32 rsvd4 : 1;
2708 Uint32 triga_i0fsdly : 3;
2709 Uint32 rsvd3 : 1;
2710 Uint32 triga_q1bus_sel : 3;
2711 Uint32 rsvd2 : 1;
2712 Uint32 triga_i1bus_sel : 3;
2713 Uint32 rsvd1 : 1;
2714 Uint32 triga_q0bus_sel : 3;
2715 Uint32 rsvd0 : 1;
2716 Uint32 triga_i0bus_sel : 3;
2717 #else
2718 Uint32 triga_i0bus_sel : 3;
2719 Uint32 rsvd0 : 1;
2720 Uint32 triga_q0bus_sel : 3;
2721 Uint32 rsvd1 : 1;
2722 Uint32 triga_i1bus_sel : 3;
2723 Uint32 rsvd2 : 1;
2724 Uint32 triga_q1bus_sel : 3;
2725 Uint32 rsvd3 : 1;
2726 Uint32 triga_i0fsdly : 3;
2727 Uint32 rsvd4 : 1;
2728 Uint32 triga_q0fsdly : 3;
2729 Uint32 rsvd5 : 1;
2730 Uint32 triga_i1fsdly : 3;
2731 Uint32 rsvd6 : 1;
2732 Uint32 triga_q1fsdly : 3;
2733 Uint32 rsvd7 : 1;
2734 #endif
2735 } CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG;
2737 /* choose between bus0 ~bus7 for I0 data, if total number of buses at a capture node is less than 8, then some buses will be duplicated. */
2738 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I0BUS_SEL_MASK (0x00000007u)
2739 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I0BUS_SEL_SHIFT (0x00000000u)
2740 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I0BUS_SEL_RESETVAL (0x00000000u)
2742 /* choose between bus0 ~bus7 for Q0 data. */
2743 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q0BUS_SEL_MASK (0x00000070u)
2744 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q0BUS_SEL_SHIFT (0x00000004u)
2745 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q0BUS_SEL_RESETVAL (0x00000000u)
2747 /* choose between bus0 ~bus7 for I1 data. Only matters when 'triga_multiband' is set to '1'. */
2748 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I1BUS_SEL_MASK (0x00000700u)
2749 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I1BUS_SEL_SHIFT (0x00000008u)
2750 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I1BUS_SEL_RESETVAL (0x00000000u)
2752 /* choose between bus0 ~bus7 for Q1 data. Only matters when 'triga_multiband' is set to '1'. */
2753 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q1BUS_SEL_MASK (0x00007000u)
2754 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q1BUS_SEL_SHIFT (0x0000000Cu)
2755 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q1BUS_SEL_RESETVAL (0x00000000u)
2757 /* I0 data delay locaton relative to frame start on the corresponding selected bus. */
2758 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I0FSDLY_MASK (0x00070000u)
2759 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I0FSDLY_SHIFT (0x00000010u)
2760 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I0FSDLY_RESETVAL (0x00000000u)
2762 /* Q0 data delay locaton relative to frame start on the corresponding selected bus. */
2763 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q0FSDLY_MASK (0x00700000u)
2764 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q0FSDLY_SHIFT (0x00000014u)
2765 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q0FSDLY_RESETVAL (0x00000000u)
2767 /* I1 data delay locaton relative to frame start on the corresponding selected bus. Only matters when 'triga_multiband' is set to '1'. */
2768 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I1FSDLY_MASK (0x07000000u)
2769 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I1FSDLY_SHIFT (0x00000018u)
2770 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_I1FSDLY_RESETVAL (0x00000000u)
2772 /* Q1 data delay locaton relative to frame start on the corresponding selected bus. Only matters when 'triga_multiband' is set to '1'. */
2773 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q1FSDLY_MASK (0x70000000u)
2774 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q1FSDLY_SHIFT (0x0000001Cu)
2775 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_TRIGA_Q1FSDLY_RESETVAL (0x00000000u)
2777 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_ADDR (0x000002E8u)
2778 #define CSL_DFE_CB_TRIGGER_MONITOR_A_CONFIG_REG_RESETVAL (0x00000000u)
2780 /* TRIGGER_MONITOR_A_FSF_FSFM */
2781 typedef struct
2782 {
2783 #ifdef _BIG_ENDIAN
2784 Uint32 rsvd0 : 28;
2785 Uint32 triga_fsfm : 2;
2786 Uint32 triga_fsf : 2;
2787 #else
2788 Uint32 triga_fsf : 2;
2789 Uint32 triga_fsfm : 2;
2790 Uint32 rsvd0 : 28;
2791 #endif
2792 } CSL_DFE_CB_TRIGGER_MONITOR_A_FSF_FSFM_REG;
2794 /* see definition of corresponding register for node0. */
2795 #define CSL_DFE_CB_TRIGGER_MONITOR_A_FSF_FSFM_REG_TRIGA_FSF_MASK (0x00000003u)
2796 #define CSL_DFE_CB_TRIGGER_MONITOR_A_FSF_FSFM_REG_TRIGA_FSF_SHIFT (0x00000000u)
2797 #define CSL_DFE_CB_TRIGGER_MONITOR_A_FSF_FSFM_REG_TRIGA_FSF_RESETVAL (0x00000000u)
2799 /* see definition of corresponding register for node0. */
2800 #define CSL_DFE_CB_TRIGGER_MONITOR_A_FSF_FSFM_REG_TRIGA_FSFM_MASK (0x0000000Cu)
2801 #define CSL_DFE_CB_TRIGGER_MONITOR_A_FSF_FSFM_REG_TRIGA_FSFM_SHIFT (0x00000002u)
2802 #define CSL_DFE_CB_TRIGGER_MONITOR_A_FSF_FSFM_REG_TRIGA_FSFM_RESETVAL (0x00000000u)
2804 #define CSL_DFE_CB_TRIGGER_MONITOR_A_FSF_FSFM_REG_ADDR (0x000002ECu)
2805 #define CSL_DFE_CB_TRIGGER_MONITOR_A_FSF_FSFM_REG_RESETVAL (0x00000000u)
2807 /* TRIGGER_MONITOR_B_CONFIG */
2808 typedef struct
2809 {
2810 #ifdef _BIG_ENDIAN
2811 Uint32 rsvd7 : 1;
2812 Uint32 trigb_q1fsdly : 3;
2813 Uint32 rsvd6 : 1;
2814 Uint32 trigb_i1fsdly : 3;
2815 Uint32 rsvd5 : 1;
2816 Uint32 trigb_q0fsdly : 3;
2817 Uint32 rsvd4 : 1;
2818 Uint32 trigb_i0fsdly : 3;
2819 Uint32 rsvd3 : 1;
2820 Uint32 trigb_q1bus_sel : 3;
2821 Uint32 rsvd2 : 1;
2822 Uint32 trigb_i1bus_sel : 3;
2823 Uint32 rsvd1 : 1;
2824 Uint32 trigb_q0bus_sel : 3;
2825 Uint32 rsvd0 : 1;
2826 Uint32 trigb_i0bus_sel : 3;
2827 #else
2828 Uint32 trigb_i0bus_sel : 3;
2829 Uint32 rsvd0 : 1;
2830 Uint32 trigb_q0bus_sel : 3;
2831 Uint32 rsvd1 : 1;
2832 Uint32 trigb_i1bus_sel : 3;
2833 Uint32 rsvd2 : 1;
2834 Uint32 trigb_q1bus_sel : 3;
2835 Uint32 rsvd3 : 1;
2836 Uint32 trigb_i0fsdly : 3;
2837 Uint32 rsvd4 : 1;
2838 Uint32 trigb_q0fsdly : 3;
2839 Uint32 rsvd5 : 1;
2840 Uint32 trigb_i1fsdly : 3;
2841 Uint32 rsvd6 : 1;
2842 Uint32 trigb_q1fsdly : 3;
2843 Uint32 rsvd7 : 1;
2844 #endif
2845 } CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG;
2847 /* see definition of corresponding register for triga. */
2848 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I0BUS_SEL_MASK (0x00000007u)
2849 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I0BUS_SEL_SHIFT (0x00000000u)
2850 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I0BUS_SEL_RESETVAL (0x00000000u)
2852 /* see definition of corresponding register for triga. */
2853 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q0BUS_SEL_MASK (0x00000070u)
2854 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q0BUS_SEL_SHIFT (0x00000004u)
2855 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q0BUS_SEL_RESETVAL (0x00000000u)
2857 /* see definition of corresponding register for triga. */
2858 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I1BUS_SEL_MASK (0x00000700u)
2859 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I1BUS_SEL_SHIFT (0x00000008u)
2860 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I1BUS_SEL_RESETVAL (0x00000000u)
2862 /* see definition of corresponding register for triga. */
2863 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q1BUS_SEL_MASK (0x00007000u)
2864 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q1BUS_SEL_SHIFT (0x0000000Cu)
2865 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q1BUS_SEL_RESETVAL (0x00000000u)
2867 /* see definition of corresponding register for triga. */
2868 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I0FSDLY_MASK (0x00070000u)
2869 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I0FSDLY_SHIFT (0x00000010u)
2870 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I0FSDLY_RESETVAL (0x00000000u)
2872 /* see definition of corresponding register for triga. */
2873 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q0FSDLY_MASK (0x00700000u)
2874 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q0FSDLY_SHIFT (0x00000014u)
2875 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q0FSDLY_RESETVAL (0x00000000u)
2877 /* see definition of corresponding register for triga. */
2878 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I1FSDLY_MASK (0x07000000u)
2879 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I1FSDLY_SHIFT (0x00000018u)
2880 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_I1FSDLY_RESETVAL (0x00000000u)
2882 /* see definition of corresponding register for triga. */
2883 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q1FSDLY_MASK (0x70000000u)
2884 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q1FSDLY_SHIFT (0x0000001Cu)
2885 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_TRIGB_Q1FSDLY_RESETVAL (0x00000000u)
2887 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_ADDR (0x000002F0u)
2888 #define CSL_DFE_CB_TRIGGER_MONITOR_B_CONFIG_REG_RESETVAL (0x00000000u)
2890 /* TRIGGER_MONITOR_B_FSF_FSFM */
2891 typedef struct
2892 {
2893 #ifdef _BIG_ENDIAN
2894 Uint32 rsvd0 : 28;
2895 Uint32 trigb_fsfm : 2;
2896 Uint32 trigb_fsf : 2;
2897 #else
2898 Uint32 trigb_fsf : 2;
2899 Uint32 trigb_fsfm : 2;
2900 Uint32 rsvd0 : 28;
2901 #endif
2902 } CSL_DFE_CB_TRIGGER_MONITOR_B_FSF_FSFM_REG;
2904 /* see definition of corresponding register for triga. */
2905 #define CSL_DFE_CB_TRIGGER_MONITOR_B_FSF_FSFM_REG_TRIGB_FSF_MASK (0x00000003u)
2906 #define CSL_DFE_CB_TRIGGER_MONITOR_B_FSF_FSFM_REG_TRIGB_FSF_SHIFT (0x00000000u)
2907 #define CSL_DFE_CB_TRIGGER_MONITOR_B_FSF_FSFM_REG_TRIGB_FSF_RESETVAL (0x00000000u)
2909 /* see definition of corresponding register for triga. */
2910 #define CSL_DFE_CB_TRIGGER_MONITOR_B_FSF_FSFM_REG_TRIGB_FSFM_MASK (0x0000000Cu)
2911 #define CSL_DFE_CB_TRIGGER_MONITOR_B_FSF_FSFM_REG_TRIGB_FSFM_SHIFT (0x00000002u)
2912 #define CSL_DFE_CB_TRIGGER_MONITOR_B_FSF_FSFM_REG_TRIGB_FSFM_RESETVAL (0x00000000u)
2914 #define CSL_DFE_CB_TRIGGER_MONITOR_B_FSF_FSFM_REG_ADDR (0x000002F4u)
2915 #define CSL_DFE_CB_TRIGGER_MONITOR_B_FSF_FSFM_REG_RESETVAL (0x00000000u)
2917 /* TRIGA_BLK0_LENGTH */
2918 typedef struct
2919 {
2920 #ifdef _BIG_ENDIAN
2921 Uint32 rsvd0 : 16;
2922 Uint32 triga_blk0_length : 16;
2923 #else
2924 Uint32 triga_blk0_length : 16;
2925 Uint32 rsvd0 : 16;
2926 #endif
2927 } CSL_DFE_CB_TRIGA_BLK0_LENGTH_REG;
2929 /* trigger A block 0 window size (in number of samples), valid range 0~8191, bit [15:13] not in use. */
2930 #define CSL_DFE_CB_TRIGA_BLK0_LENGTH_REG_TRIGA_BLK0_LENGTH_MASK (0x0000FFFFu)
2931 #define CSL_DFE_CB_TRIGA_BLK0_LENGTH_REG_TRIGA_BLK0_LENGTH_SHIFT (0x00000000u)
2932 #define CSL_DFE_CB_TRIGA_BLK0_LENGTH_REG_TRIGA_BLK0_LENGTH_RESETVAL (0x00000000u)
2934 #define CSL_DFE_CB_TRIGA_BLK0_LENGTH_REG_ADDR (0x000002F8u)
2935 #define CSL_DFE_CB_TRIGA_BLK0_LENGTH_REG_RESETVAL (0x00000000u)
2937 /* TRIGA_BLK0_T1 */
2938 typedef struct
2939 {
2940 #ifdef _BIG_ENDIAN
2941 Uint32 triga_blk0_t1 : 32;
2942 #else
2943 Uint32 triga_blk0_t1 : 32;
2944 #endif
2945 } CSL_DFE_CB_TRIGA_BLK0_T1_REG;
2947 /* trigger A block 0 threshold 1 (unsigned number) */
2948 #define CSL_DFE_CB_TRIGA_BLK0_T1_REG_TRIGA_BLK0_T1_MASK (0xFFFFFFFFu)
2949 #define CSL_DFE_CB_TRIGA_BLK0_T1_REG_TRIGA_BLK0_T1_SHIFT (0x00000000u)
2950 #define CSL_DFE_CB_TRIGA_BLK0_T1_REG_TRIGA_BLK0_T1_RESETVAL (0x00000000u)
2952 #define CSL_DFE_CB_TRIGA_BLK0_T1_REG_ADDR (0x000002FCu)
2953 #define CSL_DFE_CB_TRIGA_BLK0_T1_REG_RESETVAL (0x00000000u)
2955 /* TRIGA_BLK0_T2 */
2956 typedef struct
2957 {
2958 #ifdef _BIG_ENDIAN
2959 Uint32 rsvd0 : 16;
2960 Uint32 triga_blk0_t2 : 16;
2961 #else
2962 Uint32 triga_blk0_t2 : 16;
2963 Uint32 rsvd0 : 16;
2964 #endif
2965 } CSL_DFE_CB_TRIGA_BLK0_T2_REG;
2967 /* trigger A block 0 threshold 2 (unsigned number) */
2968 #define CSL_DFE_CB_TRIGA_BLK0_T2_REG_TRIGA_BLK0_T2_MASK (0x0000FFFFu)
2969 #define CSL_DFE_CB_TRIGA_BLK0_T2_REG_TRIGA_BLK0_T2_SHIFT (0x00000000u)
2970 #define CSL_DFE_CB_TRIGA_BLK0_T2_REG_TRIGA_BLK0_T2_RESETVAL (0x00000000u)
2972 #define CSL_DFE_CB_TRIGA_BLK0_T2_REG_ADDR (0x00000300u)
2973 #define CSL_DFE_CB_TRIGA_BLK0_T2_REG_RESETVAL (0x00000000u)
2975 /* TRIGA_BLK1_LENGTH */
2976 typedef struct
2977 {
2978 #ifdef _BIG_ENDIAN
2979 Uint32 rsvd0 : 16;
2980 Uint32 triga_blk1_length : 16;
2981 #else
2982 Uint32 triga_blk1_length : 16;
2983 Uint32 rsvd0 : 16;
2984 #endif
2985 } CSL_DFE_CB_TRIGA_BLK1_LENGTH_REG;
2987 /* trigger A block 1 window size (in number of samples), valid range 0~8191, bit [15:13] not in use. */
2988 #define CSL_DFE_CB_TRIGA_BLK1_LENGTH_REG_TRIGA_BLK1_LENGTH_MASK (0x0000FFFFu)
2989 #define CSL_DFE_CB_TRIGA_BLK1_LENGTH_REG_TRIGA_BLK1_LENGTH_SHIFT (0x00000000u)
2990 #define CSL_DFE_CB_TRIGA_BLK1_LENGTH_REG_TRIGA_BLK1_LENGTH_RESETVAL (0x00000000u)
2992 #define CSL_DFE_CB_TRIGA_BLK1_LENGTH_REG_ADDR (0x00000304u)
2993 #define CSL_DFE_CB_TRIGA_BLK1_LENGTH_REG_RESETVAL (0x00000000u)
2995 /* TRIGA_BLK1_T1 */
2996 typedef struct
2997 {
2998 #ifdef _BIG_ENDIAN
2999 Uint32 triga_blk1_t1 : 32;
3000 #else
3001 Uint32 triga_blk1_t1 : 32;
3002 #endif
3003 } CSL_DFE_CB_TRIGA_BLK1_T1_REG;
3005 /* trigger A block 1 threshold 1 (unsigned number) */
3006 #define CSL_DFE_CB_TRIGA_BLK1_T1_REG_TRIGA_BLK1_T1_MASK (0xFFFFFFFFu)
3007 #define CSL_DFE_CB_TRIGA_BLK1_T1_REG_TRIGA_BLK1_T1_SHIFT (0x00000000u)
3008 #define CSL_DFE_CB_TRIGA_BLK1_T1_REG_TRIGA_BLK1_T1_RESETVAL (0x00000000u)
3010 #define CSL_DFE_CB_TRIGA_BLK1_T1_REG_ADDR (0x00000308u)
3011 #define CSL_DFE_CB_TRIGA_BLK1_T1_REG_RESETVAL (0x00000000u)
3013 /* TRIGA_BLK1_T2 */
3014 typedef struct
3015 {
3016 #ifdef _BIG_ENDIAN
3017 Uint32 rsvd0 : 16;
3018 Uint32 triga_blk1_t2 : 16;
3019 #else
3020 Uint32 triga_blk1_t2 : 16;
3021 Uint32 rsvd0 : 16;
3022 #endif
3023 } CSL_DFE_CB_TRIGA_BLK1_T2_REG;
3025 /* trigger A block 1 threshold 2 (unsigned number) */
3026 #define CSL_DFE_CB_TRIGA_BLK1_T2_REG_TRIGA_BLK1_T2_MASK (0x0000FFFFu)
3027 #define CSL_DFE_CB_TRIGA_BLK1_T2_REG_TRIGA_BLK1_T2_SHIFT (0x00000000u)
3028 #define CSL_DFE_CB_TRIGA_BLK1_T2_REG_TRIGA_BLK1_T2_RESETVAL (0x00000000u)
3030 #define CSL_DFE_CB_TRIGA_BLK1_T2_REG_ADDR (0x0000030Cu)
3031 #define CSL_DFE_CB_TRIGA_BLK1_T2_REG_RESETVAL (0x00000000u)
3033 /* TRIGB_BLK0_LENGTH */
3034 typedef struct
3035 {
3036 #ifdef _BIG_ENDIAN
3037 Uint32 rsvd0 : 16;
3038 Uint32 trigb_blk0_length : 16;
3039 #else
3040 Uint32 trigb_blk0_length : 16;
3041 Uint32 rsvd0 : 16;
3042 #endif
3043 } CSL_DFE_CB_TRIGB_BLK0_LENGTH_REG;
3045 /* trigger B block 0 window size (in number of samples), valid range 0~8191, bit [15:13] not in use. */
3046 #define CSL_DFE_CB_TRIGB_BLK0_LENGTH_REG_TRIGB_BLK0_LENGTH_MASK (0x0000FFFFu)
3047 #define CSL_DFE_CB_TRIGB_BLK0_LENGTH_REG_TRIGB_BLK0_LENGTH_SHIFT (0x00000000u)
3048 #define CSL_DFE_CB_TRIGB_BLK0_LENGTH_REG_TRIGB_BLK0_LENGTH_RESETVAL (0x00000000u)
3050 #define CSL_DFE_CB_TRIGB_BLK0_LENGTH_REG_ADDR (0x00000310u)
3051 #define CSL_DFE_CB_TRIGB_BLK0_LENGTH_REG_RESETVAL (0x00000000u)
3053 /* TRIGB_BLK0_T1 */
3054 typedef struct
3055 {
3056 #ifdef _BIG_ENDIAN
3057 Uint32 trigb_blk0_t1 : 32;
3058 #else
3059 Uint32 trigb_blk0_t1 : 32;
3060 #endif
3061 } CSL_DFE_CB_TRIGB_BLK0_T1_REG;
3063 /* trigger B block 0 threshold 1 (unsigned number) */
3064 #define CSL_DFE_CB_TRIGB_BLK0_T1_REG_TRIGB_BLK0_T1_MASK (0xFFFFFFFFu)
3065 #define CSL_DFE_CB_TRIGB_BLK0_T1_REG_TRIGB_BLK0_T1_SHIFT (0x00000000u)
3066 #define CSL_DFE_CB_TRIGB_BLK0_T1_REG_TRIGB_BLK0_T1_RESETVAL (0x00000000u)
3068 #define CSL_DFE_CB_TRIGB_BLK0_T1_REG_ADDR (0x00000314u)
3069 #define CSL_DFE_CB_TRIGB_BLK0_T1_REG_RESETVAL (0x00000000u)
3071 /* TRIGB_BLK0_T2 */
3072 typedef struct
3073 {
3074 #ifdef _BIG_ENDIAN
3075 Uint32 rsvd0 : 16;
3076 Uint32 trigb_blk0_t2 : 16;
3077 #else
3078 Uint32 trigb_blk0_t2 : 16;
3079 Uint32 rsvd0 : 16;
3080 #endif
3081 } CSL_DFE_CB_TRIGB_BLK0_T2_REG;
3083 /* trigger B block 0 threshold 2 (unsigned number) */
3084 #define CSL_DFE_CB_TRIGB_BLK0_T2_REG_TRIGB_BLK0_T2_MASK (0x0000FFFFu)
3085 #define CSL_DFE_CB_TRIGB_BLK0_T2_REG_TRIGB_BLK0_T2_SHIFT (0x00000000u)
3086 #define CSL_DFE_CB_TRIGB_BLK0_T2_REG_TRIGB_BLK0_T2_RESETVAL (0x00000000u)
3088 #define CSL_DFE_CB_TRIGB_BLK0_T2_REG_ADDR (0x00000318u)
3089 #define CSL_DFE_CB_TRIGB_BLK0_T2_REG_RESETVAL (0x00000000u)
3091 /* TRIGB_BLK1_LENGTH */
3092 typedef struct
3093 {
3094 #ifdef _BIG_ENDIAN
3095 Uint32 rsvd0 : 16;
3096 Uint32 trigb_blk1_length : 16;
3097 #else
3098 Uint32 trigb_blk1_length : 16;
3099 Uint32 rsvd0 : 16;
3100 #endif
3101 } CSL_DFE_CB_TRIGB_BLK1_LENGTH_REG;
3103 /* trigger B block 1 window size (in number of samples), valid range 0~8191, bit [15:13] not in use. */
3104 #define CSL_DFE_CB_TRIGB_BLK1_LENGTH_REG_TRIGB_BLK1_LENGTH_MASK (0x0000FFFFu)
3105 #define CSL_DFE_CB_TRIGB_BLK1_LENGTH_REG_TRIGB_BLK1_LENGTH_SHIFT (0x00000000u)
3106 #define CSL_DFE_CB_TRIGB_BLK1_LENGTH_REG_TRIGB_BLK1_LENGTH_RESETVAL (0x00000000u)
3108 #define CSL_DFE_CB_TRIGB_BLK1_LENGTH_REG_ADDR (0x0000031Cu)
3109 #define CSL_DFE_CB_TRIGB_BLK1_LENGTH_REG_RESETVAL (0x00000000u)
3111 /* TRIGB_BLK1_T1 */
3112 typedef struct
3113 {
3114 #ifdef _BIG_ENDIAN
3115 Uint32 trigb_blk1_t1 : 32;
3116 #else
3117 Uint32 trigb_blk1_t1 : 32;
3118 #endif
3119 } CSL_DFE_CB_TRIGB_BLK1_T1_REG;
3121 /* trigger B block 1 threshold 1 (unsigned number) */
3122 #define CSL_DFE_CB_TRIGB_BLK1_T1_REG_TRIGB_BLK1_T1_MASK (0xFFFFFFFFu)
3123 #define CSL_DFE_CB_TRIGB_BLK1_T1_REG_TRIGB_BLK1_T1_SHIFT (0x00000000u)
3124 #define CSL_DFE_CB_TRIGB_BLK1_T1_REG_TRIGB_BLK1_T1_RESETVAL (0x00000000u)
3126 #define CSL_DFE_CB_TRIGB_BLK1_T1_REG_ADDR (0x00000320u)
3127 #define CSL_DFE_CB_TRIGB_BLK1_T1_REG_RESETVAL (0x00000000u)
3129 /* TRIGB_BLK1_T2 */
3130 typedef struct
3131 {
3132 #ifdef _BIG_ENDIAN
3133 Uint32 rsvd0 : 16;
3134 Uint32 trigb_blk1_t2 : 16;
3135 #else
3136 Uint32 trigb_blk1_t2 : 16;
3137 Uint32 rsvd0 : 16;
3138 #endif
3139 } CSL_DFE_CB_TRIGB_BLK1_T2_REG;
3141 /* trigger B block 1 threshold 2 (unsigned number) */
3142 #define CSL_DFE_CB_TRIGB_BLK1_T2_REG_TRIGB_BLK1_T2_MASK (0x0000FFFFu)
3143 #define CSL_DFE_CB_TRIGB_BLK1_T2_REG_TRIGB_BLK1_T2_SHIFT (0x00000000u)
3144 #define CSL_DFE_CB_TRIGB_BLK1_T2_REG_TRIGB_BLK1_T2_RESETVAL (0x00000000u)
3146 #define CSL_DFE_CB_TRIGB_BLK1_T2_REG_ADDR (0x00000324u)
3147 #define CSL_DFE_CB_TRIGB_BLK1_T2_REG_RESETVAL (0x00000000u)
3149 /* TRIGGER_MONITOR_DECODER */
3150 typedef struct
3151 {
3152 #ifdef _BIG_ENDIAN
3153 Uint32 rsvd0 : 16;
3154 Uint32 trigger_monitor_decoder : 16;
3155 #else
3156 Uint32 trigger_monitor_decoder : 16;
3157 Uint32 rsvd0 : 16;
3158 #endif
3159 } CSL_DFE_CB_TRIGGER_MONITOR_DECODER_REG;
3161 /* for decoding the output from the four trigger monitor blocks, the output from [trigb_blk1, trigb_blk0, triga_blk1, triga_blk0] will be used as 4-bit input address to this decoder, and the output is the bit specified by the 4-bit address. For example, if we program 'trigger_monitor_decoder' to 0x8000, that means the decoder output will be high only when the output from all four trigger monitor blocks are high, because only bit 15 is '1'. */
3162 #define CSL_DFE_CB_TRIGGER_MONITOR_DECODER_REG_TRIGGER_MONITOR_DECODER_MASK (0x0000FFFFu)
3163 #define CSL_DFE_CB_TRIGGER_MONITOR_DECODER_REG_TRIGGER_MONITOR_DECODER_SHIFT (0x00000000u)
3164 #define CSL_DFE_CB_TRIGGER_MONITOR_DECODER_REG_TRIGGER_MONITOR_DECODER_RESETVAL (0x0000FFFFu)
3166 #define CSL_DFE_CB_TRIGGER_MONITOR_DECODER_REG_ADDR (0x00000328u)
3167 #define CSL_DFE_CB_TRIGGER_MONITOR_DECODER_REG_RESETVAL (0x0000FFFFu)
3169 /* GSG_MODE */
3170 typedef struct
3171 {
3172 #ifdef _BIG_ENDIAN
3173 Uint32 rsvd0 : 20;
3174 Uint32 gsg5_mode : 2;
3175 Uint32 gsg4_mode : 2;
3176 Uint32 gsg3_mode : 2;
3177 Uint32 gsg2_mode : 2;
3178 Uint32 gsg1_mode : 2;
3179 Uint32 gsg0_mode : 2;
3180 #else
3181 Uint32 gsg0_mode : 2;
3182 Uint32 gsg1_mode : 2;
3183 Uint32 gsg2_mode : 2;
3184 Uint32 gsg3_mode : 2;
3185 Uint32 gsg4_mode : 2;
3186 Uint32 gsg5_mode : 2;
3187 Uint32 rsvd0 : 20;
3188 #endif
3189 } CSL_DFE_CB_GSG_MODE_REG;
3191 /* 0 = off */
3192 #define CSL_DFE_CB_GSG_MODE_REG_GSG0_MODE_MASK (0x00000003u)
3193 #define CSL_DFE_CB_GSG_MODE_REG_GSG0_MODE_SHIFT (0x00000000u)
3194 #define CSL_DFE_CB_GSG_MODE_REG_GSG0_MODE_RESETVAL (0x00000000u)
3196 /* same as gsg0_mode */
3197 #define CSL_DFE_CB_GSG_MODE_REG_GSG1_MODE_MASK (0x0000000Cu)
3198 #define CSL_DFE_CB_GSG_MODE_REG_GSG1_MODE_SHIFT (0x00000002u)
3199 #define CSL_DFE_CB_GSG_MODE_REG_GSG1_MODE_RESETVAL (0x00000000u)
3201 /* same as gsg0_mode */
3202 #define CSL_DFE_CB_GSG_MODE_REG_GSG2_MODE_MASK (0x00000030u)
3203 #define CSL_DFE_CB_GSG_MODE_REG_GSG2_MODE_SHIFT (0x00000004u)
3204 #define CSL_DFE_CB_GSG_MODE_REG_GSG2_MODE_RESETVAL (0x00000000u)
3206 /* same as gsg0_mode */
3207 #define CSL_DFE_CB_GSG_MODE_REG_GSG3_MODE_MASK (0x000000C0u)
3208 #define CSL_DFE_CB_GSG_MODE_REG_GSG3_MODE_SHIFT (0x00000006u)
3209 #define CSL_DFE_CB_GSG_MODE_REG_GSG3_MODE_RESETVAL (0x00000000u)
3211 /* same as gsg0_mode */
3212 #define CSL_DFE_CB_GSG_MODE_REG_GSG4_MODE_MASK (0x00000300u)
3213 #define CSL_DFE_CB_GSG_MODE_REG_GSG4_MODE_SHIFT (0x00000008u)
3214 #define CSL_DFE_CB_GSG_MODE_REG_GSG4_MODE_RESETVAL (0x00000000u)
3216 /* same as gsg0_mode */
3217 #define CSL_DFE_CB_GSG_MODE_REG_GSG5_MODE_MASK (0x00000C00u)
3218 #define CSL_DFE_CB_GSG_MODE_REG_GSG5_MODE_SHIFT (0x0000000Au)
3219 #define CSL_DFE_CB_GSG_MODE_REG_GSG5_MODE_RESETVAL (0x00000000u)
3221 #define CSL_DFE_CB_GSG_MODE_REG_ADDR (0x0000032Cu)
3222 #define CSL_DFE_CB_GSG_MODE_REG_RESETVAL (0x00000000u)
3224 /* GSG0_DELAYFROMSYNC */
3225 typedef struct
3226 {
3227 #ifdef _BIG_ENDIAN
3228 Uint32 rsvd0 : 8;
3229 Uint32 gsg0_delayfromsync : 24;
3230 #else
3231 Uint32 gsg0_delayfromsync : 24;
3232 Uint32 rsvd0 : 8;
3233 #endif
3234 } CSL_DFE_CB_GSG0_DELAYFROMSYNC_REG;
3236 /* interval in samples from sync to start of first 'on' period minus 1 sample */
3237 #define CSL_DFE_CB_GSG0_DELAYFROMSYNC_REG_GSG0_DELAYFROMSYNC_MASK (0x00FFFFFFu)
3238 #define CSL_DFE_CB_GSG0_DELAYFROMSYNC_REG_GSG0_DELAYFROMSYNC_SHIFT (0x00000000u)
3239 #define CSL_DFE_CB_GSG0_DELAYFROMSYNC_REG_GSG0_DELAYFROMSYNC_RESETVAL (0x00000000u)
3241 #define CSL_DFE_CB_GSG0_DELAYFROMSYNC_REG_ADDR (0x00000330u)
3242 #define CSL_DFE_CB_GSG0_DELAYFROMSYNC_REG_RESETVAL (0x00000000u)
3244 /* GSG0_TIMER1 */
3245 typedef struct
3246 {
3247 #ifdef _BIG_ENDIAN
3248 Uint32 rsvd0 : 8;
3249 Uint32 gsg0_timer1 : 24;
3250 #else
3251 Uint32 gsg0_timer1 : 24;
3252 Uint32 rsvd0 : 8;
3253 #endif
3254 } CSL_DFE_CB_GSG0_TIMER1_REG;
3256 /* duration in samples of the first 'on' period */
3257 #define CSL_DFE_CB_GSG0_TIMER1_REG_GSG0_TIMER1_MASK (0x00FFFFFFu)
3258 #define CSL_DFE_CB_GSG0_TIMER1_REG_GSG0_TIMER1_SHIFT (0x00000000u)
3259 #define CSL_DFE_CB_GSG0_TIMER1_REG_GSG0_TIMER1_RESETVAL (0x00000000u)
3261 #define CSL_DFE_CB_GSG0_TIMER1_REG_ADDR (0x00000334u)
3262 #define CSL_DFE_CB_GSG0_TIMER1_REG_RESETVAL (0x00000000u)
3264 /* GSG0_TIMER2 */
3265 typedef struct
3266 {
3267 #ifdef _BIG_ENDIAN
3268 Uint32 rsvd0 : 8;
3269 Uint32 gsg0_timer2 : 24;
3270 #else
3271 Uint32 gsg0_timer2 : 24;
3272 Uint32 rsvd0 : 8;
3273 #endif
3274 } CSL_DFE_CB_GSG0_TIMER2_REG;
3276 /* off' duration in samples between the first 'on' period and the second 'on' period */
3277 #define CSL_DFE_CB_GSG0_TIMER2_REG_GSG0_TIMER2_MASK (0x00FFFFFFu)
3278 #define CSL_DFE_CB_GSG0_TIMER2_REG_GSG0_TIMER2_SHIFT (0x00000000u)
3279 #define CSL_DFE_CB_GSG0_TIMER2_REG_GSG0_TIMER2_RESETVAL (0x00000000u)
3281 #define CSL_DFE_CB_GSG0_TIMER2_REG_ADDR (0x00000338u)
3282 #define CSL_DFE_CB_GSG0_TIMER2_REG_RESETVAL (0x00000000u)
3284 /* GSG0_TIMER3 */
3285 typedef struct
3286 {
3287 #ifdef _BIG_ENDIAN
3288 Uint32 rsvd0 : 8;
3289 Uint32 gsg0_timer3 : 24;
3290 #else
3291 Uint32 gsg0_timer3 : 24;
3292 Uint32 rsvd0 : 8;
3293 #endif
3294 } CSL_DFE_CB_GSG0_TIMER3_REG;
3296 /* duration in samples of the second 'on' period */
3297 #define CSL_DFE_CB_GSG0_TIMER3_REG_GSG0_TIMER3_MASK (0x00FFFFFFu)
3298 #define CSL_DFE_CB_GSG0_TIMER3_REG_GSG0_TIMER3_SHIFT (0x00000000u)
3299 #define CSL_DFE_CB_GSG0_TIMER3_REG_GSG0_TIMER3_RESETVAL (0x00000000u)
3301 #define CSL_DFE_CB_GSG0_TIMER3_REG_ADDR (0x0000033Cu)
3302 #define CSL_DFE_CB_GSG0_TIMER3_REG_RESETVAL (0x00000000u)
3304 /* GSG0_TIMER4 */
3305 typedef struct
3306 {
3307 #ifdef _BIG_ENDIAN
3308 Uint32 rsvd0 : 8;
3309 Uint32 gsg0_timer4 : 24;
3310 #else
3311 Uint32 gsg0_timer4 : 24;
3312 Uint32 rsvd0 : 8;
3313 #endif
3314 } CSL_DFE_CB_GSG0_TIMER4_REG;
3316 /* off' duration in samples between the second 'on' period and the third 'on' period */
3317 #define CSL_DFE_CB_GSG0_TIMER4_REG_GSG0_TIMER4_MASK (0x00FFFFFFu)
3318 #define CSL_DFE_CB_GSG0_TIMER4_REG_GSG0_TIMER4_SHIFT (0x00000000u)
3319 #define CSL_DFE_CB_GSG0_TIMER4_REG_GSG0_TIMER4_RESETVAL (0x00000000u)
3321 #define CSL_DFE_CB_GSG0_TIMER4_REG_ADDR (0x00000340u)
3322 #define CSL_DFE_CB_GSG0_TIMER4_REG_RESETVAL (0x00000000u)
3324 /* GSG0_TIMER5 */
3325 typedef struct
3326 {
3327 #ifdef _BIG_ENDIAN
3328 Uint32 rsvd0 : 8;
3329 Uint32 gsg0_timer5 : 24;
3330 #else
3331 Uint32 gsg0_timer5 : 24;
3332 Uint32 rsvd0 : 8;
3333 #endif
3334 } CSL_DFE_CB_GSG0_TIMER5_REG;
3336 /* duration in samples of the third 'on' period */
3337 #define CSL_DFE_CB_GSG0_TIMER5_REG_GSG0_TIMER5_MASK (0x00FFFFFFu)
3338 #define CSL_DFE_CB_GSG0_TIMER5_REG_GSG0_TIMER5_SHIFT (0x00000000u)
3339 #define CSL_DFE_CB_GSG0_TIMER5_REG_GSG0_TIMER5_RESETVAL (0x00000000u)
3341 #define CSL_DFE_CB_GSG0_TIMER5_REG_ADDR (0x00000344u)
3342 #define CSL_DFE_CB_GSG0_TIMER5_REG_RESETVAL (0x00000000u)
3344 /* GSG1_DELAYFROMSYNC */
3345 typedef struct
3346 {
3347 #ifdef _BIG_ENDIAN
3348 Uint32 rsvd0 : 8;
3349 Uint32 gsg1_delayfromsync : 24;
3350 #else
3351 Uint32 gsg1_delayfromsync : 24;
3352 Uint32 rsvd0 : 8;
3353 #endif
3354 } CSL_DFE_CB_GSG1_DELAYFROMSYNC_REG;
3356 /* same as gsg0_delayfromsync */
3357 #define CSL_DFE_CB_GSG1_DELAYFROMSYNC_REG_GSG1_DELAYFROMSYNC_MASK (0x00FFFFFFu)
3358 #define CSL_DFE_CB_GSG1_DELAYFROMSYNC_REG_GSG1_DELAYFROMSYNC_SHIFT (0x00000000u)
3359 #define CSL_DFE_CB_GSG1_DELAYFROMSYNC_REG_GSG1_DELAYFROMSYNC_RESETVAL (0x00000000u)
3361 #define CSL_DFE_CB_GSG1_DELAYFROMSYNC_REG_ADDR (0x00000348u)
3362 #define CSL_DFE_CB_GSG1_DELAYFROMSYNC_REG_RESETVAL (0x00000000u)
3364 /* GSG1_TIMER1 */
3365 typedef struct
3366 {
3367 #ifdef _BIG_ENDIAN
3368 Uint32 rsvd0 : 8;
3369 Uint32 gsg1_timer1 : 24;
3370 #else
3371 Uint32 gsg1_timer1 : 24;
3372 Uint32 rsvd0 : 8;
3373 #endif
3374 } CSL_DFE_CB_GSG1_TIMER1_REG;
3376 /* same as gsg0_timer1 */
3377 #define CSL_DFE_CB_GSG1_TIMER1_REG_GSG1_TIMER1_MASK (0x00FFFFFFu)
3378 #define CSL_DFE_CB_GSG1_TIMER1_REG_GSG1_TIMER1_SHIFT (0x00000000u)
3379 #define CSL_DFE_CB_GSG1_TIMER1_REG_GSG1_TIMER1_RESETVAL (0x00000000u)
3381 #define CSL_DFE_CB_GSG1_TIMER1_REG_ADDR (0x0000034Cu)
3382 #define CSL_DFE_CB_GSG1_TIMER1_REG_RESETVAL (0x00000000u)
3384 /* GSG1_TIMER2 */
3385 typedef struct
3386 {
3387 #ifdef _BIG_ENDIAN
3388 Uint32 rsvd0 : 8;
3389 Uint32 gsg1_timer2 : 24;
3390 #else
3391 Uint32 gsg1_timer2 : 24;
3392 Uint32 rsvd0 : 8;
3393 #endif
3394 } CSL_DFE_CB_GSG1_TIMER2_REG;
3396 /* same as gsg0_timer2 */
3397 #define CSL_DFE_CB_GSG1_TIMER2_REG_GSG1_TIMER2_MASK (0x00FFFFFFu)
3398 #define CSL_DFE_CB_GSG1_TIMER2_REG_GSG1_TIMER2_SHIFT (0x00000000u)
3399 #define CSL_DFE_CB_GSG1_TIMER2_REG_GSG1_TIMER2_RESETVAL (0x00000000u)
3401 #define CSL_DFE_CB_GSG1_TIMER2_REG_ADDR (0x00000350u)
3402 #define CSL_DFE_CB_GSG1_TIMER2_REG_RESETVAL (0x00000000u)
3404 /* GSG1_TIMER3 */
3405 typedef struct
3406 {
3407 #ifdef _BIG_ENDIAN
3408 Uint32 rsvd0 : 8;
3409 Uint32 gsg1_timer3 : 24;
3410 #else
3411 Uint32 gsg1_timer3 : 24;
3412 Uint32 rsvd0 : 8;
3413 #endif
3414 } CSL_DFE_CB_GSG1_TIMER3_REG;
3416 /* same as gsg0_timer3 */
3417 #define CSL_DFE_CB_GSG1_TIMER3_REG_GSG1_TIMER3_MASK (0x00FFFFFFu)
3418 #define CSL_DFE_CB_GSG1_TIMER3_REG_GSG1_TIMER3_SHIFT (0x00000000u)
3419 #define CSL_DFE_CB_GSG1_TIMER3_REG_GSG1_TIMER3_RESETVAL (0x00000000u)
3421 #define CSL_DFE_CB_GSG1_TIMER3_REG_ADDR (0x00000354u)
3422 #define CSL_DFE_CB_GSG1_TIMER3_REG_RESETVAL (0x00000000u)
3424 /* GSG1_TIMER4 */
3425 typedef struct
3426 {
3427 #ifdef _BIG_ENDIAN
3428 Uint32 rsvd0 : 8;
3429 Uint32 gsg1_timer4 : 24;
3430 #else
3431 Uint32 gsg1_timer4 : 24;
3432 Uint32 rsvd0 : 8;
3433 #endif
3434 } CSL_DFE_CB_GSG1_TIMER4_REG;
3436 /* same as gsg0_timer4 */
3437 #define CSL_DFE_CB_GSG1_TIMER4_REG_GSG1_TIMER4_MASK (0x00FFFFFFu)
3438 #define CSL_DFE_CB_GSG1_TIMER4_REG_GSG1_TIMER4_SHIFT (0x00000000u)
3439 #define CSL_DFE_CB_GSG1_TIMER4_REG_GSG1_TIMER4_RESETVAL (0x00000000u)
3441 #define CSL_DFE_CB_GSG1_TIMER4_REG_ADDR (0x00000358u)
3442 #define CSL_DFE_CB_GSG1_TIMER4_REG_RESETVAL (0x00000000u)
3444 /* GSG1_TIMER5 */
3445 typedef struct
3446 {
3447 #ifdef _BIG_ENDIAN
3448 Uint32 rsvd0 : 8;
3449 Uint32 gsg1_timer5 : 24;
3450 #else
3451 Uint32 gsg1_timer5 : 24;
3452 Uint32 rsvd0 : 8;
3453 #endif
3454 } CSL_DFE_CB_GSG1_TIMER5_REG;
3456 /* same as gsg0_timer5 */
3457 #define CSL_DFE_CB_GSG1_TIMER5_REG_GSG1_TIMER5_MASK (0x00FFFFFFu)
3458 #define CSL_DFE_CB_GSG1_TIMER5_REG_GSG1_TIMER5_SHIFT (0x00000000u)
3459 #define CSL_DFE_CB_GSG1_TIMER5_REG_GSG1_TIMER5_RESETVAL (0x00000000u)
3461 #define CSL_DFE_CB_GSG1_TIMER5_REG_ADDR (0x0000035Cu)
3462 #define CSL_DFE_CB_GSG1_TIMER5_REG_RESETVAL (0x00000000u)
3464 /* GSG2_DELAYFROMSYNC */
3465 typedef struct
3466 {
3467 #ifdef _BIG_ENDIAN
3468 Uint32 rsvd0 : 8;
3469 Uint32 gsg2_delayfromsync : 24;
3470 #else
3471 Uint32 gsg2_delayfromsync : 24;
3472 Uint32 rsvd0 : 8;
3473 #endif
3474 } CSL_DFE_CB_GSG2_DELAYFROMSYNC_REG;
3476 /* same as gsg0_delayfromsync */
3477 #define CSL_DFE_CB_GSG2_DELAYFROMSYNC_REG_GSG2_DELAYFROMSYNC_MASK (0x00FFFFFFu)
3478 #define CSL_DFE_CB_GSG2_DELAYFROMSYNC_REG_GSG2_DELAYFROMSYNC_SHIFT (0x00000000u)
3479 #define CSL_DFE_CB_GSG2_DELAYFROMSYNC_REG_GSG2_DELAYFROMSYNC_RESETVAL (0x00000000u)
3481 #define CSL_DFE_CB_GSG2_DELAYFROMSYNC_REG_ADDR (0x00000360u)
3482 #define CSL_DFE_CB_GSG2_DELAYFROMSYNC_REG_RESETVAL (0x00000000u)
3484 /* GSG2_TIMER1 */
3485 typedef struct
3486 {
3487 #ifdef _BIG_ENDIAN
3488 Uint32 rsvd0 : 8;
3489 Uint32 gsg2_timer1 : 24;
3490 #else
3491 Uint32 gsg2_timer1 : 24;
3492 Uint32 rsvd0 : 8;
3493 #endif
3494 } CSL_DFE_CB_GSG2_TIMER1_REG;
3496 /* same as gsg0_timer1 */
3497 #define CSL_DFE_CB_GSG2_TIMER1_REG_GSG2_TIMER1_MASK (0x00FFFFFFu)
3498 #define CSL_DFE_CB_GSG2_TIMER1_REG_GSG2_TIMER1_SHIFT (0x00000000u)
3499 #define CSL_DFE_CB_GSG2_TIMER1_REG_GSG2_TIMER1_RESETVAL (0x00000000u)
3501 #define CSL_DFE_CB_GSG2_TIMER1_REG_ADDR (0x00000364u)
3502 #define CSL_DFE_CB_GSG2_TIMER1_REG_RESETVAL (0x00000000u)
3504 /* GSG2_TIMER2 */
3505 typedef struct
3506 {
3507 #ifdef _BIG_ENDIAN
3508 Uint32 rsvd0 : 8;
3509 Uint32 gsg2_timer2 : 24;
3510 #else
3511 Uint32 gsg2_timer2 : 24;
3512 Uint32 rsvd0 : 8;
3513 #endif
3514 } CSL_DFE_CB_GSG2_TIMER2_REG;
3516 /* same as gsg0_timer2 */
3517 #define CSL_DFE_CB_GSG2_TIMER2_REG_GSG2_TIMER2_MASK (0x00FFFFFFu)
3518 #define CSL_DFE_CB_GSG2_TIMER2_REG_GSG2_TIMER2_SHIFT (0x00000000u)
3519 #define CSL_DFE_CB_GSG2_TIMER2_REG_GSG2_TIMER2_RESETVAL (0x00000000u)
3521 #define CSL_DFE_CB_GSG2_TIMER2_REG_ADDR (0x00000368u)
3522 #define CSL_DFE_CB_GSG2_TIMER2_REG_RESETVAL (0x00000000u)
3524 /* GSG2_TIMER3 */
3525 typedef struct
3526 {
3527 #ifdef _BIG_ENDIAN
3528 Uint32 rsvd0 : 8;
3529 Uint32 gsg2_timer3 : 24;
3530 #else
3531 Uint32 gsg2_timer3 : 24;
3532 Uint32 rsvd0 : 8;
3533 #endif
3534 } CSL_DFE_CB_GSG2_TIMER3_REG;
3536 /* same as gsg0_timer3 */
3537 #define CSL_DFE_CB_GSG2_TIMER3_REG_GSG2_TIMER3_MASK (0x00FFFFFFu)
3538 #define CSL_DFE_CB_GSG2_TIMER3_REG_GSG2_TIMER3_SHIFT (0x00000000u)
3539 #define CSL_DFE_CB_GSG2_TIMER3_REG_GSG2_TIMER3_RESETVAL (0x00000000u)
3541 #define CSL_DFE_CB_GSG2_TIMER3_REG_ADDR (0x0000036Cu)
3542 #define CSL_DFE_CB_GSG2_TIMER3_REG_RESETVAL (0x00000000u)
3544 /* GSG2_TIMER4 */
3545 typedef struct
3546 {
3547 #ifdef _BIG_ENDIAN
3548 Uint32 rsvd0 : 8;
3549 Uint32 gsg2_timer4 : 24;
3550 #else
3551 Uint32 gsg2_timer4 : 24;
3552 Uint32 rsvd0 : 8;
3553 #endif
3554 } CSL_DFE_CB_GSG2_TIMER4_REG;
3556 /* same as gsg0_timer4 */
3557 #define CSL_DFE_CB_GSG2_TIMER4_REG_GSG2_TIMER4_MASK (0x00FFFFFFu)
3558 #define CSL_DFE_CB_GSG2_TIMER4_REG_GSG2_TIMER4_SHIFT (0x00000000u)
3559 #define CSL_DFE_CB_GSG2_TIMER4_REG_GSG2_TIMER4_RESETVAL (0x00000000u)
3561 #define CSL_DFE_CB_GSG2_TIMER4_REG_ADDR (0x00000370u)
3562 #define CSL_DFE_CB_GSG2_TIMER4_REG_RESETVAL (0x00000000u)
3564 /* GSG2_TIMER5 */
3565 typedef struct
3566 {
3567 #ifdef _BIG_ENDIAN
3568 Uint32 rsvd0 : 8;
3569 Uint32 gsg2_timer5 : 24;
3570 #else
3571 Uint32 gsg2_timer5 : 24;
3572 Uint32 rsvd0 : 8;
3573 #endif
3574 } CSL_DFE_CB_GSG2_TIMER5_REG;
3576 /* same as gsg0_timer5 */
3577 #define CSL_DFE_CB_GSG2_TIMER5_REG_GSG2_TIMER5_MASK (0x00FFFFFFu)
3578 #define CSL_DFE_CB_GSG2_TIMER5_REG_GSG2_TIMER5_SHIFT (0x00000000u)
3579 #define CSL_DFE_CB_GSG2_TIMER5_REG_GSG2_TIMER5_RESETVAL (0x00000000u)
3581 #define CSL_DFE_CB_GSG2_TIMER5_REG_ADDR (0x00000374u)
3582 #define CSL_DFE_CB_GSG2_TIMER5_REG_RESETVAL (0x00000000u)
3584 /* GSG3_DELAYFROMSYNC */
3585 typedef struct
3586 {
3587 #ifdef _BIG_ENDIAN
3588 Uint32 rsvd0 : 8;
3589 Uint32 gsg3_delayfromsync : 24;
3590 #else
3591 Uint32 gsg3_delayfromsync : 24;
3592 Uint32 rsvd0 : 8;
3593 #endif
3594 } CSL_DFE_CB_GSG3_DELAYFROMSYNC_REG;
3596 /* same as gsg0_delayfromsync */
3597 #define CSL_DFE_CB_GSG3_DELAYFROMSYNC_REG_GSG3_DELAYFROMSYNC_MASK (0x00FFFFFFu)
3598 #define CSL_DFE_CB_GSG3_DELAYFROMSYNC_REG_GSG3_DELAYFROMSYNC_SHIFT (0x00000000u)
3599 #define CSL_DFE_CB_GSG3_DELAYFROMSYNC_REG_GSG3_DELAYFROMSYNC_RESETVAL (0x00000000u)
3601 #define CSL_DFE_CB_GSG3_DELAYFROMSYNC_REG_ADDR (0x00000378u)
3602 #define CSL_DFE_CB_GSG3_DELAYFROMSYNC_REG_RESETVAL (0x00000000u)
3604 /* GSG3_TIMER1 */
3605 typedef struct
3606 {
3607 #ifdef _BIG_ENDIAN
3608 Uint32 rsvd0 : 8;
3609 Uint32 gsg3_timer1 : 24;
3610 #else
3611 Uint32 gsg3_timer1 : 24;
3612 Uint32 rsvd0 : 8;
3613 #endif
3614 } CSL_DFE_CB_GSG3_TIMER1_REG;
3616 /* same as gsg0_timer1 */
3617 #define CSL_DFE_CB_GSG3_TIMER1_REG_GSG3_TIMER1_MASK (0x00FFFFFFu)
3618 #define CSL_DFE_CB_GSG3_TIMER1_REG_GSG3_TIMER1_SHIFT (0x00000000u)
3619 #define CSL_DFE_CB_GSG3_TIMER1_REG_GSG3_TIMER1_RESETVAL (0x00000000u)
3621 #define CSL_DFE_CB_GSG3_TIMER1_REG_ADDR (0x0000037Cu)
3622 #define CSL_DFE_CB_GSG3_TIMER1_REG_RESETVAL (0x00000000u)
3624 /* GSG3_TIMER2 */
3625 typedef struct
3626 {
3627 #ifdef _BIG_ENDIAN
3628 Uint32 rsvd0 : 8;
3629 Uint32 gsg3_timer2 : 24;
3630 #else
3631 Uint32 gsg3_timer2 : 24;
3632 Uint32 rsvd0 : 8;
3633 #endif
3634 } CSL_DFE_CB_GSG3_TIMER2_REG;
3636 /* same as gsg0_timer2 */
3637 #define CSL_DFE_CB_GSG3_TIMER2_REG_GSG3_TIMER2_MASK (0x00FFFFFFu)
3638 #define CSL_DFE_CB_GSG3_TIMER2_REG_GSG3_TIMER2_SHIFT (0x00000000u)
3639 #define CSL_DFE_CB_GSG3_TIMER2_REG_GSG3_TIMER2_RESETVAL (0x00000000u)
3641 #define CSL_DFE_CB_GSG3_TIMER2_REG_ADDR (0x00000380u)
3642 #define CSL_DFE_CB_GSG3_TIMER2_REG_RESETVAL (0x00000000u)
3644 /* GSG3_TIMER3 */
3645 typedef struct
3646 {
3647 #ifdef _BIG_ENDIAN
3648 Uint32 rsvd0 : 8;
3649 Uint32 gsg3_timer3 : 24;
3650 #else
3651 Uint32 gsg3_timer3 : 24;
3652 Uint32 rsvd0 : 8;
3653 #endif
3654 } CSL_DFE_CB_GSG3_TIMER3_REG;
3656 /* same as gsg0_timer3 */
3657 #define CSL_DFE_CB_GSG3_TIMER3_REG_GSG3_TIMER3_MASK (0x00FFFFFFu)
3658 #define CSL_DFE_CB_GSG3_TIMER3_REG_GSG3_TIMER3_SHIFT (0x00000000u)
3659 #define CSL_DFE_CB_GSG3_TIMER3_REG_GSG3_TIMER3_RESETVAL (0x00000000u)
3661 #define CSL_DFE_CB_GSG3_TIMER3_REG_ADDR (0x00000384u)
3662 #define CSL_DFE_CB_GSG3_TIMER3_REG_RESETVAL (0x00000000u)
3664 /* GSG3_TIMER4 */
3665 typedef struct
3666 {
3667 #ifdef _BIG_ENDIAN
3668 Uint32 rsvd0 : 8;
3669 Uint32 gsg3_timer4 : 24;
3670 #else
3671 Uint32 gsg3_timer4 : 24;
3672 Uint32 rsvd0 : 8;
3673 #endif
3674 } CSL_DFE_CB_GSG3_TIMER4_REG;
3676 /* same as gsg0_timer4 */
3677 #define CSL_DFE_CB_GSG3_TIMER4_REG_GSG3_TIMER4_MASK (0x00FFFFFFu)
3678 #define CSL_DFE_CB_GSG3_TIMER4_REG_GSG3_TIMER4_SHIFT (0x00000000u)
3679 #define CSL_DFE_CB_GSG3_TIMER4_REG_GSG3_TIMER4_RESETVAL (0x00000000u)
3681 #define CSL_DFE_CB_GSG3_TIMER4_REG_ADDR (0x00000388u)
3682 #define CSL_DFE_CB_GSG3_TIMER4_REG_RESETVAL (0x00000000u)
3684 /* GSG3_TIMER5 */
3685 typedef struct
3686 {
3687 #ifdef _BIG_ENDIAN
3688 Uint32 rsvd0 : 8;
3689 Uint32 gsg3_timer5 : 24;
3690 #else
3691 Uint32 gsg3_timer5 : 24;
3692 Uint32 rsvd0 : 8;
3693 #endif
3694 } CSL_DFE_CB_GSG3_TIMER5_REG;
3696 /* same as gsg0_timer5 */
3697 #define CSL_DFE_CB_GSG3_TIMER5_REG_GSG3_TIMER5_MASK (0x00FFFFFFu)
3698 #define CSL_DFE_CB_GSG3_TIMER5_REG_GSG3_TIMER5_SHIFT (0x00000000u)
3699 #define CSL_DFE_CB_GSG3_TIMER5_REG_GSG3_TIMER5_RESETVAL (0x00000000u)
3701 #define CSL_DFE_CB_GSG3_TIMER5_REG_ADDR (0x0000038Cu)
3702 #define CSL_DFE_CB_GSG3_TIMER5_REG_RESETVAL (0x00000000u)
3704 /* GSG4_DELAYFROMSYNC */
3705 typedef struct
3706 {
3707 #ifdef _BIG_ENDIAN
3708 Uint32 rsvd0 : 8;
3709 Uint32 gsg4_delayfromsync : 24;
3710 #else
3711 Uint32 gsg4_delayfromsync : 24;
3712 Uint32 rsvd0 : 8;
3713 #endif
3714 } CSL_DFE_CB_GSG4_DELAYFROMSYNC_REG;
3716 /* same as gsg0_delayfromsync */
3717 #define CSL_DFE_CB_GSG4_DELAYFROMSYNC_REG_GSG4_DELAYFROMSYNC_MASK (0x00FFFFFFu)
3718 #define CSL_DFE_CB_GSG4_DELAYFROMSYNC_REG_GSG4_DELAYFROMSYNC_SHIFT (0x00000000u)
3719 #define CSL_DFE_CB_GSG4_DELAYFROMSYNC_REG_GSG4_DELAYFROMSYNC_RESETVAL (0x00000000u)
3721 #define CSL_DFE_CB_GSG4_DELAYFROMSYNC_REG_ADDR (0x00000390u)
3722 #define CSL_DFE_CB_GSG4_DELAYFROMSYNC_REG_RESETVAL (0x00000000u)
3724 /* GSG4_TIMER1 */
3725 typedef struct
3726 {
3727 #ifdef _BIG_ENDIAN
3728 Uint32 rsvd0 : 8;
3729 Uint32 gsg4_timer1 : 24;
3730 #else
3731 Uint32 gsg4_timer1 : 24;
3732 Uint32 rsvd0 : 8;
3733 #endif
3734 } CSL_DFE_CB_GSG4_TIMER1_REG;
3736 /* same as gsg0_timer1 */
3737 #define CSL_DFE_CB_GSG4_TIMER1_REG_GSG4_TIMER1_MASK (0x00FFFFFFu)
3738 #define CSL_DFE_CB_GSG4_TIMER1_REG_GSG4_TIMER1_SHIFT (0x00000000u)
3739 #define CSL_DFE_CB_GSG4_TIMER1_REG_GSG4_TIMER1_RESETVAL (0x00000000u)
3741 #define CSL_DFE_CB_GSG4_TIMER1_REG_ADDR (0x00000394u)
3742 #define CSL_DFE_CB_GSG4_TIMER1_REG_RESETVAL (0x00000000u)
3744 /* GSG4_TIMER2 */
3745 typedef struct
3746 {
3747 #ifdef _BIG_ENDIAN
3748 Uint32 rsvd0 : 8;
3749 Uint32 gsg4_timer2 : 24;
3750 #else
3751 Uint32 gsg4_timer2 : 24;
3752 Uint32 rsvd0 : 8;
3753 #endif
3754 } CSL_DFE_CB_GSG4_TIMER2_REG;
3756 /* same as gsg0_timer2 */
3757 #define CSL_DFE_CB_GSG4_TIMER2_REG_GSG4_TIMER2_MASK (0x00FFFFFFu)
3758 #define CSL_DFE_CB_GSG4_TIMER2_REG_GSG4_TIMER2_SHIFT (0x00000000u)
3759 #define CSL_DFE_CB_GSG4_TIMER2_REG_GSG4_TIMER2_RESETVAL (0x00000000u)
3761 #define CSL_DFE_CB_GSG4_TIMER2_REG_ADDR (0x00000398u)
3762 #define CSL_DFE_CB_GSG4_TIMER2_REG_RESETVAL (0x00000000u)
3764 /* GSG4_TIMER3 */
3765 typedef struct
3766 {
3767 #ifdef _BIG_ENDIAN
3768 Uint32 rsvd0 : 8;
3769 Uint32 gsg4_timer3 : 24;
3770 #else
3771 Uint32 gsg4_timer3 : 24;
3772 Uint32 rsvd0 : 8;
3773 #endif
3774 } CSL_DFE_CB_GSG4_TIMER3_REG;
3776 /* same as gsg0_timer3 */
3777 #define CSL_DFE_CB_GSG4_TIMER3_REG_GSG4_TIMER3_MASK (0x00FFFFFFu)
3778 #define CSL_DFE_CB_GSG4_TIMER3_REG_GSG4_TIMER3_SHIFT (0x00000000u)
3779 #define CSL_DFE_CB_GSG4_TIMER3_REG_GSG4_TIMER3_RESETVAL (0x00000000u)
3781 #define CSL_DFE_CB_GSG4_TIMER3_REG_ADDR (0x0000039Cu)
3782 #define CSL_DFE_CB_GSG4_TIMER3_REG_RESETVAL (0x00000000u)
3784 /* GSG4_TIMER4 */
3785 typedef struct
3786 {
3787 #ifdef _BIG_ENDIAN
3788 Uint32 rsvd0 : 8;
3789 Uint32 gsg4_timer4 : 24;
3790 #else
3791 Uint32 gsg4_timer4 : 24;
3792 Uint32 rsvd0 : 8;
3793 #endif
3794 } CSL_DFE_CB_GSG4_TIMER4_REG;
3796 /* same as gsg0_timer4 */
3797 #define CSL_DFE_CB_GSG4_TIMER4_REG_GSG4_TIMER4_MASK (0x00FFFFFFu)
3798 #define CSL_DFE_CB_GSG4_TIMER4_REG_GSG4_TIMER4_SHIFT (0x00000000u)
3799 #define CSL_DFE_CB_GSG4_TIMER4_REG_GSG4_TIMER4_RESETVAL (0x00000000u)
3801 #define CSL_DFE_CB_GSG4_TIMER4_REG_ADDR (0x000003A0u)
3802 #define CSL_DFE_CB_GSG4_TIMER4_REG_RESETVAL (0x00000000u)
3804 /* GSG4_TIMER5 */
3805 typedef struct
3806 {
3807 #ifdef _BIG_ENDIAN
3808 Uint32 rsvd0 : 8;
3809 Uint32 gsg4_timer5 : 24;
3810 #else
3811 Uint32 gsg4_timer5 : 24;
3812 Uint32 rsvd0 : 8;
3813 #endif
3814 } CSL_DFE_CB_GSG4_TIMER5_REG;
3816 /* same as gsg0_timer5 */
3817 #define CSL_DFE_CB_GSG4_TIMER5_REG_GSG4_TIMER5_MASK (0x00FFFFFFu)
3818 #define CSL_DFE_CB_GSG4_TIMER5_REG_GSG4_TIMER5_SHIFT (0x00000000u)
3819 #define CSL_DFE_CB_GSG4_TIMER5_REG_GSG4_TIMER5_RESETVAL (0x00000000u)
3821 #define CSL_DFE_CB_GSG4_TIMER5_REG_ADDR (0x000003A4u)
3822 #define CSL_DFE_CB_GSG4_TIMER5_REG_RESETVAL (0x00000000u)
3824 /* GSG5_DELAYFROMSYNC */
3825 typedef struct
3826 {
3827 #ifdef _BIG_ENDIAN
3828 Uint32 rsvd0 : 8;
3829 Uint32 gsg5_delayfromsync : 24;
3830 #else
3831 Uint32 gsg5_delayfromsync : 24;
3832 Uint32 rsvd0 : 8;
3833 #endif
3834 } CSL_DFE_CB_GSG5_DELAYFROMSYNC_REG;
3836 /* same as gsg0_delayfromsync */
3837 #define CSL_DFE_CB_GSG5_DELAYFROMSYNC_REG_GSG5_DELAYFROMSYNC_MASK (0x00FFFFFFu)
3838 #define CSL_DFE_CB_GSG5_DELAYFROMSYNC_REG_GSG5_DELAYFROMSYNC_SHIFT (0x00000000u)
3839 #define CSL_DFE_CB_GSG5_DELAYFROMSYNC_REG_GSG5_DELAYFROMSYNC_RESETVAL (0x00000000u)
3841 #define CSL_DFE_CB_GSG5_DELAYFROMSYNC_REG_ADDR (0x000003A8u)
3842 #define CSL_DFE_CB_GSG5_DELAYFROMSYNC_REG_RESETVAL (0x00000000u)
3844 /* GSG5_TIMER1 */
3845 typedef struct
3846 {
3847 #ifdef _BIG_ENDIAN
3848 Uint32 rsvd0 : 8;
3849 Uint32 gsg5_timer1 : 24;
3850 #else
3851 Uint32 gsg5_timer1 : 24;
3852 Uint32 rsvd0 : 8;
3853 #endif
3854 } CSL_DFE_CB_GSG5_TIMER1_REG;
3856 /* same as gsg0_timer1 */
3857 #define CSL_DFE_CB_GSG5_TIMER1_REG_GSG5_TIMER1_MASK (0x00FFFFFFu)
3858 #define CSL_DFE_CB_GSG5_TIMER1_REG_GSG5_TIMER1_SHIFT (0x00000000u)
3859 #define CSL_DFE_CB_GSG5_TIMER1_REG_GSG5_TIMER1_RESETVAL (0x00000000u)
3861 #define CSL_DFE_CB_GSG5_TIMER1_REG_ADDR (0x000003ACu)
3862 #define CSL_DFE_CB_GSG5_TIMER1_REG_RESETVAL (0x00000000u)
3864 /* GSG5_TIMER2 */
3865 typedef struct
3866 {
3867 #ifdef _BIG_ENDIAN
3868 Uint32 rsvd0 : 8;
3869 Uint32 gsg5_timer2 : 24;
3870 #else
3871 Uint32 gsg5_timer2 : 24;
3872 Uint32 rsvd0 : 8;
3873 #endif
3874 } CSL_DFE_CB_GSG5_TIMER2_REG;
3876 /* same as gsg0_timer2 */
3877 #define CSL_DFE_CB_GSG5_TIMER2_REG_GSG5_TIMER2_MASK (0x00FFFFFFu)
3878 #define CSL_DFE_CB_GSG5_TIMER2_REG_GSG5_TIMER2_SHIFT (0x00000000u)
3879 #define CSL_DFE_CB_GSG5_TIMER2_REG_GSG5_TIMER2_RESETVAL (0x00000000u)
3881 #define CSL_DFE_CB_GSG5_TIMER2_REG_ADDR (0x000003B0u)
3882 #define CSL_DFE_CB_GSG5_TIMER2_REG_RESETVAL (0x00000000u)
3884 /* GSG5_TIMER3 */
3885 typedef struct
3886 {
3887 #ifdef _BIG_ENDIAN
3888 Uint32 rsvd0 : 8;
3889 Uint32 gsg5_timer3 : 24;
3890 #else
3891 Uint32 gsg5_timer3 : 24;
3892 Uint32 rsvd0 : 8;
3893 #endif
3894 } CSL_DFE_CB_GSG5_TIMER3_REG;
3896 /* same as gsg0_timer3 */
3897 #define CSL_DFE_CB_GSG5_TIMER3_REG_GSG5_TIMER3_MASK (0x00FFFFFFu)
3898 #define CSL_DFE_CB_GSG5_TIMER3_REG_GSG5_TIMER3_SHIFT (0x00000000u)
3899 #define CSL_DFE_CB_GSG5_TIMER3_REG_GSG5_TIMER3_RESETVAL (0x00000000u)
3901 #define CSL_DFE_CB_GSG5_TIMER3_REG_ADDR (0x000003B4u)
3902 #define CSL_DFE_CB_GSG5_TIMER3_REG_RESETVAL (0x00000000u)
3904 /* GSG5_TIMER4 */
3905 typedef struct
3906 {
3907 #ifdef _BIG_ENDIAN
3908 Uint32 rsvd0 : 8;
3909 Uint32 gsg5_timer4 : 24;
3910 #else
3911 Uint32 gsg5_timer4 : 24;
3912 Uint32 rsvd0 : 8;
3913 #endif
3914 } CSL_DFE_CB_GSG5_TIMER4_REG;
3916 /* same as gsg0_timer4 */
3917 #define CSL_DFE_CB_GSG5_TIMER4_REG_GSG5_TIMER4_MASK (0x00FFFFFFu)
3918 #define CSL_DFE_CB_GSG5_TIMER4_REG_GSG5_TIMER4_SHIFT (0x00000000u)
3919 #define CSL_DFE_CB_GSG5_TIMER4_REG_GSG5_TIMER4_RESETVAL (0x00000000u)
3921 #define CSL_DFE_CB_GSG5_TIMER4_REG_ADDR (0x000003B8u)
3922 #define CSL_DFE_CB_GSG5_TIMER4_REG_RESETVAL (0x00000000u)
3924 /* GSG5_TIMER5 */
3925 typedef struct
3926 {
3927 #ifdef _BIG_ENDIAN
3928 Uint32 rsvd0 : 8;
3929 Uint32 gsg5_timer5 : 24;
3930 #else
3931 Uint32 gsg5_timer5 : 24;
3932 Uint32 rsvd0 : 8;
3933 #endif
3934 } CSL_DFE_CB_GSG5_TIMER5_REG;
3936 /* same as gsg0_timer5 */
3937 #define CSL_DFE_CB_GSG5_TIMER5_REG_GSG5_TIMER5_MASK (0x00FFFFFFu)
3938 #define CSL_DFE_CB_GSG5_TIMER5_REG_GSG5_TIMER5_SHIFT (0x00000000u)
3939 #define CSL_DFE_CB_GSG5_TIMER5_REG_GSG5_TIMER5_RESETVAL (0x00000000u)
3941 #define CSL_DFE_CB_GSG5_TIMER5_REG_ADDR (0x000003BCu)
3942 #define CSL_DFE_CB_GSG5_TIMER5_REG_RESETVAL (0x00000000u)
3944 /* GSG_SSEL */
3945 typedef struct
3946 {
3947 #ifdef _BIG_ENDIAN
3948 Uint32 rsvd0 : 8;
3949 Uint32 gsg5_ssel : 4;
3950 Uint32 gsg4_ssel : 4;
3951 Uint32 gsg3_ssel : 4;
3952 Uint32 gsg2_ssel : 4;
3953 Uint32 gsg1_ssel : 4;
3954 Uint32 gsg0_ssel : 4;
3955 #else
3956 Uint32 gsg0_ssel : 4;
3957 Uint32 gsg1_ssel : 4;
3958 Uint32 gsg2_ssel : 4;
3959 Uint32 gsg3_ssel : 4;
3960 Uint32 gsg4_ssel : 4;
3961 Uint32 gsg5_ssel : 4;
3962 Uint32 rsvd0 : 8;
3963 #endif
3964 } CSL_DFE_CB_GSG_SSEL_REG;
3966 /* gsg0 sync select */
3967 #define CSL_DFE_CB_GSG_SSEL_REG_GSG0_SSEL_MASK (0x0000000Fu)
3968 #define CSL_DFE_CB_GSG_SSEL_REG_GSG0_SSEL_SHIFT (0x00000000u)
3969 #define CSL_DFE_CB_GSG_SSEL_REG_GSG0_SSEL_RESETVAL (0x00000000u)
3971 /* gsg1 sync select */
3972 #define CSL_DFE_CB_GSG_SSEL_REG_GSG1_SSEL_MASK (0x000000F0u)
3973 #define CSL_DFE_CB_GSG_SSEL_REG_GSG1_SSEL_SHIFT (0x00000004u)
3974 #define CSL_DFE_CB_GSG_SSEL_REG_GSG1_SSEL_RESETVAL (0x00000000u)
3976 /* gsg2 sync select */
3977 #define CSL_DFE_CB_GSG_SSEL_REG_GSG2_SSEL_MASK (0x00000F00u)
3978 #define CSL_DFE_CB_GSG_SSEL_REG_GSG2_SSEL_SHIFT (0x00000008u)
3979 #define CSL_DFE_CB_GSG_SSEL_REG_GSG2_SSEL_RESETVAL (0x00000000u)
3981 /* gsg3 sync select */
3982 #define CSL_DFE_CB_GSG_SSEL_REG_GSG3_SSEL_MASK (0x0000F000u)
3983 #define CSL_DFE_CB_GSG_SSEL_REG_GSG3_SSEL_SHIFT (0x0000000Cu)
3984 #define CSL_DFE_CB_GSG_SSEL_REG_GSG3_SSEL_RESETVAL (0x00000000u)
3986 /* gsg4 sync select */
3987 #define CSL_DFE_CB_GSG_SSEL_REG_GSG4_SSEL_MASK (0x000F0000u)
3988 #define CSL_DFE_CB_GSG_SSEL_REG_GSG4_SSEL_SHIFT (0x00000010u)
3989 #define CSL_DFE_CB_GSG_SSEL_REG_GSG4_SSEL_RESETVAL (0x00000000u)
3991 /* gsg5 sync select */
3992 #define CSL_DFE_CB_GSG_SSEL_REG_GSG5_SSEL_MASK (0x00F00000u)
3993 #define CSL_DFE_CB_GSG_SSEL_REG_GSG5_SSEL_SHIFT (0x00000014u)
3994 #define CSL_DFE_CB_GSG_SSEL_REG_GSG5_SSEL_RESETVAL (0x00000000u)
3996 #define CSL_DFE_CB_GSG_SSEL_REG_ADDR (0x000003C4u)
3997 #define CSL_DFE_CB_GSG_SSEL_REG_RESETVAL (0x00000000u)
3999 /* GSG_SEQ_SEL_PART1 */
4000 typedef struct
4001 {
4002 #ifdef _BIG_ENDIAN
4003 Uint32 cb_f_fb_ant2_gsg_sel : 4;
4004 Uint32 cb_f_ref_ant2_gsg_sel : 4;
4005 Uint32 cb_f_fb_ant1_gsg_sel : 4;
4006 Uint32 cb_f_ref_ant1_gsg_sel : 4;
4007 Uint32 cb_f_fb_ant0_gsg_sel : 4;
4008 Uint32 cb_f_ref_ant0_gsg_sel : 4;
4009 Uint32 cb_c_fb_gsg_sel : 4;
4010 Uint32 cb_c_ref_gsg_sel : 4;
4011 #else
4012 Uint32 cb_c_ref_gsg_sel : 4;
4013 Uint32 cb_c_fb_gsg_sel : 4;
4014 Uint32 cb_f_ref_ant0_gsg_sel : 4;
4015 Uint32 cb_f_fb_ant0_gsg_sel : 4;
4016 Uint32 cb_f_ref_ant1_gsg_sel : 4;
4017 Uint32 cb_f_fb_ant1_gsg_sel : 4;
4018 Uint32 cb_f_ref_ant2_gsg_sel : 4;
4019 Uint32 cb_f_fb_ant2_gsg_sel : 4;
4020 #endif
4021 } CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG;
4023 /* gsg signal selection for CB-C capture of reference signal, bit [0]: */
4024 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_C_REF_GSG_SEL_MASK (0x0000000Fu)
4025 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_C_REF_GSG_SEL_SHIFT (0x00000000u)
4026 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_C_REF_GSG_SEL_RESETVAL (0x00000000u)
4028 /* similar to 'cba_gsg_sel' */
4029 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_C_FB_GSG_SEL_MASK (0x000000F0u)
4030 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_C_FB_GSG_SEL_SHIFT (0x00000004u)
4031 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_C_FB_GSG_SEL_RESETVAL (0x00000000u)
4033 /* similar to 'cba_gsg_sel' (define this register per antenna such that we can quickly switch between four antennas for CB-F with out aid from DSP) */
4034 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_REF_ANT0_GSG_SEL_MASK (0x00000F00u)
4035 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_REF_ANT0_GSG_SEL_SHIFT (0x00000008u)
4036 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_REF_ANT0_GSG_SEL_RESETVAL (0x00000000u)
4038 /* similar to 'cba_gsg_sel' */
4039 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_FB_ANT0_GSG_SEL_MASK (0x0000F000u)
4040 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_FB_ANT0_GSG_SEL_SHIFT (0x0000000Cu)
4041 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_FB_ANT0_GSG_SEL_RESETVAL (0x00000000u)
4043 /* similar to 'cba_gsg_sel' */
4044 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_REF_ANT1_GSG_SEL_MASK (0x000F0000u)
4045 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_REF_ANT1_GSG_SEL_SHIFT (0x00000010u)
4046 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_REF_ANT1_GSG_SEL_RESETVAL (0x00000000u)
4048 /* similar to 'cba_gsg_sel' */
4049 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_FB_ANT1_GSG_SEL_MASK (0x00F00000u)
4050 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_FB_ANT1_GSG_SEL_SHIFT (0x00000014u)
4051 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_FB_ANT1_GSG_SEL_RESETVAL (0x00000000u)
4053 /* similar to 'cba_gsg_sel' */
4054 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_REF_ANT2_GSG_SEL_MASK (0x0F000000u)
4055 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_REF_ANT2_GSG_SEL_SHIFT (0x00000018u)
4056 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_REF_ANT2_GSG_SEL_RESETVAL (0x00000000u)
4058 /* similar to 'cba_gsg_sel' */
4059 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_FB_ANT2_GSG_SEL_MASK (0xF0000000u)
4060 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_FB_ANT2_GSG_SEL_SHIFT (0x0000001Cu)
4061 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_CB_F_FB_ANT2_GSG_SEL_RESETVAL (0x00000000u)
4063 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_ADDR (0x000003C8u)
4064 #define CSL_DFE_CB_GSG_SEQ_SEL_PART1_REG_RESETVAL (0x00000000u)
4066 /* GSG_SEQ_SEL_PART2 */
4067 typedef struct
4068 {
4069 #ifdef _BIG_ENDIAN
4070 Uint32 rsvd0 : 16;
4071 Uint32 trigb_gsg_sel : 4;
4072 Uint32 triga_gsg_sel : 4;
4073 Uint32 cb_f_fb_ant3_gsg_sel : 4;
4074 Uint32 cb_f_ref_ant3_gsg_sel : 4;
4075 #else
4076 Uint32 cb_f_ref_ant3_gsg_sel : 4;
4077 Uint32 cb_f_fb_ant3_gsg_sel : 4;
4078 Uint32 triga_gsg_sel : 4;
4079 Uint32 trigb_gsg_sel : 4;
4080 Uint32 rsvd0 : 16;
4081 #endif
4082 } CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG;
4084 /* similar to 'cba_gsg_sel' */
4085 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_CB_F_REF_ANT3_GSG_SEL_MASK (0x0000000Fu)
4086 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_CB_F_REF_ANT3_GSG_SEL_SHIFT (0x00000000u)
4087 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_CB_F_REF_ANT3_GSG_SEL_RESETVAL (0x00000000u)
4089 /* similar to 'cba_gsg_sel' */
4090 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_CB_F_FB_ANT3_GSG_SEL_MASK (0x000000F0u)
4091 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_CB_F_FB_ANT3_GSG_SEL_SHIFT (0x00000004u)
4092 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_CB_F_FB_ANT3_GSG_SEL_RESETVAL (0x00000000u)
4094 /* similar to 'cba_gsg_sel' */
4095 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_TRIGA_GSG_SEL_MASK (0x00000F00u)
4096 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_TRIGA_GSG_SEL_SHIFT (0x00000008u)
4097 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_TRIGA_GSG_SEL_RESETVAL (0x00000000u)
4099 /* similar to 'cba_gsg_sel' */
4100 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_TRIGB_GSG_SEL_MASK (0x0000F000u)
4101 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_TRIGB_GSG_SEL_SHIFT (0x0000000Cu)
4102 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_TRIGB_GSG_SEL_RESETVAL (0x00000000u)
4104 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_ADDR (0x000003CCu)
4105 #define CSL_DFE_CB_GSG_SEQ_SEL_PART2_REG_RESETVAL (0x00000000u)
4107 /* SILENT_DETECT_SETTING */
4108 typedef struct
4109 {
4110 #ifdef _BIG_ENDIAN
4111 Uint32 silent_detect_thresh : 24;
4112 Uint32 silent_detect_samples : 7;
4113 Uint32 silent_detect_en : 1;
4114 #else
4115 Uint32 silent_detect_en : 1;
4116 Uint32 silent_detect_samples : 7;
4117 Uint32 silent_detect_thresh : 24;
4118 #endif
4119 } CSL_DFE_CB_SILENT_DETECT_SETTING_REG;
4121 /* enable silent detection */
4122 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_SILENT_DETECT_EN_MASK (0x00000001u)
4123 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_SILENT_DETECT_EN_SHIFT (0x00000000u)
4124 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_SILENT_DETECT_EN_RESETVAL (0x00000000u)
4126 /* Number of continuous samples with mag_squared value below the threshold in a chunk to qualify 'silent period', 0~127. */
4127 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_SILENT_DETECT_SAMPLES_MASK (0x000000FEu)
4128 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_SILENT_DETECT_SAMPLES_SHIFT (0x00000001u)
4129 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_SILENT_DETECT_SAMPLES_RESETVAL (0x00000000u)
4131 /* Unsigned value. Threshold to compare mag-squared of the complex signal to qualify silent period'. Mag-squared of signal (only take 16-MSB's) will be saturated to 24-bit before comparison. */
4132 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_SILENT_DETECT_THRESH_MASK (0xFFFFFF00u)
4133 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_SILENT_DETECT_THRESH_SHIFT (0x00000008u)
4134 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_SILENT_DETECT_THRESH_RESETVAL (0x00000000u)
4136 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_ADDR (0x000003D0u)
4137 #define CSL_DFE_CB_SILENT_DETECT_SETTING_REG_RESETVAL (0x00000000u)
4139 /* CB_F_CHUNK_SELECTION */
4140 typedef struct
4141 {
4142 #ifdef _BIG_ENDIAN
4143 Uint32 rsvd3 : 17;
4144 Uint32 ant3_criteria_disable : 3;
4145 Uint32 rsvd2 : 1;
4146 Uint32 ant2_criteria_disable : 3;
4147 Uint32 rsvd1 : 1;
4148 Uint32 ant1_criteria_disable : 3;
4149 Uint32 rsvd0 : 1;
4150 Uint32 ant0_criteria_disable : 3;
4151 #else
4152 Uint32 ant0_criteria_disable : 3;
4153 Uint32 rsvd0 : 1;
4154 Uint32 ant1_criteria_disable : 3;
4155 Uint32 rsvd1 : 1;
4156 Uint32 ant2_criteria_disable : 3;
4157 Uint32 rsvd2 : 1;
4158 Uint32 ant3_criteria_disable : 3;
4159 Uint32 rsvd3 : 17;
4160 #endif
4161 } CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG;
4163 /* bit[0] is to disable highest peak criteria, bit[1] is to disable RMS value criteria, bit [2] is to diable peak density (sum of 3 max peaks) criteria: 0 = enabled, 1= disabled. */
4164 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT0_CRITERIA_DISABLE_MASK (0x00000007u)
4165 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT0_CRITERIA_DISABLE_SHIFT (0x00000000u)
4166 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT0_CRITERIA_DISABLE_RESETVAL (0x00000000u)
4168 /* similar to ant1_criteria_disable */
4169 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT1_CRITERIA_DISABLE_MASK (0x00000070u)
4170 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT1_CRITERIA_DISABLE_SHIFT (0x00000004u)
4171 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT1_CRITERIA_DISABLE_RESETVAL (0x00000000u)
4173 /* similar to ant2_criteria_disable */
4174 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT2_CRITERIA_DISABLE_MASK (0x00000700u)
4175 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT2_CRITERIA_DISABLE_SHIFT (0x00000008u)
4176 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT2_CRITERIA_DISABLE_RESETVAL (0x00000000u)
4178 /* similar to ant3_criteria_disable */
4179 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT3_CRITERIA_DISABLE_MASK (0x00007000u)
4180 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT3_CRITERIA_DISABLE_SHIFT (0x0000000Cu)
4181 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ANT3_CRITERIA_DISABLE_RESETVAL (0x00000000u)
4183 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_ADDR (0x000003D4u)
4184 #define CSL_DFE_CB_CB_F_CHUNK_SELECTION_REG_RESETVAL (0x00000000u)
4186 /* CB_F_BROKEN_CHAIN_DETECTION */
4187 typedef struct
4188 {
4189 #ifdef _BIG_ENDIAN
4190 Uint32 rsvd0 : 12;
4191 Uint32 cb_f_ref_fb_powerratio : 4;
4192 Uint32 cb_f_powerth : 16;
4193 #else
4194 Uint32 cb_f_powerth : 16;
4195 Uint32 cb_f_ref_fb_powerratio : 4;
4196 Uint32 rsvd0 : 12;
4197 #endif
4198 } CSL_DFE_CB_CB_F_BROKEN_CHAIN_DETECTION_REG;
4200 /* unsigned value in (-1, 17) format. Threshold to compare the RMS power of the captured reference chunk. If reference chunk RMS value is greater than this threshold and (feedback chunk RMS * cb_f_ref_fb_powerRatio), the feedback chain will be considered broken. */
4201 #define CSL_DFE_CB_CB_F_BROKEN_CHAIN_DETECTION_REG_CB_F_POWERTH_MASK (0x0000FFFFu)
4202 #define CSL_DFE_CB_CB_F_BROKEN_CHAIN_DETECTION_REG_CB_F_POWERTH_SHIFT (0x00000000u)
4203 #define CSL_DFE_CB_CB_F_BROKEN_CHAIN_DETECTION_REG_CB_F_POWERTH_RESETVAL (0x00000000u)
4205 /* unsigned value in (4, 0), will be multiplied with feedback chunk RMS before compare to reference chunk RMS. */
4206 #define CSL_DFE_CB_CB_F_BROKEN_CHAIN_DETECTION_REG_CB_F_REF_FB_POWERRATIO_MASK (0x000F0000u)
4207 #define CSL_DFE_CB_CB_F_BROKEN_CHAIN_DETECTION_REG_CB_F_REF_FB_POWERRATIO_SHIFT (0x00000010u)
4208 #define CSL_DFE_CB_CB_F_BROKEN_CHAIN_DETECTION_REG_CB_F_REF_FB_POWERRATIO_RESETVAL (0x00000000u)
4210 #define CSL_DFE_CB_CB_F_BROKEN_CHAIN_DETECTION_REG_ADDR (0x000003D8u)
4211 #define CSL_DFE_CB_CB_F_BROKEN_CHAIN_DETECTION_REG_RESETVAL (0x00000000u)
4213 /* CB_F_MAXREFPOWER_ANT0_1 */
4214 typedef struct
4215 {
4216 #ifdef _BIG_ENDIAN
4217 Uint32 cb_f_maxrefpower_ant1 : 16;
4218 Uint32 cb_f_maxrefpower_ant0 : 16;
4219 #else
4220 Uint32 cb_f_maxrefpower_ant0 : 16;
4221 Uint32 cb_f_maxrefpower_ant1 : 16;
4222 #endif
4223 } CSL_DFE_CB_CB_F_MAXREFPOWER_ANT0_1_REG;
4225 /* Normalized block RMS power of the reference signal in (-1, 17) format. The position and duration of the block is defined by the corresponding GSG gating signal. This RMS power will be compared to the average power of captured reference chunks to determine the validity of this capture. */
4226 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT0_1_REG_CB_F_MAXREFPOWER_ANT0_MASK (0x0000FFFFu)
4227 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT0_1_REG_CB_F_MAXREFPOWER_ANT0_SHIFT (0x00000000u)
4228 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT0_1_REG_CB_F_MAXREFPOWER_ANT0_RESETVAL (0x00000000u)
4230 /* same as above, for antenna1. */
4231 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT0_1_REG_CB_F_MAXREFPOWER_ANT1_MASK (0xFFFF0000u)
4232 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT0_1_REG_CB_F_MAXREFPOWER_ANT1_SHIFT (0x00000010u)
4233 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT0_1_REG_CB_F_MAXREFPOWER_ANT1_RESETVAL (0x00000000u)
4235 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT0_1_REG_ADDR (0x000003DCu)
4236 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT0_1_REG_RESETVAL (0x00000000u)
4238 /* CB_F_MAXREFPOWER_ANT2_3 */
4239 typedef struct
4240 {
4241 #ifdef _BIG_ENDIAN
4242 Uint32 cb_f_maxrefpower_ant3 : 16;
4243 Uint32 cb_f_maxrefpower_ant2 : 16;
4244 #else
4245 Uint32 cb_f_maxrefpower_ant2 : 16;
4246 Uint32 cb_f_maxrefpower_ant3 : 16;
4247 #endif
4248 } CSL_DFE_CB_CB_F_MAXREFPOWER_ANT2_3_REG;
4250 /* same as above, for antenna2. */
4251 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT2_3_REG_CB_F_MAXREFPOWER_ANT2_MASK (0x0000FFFFu)
4252 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT2_3_REG_CB_F_MAXREFPOWER_ANT2_SHIFT (0x00000000u)
4253 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT2_3_REG_CB_F_MAXREFPOWER_ANT2_RESETVAL (0x00000000u)
4255 /* same as above, for antenna3. */
4256 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT2_3_REG_CB_F_MAXREFPOWER_ANT3_MASK (0xFFFF0000u)
4257 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT2_3_REG_CB_F_MAXREFPOWER_ANT3_SHIFT (0x00000010u)
4258 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT2_3_REG_CB_F_MAXREFPOWER_ANT3_RESETVAL (0x00000000u)
4260 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT2_3_REG_ADDR (0x000003E0u)
4261 #define CSL_DFE_CB_CB_F_MAXREFPOWER_ANT2_3_REG_RESETVAL (0x00000000u)
4263 /* CB_F_DELTAPOWERINLINEAR */
4264 typedef struct
4265 {
4266 #ifdef _BIG_ENDIAN
4267 Uint32 rsvd3 : 2;
4268 Uint32 cb_f_deltapower_ant3 : 6;
4269 Uint32 rsvd2 : 2;
4270 Uint32 cb_f_deltapower_ant2 : 6;
4271 Uint32 rsvd1 : 2;
4272 Uint32 cb_f_deltapower_ant1 : 6;
4273 Uint32 rsvd0 : 2;
4274 Uint32 cb_f_deltapower_ant0 : 6;
4275 #else
4276 Uint32 cb_f_deltapower_ant0 : 6;
4277 Uint32 rsvd0 : 2;
4278 Uint32 cb_f_deltapower_ant1 : 6;
4279 Uint32 rsvd1 : 2;
4280 Uint32 cb_f_deltapower_ant2 : 6;
4281 Uint32 rsvd2 : 2;
4282 Uint32 cb_f_deltapower_ant3 : 6;
4283 Uint32 rsvd3 : 2;
4284 #endif
4285 } CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG;
4287 /* unsigned value in (0, 6). The meaured block RMS power of the reference signal for antenna0, i.e. cb_f_MaxRefPower_ant0, will be multiplied with 'cb_f_deltaPower_ant0' to get a dynamic threshold, which will be compared with average power of all captured reference chunks for antenna0 to check for 'bad buffer' condition. */
4288 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT0_MASK (0x0000003Fu)
4289 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT0_SHIFT (0x00000000u)
4290 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT0_RESETVAL (0x00000001u)
4292 /* same as 'cb_f_deltaPower_ant0', for antenna1 */
4293 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT1_MASK (0x00003F00u)
4294 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT1_SHIFT (0x00000008u)
4295 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT1_RESETVAL (0x00000001u)
4297 /* same as 'cb_f_deltaPower_ant0', for antenna2 */
4298 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT2_MASK (0x003F0000u)
4299 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT2_SHIFT (0x00000010u)
4300 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT2_RESETVAL (0x00000001u)
4302 /* same as 'cb_f_deltaPower_ant0', for antenna3 */
4303 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT3_MASK (0x3F000000u)
4304 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT3_SHIFT (0x00000018u)
4305 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_CB_F_DELTAPOWER_ANT3_RESETVAL (0x00000001u)
4307 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_ADDR (0x000003E4u)
4308 #define CSL_DFE_CB_CB_F_DELTAPOWERINLINEAR_REG_RESETVAL (0x01010101u)
4310 /* CB_F_BADBUFFER_DETECTION_EN */
4311 typedef struct
4312 {
4313 #ifdef _BIG_ENDIAN
4314 Uint32 rsvd0 : 28;
4315 Uint32 bad_buffer_detection_en_ant3 : 1;
4316 Uint32 bad_buffer_detection_en_ant2 : 1;
4317 Uint32 bad_buffer_detection_en_ant1 : 1;
4318 Uint32 bad_buffer_detection_en_ant0 : 1;
4319 #else
4320 Uint32 bad_buffer_detection_en_ant0 : 1;
4321 Uint32 bad_buffer_detection_en_ant1 : 1;
4322 Uint32 bad_buffer_detection_en_ant2 : 1;
4323 Uint32 bad_buffer_detection_en_ant3 : 1;
4324 Uint32 rsvd0 : 28;
4325 #endif
4326 } CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG;
4328 /* To enable bad buffer detection for antenna 0 */
4329 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT0_MASK (0x00000001u)
4330 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT0_SHIFT (0x00000000u)
4331 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT0_RESETVAL (0x00000000u)
4333 /* To enable bad buffer detection for antenna 1 */
4334 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT1_MASK (0x00000002u)
4335 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT1_SHIFT (0x00000001u)
4336 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT1_RESETVAL (0x00000000u)
4338 /* To enable bad buffer detection for antenna 2 */
4339 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT2_MASK (0x00000004u)
4340 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT2_SHIFT (0x00000002u)
4341 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT2_RESETVAL (0x00000000u)
4343 /* To enable bad buffer detection for antenna 3 */
4344 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT3_MASK (0x00000008u)
4345 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT3_SHIFT (0x00000003u)
4346 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_BAD_BUFFER_DETECTION_EN_ANT3_RESETVAL (0x00000000u)
4348 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_ADDR (0x000003E8u)
4349 #define CSL_DFE_CB_CB_F_BADBUFFER_DETECTION_EN_REG_RESETVAL (0x00000000u)
4351 /* POWER_MONITOR_SYNC_DLY_ANT0 */
4352 typedef struct
4353 {
4354 #ifdef _BIG_ENDIAN
4355 Uint32 rsvd0 : 8;
4356 Uint32 power_monitor_sync_dly_ant0 : 24;
4357 #else
4358 Uint32 power_monitor_sync_dly_ant0 : 24;
4359 Uint32 rsvd0 : 8;
4360 #endif
4361 } CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT0_REG;
4363 /* Delay of the start of power integration after sync event for antenna0 (in samples) */
4364 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT0_REG_POWER_MONITOR_SYNC_DLY_ANT0_MASK (0x00FFFFFFu)
4365 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT0_REG_POWER_MONITOR_SYNC_DLY_ANT0_SHIFT (0x00000000u)
4366 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT0_REG_POWER_MONITOR_SYNC_DLY_ANT0_RESETVAL (0x00000000u)
4368 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT0_REG_ADDR (0x000003ECu)
4369 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT0_REG_RESETVAL (0x00000000u)
4371 /* POWER_MONITOR_SYNC_DLY_ANT1 */
4372 typedef struct
4373 {
4374 #ifdef _BIG_ENDIAN
4375 Uint32 rsvd0 : 8;
4376 Uint32 power_monitor_sync_dly_ant1 : 24;
4377 #else
4378 Uint32 power_monitor_sync_dly_ant1 : 24;
4379 Uint32 rsvd0 : 8;
4380 #endif
4381 } CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT1_REG;
4383 /* Delay of the start of power integration after sync event for antenna1(in samples) */
4384 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT1_REG_POWER_MONITOR_SYNC_DLY_ANT1_MASK (0x00FFFFFFu)
4385 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT1_REG_POWER_MONITOR_SYNC_DLY_ANT1_SHIFT (0x00000000u)
4386 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT1_REG_POWER_MONITOR_SYNC_DLY_ANT1_RESETVAL (0x00000000u)
4388 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT1_REG_ADDR (0x000003F0u)
4389 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT1_REG_RESETVAL (0x00000000u)
4391 /* POWER_MONITOR_SYNC_DLY_ANT2 */
4392 typedef struct
4393 {
4394 #ifdef _BIG_ENDIAN
4395 Uint32 rsvd0 : 8;
4396 Uint32 power_monitor_sync_dly_ant2 : 24;
4397 #else
4398 Uint32 power_monitor_sync_dly_ant2 : 24;
4399 Uint32 rsvd0 : 8;
4400 #endif
4401 } CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT2_REG;
4403 /* Delay of the start of power integration after sync event for antenna2 (in samples) */
4404 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT2_REG_POWER_MONITOR_SYNC_DLY_ANT2_MASK (0x00FFFFFFu)
4405 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT2_REG_POWER_MONITOR_SYNC_DLY_ANT2_SHIFT (0x00000000u)
4406 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT2_REG_POWER_MONITOR_SYNC_DLY_ANT2_RESETVAL (0x00000000u)
4408 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT2_REG_ADDR (0x000003F4u)
4409 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT2_REG_RESETVAL (0x00000000u)
4411 /* POWER_MONITOR_SYNC_DLY_ANT3 */
4412 typedef struct
4413 {
4414 #ifdef _BIG_ENDIAN
4415 Uint32 rsvd0 : 8;
4416 Uint32 power_monitor_sync_dly_ant3 : 24;
4417 #else
4418 Uint32 power_monitor_sync_dly_ant3 : 24;
4419 Uint32 rsvd0 : 8;
4420 #endif
4421 } CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT3_REG;
4423 /* Delay of the start of power integration after sync event for antenna3 (in samples) */
4424 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT3_REG_POWER_MONITOR_SYNC_DLY_ANT3_MASK (0x00FFFFFFu)
4425 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT3_REG_POWER_MONITOR_SYNC_DLY_ANT3_SHIFT (0x00000000u)
4426 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT3_REG_POWER_MONITOR_SYNC_DLY_ANT3_RESETVAL (0x00000000u)
4428 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT3_REG_ADDR (0x000003F8u)
4429 #define CSL_DFE_CB_POWER_MONITOR_SYNC_DLY_ANT3_REG_RESETVAL (0x00000000u)
4431 /* POWER_MONITOR_INTG_PD_ANT0 */
4432 typedef struct
4433 {
4434 #ifdef _BIG_ENDIAN
4435 Uint32 rsvd0 : 8;
4436 Uint32 power_monitor_intg_pd_ant0 : 24;
4437 #else
4438 Uint32 power_monitor_intg_pd_ant0 : 24;
4439 Uint32 rsvd0 : 8;
4440 #endif
4441 } CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT0_REG;
4443 /* Power integration time in samples for antenna0, must be power of 2 to simplify normalization after power measurement is done. */
4444 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT0_REG_POWER_MONITOR_INTG_PD_ANT0_MASK (0x00FFFFFFu)
4445 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT0_REG_POWER_MONITOR_INTG_PD_ANT0_SHIFT (0x00000000u)
4446 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT0_REG_POWER_MONITOR_INTG_PD_ANT0_RESETVAL (0x00000000u)
4448 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT0_REG_ADDR (0x000003FCu)
4449 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT0_REG_RESETVAL (0x00000000u)
4451 /* POWER_MONITOR_INTG_PD_ANT1 */
4452 typedef struct
4453 {
4454 #ifdef _BIG_ENDIAN
4455 Uint32 rsvd0 : 8;
4456 Uint32 power_monitor_intg_pd_ant1 : 24;
4457 #else
4458 Uint32 power_monitor_intg_pd_ant1 : 24;
4459 Uint32 rsvd0 : 8;
4460 #endif
4461 } CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT1_REG;
4463 /* same as 'power_monitor_intg_pd_ant0', for antenna1 */
4464 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT1_REG_POWER_MONITOR_INTG_PD_ANT1_MASK (0x00FFFFFFu)
4465 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT1_REG_POWER_MONITOR_INTG_PD_ANT1_SHIFT (0x00000000u)
4466 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT1_REG_POWER_MONITOR_INTG_PD_ANT1_RESETVAL (0x00000000u)
4468 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT1_REG_ADDR (0x00000400u)
4469 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT1_REG_RESETVAL (0x00000000u)
4471 /* POWER_MONITOR_INTG_PD_ANT2 */
4472 typedef struct
4473 {
4474 #ifdef _BIG_ENDIAN
4475 Uint32 rsvd0 : 8;
4476 Uint32 power_monitor_intg_pd_ant2 : 24;
4477 #else
4478 Uint32 power_monitor_intg_pd_ant2 : 24;
4479 Uint32 rsvd0 : 8;
4480 #endif
4481 } CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT2_REG;
4483 /* same as 'power_monitor_intg_pd_ant0', for antenna2 */
4484 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT2_REG_POWER_MONITOR_INTG_PD_ANT2_MASK (0x00FFFFFFu)
4485 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT2_REG_POWER_MONITOR_INTG_PD_ANT2_SHIFT (0x00000000u)
4486 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT2_REG_POWER_MONITOR_INTG_PD_ANT2_RESETVAL (0x00000000u)
4488 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT2_REG_ADDR (0x00000404u)
4489 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT2_REG_RESETVAL (0x00000000u)
4491 /* POWER_MONITOR_INTG_PD_ANT3 */
4492 typedef struct
4493 {
4494 #ifdef _BIG_ENDIAN
4495 Uint32 rsvd0 : 8;
4496 Uint32 power_monitor_intg_pd_ant3 : 24;
4497 #else
4498 Uint32 power_monitor_intg_pd_ant3 : 24;
4499 Uint32 rsvd0 : 8;
4500 #endif
4501 } CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT3_REG;
4503 /* same as 'power_monitor_intg_pd_ant0', for antenna3 */
4504 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT3_REG_POWER_MONITOR_INTG_PD_ANT3_MASK (0x00FFFFFFu)
4505 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT3_REG_POWER_MONITOR_INTG_PD_ANT3_SHIFT (0x00000000u)
4506 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT3_REG_POWER_MONITOR_INTG_PD_ANT3_RESETVAL (0x00000000u)
4508 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT3_REG_ADDR (0x00000408u)
4509 #define CSL_DFE_CB_POWER_MONITOR_INTG_PD_ANT3_REG_RESETVAL (0x00000000u)
4511 /* POWER_MONITOR_CONFIG_ANT0 */
4512 typedef struct
4513 {
4514 #ifdef _BIG_ENDIAN
4515 Uint32 rsvd3 : 9;
4516 Uint32 power_monitor_ant0_q0fsdly : 3;
4517 Uint32 rsvd2 : 1;
4518 Uint32 power_monitor_ant0_i0fsdly : 3;
4519 Uint32 rsvd1 : 9;
4520 Uint32 power_monitor_ant0_q0bus_sel : 3;
4521 Uint32 rsvd0 : 1;
4522 Uint32 power_monitor_ant0_i0bus_sel : 3;
4523 #else
4524 Uint32 power_monitor_ant0_i0bus_sel : 3;
4525 Uint32 rsvd0 : 1;
4526 Uint32 power_monitor_ant0_q0bus_sel : 3;
4527 Uint32 rsvd1 : 9;
4528 Uint32 power_monitor_ant0_i0fsdly : 3;
4529 Uint32 rsvd2 : 1;
4530 Uint32 power_monitor_ant0_q0fsdly : 3;
4531 Uint32 rsvd3 : 9;
4532 #endif
4533 } CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG;
4535 /* see definition of corresponding register for node0. */
4536 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_I0BUS_SEL_MASK (0x00000007u)
4537 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_I0BUS_SEL_SHIFT (0x00000000u)
4538 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_I0BUS_SEL_RESETVAL (0x00000000u)
4540 /* see definition of corresponding register for node0. */
4541 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_Q0BUS_SEL_MASK (0x00000070u)
4542 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_Q0BUS_SEL_SHIFT (0x00000004u)
4543 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_Q0BUS_SEL_RESETVAL (0x00000000u)
4545 /* see definition of corresponding register for node0. */
4546 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_I0FSDLY_MASK (0x00070000u)
4547 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_I0FSDLY_SHIFT (0x00000010u)
4548 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_I0FSDLY_RESETVAL (0x00000000u)
4550 /* see definition of corresponding register for node0. */
4551 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_Q0FSDLY_MASK (0x00700000u)
4552 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_Q0FSDLY_SHIFT (0x00000014u)
4553 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_POWER_MONITOR_ANT0_Q0FSDLY_RESETVAL (0x00000000u)
4555 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_ADDR (0x0000040Cu)
4556 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT0_REG_RESETVAL (0x00000000u)
4558 /* POWER_MONITOR_ANT0_FSF_FSFM */
4559 typedef struct
4560 {
4561 #ifdef _BIG_ENDIAN
4562 Uint32 rsvd0 : 28;
4563 Uint32 power_monitor_ant0_fsfm : 2;
4564 Uint32 power_monitor_ant0_fsf : 2;
4565 #else
4566 Uint32 power_monitor_ant0_fsf : 2;
4567 Uint32 power_monitor_ant0_fsfm : 2;
4568 Uint32 rsvd0 : 28;
4569 #endif
4570 } CSL_DFE_CB_POWER_MONITOR_ANT0_FSF_FSFM_REG;
4572 /* see definition of corresponding register for node0. */
4573 #define CSL_DFE_CB_POWER_MONITOR_ANT0_FSF_FSFM_REG_POWER_MONITOR_ANT0_FSF_MASK (0x00000003u)
4574 #define CSL_DFE_CB_POWER_MONITOR_ANT0_FSF_FSFM_REG_POWER_MONITOR_ANT0_FSF_SHIFT (0x00000000u)
4575 #define CSL_DFE_CB_POWER_MONITOR_ANT0_FSF_FSFM_REG_POWER_MONITOR_ANT0_FSF_RESETVAL (0x00000000u)
4577 /* see definition of corresponding register for node0. */
4578 #define CSL_DFE_CB_POWER_MONITOR_ANT0_FSF_FSFM_REG_POWER_MONITOR_ANT0_FSFM_MASK (0x0000000Cu)
4579 #define CSL_DFE_CB_POWER_MONITOR_ANT0_FSF_FSFM_REG_POWER_MONITOR_ANT0_FSFM_SHIFT (0x00000002u)
4580 #define CSL_DFE_CB_POWER_MONITOR_ANT0_FSF_FSFM_REG_POWER_MONITOR_ANT0_FSFM_RESETVAL (0x00000000u)
4582 #define CSL_DFE_CB_POWER_MONITOR_ANT0_FSF_FSFM_REG_ADDR (0x00000410u)
4583 #define CSL_DFE_CB_POWER_MONITOR_ANT0_FSF_FSFM_REG_RESETVAL (0x00000000u)
4585 /* POWER_MONITOR_CONFIG_ANT1 */
4586 typedef struct
4587 {
4588 #ifdef _BIG_ENDIAN
4589 Uint32 rsvd3 : 9;
4590 Uint32 power_monitor_ant1_q0fsdly : 3;
4591 Uint32 rsvd2 : 1;
4592 Uint32 power_monitor_ant1_i0fsdly : 3;
4593 Uint32 rsvd1 : 9;
4594 Uint32 power_monitor_ant1_q0bus_sel : 3;
4595 Uint32 rsvd0 : 1;
4596 Uint32 power_monitor_ant1_i0bus_sel : 3;
4597 #else
4598 Uint32 power_monitor_ant1_i0bus_sel : 3;
4599 Uint32 rsvd0 : 1;
4600 Uint32 power_monitor_ant1_q0bus_sel : 3;
4601 Uint32 rsvd1 : 9;
4602 Uint32 power_monitor_ant1_i0fsdly : 3;
4603 Uint32 rsvd2 : 1;
4604 Uint32 power_monitor_ant1_q0fsdly : 3;
4605 Uint32 rsvd3 : 9;
4606 #endif
4607 } CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG;
4609 /* see definition of corresponding register for node0. */
4610 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_I0BUS_SEL_MASK (0x00000007u)
4611 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_I0BUS_SEL_SHIFT (0x00000000u)
4612 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_I0BUS_SEL_RESETVAL (0x00000000u)
4614 /* see definition of corresponding register for node0. */
4615 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_Q0BUS_SEL_MASK (0x00000070u)
4616 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_Q0BUS_SEL_SHIFT (0x00000004u)
4617 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_Q0BUS_SEL_RESETVAL (0x00000000u)
4619 /* see definition of corresponding register for node0. */
4620 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_I0FSDLY_MASK (0x00070000u)
4621 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_I0FSDLY_SHIFT (0x00000010u)
4622 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_I0FSDLY_RESETVAL (0x00000000u)
4624 /* see definition of corresponding register for node0. */
4625 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_Q0FSDLY_MASK (0x00700000u)
4626 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_Q0FSDLY_SHIFT (0x00000014u)
4627 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_POWER_MONITOR_ANT1_Q0FSDLY_RESETVAL (0x00000000u)
4629 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_ADDR (0x00000414u)
4630 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT1_REG_RESETVAL (0x00000000u)
4632 /* POWER_MONITOR_ANT1_FSF_FSFM */
4633 typedef struct
4634 {
4635 #ifdef _BIG_ENDIAN
4636 Uint32 rsvd0 : 28;
4637 Uint32 power_monitor_ant1_fsfm : 2;
4638 Uint32 power_monitor_ant1_fsf : 2;
4639 #else
4640 Uint32 power_monitor_ant1_fsf : 2;
4641 Uint32 power_monitor_ant1_fsfm : 2;
4642 Uint32 rsvd0 : 28;
4643 #endif
4644 } CSL_DFE_CB_POWER_MONITOR_ANT1_FSF_FSFM_REG;
4646 /* see definition of corresponding register for node0. */
4647 #define CSL_DFE_CB_POWER_MONITOR_ANT1_FSF_FSFM_REG_POWER_MONITOR_ANT1_FSF_MASK (0x00000003u)
4648 #define CSL_DFE_CB_POWER_MONITOR_ANT1_FSF_FSFM_REG_POWER_MONITOR_ANT1_FSF_SHIFT (0x00000000u)
4649 #define CSL_DFE_CB_POWER_MONITOR_ANT1_FSF_FSFM_REG_POWER_MONITOR_ANT1_FSF_RESETVAL (0x00000000u)
4651 /* see definition of corresponding register for node0. */
4652 #define CSL_DFE_CB_POWER_MONITOR_ANT1_FSF_FSFM_REG_POWER_MONITOR_ANT1_FSFM_MASK (0x0000000Cu)
4653 #define CSL_DFE_CB_POWER_MONITOR_ANT1_FSF_FSFM_REG_POWER_MONITOR_ANT1_FSFM_SHIFT (0x00000002u)
4654 #define CSL_DFE_CB_POWER_MONITOR_ANT1_FSF_FSFM_REG_POWER_MONITOR_ANT1_FSFM_RESETVAL (0x00000000u)
4656 #define CSL_DFE_CB_POWER_MONITOR_ANT1_FSF_FSFM_REG_ADDR (0x00000418u)
4657 #define CSL_DFE_CB_POWER_MONITOR_ANT1_FSF_FSFM_REG_RESETVAL (0x00000000u)
4659 /* POWER_MONITOR_CONFIG_ANT2 */
4660 typedef struct
4661 {
4662 #ifdef _BIG_ENDIAN
4663 Uint32 rsvd3 : 9;
4664 Uint32 power_monitor_ant2_q0fsdly : 3;
4665 Uint32 rsvd2 : 1;
4666 Uint32 power_monitor_ant2_i0fsdly : 3;
4667 Uint32 rsvd1 : 9;
4668 Uint32 power_monitor_ant2_q0bus_sel : 3;
4669 Uint32 rsvd0 : 1;
4670 Uint32 power_monitor_ant2_i0bus_sel : 3;
4671 #else
4672 Uint32 power_monitor_ant2_i0bus_sel : 3;
4673 Uint32 rsvd0 : 1;
4674 Uint32 power_monitor_ant2_q0bus_sel : 3;
4675 Uint32 rsvd1 : 9;
4676 Uint32 power_monitor_ant2_i0fsdly : 3;
4677 Uint32 rsvd2 : 1;
4678 Uint32 power_monitor_ant2_q0fsdly : 3;
4679 Uint32 rsvd3 : 9;
4680 #endif
4681 } CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG;
4683 /* see definition of corresponding register for node0. */
4684 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_I0BUS_SEL_MASK (0x00000007u)
4685 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_I0BUS_SEL_SHIFT (0x00000000u)
4686 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_I0BUS_SEL_RESETVAL (0x00000000u)
4688 /* see definition of corresponding register for node0. */
4689 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_Q0BUS_SEL_MASK (0x00000070u)
4690 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_Q0BUS_SEL_SHIFT (0x00000004u)
4691 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_Q0BUS_SEL_RESETVAL (0x00000000u)
4693 /* see definition of corresponding register for node0. */
4694 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_I0FSDLY_MASK (0x00070000u)
4695 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_I0FSDLY_SHIFT (0x00000010u)
4696 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_I0FSDLY_RESETVAL (0x00000000u)
4698 /* see definition of corresponding register for node0. */
4699 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_Q0FSDLY_MASK (0x00700000u)
4700 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_Q0FSDLY_SHIFT (0x00000014u)
4701 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_POWER_MONITOR_ANT2_Q0FSDLY_RESETVAL (0x00000000u)
4703 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_ADDR (0x0000041Cu)
4704 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT2_REG_RESETVAL (0x00000000u)
4706 /* POWER_MONITOR_ANT2_FSF_FSFM */
4707 typedef struct
4708 {
4709 #ifdef _BIG_ENDIAN
4710 Uint32 rsvd0 : 28;
4711 Uint32 power_monitor_ant2_fsfm : 2;
4712 Uint32 power_monitor_ant2_fsf : 2;
4713 #else
4714 Uint32 power_monitor_ant2_fsf : 2;
4715 Uint32 power_monitor_ant2_fsfm : 2;
4716 Uint32 rsvd0 : 28;
4717 #endif
4718 } CSL_DFE_CB_POWER_MONITOR_ANT2_FSF_FSFM_REG;
4720 /* see definition of corresponding register for node0. */
4721 #define CSL_DFE_CB_POWER_MONITOR_ANT2_FSF_FSFM_REG_POWER_MONITOR_ANT2_FSF_MASK (0x00000003u)
4722 #define CSL_DFE_CB_POWER_MONITOR_ANT2_FSF_FSFM_REG_POWER_MONITOR_ANT2_FSF_SHIFT (0x00000000u)
4723 #define CSL_DFE_CB_POWER_MONITOR_ANT2_FSF_FSFM_REG_POWER_MONITOR_ANT2_FSF_RESETVAL (0x00000000u)
4725 /* see definition of corresponding register for node0. */
4726 #define CSL_DFE_CB_POWER_MONITOR_ANT2_FSF_FSFM_REG_POWER_MONITOR_ANT2_FSFM_MASK (0x0000000Cu)
4727 #define CSL_DFE_CB_POWER_MONITOR_ANT2_FSF_FSFM_REG_POWER_MONITOR_ANT2_FSFM_SHIFT (0x00000002u)
4728 #define CSL_DFE_CB_POWER_MONITOR_ANT2_FSF_FSFM_REG_POWER_MONITOR_ANT2_FSFM_RESETVAL (0x00000000u)
4730 #define CSL_DFE_CB_POWER_MONITOR_ANT2_FSF_FSFM_REG_ADDR (0x00000420u)
4731 #define CSL_DFE_CB_POWER_MONITOR_ANT2_FSF_FSFM_REG_RESETVAL (0x00000000u)
4733 /* POWER_MONITOR_CONFIG_ANT3 */
4734 typedef struct
4735 {
4736 #ifdef _BIG_ENDIAN
4737 Uint32 rsvd3 : 9;
4738 Uint32 power_monitor_ant3_q0fsdly : 3;
4739 Uint32 rsvd2 : 1;
4740 Uint32 power_monitor_ant3_i0fsdly : 3;
4741 Uint32 rsvd1 : 9;
4742 Uint32 power_monitor_ant3_q0bus_sel : 3;
4743 Uint32 rsvd0 : 1;
4744 Uint32 power_monitor_ant3_i0bus_sel : 3;
4745 #else
4746 Uint32 power_monitor_ant3_i0bus_sel : 3;
4747 Uint32 rsvd0 : 1;
4748 Uint32 power_monitor_ant3_q0bus_sel : 3;
4749 Uint32 rsvd1 : 9;
4750 Uint32 power_monitor_ant3_i0fsdly : 3;
4751 Uint32 rsvd2 : 1;
4752 Uint32 power_monitor_ant3_q0fsdly : 3;
4753 Uint32 rsvd3 : 9;
4754 #endif
4755 } CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG;
4757 /* see definition of corresponding register for node0. */
4758 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_I0BUS_SEL_MASK (0x00000007u)
4759 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_I0BUS_SEL_SHIFT (0x00000000u)
4760 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_I0BUS_SEL_RESETVAL (0x00000000u)
4762 /* see definition of corresponding register for node0. */
4763 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_Q0BUS_SEL_MASK (0x00000070u)
4764 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_Q0BUS_SEL_SHIFT (0x00000004u)
4765 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_Q0BUS_SEL_RESETVAL (0x00000000u)
4767 /* see definition of corresponding register for node0. */
4768 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_I0FSDLY_MASK (0x00070000u)
4769 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_I0FSDLY_SHIFT (0x00000010u)
4770 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_I0FSDLY_RESETVAL (0x00000000u)
4772 /* see definition of corresponding register for node0. */
4773 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_Q0FSDLY_MASK (0x00700000u)
4774 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_Q0FSDLY_SHIFT (0x00000014u)
4775 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_POWER_MONITOR_ANT3_Q0FSDLY_RESETVAL (0x00000000u)
4777 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_ADDR (0x00000424u)
4778 #define CSL_DFE_CB_POWER_MONITOR_CONFIG_ANT3_REG_RESETVAL (0x00000000u)
4780 /* POWER_MONITOR_ANT3_FSF_FSFM */
4781 typedef struct
4782 {
4783 #ifdef _BIG_ENDIAN
4784 Uint32 rsvd0 : 28;
4785 Uint32 power_monitor_ant3_fsfm : 2;
4786 Uint32 power_monitor_ant3_fsf : 2;
4787 #else
4788 Uint32 power_monitor_ant3_fsf : 2;
4789 Uint32 power_monitor_ant3_fsfm : 2;
4790 Uint32 rsvd0 : 28;
4791 #endif
4792 } CSL_DFE_CB_POWER_MONITOR_ANT3_FSF_FSFM_REG;
4794 /* see definition of corresponding register for node0. */
4795 #define CSL_DFE_CB_POWER_MONITOR_ANT3_FSF_FSFM_REG_POWER_MONITOR_ANT3_FSF_MASK (0x00000003u)
4796 #define CSL_DFE_CB_POWER_MONITOR_ANT3_FSF_FSFM_REG_POWER_MONITOR_ANT3_FSF_SHIFT (0x00000000u)
4797 #define CSL_DFE_CB_POWER_MONITOR_ANT3_FSF_FSFM_REG_POWER_MONITOR_ANT3_FSF_RESETVAL (0x00000000u)
4799 /* see definition of corresponding register for node0. */
4800 #define CSL_DFE_CB_POWER_MONITOR_ANT3_FSF_FSFM_REG_POWER_MONITOR_ANT3_FSFM_MASK (0x0000000Cu)
4801 #define CSL_DFE_CB_POWER_MONITOR_ANT3_FSF_FSFM_REG_POWER_MONITOR_ANT3_FSFM_SHIFT (0x00000002u)
4802 #define CSL_DFE_CB_POWER_MONITOR_ANT3_FSF_FSFM_REG_POWER_MONITOR_ANT3_FSFM_RESETVAL (0x00000000u)
4804 #define CSL_DFE_CB_POWER_MONITOR_ANT3_FSF_FSFM_REG_ADDR (0x00000428u)
4805 #define CSL_DFE_CB_POWER_MONITOR_ANT3_FSF_FSFM_REG_RESETVAL (0x00000000u)
4807 /* POWER_MONITOR_NODE_SEL */
4808 typedef struct
4809 {
4810 #ifdef _BIG_ENDIAN
4811 Uint32 rsvd0 : 28;
4812 Uint32 power_monitor_sel : 4;
4813 #else
4814 Uint32 power_monitor_sel : 4;
4815 Uint32 rsvd0 : 28;
4816 #endif
4817 } CSL_DFE_CB_POWER_MONITOR_NODE_SEL_REG;
4819 /* node selection for power monitor, refer to 'cba_sel' for definition of capture nodes. */
4820 #define CSL_DFE_CB_POWER_MONITOR_NODE_SEL_REG_POWER_MONITOR_SEL_MASK (0x0000000Fu)
4821 #define CSL_DFE_CB_POWER_MONITOR_NODE_SEL_REG_POWER_MONITOR_SEL_SHIFT (0x00000000u)
4822 #define CSL_DFE_CB_POWER_MONITOR_NODE_SEL_REG_POWER_MONITOR_SEL_RESETVAL (0x00000000u)
4824 #define CSL_DFE_CB_POWER_MONITOR_NODE_SEL_REG_ADDR (0x0000042Cu)
4825 #define CSL_DFE_CB_POWER_MONITOR_NODE_SEL_REG_RESETVAL (0x00000000u)
4827 /* CB_SOURCING_CONTROL */
4828 typedef struct
4829 {
4830 #ifdef _BIG_ENDIAN
4831 Uint32 rsvd2 : 7;
4832 Uint32 cb_sc_repeat : 1;
4833 Uint32 rsvd1 : 1;
4834 Uint32 cb_sc_size : 15;
4835 Uint32 rsvd0 : 2;
4836 Uint32 cb_sc_fsl : 6;
4837 #else
4838 Uint32 cb_sc_fsl : 6;
4839 Uint32 rsvd0 : 2;
4840 Uint32 cb_sc_size : 15;
4841 Uint32 rsvd1 : 1;
4842 Uint32 cb_sc_repeat : 1;
4843 Uint32 rsvd2 : 7;
4844 #endif
4845 } CSL_DFE_CB_CB_SOURCING_CONTROL_REG;
4847 /* source mode frame length; values are 0 to 63 clock cycles ,i.e. frame length minus 1 */
4848 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_CB_SC_FSL_MASK (0x0000003Fu)
4849 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_CB_SC_FSL_SHIFT (0x00000000u)
4850 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_CB_SC_FSL_RESETVAL (0x00000000u)
4852 /* number of data to be sourced minus 1; Max 32768 complex samples (in I/Q interleaved mode, max is 16384 complex samples) . Note that since each capture buffer is of size 8k, we need to concatenate capture buffer A and B if the soucing size is between 8k~16k. We need to concatenate capture buffer A, B, C if the sourcing size is between 16k and 24k and we need to concatenate all four capture buffers if sourcing size is between 24k~32k. The user need to program the corresponding buffers to 'sourcing mode'. */
4853 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_CB_SC_SIZE_MASK (0x007FFF00u)
4854 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_CB_SC_SIZE_SHIFT (0x00000008u)
4855 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_CB_SC_SIZE_RESETVAL (0x00000000u)
4857 /* repeat source data: 1: repeat; 0: source data once */
4858 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_CB_SC_REPEAT_MASK (0x01000000u)
4859 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_CB_SC_REPEAT_SHIFT (0x00000018u)
4860 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_CB_SC_REPEAT_RESETVAL (0x00000000u)
4862 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_ADDR (0x00000430u)
4863 #define CSL_DFE_CB_CB_SOURCING_CONTROL_REG_RESETVAL (0x00000000u)
4865 /* CB_TIME_STEP */
4866 typedef struct
4867 {
4868 #ifdef _BIG_ENDIAN
4869 Uint32 time_step : 32;
4870 #else
4871 Uint32 time_step : 32;
4872 #endif
4873 } CSL_DFE_CB_CB_TIME_STEP_REG;
4875 /* Farrow-style time accumulation word. Gates off a clock when it overflows. This removes one clock out of every (2^31)/time_step clocks. Put another way: multiplies the clock rate by ((2^31)-time_step)/(2^31). */
4876 #define CSL_DFE_CB_CB_TIME_STEP_REG_TIME_STEP_MASK (0xFFFFFFFFu)
4877 #define CSL_DFE_CB_CB_TIME_STEP_REG_TIME_STEP_SHIFT (0x00000000u)
4878 #define CSL_DFE_CB_CB_TIME_STEP_REG_TIME_STEP_RESETVAL (0x00000000u)
4880 #define CSL_DFE_CB_CB_TIME_STEP_REG_ADDR (0x00000434u)
4881 #define CSL_DFE_CB_CB_TIME_STEP_REG_RESETVAL (0x00000000u)
4883 /* CB_RESET_INT */
4884 typedef struct
4885 {
4886 #ifdef _BIG_ENDIAN
4887 Uint32 reset_int : 32;
4888 #else
4889 Uint32 reset_int : 32;
4890 #endif
4891 } CSL_DFE_CB_CB_RESET_INT_REG;
4893 /* Farrow-style reset interval. Resets the time accumulator every reset_int plus 1 clocks (resetting also counts as an overflow, so it gates a clock). If 0, then reset is disabled. If the output clock is N/D the rate of the ungated clock, then this should be set to D-1. */
4894 #define CSL_DFE_CB_CB_RESET_INT_REG_RESET_INT_MASK (0xFFFFFFFFu)
4895 #define CSL_DFE_CB_CB_RESET_INT_REG_RESET_INT_SHIFT (0x00000000u)
4896 #define CSL_DFE_CB_CB_RESET_INT_REG_RESET_INT_RESETVAL (0x00000000u)
4898 #define CSL_DFE_CB_CB_RESET_INT_REG_ADDR (0x00000438u)
4899 #define CSL_DFE_CB_CB_RESET_INT_REG_RESETVAL (0x00000000u)
4901 /* CB_TDD_PERIOD */
4902 typedef struct
4903 {
4904 #ifdef _BIG_ENDIAN
4905 Uint32 rsvd0 : 8;
4906 Uint32 tdd_period : 24;
4907 #else
4908 Uint32 tdd_period : 24;
4909 Uint32 rsvd0 : 8;
4910 #endif
4911 } CSL_DFE_CB_CB_TDD_PERIOD_REG;
4913 /* TDD count period. Counts from 0 to programmed value and repeats. */
4914 #define CSL_DFE_CB_CB_TDD_PERIOD_REG_TDD_PERIOD_MASK (0x00FFFFFFu)
4915 #define CSL_DFE_CB_CB_TDD_PERIOD_REG_TDD_PERIOD_SHIFT (0x00000000u)
4916 #define CSL_DFE_CB_CB_TDD_PERIOD_REG_TDD_PERIOD_RESETVAL (0x00000000u)
4918 #define CSL_DFE_CB_CB_TDD_PERIOD_REG_ADDR (0x0000043Cu)
4919 #define CSL_DFE_CB_CB_TDD_PERIOD_REG_RESETVAL (0x00000000u)
4921 /* CB_TDD_ON_0 */
4922 typedef struct
4923 {
4924 #ifdef _BIG_ENDIAN
4925 Uint32 rsvd0 : 8;
4926 Uint32 tdd_on_0 : 24;
4927 #else
4928 Uint32 tdd_on_0 : 24;
4929 Uint32 rsvd0 : 8;
4930 #endif
4931 } CSL_DFE_CB_CB_TDD_ON_0_REG;
4933 /* TDD on time. Turns on clocks when counter hits this value. Remains on until it his an off time. */
4934 #define CSL_DFE_CB_CB_TDD_ON_0_REG_TDD_ON_0_MASK (0x00FFFFFFu)
4935 #define CSL_DFE_CB_CB_TDD_ON_0_REG_TDD_ON_0_SHIFT (0x00000000u)
4936 #define CSL_DFE_CB_CB_TDD_ON_0_REG_TDD_ON_0_RESETVAL (0x00000000u)
4938 #define CSL_DFE_CB_CB_TDD_ON_0_REG_ADDR (0x00000440u)
4939 #define CSL_DFE_CB_CB_TDD_ON_0_REG_RESETVAL (0x00000000u)
4941 /* CB_TDD_OFF_0 */
4942 typedef struct
4943 {
4944 #ifdef _BIG_ENDIAN
4945 Uint32 rsvd0 : 8;
4946 Uint32 tdd_off_0 : 24;
4947 #else
4948 Uint32 tdd_off_0 : 24;
4949 Uint32 rsvd0 : 8;
4950 #endif
4951 } CSL_DFE_CB_CB_TDD_OFF_0_REG;
4953 /* TDD off time. Turns off clocks when counter hits this value. Remains off until it his an on time. */
4954 #define CSL_DFE_CB_CB_TDD_OFF_0_REG_TDD_OFF_0_MASK (0x00FFFFFFu)
4955 #define CSL_DFE_CB_CB_TDD_OFF_0_REG_TDD_OFF_0_SHIFT (0x00000000u)
4956 #define CSL_DFE_CB_CB_TDD_OFF_0_REG_TDD_OFF_0_RESETVAL (0x00000000u)
4958 #define CSL_DFE_CB_CB_TDD_OFF_0_REG_ADDR (0x00000444u)
4959 #define CSL_DFE_CB_CB_TDD_OFF_0_REG_RESETVAL (0x00000000u)
4961 /* CB_TDD_ON_1 */
4962 typedef struct
4963 {
4964 #ifdef _BIG_ENDIAN
4965 Uint32 rsvd0 : 8;
4966 Uint32 tdd_on_1 : 24;
4967 #else
4968 Uint32 tdd_on_1 : 24;
4969 Uint32 rsvd0 : 8;
4970 #endif
4971 } CSL_DFE_CB_CB_TDD_ON_1_REG;
4973 /* TDD on time. Turns on clocks when counter hits this value. Remains on until it his an off time. */
4974 #define CSL_DFE_CB_CB_TDD_ON_1_REG_TDD_ON_1_MASK (0x00FFFFFFu)
4975 #define CSL_DFE_CB_CB_TDD_ON_1_REG_TDD_ON_1_SHIFT (0x00000000u)
4976 #define CSL_DFE_CB_CB_TDD_ON_1_REG_TDD_ON_1_RESETVAL (0x00000000u)
4978 #define CSL_DFE_CB_CB_TDD_ON_1_REG_ADDR (0x00000448u)
4979 #define CSL_DFE_CB_CB_TDD_ON_1_REG_RESETVAL (0x00000000u)
4981 /* CB_TDD_OFF_1 */
4982 typedef struct
4983 {
4984 #ifdef _BIG_ENDIAN
4985 Uint32 rsvd0 : 8;
4986 Uint32 tdd_off_1 : 24;
4987 #else
4988 Uint32 tdd_off_1 : 24;
4989 Uint32 rsvd0 : 8;
4990 #endif
4991 } CSL_DFE_CB_CB_TDD_OFF_1_REG;
4993 /* TDD off time. Turns off clocks when counter hits this value. Remains off until it his an on time. */
4994 #define CSL_DFE_CB_CB_TDD_OFF_1_REG_TDD_OFF_1_MASK (0x00FFFFFFu)
4995 #define CSL_DFE_CB_CB_TDD_OFF_1_REG_TDD_OFF_1_SHIFT (0x00000000u)
4996 #define CSL_DFE_CB_CB_TDD_OFF_1_REG_TDD_OFF_1_RESETVAL (0x00000000u)
4998 #define CSL_DFE_CB_CB_TDD_OFF_1_REG_ADDR (0x0000044Cu)
4999 #define CSL_DFE_CB_CB_TDD_OFF_1_REG_RESETVAL (0x00000000u)
5001 /* INITS */
5002 typedef struct
5003 {
5004 #ifdef _BIG_ENDIAN
5005 Uint32 rsvd0 : 25;
5006 Uint32 clear_data : 1;
5007 Uint32 init_state : 1;
5008 Uint32 init_clk_gate : 1;
5009 Uint32 inits_ssel : 4;
5010 #else
5011 Uint32 inits_ssel : 4;
5012 Uint32 init_clk_gate : 1;
5013 Uint32 init_state : 1;
5014 Uint32 clear_data : 1;
5015 Uint32 rsvd0 : 25;
5016 #endif
5017 } CSL_DFE_CB_INITS_REG;
5019 /* sync select for 'init_state' */
5020 #define CSL_DFE_CB_INITS_REG_INITS_SSEL_MASK (0x0000000Fu)
5021 #define CSL_DFE_CB_INITS_REG_INITS_SSEL_SHIFT (0x00000000u)
5022 #define CSL_DFE_CB_INITS_REG_INITS_SSEL_RESETVAL (0x00000000u)
5024 /* for init_clk_gate */
5025 #define CSL_DFE_CB_INITS_REG_INIT_CLK_GATE_MASK (0x00000010u)
5026 #define CSL_DFE_CB_INITS_REG_INIT_CLK_GATE_SHIFT (0x00000004u)
5027 #define CSL_DFE_CB_INITS_REG_INIT_CLK_GATE_RESETVAL (0x00000001u)
5029 /* for init_state */
5030 #define CSL_DFE_CB_INITS_REG_INIT_STATE_MASK (0x00000020u)
5031 #define CSL_DFE_CB_INITS_REG_INIT_STATE_SHIFT (0x00000005u)
5032 #define CSL_DFE_CB_INITS_REG_INIT_STATE_RESETVAL (0x00000001u)
5034 /* for clear_data */
5035 #define CSL_DFE_CB_INITS_REG_CLEAR_DATA_MASK (0x00000040u)
5036 #define CSL_DFE_CB_INITS_REG_CLEAR_DATA_SHIFT (0x00000006u)
5037 #define CSL_DFE_CB_INITS_REG_CLEAR_DATA_RESETVAL (0x00000001u)
5039 #define CSL_DFE_CB_INITS_REG_ADDR (0x00000450u)
5040 #define CSL_DFE_CB_INITS_REG_RESETVAL (0x00000070u)
5042 /* CB_SYNC_SELECT_PART1 */
5043 typedef struct
5044 {
5045 #ifdef _BIG_ENDIAN
5046 Uint32 rsvd0 : 16;
5047 Uint32 cb_f_powermonitor_ssel : 4;
5048 Uint32 cb_source_ssel : 4;
5049 Uint32 cb_f_start_ssel : 4;
5050 Uint32 cb_c_start_ssel : 4;
5051 #else
5052 Uint32 cb_c_start_ssel : 4;
5053 Uint32 cb_f_start_ssel : 4;
5054 Uint32 cb_source_ssel : 4;
5055 Uint32 cb_f_powermonitor_ssel : 4;
5056 Uint32 rsvd0 : 16;
5057 #endif
5058 } CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG;
5060 /* coarse capture buffer start sync select */
5061 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_C_START_SSEL_MASK (0x0000000Fu)
5062 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_C_START_SSEL_SHIFT (0x00000000u)
5063 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_C_START_SSEL_RESETVAL (0x00000000u)
5065 /* fine capture buffer start sync select */
5066 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_F_START_SSEL_MASK (0x000000F0u)
5067 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_F_START_SSEL_SHIFT (0x00000004u)
5068 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_F_START_SSEL_RESETVAL (0x00000000u)
5070 /* capture buffer source mode sync select */
5071 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_SOURCE_SSEL_MASK (0x00000F00u)
5072 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_SOURCE_SSEL_SHIFT (0x00000008u)
5073 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_SOURCE_SSEL_RESETVAL (0x00000000u)
5075 /* sync select for CB-F power monitor in order to get MaxRefPwr */
5076 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_F_POWERMONITOR_SSEL_MASK (0x0000F000u)
5077 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_F_POWERMONITOR_SSEL_SHIFT (0x0000000Cu)
5078 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_CB_F_POWERMONITOR_SSEL_RESETVAL (0x00000000u)
5080 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_ADDR (0x00000454u)
5081 #define CSL_DFE_CB_CB_SYNC_SELECT_PART1_REG_RESETVAL (0x00000000u)
5083 /* CB_SYNC_SELECT_PART2 */
5084 typedef struct
5085 {
5086 #ifdef _BIG_ENDIAN
5087 Uint32 rsvd0 : 16;
5088 Uint32 cbd_frac_cnt_ssel : 4;
5089 Uint32 cbc_frac_cnt_ssel : 4;
5090 Uint32 cbb_frac_cnt_ssel : 4;
5091 Uint32 cba_frac_cnt_ssel : 4;
5092 #else
5093 Uint32 cba_frac_cnt_ssel : 4;
5094 Uint32 cbb_frac_cnt_ssel : 4;
5095 Uint32 cbc_frac_cnt_ssel : 4;
5096 Uint32 cbd_frac_cnt_ssel : 4;
5097 Uint32 rsvd0 : 16;
5098 #endif
5099 } CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG;
5101 /* cba fractional counter sync select */
5102 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBA_FRAC_CNT_SSEL_MASK (0x0000000Fu)
5103 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBA_FRAC_CNT_SSEL_SHIFT (0x00000000u)
5104 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBA_FRAC_CNT_SSEL_RESETVAL (0x00000000u)
5106 /* cbb fractional counter sync select */
5107 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBB_FRAC_CNT_SSEL_MASK (0x000000F0u)
5108 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBB_FRAC_CNT_SSEL_SHIFT (0x00000004u)
5109 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBB_FRAC_CNT_SSEL_RESETVAL (0x00000000u)
5111 /* cbc fractional counter sync select */
5112 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBC_FRAC_CNT_SSEL_MASK (0x00000F00u)
5113 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBC_FRAC_CNT_SSEL_SHIFT (0x00000008u)
5114 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBC_FRAC_CNT_SSEL_RESETVAL (0x00000000u)
5116 /* cbd fractional counter sync select */
5117 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBD_FRAC_CNT_SSEL_MASK (0x0000F000u)
5118 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBD_FRAC_CNT_SSEL_SHIFT (0x0000000Cu)
5119 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_CBD_FRAC_CNT_SSEL_RESETVAL (0x00000000u)
5121 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_ADDR (0x00000458u)
5122 #define CSL_DFE_CB_CB_SYNC_SELECT_PART2_REG_RESETVAL (0x00000000u)
5124 /* CB_SYNC_SELECT_PART3 */
5125 typedef struct
5126 {
5127 #ifdef _BIG_ENDIAN
5128 Uint32 rsvd0 : 16;
5129 Uint32 cbd_len_cnt_ssel : 4;
5130 Uint32 cbc_len_cnt_ssel : 4;
5131 Uint32 cbb_len_cnt_ssel : 4;
5132 Uint32 cba_len_cnt_ssel : 4;
5133 #else
5134 Uint32 cba_len_cnt_ssel : 4;
5135 Uint32 cbb_len_cnt_ssel : 4;
5136 Uint32 cbc_len_cnt_ssel : 4;
5137 Uint32 cbd_len_cnt_ssel : 4;
5138 Uint32 rsvd0 : 16;
5139 #endif
5140 } CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG;
5142 /* cba length counter sync select */
5143 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBA_LEN_CNT_SSEL_MASK (0x0000000Fu)
5144 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBA_LEN_CNT_SSEL_SHIFT (0x00000000u)
5145 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBA_LEN_CNT_SSEL_RESETVAL (0x00000000u)
5147 /* cbb length counter sync select */
5148 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBB_LEN_CNT_SSEL_MASK (0x000000F0u)
5149 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBB_LEN_CNT_SSEL_SHIFT (0x00000004u)
5150 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBB_LEN_CNT_SSEL_RESETVAL (0x00000000u)
5152 /* cbc length counter sync select */
5153 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBC_LEN_CNT_SSEL_MASK (0x00000F00u)
5154 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBC_LEN_CNT_SSEL_SHIFT (0x00000008u)
5155 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBC_LEN_CNT_SSEL_RESETVAL (0x00000000u)
5157 /* cbd length counter sync select */
5158 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBD_LEN_CNT_SSEL_MASK (0x0000F000u)
5159 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBD_LEN_CNT_SSEL_SHIFT (0x0000000Cu)
5160 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_CBD_LEN_CNT_SSEL_RESETVAL (0x00000000u)
5162 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_ADDR (0x0000045Cu)
5163 #define CSL_DFE_CB_CB_SYNC_SELECT_PART3_REG_RESETVAL (0x00000000u)
5165 /* CB_SRC_NODE_CONTROL */
5166 typedef struct
5167 {
5168 #ifdef _BIG_ENDIAN
5169 Uint32 rsvd0 : 22;
5170 Uint32 cb_src_dduc_to_bb : 1;
5171 Uint32 cb_src_fb_to_dduc : 1;
5172 Uint32 cb_src_rx_to_dduc : 1;
5173 Uint32 cb_src_jesd_to_fb : 1;
5174 Uint32 cb_src_jesd_to_rx : 1;
5175 Uint32 cb_src_tx_to_jesd : 1;
5176 Uint32 cb_src_dpd_to_tx : 1;
5177 Uint32 cb_src_cdfr_to_dpd : 1;
5178 Uint32 cb_src_sum_to_cfr : 1;
5179 Uint32 cb_src_bb_to_dduc : 1;
5180 #else
5181 Uint32 cb_src_bb_to_dduc : 1;
5182 Uint32 cb_src_sum_to_cfr : 1;
5183 Uint32 cb_src_cdfr_to_dpd : 1;
5184 Uint32 cb_src_dpd_to_tx : 1;
5185 Uint32 cb_src_tx_to_jesd : 1;
5186 Uint32 cb_src_jesd_to_rx : 1;
5187 Uint32 cb_src_jesd_to_fb : 1;
5188 Uint32 cb_src_rx_to_dduc : 1;
5189 Uint32 cb_src_fb_to_dduc : 1;
5190 Uint32 cb_src_dduc_to_bb : 1;
5191 Uint32 rsvd0 : 22;
5192 #endif
5193 } CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG;
5195 /* determine whether we want to source into a spcific node: */
5196 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_BB_TO_DDUC_MASK (0x00000001u)
5197 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_BB_TO_DDUC_SHIFT (0x00000000u)
5198 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_BB_TO_DDUC_RESETVAL (0x00000000u)
5200 /* same as above */
5201 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_SUM_TO_CFR_MASK (0x00000002u)
5202 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_SUM_TO_CFR_SHIFT (0x00000001u)
5203 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_SUM_TO_CFR_RESETVAL (0x00000000u)
5205 /* same as above */
5206 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_CDFR_TO_DPD_MASK (0x00000004u)
5207 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_CDFR_TO_DPD_SHIFT (0x00000002u)
5208 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_CDFR_TO_DPD_RESETVAL (0x00000000u)
5210 /* same as above */
5211 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_DPD_TO_TX_MASK (0x00000008u)
5212 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_DPD_TO_TX_SHIFT (0x00000003u)
5213 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_DPD_TO_TX_RESETVAL (0x00000000u)
5215 /* same as above */
5216 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_TX_TO_JESD_MASK (0x00000010u)
5217 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_TX_TO_JESD_SHIFT (0x00000004u)
5218 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_TX_TO_JESD_RESETVAL (0x00000000u)
5220 /* same as above */
5221 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_JESD_TO_RX_MASK (0x00000020u)
5222 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_JESD_TO_RX_SHIFT (0x00000005u)
5223 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_JESD_TO_RX_RESETVAL (0x00000000u)
5225 /* same as above */
5226 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_JESD_TO_FB_MASK (0x00000040u)
5227 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_JESD_TO_FB_SHIFT (0x00000006u)
5228 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_JESD_TO_FB_RESETVAL (0x00000000u)
5230 /* same as above */
5231 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_RX_TO_DDUC_MASK (0x00000080u)
5232 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_RX_TO_DDUC_SHIFT (0x00000007u)
5233 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_RX_TO_DDUC_RESETVAL (0x00000000u)
5235 /* same as above */
5236 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_FB_TO_DDUC_MASK (0x00000100u)
5237 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_FB_TO_DDUC_SHIFT (0x00000008u)
5238 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_FB_TO_DDUC_RESETVAL (0x00000000u)
5240 /* same as above */
5241 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_DDUC_TO_BB_MASK (0x00000200u)
5242 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_DDUC_TO_BB_SHIFT (0x00000009u)
5243 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_CB_SRC_DDUC_TO_BB_RESETVAL (0x00000000u)
5245 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_ADDR (0x00000460u)
5246 #define CSL_DFE_CB_CB_SRC_NODE_CONTROL_REG_RESETVAL (0x00000000u)
5248 /* BUFFER_FULL_FLAG */
5249 typedef struct
5250 {
5251 #ifdef _BIG_ENDIAN
5252 Uint32 rsvd0 : 28;
5253 Uint32 cbd_full : 1;
5254 Uint32 cbc_full : 1;
5255 Uint32 cbb_full : 1;
5256 Uint32 cba_full : 1;
5257 #else
5258 Uint32 cba_full : 1;
5259 Uint32 cbb_full : 1;
5260 Uint32 cbc_full : 1;
5261 Uint32 cbd_full : 1;
5262 Uint32 rsvd0 : 28;
5263 #endif
5264 } CSL_DFE_CB_BUFFER_FULL_FLAG_REG;
5266 /* The bit will be set to '1' once buffer A is filled with valid data. It will be reset to '0' once cb_c restarts. This buffer is mainly for smart capture mode, especially when 'trig_blk_length' is smaller than buffer size, it is possible that a 'stop capture' is captured before the buffer is filled up with valid data. */
5267 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBA_FULL_MASK (0x00000001u)
5268 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBA_FULL_SHIFT (0x00000000u)
5269 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBA_FULL_RESETVAL (0x00000000u)
5271 /* same as cba_full. */
5272 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBB_FULL_MASK (0x00000002u)
5273 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBB_FULL_SHIFT (0x00000001u)
5274 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBB_FULL_RESETVAL (0x00000000u)
5276 /* same as cba_full. */
5277 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBC_FULL_MASK (0x00000004u)
5278 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBC_FULL_SHIFT (0x00000002u)
5279 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBC_FULL_RESETVAL (0x00000000u)
5281 /* same as cba_full. */
5282 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBD_FULL_MASK (0x00000008u)
5283 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBD_FULL_SHIFT (0x00000003u)
5284 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_CBD_FULL_RESETVAL (0x00000000u)
5286 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_ADDR (0x00000464u)
5287 #define CSL_DFE_CB_BUFFER_FULL_FLAG_REG_RESETVAL (0x00000000u)
5289 /* TRIGA_BLK0_OUTPWR */
5290 typedef struct
5291 {
5292 #ifdef _BIG_ENDIAN
5293 Uint32 rsvd0 : 3;
5294 Uint32 triga_blk0_outpwr : 29;
5295 #else
5296 Uint32 triga_blk0_outpwr : 29;
5297 Uint32 rsvd0 : 3;
5298 #endif
5299 } CSL_DFE_CB_TRIGA_BLK0_OUTPWR_REG;
5301 /* At the end of blk length, triga blk0 will report the average power of this block. How to interprete this value would also depend on setting of trga_blk0, e.g. triga_blk0_MagSqd_sel, triga_blk0_IOC and the threshold T1. Typical setting would be triga_blk0_length = 8191, triga_blk0_MagSqd_sel = 1, triga_blk0_IOC=1 and triga_blk0_T1=0. */
5302 #define CSL_DFE_CB_TRIGA_BLK0_OUTPWR_REG_TRIGA_BLK0_OUTPWR_MASK (0x1FFFFFFFu)
5303 #define CSL_DFE_CB_TRIGA_BLK0_OUTPWR_REG_TRIGA_BLK0_OUTPWR_SHIFT (0x00000000u)
5304 #define CSL_DFE_CB_TRIGA_BLK0_OUTPWR_REG_TRIGA_BLK0_OUTPWR_RESETVAL (0x00000000u)
5306 #define CSL_DFE_CB_TRIGA_BLK0_OUTPWR_REG_ADDR (0x00000468u)
5307 #define CSL_DFE_CB_TRIGA_BLK0_OUTPWR_REG_RESETVAL (0x00000000u)
5309 /* TRIGA_BLK1_OUTPWR */
5310 typedef struct
5311 {
5312 #ifdef _BIG_ENDIAN
5313 Uint32 rsvd0 : 3;
5314 Uint32 triga_blk1_outpwr : 29;
5315 #else
5316 Uint32 triga_blk1_outpwr : 29;
5317 Uint32 rsvd0 : 3;
5318 #endif
5319 } CSL_DFE_CB_TRIGA_BLK1_OUTPWR_REG;
5321 /* similar to triga_blk0_outpwr */
5322 #define CSL_DFE_CB_TRIGA_BLK1_OUTPWR_REG_TRIGA_BLK1_OUTPWR_MASK (0x1FFFFFFFu)
5323 #define CSL_DFE_CB_TRIGA_BLK1_OUTPWR_REG_TRIGA_BLK1_OUTPWR_SHIFT (0x00000000u)
5324 #define CSL_DFE_CB_TRIGA_BLK1_OUTPWR_REG_TRIGA_BLK1_OUTPWR_RESETVAL (0x00000000u)
5326 #define CSL_DFE_CB_TRIGA_BLK1_OUTPWR_REG_ADDR (0x0000046Cu)
5327 #define CSL_DFE_CB_TRIGA_BLK1_OUTPWR_REG_RESETVAL (0x00000000u)
5329 /* TRIGB_BLK0_OUTPWR */
5330 typedef struct
5331 {
5332 #ifdef _BIG_ENDIAN
5333 Uint32 rsvd0 : 3;
5334 Uint32 trigb_blk0_outpwr : 29;
5335 #else
5336 Uint32 trigb_blk0_outpwr : 29;
5337 Uint32 rsvd0 : 3;
5338 #endif
5339 } CSL_DFE_CB_TRIGB_BLK0_OUTPWR_REG;
5341 /* similar to triga_blk0_outpwr */
5342 #define CSL_DFE_CB_TRIGB_BLK0_OUTPWR_REG_TRIGB_BLK0_OUTPWR_MASK (0x1FFFFFFFu)
5343 #define CSL_DFE_CB_TRIGB_BLK0_OUTPWR_REG_TRIGB_BLK0_OUTPWR_SHIFT (0x00000000u)
5344 #define CSL_DFE_CB_TRIGB_BLK0_OUTPWR_REG_TRIGB_BLK0_OUTPWR_RESETVAL (0x00000000u)
5346 #define CSL_DFE_CB_TRIGB_BLK0_OUTPWR_REG_ADDR (0x00000470u)
5347 #define CSL_DFE_CB_TRIGB_BLK0_OUTPWR_REG_RESETVAL (0x00000000u)
5349 /* TRIGB_BLK1_OUTPWR */
5350 typedef struct
5351 {
5352 #ifdef _BIG_ENDIAN
5353 Uint32 rsvd0 : 3;
5354 Uint32 trigb_blk1_outpwr : 29;
5355 #else
5356 Uint32 trigb_blk1_outpwr : 29;
5357 Uint32 rsvd0 : 3;
5358 #endif
5359 } CSL_DFE_CB_TRIGB_BLK1_OUTPWR_REG;
5361 /* similar to triga_blk0_outpwr */
5362 #define CSL_DFE_CB_TRIGB_BLK1_OUTPWR_REG_TRIGB_BLK1_OUTPWR_MASK (0x1FFFFFFFu)
5363 #define CSL_DFE_CB_TRIGB_BLK1_OUTPWR_REG_TRIGB_BLK1_OUTPWR_SHIFT (0x00000000u)
5364 #define CSL_DFE_CB_TRIGB_BLK1_OUTPWR_REG_TRIGB_BLK1_OUTPWR_RESETVAL (0x00000000u)
5366 #define CSL_DFE_CB_TRIGB_BLK1_OUTPWR_REG_ADDR (0x00000474u)
5367 #define CSL_DFE_CB_TRIGB_BLK1_OUTPWR_REG_RESETVAL (0x00000000u)
5369 /* CB_REF_FB_LATENCY_ANT0 */
5370 typedef struct
5371 {
5372 #ifdef _BIG_ENDIAN
5373 Uint32 rsvd0 : 20;
5374 Uint32 ref_fb_latency_ant0 : 12;
5375 #else
5376 Uint32 ref_fb_latency_ant0 : 12;
5377 Uint32 rsvd0 : 20;
5378 #endif
5379 } CSL_DFE_CB_CB_REF_FB_LATENCY_ANT0_REG;
5381 /* 0~4095, specify the latency (in reference samples) between reference signal and the feedback signal such that we can start the capture of refrence signal and capture of feedback signal at different time. This is important when arbiter is controlling capture buffer. */
5382 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT0_REG_REF_FB_LATENCY_ANT0_MASK (0x00000FFFu)
5383 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT0_REG_REF_FB_LATENCY_ANT0_SHIFT (0x00000000u)
5384 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT0_REG_REF_FB_LATENCY_ANT0_RESETVAL (0x00000000u)
5386 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT0_REG_ADDR (0x00000478u)
5387 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT0_REG_RESETVAL (0x00000000u)
5389 /* CB_REF_FB_LATENCY_ANT1 */
5390 typedef struct
5391 {
5392 #ifdef _BIG_ENDIAN
5393 Uint32 rsvd0 : 20;
5394 Uint32 ref_fb_latency_ant1 : 12;
5395 #else
5396 Uint32 ref_fb_latency_ant1 : 12;
5397 Uint32 rsvd0 : 20;
5398 #endif
5399 } CSL_DFE_CB_CB_REF_FB_LATENCY_ANT1_REG;
5401 /* same as above */
5402 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT1_REG_REF_FB_LATENCY_ANT1_MASK (0x00000FFFu)
5403 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT1_REG_REF_FB_LATENCY_ANT1_SHIFT (0x00000000u)
5404 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT1_REG_REF_FB_LATENCY_ANT1_RESETVAL (0x00000000u)
5406 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT1_REG_ADDR (0x0000047Cu)
5407 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT1_REG_RESETVAL (0x00000000u)
5409 /* CB_REF_FB_LATENCY_ANT2 */
5410 typedef struct
5411 {
5412 #ifdef _BIG_ENDIAN
5413 Uint32 rsvd0 : 20;
5414 Uint32 ref_fb_latency_ant2 : 12;
5415 #else
5416 Uint32 ref_fb_latency_ant2 : 12;
5417 Uint32 rsvd0 : 20;
5418 #endif
5419 } CSL_DFE_CB_CB_REF_FB_LATENCY_ANT2_REG;
5421 /* same as above */
5422 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT2_REG_REF_FB_LATENCY_ANT2_MASK (0x00000FFFu)
5423 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT2_REG_REF_FB_LATENCY_ANT2_SHIFT (0x00000000u)
5424 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT2_REG_REF_FB_LATENCY_ANT2_RESETVAL (0x00000000u)
5426 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT2_REG_ADDR (0x00000480u)
5427 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT2_REG_RESETVAL (0x00000000u)
5429 /* CB_REF_FB_LATENCY_ANT3 */
5430 typedef struct
5431 {
5432 #ifdef _BIG_ENDIAN
5433 Uint32 rsvd0 : 20;
5434 Uint32 ref_fb_latency_ant3 : 12;
5435 #else
5436 Uint32 ref_fb_latency_ant3 : 12;
5437 Uint32 rsvd0 : 20;
5438 #endif
5439 } CSL_DFE_CB_CB_REF_FB_LATENCY_ANT3_REG;
5441 /* same as above */
5442 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT3_REG_REF_FB_LATENCY_ANT3_MASK (0x00000FFFu)
5443 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT3_REG_REF_FB_LATENCY_ANT3_SHIFT (0x00000000u)
5444 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT3_REG_REF_FB_LATENCY_ANT3_RESETVAL (0x00000000u)
5446 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT3_REG_ADDR (0x00000484u)
5447 #define CSL_DFE_CB_CB_REF_FB_LATENCY_ANT3_REG_RESETVAL (0x00000000u)
5449 /* CB_SYNC_SELECT_PART4 */
5450 typedef struct
5451 {
5452 #ifdef _BIG_ENDIAN
5453 Uint32 rsvd0 : 16;
5454 Uint32 cb_f_powermonitor_ant3_ssel : 4;
5455 Uint32 cb_f_powermonitor_ant2_ssel : 4;
5456 Uint32 cb_f_powermonitor_ant1_ssel : 4;
5457 Uint32 cb_f_powermonitor_ant0_ssel : 4;
5458 #else
5459 Uint32 cb_f_powermonitor_ant0_ssel : 4;
5460 Uint32 cb_f_powermonitor_ant1_ssel : 4;
5461 Uint32 cb_f_powermonitor_ant2_ssel : 4;
5462 Uint32 cb_f_powermonitor_ant3_ssel : 4;
5463 Uint32 rsvd0 : 16;
5464 #endif
5465 } CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG;
5467 /* sync select for CB-F power monitor in order to get MaxRefPwr for antenna 0 */
5468 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT0_SSEL_MASK (0x0000000Fu)
5469 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT0_SSEL_SHIFT (0x00000000u)
5470 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT0_SSEL_RESETVAL (0x00000000u)
5472 /* sync select for CB-F power monitor in order to get MaxRefPwr for antenna 1 */
5473 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT1_SSEL_MASK (0x000000F0u)
5474 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT1_SSEL_SHIFT (0x00000004u)
5475 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT1_SSEL_RESETVAL (0x00000000u)
5477 /* sync select for CB-F power monitor in order to get MaxRefPwr for antenna 2 */
5478 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT2_SSEL_MASK (0x00000F00u)
5479 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT2_SSEL_SHIFT (0x00000008u)
5480 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT2_SSEL_RESETVAL (0x00000000u)
5482 /* sync select for CB-F power monitor in order to get MaxRefPwr for antenna 3 */
5483 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT3_SSEL_MASK (0x0000F000u)
5484 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT3_SSEL_SHIFT (0x0000000Cu)
5485 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_CB_F_POWERMONITOR_ANT3_SSEL_RESETVAL (0x00000000u)
5487 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_ADDR (0x00000488u)
5488 #define CSL_DFE_CB_CB_SYNC_SELECT_PART4_REG_RESETVAL (0x00000000u)
5490 /* CBA_CHUNK1_2_DONE_ADDR */
5491 typedef struct
5492 {
5493 #ifdef _BIG_ENDIAN
5494 Uint32 rsvd1 : 3;
5495 Uint32 cba_chunk2_done_addr : 13;
5496 Uint32 rsvd0 : 3;
5497 Uint32 cba_chunk1_done_addr : 13;
5498 #else
5499 Uint32 cba_chunk1_done_addr : 13;
5500 Uint32 rsvd0 : 3;
5501 Uint32 cba_chunk2_done_addr : 13;
5502 Uint32 rsvd1 : 3;
5503 #endif
5504 } CSL_DFE_CB_CBA_CHUNK1_2_DONE_ADDR_REG;
5506 /* In sharing mode and trigger mode, each section of cb-c buffer (of size chunk size) is a circular buffer, this register indicates where the capture stoped when cba was capturing chunk 1 of reference signal */
5507 #define CSL_DFE_CB_CBA_CHUNK1_2_DONE_ADDR_REG_CBA_CHUNK1_DONE_ADDR_MASK (0x00001FFFu)
5508 #define CSL_DFE_CB_CBA_CHUNK1_2_DONE_ADDR_REG_CBA_CHUNK1_DONE_ADDR_SHIFT (0x00000000u)
5509 #define CSL_DFE_CB_CBA_CHUNK1_2_DONE_ADDR_REG_CBA_CHUNK1_DONE_ADDR_RESETVAL (0x00000000u)
5511 /* In sharing mode and trigger mode, each section of cb-c buffer (of size chunk size) is a circular buffer, this register indicates where the capture stoped when cba was capturing chunk 2 of reference signal */
5512 #define CSL_DFE_CB_CBA_CHUNK1_2_DONE_ADDR_REG_CBA_CHUNK2_DONE_ADDR_MASK (0x1FFF0000u)
5513 #define CSL_DFE_CB_CBA_CHUNK1_2_DONE_ADDR_REG_CBA_CHUNK2_DONE_ADDR_SHIFT (0x00000010u)
5514 #define CSL_DFE_CB_CBA_CHUNK1_2_DONE_ADDR_REG_CBA_CHUNK2_DONE_ADDR_RESETVAL (0x00000000u)
5516 #define CSL_DFE_CB_CBA_CHUNK1_2_DONE_ADDR_REG_ADDR (0x0000048Cu)
5517 #define CSL_DFE_CB_CBA_CHUNK1_2_DONE_ADDR_REG_RESETVAL (0x00000000u)
5519 /* CBA_CHUNK3_4_DONE_ADDR */
5520 typedef struct
5521 {
5522 #ifdef _BIG_ENDIAN
5523 Uint32 rsvd1 : 3;
5524 Uint32 cba_chunk4_done_addr : 13;
5525 Uint32 rsvd0 : 3;
5526 Uint32 cba_chunk3_done_addr : 13;
5527 #else
5528 Uint32 cba_chunk3_done_addr : 13;
5529 Uint32 rsvd0 : 3;
5530 Uint32 cba_chunk4_done_addr : 13;
5531 Uint32 rsvd1 : 3;
5532 #endif
5533 } CSL_DFE_CB_CBA_CHUNK3_4_DONE_ADDR_REG;
5535 /* same as above */
5536 #define CSL_DFE_CB_CBA_CHUNK3_4_DONE_ADDR_REG_CBA_CHUNK3_DONE_ADDR_MASK (0x00001FFFu)
5537 #define CSL_DFE_CB_CBA_CHUNK3_4_DONE_ADDR_REG_CBA_CHUNK3_DONE_ADDR_SHIFT (0x00000000u)
5538 #define CSL_DFE_CB_CBA_CHUNK3_4_DONE_ADDR_REG_CBA_CHUNK3_DONE_ADDR_RESETVAL (0x00000000u)
5540 /* same as above */
5541 #define CSL_DFE_CB_CBA_CHUNK3_4_DONE_ADDR_REG_CBA_CHUNK4_DONE_ADDR_MASK (0x1FFF0000u)
5542 #define CSL_DFE_CB_CBA_CHUNK3_4_DONE_ADDR_REG_CBA_CHUNK4_DONE_ADDR_SHIFT (0x00000010u)
5543 #define CSL_DFE_CB_CBA_CHUNK3_4_DONE_ADDR_REG_CBA_CHUNK4_DONE_ADDR_RESETVAL (0x00000000u)
5545 #define CSL_DFE_CB_CBA_CHUNK3_4_DONE_ADDR_REG_ADDR (0x00000490u)
5546 #define CSL_DFE_CB_CBA_CHUNK3_4_DONE_ADDR_REG_RESETVAL (0x00000000u)
5548 /* CBA_CHUNK5_6_DONE_ADDR */
5549 typedef struct
5550 {
5551 #ifdef _BIG_ENDIAN
5552 Uint32 rsvd1 : 3;
5553 Uint32 cba_chunk6_done_addr : 13;
5554 Uint32 rsvd0 : 3;
5555 Uint32 cba_chunk5_done_addr : 13;
5556 #else
5557 Uint32 cba_chunk5_done_addr : 13;
5558 Uint32 rsvd0 : 3;
5559 Uint32 cba_chunk6_done_addr : 13;
5560 Uint32 rsvd1 : 3;
5561 #endif
5562 } CSL_DFE_CB_CBA_CHUNK5_6_DONE_ADDR_REG;
5564 /* same as above */
5565 #define CSL_DFE_CB_CBA_CHUNK5_6_DONE_ADDR_REG_CBA_CHUNK5_DONE_ADDR_MASK (0x00001FFFu)
5566 #define CSL_DFE_CB_CBA_CHUNK5_6_DONE_ADDR_REG_CBA_CHUNK5_DONE_ADDR_SHIFT (0x00000000u)
5567 #define CSL_DFE_CB_CBA_CHUNK5_6_DONE_ADDR_REG_CBA_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
5569 /* same as above */
5570 #define CSL_DFE_CB_CBA_CHUNK5_6_DONE_ADDR_REG_CBA_CHUNK6_DONE_ADDR_MASK (0x1FFF0000u)
5571 #define CSL_DFE_CB_CBA_CHUNK5_6_DONE_ADDR_REG_CBA_CHUNK6_DONE_ADDR_SHIFT (0x00000010u)
5572 #define CSL_DFE_CB_CBA_CHUNK5_6_DONE_ADDR_REG_CBA_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
5574 #define CSL_DFE_CB_CBA_CHUNK5_6_DONE_ADDR_REG_ADDR (0x00000494u)
5575 #define CSL_DFE_CB_CBA_CHUNK5_6_DONE_ADDR_REG_RESETVAL (0x00000000u)
5577 /* CBA_CHUNK7_8_DONE_ADDR */
5578 typedef struct
5579 {
5580 #ifdef _BIG_ENDIAN
5581 Uint32 rsvd1 : 3;
5582 Uint32 cba_chunk6_done_addr : 13;
5583 Uint32 rsvd0 : 3;
5584 Uint32 cba_chunk5_done_addr : 13;
5585 #else
5586 Uint32 cba_chunk5_done_addr : 13;
5587 Uint32 rsvd0 : 3;
5588 Uint32 cba_chunk6_done_addr : 13;
5589 Uint32 rsvd1 : 3;
5590 #endif
5591 } CSL_DFE_CB_CBA_CHUNK7_8_DONE_ADDR_REG;
5593 /* same as above */
5594 #define CSL_DFE_CB_CBA_CHUNK7_8_DONE_ADDR_REG_CBA_CHUNK5_DONE_ADDR_MASK (0x00001FFFu)
5595 #define CSL_DFE_CB_CBA_CHUNK7_8_DONE_ADDR_REG_CBA_CHUNK5_DONE_ADDR_SHIFT (0x00000000u)
5596 #define CSL_DFE_CB_CBA_CHUNK7_8_DONE_ADDR_REG_CBA_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
5598 /* same as above */
5599 #define CSL_DFE_CB_CBA_CHUNK7_8_DONE_ADDR_REG_CBA_CHUNK6_DONE_ADDR_MASK (0x1FFF0000u)
5600 #define CSL_DFE_CB_CBA_CHUNK7_8_DONE_ADDR_REG_CBA_CHUNK6_DONE_ADDR_SHIFT (0x00000010u)
5601 #define CSL_DFE_CB_CBA_CHUNK7_8_DONE_ADDR_REG_CBA_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
5603 #define CSL_DFE_CB_CBA_CHUNK7_8_DONE_ADDR_REG_ADDR (0x00000498u)
5604 #define CSL_DFE_CB_CBA_CHUNK7_8_DONE_ADDR_REG_RESETVAL (0x00000000u)
5606 /* CBB_CHUNK1_2_DONE_ADDR */
5607 typedef struct
5608 {
5609 #ifdef _BIG_ENDIAN
5610 Uint32 rsvd1 : 3;
5611 Uint32 cbb_chunk2_done_addr : 13;
5612 Uint32 rsvd0 : 3;
5613 Uint32 cbb_chunk1_done_addr : 13;
5614 #else
5615 Uint32 cbb_chunk1_done_addr : 13;
5616 Uint32 rsvd0 : 3;
5617 Uint32 cbb_chunk2_done_addr : 13;
5618 Uint32 rsvd1 : 3;
5619 #endif
5620 } CSL_DFE_CB_CBB_CHUNK1_2_DONE_ADDR_REG;
5622 /* same as above */
5623 #define CSL_DFE_CB_CBB_CHUNK1_2_DONE_ADDR_REG_CBB_CHUNK1_DONE_ADDR_MASK (0x00001FFFu)
5624 #define CSL_DFE_CB_CBB_CHUNK1_2_DONE_ADDR_REG_CBB_CHUNK1_DONE_ADDR_SHIFT (0x00000000u)
5625 #define CSL_DFE_CB_CBB_CHUNK1_2_DONE_ADDR_REG_CBB_CHUNK1_DONE_ADDR_RESETVAL (0x00000000u)
5627 /* same as above */
5628 #define CSL_DFE_CB_CBB_CHUNK1_2_DONE_ADDR_REG_CBB_CHUNK2_DONE_ADDR_MASK (0x1FFF0000u)
5629 #define CSL_DFE_CB_CBB_CHUNK1_2_DONE_ADDR_REG_CBB_CHUNK2_DONE_ADDR_SHIFT (0x00000010u)
5630 #define CSL_DFE_CB_CBB_CHUNK1_2_DONE_ADDR_REG_CBB_CHUNK2_DONE_ADDR_RESETVAL (0x00000000u)
5632 #define CSL_DFE_CB_CBB_CHUNK1_2_DONE_ADDR_REG_ADDR (0x0000049Cu)
5633 #define CSL_DFE_CB_CBB_CHUNK1_2_DONE_ADDR_REG_RESETVAL (0x00000000u)
5635 /* CBB_CHUNK3_4_DONE_ADDR */
5636 typedef struct
5637 {
5638 #ifdef _BIG_ENDIAN
5639 Uint32 rsvd1 : 3;
5640 Uint32 cbb_chunk4_done_addr : 13;
5641 Uint32 rsvd0 : 3;
5642 Uint32 cbb_chunk3_done_addr : 13;
5643 #else
5644 Uint32 cbb_chunk3_done_addr : 13;
5645 Uint32 rsvd0 : 3;
5646 Uint32 cbb_chunk4_done_addr : 13;
5647 Uint32 rsvd1 : 3;
5648 #endif
5649 } CSL_DFE_CB_CBB_CHUNK3_4_DONE_ADDR_REG;
5651 /* same as above */
5652 #define CSL_DFE_CB_CBB_CHUNK3_4_DONE_ADDR_REG_CBB_CHUNK3_DONE_ADDR_MASK (0x00001FFFu)
5653 #define CSL_DFE_CB_CBB_CHUNK3_4_DONE_ADDR_REG_CBB_CHUNK3_DONE_ADDR_SHIFT (0x00000000u)
5654 #define CSL_DFE_CB_CBB_CHUNK3_4_DONE_ADDR_REG_CBB_CHUNK3_DONE_ADDR_RESETVAL (0x00000000u)
5656 /* same as above */
5657 #define CSL_DFE_CB_CBB_CHUNK3_4_DONE_ADDR_REG_CBB_CHUNK4_DONE_ADDR_MASK (0x1FFF0000u)
5658 #define CSL_DFE_CB_CBB_CHUNK3_4_DONE_ADDR_REG_CBB_CHUNK4_DONE_ADDR_SHIFT (0x00000010u)
5659 #define CSL_DFE_CB_CBB_CHUNK3_4_DONE_ADDR_REG_CBB_CHUNK4_DONE_ADDR_RESETVAL (0x00000000u)
5661 #define CSL_DFE_CB_CBB_CHUNK3_4_DONE_ADDR_REG_ADDR (0x000004A0u)
5662 #define CSL_DFE_CB_CBB_CHUNK3_4_DONE_ADDR_REG_RESETVAL (0x00000000u)
5664 /* CBB_CHUNK5_6_DONE_ADDR */
5665 typedef struct
5666 {
5667 #ifdef _BIG_ENDIAN
5668 Uint32 rsvd1 : 3;
5669 Uint32 cbb_chunk6_done_addr : 13;
5670 Uint32 rsvd0 : 3;
5671 Uint32 cbb_chunk5_done_addr : 13;
5672 #else
5673 Uint32 cbb_chunk5_done_addr : 13;
5674 Uint32 rsvd0 : 3;
5675 Uint32 cbb_chunk6_done_addr : 13;
5676 Uint32 rsvd1 : 3;
5677 #endif
5678 } CSL_DFE_CB_CBB_CHUNK5_6_DONE_ADDR_REG;
5680 /* same as above */
5681 #define CSL_DFE_CB_CBB_CHUNK5_6_DONE_ADDR_REG_CBB_CHUNK5_DONE_ADDR_MASK (0x00001FFFu)
5682 #define CSL_DFE_CB_CBB_CHUNK5_6_DONE_ADDR_REG_CBB_CHUNK5_DONE_ADDR_SHIFT (0x00000000u)
5683 #define CSL_DFE_CB_CBB_CHUNK5_6_DONE_ADDR_REG_CBB_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
5685 /* same as above */
5686 #define CSL_DFE_CB_CBB_CHUNK5_6_DONE_ADDR_REG_CBB_CHUNK6_DONE_ADDR_MASK (0x1FFF0000u)
5687 #define CSL_DFE_CB_CBB_CHUNK5_6_DONE_ADDR_REG_CBB_CHUNK6_DONE_ADDR_SHIFT (0x00000010u)
5688 #define CSL_DFE_CB_CBB_CHUNK5_6_DONE_ADDR_REG_CBB_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
5690 #define CSL_DFE_CB_CBB_CHUNK5_6_DONE_ADDR_REG_ADDR (0x000004A4u)
5691 #define CSL_DFE_CB_CBB_CHUNK5_6_DONE_ADDR_REG_RESETVAL (0x00000000u)
5693 /* CBB_CHUNK7_8_DONE_ADDR */
5694 typedef struct
5695 {
5696 #ifdef _BIG_ENDIAN
5697 Uint32 rsvd1 : 3;
5698 Uint32 cbb_chunk6_done_addr : 13;
5699 Uint32 rsvd0 : 3;
5700 Uint32 cbb_chunk5_done_addr : 13;
5701 #else
5702 Uint32 cbb_chunk5_done_addr : 13;
5703 Uint32 rsvd0 : 3;
5704 Uint32 cbb_chunk6_done_addr : 13;
5705 Uint32 rsvd1 : 3;
5706 #endif
5707 } CSL_DFE_CB_CBB_CHUNK7_8_DONE_ADDR_REG;
5709 /* same as above */
5710 #define CSL_DFE_CB_CBB_CHUNK7_8_DONE_ADDR_REG_CBB_CHUNK5_DONE_ADDR_MASK (0x00001FFFu)
5711 #define CSL_DFE_CB_CBB_CHUNK7_8_DONE_ADDR_REG_CBB_CHUNK5_DONE_ADDR_SHIFT (0x00000000u)
5712 #define CSL_DFE_CB_CBB_CHUNK7_8_DONE_ADDR_REG_CBB_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
5714 /* same as above */
5715 #define CSL_DFE_CB_CBB_CHUNK7_8_DONE_ADDR_REG_CBB_CHUNK6_DONE_ADDR_MASK (0x1FFF0000u)
5716 #define CSL_DFE_CB_CBB_CHUNK7_8_DONE_ADDR_REG_CBB_CHUNK6_DONE_ADDR_SHIFT (0x00000010u)
5717 #define CSL_DFE_CB_CBB_CHUNK7_8_DONE_ADDR_REG_CBB_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
5719 #define CSL_DFE_CB_CBB_CHUNK7_8_DONE_ADDR_REG_ADDR (0x000004A8u)
5720 #define CSL_DFE_CB_CBB_CHUNK7_8_DONE_ADDR_REG_RESETVAL (0x00000000u)
5722 /* CBC_CHUNK1_2_DONE_ADDR */
5723 typedef struct
5724 {
5725 #ifdef _BIG_ENDIAN
5726 Uint32 rsvd1 : 3;
5727 Uint32 cbc_chunk2_done_addr : 13;
5728 Uint32 rsvd0 : 3;
5729 Uint32 cbc_chunk1_done_addr : 13;
5730 #else
5731 Uint32 cbc_chunk1_done_addr : 13;
5732 Uint32 rsvd0 : 3;
5733 Uint32 cbc_chunk2_done_addr : 13;
5734 Uint32 rsvd1 : 3;
5735 #endif
5736 } CSL_DFE_CB_CBC_CHUNK1_2_DONE_ADDR_REG;
5738 /* same as above */
5739 #define CSL_DFE_CB_CBC_CHUNK1_2_DONE_ADDR_REG_CBC_CHUNK1_DONE_ADDR_MASK (0x00001FFFu)
5740 #define CSL_DFE_CB_CBC_CHUNK1_2_DONE_ADDR_REG_CBC_CHUNK1_DONE_ADDR_SHIFT (0x00000000u)
5741 #define CSL_DFE_CB_CBC_CHUNK1_2_DONE_ADDR_REG_CBC_CHUNK1_DONE_ADDR_RESETVAL (0x00000000u)
5743 /* same as above */
5744 #define CSL_DFE_CB_CBC_CHUNK1_2_DONE_ADDR_REG_CBC_CHUNK2_DONE_ADDR_MASK (0x1FFF0000u)
5745 #define CSL_DFE_CB_CBC_CHUNK1_2_DONE_ADDR_REG_CBC_CHUNK2_DONE_ADDR_SHIFT (0x00000010u)
5746 #define CSL_DFE_CB_CBC_CHUNK1_2_DONE_ADDR_REG_CBC_CHUNK2_DONE_ADDR_RESETVAL (0x00000000u)
5748 #define CSL_DFE_CB_CBC_CHUNK1_2_DONE_ADDR_REG_ADDR (0x000004ACu)
5749 #define CSL_DFE_CB_CBC_CHUNK1_2_DONE_ADDR_REG_RESETVAL (0x00000000u)
5751 /* CBC_CHUNK3_4_DONE_ADDR */
5752 typedef struct
5753 {
5754 #ifdef _BIG_ENDIAN
5755 Uint32 rsvd1 : 3;
5756 Uint32 cbc_chunk4_done_addr : 13;
5757 Uint32 rsvd0 : 3;
5758 Uint32 cbc_chunk3_done_addr : 13;
5759 #else
5760 Uint32 cbc_chunk3_done_addr : 13;
5761 Uint32 rsvd0 : 3;
5762 Uint32 cbc_chunk4_done_addr : 13;
5763 Uint32 rsvd1 : 3;
5764 #endif
5765 } CSL_DFE_CB_CBC_CHUNK3_4_DONE_ADDR_REG;
5767 /* same as above */
5768 #define CSL_DFE_CB_CBC_CHUNK3_4_DONE_ADDR_REG_CBC_CHUNK3_DONE_ADDR_MASK (0x00001FFFu)
5769 #define CSL_DFE_CB_CBC_CHUNK3_4_DONE_ADDR_REG_CBC_CHUNK3_DONE_ADDR_SHIFT (0x00000000u)
5770 #define CSL_DFE_CB_CBC_CHUNK3_4_DONE_ADDR_REG_CBC_CHUNK3_DONE_ADDR_RESETVAL (0x00000000u)
5772 /* same as above */
5773 #define CSL_DFE_CB_CBC_CHUNK3_4_DONE_ADDR_REG_CBC_CHUNK4_DONE_ADDR_MASK (0x1FFF0000u)
5774 #define CSL_DFE_CB_CBC_CHUNK3_4_DONE_ADDR_REG_CBC_CHUNK4_DONE_ADDR_SHIFT (0x00000010u)
5775 #define CSL_DFE_CB_CBC_CHUNK3_4_DONE_ADDR_REG_CBC_CHUNK4_DONE_ADDR_RESETVAL (0x00000000u)
5777 #define CSL_DFE_CB_CBC_CHUNK3_4_DONE_ADDR_REG_ADDR (0x000004B0u)
5778 #define CSL_DFE_CB_CBC_CHUNK3_4_DONE_ADDR_REG_RESETVAL (0x00000000u)
5780 /* CBC_CHUNK5_6_DONE_ADDR */
5781 typedef struct
5782 {
5783 #ifdef _BIG_ENDIAN
5784 Uint32 rsvd1 : 3;
5785 Uint32 cbc_chunk6_done_addr : 13;
5786 Uint32 rsvd0 : 3;
5787 Uint32 cbc_chunk5_done_addr : 13;
5788 #else
5789 Uint32 cbc_chunk5_done_addr : 13;
5790 Uint32 rsvd0 : 3;
5791 Uint32 cbc_chunk6_done_addr : 13;
5792 Uint32 rsvd1 : 3;
5793 #endif
5794 } CSL_DFE_CB_CBC_CHUNK5_6_DONE_ADDR_REG;
5796 /* same as above */
5797 #define CSL_DFE_CB_CBC_CHUNK5_6_DONE_ADDR_REG_CBC_CHUNK5_DONE_ADDR_MASK (0x00001FFFu)
5798 #define CSL_DFE_CB_CBC_CHUNK5_6_DONE_ADDR_REG_CBC_CHUNK5_DONE_ADDR_SHIFT (0x00000000u)
5799 #define CSL_DFE_CB_CBC_CHUNK5_6_DONE_ADDR_REG_CBC_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
5801 /* same as above */
5802 #define CSL_DFE_CB_CBC_CHUNK5_6_DONE_ADDR_REG_CBC_CHUNK6_DONE_ADDR_MASK (0x1FFF0000u)
5803 #define CSL_DFE_CB_CBC_CHUNK5_6_DONE_ADDR_REG_CBC_CHUNK6_DONE_ADDR_SHIFT (0x00000010u)
5804 #define CSL_DFE_CB_CBC_CHUNK5_6_DONE_ADDR_REG_CBC_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
5806 #define CSL_DFE_CB_CBC_CHUNK5_6_DONE_ADDR_REG_ADDR (0x000004B4u)
5807 #define CSL_DFE_CB_CBC_CHUNK5_6_DONE_ADDR_REG_RESETVAL (0x00000000u)
5809 /* CBC_CHUNK7_8_DONE_ADDR */
5810 typedef struct
5811 {
5812 #ifdef _BIG_ENDIAN
5813 Uint32 rsvd1 : 3;
5814 Uint32 cbc_chunk6_done_addr : 13;
5815 Uint32 rsvd0 : 3;
5816 Uint32 cbc_chunk5_done_addr : 13;
5817 #else
5818 Uint32 cbc_chunk5_done_addr : 13;
5819 Uint32 rsvd0 : 3;
5820 Uint32 cbc_chunk6_done_addr : 13;
5821 Uint32 rsvd1 : 3;
5822 #endif
5823 } CSL_DFE_CB_CBC_CHUNK7_8_DONE_ADDR_REG;
5825 /* same as above */
5826 #define CSL_DFE_CB_CBC_CHUNK7_8_DONE_ADDR_REG_CBC_CHUNK5_DONE_ADDR_MASK (0x00001FFFu)
5827 #define CSL_DFE_CB_CBC_CHUNK7_8_DONE_ADDR_REG_CBC_CHUNK5_DONE_ADDR_SHIFT (0x00000000u)
5828 #define CSL_DFE_CB_CBC_CHUNK7_8_DONE_ADDR_REG_CBC_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
5830 /* same as above */
5831 #define CSL_DFE_CB_CBC_CHUNK7_8_DONE_ADDR_REG_CBC_CHUNK6_DONE_ADDR_MASK (0x1FFF0000u)
5832 #define CSL_DFE_CB_CBC_CHUNK7_8_DONE_ADDR_REG_CBC_CHUNK6_DONE_ADDR_SHIFT (0x00000010u)
5833 #define CSL_DFE_CB_CBC_CHUNK7_8_DONE_ADDR_REG_CBC_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
5835 #define CSL_DFE_CB_CBC_CHUNK7_8_DONE_ADDR_REG_ADDR (0x000004B8u)
5836 #define CSL_DFE_CB_CBC_CHUNK7_8_DONE_ADDR_REG_RESETVAL (0x00000000u)
5838 /* CBD_CHUNK1_2_DONE_ADDR */
5839 typedef struct
5840 {
5841 #ifdef _BIG_ENDIAN
5842 Uint32 rsvd1 : 3;
5843 Uint32 cbd_chunk2_done_addr : 13;
5844 Uint32 rsvd0 : 3;
5845 Uint32 cbd_chunk1_done_addr : 13;
5846 #else
5847 Uint32 cbd_chunk1_done_addr : 13;
5848 Uint32 rsvd0 : 3;
5849 Uint32 cbd_chunk2_done_addr : 13;
5850 Uint32 rsvd1 : 3;
5851 #endif
5852 } CSL_DFE_CB_CBD_CHUNK1_2_DONE_ADDR_REG;
5854 /* same as above */
5855 #define CSL_DFE_CB_CBD_CHUNK1_2_DONE_ADDR_REG_CBD_CHUNK1_DONE_ADDR_MASK (0x00001FFFu)
5856 #define CSL_DFE_CB_CBD_CHUNK1_2_DONE_ADDR_REG_CBD_CHUNK1_DONE_ADDR_SHIFT (0x00000000u)
5857 #define CSL_DFE_CB_CBD_CHUNK1_2_DONE_ADDR_REG_CBD_CHUNK1_DONE_ADDR_RESETVAL (0x00000000u)
5859 /* same as above */
5860 #define CSL_DFE_CB_CBD_CHUNK1_2_DONE_ADDR_REG_CBD_CHUNK2_DONE_ADDR_MASK (0x1FFF0000u)
5861 #define CSL_DFE_CB_CBD_CHUNK1_2_DONE_ADDR_REG_CBD_CHUNK2_DONE_ADDR_SHIFT (0x00000010u)
5862 #define CSL_DFE_CB_CBD_CHUNK1_2_DONE_ADDR_REG_CBD_CHUNK2_DONE_ADDR_RESETVAL (0x00000000u)
5864 #define CSL_DFE_CB_CBD_CHUNK1_2_DONE_ADDR_REG_ADDR (0x000004BCu)
5865 #define CSL_DFE_CB_CBD_CHUNK1_2_DONE_ADDR_REG_RESETVAL (0x00000000u)
5867 /* CBD_CHUNK3_4_DONE_ADDR */
5868 typedef struct
5869 {
5870 #ifdef _BIG_ENDIAN
5871 Uint32 rsvd1 : 3;
5872 Uint32 cbd_chunk4_done_addr : 13;
5873 Uint32 rsvd0 : 3;
5874 Uint32 cbd_chunk3_done_addr : 13;
5875 #else
5876 Uint32 cbd_chunk3_done_addr : 13;
5877 Uint32 rsvd0 : 3;
5878 Uint32 cbd_chunk4_done_addr : 13;
5879 Uint32 rsvd1 : 3;
5880 #endif
5881 } CSL_DFE_CB_CBD_CHUNK3_4_DONE_ADDR_REG;
5883 /* same as above */
5884 #define CSL_DFE_CB_CBD_CHUNK3_4_DONE_ADDR_REG_CBD_CHUNK3_DONE_ADDR_MASK (0x00001FFFu)
5885 #define CSL_DFE_CB_CBD_CHUNK3_4_DONE_ADDR_REG_CBD_CHUNK3_DONE_ADDR_SHIFT (0x00000000u)
5886 #define CSL_DFE_CB_CBD_CHUNK3_4_DONE_ADDR_REG_CBD_CHUNK3_DONE_ADDR_RESETVAL (0x00000000u)
5888 /* same as above */
5889 #define CSL_DFE_CB_CBD_CHUNK3_4_DONE_ADDR_REG_CBD_CHUNK4_DONE_ADDR_MASK (0x1FFF0000u)
5890 #define CSL_DFE_CB_CBD_CHUNK3_4_DONE_ADDR_REG_CBD_CHUNK4_DONE_ADDR_SHIFT (0x00000010u)
5891 #define CSL_DFE_CB_CBD_CHUNK3_4_DONE_ADDR_REG_CBD_CHUNK4_DONE_ADDR_RESETVAL (0x00000000u)
5893 #define CSL_DFE_CB_CBD_CHUNK3_4_DONE_ADDR_REG_ADDR (0x000004C0u)
5894 #define CSL_DFE_CB_CBD_CHUNK3_4_DONE_ADDR_REG_RESETVAL (0x00000000u)
5896 /* CBD_CHUNK5_6_DONE_ADDR */
5897 typedef struct
5898 {
5899 #ifdef _BIG_ENDIAN
5900 Uint32 rsvd1 : 3;
5901 Uint32 cbd_chunk6_done_addr : 13;
5902 Uint32 rsvd0 : 3;
5903 Uint32 cbd_chunk5_done_addr : 13;
5904 #else
5905 Uint32 cbd_chunk5_done_addr : 13;
5906 Uint32 rsvd0 : 3;
5907 Uint32 cbd_chunk6_done_addr : 13;
5908 Uint32 rsvd1 : 3;
5909 #endif
5910 } CSL_DFE_CB_CBD_CHUNK5_6_DONE_ADDR_REG;
5912 /* same as above */
5913 #define CSL_DFE_CB_CBD_CHUNK5_6_DONE_ADDR_REG_CBD_CHUNK5_DONE_ADDR_MASK (0x00001FFFu)
5914 #define CSL_DFE_CB_CBD_CHUNK5_6_DONE_ADDR_REG_CBD_CHUNK5_DONE_ADDR_SHIFT (0x00000000u)
5915 #define CSL_DFE_CB_CBD_CHUNK5_6_DONE_ADDR_REG_CBD_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
5917 /* same as above */
5918 #define CSL_DFE_CB_CBD_CHUNK5_6_DONE_ADDR_REG_CBD_CHUNK6_DONE_ADDR_MASK (0x1FFF0000u)
5919 #define CSL_DFE_CB_CBD_CHUNK5_6_DONE_ADDR_REG_CBD_CHUNK6_DONE_ADDR_SHIFT (0x00000010u)
5920 #define CSL_DFE_CB_CBD_CHUNK5_6_DONE_ADDR_REG_CBD_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
5922 #define CSL_DFE_CB_CBD_CHUNK5_6_DONE_ADDR_REG_ADDR (0x000004C4u)
5923 #define CSL_DFE_CB_CBD_CHUNK5_6_DONE_ADDR_REG_RESETVAL (0x00000000u)
5925 /* CBD_CHUNK7_8_DONE_ADDR */
5926 typedef struct
5927 {
5928 #ifdef _BIG_ENDIAN
5929 Uint32 rsvd1 : 3;
5930 Uint32 cbd_chunk6_done_addr : 13;
5931 Uint32 rsvd0 : 3;
5932 Uint32 cbd_chunk5_done_addr : 13;
5933 #else
5934 Uint32 cbd_chunk5_done_addr : 13;
5935 Uint32 rsvd0 : 3;
5936 Uint32 cbd_chunk6_done_addr : 13;
5937 Uint32 rsvd1 : 3;
5938 #endif
5939 } CSL_DFE_CB_CBD_CHUNK7_8_DONE_ADDR_REG;
5941 /* same as above */
5942 #define CSL_DFE_CB_CBD_CHUNK7_8_DONE_ADDR_REG_CBD_CHUNK5_DONE_ADDR_MASK (0x00001FFFu)
5943 #define CSL_DFE_CB_CBD_CHUNK7_8_DONE_ADDR_REG_CBD_CHUNK5_DONE_ADDR_SHIFT (0x00000000u)
5944 #define CSL_DFE_CB_CBD_CHUNK7_8_DONE_ADDR_REG_CBD_CHUNK5_DONE_ADDR_RESETVAL (0x00000000u)
5946 /* same as above */
5947 #define CSL_DFE_CB_CBD_CHUNK7_8_DONE_ADDR_REG_CBD_CHUNK6_DONE_ADDR_MASK (0x1FFF0000u)
5948 #define CSL_DFE_CB_CBD_CHUNK7_8_DONE_ADDR_REG_CBD_CHUNK6_DONE_ADDR_SHIFT (0x00000010u)
5949 #define CSL_DFE_CB_CBD_CHUNK7_8_DONE_ADDR_REG_CBD_CHUNK6_DONE_ADDR_RESETVAL (0x00000000u)
5951 #define CSL_DFE_CB_CBD_CHUNK7_8_DONE_ADDR_REG_ADDR (0x000004C8u)
5952 #define CSL_DFE_CB_CBD_CHUNK7_8_DONE_ADDR_REG_RESETVAL (0x00000000u)
5954 /* CAPTURE_BUFFER_A_16MSB */
5955 typedef struct
5956 {
5957 #ifdef _BIG_ENDIAN
5958 Uint32 capture_buffer_a_i_16msb : 16;
5959 Uint32 capture_buffer_a_q_16msb : 16;
5960 #else
5961 Uint32 capture_buffer_a_q_16msb : 16;
5962 Uint32 capture_buffer_a_i_16msb : 16;
5963 #endif
5964 } CSL_DFE_CB_CAPTURE_BUFFER_A_16MSB_REG;
5966 /* capture buffer A data, Q[17:2], memory is also readable when 'cba_mode' is set to 'mpu_mode' regardless 'mem_mpu_access'. */
5967 #define CSL_DFE_CB_CAPTURE_BUFFER_A_16MSB_REG_CAPTURE_BUFFER_A_Q_16MSB_MASK (0x0000FFFFu)
5968 #define CSL_DFE_CB_CAPTURE_BUFFER_A_16MSB_REG_CAPTURE_BUFFER_A_Q_16MSB_SHIFT (0x00000000u)
5969 #define CSL_DFE_CB_CAPTURE_BUFFER_A_16MSB_REG_CAPTURE_BUFFER_A_Q_16MSB_RESETVAL (0x00000000u)
5971 /* capture buffer A data, I[17:2], memory is also readable when 'cba_mode' is set to 'mpu_mode' regardless 'mem_mpu_access'. */
5972 #define CSL_DFE_CB_CAPTURE_BUFFER_A_16MSB_REG_CAPTURE_BUFFER_A_I_16MSB_MASK (0xFFFF0000u)
5973 #define CSL_DFE_CB_CAPTURE_BUFFER_A_16MSB_REG_CAPTURE_BUFFER_A_I_16MSB_SHIFT (0x00000010u)
5974 #define CSL_DFE_CB_CAPTURE_BUFFER_A_16MSB_REG_CAPTURE_BUFFER_A_I_16MSB_RESETVAL (0x00000000u)
5976 #define CSL_DFE_CB_CAPTURE_BUFFER_A_16MSB_REG_ADDR (0x00040000u)
5977 #define CSL_DFE_CB_CAPTURE_BUFFER_A_16MSB_REG_RESETVAL (0x00000000u)
5979 /* CAPTURE_BUFFER_B_16MSB */
5980 typedef struct
5981 {
5982 #ifdef _BIG_ENDIAN
5983 Uint32 capture_buffer_b_i_16msb : 16;
5984 Uint32 capture_buffer_b_q_16msb : 16;
5985 #else
5986 Uint32 capture_buffer_b_q_16msb : 16;
5987 Uint32 capture_buffer_b_i_16msb : 16;
5988 #endif
5989 } CSL_DFE_CB_CAPTURE_BUFFER_B_16MSB_REG;
5991 /* capture buffer B data, Q[17:2], memory is also readable when 'cba_mode' is set to 'mpu_mode' regardless 'mem_mpu_access'. */
5992 #define CSL_DFE_CB_CAPTURE_BUFFER_B_16MSB_REG_CAPTURE_BUFFER_B_Q_16MSB_MASK (0x0000FFFFu)
5993 #define CSL_DFE_CB_CAPTURE_BUFFER_B_16MSB_REG_CAPTURE_BUFFER_B_Q_16MSB_SHIFT (0x00000000u)
5994 #define CSL_DFE_CB_CAPTURE_BUFFER_B_16MSB_REG_CAPTURE_BUFFER_B_Q_16MSB_RESETVAL (0x00000000u)
5996 /* capture buffer B data, I[17:2], memory is also readable when 'cba_mode' is set to 'mpu_mode' regardless 'mem_mpu_access'. */
5997 #define CSL_DFE_CB_CAPTURE_BUFFER_B_16MSB_REG_CAPTURE_BUFFER_B_I_16MSB_MASK (0xFFFF0000u)
5998 #define CSL_DFE_CB_CAPTURE_BUFFER_B_16MSB_REG_CAPTURE_BUFFER_B_I_16MSB_SHIFT (0x00000010u)
5999 #define CSL_DFE_CB_CAPTURE_BUFFER_B_16MSB_REG_CAPTURE_BUFFER_B_I_16MSB_RESETVAL (0x00000000u)
6001 #define CSL_DFE_CB_CAPTURE_BUFFER_B_16MSB_REG_ADDR (0x00048000u)
6002 #define CSL_DFE_CB_CAPTURE_BUFFER_B_16MSB_REG_RESETVAL (0x00000000u)
6004 /* CAPTURE_BUFFER_C_16MSB */
6005 typedef struct
6006 {
6007 #ifdef _BIG_ENDIAN
6008 Uint32 capture_buffer_c_i_16msb : 16;
6009 Uint32 capture_buffer_c_q_16msb : 16;
6010 #else
6011 Uint32 capture_buffer_c_q_16msb : 16;
6012 Uint32 capture_buffer_c_i_16msb : 16;
6013 #endif
6014 } CSL_DFE_CB_CAPTURE_BUFFER_C_16MSB_REG;
6016 /* capture buffer C data, Q[17:2], memory is also readable when 'cba_mode' is set to 'mpu_mode' regardless 'mem_mpu_access'. */
6017 #define CSL_DFE_CB_CAPTURE_BUFFER_C_16MSB_REG_CAPTURE_BUFFER_C_Q_16MSB_MASK (0x0000FFFFu)
6018 #define CSL_DFE_CB_CAPTURE_BUFFER_C_16MSB_REG_CAPTURE_BUFFER_C_Q_16MSB_SHIFT (0x00000000u)
6019 #define CSL_DFE_CB_CAPTURE_BUFFER_C_16MSB_REG_CAPTURE_BUFFER_C_Q_16MSB_RESETVAL (0x00000000u)
6021 /* capture buffer C data, I[17:2], memory is also readable when 'cba_mode' is set to 'mpu_mode' regardless 'mem_mpu_access'. */
6022 #define CSL_DFE_CB_CAPTURE_BUFFER_C_16MSB_REG_CAPTURE_BUFFER_C_I_16MSB_MASK (0xFFFF0000u)
6023 #define CSL_DFE_CB_CAPTURE_BUFFER_C_16MSB_REG_CAPTURE_BUFFER_C_I_16MSB_SHIFT (0x00000010u)
6024 #define CSL_DFE_CB_CAPTURE_BUFFER_C_16MSB_REG_CAPTURE_BUFFER_C_I_16MSB_RESETVAL (0x00000000u)
6026 #define CSL_DFE_CB_CAPTURE_BUFFER_C_16MSB_REG_ADDR (0x00050000u)
6027 #define CSL_DFE_CB_CAPTURE_BUFFER_C_16MSB_REG_RESETVAL (0x00000000u)
6029 /* CAPTURE_BUFFER_D_16MSB */
6030 typedef struct
6031 {
6032 #ifdef _BIG_ENDIAN
6033 Uint32 capture_buffer_d_i_16msb : 16;
6034 Uint32 capture_buffer_d_q_16msb : 16;
6035 #else
6036 Uint32 capture_buffer_d_q_16msb : 16;
6037 Uint32 capture_buffer_d_i_16msb : 16;
6038 #endif
6039 } CSL_DFE_CB_CAPTURE_BUFFER_D_16MSB_REG;
6041 /* capture buffer D data, Q[17:2], memory is also readable when 'cba_mode' is set to 'mpu_mode' regardless 'mem_mpu_access'. */
6042 #define CSL_DFE_CB_CAPTURE_BUFFER_D_16MSB_REG_CAPTURE_BUFFER_D_Q_16MSB_MASK (0x0000FFFFu)
6043 #define CSL_DFE_CB_CAPTURE_BUFFER_D_16MSB_REG_CAPTURE_BUFFER_D_Q_16MSB_SHIFT (0x00000000u)
6044 #define CSL_DFE_CB_CAPTURE_BUFFER_D_16MSB_REG_CAPTURE_BUFFER_D_Q_16MSB_RESETVAL (0x00000000u)
6046 /* capture buffer D data, I[17:2], memory is also readable when 'cba_mode' is set to 'mpu_mode' regardless 'mem_mpu_access'. */
6047 #define CSL_DFE_CB_CAPTURE_BUFFER_D_16MSB_REG_CAPTURE_BUFFER_D_I_16MSB_MASK (0xFFFF0000u)
6048 #define CSL_DFE_CB_CAPTURE_BUFFER_D_16MSB_REG_CAPTURE_BUFFER_D_I_16MSB_SHIFT (0x00000010u)
6049 #define CSL_DFE_CB_CAPTURE_BUFFER_D_16MSB_REG_CAPTURE_BUFFER_D_I_16MSB_RESETVAL (0x00000000u)
6051 #define CSL_DFE_CB_CAPTURE_BUFFER_D_16MSB_REG_ADDR (0x00058000u)
6052 #define CSL_DFE_CB_CAPTURE_BUFFER_D_16MSB_REG_RESETVAL (0x00000000u)
6054 /* CAPTURE_BUFFER_A_2LSB */
6055 typedef struct
6056 {
6057 #ifdef _BIG_ENDIAN
6058 Uint32 rsvd1 : 14;
6059 Uint32 capture_buffer_a_i_2lsb : 2;
6060 Uint32 rsvd0 : 14;
6061 Uint32 capture_buffer_a_q_2lsb : 2;
6062 #else
6063 Uint32 capture_buffer_a_q_2lsb : 2;
6064 Uint32 rsvd0 : 14;
6065 Uint32 capture_buffer_a_i_2lsb : 2;
6066 Uint32 rsvd1 : 14;
6067 #endif
6068 } CSL_DFE_CB_CAPTURE_BUFFER_A_2LSB_REG;
6070 /* capture buffer A data, Q[1:0]. Note that when we read, we can read out Q[15:0]. */
6071 #define CSL_DFE_CB_CAPTURE_BUFFER_A_2LSB_REG_CAPTURE_BUFFER_A_Q_2LSB_MASK (0x00000003u)
6072 #define CSL_DFE_CB_CAPTURE_BUFFER_A_2LSB_REG_CAPTURE_BUFFER_A_Q_2LSB_SHIFT (0x00000000u)
6073 #define CSL_DFE_CB_CAPTURE_BUFFER_A_2LSB_REG_CAPTURE_BUFFER_A_Q_2LSB_RESETVAL (0x00000000u)
6075 /* capture buffer A data, I[1:0], Note that when we read, we can read out I[15:0]. */
6076 #define CSL_DFE_CB_CAPTURE_BUFFER_A_2LSB_REG_CAPTURE_BUFFER_A_I_2LSB_MASK (0x00030000u)
6077 #define CSL_DFE_CB_CAPTURE_BUFFER_A_2LSB_REG_CAPTURE_BUFFER_A_I_2LSB_SHIFT (0x00000010u)
6078 #define CSL_DFE_CB_CAPTURE_BUFFER_A_2LSB_REG_CAPTURE_BUFFER_A_I_2LSB_RESETVAL (0x00000000u)
6080 #define CSL_DFE_CB_CAPTURE_BUFFER_A_2LSB_REG_ADDR (0x00060000u)
6081 #define CSL_DFE_CB_CAPTURE_BUFFER_A_2LSB_REG_RESETVAL (0x00000000u)
6083 /* CAPTURE_BUFFER_B_2LSB */
6084 typedef struct
6085 {
6086 #ifdef _BIG_ENDIAN
6087 Uint32 rsvd1 : 14;
6088 Uint32 capture_buffer_b_i_2lsb : 2;
6089 Uint32 rsvd0 : 14;
6090 Uint32 capture_buffer_b_q_2lsb : 2;
6091 #else
6092 Uint32 capture_buffer_b_q_2lsb : 2;
6093 Uint32 rsvd0 : 14;
6094 Uint32 capture_buffer_b_i_2lsb : 2;
6095 Uint32 rsvd1 : 14;
6096 #endif
6097 } CSL_DFE_CB_CAPTURE_BUFFER_B_2LSB_REG;
6099 /* capture buffer B data, Q[1:0]. Note that when we read, we can read out Q[15:0]. */
6100 #define CSL_DFE_CB_CAPTURE_BUFFER_B_2LSB_REG_CAPTURE_BUFFER_B_Q_2LSB_MASK (0x00000003u)
6101 #define CSL_DFE_CB_CAPTURE_BUFFER_B_2LSB_REG_CAPTURE_BUFFER_B_Q_2LSB_SHIFT (0x00000000u)
6102 #define CSL_DFE_CB_CAPTURE_BUFFER_B_2LSB_REG_CAPTURE_BUFFER_B_Q_2LSB_RESETVAL (0x00000000u)
6104 /* capture buffer B data, I[1:0], Note that when we read, we can read out I[15:0]. */
6105 #define CSL_DFE_CB_CAPTURE_BUFFER_B_2LSB_REG_CAPTURE_BUFFER_B_I_2LSB_MASK (0x00030000u)
6106 #define CSL_DFE_CB_CAPTURE_BUFFER_B_2LSB_REG_CAPTURE_BUFFER_B_I_2LSB_SHIFT (0x00000010u)
6107 #define CSL_DFE_CB_CAPTURE_BUFFER_B_2LSB_REG_CAPTURE_BUFFER_B_I_2LSB_RESETVAL (0x00000000u)
6109 #define CSL_DFE_CB_CAPTURE_BUFFER_B_2LSB_REG_ADDR (0x00068000u)
6110 #define CSL_DFE_CB_CAPTURE_BUFFER_B_2LSB_REG_RESETVAL (0x00000000u)
6112 /* CAPTURE_BUFFER_C_2LSB */
6113 typedef struct
6114 {
6115 #ifdef _BIG_ENDIAN
6116 Uint32 rsvd1 : 14;
6117 Uint32 capture_buffer_c_i_2lsb : 2;
6118 Uint32 rsvd0 : 14;
6119 Uint32 capture_buffer_c_q_2lsb : 2;
6120 #else
6121 Uint32 capture_buffer_c_q_2lsb : 2;
6122 Uint32 rsvd0 : 14;
6123 Uint32 capture_buffer_c_i_2lsb : 2;
6124 Uint32 rsvd1 : 14;
6125 #endif
6126 } CSL_DFE_CB_CAPTURE_BUFFER_C_2LSB_REG;
6128 /* capture buffer C data, Q[1:0]. Note that when we read, we can read out Q[15:0]. */
6129 #define CSL_DFE_CB_CAPTURE_BUFFER_C_2LSB_REG_CAPTURE_BUFFER_C_Q_2LSB_MASK (0x00000003u)
6130 #define CSL_DFE_CB_CAPTURE_BUFFER_C_2LSB_REG_CAPTURE_BUFFER_C_Q_2LSB_SHIFT (0x00000000u)
6131 #define CSL_DFE_CB_CAPTURE_BUFFER_C_2LSB_REG_CAPTURE_BUFFER_C_Q_2LSB_RESETVAL (0x00000000u)
6133 /* capture buffer C data, I[1:0], Note that when we read, we can read out I[15:0]. */
6134 #define CSL_DFE_CB_CAPTURE_BUFFER_C_2LSB_REG_CAPTURE_BUFFER_C_I_2LSB_MASK (0x00030000u)
6135 #define CSL_DFE_CB_CAPTURE_BUFFER_C_2LSB_REG_CAPTURE_BUFFER_C_I_2LSB_SHIFT (0x00000010u)
6136 #define CSL_DFE_CB_CAPTURE_BUFFER_C_2LSB_REG_CAPTURE_BUFFER_C_I_2LSB_RESETVAL (0x00000000u)
6138 #define CSL_DFE_CB_CAPTURE_BUFFER_C_2LSB_REG_ADDR (0x00070000u)
6139 #define CSL_DFE_CB_CAPTURE_BUFFER_C_2LSB_REG_RESETVAL (0x00000000u)
6141 /* CAPTURE_BUFFER_D_2LSB */
6142 typedef struct
6143 {
6144 #ifdef _BIG_ENDIAN
6145 Uint32 rsvd1 : 14;
6146 Uint32 capture_buffer_d_i_2lsb : 2;
6147 Uint32 rsvd0 : 14;
6148 Uint32 capture_buffer_d_q_2lsb : 2;
6149 #else
6150 Uint32 capture_buffer_d_q_2lsb : 2;
6151 Uint32 rsvd0 : 14;
6152 Uint32 capture_buffer_d_i_2lsb : 2;
6153 Uint32 rsvd1 : 14;
6154 #endif
6155 } CSL_DFE_CB_CAPTURE_BUFFER_D_2LSB_REG;
6157 /* capture buffer D data, Q[1:0]. Note that when we read, we can read out Q[15:0]. */
6158 #define CSL_DFE_CB_CAPTURE_BUFFER_D_2LSB_REG_CAPTURE_BUFFER_D_Q_2LSB_MASK (0x00000003u)
6159 #define CSL_DFE_CB_CAPTURE_BUFFER_D_2LSB_REG_CAPTURE_BUFFER_D_Q_2LSB_SHIFT (0x00000000u)
6160 #define CSL_DFE_CB_CAPTURE_BUFFER_D_2LSB_REG_CAPTURE_BUFFER_D_Q_2LSB_RESETVAL (0x00000000u)
6162 /* capture buffer D data, I[1:0], Note that when we read, we can read out I[15:0]. */
6163 #define CSL_DFE_CB_CAPTURE_BUFFER_D_2LSB_REG_CAPTURE_BUFFER_D_I_2LSB_MASK (0x00030000u)
6164 #define CSL_DFE_CB_CAPTURE_BUFFER_D_2LSB_REG_CAPTURE_BUFFER_D_I_2LSB_SHIFT (0x00000010u)
6165 #define CSL_DFE_CB_CAPTURE_BUFFER_D_2LSB_REG_CAPTURE_BUFFER_D_I_2LSB_RESETVAL (0x00000000u)
6167 #define CSL_DFE_CB_CAPTURE_BUFFER_D_2LSB_REG_ADDR (0x00078000u)
6168 #define CSL_DFE_CB_CAPTURE_BUFFER_D_2LSB_REG_RESETVAL (0x00000000u)
6170 #endif /* __CSLR_DFE_CB_H__ */