1 /********************************************************************
2 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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32 */
33 #ifndef _CSLR_EVETPCC_H_
34 #define _CSLR_EVETPCC_H_
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40 #include <ti/csl/cslr.h>
41 #include <ti/csl/tistdtypes.h>
44 /**************************************************************************
45 * Register Overlay Structure for QRAEN
46 **************************************************************************/
47 typedef struct {
48 volatile Uint32 QRAEN[8];
49 } CSL_EvetpccQraenRegs;
52 /**************************************************************************
53 * Register Overlay Structure for CONFIG
54 **************************************************************************/
55 typedef struct {
56 volatile Uint32 QSTATN[2];
57 volatile Uint8 RSVD0[24];
58 volatile Uint32 QWMTHRA;
59 volatile Uint32 QWMTHRB;
60 volatile Uint8 RSVD1[24];
61 volatile Uint32 CCSTAT;
62 volatile Uint8 RSVD2[188];
63 volatile Uint32 AETCTL;
64 volatile Uint32 AETSTAT;
65 volatile Uint32 AETCMD;
66 volatile Uint8 RSVD3[244];
67 volatile Uint32 MPFAR;
68 volatile Uint32 MPFSR;
69 volatile Uint32 MPFCR;
70 volatile Uint32 MPPAG;
71 volatile Uint32 MPPAN[8];
72 volatile Uint8 RSVD4[2000];
73 volatile Uint32 ER;
74 volatile Uint32 ERH;
75 volatile Uint32 ECR;
76 volatile Uint32 ECRH;
77 volatile Uint32 ESR;
78 volatile Uint32 ESRH;
79 volatile Uint32 CER;
80 volatile Uint32 CERH;
81 volatile Uint32 EER;
82 volatile Uint32 EERH;
83 volatile Uint32 EECR;
84 volatile Uint32 EECRH;
85 volatile Uint32 EESR;
86 volatile Uint32 EESRH;
87 volatile Uint32 SER;
88 volatile Uint32 SERH;
89 volatile Uint32 SECR;
90 volatile Uint32 SECRH;
91 volatile Uint8 RSVD5[8];
92 volatile Uint32 IER;
93 volatile Uint32 IERH;
94 volatile Uint32 IECR;
95 volatile Uint32 IECRH;
96 volatile Uint32 IESR;
97 volatile Uint32 IESRH;
98 volatile Uint32 IPR;
99 volatile Uint32 IPRH;
100 volatile Uint32 ICR;
101 volatile Uint32 ICRH;
102 volatile Uint32 IEVAL;
103 volatile Uint8 RSVD6[4];
104 volatile Uint32 QER;
105 volatile Uint32 QEER;
106 volatile Uint32 QEECR;
107 volatile Uint32 QEESR;
108 volatile Uint32 QSER;
109 volatile Uint32 QSECR;
110 } CSL_EvetpccConfigRegs;
113 /**************************************************************************
114 * Register Overlay Structure for SHADOW_N
115 **************************************************************************/
116 typedef struct {
117 volatile Uint32 ER_RN;
118 volatile Uint32 ERH_RN;
119 volatile Uint32 ECR_RN;
120 volatile Uint32 ECRH_RN;
121 volatile Uint32 ESR_RN;
122 volatile Uint32 ESRH_RN;
123 volatile Uint32 CER_RN;
124 volatile Uint32 CERH_RN;
125 volatile Uint32 EER_RN;
126 volatile Uint32 EERH_RN;
127 volatile Uint32 EECR_RN;
128 volatile Uint32 EECRH_RN;
129 volatile Uint32 EESR_RN;
130 volatile Uint32 EESRH_RN;
131 volatile Uint32 SER_RN;
132 volatile Uint32 SERH_RN;
133 volatile Uint32 SECR_RN;
134 volatile Uint32 SECRH_RN;
135 volatile Uint8 RSVD0[8];
136 volatile Uint32 IER_RN;
137 volatile Uint32 IERH_RN;
138 volatile Uint32 IECR_RN;
139 volatile Uint32 IECRH_RN;
140 volatile Uint32 IESR_RN;
141 volatile Uint32 IESRH_RN;
142 volatile Uint32 IPR_RN;
143 volatile Uint32 IPRH_RN;
144 volatile Uint32 ICR_RN;
145 volatile Uint32 ICRH_RN;
146 volatile Uint32 IEVAL_RN;
147 volatile Uint8 RSVD1[4];
148 volatile Uint32 QER_RN;
149 volatile Uint32 QEER_RN;
150 volatile Uint32 QEECR_RN;
151 volatile Uint32 QEESR_RN;
152 volatile Uint32 QSER_RN;
153 volatile Uint32 QSECR_RN;
154 volatile Uint8 RSVD2[360];
155 } CSL_EvetpccShadow_nRegs;
158 /**************************************************************************
159 * Register Overlay Structure for PARAMSET
160 **************************************************************************/
161 typedef struct {
162 volatile Uint32 OPT;
163 volatile Uint32 SRC;
164 volatile Uint32 ABCNT;
165 volatile Uint32 DST;
166 volatile Uint32 BIDX;
167 volatile Uint32 LNK;
168 volatile Uint32 CIDX;
169 volatile Uint32 CCNT;
170 } CSL_EvetpccParamsetRegs;
173 /**************************************************************************
174 * Register Overlay Structure
175 **************************************************************************/
176 typedef struct {
177 volatile Uint32 PID;
178 volatile Uint32 CCCFG;
179 volatile Uint8 RSVD0[244];
180 volatile Uint32 CLKGDIS;
181 volatile Uint32 DCHMAPN[16];
182 volatile Uint8 RSVD1[192];
183 volatile Uint32 QCHMAPN[8];
184 volatile Uint8 RSVD2[32];
185 volatile Uint32 DMAQNUMN[2];
186 volatile Uint8 RSVD3[24];
187 volatile Uint32 QDMAQNUM;
188 volatile Uint8 RSVD4[28];
189 volatile Uint32 QUETCMAP;
190 volatile Uint32 QUEPRI;
191 volatile Uint8 RSVD5[120];
192 volatile Uint32 EMR;
193 volatile Uint32 EMRH;
194 volatile Uint32 EMCR;
195 volatile Uint32 EMCRH;
196 volatile Uint32 QEMR;
197 volatile Uint32 QEMCR;
198 volatile Uint32 CCERR;
199 volatile Uint32 CCERRCLR;
200 volatile Uint32 EEVAL;
201 volatile Uint8 RSVD6[92];
202 CSL_EvetpccQraenRegs QRAEN;
203 volatile Uint8 RSVD7[608];
204 CSL_EvetpccConfigRegs CONFIG;
205 volatile Uint8 RSVD8[3944];
206 CSL_EvetpccShadow_nRegs SHADOW_N[8];
207 volatile Uint8 RSVD9[4096];
208 CSL_EvetpccParamsetRegs PARAMSET[128];
209 } CSL_EveTpccRegs;
214 /**************************************************************************
215 * Register Macros
216 **************************************************************************/
218 /* Peripheral ID Register */
219 #define CSL_EVETPCC_PID (0x0U)
221 /* CC Configuration Register */
222 #define CSL_EVETPCC_CCCFG (0x4U)
224 /* Auto Clock Gate Disable */
225 #define CSL_EVETPCC_CLKGDIS (0xFCU)
227 /* DMA Channel N Mapping Register */
228 #define CSL_EVETPCC_DCHMAPN(i) (0x100U + ((i) * (0x4U)))
230 /* QDMA Channel N Mapping Register */
231 #define CSL_EVETPCC_QCHMAPN(i) (0x200U + ((i) * (0x4U)))
233 /* DMA Queue Number Register n Contains the Event queue number to be used for
234 * the corresponding DMA Channel. */
235 #define CSL_EVETPCC_DMAQNUMN(i) (0x240U + ((i) * (0x4U)))
237 /* QDMA Queue Number Register Contains the Event queue number to be used for
238 * the corresponding QDMA Channel. */
239 #define CSL_EVETPCC_QDMAQNUM (0x260U)
241 /* Queue to TC Mapping */
242 #define CSL_EVETPCC_QUETCMAP (0x280U)
244 /* Queue Priority */
245 #define CSL_EVETPCC_QUEPRI (0x284U)
247 /* Event Missed Register: The Event Missed register is set if 2 events are
248 * received without the first event being cleared or if a Null TR is serviced.
249 * Chained events (CER), Set Events (ESR), and normal events (ER) are treated
250 * individually. If any bit in the EMR register is set (and all errors
251 * (including QEMR/CCERR) were previously clear), then an error will be
252 * signaled with TPCC error interrupt. */
253 #define CSL_EVETPCC_EMR (0x300U)
255 /* Event Missed Register (High Part): The Event Missed register is set if 2
256 * events are received without the first event being cleared or if a Null TR
257 * is serviced. Chained events (CER), Set Events (ESR), and normal events (ER)
258 * are treated individually. If any bit in the EMR register is set (and all
259 * errors (including QEMR/CCERR) were previously clear), then an error will be
260 * signaled with TPCC error interrupt. */
261 #define CSL_EVETPCC_EMRH (0x304U)
263 /* Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the
264 * EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits
265 * must be cleared before additional error interrupts will be asserted by CC. */
266 #define CSL_EVETPCC_EMCR (0x308U)
268 /* Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En
269 * bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect..
270 * All error bits must be cleared before additional error interrupts will be
271 * asserted by CC. */
272 #define CSL_EVETPCC_EMCRH (0x30CU)
274 /* QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA
275 * events are detected without the first event being cleared or if a Null TR
276 * is serviced.. If any bit in the QEMR register is set (and all errors
277 * (including EMR/CCERR) were previously clear), then an error will be
278 * signaled with TPCC error interrupt. */
279 #define CSL_EVETPCC_QEMR (0x310U)
281 /* QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit
282 * causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All
283 * error bits must be cleared before additional error interrupts will be
284 * asserted by CC. */
285 #define CSL_EVETPCC_QEMCR (0x314U)
287 /* CC Error Register */
288 #define CSL_EVETPCC_CCERR (0x318U)
290 /* CC Error Clear Register */
291 #define CSL_EVETPCC_CCERRCLR (0x31CU)
293 /* Error Eval Register */
294 #define CSL_EVETPCC_EEVAL (0x320U)
296 /* QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via
297 * Region M address space to Bit N in any QDMA Channel Register are not
298 * allowed. Reads will return 'b0 on Bit N and writes will not modify the
299 * state of bit N. Enabled interrupt bits for bit N do not contribute to the
300 * generation of the TPCC region M interrupt. En = 1 : Accesses via Region M
301 * address space to Bit N in any QDMA Channel Register are allowed. Reads will
302 * return the value from Bit N and writes will modify the state of bit N.
303 * Enabled interrupt bits for bit N do contribute to the generation of the
304 * TPCC region n interrupt. */
305 #define CSL_EVETPCC_QRAEN(i) (0x380U + ((i) * (0x4U)))
307 /* QSTATn Register Set */
308 #define CSL_EVETPCC_QSTATN(i) (0x600U + ((i) * (0x4U)))
310 /* Queue Threshold A, for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit
311 * is set when the number of Events in QueueN at an instant in time (visible
312 * via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn.
313 * Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11
314 * disables threshold errors. */
315 #define CSL_EVETPCC_QWMTHRA (0x620U)
317 /* Queue Threshold B, for Q[7:4]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit
318 * is set when the number of Events in QueueN at an instant in time (visible
319 * via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn.
320 * Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11
321 * disables threshold errors. */
322 #define CSL_EVETPCC_QWMTHRB (0x624U)
324 /* CC Status Register */
325 #define CSL_EVETPCC_CCSTAT (0x640U)
327 /* Advanced Event Trigger Control */
328 #define CSL_EVETPCC_AETCTL (0x700U)
330 /* Advanced Event Trigger Stat */
331 #define CSL_EVETPCC_AETSTAT (0x704U)
333 /* AET Command */
334 #define CSL_EVETPCC_AETCMD (0x708U)
336 /* Memory Protection Fault Address */
337 #define CSL_EVETPCC_MPFAR (0x800U)
339 /* Memory Protection Fault Status Register */
340 #define CSL_EVETPCC_MPFSR (0x804U)
342 /* Memory Protection Fault Command Register */
343 #define CSL_EVETPCC_MPFCR (0x808U)
345 /* Memory Protection Page Attribute for Global registers */
346 #define CSL_EVETPCC_MPPAG (0x80CU)
348 /* MP Permission Attribute for DMA Region n */
349 #define CSL_EVETPCC_MPPAN(i) (0x810U + ((i) * (0x4U)))
351 /* Event Register: If ER.En bit is set and the EER.En bit is also set, then
352 * the corresponding DMA channel is prioritized vs. other pending DMA events
353 * for submission to the TC. ER.En bit is set when the input event #n
354 * transitions from inactive (low) to active (high), regardless of the state
355 * of EER.En bit. ER.En bit is cleared when the corresponding event is
356 * prioritized and serviced. If the ER.En bit is already set and a new
357 * inactive to active transition is detected on the input event #n input AND
358 * the corresponding bit in the EER register is set, then the corresponding
359 * bit in the Event Missed Register is set. Event N can be cleared via sw by
360 * writing a '1' to the ECR pseudo-register. */
361 #define CSL_EVETPCC_ER (0x1000U)
363 /* Event Register (High Part): If ERH.En bit is set and the EERH.En bit is
364 * also set, then the corresponding DMA channel is prioritized vs. other
365 * pending DMA events for submission to the TC. ERH.En bit is set when the
366 * input event #n transitions from inactive (low) to active (high), regardless
367 * of the state of EERH.En bit. ER.En bit is cleared when the corresponding
368 * event is prioritized and serviced. If the ERH.En bit is already set and a
369 * new inactive to active transition is detected on the input event #n input
370 * AND the corresponding bit in the EERH register is set, then the
371 * corresponding bit in the Event Missed Register is set. Event N can be
372 * cleared via sw by writing a '1' to the ECRH pseudo-register. */
373 #define CSL_EVETPCC_ERH (0x1004U)
375 /* Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En
376 * bit to be cleared. CPU write of '0' has no effect. */
377 #define CSL_EVETPCC_ECR (0x1008U)
379 /* Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit
380 * causes the ERH.En bit to be cleared. CPU write of '0' has no effect. */
381 #define CSL_EVETPCC_ECRH (0x100CU)
383 /* Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit
384 * to be set. CPU write of '0' has no effect. */
385 #define CSL_EVETPCC_ESR (0x1010U)
387 /* Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes
388 * the ERH.En bit to be set. CPU write of '0' has no effect. */
389 #define CSL_EVETPCC_ESRH (0x1014U)
391 /* Chained Event Register: If CER.En bit is set (regardless of state of
392 * EER.En), then the corresponding DMA channel is prioritized vs. other
393 * pending DMA events for submission to the TC. CER.En bit is set when a
394 * chaining completion code is returned from one of the 3PTCs via the
395 * completion interface, or is generated internally via Early Completion path.
396 * CER.En bit is cleared when the corresponding event is prioritized and
397 * serviced. If the CER.En bit is already set and the corresponding chaining
398 * completion code is returned from the TC, then the corresponding bit in the
399 * Event Missed Register is set. CER.En cannot be set or cleared via software. */
400 #define CSL_EVETPCC_CER (0x1018U)
402 /* Chained Event Register (High Part): If CERH.En bit is set (regardless of
403 * state of EERH.En), then the corresponding DMA channel is prioritized vs.
404 * other pending DMA events for submission to the TC. CERH.En bit is set when
405 * a chaining completion code is returned from one of the 3PTCs via the
406 * completion interface, or is generated internally via Early Completion path.
407 * CERH.En bit is cleared when the corresponding event is prioritized and
408 * serviced. If the CERH.En bit is already set and the corresponding chaining
409 * completion code is returned from the TC, then the corresponding bit in the
410 * Event Missed Register is set. CERH.En cannot be set or cleared via
411 * software. */
412 #define CSL_EVETPCC_CERH (0x101CU)
414 /* Event Enable Register: Enables DMA transfers for ER.En pending events.
415 * ER.En is set based on externally asserted events (via tpcc_eventN_pi). This
416 * register has no effect on Chained Event Register (CER) or Event Set
417 * Register (ESR). Note that if a bit is set in ER.En while EER.En is
418 * disabled, no action is taken. If EER.En is enabled at a later point (and
419 * ER.En has not been cleared via SW) then the event will be recognized as a
420 * valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via
421 * writes to EESR and can be disabled via writes to EECR register. EER.En = 0:
422 * ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled
423 * to trigger DMA transfers. */
424 #define CSL_EVETPCC_EER (0x1020U)
426 /* Event Enable Register (High Part): Enables DMA transfers for ERH.En pending
427 * events. ERH.En is set based on externally asserted events (via
428 * tpcc_eventN_pi). This register has no effect on Chained Event Register
429 * (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En
430 * while EERH.En is disabled, no action is taken. If EERH.En is enabled at a
431 * later point (and ERH.En has not been cleared via SW) then the event will be
432 * recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events
433 * can be enabled via writes to EESRH and can be disabled via writes to EECRH
434 * register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers.
435 * EERH.En = 1: ER.En is enabled to trigger DMA transfers. */
436 #define CSL_EVETPCC_EERH (0x1024U)
438 /* Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the
439 * EER.En bit to be cleared. CPU write of '0' has no effect.. */
440 #define CSL_EVETPCC_EECR (0x1028U)
442 /* Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En
443 * bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.. */
444 #define CSL_EVETPCC_EECRH (0x102CU)
446 /* Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the
447 * EER.En bit to be set. CPU write of '0' has no effect.. */
448 #define CSL_EVETPCC_EESR (0x1030U)
450 /* Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit
451 * causes the EERH.En bit to be set. CPU write of '0' has no effect.. */
452 #define CSL_EVETPCC_EESRH (0x1034U)
454 /* Secondary Event Register: The secondary event register is used along with
455 * the Event Register (ER) to provide information on the state of an Event. En
456 * = 0 : Event is not currently in the Event Queue. En = 1 : Event is
457 * currently stored in Event Queue. Event arbiter will not prioritize
458 * additional events. */
459 #define CSL_EVETPCC_SER (0x1038U)
461 /* Secondary Event Register (High Part): The secondary event register is used
462 * along with the Event Register (ERH) to provide information on the state of
463 * an Event. En = 0 : Event is not currently in the Event Queue. En = 1 :
464 * Event is currently stored in Event Queue. Event arbiter will not prioritize
465 * additional events. */
466 #define CSL_EVETPCC_SERH (0x103CU)
468 /* Secondary Event Clear Register: The secondary event clear register is used
469 * to clear the status of the SER registers. CPU write of '1' to the SECR.En
470 * bit clears the SER register. CPU write of '0' has no effect. */
471 #define CSL_EVETPCC_SECR (0x1040U)
473 /* Secondary Event Clear Register (High Part): The secondary event clear
474 * register is used to clear the status of the SERH registers. CPU write of
475 * '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no
476 * effect. */
477 #define CSL_EVETPCC_SECRH (0x1044U)
479 /* Int Enable Register: IER.In is not directly writeable. Interrupts can be
480 * enabled via writes to IESR and can be disabled via writes to IECR register.
481 * IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS
482 * enabled for interrupts. */
483 #define CSL_EVETPCC_IER (0x1050U)
485 /* Int Enable Register (High Part): IERH.In is not directly writeable.
486 * Interrupts can be enabled via writes to IESRH and can be disabled via
487 * writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for
488 * interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts. */
489 #define CSL_EVETPCC_IERH (0x1054U)
491 /* Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the
492 * IER.In bit to be cleared. CPU write of '0' has no effect.. */
493 #define CSL_EVETPCC_IECR (0x1058U)
495 /* Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit
496 * causes the IERH.In bit to be cleared. CPU write of '0' has no effect.. */
497 #define CSL_EVETPCC_IECRH (0x105CU)
499 /* Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the
500 * IESR.In bit to be set. CPU write of '0' has no effect.. */
501 #define CSL_EVETPCC_IESR (0x1060U)
503 /* Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit
504 * causes the IESRH.In bit to be set. CPU write of '0' has no effect.. */
505 #define CSL_EVETPCC_IESRH (0x1064U)
507 /* Interrupt Pending Register: IPR.In bit is set when a interrupt completion
508 * code with TCC of N is detected. IPR.In bit is cleared via software by
509 * writing a '1' to ICR.In bit. */
510 #define CSL_EVETPCC_IPR (0x1068U)
512 /* Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt
513 * completion code with TCC of N is detected. IPRH.In bit is cleared via
514 * software by writing a '1' to ICRH.In bit. */
515 #define CSL_EVETPCC_IPRH (0x106CU)
517 /* Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the
518 * IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits
519 * must be cleared before additional interrupts will be asserted by CC. */
520 #define CSL_EVETPCC_ICR (0x1070U)
522 /* Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit
523 * causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All
524 * IPRH.In bits must be cleared before additional interrupts will be asserted
525 * by CC. */
526 #define CSL_EVETPCC_ICRH (0x1074U)
528 /* Interrupt Eval Register */
529 #define CSL_EVETPCC_IEVAL (0x1078U)
531 /* QDMA Event Register: If QER.En bit is set, then the corresponding QDMA
532 * channel is prioritized vs. other qdma events for submission to the TC.
533 * QER.En bit is set when a vbus write byte matches the address defined in the
534 * QCHMAPn register. QER.En bit is cleared when the corresponding event is
535 * prioritized and serviced. QER.En is also cleared when user writes a '1' to
536 * the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is
537 * detected due to user write to QDMA trigger location and QEER register is
538 * set, then the corresponding bit in the QDMA Event Missed Register is set. */
539 #define CSL_EVETPCC_QER (0x1080U)
541 /* QDMA Event Enable Register: Enabled/disabled QDMA address comparator for
542 * QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be
543 * enabled via writes to QEESR and can be disabled via writes to QEECR
544 * register. QEER.En = 1, The corresponding QDMA channel comparator is enabled
545 * and Events will be recognized and latched in QER.En. QEER.En = 0, The
546 * corresponding QDMA channel comparator is disabled. Events will not be
547 * recognized/latched in QER.En. */
548 #define CSL_EVETPCC_QEER (0x1084U)
550 /* QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit
551 * causes the QEER.En bit to be cleared. CPU write of '0' has no effect.. */
552 #define CSL_EVETPCC_QEECR (0x1088U)
554 /* QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes
555 * the QEESR.En bit to be set. CPU write of '0' has no effect.. */
556 #define CSL_EVETPCC_QEESR (0x108CU)
558 /* QDMA Secondary Event Register: The QDMA secondary event register is used
559 * along with the QDMA Event Register (QER) to provide information on the
560 * state of a QDMA Event. En = 0 : Event is not currently in the Event Queue.
561 * En = 1 : Event is currently stored in Event Queue. Event arbiter will not
562 * prioritize additional events. */
563 #define CSL_EVETPCC_QSER (0x1090U)
565 /* QDMA Secondary Event Clear Register: The secondary event clear register is
566 * used to clear the status of the QSER and QER register (note that this is
567 * slightly different than the SER operation, which does not clear the ER.En
568 * register). CPU write of '1' to the QSECR.En bit clears the QSER.En and
569 * QER.En register fields. CPU write of '0' has no effect.. */
570 #define CSL_EVETPCC_QSECR (0x1094U)
572 /* Interrupt Eval Register */
573 #define CSL_EVETPCC_IEVAL_RN(n) (0x2078U + ((n) * (0x200U)))
575 /* Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit
576 * causes the IESRH.In bit to be set. CPU write of '0' has no effect.. */
577 #define CSL_EVETPCC_IESRH_RN(n) (0x2064U + ((n) * (0x200U)))
579 /* Secondary Event Register: The secondary event register is used along with
580 * the Event Register (ER) to provide information on the state of an Event. En
581 * = 0 : Event is not currently in the Event Queue. En = 1 : Event is
582 * currently stored in Event Queue. Event arbiter will not prioritize
583 * additional events. */
584 #define CSL_EVETPCC_SER_RN(n) (0x2038U + ((n) * (0x200U)))
586 /* Secondary Event Register (High Part): The secondary event register is used
587 * along with the Event Register (ERH) to provide information on the state of
588 * an Event. En = 0 : Event is not currently in the Event Queue. En = 1 :
589 * Event is currently stored in Event Queue. Event arbiter will not prioritize
590 * additional events. */
591 #define CSL_EVETPCC_SERH_RN(n) (0x203CU + ((n) * (0x200U)))
593 /* Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit
594 * to be set. CPU write of '0' has no effect. */
595 #define CSL_EVETPCC_ESR_RN(n) (0x2010U + ((n) * (0x200U)))
597 /* Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the
598 * EER.En bit to be cleared. CPU write of '0' has no effect.. */
599 #define CSL_EVETPCC_EECR_RN(n) (0x2028U + ((n) * (0x200U)))
601 /* Event Register: If ER.En bit is set and the EER.En bit is also set, then
602 * the corresponding DMA channel is prioritized vs. other pending DMA events
603 * for submission to the TC. ER.En bit is set when the input event #n
604 * transitions from inactive (low) to active (high), regardless of the state
605 * of EER.En bit. ER.En bit is cleared when the corresponding event is
606 * prioritized and serviced. If the ER.En bit is already set and a new
607 * inactive to active transition is detected on the input event #n input AND
608 * the corresponding bit in the EER register is set, then the corresponding
609 * bit in the Event Missed Register is set. Event N can be cleared via sw by
610 * writing a '1' to the ECR pseudo-register. */
611 #define CSL_EVETPCC_ER_RN(n) (0x2000U + ((n) * (0x200U)))
613 /* Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit
614 * causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All
615 * IPRH.In bits must be cleared before additional interrupts will be asserted
616 * by CC. */
617 #define CSL_EVETPCC_ICRH_RN(n) (0x2074U + ((n) * (0x200U)))
619 /* Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En
620 * bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.. */
621 #define CSL_EVETPCC_EECRH_RN(n) (0x202CU + ((n) * (0x200U)))
623 /* Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the
624 * IESR.In bit to be set. CPU write of '0' has no effect.. */
625 #define CSL_EVETPCC_IESR_RN(n) (0x2060U + ((n) * (0x200U)))
627 /* Secondary Event Clear Register: The secondary event clear register is used
628 * to clear the status of the SER registers. CPU write of '1' to the SECR.En
629 * bit clears the SER register. CPU write of '0' has no effect. */
630 #define CSL_EVETPCC_SECR_RN(n) (0x2040U + ((n) * (0x200U)))
632 /* Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the
633 * EER.En bit to be set. CPU write of '0' has no effect.. */
634 #define CSL_EVETPCC_EESR_RN(n) (0x2030U + ((n) * (0x200U)))
636 /* QDMA Event Register: If QER.En bit is set, then the corresponding QDMA
637 * channel is prioritized vs. other qdma events for submission to the TC.
638 * QER.En bit is set when a vbus write byte matches the address defined in the
639 * QCHMAPn register. QER.En bit is cleared when the corresponding event is
640 * prioritized and serviced. QER.En is also cleared when user writes a '1' to
641 * the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is
642 * detected due to user write to QDMA trigger location and QEER register is
643 * set, then the corresponding bit in the QDMA Event Missed Register is set. */
644 #define CSL_EVETPCC_QER_RN(n) (0x2080U + ((n) * (0x200U)))
646 /* Secondary Event Clear Register (High Part): The secondary event clear
647 * register is used to clear the status of the SERH registers. CPU write of
648 * '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no
649 * effect. */
650 #define CSL_EVETPCC_SECRH_RN(n) (0x2044U + ((n) * (0x200U)))
652 /* Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit
653 * causes the EERH.En bit to be set. CPU write of '0' has no effect.. */
654 #define CSL_EVETPCC_EESRH_RN(n) (0x2034U + ((n) * (0x200U)))
656 /* Int Enable Register: IER.In is not directly writeable. Interrupts can be
657 * enabled via writes to IESR and can be disabled via writes to IECR register.
658 * IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS
659 * enabled for interrupts. */
660 #define CSL_EVETPCC_IER_RN(n) (0x2050U + ((n) * (0x200U)))
662 /* QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit
663 * causes the QEER.En bit to be cleared. CPU write of '0' has no effect.. */
664 #define CSL_EVETPCC_QEECR_RN(n) (0x2088U + ((n) * (0x200U)))
666 /* Event Enable Register: Enables DMA transfers for ER.En pending events.
667 * ER.En is set based on externally asserted events (via tpcc_eventN_pi). This
668 * register has no effect on Chained Event Register (CER) or Event Set
669 * Register (ESR). Note that if a bit is set in ER.En while EER.En is
670 * disabled, no action is taken. If EER.En is enabled at a later point (and
671 * ER.En has not been cleared via SW) then the event will be recognized as a
672 * valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via
673 * writes to EESR and can be disabled via writes to EECR register. EER.En = 0:
674 * ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled
675 * to trigger DMA transfers. */
676 #define CSL_EVETPCC_EER_RN(n) (0x2020U + ((n) * (0x200U)))
678 /* Chained Event Register (High Part): If CERH.En bit is set (regardless of
679 * state of EERH.En), then the corresponding DMA channel is prioritized vs.
680 * other pending DMA events for submission to the TC. CERH.En bit is set when
681 * a chaining completion code is returned from one of the 3PTCs via the
682 * completion interface, or is generated internally via Early Completion path.
683 * CERH.En bit is cleared when the corresponding event is prioritized and
684 * serviced. If the CERH.En bit is already set and the corresponding chaining
685 * completion code is returned from the TC, then the corresponding bit in the
686 * Event Missed Register is set. CERH.En cannot be set or cleared via
687 * software. */
688 #define CSL_EVETPCC_CERH_RN(n) (0x201CU + ((n) * (0x200U)))
690 /* QDMA Event Enable Register: Enabled/disabled QDMA address comparator for
691 * QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be
692 * enabled via writes to QEESR and can be disabled via writes to QEECR
693 * register. QEER.En = 1, The corresponding QDMA channel comparator is enabled
694 * and Events will be recognized and latched in QER.En. QEER.En = 0, The
695 * corresponding QDMA channel comparator is disabled. Events will not be
696 * recognized/latched in QER.En. */
697 #define CSL_EVETPCC_QEER_RN(n) (0x2084U + ((n) * (0x200U)))
699 /* QDMA Secondary Event Clear Register: The secondary event clear register is
700 * used to clear the status of the QSER and QER register (note that this is
701 * slightly different than the SER operation, which does not clear the ER.En
702 * register). CPU write of '1' to the QSECR.En bit clears the QSER.En and
703 * QER.En register fields. CPU write of '0' has no effect.. */
704 #define CSL_EVETPCC_QSECR_RN(n) (0x2094U + ((n) * (0x200U)))
706 /* Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit
707 * causes the ERH.En bit to be cleared. CPU write of '0' has no effect. */
708 #define CSL_EVETPCC_ECRH_RN(n) (0x200CU + ((n) * (0x200U)))
710 /* Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the
711 * IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits
712 * must be cleared before additional interrupts will be asserted by CC. */
713 #define CSL_EVETPCC_ICR_RN(n) (0x2070U + ((n) * (0x200U)))
715 /* Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt
716 * completion code with TCC of N is detected. IPRH.In bit is cleared via
717 * software by writing a '1' to ICRH.In bit. */
718 #define CSL_EVETPCC_IPRH_RN(n) (0x206CU + ((n) * (0x200U)))
720 /* Chained Event Register: If CER.En bit is set (regardless of state of
721 * EER.En), then the corresponding DMA channel is prioritized vs. other
722 * pending DMA events for submission to the TC. CER.En bit is set when a
723 * chaining completion code is returned from one of the 3PTCs via the
724 * completion interface, or is generated internally via Early Completion path.
725 * CER.En bit is cleared when the corresponding event is prioritized and
726 * serviced. If the CER.En bit is already set and the corresponding chaining
727 * completion code is returned from the TC, then the corresponding bit in the
728 * Event Missed Register is set. CER.En cannot be set or cleared via software. */
729 #define CSL_EVETPCC_CER_RN(n) (0x2018U + ((n) * (0x200U)))
731 /* Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit
732 * causes the IERH.In bit to be cleared. CPU write of '0' has no effect.. */
733 #define CSL_EVETPCC_IECRH_RN(n) (0x205CU + ((n) * (0x200U)))
735 /* Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the
736 * IER.In bit to be cleared. CPU write of '0' has no effect.. */
737 #define CSL_EVETPCC_IECR_RN(n) (0x2058U + ((n) * (0x200U)))
739 /* QDMA Secondary Event Register: The QDMA secondary event register is used
740 * along with the QDMA Event Register (QER) to provide information on the
741 * state of a QDMA Event. En = 0 : Event is not currently in the Event Queue.
742 * En = 1 : Event is currently stored in Event Queue. Event arbiter will not
743 * prioritize additional events. */
744 #define CSL_EVETPCC_QSER_RN(n) (0x2090U + ((n) * (0x200U)))
746 /* Int Enable Register (High Part): IERH.In is not directly writeable.
747 * Interrupts can be enabled via writes to IESRH and can be disabled via
748 * writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for
749 * interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts. */
750 #define CSL_EVETPCC_IERH_RN(n) (0x2054U + ((n) * (0x200U)))
752 /* Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En
753 * bit to be cleared. CPU write of '0' has no effect. */
754 #define CSL_EVETPCC_ECR_RN(n) (0x2008U + ((n) * (0x200U)))
756 /* Event Enable Register (High Part): Enables DMA transfers for ERH.En pending
757 * events. ERH.En is set based on externally asserted events (via
758 * tpcc_eventN_pi). This register has no effect on Chained Event Register
759 * (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En
760 * while EERH.En is disabled, no action is taken. If EERH.En is enabled at a
761 * later point (and ERH.En has not been cleared via SW) then the event will be
762 * recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events
763 * can be enabled via writes to EESRH and can be disabled via writes to EECRH
764 * register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers.
765 * EERH.En = 1: ER.En is enabled to trigger DMA transfers. */
766 #define CSL_EVETPCC_EERH_RN(n) (0x2024U + ((n) * (0x200U)))
768 /* Interrupt Pending Register: IPR.In bit is set when a interrupt completion
769 * code with TCC of N is detected. IPR.In bit is cleared via software by
770 * writing a '1' to ICR.In bit. */
771 #define CSL_EVETPCC_IPR_RN(n) (0x2068U + ((n) * (0x200U)))
773 /* Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes
774 * the ERH.En bit to be set. CPU write of '0' has no effect. */
775 #define CSL_EVETPCC_ESRH_RN(n) (0x2014U + ((n) * (0x200U)))
777 /* QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes
778 * the QEESR.En bit to be set. CPU write of '0' has no effect.. */
779 #define CSL_EVETPCC_QEESR_RN(n) (0x208CU + ((n) * (0x200U)))
781 /* Event Register (High Part): If ERH.En bit is set and the EERH.En bit is
782 * also set, then the corresponding DMA channel is prioritized vs. other
783 * pending DMA events for submission to the TC. ERH.En bit is set when the
784 * input event #n transitions from inactive (low) to active (high), regardless
785 * of the state of EERH.En bit. ER.En bit is cleared when the corresponding
786 * event is prioritized and serviced. If the ERH.En bit is already set and a
787 * new inactive to active transition is detected on the input event #n input
788 * AND the corresponding bit in the EERH register is set, then the
789 * corresponding bit in the Event Missed Register is set. Event N can be
790 * cleared via sw by writing a '1' to the ECRH pseudo-register. */
791 #define CSL_EVETPCC_ERH_RN(n) (0x2004U + ((n) * (0x200U)))
793 /* Options Parameter */
794 #define CSL_EVETPCC_OPT(n) (0x4000U + ((n) * (0x20U)))
796 /* Source Address */
797 #define CSL_EVETPCC_SRC(n) (0x4004U + ((n) * (0x20U)))
799 /* A and B byte count */
800 #define CSL_EVETPCC_ABCNT(n) (0x4008U + ((n) * (0x20U)))
802 /* BIDX */
803 #define CSL_EVETPCC_BIDX(n) (0x4010U + ((n) * (0x20U)))
805 /* Link and Reload parameters */
806 #define CSL_EVETPCC_LNK(n) (0x4014U + ((n) * (0x20U)))
808 /* CIDX */
809 #define CSL_EVETPCC_CIDX(n) (0x4018U + ((n) * (0x20U)))
811 /* C byte count */
812 #define CSL_EVETPCC_CCNT(n) (0x401CU + ((n) * (0x20U)))
814 /* Destination Address */
815 #define CSL_EVETPCC_DST(n) (0x400CU + ((n) * (0x20U)))
818 /**************************************************************************
819 * Field Definition Macros
820 **************************************************************************/
822 /* PID */
824 #define CSL_EVETPCC_PID_MINOR_MASK (0x0000003FU)
825 #define CSL_EVETPCC_PID_MINOR_SHIFT (0U)
826 #define CSL_EVETPCC_PID_MINOR_RESETVAL (0x00000000U)
827 #define CSL_EVETPCC_PID_MINOR_MAX (0x0000003fU)
829 #define CSL_EVETPCC_PID_CUSTOM_MASK (0x000000C0U)
830 #define CSL_EVETPCC_PID_CUSTOM_SHIFT (6U)
831 #define CSL_EVETPCC_PID_CUSTOM_RESETVAL (0x00000000U)
832 #define CSL_EVETPCC_PID_CUSTOM_MAX (0x00000003U)
834 #define CSL_EVETPCC_PID_MAJOR_MASK (0x00000700U)
835 #define CSL_EVETPCC_PID_MAJOR_SHIFT (8U)
836 #define CSL_EVETPCC_PID_MAJOR_RESETVAL (0x00000003U)
837 #define CSL_EVETPCC_PID_MAJOR_MAX (0x00000007U)
839 #define CSL_EVETPCC_PID_RTL_MASK (0x0000F800U)
840 #define CSL_EVETPCC_PID_RTL_SHIFT (11U)
841 #define CSL_EVETPCC_PID_RTL_RESETVAL (0x00000000U)
842 #define CSL_EVETPCC_PID_RTL_MAX (0x0000001fU)
844 #define CSL_EVETPCC_PID_FUNC_MASK (0x0FFF0000U)
845 #define CSL_EVETPCC_PID_FUNC_SHIFT (16U)
846 #define CSL_EVETPCC_PID_FUNC_RESETVAL (0x00000001U)
847 #define CSL_EVETPCC_PID_FUNC_MAX (0x00000fffU)
849 #define CSL_EVETPCC_PID_SCHEME_MASK (0xC0000000U)
850 #define CSL_EVETPCC_PID_SCHEME_SHIFT (30U)
851 #define CSL_EVETPCC_PID_SCHEME_RESETVAL (0x00000001U)
852 #define CSL_EVETPCC_PID_SCHEME_MAX (0x00000003U)
854 #define CSL_EVETPCC_PID_RESETVAL (0x40010300U)
856 /* CCCFG */
858 #define CSL_EVETPCC_CCCFG_NUMTC_MASK (0x00070000U)
859 #define CSL_EVETPCC_CCCFG_NUMTC_SHIFT (16U)
860 #define CSL_EVETPCC_CCCFG_NUMTC_RESETVAL (0x00000001U)
861 #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC7 (0x00000006U)
862 #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC4 (0x00000003U)
863 #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC1 (0x00000000U)
864 #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC6 (0x00000005U)
865 #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC8 (0x00000007U)
866 #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC5 (0x00000004U)
867 #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC3 (0x00000002U)
868 #define CSL_EVETPCC_CCCFG_NUMTC_NUMTC2 (0x00000001U)
870 #define CSL_EVETPCC_CCCFG_NUMREGN_MASK (0x00300000U)
871 #define CSL_EVETPCC_CCCFG_NUMREGN_SHIFT (20U)
872 #define CSL_EVETPCC_CCCFG_NUMREGN_RESETVAL (0x00000003U)
873 #define CSL_EVETPCC_CCCFG_NUMREGN_NUMREG4 (0x00000002U)
874 #define CSL_EVETPCC_CCCFG_NUMREGN_NUMREG8 (0x00000003U)
875 #define CSL_EVETPCC_CCCFG_NUMREGN_NUMREG0 (0x00000000U)
876 #define CSL_EVETPCC_CCCFG_NUMREGN_NUMREG2 (0x00000001U)
878 #define CSL_EVETPCC_CCCFG_NUMINTCH_MASK (0x00000700U)
879 #define CSL_EVETPCC_CCCFG_NUMINTCH_SHIFT (8U)
880 #define CSL_EVETPCC_CCCFG_NUMINTCH_RESETVAL (0x00000004U)
881 #define CSL_EVETPCC_CCCFG_NUMINTCH_NUMINTCH32 (0x00000003U)
882 #define CSL_EVETPCC_CCCFG_NUMINTCH_NUMINTCH64 (0x00000004U)
883 #define CSL_EVETPCC_CCCFG_NUMINTCH_NUMINTCH16 (0x00000002U)
884 #define CSL_EVETPCC_CCCFG_NUMINTCH_NUMINTCH8 (0x00000001U)
886 #define CSL_EVETPCC_CCCFG_NUMPAENTRY_MASK (0x00007000U)
887 #define CSL_EVETPCC_CCCFG_NUMPAENTRY_SHIFT (12U)
888 #define CSL_EVETPCC_CCCFG_NUMPAENTRY_RESETVAL (0x00000003U)
889 #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES16 (0x00000000U)
890 #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES32 (0x00000001U)
891 #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES64 (0x00000002U)
892 #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES128 (0x00000003U)
893 #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES256 (0x00000004U)
894 #define CSL_EVETPCC_CCCFG_NUMPAENTRY_NUMPARAMENTRIES512 (0x00000005U)
896 #define CSL_EVETPCC_CCCFG_CHMAPEXIST_MASK (0x01000000U)
897 #define CSL_EVETPCC_CCCFG_CHMAPEXIST_SHIFT (24U)
898 #define CSL_EVETPCC_CCCFG_CHMAPEXIST_RESETVAL (0x00000001U)
899 #define CSL_EVETPCC_CCCFG_CHMAPEXIST_MAX (0x00000001U)
901 #define CSL_EVETPCC_CCCFG_MPEXIST_MASK (0x02000000U)
902 #define CSL_EVETPCC_CCCFG_MPEXIST_SHIFT (25U)
903 #define CSL_EVETPCC_CCCFG_MPEXIST_RESETVAL (0x00000001U)
904 #define CSL_EVETPCC_CCCFG_MPEXIST_MAX (0x00000001U)
906 #define CSL_EVETPCC_CCCFG_NUMDMACH_MASK (0x00000007U)
907 #define CSL_EVETPCC_CCCFG_NUMDMACH_SHIFT (0U)
908 #define CSL_EVETPCC_CCCFG_NUMDMACH_RESETVAL (0x00000005U)
909 #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH4 (0x00000001U)
910 #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH32 (0x00000004U)
911 #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH8 (0x00000002U)
912 #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH64 (0x00000005U)
913 #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH16 (0x00000003U)
914 #define CSL_EVETPCC_CCCFG_NUMDMACH_NUMDMACH0 (0x00000000U)
916 #define CSL_EVETPCC_CCCFG_NUMQDMACH_MASK (0x00000070U)
917 #define CSL_EVETPCC_CCCFG_NUMQDMACH_SHIFT (4U)
918 #define CSL_EVETPCC_CCCFG_NUMQDMACH_RESETVAL (0x00000004U)
919 #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH4 (0x00000002U)
920 #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH8 (0x00000004U)
921 #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH6 (0x00000003U)
922 #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH0 (0x00000000U)
923 #define CSL_EVETPCC_CCCFG_NUMQDMACH_NUMQDMACH2 (0x00000001U)
925 #define CSL_EVETPCC_CCCFG_RESETVAL (0x03313445U)
927 /* CLKGDIS */
929 #define CSL_EVETPCC_CLKGDIS_CLKGDIS_MASK (0x00000001U)
930 #define CSL_EVETPCC_CLKGDIS_CLKGDIS_SHIFT (0U)
931 #define CSL_EVETPCC_CLKGDIS_CLKGDIS_RESETVAL (0x00000000U)
932 #define CSL_EVETPCC_CLKGDIS_CLKGDIS_MAX (0x00000001U)
934 #define CSL_EVETPCC_CLKGDIS_RESETVAL (0x00000000U)
936 /* DCHMAPN */
938 #define CSL_EVETPCC_DCHMAPN_PAENTRY_MASK (0x00003FE0U)
939 #define CSL_EVETPCC_DCHMAPN_PAENTRY_SHIFT (5U)
940 #define CSL_EVETPCC_DCHMAPN_PAENTRY_RESETVAL (0x00000000U)
941 #define CSL_EVETPCC_DCHMAPN_PAENTRY_MAX (0x000001ffU)
943 #define CSL_EVETPCC_DCHMAPN_RESETVAL (0x00000000U)
945 /* QCHMAPN */
947 #define CSL_EVETPCC_QCHMAPN_PAENTRY_MASK (0x00003FE0U)
948 #define CSL_EVETPCC_QCHMAPN_PAENTRY_SHIFT (5U)
949 #define CSL_EVETPCC_QCHMAPN_PAENTRY_RESETVAL (0x00000000U)
950 #define CSL_EVETPCC_QCHMAPN_PAENTRY_MAX (0x000001ffU)
952 #define CSL_EVETPCC_QCHMAPN_TRWORD_MASK (0x0000001CU)
953 #define CSL_EVETPCC_QCHMAPN_TRWORD_SHIFT (2U)
954 #define CSL_EVETPCC_QCHMAPN_TRWORD_RESETVAL (0x00000000U)
955 #define CSL_EVETPCC_QCHMAPN_TRWORD_MAX (0x00000007U)
957 #define CSL_EVETPCC_QCHMAPN_RESETVAL (0x00000000U)
959 /* DMAQNUMN */
961 #define CSL_EVETPCC_DMAQNUMN_E6_MASK (0x07000000U)
962 #define CSL_EVETPCC_DMAQNUMN_E6_SHIFT (24U)
963 #define CSL_EVETPCC_DMAQNUMN_E6_RESETVAL (0x00000000U)
964 #define CSL_EVETPCC_DMAQNUMN_E6_Q3 (0x00000003U)
965 #define CSL_EVETPCC_DMAQNUMN_E6_Q7 (0x00000007U)
966 #define CSL_EVETPCC_DMAQNUMN_E6_Q4 (0x00000004U)
967 #define CSL_EVETPCC_DMAQNUMN_E6_Q6 (0x00000006U)
968 #define CSL_EVETPCC_DMAQNUMN_E6_Q1 (0x00000001U)
969 #define CSL_EVETPCC_DMAQNUMN_E6_Q0 (0x00000000U)
970 #define CSL_EVETPCC_DMAQNUMN_E6_Q5 (0x00000005U)
971 #define CSL_EVETPCC_DMAQNUMN_E6_Q2 (0x00000002U)
973 #define CSL_EVETPCC_DMAQNUMN_E2_MASK (0x00000700U)
974 #define CSL_EVETPCC_DMAQNUMN_E2_SHIFT (8U)
975 #define CSL_EVETPCC_DMAQNUMN_E2_RESETVAL (0x00000000U)
976 #define CSL_EVETPCC_DMAQNUMN_E2_Q4 (0x00000004U)
977 #define CSL_EVETPCC_DMAQNUMN_E2_Q7 (0x00000007U)
978 #define CSL_EVETPCC_DMAQNUMN_E2_Q1 (0x00000001U)
979 #define CSL_EVETPCC_DMAQNUMN_E2_Q2 (0x00000002U)
980 #define CSL_EVETPCC_DMAQNUMN_E2_Q5 (0x00000005U)
981 #define CSL_EVETPCC_DMAQNUMN_E2_Q0 (0x00000000U)
982 #define CSL_EVETPCC_DMAQNUMN_E2_Q3 (0x00000003U)
983 #define CSL_EVETPCC_DMAQNUMN_E2_Q6 (0x00000006U)
985 #define CSL_EVETPCC_DMAQNUMN_E1_MASK (0x00000070U)
986 #define CSL_EVETPCC_DMAQNUMN_E1_SHIFT (4U)
987 #define CSL_EVETPCC_DMAQNUMN_E1_RESETVAL (0x00000000U)
988 #define CSL_EVETPCC_DMAQNUMN_E1_Q4 (0x00000004U)
989 #define CSL_EVETPCC_DMAQNUMN_E1_Q3 (0x00000003U)
990 #define CSL_EVETPCC_DMAQNUMN_E1_Q6 (0x00000006U)
991 #define CSL_EVETPCC_DMAQNUMN_E1_Q0 (0x00000000U)
992 #define CSL_EVETPCC_DMAQNUMN_E1_Q1 (0x00000001U)
993 #define CSL_EVETPCC_DMAQNUMN_E1_Q7 (0x00000007U)
994 #define CSL_EVETPCC_DMAQNUMN_E1_Q2 (0x00000002U)
995 #define CSL_EVETPCC_DMAQNUMN_E1_Q5 (0x00000005U)
997 #define CSL_EVETPCC_DMAQNUMN_E4_MASK (0x00070000U)
998 #define CSL_EVETPCC_DMAQNUMN_E4_SHIFT (16U)
999 #define CSL_EVETPCC_DMAQNUMN_E4_RESETVAL (0x00000000U)
1000 #define CSL_EVETPCC_DMAQNUMN_E4_Q1 (0x00000001U)
1001 #define CSL_EVETPCC_DMAQNUMN_E4_Q0 (0x00000000U)
1002 #define CSL_EVETPCC_DMAQNUMN_E4_Q4 (0x00000004U)
1003 #define CSL_EVETPCC_DMAQNUMN_E4_Q2 (0x00000002U)
1004 #define CSL_EVETPCC_DMAQNUMN_E4_Q5 (0x00000005U)
1005 #define CSL_EVETPCC_DMAQNUMN_E4_Q7 (0x00000007U)
1006 #define CSL_EVETPCC_DMAQNUMN_E4_Q3 (0x00000003U)
1007 #define CSL_EVETPCC_DMAQNUMN_E4_Q6 (0x00000006U)
1009 #define CSL_EVETPCC_DMAQNUMN_E3_MASK (0x00007000U)
1010 #define CSL_EVETPCC_DMAQNUMN_E3_SHIFT (12U)
1011 #define CSL_EVETPCC_DMAQNUMN_E3_RESETVAL (0x00000000U)
1012 #define CSL_EVETPCC_DMAQNUMN_E3_Q2 (0x00000002U)
1013 #define CSL_EVETPCC_DMAQNUMN_E3_Q5 (0x00000005U)
1014 #define CSL_EVETPCC_DMAQNUMN_E3_Q0 (0x00000000U)
1015 #define CSL_EVETPCC_DMAQNUMN_E3_Q4 (0x00000004U)
1016 #define CSL_EVETPCC_DMAQNUMN_E3_Q3 (0x00000003U)
1017 #define CSL_EVETPCC_DMAQNUMN_E3_Q6 (0x00000006U)
1018 #define CSL_EVETPCC_DMAQNUMN_E3_Q7 (0x00000007U)
1019 #define CSL_EVETPCC_DMAQNUMN_E3_Q1 (0x00000001U)
1021 #define CSL_EVETPCC_DMAQNUMN_E5_MASK (0x00700000U)
1022 #define CSL_EVETPCC_DMAQNUMN_E5_SHIFT (20U)
1023 #define CSL_EVETPCC_DMAQNUMN_E5_RESETVAL (0x00000000U)
1024 #define CSL_EVETPCC_DMAQNUMN_E5_Q7 (0x00000007U)
1025 #define CSL_EVETPCC_DMAQNUMN_E5_Q1 (0x00000001U)
1026 #define CSL_EVETPCC_DMAQNUMN_E5_Q2 (0x00000002U)
1027 #define CSL_EVETPCC_DMAQNUMN_E5_Q5 (0x00000005U)
1028 #define CSL_EVETPCC_DMAQNUMN_E5_Q3 (0x00000003U)
1029 #define CSL_EVETPCC_DMAQNUMN_E5_Q4 (0x00000004U)
1030 #define CSL_EVETPCC_DMAQNUMN_E5_Q6 (0x00000006U)
1031 #define CSL_EVETPCC_DMAQNUMN_E5_Q0 (0x00000000U)
1033 #define CSL_EVETPCC_DMAQNUMN_E0_MASK (0x00000007U)
1034 #define CSL_EVETPCC_DMAQNUMN_E0_SHIFT (0U)
1035 #define CSL_EVETPCC_DMAQNUMN_E0_RESETVAL (0x00000000U)
1036 #define CSL_EVETPCC_DMAQNUMN_E0_Q5 (0x00000005U)
1037 #define CSL_EVETPCC_DMAQNUMN_E0_Q4 (0x00000004U)
1038 #define CSL_EVETPCC_DMAQNUMN_E0_Q6 (0x00000006U)
1039 #define CSL_EVETPCC_DMAQNUMN_E0_Q1 (0x00000001U)
1040 #define CSL_EVETPCC_DMAQNUMN_E0_Q0 (0x00000000U)
1041 #define CSL_EVETPCC_DMAQNUMN_E0_Q3 (0x00000003U)
1042 #define CSL_EVETPCC_DMAQNUMN_E0_Q2 (0x00000002U)
1043 #define CSL_EVETPCC_DMAQNUMN_E0_Q7 (0x00000007U)
1045 #define CSL_EVETPCC_DMAQNUMN_E7_MASK (0x70000000U)
1046 #define CSL_EVETPCC_DMAQNUMN_E7_SHIFT (28U)
1047 #define CSL_EVETPCC_DMAQNUMN_E7_RESETVAL (0x00000000U)
1048 #define CSL_EVETPCC_DMAQNUMN_E7_Q3 (0x00000003U)
1049 #define CSL_EVETPCC_DMAQNUMN_E7_Q7 (0x00000007U)
1050 #define CSL_EVETPCC_DMAQNUMN_E7_Q6 (0x00000006U)
1051 #define CSL_EVETPCC_DMAQNUMN_E7_Q1 (0x00000001U)
1052 #define CSL_EVETPCC_DMAQNUMN_E7_Q0 (0x00000000U)
1053 #define CSL_EVETPCC_DMAQNUMN_E7_Q4 (0x00000004U)
1054 #define CSL_EVETPCC_DMAQNUMN_E7_Q2 (0x00000002U)
1055 #define CSL_EVETPCC_DMAQNUMN_E7_Q5 (0x00000005U)
1057 #define CSL_EVETPCC_DMAQNUMN_RESETVAL (0x00000000U)
1059 /* QDMAQNUM */
1061 #define CSL_EVETPCC_QDMAQNUM_E5_MASK (0x00700000U)
1062 #define CSL_EVETPCC_QDMAQNUM_E5_SHIFT (20U)
1063 #define CSL_EVETPCC_QDMAQNUM_E5_RESETVAL (0x00000000U)
1064 #define CSL_EVETPCC_QDMAQNUM_E5_Q7 (0x00000007U)
1065 #define CSL_EVETPCC_QDMAQNUM_E5_Q0 (0x00000000U)
1066 #define CSL_EVETPCC_QDMAQNUM_E5_Q3 (0x00000003U)
1067 #define CSL_EVETPCC_QDMAQNUM_E5_Q2 (0x00000002U)
1068 #define CSL_EVETPCC_QDMAQNUM_E5_Q6 (0x00000006U)
1069 #define CSL_EVETPCC_QDMAQNUM_E5_Q4 (0x00000004U)
1070 #define CSL_EVETPCC_QDMAQNUM_E5_Q5 (0x00000005U)
1071 #define CSL_EVETPCC_QDMAQNUM_E5_Q1 (0x00000001U)
1073 #define CSL_EVETPCC_QDMAQNUM_E6_MASK (0x07000000U)
1074 #define CSL_EVETPCC_QDMAQNUM_E6_SHIFT (24U)
1075 #define CSL_EVETPCC_QDMAQNUM_E6_RESETVAL (0x00000000U)
1076 #define CSL_EVETPCC_QDMAQNUM_E6_Q1 (0x00000001U)
1077 #define CSL_EVETPCC_QDMAQNUM_E6_Q5 (0x00000005U)
1078 #define CSL_EVETPCC_QDMAQNUM_E6_Q0 (0x00000000U)
1079 #define CSL_EVETPCC_QDMAQNUM_E6_Q4 (0x00000004U)
1080 #define CSL_EVETPCC_QDMAQNUM_E6_Q7 (0x00000007U)
1081 #define CSL_EVETPCC_QDMAQNUM_E6_Q2 (0x00000002U)
1082 #define CSL_EVETPCC_QDMAQNUM_E6_Q6 (0x00000006U)
1083 #define CSL_EVETPCC_QDMAQNUM_E6_Q3 (0x00000003U)
1085 #define CSL_EVETPCC_QDMAQNUM_E7_MASK (0x70000000U)
1086 #define CSL_EVETPCC_QDMAQNUM_E7_SHIFT (28U)
1087 #define CSL_EVETPCC_QDMAQNUM_E7_RESETVAL (0x00000000U)
1088 #define CSL_EVETPCC_QDMAQNUM_E7_Q0 (0x00000000U)
1089 #define CSL_EVETPCC_QDMAQNUM_E7_Q4 (0x00000004U)
1090 #define CSL_EVETPCC_QDMAQNUM_E7_Q5 (0x00000005U)
1091 #define CSL_EVETPCC_QDMAQNUM_E7_Q3 (0x00000003U)
1092 #define CSL_EVETPCC_QDMAQNUM_E7_Q2 (0x00000002U)
1093 #define CSL_EVETPCC_QDMAQNUM_E7_Q1 (0x00000001U)
1094 #define CSL_EVETPCC_QDMAQNUM_E7_Q6 (0x00000006U)
1095 #define CSL_EVETPCC_QDMAQNUM_E7_Q7 (0x00000007U)
1097 #define CSL_EVETPCC_QDMAQNUM_E4_MASK (0x00070000U)
1098 #define CSL_EVETPCC_QDMAQNUM_E4_SHIFT (16U)
1099 #define CSL_EVETPCC_QDMAQNUM_E4_RESETVAL (0x00000000U)
1100 #define CSL_EVETPCC_QDMAQNUM_E4_Q0 (0x00000000U)
1101 #define CSL_EVETPCC_QDMAQNUM_E4_Q4 (0x00000004U)
1102 #define CSL_EVETPCC_QDMAQNUM_E4_Q6 (0x00000006U)
1103 #define CSL_EVETPCC_QDMAQNUM_E4_Q3 (0x00000003U)
1104 #define CSL_EVETPCC_QDMAQNUM_E4_Q1 (0x00000001U)
1105 #define CSL_EVETPCC_QDMAQNUM_E4_Q2 (0x00000002U)
1106 #define CSL_EVETPCC_QDMAQNUM_E4_Q5 (0x00000005U)
1107 #define CSL_EVETPCC_QDMAQNUM_E4_Q7 (0x00000007U)
1109 #define CSL_EVETPCC_QDMAQNUM_E3_MASK (0x00007000U)
1110 #define CSL_EVETPCC_QDMAQNUM_E3_SHIFT (12U)
1111 #define CSL_EVETPCC_QDMAQNUM_E3_RESETVAL (0x00000000U)
1112 #define CSL_EVETPCC_QDMAQNUM_E3_Q5 (0x00000005U)
1113 #define CSL_EVETPCC_QDMAQNUM_E3_Q7 (0x00000007U)
1114 #define CSL_EVETPCC_QDMAQNUM_E3_Q4 (0x00000004U)
1115 #define CSL_EVETPCC_QDMAQNUM_E3_Q6 (0x00000006U)
1116 #define CSL_EVETPCC_QDMAQNUM_E3_Q3 (0x00000003U)
1117 #define CSL_EVETPCC_QDMAQNUM_E3_Q2 (0x00000002U)
1118 #define CSL_EVETPCC_QDMAQNUM_E3_Q1 (0x00000001U)
1119 #define CSL_EVETPCC_QDMAQNUM_E3_Q0 (0x00000000U)
1121 #define CSL_EVETPCC_QDMAQNUM_E1_MASK (0x00000070U)
1122 #define CSL_EVETPCC_QDMAQNUM_E1_SHIFT (4U)
1123 #define CSL_EVETPCC_QDMAQNUM_E1_RESETVAL (0x00000000U)
1124 #define CSL_EVETPCC_QDMAQNUM_E1_Q3 (0x00000003U)
1125 #define CSL_EVETPCC_QDMAQNUM_E1_Q5 (0x00000005U)
1126 #define CSL_EVETPCC_QDMAQNUM_E1_Q7 (0x00000007U)
1127 #define CSL_EVETPCC_QDMAQNUM_E1_Q1 (0x00000001U)
1128 #define CSL_EVETPCC_QDMAQNUM_E1_Q6 (0x00000006U)
1129 #define CSL_EVETPCC_QDMAQNUM_E1_Q0 (0x00000000U)
1130 #define CSL_EVETPCC_QDMAQNUM_E1_Q4 (0x00000004U)
1131 #define CSL_EVETPCC_QDMAQNUM_E1_Q2 (0x00000002U)
1133 #define CSL_EVETPCC_QDMAQNUM_E0_MASK (0x00000007U)
1134 #define CSL_EVETPCC_QDMAQNUM_E0_SHIFT (0U)
1135 #define CSL_EVETPCC_QDMAQNUM_E0_RESETVAL (0x00000000U)
1136 #define CSL_EVETPCC_QDMAQNUM_E0_Q1 (0x00000001U)
1137 #define CSL_EVETPCC_QDMAQNUM_E0_Q6 (0x00000006U)
1138 #define CSL_EVETPCC_QDMAQNUM_E0_Q3 (0x00000003U)
1139 #define CSL_EVETPCC_QDMAQNUM_E0_Q4 (0x00000004U)
1140 #define CSL_EVETPCC_QDMAQNUM_E0_Q7 (0x00000007U)
1141 #define CSL_EVETPCC_QDMAQNUM_E0_Q2 (0x00000002U)
1142 #define CSL_EVETPCC_QDMAQNUM_E0_Q5 (0x00000005U)
1143 #define CSL_EVETPCC_QDMAQNUM_E0_Q0 (0x00000000U)
1145 #define CSL_EVETPCC_QDMAQNUM_E2_MASK (0x00000700U)
1146 #define CSL_EVETPCC_QDMAQNUM_E2_SHIFT (8U)
1147 #define CSL_EVETPCC_QDMAQNUM_E2_RESETVAL (0x00000000U)
1148 #define CSL_EVETPCC_QDMAQNUM_E2_Q5 (0x00000005U)
1149 #define CSL_EVETPCC_QDMAQNUM_E2_Q7 (0x00000007U)
1150 #define CSL_EVETPCC_QDMAQNUM_E2_Q0 (0x00000000U)
1151 #define CSL_EVETPCC_QDMAQNUM_E2_Q1 (0x00000001U)
1152 #define CSL_EVETPCC_QDMAQNUM_E2_Q2 (0x00000002U)
1153 #define CSL_EVETPCC_QDMAQNUM_E2_Q4 (0x00000004U)
1154 #define CSL_EVETPCC_QDMAQNUM_E2_Q6 (0x00000006U)
1155 #define CSL_EVETPCC_QDMAQNUM_E2_Q3 (0x00000003U)
1157 #define CSL_EVETPCC_QDMAQNUM_RESETVAL (0x00000000U)
1159 /* QUETCMAP */
1161 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_MASK (0x00000007U)
1162 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_SHIFT (0U)
1163 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_RESETVAL (0x00000000U)
1164 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC0 (0x00000000U)
1165 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC1 (0x00000001U)
1166 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC2 (0x00000002U)
1167 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC3 (0x00000003U)
1168 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC4 (0x00000004U)
1169 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC5 (0x00000005U)
1170 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC6 (0x00000006U)
1171 #define CSL_EVETPCC_QUETCMAP_TCNUMQ0_TC7 (0x00000007U)
1173 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_MASK (0x00000070U)
1174 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_SHIFT (4U)
1175 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_RESETVAL (0x00000001U)
1176 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC1 (0x00000001U)
1177 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC0 (0x00000000U)
1178 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC6 (0x00000006U)
1179 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC2 (0x00000002U)
1180 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC3 (0x00000003U)
1181 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC5 (0x00000005U)
1182 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC7 (0x00000007U)
1183 #define CSL_EVETPCC_QUETCMAP_TCNUMQ1_TC4 (0x00000004U)
1185 #define CSL_EVETPCC_QUETCMAP_RESETVAL (0x00000010U)
1187 /* QUEPRI */
1189 #define CSL_EVETPCC_QUEPRI_PRIQ0_MASK (0x00000007U)
1190 #define CSL_EVETPCC_QUEPRI_PRIQ0_SHIFT (0U)
1191 #define CSL_EVETPCC_QUEPRI_PRIQ0_RESETVAL (0x00000000U)
1192 #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY7 (0x00000007U)
1193 #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY6 (0x00000006U)
1194 #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY5 (0x00000005U)
1195 #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY4 (0x00000004U)
1196 #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY3 (0x00000003U)
1197 #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY2 (0x00000002U)
1198 #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY1 (0x00000001U)
1199 #define CSL_EVETPCC_QUEPRI_PRIQ0_PRIORITY0 (0x00000000U)
1201 #define CSL_EVETPCC_QUEPRI_PRIQ1_MASK (0x00000070U)
1202 #define CSL_EVETPCC_QUEPRI_PRIQ1_SHIFT (4U)
1203 #define CSL_EVETPCC_QUEPRI_PRIQ1_RESETVAL (0x00000000U)
1204 #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY7 (0x00000007U)
1205 #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY6 (0x00000006U)
1206 #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY0 (0x00000000U)
1207 #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY1 (0x00000001U)
1208 #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY3 (0x00000003U)
1209 #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY4 (0x00000004U)
1210 #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY2 (0x00000002U)
1211 #define CSL_EVETPCC_QUEPRI_PRIQ1_PRIORITY5 (0x00000005U)
1213 #define CSL_EVETPCC_QUEPRI_RESETVAL (0x00000000U)
1215 /* EMR */
1217 #define CSL_EVETPCC_EMR_E0_MASK (0x00000001U)
1218 #define CSL_EVETPCC_EMR_E0_SHIFT (0U)
1219 #define CSL_EVETPCC_EMR_E0_RESETVAL (0x00000000U)
1220 #define CSL_EVETPCC_EMR_E0_MAX (0x00000001U)
1222 #define CSL_EVETPCC_EMR_E1_MASK (0x00000002U)
1223 #define CSL_EVETPCC_EMR_E1_SHIFT (1U)
1224 #define CSL_EVETPCC_EMR_E1_RESETVAL (0x00000000U)
1225 #define CSL_EVETPCC_EMR_E1_MAX (0x00000001U)
1227 #define CSL_EVETPCC_EMR_E2_MASK (0x00000004U)
1228 #define CSL_EVETPCC_EMR_E2_SHIFT (2U)
1229 #define CSL_EVETPCC_EMR_E2_RESETVAL (0x00000000U)
1230 #define CSL_EVETPCC_EMR_E2_MAX (0x00000001U)
1232 #define CSL_EVETPCC_EMR_E3_MASK (0x00000008U)
1233 #define CSL_EVETPCC_EMR_E3_SHIFT (3U)
1234 #define CSL_EVETPCC_EMR_E3_RESETVAL (0x00000000U)
1235 #define CSL_EVETPCC_EMR_E3_MAX (0x00000001U)
1237 #define CSL_EVETPCC_EMR_E4_MASK (0x00000010U)
1238 #define CSL_EVETPCC_EMR_E4_SHIFT (4U)
1239 #define CSL_EVETPCC_EMR_E4_RESETVAL (0x00000000U)
1240 #define CSL_EVETPCC_EMR_E4_MAX (0x00000001U)
1242 #define CSL_EVETPCC_EMR_E5_MASK (0x00000020U)
1243 #define CSL_EVETPCC_EMR_E5_SHIFT (5U)
1244 #define CSL_EVETPCC_EMR_E5_RESETVAL (0x00000000U)
1245 #define CSL_EVETPCC_EMR_E5_MAX (0x00000001U)
1247 #define CSL_EVETPCC_EMR_E6_MASK (0x00000040U)
1248 #define CSL_EVETPCC_EMR_E6_SHIFT (6U)
1249 #define CSL_EVETPCC_EMR_E6_RESETVAL (0x00000000U)
1250 #define CSL_EVETPCC_EMR_E6_MAX (0x00000001U)
1252 #define CSL_EVETPCC_EMR_E7_MASK (0x00000080U)
1253 #define CSL_EVETPCC_EMR_E7_SHIFT (7U)
1254 #define CSL_EVETPCC_EMR_E7_RESETVAL (0x00000000U)
1255 #define CSL_EVETPCC_EMR_E7_MAX (0x00000001U)
1257 #define CSL_EVETPCC_EMR_E8_MASK (0x00000100U)
1258 #define CSL_EVETPCC_EMR_E8_SHIFT (8U)
1259 #define CSL_EVETPCC_EMR_E8_RESETVAL (0x00000000U)
1260 #define CSL_EVETPCC_EMR_E8_MAX (0x00000001U)
1262 #define CSL_EVETPCC_EMR_E9_MASK (0x00000200U)
1263 #define CSL_EVETPCC_EMR_E9_SHIFT (9U)
1264 #define CSL_EVETPCC_EMR_E9_RESETVAL (0x00000000U)
1265 #define CSL_EVETPCC_EMR_E9_MAX (0x00000001U)
1267 #define CSL_EVETPCC_EMR_E10_MASK (0x00000400U)
1268 #define CSL_EVETPCC_EMR_E10_SHIFT (10U)
1269 #define CSL_EVETPCC_EMR_E10_RESETVAL (0x00000000U)
1270 #define CSL_EVETPCC_EMR_E10_MAX (0x00000001U)
1272 #define CSL_EVETPCC_EMR_E11_MASK (0x00000800U)
1273 #define CSL_EVETPCC_EMR_E11_SHIFT (11U)
1274 #define CSL_EVETPCC_EMR_E11_RESETVAL (0x00000000U)
1275 #define CSL_EVETPCC_EMR_E11_MAX (0x00000001U)
1277 #define CSL_EVETPCC_EMR_E12_MASK (0x00001000U)
1278 #define CSL_EVETPCC_EMR_E12_SHIFT (12U)
1279 #define CSL_EVETPCC_EMR_E12_RESETVAL (0x00000000U)
1280 #define CSL_EVETPCC_EMR_E12_MAX (0x00000001U)
1282 #define CSL_EVETPCC_EMR_E13_MASK (0x00002000U)
1283 #define CSL_EVETPCC_EMR_E13_SHIFT (13U)
1284 #define CSL_EVETPCC_EMR_E13_RESETVAL (0x00000000U)
1285 #define CSL_EVETPCC_EMR_E13_MAX (0x00000001U)
1287 #define CSL_EVETPCC_EMR_E14_MASK (0x00004000U)
1288 #define CSL_EVETPCC_EMR_E14_SHIFT (14U)
1289 #define CSL_EVETPCC_EMR_E14_RESETVAL (0x00000000U)
1290 #define CSL_EVETPCC_EMR_E14_MAX (0x00000001U)
1292 #define CSL_EVETPCC_EMR_E15_MASK (0x00008000U)
1293 #define CSL_EVETPCC_EMR_E15_SHIFT (15U)
1294 #define CSL_EVETPCC_EMR_E15_RESETVAL (0x00000000U)
1295 #define CSL_EVETPCC_EMR_E15_MAX (0x00000001U)
1297 #define CSL_EVETPCC_EMR_E16_MASK (0x00010000U)
1298 #define CSL_EVETPCC_EMR_E16_SHIFT (16U)
1299 #define CSL_EVETPCC_EMR_E16_RESETVAL (0x00000000U)
1300 #define CSL_EVETPCC_EMR_E16_MAX (0x00000001U)
1302 #define CSL_EVETPCC_EMR_E17_MASK (0x00020000U)
1303 #define CSL_EVETPCC_EMR_E17_SHIFT (17U)
1304 #define CSL_EVETPCC_EMR_E17_RESETVAL (0x00000000U)
1305 #define CSL_EVETPCC_EMR_E17_MAX (0x00000001U)
1307 #define CSL_EVETPCC_EMR_E18_MASK (0x00040000U)
1308 #define CSL_EVETPCC_EMR_E18_SHIFT (18U)
1309 #define CSL_EVETPCC_EMR_E18_RESETVAL (0x00000000U)
1310 #define CSL_EVETPCC_EMR_E18_MAX (0x00000001U)
1312 #define CSL_EVETPCC_EMR_E19_MASK (0x00080000U)
1313 #define CSL_EVETPCC_EMR_E19_SHIFT (19U)
1314 #define CSL_EVETPCC_EMR_E19_RESETVAL (0x00000000U)
1315 #define CSL_EVETPCC_EMR_E19_MAX (0x00000001U)
1317 #define CSL_EVETPCC_EMR_E20_MASK (0x00100000U)
1318 #define CSL_EVETPCC_EMR_E20_SHIFT (20U)
1319 #define CSL_EVETPCC_EMR_E20_RESETVAL (0x00000000U)
1320 #define CSL_EVETPCC_EMR_E20_MAX (0x00000001U)
1322 #define CSL_EVETPCC_EMR_E21_MASK (0x00200000U)
1323 #define CSL_EVETPCC_EMR_E21_SHIFT (21U)
1324 #define CSL_EVETPCC_EMR_E21_RESETVAL (0x00000000U)
1325 #define CSL_EVETPCC_EMR_E21_MAX (0x00000001U)
1327 #define CSL_EVETPCC_EMR_E22_MASK (0x00400000U)
1328 #define CSL_EVETPCC_EMR_E22_SHIFT (22U)
1329 #define CSL_EVETPCC_EMR_E22_RESETVAL (0x00000000U)
1330 #define CSL_EVETPCC_EMR_E22_MAX (0x00000001U)
1332 #define CSL_EVETPCC_EMR_E23_MASK (0x00800000U)
1333 #define CSL_EVETPCC_EMR_E23_SHIFT (23U)
1334 #define CSL_EVETPCC_EMR_E23_RESETVAL (0x00000000U)
1335 #define CSL_EVETPCC_EMR_E23_MAX (0x00000001U)
1337 #define CSL_EVETPCC_EMR_E24_MASK (0x01000000U)
1338 #define CSL_EVETPCC_EMR_E24_SHIFT (24U)
1339 #define CSL_EVETPCC_EMR_E24_RESETVAL (0x00000000U)
1340 #define CSL_EVETPCC_EMR_E24_MAX (0x00000001U)
1342 #define CSL_EVETPCC_EMR_E25_MASK (0x02000000U)
1343 #define CSL_EVETPCC_EMR_E25_SHIFT (25U)
1344 #define CSL_EVETPCC_EMR_E25_RESETVAL (0x00000000U)
1345 #define CSL_EVETPCC_EMR_E25_MAX (0x00000001U)
1347 #define CSL_EVETPCC_EMR_E26_MASK (0x04000000U)
1348 #define CSL_EVETPCC_EMR_E26_SHIFT (26U)
1349 #define CSL_EVETPCC_EMR_E26_RESETVAL (0x00000000U)
1350 #define CSL_EVETPCC_EMR_E26_MAX (0x00000001U)
1352 #define CSL_EVETPCC_EMR_E27_MASK (0x08000000U)
1353 #define CSL_EVETPCC_EMR_E27_SHIFT (27U)
1354 #define CSL_EVETPCC_EMR_E27_RESETVAL (0x00000000U)
1355 #define CSL_EVETPCC_EMR_E27_MAX (0x00000001U)
1357 #define CSL_EVETPCC_EMR_E28_MASK (0x10000000U)
1358 #define CSL_EVETPCC_EMR_E28_SHIFT (28U)
1359 #define CSL_EVETPCC_EMR_E28_RESETVAL (0x00000000U)
1360 #define CSL_EVETPCC_EMR_E28_MAX (0x00000001U)
1362 #define CSL_EVETPCC_EMR_E29_MASK (0x20000000U)
1363 #define CSL_EVETPCC_EMR_E29_SHIFT (29U)
1364 #define CSL_EVETPCC_EMR_E29_RESETVAL (0x00000000U)
1365 #define CSL_EVETPCC_EMR_E29_MAX (0x00000001U)
1367 #define CSL_EVETPCC_EMR_E30_MASK (0x40000000U)
1368 #define CSL_EVETPCC_EMR_E30_SHIFT (30U)
1369 #define CSL_EVETPCC_EMR_E30_RESETVAL (0x00000000U)
1370 #define CSL_EVETPCC_EMR_E30_MAX (0x00000001U)
1372 #define CSL_EVETPCC_EMR_E31_MASK (0x80000000U)
1373 #define CSL_EVETPCC_EMR_E31_SHIFT (31U)
1374 #define CSL_EVETPCC_EMR_E31_RESETVAL (0x00000000U)
1375 #define CSL_EVETPCC_EMR_E31_MAX (0x00000001U)
1377 #define CSL_EVETPCC_EMR_RESETVAL (0x00000000U)
1379 /* EMRH */
1381 #define CSL_EVETPCC_EMRH_E48_MASK (0x00010000U)
1382 #define CSL_EVETPCC_EMRH_E48_SHIFT (16U)
1383 #define CSL_EVETPCC_EMRH_E48_RESETVAL (0x00000000U)
1384 #define CSL_EVETPCC_EMRH_E48_MAX (0x00000001U)
1386 #define CSL_EVETPCC_EMRH_E33_MASK (0x00000002U)
1387 #define CSL_EVETPCC_EMRH_E33_SHIFT (1U)
1388 #define CSL_EVETPCC_EMRH_E33_RESETVAL (0x00000000U)
1389 #define CSL_EVETPCC_EMRH_E33_MAX (0x00000001U)
1391 #define CSL_EVETPCC_EMRH_E42_MASK (0x00000400U)
1392 #define CSL_EVETPCC_EMRH_E42_SHIFT (10U)
1393 #define CSL_EVETPCC_EMRH_E42_RESETVAL (0x00000000U)
1394 #define CSL_EVETPCC_EMRH_E42_MAX (0x00000001U)
1396 #define CSL_EVETPCC_EMRH_E43_MASK (0x00000800U)
1397 #define CSL_EVETPCC_EMRH_E43_SHIFT (11U)
1398 #define CSL_EVETPCC_EMRH_E43_RESETVAL (0x00000000U)
1399 #define CSL_EVETPCC_EMRH_E43_MAX (0x00000001U)
1401 #define CSL_EVETPCC_EMRH_E45_MASK (0x00002000U)
1402 #define CSL_EVETPCC_EMRH_E45_SHIFT (13U)
1403 #define CSL_EVETPCC_EMRH_E45_RESETVAL (0x00000000U)
1404 #define CSL_EVETPCC_EMRH_E45_MAX (0x00000001U)
1406 #define CSL_EVETPCC_EMRH_E60_MASK (0x10000000U)
1407 #define CSL_EVETPCC_EMRH_E60_SHIFT (28U)
1408 #define CSL_EVETPCC_EMRH_E60_RESETVAL (0x00000000U)
1409 #define CSL_EVETPCC_EMRH_E60_MAX (0x00000001U)
1411 #define CSL_EVETPCC_EMRH_E49_MASK (0x00020000U)
1412 #define CSL_EVETPCC_EMRH_E49_SHIFT (17U)
1413 #define CSL_EVETPCC_EMRH_E49_RESETVAL (0x00000000U)
1414 #define CSL_EVETPCC_EMRH_E49_MAX (0x00000001U)
1416 #define CSL_EVETPCC_EMRH_E54_MASK (0x00400000U)
1417 #define CSL_EVETPCC_EMRH_E54_SHIFT (22U)
1418 #define CSL_EVETPCC_EMRH_E54_RESETVAL (0x00000000U)
1419 #define CSL_EVETPCC_EMRH_E54_MAX (0x00000001U)
1421 #define CSL_EVETPCC_EMRH_E39_MASK (0x00000080U)
1422 #define CSL_EVETPCC_EMRH_E39_SHIFT (7U)
1423 #define CSL_EVETPCC_EMRH_E39_RESETVAL (0x00000000U)
1424 #define CSL_EVETPCC_EMRH_E39_MAX (0x00000001U)
1426 #define CSL_EVETPCC_EMRH_E55_MASK (0x00800000U)
1427 #define CSL_EVETPCC_EMRH_E55_SHIFT (23U)
1428 #define CSL_EVETPCC_EMRH_E55_RESETVAL (0x00000000U)
1429 #define CSL_EVETPCC_EMRH_E55_MAX (0x00000001U)
1431 #define CSL_EVETPCC_EMRH_E53_MASK (0x00200000U)
1432 #define CSL_EVETPCC_EMRH_E53_SHIFT (21U)
1433 #define CSL_EVETPCC_EMRH_E53_RESETVAL (0x00000000U)
1434 #define CSL_EVETPCC_EMRH_E53_MAX (0x00000001U)
1436 #define CSL_EVETPCC_EMRH_E32_MASK (0x00000001U)
1437 #define CSL_EVETPCC_EMRH_E32_SHIFT (0U)
1438 #define CSL_EVETPCC_EMRH_E32_RESETVAL (0x00000000U)
1439 #define CSL_EVETPCC_EMRH_E32_MAX (0x00000001U)
1441 #define CSL_EVETPCC_EMRH_E41_MASK (0x00000200U)
1442 #define CSL_EVETPCC_EMRH_E41_SHIFT (9U)
1443 #define CSL_EVETPCC_EMRH_E41_RESETVAL (0x00000000U)
1444 #define CSL_EVETPCC_EMRH_E41_MAX (0x00000001U)
1446 #define CSL_EVETPCC_EMRH_E47_MASK (0x00008000U)
1447 #define CSL_EVETPCC_EMRH_E47_SHIFT (15U)
1448 #define CSL_EVETPCC_EMRH_E47_RESETVAL (0x00000000U)
1449 #define CSL_EVETPCC_EMRH_E47_MAX (0x00000001U)
1451 #define CSL_EVETPCC_EMRH_E58_MASK (0x04000000U)
1452 #define CSL_EVETPCC_EMRH_E58_SHIFT (26U)
1453 #define CSL_EVETPCC_EMRH_E58_RESETVAL (0x00000000U)
1454 #define CSL_EVETPCC_EMRH_E58_MAX (0x00000001U)
1456 #define CSL_EVETPCC_EMRH_E35_MASK (0x00000008U)
1457 #define CSL_EVETPCC_EMRH_E35_SHIFT (3U)
1458 #define CSL_EVETPCC_EMRH_E35_RESETVAL (0x00000000U)
1459 #define CSL_EVETPCC_EMRH_E35_MAX (0x00000001U)
1461 #define CSL_EVETPCC_EMRH_E34_MASK (0x00000004U)
1462 #define CSL_EVETPCC_EMRH_E34_SHIFT (2U)
1463 #define CSL_EVETPCC_EMRH_E34_RESETVAL (0x00000000U)
1464 #define CSL_EVETPCC_EMRH_E34_MAX (0x00000001U)
1466 #define CSL_EVETPCC_EMRH_E38_MASK (0x00000040U)
1467 #define CSL_EVETPCC_EMRH_E38_SHIFT (6U)
1468 #define CSL_EVETPCC_EMRH_E38_RESETVAL (0x00000000U)
1469 #define CSL_EVETPCC_EMRH_E38_MAX (0x00000001U)
1471 #define CSL_EVETPCC_EMRH_E59_MASK (0x08000000U)
1472 #define CSL_EVETPCC_EMRH_E59_SHIFT (27U)
1473 #define CSL_EVETPCC_EMRH_E59_RESETVAL (0x00000000U)
1474 #define CSL_EVETPCC_EMRH_E59_MAX (0x00000001U)
1476 #define CSL_EVETPCC_EMRH_E37_MASK (0x00000020U)
1477 #define CSL_EVETPCC_EMRH_E37_SHIFT (5U)
1478 #define CSL_EVETPCC_EMRH_E37_RESETVAL (0x00000000U)
1479 #define CSL_EVETPCC_EMRH_E37_MAX (0x00000001U)
1481 #define CSL_EVETPCC_EMRH_E63_MASK (0x80000000U)
1482 #define CSL_EVETPCC_EMRH_E63_SHIFT (31U)
1483 #define CSL_EVETPCC_EMRH_E63_RESETVAL (0x00000000U)
1484 #define CSL_EVETPCC_EMRH_E63_MAX (0x00000001U)
1486 #define CSL_EVETPCC_EMRH_E57_MASK (0x02000000U)
1487 #define CSL_EVETPCC_EMRH_E57_SHIFT (25U)
1488 #define CSL_EVETPCC_EMRH_E57_RESETVAL (0x00000000U)
1489 #define CSL_EVETPCC_EMRH_E57_MAX (0x00000001U)
1491 #define CSL_EVETPCC_EMRH_E62_MASK (0x40000000U)
1492 #define CSL_EVETPCC_EMRH_E62_SHIFT (30U)
1493 #define CSL_EVETPCC_EMRH_E62_RESETVAL (0x00000000U)
1494 #define CSL_EVETPCC_EMRH_E62_MAX (0x00000001U)
1496 #define CSL_EVETPCC_EMRH_E36_MASK (0x00000010U)
1497 #define CSL_EVETPCC_EMRH_E36_SHIFT (4U)
1498 #define CSL_EVETPCC_EMRH_E36_RESETVAL (0x00000000U)
1499 #define CSL_EVETPCC_EMRH_E36_MAX (0x00000001U)
1501 #define CSL_EVETPCC_EMRH_E44_MASK (0x00001000U)
1502 #define CSL_EVETPCC_EMRH_E44_SHIFT (12U)
1503 #define CSL_EVETPCC_EMRH_E44_RESETVAL (0x00000000U)
1504 #define CSL_EVETPCC_EMRH_E44_MAX (0x00000001U)
1506 #define CSL_EVETPCC_EMRH_E56_MASK (0x01000000U)
1507 #define CSL_EVETPCC_EMRH_E56_SHIFT (24U)
1508 #define CSL_EVETPCC_EMRH_E56_RESETVAL (0x00000000U)
1509 #define CSL_EVETPCC_EMRH_E56_MAX (0x00000001U)
1511 #define CSL_EVETPCC_EMRH_E50_MASK (0x00040000U)
1512 #define CSL_EVETPCC_EMRH_E50_SHIFT (18U)
1513 #define CSL_EVETPCC_EMRH_E50_RESETVAL (0x00000000U)
1514 #define CSL_EVETPCC_EMRH_E50_MAX (0x00000001U)
1516 #define CSL_EVETPCC_EMRH_E40_MASK (0x00000100U)
1517 #define CSL_EVETPCC_EMRH_E40_SHIFT (8U)
1518 #define CSL_EVETPCC_EMRH_E40_RESETVAL (0x00000000U)
1519 #define CSL_EVETPCC_EMRH_E40_MAX (0x00000001U)
1521 #define CSL_EVETPCC_EMRH_E46_MASK (0x00004000U)
1522 #define CSL_EVETPCC_EMRH_E46_SHIFT (14U)
1523 #define CSL_EVETPCC_EMRH_E46_RESETVAL (0x00000000U)
1524 #define CSL_EVETPCC_EMRH_E46_MAX (0x00000001U)
1526 #define CSL_EVETPCC_EMRH_E51_MASK (0x00080000U)
1527 #define CSL_EVETPCC_EMRH_E51_SHIFT (19U)
1528 #define CSL_EVETPCC_EMRH_E51_RESETVAL (0x00000000U)
1529 #define CSL_EVETPCC_EMRH_E51_MAX (0x00000001U)
1531 #define CSL_EVETPCC_EMRH_E52_MASK (0x00100000U)
1532 #define CSL_EVETPCC_EMRH_E52_SHIFT (20U)
1533 #define CSL_EVETPCC_EMRH_E52_RESETVAL (0x00000000U)
1534 #define CSL_EVETPCC_EMRH_E52_MAX (0x00000001U)
1536 #define CSL_EVETPCC_EMRH_E61_MASK (0x20000000U)
1537 #define CSL_EVETPCC_EMRH_E61_SHIFT (29U)
1538 #define CSL_EVETPCC_EMRH_E61_RESETVAL (0x00000000U)
1539 #define CSL_EVETPCC_EMRH_E61_MAX (0x00000001U)
1541 #define CSL_EVETPCC_EMRH_RESETVAL (0x00000000U)
1543 /* EMCR */
1545 #define CSL_EVETPCC_EMCR_E10_MASK (0x00000400U)
1546 #define CSL_EVETPCC_EMCR_E10_SHIFT (10U)
1547 #define CSL_EVETPCC_EMCR_E10_RESETVAL (0x00000000U)
1548 #define CSL_EVETPCC_EMCR_E10_MAX (0x00000001U)
1550 #define CSL_EVETPCC_EMCR_E7_MASK (0x00000080U)
1551 #define CSL_EVETPCC_EMCR_E7_SHIFT (7U)
1552 #define CSL_EVETPCC_EMCR_E7_RESETVAL (0x00000000U)
1553 #define CSL_EVETPCC_EMCR_E7_MAX (0x00000001U)
1555 #define CSL_EVETPCC_EMCR_E29_MASK (0x20000000U)
1556 #define CSL_EVETPCC_EMCR_E29_SHIFT (29U)
1557 #define CSL_EVETPCC_EMCR_E29_RESETVAL (0x00000000U)
1558 #define CSL_EVETPCC_EMCR_E29_MAX (0x00000001U)
1560 #define CSL_EVETPCC_EMCR_E30_MASK (0x40000000U)
1561 #define CSL_EVETPCC_EMCR_E30_SHIFT (30U)
1562 #define CSL_EVETPCC_EMCR_E30_RESETVAL (0x00000000U)
1563 #define CSL_EVETPCC_EMCR_E30_MAX (0x00000001U)
1565 #define CSL_EVETPCC_EMCR_E11_MASK (0x00000800U)
1566 #define CSL_EVETPCC_EMCR_E11_SHIFT (11U)
1567 #define CSL_EVETPCC_EMCR_E11_RESETVAL (0x00000000U)
1568 #define CSL_EVETPCC_EMCR_E11_MAX (0x00000001U)
1570 #define CSL_EVETPCC_EMCR_E16_MASK (0x00010000U)
1571 #define CSL_EVETPCC_EMCR_E16_SHIFT (16U)
1572 #define CSL_EVETPCC_EMCR_E16_RESETVAL (0x00000000U)
1573 #define CSL_EVETPCC_EMCR_E16_MAX (0x00000001U)
1575 #define CSL_EVETPCC_EMCR_E2_MASK (0x00000004U)
1576 #define CSL_EVETPCC_EMCR_E2_SHIFT (2U)
1577 #define CSL_EVETPCC_EMCR_E2_RESETVAL (0x00000000U)
1578 #define CSL_EVETPCC_EMCR_E2_MAX (0x00000001U)
1580 #define CSL_EVETPCC_EMCR_E28_MASK (0x10000000U)
1581 #define CSL_EVETPCC_EMCR_E28_SHIFT (28U)
1582 #define CSL_EVETPCC_EMCR_E28_RESETVAL (0x00000000U)
1583 #define CSL_EVETPCC_EMCR_E28_MAX (0x00000001U)
1585 #define CSL_EVETPCC_EMCR_E17_MASK (0x00020000U)
1586 #define CSL_EVETPCC_EMCR_E17_SHIFT (17U)
1587 #define CSL_EVETPCC_EMCR_E17_RESETVAL (0x00000000U)
1588 #define CSL_EVETPCC_EMCR_E17_MAX (0x00000001U)
1590 #define CSL_EVETPCC_EMCR_E12_MASK (0x00001000U)
1591 #define CSL_EVETPCC_EMCR_E12_SHIFT (12U)
1592 #define CSL_EVETPCC_EMCR_E12_RESETVAL (0x00000000U)
1593 #define CSL_EVETPCC_EMCR_E12_MAX (0x00000001U)
1595 #define CSL_EVETPCC_EMCR_E24_MASK (0x01000000U)
1596 #define CSL_EVETPCC_EMCR_E24_SHIFT (24U)
1597 #define CSL_EVETPCC_EMCR_E24_RESETVAL (0x00000000U)
1598 #define CSL_EVETPCC_EMCR_E24_MAX (0x00000001U)
1600 #define CSL_EVETPCC_EMCR_E4_MASK (0x00000010U)
1601 #define CSL_EVETPCC_EMCR_E4_SHIFT (4U)
1602 #define CSL_EVETPCC_EMCR_E4_RESETVAL (0x00000000U)
1603 #define CSL_EVETPCC_EMCR_E4_MAX (0x00000001U)
1605 #define CSL_EVETPCC_EMCR_E25_MASK (0x02000000U)
1606 #define CSL_EVETPCC_EMCR_E25_SHIFT (25U)
1607 #define CSL_EVETPCC_EMCR_E25_RESETVAL (0x00000000U)
1608 #define CSL_EVETPCC_EMCR_E25_MAX (0x00000001U)
1610 #define CSL_EVETPCC_EMCR_E8_MASK (0x00000100U)
1611 #define CSL_EVETPCC_EMCR_E8_SHIFT (8U)
1612 #define CSL_EVETPCC_EMCR_E8_RESETVAL (0x00000000U)
1613 #define CSL_EVETPCC_EMCR_E8_MAX (0x00000001U)
1615 #define CSL_EVETPCC_EMCR_E15_MASK (0x00008000U)
1616 #define CSL_EVETPCC_EMCR_E15_SHIFT (15U)
1617 #define CSL_EVETPCC_EMCR_E15_RESETVAL (0x00000000U)
1618 #define CSL_EVETPCC_EMCR_E15_MAX (0x00000001U)
1620 #define CSL_EVETPCC_EMCR_E31_MASK (0x80000000U)
1621 #define CSL_EVETPCC_EMCR_E31_SHIFT (31U)
1622 #define CSL_EVETPCC_EMCR_E31_RESETVAL (0x00000000U)
1623 #define CSL_EVETPCC_EMCR_E31_MAX (0x00000001U)
1625 #define CSL_EVETPCC_EMCR_E26_MASK (0x04000000U)
1626 #define CSL_EVETPCC_EMCR_E26_SHIFT (26U)
1627 #define CSL_EVETPCC_EMCR_E26_RESETVAL (0x00000000U)
1628 #define CSL_EVETPCC_EMCR_E26_MAX (0x00000001U)
1630 #define CSL_EVETPCC_EMCR_E14_MASK (0x00004000U)
1631 #define CSL_EVETPCC_EMCR_E14_SHIFT (14U)
1632 #define CSL_EVETPCC_EMCR_E14_RESETVAL (0x00000000U)
1633 #define CSL_EVETPCC_EMCR_E14_MAX (0x00000001U)
1635 #define CSL_EVETPCC_EMCR_E9_MASK (0x00000200U)
1636 #define CSL_EVETPCC_EMCR_E9_SHIFT (9U)
1637 #define CSL_EVETPCC_EMCR_E9_RESETVAL (0x00000000U)
1638 #define CSL_EVETPCC_EMCR_E9_MAX (0x00000001U)
1640 #define CSL_EVETPCC_EMCR_E23_MASK (0x00800000U)
1641 #define CSL_EVETPCC_EMCR_E23_SHIFT (23U)
1642 #define CSL_EVETPCC_EMCR_E23_RESETVAL (0x00000000U)
1643 #define CSL_EVETPCC_EMCR_E23_MAX (0x00000001U)
1645 #define CSL_EVETPCC_EMCR_E6_MASK (0x00000040U)
1646 #define CSL_EVETPCC_EMCR_E6_SHIFT (6U)
1647 #define CSL_EVETPCC_EMCR_E6_RESETVAL (0x00000000U)
1648 #define CSL_EVETPCC_EMCR_E6_MAX (0x00000001U)
1650 #define CSL_EVETPCC_EMCR_E13_MASK (0x00002000U)
1651 #define CSL_EVETPCC_EMCR_E13_SHIFT (13U)
1652 #define CSL_EVETPCC_EMCR_E13_RESETVAL (0x00000000U)
1653 #define CSL_EVETPCC_EMCR_E13_MAX (0x00000001U)
1655 #define CSL_EVETPCC_EMCR_E1_MASK (0x00000002U)
1656 #define CSL_EVETPCC_EMCR_E1_SHIFT (1U)
1657 #define CSL_EVETPCC_EMCR_E1_RESETVAL (0x00000000U)
1658 #define CSL_EVETPCC_EMCR_E1_MAX (0x00000001U)
1660 #define CSL_EVETPCC_EMCR_E21_MASK (0x00200000U)
1661 #define CSL_EVETPCC_EMCR_E21_SHIFT (21U)
1662 #define CSL_EVETPCC_EMCR_E21_RESETVAL (0x00000000U)
1663 #define CSL_EVETPCC_EMCR_E21_MAX (0x00000001U)
1665 #define CSL_EVETPCC_EMCR_E22_MASK (0x00400000U)
1666 #define CSL_EVETPCC_EMCR_E22_SHIFT (22U)
1667 #define CSL_EVETPCC_EMCR_E22_RESETVAL (0x00000000U)
1668 #define CSL_EVETPCC_EMCR_E22_MAX (0x00000001U)
1670 #define CSL_EVETPCC_EMCR_E27_MASK (0x08000000U)
1671 #define CSL_EVETPCC_EMCR_E27_SHIFT (27U)
1672 #define CSL_EVETPCC_EMCR_E27_RESETVAL (0x00000000U)
1673 #define CSL_EVETPCC_EMCR_E27_MAX (0x00000001U)
1675 #define CSL_EVETPCC_EMCR_E20_MASK (0x00100000U)
1676 #define CSL_EVETPCC_EMCR_E20_SHIFT (20U)
1677 #define CSL_EVETPCC_EMCR_E20_RESETVAL (0x00000000U)
1678 #define CSL_EVETPCC_EMCR_E20_MAX (0x00000001U)
1680 #define CSL_EVETPCC_EMCR_E19_MASK (0x00080000U)
1681 #define CSL_EVETPCC_EMCR_E19_SHIFT (19U)
1682 #define CSL_EVETPCC_EMCR_E19_RESETVAL (0x00000000U)
1683 #define CSL_EVETPCC_EMCR_E19_MAX (0x00000001U)
1685 #define CSL_EVETPCC_EMCR_E0_MASK (0x00000001U)
1686 #define CSL_EVETPCC_EMCR_E0_SHIFT (0U)
1687 #define CSL_EVETPCC_EMCR_E0_RESETVAL (0x00000000U)
1688 #define CSL_EVETPCC_EMCR_E0_MAX (0x00000001U)
1690 #define CSL_EVETPCC_EMCR_E5_MASK (0x00000020U)
1691 #define CSL_EVETPCC_EMCR_E5_SHIFT (5U)
1692 #define CSL_EVETPCC_EMCR_E5_RESETVAL (0x00000000U)
1693 #define CSL_EVETPCC_EMCR_E5_MAX (0x00000001U)
1695 #define CSL_EVETPCC_EMCR_E3_MASK (0x00000008U)
1696 #define CSL_EVETPCC_EMCR_E3_SHIFT (3U)
1697 #define CSL_EVETPCC_EMCR_E3_RESETVAL (0x00000000U)
1698 #define CSL_EVETPCC_EMCR_E3_MAX (0x00000001U)
1700 #define CSL_EVETPCC_EMCR_E18_MASK (0x00040000U)
1701 #define CSL_EVETPCC_EMCR_E18_SHIFT (18U)
1702 #define CSL_EVETPCC_EMCR_E18_RESETVAL (0x00000000U)
1703 #define CSL_EVETPCC_EMCR_E18_MAX (0x00000001U)
1705 #define CSL_EVETPCC_EMCR_RESETVAL (0x00000000U)
1707 /* EMCRH */
1709 #define CSL_EVETPCC_EMCRH_E41_MASK (0x00000200U)
1710 #define CSL_EVETPCC_EMCRH_E41_SHIFT (9U)
1711 #define CSL_EVETPCC_EMCRH_E41_RESETVAL (0x00000000U)
1712 #define CSL_EVETPCC_EMCRH_E41_MAX (0x00000001U)
1714 #define CSL_EVETPCC_EMCRH_E60_MASK (0x10000000U)
1715 #define CSL_EVETPCC_EMCRH_E60_SHIFT (28U)
1716 #define CSL_EVETPCC_EMCRH_E60_RESETVAL (0x00000000U)
1717 #define CSL_EVETPCC_EMCRH_E60_MAX (0x00000001U)
1719 #define CSL_EVETPCC_EMCRH_E43_MASK (0x00000800U)
1720 #define CSL_EVETPCC_EMCRH_E43_SHIFT (11U)
1721 #define CSL_EVETPCC_EMCRH_E43_RESETVAL (0x00000000U)
1722 #define CSL_EVETPCC_EMCRH_E43_MAX (0x00000001U)
1724 #define CSL_EVETPCC_EMCRH_E63_MASK (0x80000000U)
1725 #define CSL_EVETPCC_EMCRH_E63_SHIFT (31U)
1726 #define CSL_EVETPCC_EMCRH_E63_RESETVAL (0x00000000U)
1727 #define CSL_EVETPCC_EMCRH_E63_MAX (0x00000001U)
1729 #define CSL_EVETPCC_EMCRH_E55_MASK (0x00800000U)
1730 #define CSL_EVETPCC_EMCRH_E55_SHIFT (23U)
1731 #define CSL_EVETPCC_EMCRH_E55_RESETVAL (0x00000000U)
1732 #define CSL_EVETPCC_EMCRH_E55_MAX (0x00000001U)
1734 #define CSL_EVETPCC_EMCRH_E38_MASK (0x00000040U)
1735 #define CSL_EVETPCC_EMCRH_E38_SHIFT (6U)
1736 #define CSL_EVETPCC_EMCRH_E38_RESETVAL (0x00000000U)
1737 #define CSL_EVETPCC_EMCRH_E38_MAX (0x00000001U)
1739 #define CSL_EVETPCC_EMCRH_E62_MASK (0x40000000U)
1740 #define CSL_EVETPCC_EMCRH_E62_SHIFT (30U)
1741 #define CSL_EVETPCC_EMCRH_E62_RESETVAL (0x00000000U)
1742 #define CSL_EVETPCC_EMCRH_E62_MAX (0x00000001U)
1744 #define CSL_EVETPCC_EMCRH_E34_MASK (0x00000004U)
1745 #define CSL_EVETPCC_EMCRH_E34_SHIFT (2U)
1746 #define CSL_EVETPCC_EMCRH_E34_RESETVAL (0x00000000U)
1747 #define CSL_EVETPCC_EMCRH_E34_MAX (0x00000001U)
1749 #define CSL_EVETPCC_EMCRH_E46_MASK (0x00004000U)
1750 #define CSL_EVETPCC_EMCRH_E46_SHIFT (14U)
1751 #define CSL_EVETPCC_EMCRH_E46_RESETVAL (0x00000000U)
1752 #define CSL_EVETPCC_EMCRH_E46_MAX (0x00000001U)
1754 #define CSL_EVETPCC_EMCRH_E42_MASK (0x00000400U)
1755 #define CSL_EVETPCC_EMCRH_E42_SHIFT (10U)
1756 #define CSL_EVETPCC_EMCRH_E42_RESETVAL (0x00000000U)
1757 #define CSL_EVETPCC_EMCRH_E42_MAX (0x00000001U)
1759 #define CSL_EVETPCC_EMCRH_E48_MASK (0x00010000U)
1760 #define CSL_EVETPCC_EMCRH_E48_SHIFT (16U)
1761 #define CSL_EVETPCC_EMCRH_E48_RESETVAL (0x00000000U)
1762 #define CSL_EVETPCC_EMCRH_E48_MAX (0x00000001U)
1764 #define CSL_EVETPCC_EMCRH_E32_MASK (0x00000001U)
1765 #define CSL_EVETPCC_EMCRH_E32_SHIFT (0U)
1766 #define CSL_EVETPCC_EMCRH_E32_RESETVAL (0x00000000U)
1767 #define CSL_EVETPCC_EMCRH_E32_MAX (0x00000001U)
1769 #define CSL_EVETPCC_EMCRH_E44_MASK (0x00001000U)
1770 #define CSL_EVETPCC_EMCRH_E44_SHIFT (12U)
1771 #define CSL_EVETPCC_EMCRH_E44_RESETVAL (0x00000000U)
1772 #define CSL_EVETPCC_EMCRH_E44_MAX (0x00000001U)
1774 #define CSL_EVETPCC_EMCRH_E50_MASK (0x00040000U)
1775 #define CSL_EVETPCC_EMCRH_E50_SHIFT (18U)
1776 #define CSL_EVETPCC_EMCRH_E50_RESETVAL (0x00000000U)
1777 #define CSL_EVETPCC_EMCRH_E50_MAX (0x00000001U)
1779 #define CSL_EVETPCC_EMCRH_E53_MASK (0x00200000U)
1780 #define CSL_EVETPCC_EMCRH_E53_SHIFT (21U)
1781 #define CSL_EVETPCC_EMCRH_E53_RESETVAL (0x00000000U)
1782 #define CSL_EVETPCC_EMCRH_E53_MAX (0x00000001U)
1784 #define CSL_EVETPCC_EMCRH_E37_MASK (0x00000020U)
1785 #define CSL_EVETPCC_EMCRH_E37_SHIFT (5U)
1786 #define CSL_EVETPCC_EMCRH_E37_RESETVAL (0x00000000U)
1787 #define CSL_EVETPCC_EMCRH_E37_MAX (0x00000001U)
1789 #define CSL_EVETPCC_EMCRH_E45_MASK (0x00002000U)
1790 #define CSL_EVETPCC_EMCRH_E45_SHIFT (13U)
1791 #define CSL_EVETPCC_EMCRH_E45_RESETVAL (0x00000000U)
1792 #define CSL_EVETPCC_EMCRH_E45_MAX (0x00000001U)
1794 #define CSL_EVETPCC_EMCRH_E59_MASK (0x08000000U)
1795 #define CSL_EVETPCC_EMCRH_E59_SHIFT (27U)
1796 #define CSL_EVETPCC_EMCRH_E59_RESETVAL (0x00000000U)
1797 #define CSL_EVETPCC_EMCRH_E59_MAX (0x00000001U)
1799 #define CSL_EVETPCC_EMCRH_E58_MASK (0x04000000U)
1800 #define CSL_EVETPCC_EMCRH_E58_SHIFT (26U)
1801 #define CSL_EVETPCC_EMCRH_E58_RESETVAL (0x00000000U)
1802 #define CSL_EVETPCC_EMCRH_E58_MAX (0x00000001U)
1804 #define CSL_EVETPCC_EMCRH_E40_MASK (0x00000100U)
1805 #define CSL_EVETPCC_EMCRH_E40_SHIFT (8U)
1806 #define CSL_EVETPCC_EMCRH_E40_RESETVAL (0x00000000U)
1807 #define CSL_EVETPCC_EMCRH_E40_MAX (0x00000001U)
1809 #define CSL_EVETPCC_EMCRH_E54_MASK (0x00400000U)
1810 #define CSL_EVETPCC_EMCRH_E54_SHIFT (22U)
1811 #define CSL_EVETPCC_EMCRH_E54_RESETVAL (0x00000000U)
1812 #define CSL_EVETPCC_EMCRH_E54_MAX (0x00000001U)
1814 #define CSL_EVETPCC_EMCRH_E49_MASK (0x00020000U)
1815 #define CSL_EVETPCC_EMCRH_E49_SHIFT (17U)
1816 #define CSL_EVETPCC_EMCRH_E49_RESETVAL (0x00000000U)
1817 #define CSL_EVETPCC_EMCRH_E49_MAX (0x00000001U)
1819 #define CSL_EVETPCC_EMCRH_E33_MASK (0x00000002U)
1820 #define CSL_EVETPCC_EMCRH_E33_SHIFT (1U)
1821 #define CSL_EVETPCC_EMCRH_E33_RESETVAL (0x00000000U)
1822 #define CSL_EVETPCC_EMCRH_E33_MAX (0x00000001U)
1824 #define CSL_EVETPCC_EMCRH_E47_MASK (0x00008000U)
1825 #define CSL_EVETPCC_EMCRH_E47_SHIFT (15U)
1826 #define CSL_EVETPCC_EMCRH_E47_RESETVAL (0x00000000U)
1827 #define CSL_EVETPCC_EMCRH_E47_MAX (0x00000001U)
1829 #define CSL_EVETPCC_EMCRH_E36_MASK (0x00000010U)
1830 #define CSL_EVETPCC_EMCRH_E36_SHIFT (4U)
1831 #define CSL_EVETPCC_EMCRH_E36_RESETVAL (0x00000000U)
1832 #define CSL_EVETPCC_EMCRH_E36_MAX (0x00000001U)
1834 #define CSL_EVETPCC_EMCRH_E56_MASK (0x01000000U)
1835 #define CSL_EVETPCC_EMCRH_E56_SHIFT (24U)
1836 #define CSL_EVETPCC_EMCRH_E56_RESETVAL (0x00000000U)
1837 #define CSL_EVETPCC_EMCRH_E56_MAX (0x00000001U)
1839 #define CSL_EVETPCC_EMCRH_E57_MASK (0x02000000U)
1840 #define CSL_EVETPCC_EMCRH_E57_SHIFT (25U)
1841 #define CSL_EVETPCC_EMCRH_E57_RESETVAL (0x00000000U)
1842 #define CSL_EVETPCC_EMCRH_E57_MAX (0x00000001U)
1844 #define CSL_EVETPCC_EMCRH_E51_MASK (0x00080000U)
1845 #define CSL_EVETPCC_EMCRH_E51_SHIFT (19U)
1846 #define CSL_EVETPCC_EMCRH_E51_RESETVAL (0x00000000U)
1847 #define CSL_EVETPCC_EMCRH_E51_MAX (0x00000001U)
1849 #define CSL_EVETPCC_EMCRH_E61_MASK (0x20000000U)
1850 #define CSL_EVETPCC_EMCRH_E61_SHIFT (29U)
1851 #define CSL_EVETPCC_EMCRH_E61_RESETVAL (0x00000000U)
1852 #define CSL_EVETPCC_EMCRH_E61_MAX (0x00000001U)
1854 #define CSL_EVETPCC_EMCRH_E39_MASK (0x00000080U)
1855 #define CSL_EVETPCC_EMCRH_E39_SHIFT (7U)
1856 #define CSL_EVETPCC_EMCRH_E39_RESETVAL (0x00000000U)
1857 #define CSL_EVETPCC_EMCRH_E39_MAX (0x00000001U)
1859 #define CSL_EVETPCC_EMCRH_E52_MASK (0x00100000U)
1860 #define CSL_EVETPCC_EMCRH_E52_SHIFT (20U)
1861 #define CSL_EVETPCC_EMCRH_E52_RESETVAL (0x00000000U)
1862 #define CSL_EVETPCC_EMCRH_E52_MAX (0x00000001U)
1864 #define CSL_EVETPCC_EMCRH_E35_MASK (0x00000008U)
1865 #define CSL_EVETPCC_EMCRH_E35_SHIFT (3U)
1866 #define CSL_EVETPCC_EMCRH_E35_RESETVAL (0x00000000U)
1867 #define CSL_EVETPCC_EMCRH_E35_MAX (0x00000001U)
1869 #define CSL_EVETPCC_EMCRH_RESETVAL (0x00000000U)
1871 /* QEMR */
1873 #define CSL_EVETPCC_QEMR_E7_MASK (0x00000080U)
1874 #define CSL_EVETPCC_QEMR_E7_SHIFT (7U)
1875 #define CSL_EVETPCC_QEMR_E7_RESETVAL (0x00000000U)
1876 #define CSL_EVETPCC_QEMR_E7_MAX (0x00000001U)
1878 #define CSL_EVETPCC_QEMR_E6_MASK (0x00000040U)
1879 #define CSL_EVETPCC_QEMR_E6_SHIFT (6U)
1880 #define CSL_EVETPCC_QEMR_E6_RESETVAL (0x00000000U)
1881 #define CSL_EVETPCC_QEMR_E6_MAX (0x00000001U)
1883 #define CSL_EVETPCC_QEMR_E5_MASK (0x00000020U)
1884 #define CSL_EVETPCC_QEMR_E5_SHIFT (5U)
1885 #define CSL_EVETPCC_QEMR_E5_RESETVAL (0x00000000U)
1886 #define CSL_EVETPCC_QEMR_E5_MAX (0x00000001U)
1888 #define CSL_EVETPCC_QEMR_E4_MASK (0x00000010U)
1889 #define CSL_EVETPCC_QEMR_E4_SHIFT (4U)
1890 #define CSL_EVETPCC_QEMR_E4_RESETVAL (0x00000000U)
1891 #define CSL_EVETPCC_QEMR_E4_MAX (0x00000001U)
1893 #define CSL_EVETPCC_QEMR_E3_MASK (0x00000008U)
1894 #define CSL_EVETPCC_QEMR_E3_SHIFT (3U)
1895 #define CSL_EVETPCC_QEMR_E3_RESETVAL (0x00000000U)
1896 #define CSL_EVETPCC_QEMR_E3_MAX (0x00000001U)
1898 #define CSL_EVETPCC_QEMR_E2_MASK (0x00000004U)
1899 #define CSL_EVETPCC_QEMR_E2_SHIFT (2U)
1900 #define CSL_EVETPCC_QEMR_E2_RESETVAL (0x00000000U)
1901 #define CSL_EVETPCC_QEMR_E2_MAX (0x00000001U)
1903 #define CSL_EVETPCC_QEMR_E1_MASK (0x00000002U)
1904 #define CSL_EVETPCC_QEMR_E1_SHIFT (1U)
1905 #define CSL_EVETPCC_QEMR_E1_RESETVAL (0x00000000U)
1906 #define CSL_EVETPCC_QEMR_E1_MAX (0x00000001U)
1908 #define CSL_EVETPCC_QEMR_E0_MASK (0x00000001U)
1909 #define CSL_EVETPCC_QEMR_E0_SHIFT (0U)
1910 #define CSL_EVETPCC_QEMR_E0_RESETVAL (0x00000000U)
1911 #define CSL_EVETPCC_QEMR_E0_MAX (0x00000001U)
1913 #define CSL_EVETPCC_QEMR_RESETVAL (0x00000000U)
1915 /* QEMCR */
1917 #define CSL_EVETPCC_QEMCR_E7_MASK (0x00000080U)
1918 #define CSL_EVETPCC_QEMCR_E7_SHIFT (7U)
1919 #define CSL_EVETPCC_QEMCR_E7_RESETVAL (0x00000000U)
1920 #define CSL_EVETPCC_QEMCR_E7_MAX (0x00000001U)
1922 #define CSL_EVETPCC_QEMCR_E6_MASK (0x00000040U)
1923 #define CSL_EVETPCC_QEMCR_E6_SHIFT (6U)
1924 #define CSL_EVETPCC_QEMCR_E6_RESETVAL (0x00000000U)
1925 #define CSL_EVETPCC_QEMCR_E6_MAX (0x00000001U)
1927 #define CSL_EVETPCC_QEMCR_E5_MASK (0x00000020U)
1928 #define CSL_EVETPCC_QEMCR_E5_SHIFT (5U)
1929 #define CSL_EVETPCC_QEMCR_E5_RESETVAL (0x00000000U)
1930 #define CSL_EVETPCC_QEMCR_E5_MAX (0x00000001U)
1932 #define CSL_EVETPCC_QEMCR_E4_MASK (0x00000010U)
1933 #define CSL_EVETPCC_QEMCR_E4_SHIFT (4U)
1934 #define CSL_EVETPCC_QEMCR_E4_RESETVAL (0x00000000U)
1935 #define CSL_EVETPCC_QEMCR_E4_MAX (0x00000001U)
1937 #define CSL_EVETPCC_QEMCR_E3_MASK (0x00000008U)
1938 #define CSL_EVETPCC_QEMCR_E3_SHIFT (3U)
1939 #define CSL_EVETPCC_QEMCR_E3_RESETVAL (0x00000000U)
1940 #define CSL_EVETPCC_QEMCR_E3_MAX (0x00000001U)
1942 #define CSL_EVETPCC_QEMCR_E2_MASK (0x00000004U)
1943 #define CSL_EVETPCC_QEMCR_E2_SHIFT (2U)
1944 #define CSL_EVETPCC_QEMCR_E2_RESETVAL (0x00000000U)
1945 #define CSL_EVETPCC_QEMCR_E2_MAX (0x00000001U)
1947 #define CSL_EVETPCC_QEMCR_E1_MASK (0x00000002U)
1948 #define CSL_EVETPCC_QEMCR_E1_SHIFT (1U)
1949 #define CSL_EVETPCC_QEMCR_E1_RESETVAL (0x00000000U)
1950 #define CSL_EVETPCC_QEMCR_E1_MAX (0x00000001U)
1952 #define CSL_EVETPCC_QEMCR_E0_MASK (0x00000001U)
1953 #define CSL_EVETPCC_QEMCR_E0_SHIFT (0U)
1954 #define CSL_EVETPCC_QEMCR_E0_RESETVAL (0x00000000U)
1955 #define CSL_EVETPCC_QEMCR_E0_MAX (0x00000001U)
1957 #define CSL_EVETPCC_QEMCR_RESETVAL (0x00000000U)
1959 /* CCERR */
1961 #define CSL_EVETPCC_CCERR_QTHRXCD0_MASK (0x00000001U)
1962 #define CSL_EVETPCC_CCERR_QTHRXCD0_SHIFT (0U)
1963 #define CSL_EVETPCC_CCERR_QTHRXCD0_RESETVAL (0x00000000U)
1964 #define CSL_EVETPCC_CCERR_QTHRXCD0_MAX (0x00000001U)
1966 #define CSL_EVETPCC_CCERR_TCERR_MASK (0x00010000U)
1967 #define CSL_EVETPCC_CCERR_TCERR_SHIFT (16U)
1968 #define CSL_EVETPCC_CCERR_TCERR_RESETVAL (0x00000000U)
1969 #define CSL_EVETPCC_CCERR_TCERR_MAX (0x00000001U)
1971 #define CSL_EVETPCC_CCERR_QTHRXCD1_MASK (0x00000002U)
1972 #define CSL_EVETPCC_CCERR_QTHRXCD1_SHIFT (1U)
1973 #define CSL_EVETPCC_CCERR_QTHRXCD1_RESETVAL (0x00000000U)
1974 #define CSL_EVETPCC_CCERR_QTHRXCD1_MAX (0x00000001U)
1976 #define CSL_EVETPCC_CCERR_QTHRXCD2_MASK (0x00000004U)
1977 #define CSL_EVETPCC_CCERR_QTHRXCD2_SHIFT (2U)
1978 #define CSL_EVETPCC_CCERR_QTHRXCD2_RESETVAL (0x00000000U)
1979 #define CSL_EVETPCC_CCERR_QTHRXCD2_MAX (0x00000001U)
1981 #define CSL_EVETPCC_CCERR_QTHRXCD3_MASK (0x00000008U)
1982 #define CSL_EVETPCC_CCERR_QTHRXCD3_SHIFT (3U)
1983 #define CSL_EVETPCC_CCERR_QTHRXCD3_RESETVAL (0x00000000U)
1984 #define CSL_EVETPCC_CCERR_QTHRXCD3_MAX (0x00000001U)
1986 #define CSL_EVETPCC_CCERR_QTHRXCD4_MASK (0x00000010U)
1987 #define CSL_EVETPCC_CCERR_QTHRXCD4_SHIFT (4U)
1988 #define CSL_EVETPCC_CCERR_QTHRXCD4_RESETVAL (0x00000000U)
1989 #define CSL_EVETPCC_CCERR_QTHRXCD4_MAX (0x00000001U)
1991 #define CSL_EVETPCC_CCERR_QTHRXCD5_MASK (0x00000020U)
1992 #define CSL_EVETPCC_CCERR_QTHRXCD5_SHIFT (5U)
1993 #define CSL_EVETPCC_CCERR_QTHRXCD5_RESETVAL (0x00000000U)
1994 #define CSL_EVETPCC_CCERR_QTHRXCD5_MAX (0x00000001U)
1996 #define CSL_EVETPCC_CCERR_QTHRXCD6_MASK (0x00000040U)
1997 #define CSL_EVETPCC_CCERR_QTHRXCD6_SHIFT (6U)
1998 #define CSL_EVETPCC_CCERR_QTHRXCD6_RESETVAL (0x00000000U)
1999 #define CSL_EVETPCC_CCERR_QTHRXCD6_MAX (0x00000001U)
2001 #define CSL_EVETPCC_CCERR_QTHRXCD7_MASK (0x00000080U)
2002 #define CSL_EVETPCC_CCERR_QTHRXCD7_SHIFT (7U)
2003 #define CSL_EVETPCC_CCERR_QTHRXCD7_RESETVAL (0x00000000U)
2004 #define CSL_EVETPCC_CCERR_QTHRXCD7_MAX (0x00000001U)
2006 #define CSL_EVETPCC_CCERR_RESETVAL (0x00000000U)
2008 /* CCERRCLR */
2010 #define CSL_EVETPCC_CCERRCLR_QTHRXCD0_MASK (0x00000001U)
2011 #define CSL_EVETPCC_CCERRCLR_QTHRXCD0_SHIFT (0U)
2012 #define CSL_EVETPCC_CCERRCLR_QTHRXCD0_RESETVAL (0x00000000U)
2013 #define CSL_EVETPCC_CCERRCLR_QTHRXCD0_MAX (0x00000001U)
2015 #define CSL_EVETPCC_CCERRCLR_QTHRXCD1_MASK (0x00000002U)
2016 #define CSL_EVETPCC_CCERRCLR_QTHRXCD1_SHIFT (1U)
2017 #define CSL_EVETPCC_CCERRCLR_QTHRXCD1_RESETVAL (0x00000000U)
2018 #define CSL_EVETPCC_CCERRCLR_QTHRXCD1_MAX (0x00000001U)
2020 #define CSL_EVETPCC_CCERRCLR_QTHRXCD2_MASK (0x00000004U)
2021 #define CSL_EVETPCC_CCERRCLR_QTHRXCD2_SHIFT (2U)
2022 #define CSL_EVETPCC_CCERRCLR_QTHRXCD2_RESETVAL (0x00000000U)
2023 #define CSL_EVETPCC_CCERRCLR_QTHRXCD2_MAX (0x00000001U)
2025 #define CSL_EVETPCC_CCERRCLR_QTHRXCD3_MASK (0x00000008U)
2026 #define CSL_EVETPCC_CCERRCLR_QTHRXCD3_SHIFT (3U)
2027 #define CSL_EVETPCC_CCERRCLR_QTHRXCD3_RESETVAL (0x00000000U)
2028 #define CSL_EVETPCC_CCERRCLR_QTHRXCD3_MAX (0x00000001U)
2030 #define CSL_EVETPCC_CCERRCLR_QTHRXCD4_MASK (0x00000010U)
2031 #define CSL_EVETPCC_CCERRCLR_QTHRXCD4_SHIFT (4U)
2032 #define CSL_EVETPCC_CCERRCLR_QTHRXCD4_RESETVAL (0x00000000U)
2033 #define CSL_EVETPCC_CCERRCLR_QTHRXCD4_MAX (0x00000001U)
2035 #define CSL_EVETPCC_CCERRCLR_QTHRXCD5_MASK (0x00000020U)
2036 #define CSL_EVETPCC_CCERRCLR_QTHRXCD5_SHIFT (5U)
2037 #define CSL_EVETPCC_CCERRCLR_QTHRXCD5_RESETVAL (0x00000000U)
2038 #define CSL_EVETPCC_CCERRCLR_QTHRXCD5_MAX (0x00000001U)
2040 #define CSL_EVETPCC_CCERRCLR_QTHRXCD6_MASK (0x00000040U)
2041 #define CSL_EVETPCC_CCERRCLR_QTHRXCD6_SHIFT (6U)
2042 #define CSL_EVETPCC_CCERRCLR_QTHRXCD6_RESETVAL (0x00000000U)
2043 #define CSL_EVETPCC_CCERRCLR_QTHRXCD6_MAX (0x00000001U)
2045 #define CSL_EVETPCC_CCERRCLR_QTHRXCD7_MASK (0x00000080U)
2046 #define CSL_EVETPCC_CCERRCLR_QTHRXCD7_SHIFT (7U)
2047 #define CSL_EVETPCC_CCERRCLR_QTHRXCD7_RESETVAL (0x00000000U)
2048 #define CSL_EVETPCC_CCERRCLR_QTHRXCD7_MAX (0x00000001U)
2050 #define CSL_EVETPCC_CCERRCLR_TCERR_MASK (0x00010000U)
2051 #define CSL_EVETPCC_CCERRCLR_TCERR_SHIFT (16U)
2052 #define CSL_EVETPCC_CCERRCLR_TCERR_RESETVAL (0x00000000U)
2053 #define CSL_EVETPCC_CCERRCLR_TCERR_MAX (0x00000001U)
2055 #define CSL_EVETPCC_CCERRCLR_RESETVAL (0x00000000U)
2057 /* EEVAL */
2059 #define CSL_EVETPCC_EEVAL_SET_MASK (0x00000002U)
2060 #define CSL_EVETPCC_EEVAL_SET_SHIFT (1U)
2061 #define CSL_EVETPCC_EEVAL_SET_RESETVAL (0x00000000U)
2062 #define CSL_EVETPCC_EEVAL_SET_MAX (0x00000001U)
2064 #define CSL_EVETPCC_EEVAL_EVAL_MASK (0x00000001U)
2065 #define CSL_EVETPCC_EEVAL_EVAL_SHIFT (0U)
2066 #define CSL_EVETPCC_EEVAL_EVAL_RESETVAL (0x00000000U)
2067 #define CSL_EVETPCC_EEVAL_EVAL_MAX (0x00000001U)
2069 #define CSL_EVETPCC_EEVAL_RESETVAL (0x00000000U)
2071 /* QRAEN */
2073 #define CSL_EVETPCC_QRAEN_E3_MASK (0x00000008U)
2074 #define CSL_EVETPCC_QRAEN_E3_SHIFT (3U)
2075 #define CSL_EVETPCC_QRAEN_E3_RESETVAL (0x00000000U)
2076 #define CSL_EVETPCC_QRAEN_E3_MAX (0x00000001U)
2078 #define CSL_EVETPCC_QRAEN_E4_MASK (0x00000010U)
2079 #define CSL_EVETPCC_QRAEN_E4_SHIFT (4U)
2080 #define CSL_EVETPCC_QRAEN_E4_RESETVAL (0x00000000U)
2081 #define CSL_EVETPCC_QRAEN_E4_MAX (0x00000001U)
2083 #define CSL_EVETPCC_QRAEN_E5_MASK (0x00000020U)
2084 #define CSL_EVETPCC_QRAEN_E5_SHIFT (5U)
2085 #define CSL_EVETPCC_QRAEN_E5_RESETVAL (0x00000000U)
2086 #define CSL_EVETPCC_QRAEN_E5_MAX (0x00000001U)
2088 #define CSL_EVETPCC_QRAEN_E1_MASK (0x00000002U)
2089 #define CSL_EVETPCC_QRAEN_E1_SHIFT (1U)
2090 #define CSL_EVETPCC_QRAEN_E1_RESETVAL (0x00000000U)
2091 #define CSL_EVETPCC_QRAEN_E1_MAX (0x00000001U)
2093 #define CSL_EVETPCC_QRAEN_E7_MASK (0x00000080U)
2094 #define CSL_EVETPCC_QRAEN_E7_SHIFT (7U)
2095 #define CSL_EVETPCC_QRAEN_E7_RESETVAL (0x00000000U)
2096 #define CSL_EVETPCC_QRAEN_E7_MAX (0x00000001U)
2098 #define CSL_EVETPCC_QRAEN_E0_MASK (0x00000001U)
2099 #define CSL_EVETPCC_QRAEN_E0_SHIFT (0U)
2100 #define CSL_EVETPCC_QRAEN_E0_RESETVAL (0x00000000U)
2101 #define CSL_EVETPCC_QRAEN_E0_MAX (0x00000001U)
2103 #define CSL_EVETPCC_QRAEN_E6_MASK (0x00000040U)
2104 #define CSL_EVETPCC_QRAEN_E6_SHIFT (6U)
2105 #define CSL_EVETPCC_QRAEN_E6_RESETVAL (0x00000000U)
2106 #define CSL_EVETPCC_QRAEN_E6_MAX (0x00000001U)
2108 #define CSL_EVETPCC_QRAEN_E2_MASK (0x00000004U)
2109 #define CSL_EVETPCC_QRAEN_E2_SHIFT (2U)
2110 #define CSL_EVETPCC_QRAEN_E2_RESETVAL (0x00000000U)
2111 #define CSL_EVETPCC_QRAEN_E2_MAX (0x00000001U)
2113 #define CSL_EVETPCC_QRAEN_RESETVAL (0x00000000U)
2115 /* QSTATN */
2117 #define CSL_EVETPCC_QSTATN_STRTPTR_MASK (0x0000000FU)
2118 #define CSL_EVETPCC_QSTATN_STRTPTR_SHIFT (0U)
2119 #define CSL_EVETPCC_QSTATN_STRTPTR_RESETVAL (0x00000000U)
2120 #define CSL_EVETPCC_QSTATN_STRTPTR_MAX (0x0000000fU)
2122 #define CSL_EVETPCC_QSTATN_NUMVAL_MASK (0x00001F00U)
2123 #define CSL_EVETPCC_QSTATN_NUMVAL_SHIFT (8U)
2124 #define CSL_EVETPCC_QSTATN_NUMVAL_RESETVAL (0x00000000U)
2125 #define CSL_EVETPCC_QSTATN_NUMVAL_MAX (0x0000001fU)
2127 #define CSL_EVETPCC_QSTATN_WM_MASK (0x001F0000U)
2128 #define CSL_EVETPCC_QSTATN_WM_SHIFT (16U)
2129 #define CSL_EVETPCC_QSTATN_WM_RESETVAL (0x00000000U)
2130 #define CSL_EVETPCC_QSTATN_WM_MAX (0x0000001fU)
2132 #define CSL_EVETPCC_QSTATN_THRXCD_MASK (0x01000000U)
2133 #define CSL_EVETPCC_QSTATN_THRXCD_SHIFT (24U)
2134 #define CSL_EVETPCC_QSTATN_THRXCD_RESETVAL (0x00000000U)
2135 #define CSL_EVETPCC_QSTATN_THRXCD_MAX (0x00000001U)
2137 #define CSL_EVETPCC_QSTATN_RESETVAL (0x00000000U)
2139 /* QWMTHRA */
2141 #define CSL_EVETPCC_QWMTHRA_Q1_MASK (0x00001F00U)
2142 #define CSL_EVETPCC_QWMTHRA_Q1_SHIFT (8U)
2143 #define CSL_EVETPCC_QWMTHRA_Q1_RESETVAL (0x00000010U)
2144 #define CSL_EVETPCC_QWMTHRA_Q1_MAX (0x0000001fU)
2146 #define CSL_EVETPCC_QWMTHRA_Q0_MASK (0x0000001FU)
2147 #define CSL_EVETPCC_QWMTHRA_Q0_SHIFT (0U)
2148 #define CSL_EVETPCC_QWMTHRA_Q0_RESETVAL (0x00000010U)
2149 #define CSL_EVETPCC_QWMTHRA_Q0_MAX (0x0000001fU)
2151 #define CSL_EVETPCC_QWMTHRA_Q3_MASK (0x1F000000U)
2152 #define CSL_EVETPCC_QWMTHRA_Q3_SHIFT (24U)
2153 #define CSL_EVETPCC_QWMTHRA_Q3_RESETVAL (0x00000010U)
2154 #define CSL_EVETPCC_QWMTHRA_Q3_MAX (0x0000001fU)
2156 #define CSL_EVETPCC_QWMTHRA_Q2_MASK (0x001F0000U)
2157 #define CSL_EVETPCC_QWMTHRA_Q2_SHIFT (16U)
2158 #define CSL_EVETPCC_QWMTHRA_Q2_RESETVAL (0x00000010U)
2159 #define CSL_EVETPCC_QWMTHRA_Q2_MAX (0x0000001fU)
2161 #define CSL_EVETPCC_QWMTHRA_RESETVAL (0x10101010U)
2163 /* QWMTHRB */
2165 #define CSL_EVETPCC_QWMTHRB_Q6_MASK (0x001F0000U)
2166 #define CSL_EVETPCC_QWMTHRB_Q6_SHIFT (16U)
2167 #define CSL_EVETPCC_QWMTHRB_Q6_RESETVAL (0x00000010U)
2168 #define CSL_EVETPCC_QWMTHRB_Q6_MAX (0x0000001fU)
2170 #define CSL_EVETPCC_QWMTHRB_Q7_MASK (0x1F000000U)
2171 #define CSL_EVETPCC_QWMTHRB_Q7_SHIFT (24U)
2172 #define CSL_EVETPCC_QWMTHRB_Q7_RESETVAL (0x00000010U)
2173 #define CSL_EVETPCC_QWMTHRB_Q7_MAX (0x0000001fU)
2175 #define CSL_EVETPCC_QWMTHRB_Q4_MASK (0x0000001FU)
2176 #define CSL_EVETPCC_QWMTHRB_Q4_SHIFT (0U)
2177 #define CSL_EVETPCC_QWMTHRB_Q4_RESETVAL (0x00000010U)
2178 #define CSL_EVETPCC_QWMTHRB_Q4_MAX (0x0000001fU)
2180 #define CSL_EVETPCC_QWMTHRB_Q5_MASK (0x00001F00U)
2181 #define CSL_EVETPCC_QWMTHRB_Q5_SHIFT (8U)
2182 #define CSL_EVETPCC_QWMTHRB_Q5_RESETVAL (0x00000010U)
2183 #define CSL_EVETPCC_QWMTHRB_Q5_MAX (0x0000001fU)
2185 #define CSL_EVETPCC_QWMTHRB_RESETVAL (0x10101010U)
2187 /* CCSTAT */
2189 #define CSL_EVETPCC_CCSTAT_EVTACTV_MASK (0x00000001U)
2190 #define CSL_EVETPCC_CCSTAT_EVTACTV_SHIFT (0U)
2191 #define CSL_EVETPCC_CCSTAT_EVTACTV_RESETVAL (0x00000000U)
2192 #define CSL_EVETPCC_CCSTAT_EVTACTV_MAX (0x00000001U)
2194 #define CSL_EVETPCC_CCSTAT_QEVTACTV_MASK (0x00000002U)
2195 #define CSL_EVETPCC_CCSTAT_QEVTACTV_SHIFT (1U)
2196 #define CSL_EVETPCC_CCSTAT_QEVTACTV_RESETVAL (0x00000000U)
2197 #define CSL_EVETPCC_CCSTAT_QEVTACTV_MAX (0x00000001U)
2199 #define CSL_EVETPCC_CCSTAT_TRACTV_MASK (0x00000004U)
2200 #define CSL_EVETPCC_CCSTAT_TRACTV_SHIFT (2U)
2201 #define CSL_EVETPCC_CCSTAT_TRACTV_RESETVAL (0x00000000U)
2202 #define CSL_EVETPCC_CCSTAT_TRACTV_MAX (0x00000001U)
2204 #define CSL_EVETPCC_CCSTAT_ACTV_MASK (0x00000010U)
2205 #define CSL_EVETPCC_CCSTAT_ACTV_SHIFT (4U)
2206 #define CSL_EVETPCC_CCSTAT_ACTV_RESETVAL (0x00000000U)
2207 #define CSL_EVETPCC_CCSTAT_ACTV_MAX (0x00000001U)
2209 #define CSL_EVETPCC_CCSTAT_COMPACTV_MASK (0x00003F00U)
2210 #define CSL_EVETPCC_CCSTAT_COMPACTV_SHIFT (8U)
2211 #define CSL_EVETPCC_CCSTAT_COMPACTV_RESETVAL (0x00000000U)
2212 #define CSL_EVETPCC_CCSTAT_COMPACTV_MAX (0x0000003fU)
2214 #define CSL_EVETPCC_CCSTAT_QUEACTV0_MASK (0x00010000U)
2215 #define CSL_EVETPCC_CCSTAT_QUEACTV0_SHIFT (16U)
2216 #define CSL_EVETPCC_CCSTAT_QUEACTV0_RESETVAL (0x00000000U)
2217 #define CSL_EVETPCC_CCSTAT_QUEACTV0_MAX (0x00000001U)
2219 #define CSL_EVETPCC_CCSTAT_QUEACTV1_MASK (0x00020000U)
2220 #define CSL_EVETPCC_CCSTAT_QUEACTV1_SHIFT (17U)
2221 #define CSL_EVETPCC_CCSTAT_QUEACTV1_RESETVAL (0x00000000U)
2222 #define CSL_EVETPCC_CCSTAT_QUEACTV1_MAX (0x00000001U)
2224 #define CSL_EVETPCC_CCSTAT_QUEACTV2_MASK (0x00040000U)
2225 #define CSL_EVETPCC_CCSTAT_QUEACTV2_SHIFT (18U)
2226 #define CSL_EVETPCC_CCSTAT_QUEACTV2_RESETVAL (0x00000000U)
2227 #define CSL_EVETPCC_CCSTAT_QUEACTV2_MAX (0x00000001U)
2229 #define CSL_EVETPCC_CCSTAT_QUEACTV3_MASK (0x00080000U)
2230 #define CSL_EVETPCC_CCSTAT_QUEACTV3_SHIFT (19U)
2231 #define CSL_EVETPCC_CCSTAT_QUEACTV3_RESETVAL (0x00000000U)
2232 #define CSL_EVETPCC_CCSTAT_QUEACTV3_MAX (0x00000001U)
2234 #define CSL_EVETPCC_CCSTAT_QUEACTV4_MASK (0x00100000U)
2235 #define CSL_EVETPCC_CCSTAT_QUEACTV4_SHIFT (20U)
2236 #define CSL_EVETPCC_CCSTAT_QUEACTV4_RESETVAL (0x00000000U)
2237 #define CSL_EVETPCC_CCSTAT_QUEACTV4_MAX (0x00000001U)
2239 #define CSL_EVETPCC_CCSTAT_QUEACTV5_MASK (0x00200000U)
2240 #define CSL_EVETPCC_CCSTAT_QUEACTV5_SHIFT (21U)
2241 #define CSL_EVETPCC_CCSTAT_QUEACTV5_RESETVAL (0x00000000U)
2242 #define CSL_EVETPCC_CCSTAT_QUEACTV5_MAX (0x00000001U)
2244 #define CSL_EVETPCC_CCSTAT_QUEACTV6_MASK (0x00400000U)
2245 #define CSL_EVETPCC_CCSTAT_QUEACTV6_SHIFT (22U)
2246 #define CSL_EVETPCC_CCSTAT_QUEACTV6_RESETVAL (0x00000000U)
2247 #define CSL_EVETPCC_CCSTAT_QUEACTV6_MAX (0x00000001U)
2249 #define CSL_EVETPCC_CCSTAT_QUEACTV7_MASK (0x00800000U)
2250 #define CSL_EVETPCC_CCSTAT_QUEACTV7_SHIFT (23U)
2251 #define CSL_EVETPCC_CCSTAT_QUEACTV7_RESETVAL (0x00000000U)
2252 #define CSL_EVETPCC_CCSTAT_QUEACTV7_MAX (0x00000001U)
2254 #define CSL_EVETPCC_CCSTAT_RESETVAL (0x00000000U)
2256 /* AETCTL */
2258 #define CSL_EVETPCC_AETCTL_TYPE_MASK (0x00000040U)
2259 #define CSL_EVETPCC_AETCTL_TYPE_SHIFT (6U)
2260 #define CSL_EVETPCC_AETCTL_TYPE_RESETVAL (0x00000000U)
2261 #define CSL_EVETPCC_AETCTL_TYPE_MAX (0x00000001U)
2263 #define CSL_EVETPCC_AETCTL_STRTEVT_MASK (0x0000003FU)
2264 #define CSL_EVETPCC_AETCTL_STRTEVT_SHIFT (0U)
2265 #define CSL_EVETPCC_AETCTL_STRTEVT_RESETVAL (0x00000000U)
2266 #define CSL_EVETPCC_AETCTL_STRTEVT_MAX (0x0000003fU)
2268 #define CSL_EVETPCC_AETCTL_EN_MASK (0x80000000U)
2269 #define CSL_EVETPCC_AETCTL_EN_SHIFT (31U)
2270 #define CSL_EVETPCC_AETCTL_EN_RESETVAL (0x00000000U)
2271 #define CSL_EVETPCC_AETCTL_EN_MAX (0x00000001U)
2273 #define CSL_EVETPCC_AETCTL_ENDINT_MASK (0x00003F00U)
2274 #define CSL_EVETPCC_AETCTL_ENDINT_SHIFT (8U)
2275 #define CSL_EVETPCC_AETCTL_ENDINT_RESETVAL (0x00000000U)
2276 #define CSL_EVETPCC_AETCTL_ENDINT_MAX (0x0000003fU)
2278 #define CSL_EVETPCC_AETCTL_RESETVAL (0x00000000U)
2280 /* AETSTAT */
2282 #define CSL_EVETPCC_AETSTAT_STAT_MASK (0x00000001U)
2283 #define CSL_EVETPCC_AETSTAT_STAT_SHIFT (0U)
2284 #define CSL_EVETPCC_AETSTAT_STAT_RESETVAL (0x00000000U)
2285 #define CSL_EVETPCC_AETSTAT_STAT_MAX (0x00000001U)
2287 #define CSL_EVETPCC_AETSTAT_RESETVAL (0x00000000U)
2289 /* AETCMD */
2291 #define CSL_EVETPCC_AETCMD_CLR_MASK (0x00000001U)
2292 #define CSL_EVETPCC_AETCMD_CLR_SHIFT (0U)
2293 #define CSL_EVETPCC_AETCMD_CLR_RESETVAL (0x00000000U)
2294 #define CSL_EVETPCC_AETCMD_CLR_MAX (0x00000001U)
2296 #define CSL_EVETPCC_AETCMD_RESETVAL (0x00000000U)
2298 /* MPFAR */
2300 #define CSL_EVETPCC_MPFAR_FADDR_MASK (0xFFFFFFFFU)
2301 #define CSL_EVETPCC_MPFAR_FADDR_SHIFT (0U)
2302 #define CSL_EVETPCC_MPFAR_FADDR_RESETVAL (0x00000000U)
2303 #define CSL_EVETPCC_MPFAR_FADDR_MAX (0xffffffffU)
2305 #define CSL_EVETPCC_MPFAR_RESETVAL (0x00000000U)
2307 /* MPFSR */
2309 #define CSL_EVETPCC_MPFSR_FID_MASK (0x00001E00U)
2310 #define CSL_EVETPCC_MPFSR_FID_SHIFT (9U)
2311 #define CSL_EVETPCC_MPFSR_FID_RESETVAL (0x00000000U)
2312 #define CSL_EVETPCC_MPFSR_FID_MAX (0x0000000fU)
2314 #define CSL_EVETPCC_MPFSR_SECE_MASK (0x00000080U)
2315 #define CSL_EVETPCC_MPFSR_SECE_SHIFT (7U)
2316 #define CSL_EVETPCC_MPFSR_SECE_RESETVAL (0x00000000U)
2317 #define CSL_EVETPCC_MPFSR_SECE_MAX (0x00000001U)
2319 #define CSL_EVETPCC_MPFSR_SXE_MASK (0x00000008U)
2320 #define CSL_EVETPCC_MPFSR_SXE_SHIFT (3U)
2321 #define CSL_EVETPCC_MPFSR_SXE_RESETVAL (0x00000000U)
2322 #define CSL_EVETPCC_MPFSR_SXE_MAX (0x00000001U)
2324 #define CSL_EVETPCC_MPFSR_URE_MASK (0x00000004U)
2325 #define CSL_EVETPCC_MPFSR_URE_SHIFT (2U)
2326 #define CSL_EVETPCC_MPFSR_URE_RESETVAL (0x00000000U)
2327 #define CSL_EVETPCC_MPFSR_URE_MAX (0x00000001U)
2329 #define CSL_EVETPCC_MPFSR_SRE_MASK (0x00000020U)
2330 #define CSL_EVETPCC_MPFSR_SRE_SHIFT (5U)
2331 #define CSL_EVETPCC_MPFSR_SRE_RESETVAL (0x00000000U)
2332 #define CSL_EVETPCC_MPFSR_SRE_MAX (0x00000001U)
2334 #define CSL_EVETPCC_MPFSR_SWE_MASK (0x00000010U)
2335 #define CSL_EVETPCC_MPFSR_SWE_SHIFT (4U)
2336 #define CSL_EVETPCC_MPFSR_SWE_RESETVAL (0x00000000U)
2337 #define CSL_EVETPCC_MPFSR_SWE_MAX (0x00000001U)
2339 #define CSL_EVETPCC_MPFSR_UWE_MASK (0x00000002U)
2340 #define CSL_EVETPCC_MPFSR_UWE_SHIFT (1U)
2341 #define CSL_EVETPCC_MPFSR_UWE_RESETVAL (0x00000000U)
2342 #define CSL_EVETPCC_MPFSR_UWE_MAX (0x00000001U)
2344 #define CSL_EVETPCC_MPFSR_UXE_MASK (0x00000001U)
2345 #define CSL_EVETPCC_MPFSR_UXE_SHIFT (0U)
2346 #define CSL_EVETPCC_MPFSR_UXE_RESETVAL (0x00000000U)
2347 #define CSL_EVETPCC_MPFSR_UXE_MAX (0x00000001U)
2349 #define CSL_EVETPCC_MPFSR_RESETVAL (0x00000000U)
2351 /* MPFCR */
2353 #define CSL_EVETPCC_MPFCR_MPFCLR_MASK (0x00000001U)
2354 #define CSL_EVETPCC_MPFCR_MPFCLR_SHIFT (0U)
2355 #define CSL_EVETPCC_MPFCR_MPFCLR_RESETVAL (0x00000000U)
2356 #define CSL_EVETPCC_MPFCR_MPFCLR_MAX (0x00000001U)
2358 #define CSL_EVETPCC_MPFCR_RESETVAL (0x00000000U)
2360 /* MPPAG */
2362 #define CSL_EVETPCC_MPPAG_EMU_MASK (0x00000040U)
2363 #define CSL_EVETPCC_MPPAG_EMU_SHIFT (6U)
2364 #define CSL_EVETPCC_MPPAG_EMU_RESETVAL (0x00000001U)
2365 #define CSL_EVETPCC_MPPAG_EMU_MAX (0x00000001U)
2367 #define CSL_EVETPCC_MPPAG_EXT_MASK (0x00000200U)
2368 #define CSL_EVETPCC_MPPAG_EXT_SHIFT (9U)
2369 #define CSL_EVETPCC_MPPAG_EXT_RESETVAL (0x00000001U)
2370 #define CSL_EVETPCC_MPPAG_EXT_MAX (0x00000001U)
2372 #define CSL_EVETPCC_MPPAG_SR_MASK (0x00000020U)
2373 #define CSL_EVETPCC_MPPAG_SR_SHIFT (5U)
2374 #define CSL_EVETPCC_MPPAG_SR_RESETVAL (0x00000001U)
2375 #define CSL_EVETPCC_MPPAG_SR_MAX (0x00000001U)
2377 #define CSL_EVETPCC_MPPAG_AID4_MASK (0x00004000U)
2378 #define CSL_EVETPCC_MPPAG_AID4_SHIFT (14U)
2379 #define CSL_EVETPCC_MPPAG_AID4_RESETVAL (0x00000001U)
2380 #define CSL_EVETPCC_MPPAG_AID4_MAX (0x00000001U)
2382 #define CSL_EVETPCC_MPPAG_UR_MASK (0x00000004U)
2383 #define CSL_EVETPCC_MPPAG_UR_SHIFT (2U)
2384 #define CSL_EVETPCC_MPPAG_UR_RESETVAL (0x00000001U)
2385 #define CSL_EVETPCC_MPPAG_UR_MAX (0x00000001U)
2387 #define CSL_EVETPCC_MPPAG_AID5_MASK (0x00008000U)
2388 #define CSL_EVETPCC_MPPAG_AID5_SHIFT (15U)
2389 #define CSL_EVETPCC_MPPAG_AID5_RESETVAL (0x00000001U)
2390 #define CSL_EVETPCC_MPPAG_AID5_MAX (0x00000001U)
2392 #define CSL_EVETPCC_MPPAG_NS_MASK (0x00000080U)
2393 #define CSL_EVETPCC_MPPAG_NS_SHIFT (7U)
2394 #define CSL_EVETPCC_MPPAG_NS_RESETVAL (0x00000001U)
2395 #define CSL_EVETPCC_MPPAG_NS_MAX (0x00000001U)
2397 #define CSL_EVETPCC_MPPAG_SW_MASK (0x00000010U)
2398 #define CSL_EVETPCC_MPPAG_SW_SHIFT (4U)
2399 #define CSL_EVETPCC_MPPAG_SW_RESETVAL (0x00000001U)
2400 #define CSL_EVETPCC_MPPAG_SW_MAX (0x00000001U)
2402 #define CSL_EVETPCC_MPPAG_UW_MASK (0x00000002U)
2403 #define CSL_EVETPCC_MPPAG_UW_SHIFT (1U)
2404 #define CSL_EVETPCC_MPPAG_UW_RESETVAL (0x00000001U)
2405 #define CSL_EVETPCC_MPPAG_UW_MAX (0x00000001U)
2407 #define CSL_EVETPCC_MPPAG_AID0_MASK (0x00000400U)
2408 #define CSL_EVETPCC_MPPAG_AID0_SHIFT (10U)
2409 #define CSL_EVETPCC_MPPAG_AID0_RESETVAL (0x00000001U)
2410 #define CSL_EVETPCC_MPPAG_AID0_MAX (0x00000001U)
2412 #define CSL_EVETPCC_MPPAG_AID1_MASK (0x00000800U)
2413 #define CSL_EVETPCC_MPPAG_AID1_SHIFT (11U)
2414 #define CSL_EVETPCC_MPPAG_AID1_RESETVAL (0x00000001U)
2415 #define CSL_EVETPCC_MPPAG_AID1_MAX (0x00000001U)
2417 #define CSL_EVETPCC_MPPAG_SX_MASK (0x00000008U)
2418 #define CSL_EVETPCC_MPPAG_SX_SHIFT (3U)
2419 #define CSL_EVETPCC_MPPAG_SX_RESETVAL (0x00000000U)
2420 #define CSL_EVETPCC_MPPAG_SX_MAX (0x00000001U)
2422 #define CSL_EVETPCC_MPPAG_AID2_MASK (0x00001000U)
2423 #define CSL_EVETPCC_MPPAG_AID2_SHIFT (12U)
2424 #define CSL_EVETPCC_MPPAG_AID2_RESETVAL (0x00000001U)
2425 #define CSL_EVETPCC_MPPAG_AID2_MAX (0x00000001U)
2427 #define CSL_EVETPCC_MPPAG_UX_MASK (0x00000001U)
2428 #define CSL_EVETPCC_MPPAG_UX_SHIFT (0U)
2429 #define CSL_EVETPCC_MPPAG_UX_RESETVAL (0x00000000U)
2430 #define CSL_EVETPCC_MPPAG_UX_MAX (0x00000001U)
2432 #define CSL_EVETPCC_MPPAG_AID3_MASK (0x00002000U)
2433 #define CSL_EVETPCC_MPPAG_AID3_SHIFT (13U)
2434 #define CSL_EVETPCC_MPPAG_AID3_RESETVAL (0x00000001U)
2435 #define CSL_EVETPCC_MPPAG_AID3_MAX (0x00000001U)
2437 #define CSL_EVETPCC_MPPAG_RESETVAL (0x0000fff6U)
2439 /* MPPAN */
2441 #define CSL_EVETPCC_MPPAN_AID5_MASK (0x00008000U)
2442 #define CSL_EVETPCC_MPPAN_AID5_SHIFT (15U)
2443 #define CSL_EVETPCC_MPPAN_AID5_RESETVAL (0x00000001U)
2444 #define CSL_EVETPCC_MPPAN_AID5_MAX (0x00000001U)
2446 #define CSL_EVETPCC_MPPAN_AID4_MASK (0x00004000U)
2447 #define CSL_EVETPCC_MPPAN_AID4_SHIFT (14U)
2448 #define CSL_EVETPCC_MPPAN_AID4_RESETVAL (0x00000001U)
2449 #define CSL_EVETPCC_MPPAN_AID4_MAX (0x00000001U)
2451 #define CSL_EVETPCC_MPPAN_AID3_MASK (0x00002000U)
2452 #define CSL_EVETPCC_MPPAN_AID3_SHIFT (13U)
2453 #define CSL_EVETPCC_MPPAN_AID3_RESETVAL (0x00000001U)
2454 #define CSL_EVETPCC_MPPAN_AID3_MAX (0x00000001U)
2456 #define CSL_EVETPCC_MPPAN_AID2_MASK (0x00001000U)
2457 #define CSL_EVETPCC_MPPAN_AID2_SHIFT (12U)
2458 #define CSL_EVETPCC_MPPAN_AID2_RESETVAL (0x00000001U)
2459 #define CSL_EVETPCC_MPPAN_AID2_MAX (0x00000001U)
2461 #define CSL_EVETPCC_MPPAN_AID1_MASK (0x00000800U)
2462 #define CSL_EVETPCC_MPPAN_AID1_SHIFT (11U)
2463 #define CSL_EVETPCC_MPPAN_AID1_RESETVAL (0x00000001U)
2464 #define CSL_EVETPCC_MPPAN_AID1_MAX (0x00000001U)
2466 #define CSL_EVETPCC_MPPAN_AID0_MASK (0x00000400U)
2467 #define CSL_EVETPCC_MPPAN_AID0_SHIFT (10U)
2468 #define CSL_EVETPCC_MPPAN_AID0_RESETVAL (0x00000001U)
2469 #define CSL_EVETPCC_MPPAN_AID0_MAX (0x00000001U)
2471 #define CSL_EVETPCC_MPPAN_EXT_MASK (0x00000200U)
2472 #define CSL_EVETPCC_MPPAN_EXT_SHIFT (9U)
2473 #define CSL_EVETPCC_MPPAN_EXT_RESETVAL (0x00000001U)
2474 #define CSL_EVETPCC_MPPAN_EXT_MAX (0x00000001U)
2476 #define CSL_EVETPCC_MPPAN_NS_MASK (0x00000080U)
2477 #define CSL_EVETPCC_MPPAN_NS_SHIFT (7U)
2478 #define CSL_EVETPCC_MPPAN_NS_RESETVAL (0x00000001U)
2479 #define CSL_EVETPCC_MPPAN_NS_MAX (0x00000001U)
2481 #define CSL_EVETPCC_MPPAN_EMU_MASK (0x00000040U)
2482 #define CSL_EVETPCC_MPPAN_EMU_SHIFT (6U)
2483 #define CSL_EVETPCC_MPPAN_EMU_RESETVAL (0x00000001U)
2484 #define CSL_EVETPCC_MPPAN_EMU_MAX (0x00000001U)
2486 #define CSL_EVETPCC_MPPAN_SR_MASK (0x00000020U)
2487 #define CSL_EVETPCC_MPPAN_SR_SHIFT (5U)
2488 #define CSL_EVETPCC_MPPAN_SR_RESETVAL (0x00000001U)
2489 #define CSL_EVETPCC_MPPAN_SR_MAX (0x00000001U)
2491 #define CSL_EVETPCC_MPPAN_SW_MASK (0x00000010U)
2492 #define CSL_EVETPCC_MPPAN_SW_SHIFT (4U)
2493 #define CSL_EVETPCC_MPPAN_SW_RESETVAL (0x00000001U)
2494 #define CSL_EVETPCC_MPPAN_SW_MAX (0x00000001U)
2496 #define CSL_EVETPCC_MPPAN_SX_MASK (0x00000008U)
2497 #define CSL_EVETPCC_MPPAN_SX_SHIFT (3U)
2498 #define CSL_EVETPCC_MPPAN_SX_RESETVAL (0x00000000U)
2499 #define CSL_EVETPCC_MPPAN_SX_MAX (0x00000001U)
2501 #define CSL_EVETPCC_MPPAN_UR_MASK (0x00000004U)
2502 #define CSL_EVETPCC_MPPAN_UR_SHIFT (2U)
2503 #define CSL_EVETPCC_MPPAN_UR_RESETVAL (0x00000001U)
2504 #define CSL_EVETPCC_MPPAN_UR_MAX (0x00000001U)
2506 #define CSL_EVETPCC_MPPAN_UW_MASK (0x00000002U)
2507 #define CSL_EVETPCC_MPPAN_UW_SHIFT (1U)
2508 #define CSL_EVETPCC_MPPAN_UW_RESETVAL (0x00000001U)
2509 #define CSL_EVETPCC_MPPAN_UW_MAX (0x00000001U)
2511 #define CSL_EVETPCC_MPPAN_UX_MASK (0x00000001U)
2512 #define CSL_EVETPCC_MPPAN_UX_SHIFT (0U)
2513 #define CSL_EVETPCC_MPPAN_UX_RESETVAL (0x00000000U)
2514 #define CSL_EVETPCC_MPPAN_UX_MAX (0x00000001U)
2516 #define CSL_EVETPCC_MPPAN_RESETVAL (0x0000fef6U)
2518 /* ER */
2520 #define CSL_EVETPCC_ER_E22_MASK (0x00400000U)
2521 #define CSL_EVETPCC_ER_E22_SHIFT (22U)
2522 #define CSL_EVETPCC_ER_E22_RESETVAL (0x00000000U)
2523 #define CSL_EVETPCC_ER_E22_MAX (0x00000001U)
2525 #define CSL_EVETPCC_ER_E2_MASK (0x00000004U)
2526 #define CSL_EVETPCC_ER_E2_SHIFT (2U)
2527 #define CSL_EVETPCC_ER_E2_RESETVAL (0x00000000U)
2528 #define CSL_EVETPCC_ER_E2_MAX (0x00000001U)
2530 #define CSL_EVETPCC_ER_E19_MASK (0x00080000U)
2531 #define CSL_EVETPCC_ER_E19_SHIFT (19U)
2532 #define CSL_EVETPCC_ER_E19_RESETVAL (0x00000000U)
2533 #define CSL_EVETPCC_ER_E19_MAX (0x00000001U)
2535 #define CSL_EVETPCC_ER_E5_MASK (0x00000020U)
2536 #define CSL_EVETPCC_ER_E5_SHIFT (5U)
2537 #define CSL_EVETPCC_ER_E5_RESETVAL (0x00000000U)
2538 #define CSL_EVETPCC_ER_E5_MAX (0x00000001U)
2540 #define CSL_EVETPCC_ER_E29_MASK (0x20000000U)
2541 #define CSL_EVETPCC_ER_E29_SHIFT (29U)
2542 #define CSL_EVETPCC_ER_E29_RESETVAL (0x00000000U)
2543 #define CSL_EVETPCC_ER_E29_MAX (0x00000001U)
2545 #define CSL_EVETPCC_ER_E18_MASK (0x00040000U)
2546 #define CSL_EVETPCC_ER_E18_SHIFT (18U)
2547 #define CSL_EVETPCC_ER_E18_RESETVAL (0x00000000U)
2548 #define CSL_EVETPCC_ER_E18_MAX (0x00000001U)
2550 #define CSL_EVETPCC_ER_E6_MASK (0x00000040U)
2551 #define CSL_EVETPCC_ER_E6_SHIFT (6U)
2552 #define CSL_EVETPCC_ER_E6_RESETVAL (0x00000000U)
2553 #define CSL_EVETPCC_ER_E6_MAX (0x00000001U)
2555 #define CSL_EVETPCC_ER_E21_MASK (0x00200000U)
2556 #define CSL_EVETPCC_ER_E21_SHIFT (21U)
2557 #define CSL_EVETPCC_ER_E21_RESETVAL (0x00000000U)
2558 #define CSL_EVETPCC_ER_E21_MAX (0x00000001U)
2560 #define CSL_EVETPCC_ER_E3_MASK (0x00000008U)
2561 #define CSL_EVETPCC_ER_E3_SHIFT (3U)
2562 #define CSL_EVETPCC_ER_E3_RESETVAL (0x00000000U)
2563 #define CSL_EVETPCC_ER_E3_MAX (0x00000001U)
2565 #define CSL_EVETPCC_ER_E31_MASK (0x80000000U)
2566 #define CSL_EVETPCC_ER_E31_SHIFT (31U)
2567 #define CSL_EVETPCC_ER_E31_RESETVAL (0x00000000U)
2568 #define CSL_EVETPCC_ER_E31_MAX (0x00000001U)
2570 #define CSL_EVETPCC_ER_E20_MASK (0x00100000U)
2571 #define CSL_EVETPCC_ER_E20_SHIFT (20U)
2572 #define CSL_EVETPCC_ER_E20_RESETVAL (0x00000000U)
2573 #define CSL_EVETPCC_ER_E20_MAX (0x00000001U)
2575 #define CSL_EVETPCC_ER_E4_MASK (0x00000010U)
2576 #define CSL_EVETPCC_ER_E4_SHIFT (4U)
2577 #define CSL_EVETPCC_ER_E4_RESETVAL (0x00000000U)
2578 #define CSL_EVETPCC_ER_E4_MAX (0x00000001U)
2580 #define CSL_EVETPCC_ER_E9_MASK (0x00000200U)
2581 #define CSL_EVETPCC_ER_E9_SHIFT (9U)
2582 #define CSL_EVETPCC_ER_E9_RESETVAL (0x00000000U)
2583 #define CSL_EVETPCC_ER_E9_MAX (0x00000001U)
2585 #define CSL_EVETPCC_ER_E28_MASK (0x10000000U)
2586 #define CSL_EVETPCC_ER_E28_SHIFT (28U)
2587 #define CSL_EVETPCC_ER_E28_RESETVAL (0x00000000U)
2588 #define CSL_EVETPCC_ER_E28_MAX (0x00000001U)
2590 #define CSL_EVETPCC_ER_E14_MASK (0x00004000U)
2591 #define CSL_EVETPCC_ER_E14_SHIFT (14U)
2592 #define CSL_EVETPCC_ER_E14_RESETVAL (0x00000000U)
2593 #define CSL_EVETPCC_ER_E14_MAX (0x00000001U)
2595 #define CSL_EVETPCC_ER_E10_MASK (0x00000400U)
2596 #define CSL_EVETPCC_ER_E10_SHIFT (10U)
2597 #define CSL_EVETPCC_ER_E10_RESETVAL (0x00000000U)
2598 #define CSL_EVETPCC_ER_E10_MAX (0x00000001U)
2600 #define CSL_EVETPCC_ER_E27_MASK (0x08000000U)
2601 #define CSL_EVETPCC_ER_E27_SHIFT (27U)
2602 #define CSL_EVETPCC_ER_E27_RESETVAL (0x00000000U)
2603 #define CSL_EVETPCC_ER_E27_MAX (0x00000001U)
2605 #define CSL_EVETPCC_ER_E7_MASK (0x00000080U)
2606 #define CSL_EVETPCC_ER_E7_SHIFT (7U)
2607 #define CSL_EVETPCC_ER_E7_RESETVAL (0x00000000U)
2608 #define CSL_EVETPCC_ER_E7_MAX (0x00000001U)
2610 #define CSL_EVETPCC_ER_E17_MASK (0x00020000U)
2611 #define CSL_EVETPCC_ER_E17_SHIFT (17U)
2612 #define CSL_EVETPCC_ER_E17_RESETVAL (0x00000000U)
2613 #define CSL_EVETPCC_ER_E17_MAX (0x00000001U)
2615 #define CSL_EVETPCC_ER_E8_MASK (0x00000100U)
2616 #define CSL_EVETPCC_ER_E8_SHIFT (8U)
2617 #define CSL_EVETPCC_ER_E8_RESETVAL (0x00000000U)
2618 #define CSL_EVETPCC_ER_E8_MAX (0x00000001U)
2620 #define CSL_EVETPCC_ER_E16_MASK (0x00010000U)
2621 #define CSL_EVETPCC_ER_E16_SHIFT (16U)
2622 #define CSL_EVETPCC_ER_E16_RESETVAL (0x00000000U)
2623 #define CSL_EVETPCC_ER_E16_MAX (0x00000001U)
2625 #define CSL_EVETPCC_ER_E30_MASK (0x40000000U)
2626 #define CSL_EVETPCC_ER_E30_SHIFT (30U)
2627 #define CSL_EVETPCC_ER_E30_RESETVAL (0x00000000U)
2628 #define CSL_EVETPCC_ER_E30_MAX (0x00000001U)
2630 #define CSL_EVETPCC_ER_E24_MASK (0x01000000U)
2631 #define CSL_EVETPCC_ER_E24_SHIFT (24U)
2632 #define CSL_EVETPCC_ER_E24_RESETVAL (0x00000000U)
2633 #define CSL_EVETPCC_ER_E24_MAX (0x00000001U)
2635 #define CSL_EVETPCC_ER_E23_MASK (0x00800000U)
2636 #define CSL_EVETPCC_ER_E23_SHIFT (23U)
2637 #define CSL_EVETPCC_ER_E23_RESETVAL (0x00000000U)
2638 #define CSL_EVETPCC_ER_E23_MAX (0x00000001U)
2640 #define CSL_EVETPCC_ER_E0_MASK (0x00000001U)
2641 #define CSL_EVETPCC_ER_E0_SHIFT (0U)
2642 #define CSL_EVETPCC_ER_E0_RESETVAL (0x00000000U)
2643 #define CSL_EVETPCC_ER_E0_MAX (0x00000001U)
2645 #define CSL_EVETPCC_ER_E13_MASK (0x00002000U)
2646 #define CSL_EVETPCC_ER_E13_SHIFT (13U)
2647 #define CSL_EVETPCC_ER_E13_RESETVAL (0x00000000U)
2648 #define CSL_EVETPCC_ER_E13_MAX (0x00000001U)
2650 #define CSL_EVETPCC_ER_E11_MASK (0x00000800U)
2651 #define CSL_EVETPCC_ER_E11_SHIFT (11U)
2652 #define CSL_EVETPCC_ER_E11_RESETVAL (0x00000000U)
2653 #define CSL_EVETPCC_ER_E11_MAX (0x00000001U)
2655 #define CSL_EVETPCC_ER_E26_MASK (0x04000000U)
2656 #define CSL_EVETPCC_ER_E26_SHIFT (26U)
2657 #define CSL_EVETPCC_ER_E26_RESETVAL (0x00000000U)
2658 #define CSL_EVETPCC_ER_E26_MAX (0x00000001U)
2660 #define CSL_EVETPCC_ER_E1_MASK (0x00000002U)
2661 #define CSL_EVETPCC_ER_E1_SHIFT (1U)
2662 #define CSL_EVETPCC_ER_E1_RESETVAL (0x00000000U)
2663 #define CSL_EVETPCC_ER_E1_MAX (0x00000001U)
2665 #define CSL_EVETPCC_ER_E12_MASK (0x00001000U)
2666 #define CSL_EVETPCC_ER_E12_SHIFT (12U)
2667 #define CSL_EVETPCC_ER_E12_RESETVAL (0x00000000U)
2668 #define CSL_EVETPCC_ER_E12_MAX (0x00000001U)
2670 #define CSL_EVETPCC_ER_E25_MASK (0x02000000U)
2671 #define CSL_EVETPCC_ER_E25_SHIFT (25U)
2672 #define CSL_EVETPCC_ER_E25_RESETVAL (0x00000000U)
2673 #define CSL_EVETPCC_ER_E25_MAX (0x00000001U)
2675 #define CSL_EVETPCC_ER_E15_MASK (0x00008000U)
2676 #define CSL_EVETPCC_ER_E15_SHIFT (15U)
2677 #define CSL_EVETPCC_ER_E15_RESETVAL (0x00000000U)
2678 #define CSL_EVETPCC_ER_E15_MAX (0x00000001U)
2680 #define CSL_EVETPCC_ER_RESETVAL (0x00000000U)
2682 /* ERH */
2684 #define CSL_EVETPCC_ERH_E61_MASK (0x20000000U)
2685 #define CSL_EVETPCC_ERH_E61_SHIFT (29U)
2686 #define CSL_EVETPCC_ERH_E61_RESETVAL (0x00000000U)
2687 #define CSL_EVETPCC_ERH_E61_MAX (0x00000001U)
2689 #define CSL_EVETPCC_ERH_E54_MASK (0x00400000U)
2690 #define CSL_EVETPCC_ERH_E54_SHIFT (22U)
2691 #define CSL_EVETPCC_ERH_E54_RESETVAL (0x00000000U)
2692 #define CSL_EVETPCC_ERH_E54_MAX (0x00000001U)
2694 #define CSL_EVETPCC_ERH_E55_MASK (0x00800000U)
2695 #define CSL_EVETPCC_ERH_E55_SHIFT (23U)
2696 #define CSL_EVETPCC_ERH_E55_RESETVAL (0x00000000U)
2697 #define CSL_EVETPCC_ERH_E55_MAX (0x00000001U)
2699 #define CSL_EVETPCC_ERH_E59_MASK (0x08000000U)
2700 #define CSL_EVETPCC_ERH_E59_SHIFT (27U)
2701 #define CSL_EVETPCC_ERH_E59_RESETVAL (0x00000000U)
2702 #define CSL_EVETPCC_ERH_E59_MAX (0x00000001U)
2704 #define CSL_EVETPCC_ERH_E50_MASK (0x00040000U)
2705 #define CSL_EVETPCC_ERH_E50_SHIFT (18U)
2706 #define CSL_EVETPCC_ERH_E50_RESETVAL (0x00000000U)
2707 #define CSL_EVETPCC_ERH_E50_MAX (0x00000001U)
2709 #define CSL_EVETPCC_ERH_E52_MASK (0x00100000U)
2710 #define CSL_EVETPCC_ERH_E52_SHIFT (20U)
2711 #define CSL_EVETPCC_ERH_E52_RESETVAL (0x00000000U)
2712 #define CSL_EVETPCC_ERH_E52_MAX (0x00000001U)
2714 #define CSL_EVETPCC_ERH_E53_MASK (0x00200000U)
2715 #define CSL_EVETPCC_ERH_E53_SHIFT (21U)
2716 #define CSL_EVETPCC_ERH_E53_RESETVAL (0x00000000U)
2717 #define CSL_EVETPCC_ERH_E53_MAX (0x00000001U)
2719 #define CSL_EVETPCC_ERH_E51_MASK (0x00080000U)
2720 #define CSL_EVETPCC_ERH_E51_SHIFT (19U)
2721 #define CSL_EVETPCC_ERH_E51_RESETVAL (0x00000000U)
2722 #define CSL_EVETPCC_ERH_E51_MAX (0x00000001U)
2724 #define CSL_EVETPCC_ERH_E36_MASK (0x00000010U)
2725 #define CSL_EVETPCC_ERH_E36_SHIFT (4U)
2726 #define CSL_EVETPCC_ERH_E36_RESETVAL (0x00000000U)
2727 #define CSL_EVETPCC_ERH_E36_MAX (0x00000001U)
2729 #define CSL_EVETPCC_ERH_E40_MASK (0x00000100U)
2730 #define CSL_EVETPCC_ERH_E40_SHIFT (8U)
2731 #define CSL_EVETPCC_ERH_E40_RESETVAL (0x00000000U)
2732 #define CSL_EVETPCC_ERH_E40_MAX (0x00000001U)
2734 #define CSL_EVETPCC_ERH_E39_MASK (0x00000080U)
2735 #define CSL_EVETPCC_ERH_E39_SHIFT (7U)
2736 #define CSL_EVETPCC_ERH_E39_RESETVAL (0x00000000U)
2737 #define CSL_EVETPCC_ERH_E39_MAX (0x00000001U)
2739 #define CSL_EVETPCC_ERH_E38_MASK (0x00000040U)
2740 #define CSL_EVETPCC_ERH_E38_SHIFT (6U)
2741 #define CSL_EVETPCC_ERH_E38_RESETVAL (0x00000000U)
2742 #define CSL_EVETPCC_ERH_E38_MAX (0x00000001U)
2744 #define CSL_EVETPCC_ERH_E42_MASK (0x00000400U)
2745 #define CSL_EVETPCC_ERH_E42_SHIFT (10U)
2746 #define CSL_EVETPCC_ERH_E42_RESETVAL (0x00000000U)
2747 #define CSL_EVETPCC_ERH_E42_MAX (0x00000001U)
2749 #define CSL_EVETPCC_ERH_E49_MASK (0x00020000U)
2750 #define CSL_EVETPCC_ERH_E49_SHIFT (17U)
2751 #define CSL_EVETPCC_ERH_E49_RESETVAL (0x00000000U)
2752 #define CSL_EVETPCC_ERH_E49_MAX (0x00000001U)
2754 #define CSL_EVETPCC_ERH_E41_MASK (0x00000200U)
2755 #define CSL_EVETPCC_ERH_E41_SHIFT (9U)
2756 #define CSL_EVETPCC_ERH_E41_RESETVAL (0x00000000U)
2757 #define CSL_EVETPCC_ERH_E41_MAX (0x00000001U)
2759 #define CSL_EVETPCC_ERH_E32_MASK (0x00000001U)
2760 #define CSL_EVETPCC_ERH_E32_SHIFT (0U)
2761 #define CSL_EVETPCC_ERH_E32_RESETVAL (0x00000000U)
2762 #define CSL_EVETPCC_ERH_E32_MAX (0x00000001U)
2764 #define CSL_EVETPCC_ERH_E35_MASK (0x00000008U)
2765 #define CSL_EVETPCC_ERH_E35_SHIFT (3U)
2766 #define CSL_EVETPCC_ERH_E35_RESETVAL (0x00000000U)
2767 #define CSL_EVETPCC_ERH_E35_MAX (0x00000001U)
2769 #define CSL_EVETPCC_ERH_E43_MASK (0x00000800U)
2770 #define CSL_EVETPCC_ERH_E43_SHIFT (11U)
2771 #define CSL_EVETPCC_ERH_E43_RESETVAL (0x00000000U)
2772 #define CSL_EVETPCC_ERH_E43_MAX (0x00000001U)
2774 #define CSL_EVETPCC_ERH_E34_MASK (0x00000004U)
2775 #define CSL_EVETPCC_ERH_E34_SHIFT (2U)
2776 #define CSL_EVETPCC_ERH_E34_RESETVAL (0x00000000U)
2777 #define CSL_EVETPCC_ERH_E34_MAX (0x00000001U)
2779 #define CSL_EVETPCC_ERH_E44_MASK (0x00001000U)
2780 #define CSL_EVETPCC_ERH_E44_SHIFT (12U)
2781 #define CSL_EVETPCC_ERH_E44_RESETVAL (0x00000000U)
2782 #define CSL_EVETPCC_ERH_E44_MAX (0x00000001U)
2784 #define CSL_EVETPCC_ERH_E37_MASK (0x00000020U)
2785 #define CSL_EVETPCC_ERH_E37_SHIFT (5U)
2786 #define CSL_EVETPCC_ERH_E37_RESETVAL (0x00000000U)
2787 #define CSL_EVETPCC_ERH_E37_MAX (0x00000001U)
2789 #define CSL_EVETPCC_ERH_E45_MASK (0x00002000U)
2790 #define CSL_EVETPCC_ERH_E45_SHIFT (13U)
2791 #define CSL_EVETPCC_ERH_E45_RESETVAL (0x00000000U)
2792 #define CSL_EVETPCC_ERH_E45_MAX (0x00000001U)
2794 #define CSL_EVETPCC_ERH_E58_MASK (0x04000000U)
2795 #define CSL_EVETPCC_ERH_E58_SHIFT (26U)
2796 #define CSL_EVETPCC_ERH_E58_RESETVAL (0x00000000U)
2797 #define CSL_EVETPCC_ERH_E58_MAX (0x00000001U)
2799 #define CSL_EVETPCC_ERH_E62_MASK (0x40000000U)
2800 #define CSL_EVETPCC_ERH_E62_SHIFT (30U)
2801 #define CSL_EVETPCC_ERH_E62_RESETVAL (0x00000000U)
2802 #define CSL_EVETPCC_ERH_E62_MAX (0x00000001U)
2804 #define CSL_EVETPCC_ERH_E46_MASK (0x00004000U)
2805 #define CSL_EVETPCC_ERH_E46_SHIFT (14U)
2806 #define CSL_EVETPCC_ERH_E46_RESETVAL (0x00000000U)
2807 #define CSL_EVETPCC_ERH_E46_MAX (0x00000001U)
2809 #define CSL_EVETPCC_ERH_E57_MASK (0x02000000U)
2810 #define CSL_EVETPCC_ERH_E57_SHIFT (25U)
2811 #define CSL_EVETPCC_ERH_E57_RESETVAL (0x00000000U)
2812 #define CSL_EVETPCC_ERH_E57_MAX (0x00000001U)
2814 #define CSL_EVETPCC_ERH_E63_MASK (0x80000000U)
2815 #define CSL_EVETPCC_ERH_E63_SHIFT (31U)
2816 #define CSL_EVETPCC_ERH_E63_RESETVAL (0x00000000U)
2817 #define CSL_EVETPCC_ERH_E63_MAX (0x00000001U)
2819 #define CSL_EVETPCC_ERH_E47_MASK (0x00008000U)
2820 #define CSL_EVETPCC_ERH_E47_SHIFT (15U)
2821 #define CSL_EVETPCC_ERH_E47_RESETVAL (0x00000000U)
2822 #define CSL_EVETPCC_ERH_E47_MAX (0x00000001U)
2824 #define CSL_EVETPCC_ERH_E56_MASK (0x01000000U)
2825 #define CSL_EVETPCC_ERH_E56_SHIFT (24U)
2826 #define CSL_EVETPCC_ERH_E56_RESETVAL (0x00000000U)
2827 #define CSL_EVETPCC_ERH_E56_MAX (0x00000001U)
2829 #define CSL_EVETPCC_ERH_E48_MASK (0x00010000U)
2830 #define CSL_EVETPCC_ERH_E48_SHIFT (16U)
2831 #define CSL_EVETPCC_ERH_E48_RESETVAL (0x00000000U)
2832 #define CSL_EVETPCC_ERH_E48_MAX (0x00000001U)
2834 #define CSL_EVETPCC_ERH_E33_MASK (0x00000002U)
2835 #define CSL_EVETPCC_ERH_E33_SHIFT (1U)
2836 #define CSL_EVETPCC_ERH_E33_RESETVAL (0x00000000U)
2837 #define CSL_EVETPCC_ERH_E33_MAX (0x00000001U)
2839 #define CSL_EVETPCC_ERH_E60_MASK (0x10000000U)
2840 #define CSL_EVETPCC_ERH_E60_SHIFT (28U)
2841 #define CSL_EVETPCC_ERH_E60_RESETVAL (0x00000000U)
2842 #define CSL_EVETPCC_ERH_E60_MAX (0x00000001U)
2844 #define CSL_EVETPCC_ERH_RESETVAL (0x00000000U)
2846 /* ECR */
2848 #define CSL_EVETPCC_ECR_E16_MASK (0x00010000U)
2849 #define CSL_EVETPCC_ECR_E16_SHIFT (16U)
2850 #define CSL_EVETPCC_ECR_E16_RESETVAL (0x00000000U)
2851 #define CSL_EVETPCC_ECR_E16_MAX (0x00000001U)
2853 #define CSL_EVETPCC_ECR_E10_MASK (0x00000400U)
2854 #define CSL_EVETPCC_ECR_E10_SHIFT (10U)
2855 #define CSL_EVETPCC_ECR_E10_RESETVAL (0x00000000U)
2856 #define CSL_EVETPCC_ECR_E10_MAX (0x00000001U)
2858 #define CSL_EVETPCC_ECR_E30_MASK (0x40000000U)
2859 #define CSL_EVETPCC_ECR_E30_SHIFT (30U)
2860 #define CSL_EVETPCC_ECR_E30_RESETVAL (0x00000000U)
2861 #define CSL_EVETPCC_ECR_E30_MAX (0x00000001U)
2863 #define CSL_EVETPCC_ECR_E19_MASK (0x00080000U)
2864 #define CSL_EVETPCC_ECR_E19_SHIFT (19U)
2865 #define CSL_EVETPCC_ECR_E19_RESETVAL (0x00000000U)
2866 #define CSL_EVETPCC_ECR_E19_MAX (0x00000001U)
2868 #define CSL_EVETPCC_ECR_E29_MASK (0x20000000U)
2869 #define CSL_EVETPCC_ECR_E29_SHIFT (29U)
2870 #define CSL_EVETPCC_ECR_E29_RESETVAL (0x00000000U)
2871 #define CSL_EVETPCC_ECR_E29_MAX (0x00000001U)
2873 #define CSL_EVETPCC_ECR_E12_MASK (0x00001000U)
2874 #define CSL_EVETPCC_ECR_E12_SHIFT (12U)
2875 #define CSL_EVETPCC_ECR_E12_RESETVAL (0x00000000U)
2876 #define CSL_EVETPCC_ECR_E12_MAX (0x00000001U)
2878 #define CSL_EVETPCC_ECR_E18_MASK (0x00040000U)
2879 #define CSL_EVETPCC_ECR_E18_SHIFT (18U)
2880 #define CSL_EVETPCC_ECR_E18_RESETVAL (0x00000000U)
2881 #define CSL_EVETPCC_ECR_E18_MAX (0x00000001U)
2883 #define CSL_EVETPCC_ECR_E11_MASK (0x00000800U)
2884 #define CSL_EVETPCC_ECR_E11_SHIFT (11U)
2885 #define CSL_EVETPCC_ECR_E11_RESETVAL (0x00000000U)
2886 #define CSL_EVETPCC_ECR_E11_MAX (0x00000001U)
2888 #define CSL_EVETPCC_ECR_E21_MASK (0x00200000U)
2889 #define CSL_EVETPCC_ECR_E21_SHIFT (21U)
2890 #define CSL_EVETPCC_ECR_E21_RESETVAL (0x00000000U)
2891 #define CSL_EVETPCC_ECR_E21_MAX (0x00000001U)
2893 #define CSL_EVETPCC_ECR_E31_MASK (0x80000000U)
2894 #define CSL_EVETPCC_ECR_E31_SHIFT (31U)
2895 #define CSL_EVETPCC_ECR_E31_RESETVAL (0x00000000U)
2896 #define CSL_EVETPCC_ECR_E31_MAX (0x00000001U)
2898 #define CSL_EVETPCC_ECR_E14_MASK (0x00004000U)
2899 #define CSL_EVETPCC_ECR_E14_SHIFT (14U)
2900 #define CSL_EVETPCC_ECR_E14_RESETVAL (0x00000000U)
2901 #define CSL_EVETPCC_ECR_E14_MAX (0x00000001U)
2903 #define CSL_EVETPCC_ECR_E26_MASK (0x04000000U)
2904 #define CSL_EVETPCC_ECR_E26_SHIFT (26U)
2905 #define CSL_EVETPCC_ECR_E26_RESETVAL (0x00000000U)
2906 #define CSL_EVETPCC_ECR_E26_MAX (0x00000001U)
2908 #define CSL_EVETPCC_ECR_E13_MASK (0x00002000U)
2909 #define CSL_EVETPCC_ECR_E13_SHIFT (13U)
2910 #define CSL_EVETPCC_ECR_E13_RESETVAL (0x00000000U)
2911 #define CSL_EVETPCC_ECR_E13_MAX (0x00000001U)
2913 #define CSL_EVETPCC_ECR_E25_MASK (0x02000000U)
2914 #define CSL_EVETPCC_ECR_E25_SHIFT (25U)
2915 #define CSL_EVETPCC_ECR_E25_RESETVAL (0x00000000U)
2916 #define CSL_EVETPCC_ECR_E25_MAX (0x00000001U)
2918 #define CSL_EVETPCC_ECR_E15_MASK (0x00008000U)
2919 #define CSL_EVETPCC_ECR_E15_SHIFT (15U)
2920 #define CSL_EVETPCC_ECR_E15_RESETVAL (0x00000000U)
2921 #define CSL_EVETPCC_ECR_E15_MAX (0x00000001U)
2923 #define CSL_EVETPCC_ECR_E28_MASK (0x10000000U)
2924 #define CSL_EVETPCC_ECR_E28_SHIFT (28U)
2925 #define CSL_EVETPCC_ECR_E28_RESETVAL (0x00000000U)
2926 #define CSL_EVETPCC_ECR_E28_MAX (0x00000001U)
2928 #define CSL_EVETPCC_ECR_E17_MASK (0x00020000U)
2929 #define CSL_EVETPCC_ECR_E17_SHIFT (17U)
2930 #define CSL_EVETPCC_ECR_E17_RESETVAL (0x00000000U)
2931 #define CSL_EVETPCC_ECR_E17_MAX (0x00000001U)
2933 #define CSL_EVETPCC_ECR_E27_MASK (0x08000000U)
2934 #define CSL_EVETPCC_ECR_E27_SHIFT (27U)
2935 #define CSL_EVETPCC_ECR_E27_RESETVAL (0x00000000U)
2936 #define CSL_EVETPCC_ECR_E27_MAX (0x00000001U)
2938 #define CSL_EVETPCC_ECR_E4_MASK (0x00000010U)
2939 #define CSL_EVETPCC_ECR_E4_SHIFT (4U)
2940 #define CSL_EVETPCC_ECR_E4_RESETVAL (0x00000000U)
2941 #define CSL_EVETPCC_ECR_E4_MAX (0x00000001U)
2943 #define CSL_EVETPCC_ECR_E24_MASK (0x01000000U)
2944 #define CSL_EVETPCC_ECR_E24_SHIFT (24U)
2945 #define CSL_EVETPCC_ECR_E24_RESETVAL (0x00000000U)
2946 #define CSL_EVETPCC_ECR_E24_MAX (0x00000001U)
2948 #define CSL_EVETPCC_ECR_E2_MASK (0x00000004U)
2949 #define CSL_EVETPCC_ECR_E2_SHIFT (2U)
2950 #define CSL_EVETPCC_ECR_E2_RESETVAL (0x00000000U)
2951 #define CSL_EVETPCC_ECR_E2_MAX (0x00000001U)
2953 #define CSL_EVETPCC_ECR_E3_MASK (0x00000008U)
2954 #define CSL_EVETPCC_ECR_E3_SHIFT (3U)
2955 #define CSL_EVETPCC_ECR_E3_RESETVAL (0x00000000U)
2956 #define CSL_EVETPCC_ECR_E3_MAX (0x00000001U)
2958 #define CSL_EVETPCC_ECR_E0_MASK (0x00000001U)
2959 #define CSL_EVETPCC_ECR_E0_SHIFT (0U)
2960 #define CSL_EVETPCC_ECR_E0_RESETVAL (0x00000000U)
2961 #define CSL_EVETPCC_ECR_E0_MAX (0x00000001U)
2963 #define CSL_EVETPCC_ECR_E20_MASK (0x00100000U)
2964 #define CSL_EVETPCC_ECR_E20_SHIFT (20U)
2965 #define CSL_EVETPCC_ECR_E20_RESETVAL (0x00000000U)
2966 #define CSL_EVETPCC_ECR_E20_MAX (0x00000001U)
2968 #define CSL_EVETPCC_ECR_E6_MASK (0x00000040U)
2969 #define CSL_EVETPCC_ECR_E6_SHIFT (6U)
2970 #define CSL_EVETPCC_ECR_E6_RESETVAL (0x00000000U)
2971 #define CSL_EVETPCC_ECR_E6_MAX (0x00000001U)
2973 #define CSL_EVETPCC_ECR_E1_MASK (0x00000002U)
2974 #define CSL_EVETPCC_ECR_E1_SHIFT (1U)
2975 #define CSL_EVETPCC_ECR_E1_RESETVAL (0x00000000U)
2976 #define CSL_EVETPCC_ECR_E1_MAX (0x00000001U)
2978 #define CSL_EVETPCC_ECR_E5_MASK (0x00000020U)
2979 #define CSL_EVETPCC_ECR_E5_SHIFT (5U)
2980 #define CSL_EVETPCC_ECR_E5_RESETVAL (0x00000000U)
2981 #define CSL_EVETPCC_ECR_E5_MAX (0x00000001U)
2983 #define CSL_EVETPCC_ECR_E23_MASK (0x00800000U)
2984 #define CSL_EVETPCC_ECR_E23_SHIFT (23U)
2985 #define CSL_EVETPCC_ECR_E23_RESETVAL (0x00000000U)
2986 #define CSL_EVETPCC_ECR_E23_MAX (0x00000001U)
2988 #define CSL_EVETPCC_ECR_E8_MASK (0x00000100U)
2989 #define CSL_EVETPCC_ECR_E8_SHIFT (8U)
2990 #define CSL_EVETPCC_ECR_E8_RESETVAL (0x00000000U)
2991 #define CSL_EVETPCC_ECR_E8_MAX (0x00000001U)
2993 #define CSL_EVETPCC_ECR_E9_MASK (0x00000200U)
2994 #define CSL_EVETPCC_ECR_E9_SHIFT (9U)
2995 #define CSL_EVETPCC_ECR_E9_RESETVAL (0x00000000U)
2996 #define CSL_EVETPCC_ECR_E9_MAX (0x00000001U)
2998 #define CSL_EVETPCC_ECR_E22_MASK (0x00400000U)
2999 #define CSL_EVETPCC_ECR_E22_SHIFT (22U)
3000 #define CSL_EVETPCC_ECR_E22_RESETVAL (0x00000000U)
3001 #define CSL_EVETPCC_ECR_E22_MAX (0x00000001U)
3003 #define CSL_EVETPCC_ECR_E7_MASK (0x00000080U)
3004 #define CSL_EVETPCC_ECR_E7_SHIFT (7U)
3005 #define CSL_EVETPCC_ECR_E7_RESETVAL (0x00000000U)
3006 #define CSL_EVETPCC_ECR_E7_MAX (0x00000001U)
3008 #define CSL_EVETPCC_ECR_RESETVAL (0x00000000U)
3010 /* ECRH */
3012 #define CSL_EVETPCC_ECRH_E50_MASK (0x00040000U)
3013 #define CSL_EVETPCC_ECRH_E50_SHIFT (18U)
3014 #define CSL_EVETPCC_ECRH_E50_RESETVAL (0x00000000U)
3015 #define CSL_EVETPCC_ECRH_E50_MAX (0x00000001U)
3017 #define CSL_EVETPCC_ECRH_E36_MASK (0x00000010U)
3018 #define CSL_EVETPCC_ECRH_E36_SHIFT (4U)
3019 #define CSL_EVETPCC_ECRH_E36_RESETVAL (0x00000000U)
3020 #define CSL_EVETPCC_ECRH_E36_MAX (0x00000001U)
3022 #define CSL_EVETPCC_ECRH_E60_MASK (0x10000000U)
3023 #define CSL_EVETPCC_ECRH_E60_SHIFT (28U)
3024 #define CSL_EVETPCC_ECRH_E60_RESETVAL (0x00000000U)
3025 #define CSL_EVETPCC_ECRH_E60_MAX (0x00000001U)
3027 #define CSL_EVETPCC_ECRH_E49_MASK (0x00020000U)
3028 #define CSL_EVETPCC_ECRH_E49_SHIFT (17U)
3029 #define CSL_EVETPCC_ECRH_E49_RESETVAL (0x00000000U)
3030 #define CSL_EVETPCC_ECRH_E49_MAX (0x00000001U)
3032 #define CSL_EVETPCC_ECRH_E37_MASK (0x00000020U)
3033 #define CSL_EVETPCC_ECRH_E37_SHIFT (5U)
3034 #define CSL_EVETPCC_ECRH_E37_RESETVAL (0x00000000U)
3035 #define CSL_EVETPCC_ECRH_E37_MAX (0x00000001U)
3037 #define CSL_EVETPCC_ECRH_E48_MASK (0x00010000U)
3038 #define CSL_EVETPCC_ECRH_E48_SHIFT (16U)
3039 #define CSL_EVETPCC_ECRH_E48_RESETVAL (0x00000000U)
3040 #define CSL_EVETPCC_ECRH_E48_MAX (0x00000001U)
3042 #define CSL_EVETPCC_ECRH_E58_MASK (0x04000000U)
3043 #define CSL_EVETPCC_ECRH_E58_SHIFT (26U)
3044 #define CSL_EVETPCC_ECRH_E58_RESETVAL (0x00000000U)
3045 #define CSL_EVETPCC_ECRH_E58_MAX (0x00000001U)
3047 #define CSL_EVETPCC_ECRH_E38_MASK (0x00000040U)
3048 #define CSL_EVETPCC_ECRH_E38_SHIFT (6U)
3049 #define CSL_EVETPCC_ECRH_E38_RESETVAL (0x00000000U)
3050 #define CSL_EVETPCC_ECRH_E38_MAX (0x00000001U)
3052 #define CSL_EVETPCC_ECRH_E63_MASK (0x80000000U)
3053 #define CSL_EVETPCC_ECRH_E63_SHIFT (31U)
3054 #define CSL_EVETPCC_ECRH_E63_RESETVAL (0x00000000U)
3055 #define CSL_EVETPCC_ECRH_E63_MAX (0x00000001U)
3057 #define CSL_EVETPCC_ECRH_E47_MASK (0x00008000U)
3058 #define CSL_EVETPCC_ECRH_E47_SHIFT (15U)
3059 #define CSL_EVETPCC_ECRH_E47_RESETVAL (0x00000000U)
3060 #define CSL_EVETPCC_ECRH_E47_MAX (0x00000001U)
3062 #define CSL_EVETPCC_ECRH_E39_MASK (0x00000080U)
3063 #define CSL_EVETPCC_ECRH_E39_SHIFT (7U)
3064 #define CSL_EVETPCC_ECRH_E39_RESETVAL (0x00000000U)
3065 #define CSL_EVETPCC_ECRH_E39_MAX (0x00000001U)
3067 #define CSL_EVETPCC_ECRH_E32_MASK (0x00000001U)
3068 #define CSL_EVETPCC_ECRH_E32_SHIFT (0U)
3069 #define CSL_EVETPCC_ECRH_E32_RESETVAL (0x00000000U)
3070 #define CSL_EVETPCC_ECRH_E32_MAX (0x00000001U)
3072 #define CSL_EVETPCC_ECRH_E51_MASK (0x00080000U)
3073 #define CSL_EVETPCC_ECRH_E51_SHIFT (19U)
3074 #define CSL_EVETPCC_ECRH_E51_RESETVAL (0x00000000U)
3075 #define CSL_EVETPCC_ECRH_E51_MAX (0x00000001U)
3077 #define CSL_EVETPCC_ECRH_E33_MASK (0x00000002U)
3078 #define CSL_EVETPCC_ECRH_E33_SHIFT (1U)
3079 #define CSL_EVETPCC_ECRH_E33_RESETVAL (0x00000000U)
3080 #define CSL_EVETPCC_ECRH_E33_MAX (0x00000001U)
3082 #define CSL_EVETPCC_ECRH_E34_MASK (0x00000004U)
3083 #define CSL_EVETPCC_ECRH_E34_SHIFT (2U)
3084 #define CSL_EVETPCC_ECRH_E34_RESETVAL (0x00000000U)
3085 #define CSL_EVETPCC_ECRH_E34_MAX (0x00000001U)
3087 #define CSL_EVETPCC_ECRH_E35_MASK (0x00000008U)
3088 #define CSL_EVETPCC_ECRH_E35_SHIFT (3U)
3089 #define CSL_EVETPCC_ECRH_E35_RESETVAL (0x00000000U)
3090 #define CSL_EVETPCC_ECRH_E35_MAX (0x00000001U)
3092 #define CSL_EVETPCC_ECRH_E42_MASK (0x00000400U)
3093 #define CSL_EVETPCC_ECRH_E42_SHIFT (10U)
3094 #define CSL_EVETPCC_ECRH_E42_RESETVAL (0x00000000U)
3095 #define CSL_EVETPCC_ECRH_E42_MAX (0x00000001U)
3097 #define CSL_EVETPCC_ECRH_E52_MASK (0x00100000U)
3098 #define CSL_EVETPCC_ECRH_E52_SHIFT (20U)
3099 #define CSL_EVETPCC_ECRH_E52_RESETVAL (0x00000000U)
3100 #define CSL_EVETPCC_ECRH_E52_MAX (0x00000001U)
3102 #define CSL_EVETPCC_ECRH_E41_MASK (0x00000200U)
3103 #define CSL_EVETPCC_ECRH_E41_SHIFT (9U)
3104 #define CSL_EVETPCC_ECRH_E41_RESETVAL (0x00000000U)
3105 #define CSL_EVETPCC_ECRH_E41_MAX (0x00000001U)
3107 #define CSL_EVETPCC_ECRH_E55_MASK (0x00800000U)
3108 #define CSL_EVETPCC_ECRH_E55_SHIFT (23U)
3109 #define CSL_EVETPCC_ECRH_E55_RESETVAL (0x00000000U)
3110 #define CSL_EVETPCC_ECRH_E55_MAX (0x00000001U)
3112 #define CSL_EVETPCC_ECRH_E53_MASK (0x00200000U)
3113 #define CSL_EVETPCC_ECRH_E53_SHIFT (21U)
3114 #define CSL_EVETPCC_ECRH_E53_RESETVAL (0x00000000U)
3115 #define CSL_EVETPCC_ECRH_E53_MAX (0x00000001U)
3117 #define CSL_EVETPCC_ECRH_E46_MASK (0x00004000U)
3118 #define CSL_EVETPCC_ECRH_E46_SHIFT (14U)
3119 #define CSL_EVETPCC_ECRH_E46_RESETVAL (0x00000000U)
3120 #define CSL_EVETPCC_ECRH_E46_MAX (0x00000001U)
3122 #define CSL_EVETPCC_ECRH_E62_MASK (0x40000000U)
3123 #define CSL_EVETPCC_ECRH_E62_SHIFT (30U)
3124 #define CSL_EVETPCC_ECRH_E62_RESETVAL (0x00000000U)
3125 #define CSL_EVETPCC_ECRH_E62_MAX (0x00000001U)
3127 #define CSL_EVETPCC_ECRH_E40_MASK (0x00000100U)
3128 #define CSL_EVETPCC_ECRH_E40_SHIFT (8U)
3129 #define CSL_EVETPCC_ECRH_E40_RESETVAL (0x00000000U)
3130 #define CSL_EVETPCC_ECRH_E40_MAX (0x00000001U)
3132 #define CSL_EVETPCC_ECRH_E56_MASK (0x01000000U)
3133 #define CSL_EVETPCC_ECRH_E56_SHIFT (24U)
3134 #define CSL_EVETPCC_ECRH_E56_RESETVAL (0x00000000U)
3135 #define CSL_EVETPCC_ECRH_E56_MAX (0x00000001U)
3137 #define CSL_EVETPCC_ECRH_E61_MASK (0x20000000U)
3138 #define CSL_EVETPCC_ECRH_E61_SHIFT (29U)
3139 #define CSL_EVETPCC_ECRH_E61_RESETVAL (0x00000000U)
3140 #define CSL_EVETPCC_ECRH_E61_MAX (0x00000001U)
3142 #define CSL_EVETPCC_ECRH_E45_MASK (0x00002000U)
3143 #define CSL_EVETPCC_ECRH_E45_SHIFT (13U)
3144 #define CSL_EVETPCC_ECRH_E45_RESETVAL (0x00000000U)
3145 #define CSL_EVETPCC_ECRH_E45_MAX (0x00000001U)
3147 #define CSL_EVETPCC_ECRH_E59_MASK (0x08000000U)
3148 #define CSL_EVETPCC_ECRH_E59_SHIFT (27U)
3149 #define CSL_EVETPCC_ECRH_E59_RESETVAL (0x00000000U)
3150 #define CSL_EVETPCC_ECRH_E59_MAX (0x00000001U)
3152 #define CSL_EVETPCC_ECRH_E44_MASK (0x00001000U)
3153 #define CSL_EVETPCC_ECRH_E44_SHIFT (12U)
3154 #define CSL_EVETPCC_ECRH_E44_RESETVAL (0x00000000U)
3155 #define CSL_EVETPCC_ECRH_E44_MAX (0x00000001U)
3157 #define CSL_EVETPCC_ECRH_E54_MASK (0x00400000U)
3158 #define CSL_EVETPCC_ECRH_E54_SHIFT (22U)
3159 #define CSL_EVETPCC_ECRH_E54_RESETVAL (0x00000000U)
3160 #define CSL_EVETPCC_ECRH_E54_MAX (0x00000001U)
3162 #define CSL_EVETPCC_ECRH_E43_MASK (0x00000800U)
3163 #define CSL_EVETPCC_ECRH_E43_SHIFT (11U)
3164 #define CSL_EVETPCC_ECRH_E43_RESETVAL (0x00000000U)
3165 #define CSL_EVETPCC_ECRH_E43_MAX (0x00000001U)
3167 #define CSL_EVETPCC_ECRH_E57_MASK (0x02000000U)
3168 #define CSL_EVETPCC_ECRH_E57_SHIFT (25U)
3169 #define CSL_EVETPCC_ECRH_E57_RESETVAL (0x00000000U)
3170 #define CSL_EVETPCC_ECRH_E57_MAX (0x00000001U)
3172 #define CSL_EVETPCC_ECRH_RESETVAL (0x00000000U)
3174 /* ESR */
3176 #define CSL_EVETPCC_ESR_E3_MASK (0x00000008U)
3177 #define CSL_EVETPCC_ESR_E3_SHIFT (3U)
3178 #define CSL_EVETPCC_ESR_E3_RESETVAL (0x00000000U)
3179 #define CSL_EVETPCC_ESR_E3_MAX (0x00000001U)
3181 #define CSL_EVETPCC_ESR_E6_MASK (0x00000040U)
3182 #define CSL_EVETPCC_ESR_E6_SHIFT (6U)
3183 #define CSL_EVETPCC_ESR_E6_RESETVAL (0x00000000U)
3184 #define CSL_EVETPCC_ESR_E6_MAX (0x00000001U)
3186 #define CSL_EVETPCC_ESR_E20_MASK (0x00100000U)
3187 #define CSL_EVETPCC_ESR_E20_SHIFT (20U)
3188 #define CSL_EVETPCC_ESR_E20_RESETVAL (0x00000000U)
3189 #define CSL_EVETPCC_ESR_E20_MAX (0x00000001U)
3191 #define CSL_EVETPCC_ESR_E1_MASK (0x00000002U)
3192 #define CSL_EVETPCC_ESR_E1_SHIFT (1U)
3193 #define CSL_EVETPCC_ESR_E1_RESETVAL (0x00000000U)
3194 #define CSL_EVETPCC_ESR_E1_MAX (0x00000001U)
3196 #define CSL_EVETPCC_ESR_E4_MASK (0x00000010U)
3197 #define CSL_EVETPCC_ESR_E4_SHIFT (4U)
3198 #define CSL_EVETPCC_ESR_E4_RESETVAL (0x00000000U)
3199 #define CSL_EVETPCC_ESR_E4_MAX (0x00000001U)
3201 #define CSL_EVETPCC_ESR_E18_MASK (0x00040000U)
3202 #define CSL_EVETPCC_ESR_E18_SHIFT (18U)
3203 #define CSL_EVETPCC_ESR_E18_RESETVAL (0x00000000U)
3204 #define CSL_EVETPCC_ESR_E18_MAX (0x00000001U)
3206 #define CSL_EVETPCC_ESR_E7_MASK (0x00000080U)
3207 #define CSL_EVETPCC_ESR_E7_SHIFT (7U)
3208 #define CSL_EVETPCC_ESR_E7_RESETVAL (0x00000000U)
3209 #define CSL_EVETPCC_ESR_E7_MAX (0x00000001U)
3211 #define CSL_EVETPCC_ESR_E11_MASK (0x00000800U)
3212 #define CSL_EVETPCC_ESR_E11_SHIFT (11U)
3213 #define CSL_EVETPCC_ESR_E11_RESETVAL (0x00000000U)
3214 #define CSL_EVETPCC_ESR_E11_MAX (0x00000001U)
3216 #define CSL_EVETPCC_ESR_E10_MASK (0x00000400U)
3217 #define CSL_EVETPCC_ESR_E10_SHIFT (10U)
3218 #define CSL_EVETPCC_ESR_E10_RESETVAL (0x00000000U)
3219 #define CSL_EVETPCC_ESR_E10_MAX (0x00000001U)
3221 #define CSL_EVETPCC_ESR_E5_MASK (0x00000020U)
3222 #define CSL_EVETPCC_ESR_E5_SHIFT (5U)
3223 #define CSL_EVETPCC_ESR_E5_RESETVAL (0x00000000U)
3224 #define CSL_EVETPCC_ESR_E5_MAX (0x00000001U)
3226 #define CSL_EVETPCC_ESR_E8_MASK (0x00000100U)
3227 #define CSL_EVETPCC_ESR_E8_SHIFT (8U)
3228 #define CSL_EVETPCC_ESR_E8_RESETVAL (0x00000000U)
3229 #define CSL_EVETPCC_ESR_E8_MAX (0x00000001U)
3231 #define CSL_EVETPCC_ESR_E22_MASK (0x00400000U)
3232 #define CSL_EVETPCC_ESR_E22_SHIFT (22U)
3233 #define CSL_EVETPCC_ESR_E22_RESETVAL (0x00000000U)
3234 #define CSL_EVETPCC_ESR_E22_MAX (0x00000001U)
3236 #define CSL_EVETPCC_ESR_E21_MASK (0x00200000U)
3237 #define CSL_EVETPCC_ESR_E21_SHIFT (21U)
3238 #define CSL_EVETPCC_ESR_E21_RESETVAL (0x00000000U)
3239 #define CSL_EVETPCC_ESR_E21_MAX (0x00000001U)
3241 #define CSL_EVETPCC_ESR_E23_MASK (0x00800000U)
3242 #define CSL_EVETPCC_ESR_E23_SHIFT (23U)
3243 #define CSL_EVETPCC_ESR_E23_RESETVAL (0x00000000U)
3244 #define CSL_EVETPCC_ESR_E23_MAX (0x00000001U)
3246 #define CSL_EVETPCC_ESR_E31_MASK (0x80000000U)
3247 #define CSL_EVETPCC_ESR_E31_SHIFT (31U)
3248 #define CSL_EVETPCC_ESR_E31_RESETVAL (0x00000000U)
3249 #define CSL_EVETPCC_ESR_E31_MAX (0x00000001U)
3251 #define CSL_EVETPCC_ESR_E15_MASK (0x00008000U)
3252 #define CSL_EVETPCC_ESR_E15_SHIFT (15U)
3253 #define CSL_EVETPCC_ESR_E15_RESETVAL (0x00000000U)
3254 #define CSL_EVETPCC_ESR_E15_MAX (0x00000001U)
3256 #define CSL_EVETPCC_ESR_E26_MASK (0x04000000U)
3257 #define CSL_EVETPCC_ESR_E26_SHIFT (26U)
3258 #define CSL_EVETPCC_ESR_E26_RESETVAL (0x00000000U)
3259 #define CSL_EVETPCC_ESR_E26_MAX (0x00000001U)
3261 #define CSL_EVETPCC_ESR_E24_MASK (0x01000000U)
3262 #define CSL_EVETPCC_ESR_E24_SHIFT (24U)
3263 #define CSL_EVETPCC_ESR_E24_RESETVAL (0x00000000U)
3264 #define CSL_EVETPCC_ESR_E24_MAX (0x00000001U)
3266 #define CSL_EVETPCC_ESR_E12_MASK (0x00001000U)
3267 #define CSL_EVETPCC_ESR_E12_SHIFT (12U)
3268 #define CSL_EVETPCC_ESR_E12_RESETVAL (0x00000000U)
3269 #define CSL_EVETPCC_ESR_E12_MAX (0x00000001U)
3271 #define CSL_EVETPCC_ESR_E13_MASK (0x00002000U)
3272 #define CSL_EVETPCC_ESR_E13_SHIFT (13U)
3273 #define CSL_EVETPCC_ESR_E13_RESETVAL (0x00000000U)
3274 #define CSL_EVETPCC_ESR_E13_MAX (0x00000001U)
3276 #define CSL_EVETPCC_ESR_E9_MASK (0x00000200U)
3277 #define CSL_EVETPCC_ESR_E9_SHIFT (9U)
3278 #define CSL_EVETPCC_ESR_E9_RESETVAL (0x00000000U)
3279 #define CSL_EVETPCC_ESR_E9_MAX (0x00000001U)
3281 #define CSL_EVETPCC_ESR_E28_MASK (0x10000000U)
3282 #define CSL_EVETPCC_ESR_E28_SHIFT (28U)
3283 #define CSL_EVETPCC_ESR_E28_RESETVAL (0x00000000U)
3284 #define CSL_EVETPCC_ESR_E28_MAX (0x00000001U)
3286 #define CSL_EVETPCC_ESR_E25_MASK (0x02000000U)
3287 #define CSL_EVETPCC_ESR_E25_SHIFT (25U)
3288 #define CSL_EVETPCC_ESR_E25_RESETVAL (0x00000000U)
3289 #define CSL_EVETPCC_ESR_E25_MAX (0x00000001U)
3291 #define CSL_EVETPCC_ESR_E0_MASK (0x00000001U)
3292 #define CSL_EVETPCC_ESR_E0_SHIFT (0U)
3293 #define CSL_EVETPCC_ESR_E0_RESETVAL (0x00000000U)
3294 #define CSL_EVETPCC_ESR_E0_MAX (0x00000001U)
3296 #define CSL_EVETPCC_ESR_E19_MASK (0x00080000U)
3297 #define CSL_EVETPCC_ESR_E19_SHIFT (19U)
3298 #define CSL_EVETPCC_ESR_E19_RESETVAL (0x00000000U)
3299 #define CSL_EVETPCC_ESR_E19_MAX (0x00000001U)
3301 #define CSL_EVETPCC_ESR_E16_MASK (0x00010000U)
3302 #define CSL_EVETPCC_ESR_E16_SHIFT (16U)
3303 #define CSL_EVETPCC_ESR_E16_RESETVAL (0x00000000U)
3304 #define CSL_EVETPCC_ESR_E16_MAX (0x00000001U)
3306 #define CSL_EVETPCC_ESR_E2_MASK (0x00000004U)
3307 #define CSL_EVETPCC_ESR_E2_SHIFT (2U)
3308 #define CSL_EVETPCC_ESR_E2_RESETVAL (0x00000000U)
3309 #define CSL_EVETPCC_ESR_E2_MAX (0x00000001U)
3311 #define CSL_EVETPCC_ESR_E27_MASK (0x08000000U)
3312 #define CSL_EVETPCC_ESR_E27_SHIFT (27U)
3313 #define CSL_EVETPCC_ESR_E27_RESETVAL (0x00000000U)
3314 #define CSL_EVETPCC_ESR_E27_MAX (0x00000001U)
3316 #define CSL_EVETPCC_ESR_E17_MASK (0x00020000U)
3317 #define CSL_EVETPCC_ESR_E17_SHIFT (17U)
3318 #define CSL_EVETPCC_ESR_E17_RESETVAL (0x00000000U)
3319 #define CSL_EVETPCC_ESR_E17_MAX (0x00000001U)
3321 #define CSL_EVETPCC_ESR_E30_MASK (0x40000000U)
3322 #define CSL_EVETPCC_ESR_E30_SHIFT (30U)
3323 #define CSL_EVETPCC_ESR_E30_RESETVAL (0x00000000U)
3324 #define CSL_EVETPCC_ESR_E30_MAX (0x00000001U)
3326 #define CSL_EVETPCC_ESR_E14_MASK (0x00004000U)
3327 #define CSL_EVETPCC_ESR_E14_SHIFT (14U)
3328 #define CSL_EVETPCC_ESR_E14_RESETVAL (0x00000000U)
3329 #define CSL_EVETPCC_ESR_E14_MAX (0x00000001U)
3331 #define CSL_EVETPCC_ESR_E29_MASK (0x20000000U)
3332 #define CSL_EVETPCC_ESR_E29_SHIFT (29U)
3333 #define CSL_EVETPCC_ESR_E29_RESETVAL (0x00000000U)
3334 #define CSL_EVETPCC_ESR_E29_MAX (0x00000001U)
3336 #define CSL_EVETPCC_ESR_RESETVAL (0x00000000U)
3338 /* ESRH */
3340 #define CSL_EVETPCC_ESRH_E41_MASK (0x00000200U)
3341 #define CSL_EVETPCC_ESRH_E41_SHIFT (9U)
3342 #define CSL_EVETPCC_ESRH_E41_RESETVAL (0x00000000U)
3343 #define CSL_EVETPCC_ESRH_E41_MAX (0x00000001U)
3345 #define CSL_EVETPCC_ESRH_E57_MASK (0x02000000U)
3346 #define CSL_EVETPCC_ESRH_E57_SHIFT (25U)
3347 #define CSL_EVETPCC_ESRH_E57_RESETVAL (0x00000000U)
3348 #define CSL_EVETPCC_ESRH_E57_MAX (0x00000001U)
3350 #define CSL_EVETPCC_ESRH_E46_MASK (0x00004000U)
3351 #define CSL_EVETPCC_ESRH_E46_SHIFT (14U)
3352 #define CSL_EVETPCC_ESRH_E46_RESETVAL (0x00000000U)
3353 #define CSL_EVETPCC_ESRH_E46_MAX (0x00000001U)
3355 #define CSL_EVETPCC_ESRH_E42_MASK (0x00000400U)
3356 #define CSL_EVETPCC_ESRH_E42_SHIFT (10U)
3357 #define CSL_EVETPCC_ESRH_E42_RESETVAL (0x00000000U)
3358 #define CSL_EVETPCC_ESRH_E42_MAX (0x00000001U)
3360 #define CSL_EVETPCC_ESRH_E56_MASK (0x01000000U)
3361 #define CSL_EVETPCC_ESRH_E56_SHIFT (24U)
3362 #define CSL_EVETPCC_ESRH_E56_RESETVAL (0x00000000U)
3363 #define CSL_EVETPCC_ESRH_E56_MAX (0x00000001U)
3365 #define CSL_EVETPCC_ESRH_E33_MASK (0x00000002U)
3366 #define CSL_EVETPCC_ESRH_E33_SHIFT (1U)
3367 #define CSL_EVETPCC_ESRH_E33_RESETVAL (0x00000000U)
3368 #define CSL_EVETPCC_ESRH_E33_MAX (0x00000001U)
3370 #define CSL_EVETPCC_ESRH_E43_MASK (0x00000800U)
3371 #define CSL_EVETPCC_ESRH_E43_SHIFT (11U)
3372 #define CSL_EVETPCC_ESRH_E43_RESETVAL (0x00000000U)
3373 #define CSL_EVETPCC_ESRH_E43_MAX (0x00000001U)
3375 #define CSL_EVETPCC_ESRH_E55_MASK (0x00800000U)
3376 #define CSL_EVETPCC_ESRH_E55_SHIFT (23U)
3377 #define CSL_EVETPCC_ESRH_E55_RESETVAL (0x00000000U)
3378 #define CSL_EVETPCC_ESRH_E55_MAX (0x00000001U)
3380 #define CSL_EVETPCC_ESRH_E32_MASK (0x00000001U)
3381 #define CSL_EVETPCC_ESRH_E32_SHIFT (0U)
3382 #define CSL_EVETPCC_ESRH_E32_RESETVAL (0x00000000U)
3383 #define CSL_EVETPCC_ESRH_E32_MAX (0x00000001U)
3385 #define CSL_EVETPCC_ESRH_E48_MASK (0x00010000U)
3386 #define CSL_EVETPCC_ESRH_E48_SHIFT (16U)
3387 #define CSL_EVETPCC_ESRH_E48_RESETVAL (0x00000000U)
3388 #define CSL_EVETPCC_ESRH_E48_MAX (0x00000001U)
3390 #define CSL_EVETPCC_ESRH_E44_MASK (0x00001000U)
3391 #define CSL_EVETPCC_ESRH_E44_SHIFT (12U)
3392 #define CSL_EVETPCC_ESRH_E44_RESETVAL (0x00000000U)
3393 #define CSL_EVETPCC_ESRH_E44_MAX (0x00000001U)
3395 #define CSL_EVETPCC_ESRH_E45_MASK (0x00002000U)
3396 #define CSL_EVETPCC_ESRH_E45_SHIFT (13U)
3397 #define CSL_EVETPCC_ESRH_E45_RESETVAL (0x00000000U)
3398 #define CSL_EVETPCC_ESRH_E45_MAX (0x00000001U)
3400 #define CSL_EVETPCC_ESRH_E49_MASK (0x00020000U)
3401 #define CSL_EVETPCC_ESRH_E49_SHIFT (17U)
3402 #define CSL_EVETPCC_ESRH_E49_RESETVAL (0x00000000U)
3403 #define CSL_EVETPCC_ESRH_E49_MAX (0x00000001U)
3405 #define CSL_EVETPCC_ESRH_E61_MASK (0x20000000U)
3406 #define CSL_EVETPCC_ESRH_E61_SHIFT (29U)
3407 #define CSL_EVETPCC_ESRH_E61_RESETVAL (0x00000000U)
3408 #define CSL_EVETPCC_ESRH_E61_MAX (0x00000001U)
3410 #define CSL_EVETPCC_ESRH_E52_MASK (0x00100000U)
3411 #define CSL_EVETPCC_ESRH_E52_SHIFT (20U)
3412 #define CSL_EVETPCC_ESRH_E52_RESETVAL (0x00000000U)
3413 #define CSL_EVETPCC_ESRH_E52_MAX (0x00000001U)
3415 #define CSL_EVETPCC_ESRH_E63_MASK (0x80000000U)
3416 #define CSL_EVETPCC_ESRH_E63_SHIFT (31U)
3417 #define CSL_EVETPCC_ESRH_E63_RESETVAL (0x00000000U)
3418 #define CSL_EVETPCC_ESRH_E63_MAX (0x00000001U)
3420 #define CSL_EVETPCC_ESRH_E34_MASK (0x00000004U)
3421 #define CSL_EVETPCC_ESRH_E34_SHIFT (2U)
3422 #define CSL_EVETPCC_ESRH_E34_RESETVAL (0x00000000U)
3423 #define CSL_EVETPCC_ESRH_E34_MAX (0x00000001U)
3425 #define CSL_EVETPCC_ESRH_E47_MASK (0x00008000U)
3426 #define CSL_EVETPCC_ESRH_E47_SHIFT (15U)
3427 #define CSL_EVETPCC_ESRH_E47_RESETVAL (0x00000000U)
3428 #define CSL_EVETPCC_ESRH_E47_MAX (0x00000001U)
3430 #define CSL_EVETPCC_ESRH_E60_MASK (0x10000000U)
3431 #define CSL_EVETPCC_ESRH_E60_SHIFT (28U)
3432 #define CSL_EVETPCC_ESRH_E60_RESETVAL (0x00000000U)
3433 #define CSL_EVETPCC_ESRH_E60_MAX (0x00000001U)
3435 #define CSL_EVETPCC_ESRH_E59_MASK (0x08000000U)
3436 #define CSL_EVETPCC_ESRH_E59_SHIFT (27U)
3437 #define CSL_EVETPCC_ESRH_E59_RESETVAL (0x00000000U)
3438 #define CSL_EVETPCC_ESRH_E59_MAX (0x00000001U)
3440 #define CSL_EVETPCC_ESRH_E50_MASK (0x00040000U)
3441 #define CSL_EVETPCC_ESRH_E50_SHIFT (18U)
3442 #define CSL_EVETPCC_ESRH_E50_RESETVAL (0x00000000U)
3443 #define CSL_EVETPCC_ESRH_E50_MAX (0x00000001U)
3445 #define CSL_EVETPCC_ESRH_E58_MASK (0x04000000U)
3446 #define CSL_EVETPCC_ESRH_E58_SHIFT (26U)
3447 #define CSL_EVETPCC_ESRH_E58_RESETVAL (0x00000000U)
3448 #define CSL_EVETPCC_ESRH_E58_MAX (0x00000001U)
3450 #define CSL_EVETPCC_ESRH_E53_MASK (0x00200000U)
3451 #define CSL_EVETPCC_ESRH_E53_SHIFT (21U)
3452 #define CSL_EVETPCC_ESRH_E53_RESETVAL (0x00000000U)
3453 #define CSL_EVETPCC_ESRH_E53_MAX (0x00000001U)
3455 #define CSL_EVETPCC_ESRH_E35_MASK (0x00000008U)
3456 #define CSL_EVETPCC_ESRH_E35_SHIFT (3U)
3457 #define CSL_EVETPCC_ESRH_E35_RESETVAL (0x00000000U)
3458 #define CSL_EVETPCC_ESRH_E35_MAX (0x00000001U)
3460 #define CSL_EVETPCC_ESRH_E51_MASK (0x00080000U)
3461 #define CSL_EVETPCC_ESRH_E51_SHIFT (19U)
3462 #define CSL_EVETPCC_ESRH_E51_RESETVAL (0x00000000U)
3463 #define CSL_EVETPCC_ESRH_E51_MAX (0x00000001U)
3465 #define CSL_EVETPCC_ESRH_E54_MASK (0x00400000U)
3466 #define CSL_EVETPCC_ESRH_E54_SHIFT (22U)
3467 #define CSL_EVETPCC_ESRH_E54_RESETVAL (0x00000000U)
3468 #define CSL_EVETPCC_ESRH_E54_MAX (0x00000001U)
3470 #define CSL_EVETPCC_ESRH_E36_MASK (0x00000010U)
3471 #define CSL_EVETPCC_ESRH_E36_SHIFT (4U)
3472 #define CSL_EVETPCC_ESRH_E36_RESETVAL (0x00000000U)
3473 #define CSL_EVETPCC_ESRH_E36_MAX (0x00000001U)
3475 #define CSL_EVETPCC_ESRH_E62_MASK (0x40000000U)
3476 #define CSL_EVETPCC_ESRH_E62_SHIFT (30U)
3477 #define CSL_EVETPCC_ESRH_E62_RESETVAL (0x00000000U)
3478 #define CSL_EVETPCC_ESRH_E62_MAX (0x00000001U)
3480 #define CSL_EVETPCC_ESRH_E37_MASK (0x00000020U)
3481 #define CSL_EVETPCC_ESRH_E37_SHIFT (5U)
3482 #define CSL_EVETPCC_ESRH_E37_RESETVAL (0x00000000U)
3483 #define CSL_EVETPCC_ESRH_E37_MAX (0x00000001U)
3485 #define CSL_EVETPCC_ESRH_E38_MASK (0x00000040U)
3486 #define CSL_EVETPCC_ESRH_E38_SHIFT (6U)
3487 #define CSL_EVETPCC_ESRH_E38_RESETVAL (0x00000000U)
3488 #define CSL_EVETPCC_ESRH_E38_MAX (0x00000001U)
3490 #define CSL_EVETPCC_ESRH_E39_MASK (0x00000080U)
3491 #define CSL_EVETPCC_ESRH_E39_SHIFT (7U)
3492 #define CSL_EVETPCC_ESRH_E39_RESETVAL (0x00000000U)
3493 #define CSL_EVETPCC_ESRH_E39_MAX (0x00000001U)
3495 #define CSL_EVETPCC_ESRH_E40_MASK (0x00000100U)
3496 #define CSL_EVETPCC_ESRH_E40_SHIFT (8U)
3497 #define CSL_EVETPCC_ESRH_E40_RESETVAL (0x00000000U)
3498 #define CSL_EVETPCC_ESRH_E40_MAX (0x00000001U)
3500 #define CSL_EVETPCC_ESRH_RESETVAL (0x00000000U)
3502 /* CER */
3504 #define CSL_EVETPCC_CER_E6_MASK (0x00000040U)
3505 #define CSL_EVETPCC_CER_E6_SHIFT (6U)
3506 #define CSL_EVETPCC_CER_E6_RESETVAL (0x00000000U)
3507 #define CSL_EVETPCC_CER_E6_MAX (0x00000001U)
3509 #define CSL_EVETPCC_CER_E25_MASK (0x02000000U)
3510 #define CSL_EVETPCC_CER_E25_SHIFT (25U)
3511 #define CSL_EVETPCC_CER_E25_RESETVAL (0x00000000U)
3512 #define CSL_EVETPCC_CER_E25_MAX (0x00000001U)
3514 #define CSL_EVETPCC_CER_E18_MASK (0x00040000U)
3515 #define CSL_EVETPCC_CER_E18_SHIFT (18U)
3516 #define CSL_EVETPCC_CER_E18_RESETVAL (0x00000000U)
3517 #define CSL_EVETPCC_CER_E18_MAX (0x00000001U)
3519 #define CSL_EVETPCC_CER_E7_MASK (0x00000080U)
3520 #define CSL_EVETPCC_CER_E7_SHIFT (7U)
3521 #define CSL_EVETPCC_CER_E7_RESETVAL (0x00000000U)
3522 #define CSL_EVETPCC_CER_E7_MAX (0x00000001U)
3524 #define CSL_EVETPCC_CER_E24_MASK (0x01000000U)
3525 #define CSL_EVETPCC_CER_E24_SHIFT (24U)
3526 #define CSL_EVETPCC_CER_E24_RESETVAL (0x00000000U)
3527 #define CSL_EVETPCC_CER_E24_MAX (0x00000001U)
3529 #define CSL_EVETPCC_CER_E31_MASK (0x80000000U)
3530 #define CSL_EVETPCC_CER_E31_SHIFT (31U)
3531 #define CSL_EVETPCC_CER_E31_RESETVAL (0x00000000U)
3532 #define CSL_EVETPCC_CER_E31_MAX (0x00000001U)
3534 #define CSL_EVETPCC_CER_E8_MASK (0x00000100U)
3535 #define CSL_EVETPCC_CER_E8_SHIFT (8U)
3536 #define CSL_EVETPCC_CER_E8_RESETVAL (0x00000000U)
3537 #define CSL_EVETPCC_CER_E8_MAX (0x00000001U)
3539 #define CSL_EVETPCC_CER_E26_MASK (0x04000000U)
3540 #define CSL_EVETPCC_CER_E26_SHIFT (26U)
3541 #define CSL_EVETPCC_CER_E26_RESETVAL (0x00000000U)
3542 #define CSL_EVETPCC_CER_E26_MAX (0x00000001U)
3544 #define CSL_EVETPCC_CER_E29_MASK (0x20000000U)
3545 #define CSL_EVETPCC_CER_E29_SHIFT (29U)
3546 #define CSL_EVETPCC_CER_E29_RESETVAL (0x00000000U)
3547 #define CSL_EVETPCC_CER_E29_MAX (0x00000001U)
3549 #define CSL_EVETPCC_CER_E9_MASK (0x00000200U)
3550 #define CSL_EVETPCC_CER_E9_SHIFT (9U)
3551 #define CSL_EVETPCC_CER_E9_RESETVAL (0x00000000U)
3552 #define CSL_EVETPCC_CER_E9_MAX (0x00000001U)
3554 #define CSL_EVETPCC_CER_E30_MASK (0x40000000U)
3555 #define CSL_EVETPCC_CER_E30_SHIFT (30U)
3556 #define CSL_EVETPCC_CER_E30_RESETVAL (0x00000000U)
3557 #define CSL_EVETPCC_CER_E30_MAX (0x00000001U)
3559 #define CSL_EVETPCC_CER_E10_MASK (0x00000400U)
3560 #define CSL_EVETPCC_CER_E10_SHIFT (10U)
3561 #define CSL_EVETPCC_CER_E10_RESETVAL (0x00000000U)
3562 #define CSL_EVETPCC_CER_E10_MAX (0x00000001U)
3564 #define CSL_EVETPCC_CER_E28_MASK (0x10000000U)
3565 #define CSL_EVETPCC_CER_E28_SHIFT (28U)
3566 #define CSL_EVETPCC_CER_E28_RESETVAL (0x00000000U)
3567 #define CSL_EVETPCC_CER_E28_MAX (0x00000001U)
3569 #define CSL_EVETPCC_CER_E11_MASK (0x00000800U)
3570 #define CSL_EVETPCC_CER_E11_SHIFT (11U)
3571 #define CSL_EVETPCC_CER_E11_RESETVAL (0x00000000U)
3572 #define CSL_EVETPCC_CER_E11_MAX (0x00000001U)
3574 #define CSL_EVETPCC_CER_E27_MASK (0x08000000U)
3575 #define CSL_EVETPCC_CER_E27_SHIFT (27U)
3576 #define CSL_EVETPCC_CER_E27_RESETVAL (0x00000000U)
3577 #define CSL_EVETPCC_CER_E27_MAX (0x00000001U)
3579 #define CSL_EVETPCC_CER_E0_MASK (0x00000001U)
3580 #define CSL_EVETPCC_CER_E0_SHIFT (0U)
3581 #define CSL_EVETPCC_CER_E0_RESETVAL (0x00000000U)
3582 #define CSL_EVETPCC_CER_E0_MAX (0x00000001U)
3584 #define CSL_EVETPCC_CER_E12_MASK (0x00001000U)
3585 #define CSL_EVETPCC_CER_E12_SHIFT (12U)
3586 #define CSL_EVETPCC_CER_E12_RESETVAL (0x00000000U)
3587 #define CSL_EVETPCC_CER_E12_MAX (0x00000001U)
3589 #define CSL_EVETPCC_CER_E1_MASK (0x00000002U)
3590 #define CSL_EVETPCC_CER_E1_SHIFT (1U)
3591 #define CSL_EVETPCC_CER_E1_RESETVAL (0x00000000U)
3592 #define CSL_EVETPCC_CER_E1_MAX (0x00000001U)
3594 #define CSL_EVETPCC_CER_E13_MASK (0x00002000U)
3595 #define CSL_EVETPCC_CER_E13_SHIFT (13U)
3596 #define CSL_EVETPCC_CER_E13_RESETVAL (0x00000000U)
3597 #define CSL_EVETPCC_CER_E13_MAX (0x00000001U)
3599 #define CSL_EVETPCC_CER_E19_MASK (0x00080000U)
3600 #define CSL_EVETPCC_CER_E19_SHIFT (19U)
3601 #define CSL_EVETPCC_CER_E19_RESETVAL (0x00000000U)
3602 #define CSL_EVETPCC_CER_E19_MAX (0x00000001U)
3604 #define CSL_EVETPCC_CER_E2_MASK (0x00000004U)
3605 #define CSL_EVETPCC_CER_E2_SHIFT (2U)
3606 #define CSL_EVETPCC_CER_E2_RESETVAL (0x00000000U)
3607 #define CSL_EVETPCC_CER_E2_MAX (0x00000001U)
3609 #define CSL_EVETPCC_CER_E14_MASK (0x00004000U)
3610 #define CSL_EVETPCC_CER_E14_SHIFT (14U)
3611 #define CSL_EVETPCC_CER_E14_RESETVAL (0x00000000U)
3612 #define CSL_EVETPCC_CER_E14_MAX (0x00000001U)
3614 #define CSL_EVETPCC_CER_E3_MASK (0x00000008U)
3615 #define CSL_EVETPCC_CER_E3_SHIFT (3U)
3616 #define CSL_EVETPCC_CER_E3_RESETVAL (0x00000000U)
3617 #define CSL_EVETPCC_CER_E3_MAX (0x00000001U)
3619 #define CSL_EVETPCC_CER_E15_MASK (0x00008000U)
3620 #define CSL_EVETPCC_CER_E15_SHIFT (15U)
3621 #define CSL_EVETPCC_CER_E15_RESETVAL (0x00000000U)
3622 #define CSL_EVETPCC_CER_E15_MAX (0x00000001U)
3624 #define CSL_EVETPCC_CER_E21_MASK (0x00200000U)
3625 #define CSL_EVETPCC_CER_E21_SHIFT (21U)
3626 #define CSL_EVETPCC_CER_E21_RESETVAL (0x00000000U)
3627 #define CSL_EVETPCC_CER_E21_MAX (0x00000001U)
3629 #define CSL_EVETPCC_CER_E20_MASK (0x00100000U)
3630 #define CSL_EVETPCC_CER_E20_SHIFT (20U)
3631 #define CSL_EVETPCC_CER_E20_RESETVAL (0x00000000U)
3632 #define CSL_EVETPCC_CER_E20_MAX (0x00000001U)
3634 #define CSL_EVETPCC_CER_E4_MASK (0x00000010U)
3635 #define CSL_EVETPCC_CER_E4_SHIFT (4U)
3636 #define CSL_EVETPCC_CER_E4_RESETVAL (0x00000000U)
3637 #define CSL_EVETPCC_CER_E4_MAX (0x00000001U)
3639 #define CSL_EVETPCC_CER_E23_MASK (0x00800000U)
3640 #define CSL_EVETPCC_CER_E23_SHIFT (23U)
3641 #define CSL_EVETPCC_CER_E23_RESETVAL (0x00000000U)
3642 #define CSL_EVETPCC_CER_E23_MAX (0x00000001U)
3644 #define CSL_EVETPCC_CER_E16_MASK (0x00010000U)
3645 #define CSL_EVETPCC_CER_E16_SHIFT (16U)
3646 #define CSL_EVETPCC_CER_E16_RESETVAL (0x00000000U)
3647 #define CSL_EVETPCC_CER_E16_MAX (0x00000001U)
3649 #define CSL_EVETPCC_CER_E5_MASK (0x00000020U)
3650 #define CSL_EVETPCC_CER_E5_SHIFT (5U)
3651 #define CSL_EVETPCC_CER_E5_RESETVAL (0x00000000U)
3652 #define CSL_EVETPCC_CER_E5_MAX (0x00000001U)
3654 #define CSL_EVETPCC_CER_E22_MASK (0x00400000U)
3655 #define CSL_EVETPCC_CER_E22_SHIFT (22U)
3656 #define CSL_EVETPCC_CER_E22_RESETVAL (0x00000000U)
3657 #define CSL_EVETPCC_CER_E22_MAX (0x00000001U)
3659 #define CSL_EVETPCC_CER_E17_MASK (0x00020000U)
3660 #define CSL_EVETPCC_CER_E17_SHIFT (17U)
3661 #define CSL_EVETPCC_CER_E17_RESETVAL (0x00000000U)
3662 #define CSL_EVETPCC_CER_E17_MAX (0x00000001U)
3664 #define CSL_EVETPCC_CER_RESETVAL (0x00000000U)
3666 /* CERH */
3668 #define CSL_EVETPCC_CERH_E49_MASK (0x00020000U)
3669 #define CSL_EVETPCC_CERH_E49_SHIFT (17U)
3670 #define CSL_EVETPCC_CERH_E49_RESETVAL (0x00000000U)
3671 #define CSL_EVETPCC_CERH_E49_MAX (0x00000001U)
3673 #define CSL_EVETPCC_CERH_E38_MASK (0x00000040U)
3674 #define CSL_EVETPCC_CERH_E38_SHIFT (6U)
3675 #define CSL_EVETPCC_CERH_E38_RESETVAL (0x00000000U)
3676 #define CSL_EVETPCC_CERH_E38_MAX (0x00000001U)
3678 #define CSL_EVETPCC_CERH_E39_MASK (0x00000080U)
3679 #define CSL_EVETPCC_CERH_E39_SHIFT (7U)
3680 #define CSL_EVETPCC_CERH_E39_RESETVAL (0x00000000U)
3681 #define CSL_EVETPCC_CERH_E39_MAX (0x00000001U)
3683 #define CSL_EVETPCC_CERH_E40_MASK (0x00000100U)
3684 #define CSL_EVETPCC_CERH_E40_SHIFT (8U)
3685 #define CSL_EVETPCC_CERH_E40_RESETVAL (0x00000000U)
3686 #define CSL_EVETPCC_CERH_E40_MAX (0x00000001U)
3688 #define CSL_EVETPCC_CERH_E63_MASK (0x80000000U)
3689 #define CSL_EVETPCC_CERH_E63_SHIFT (31U)
3690 #define CSL_EVETPCC_CERH_E63_RESETVAL (0x00000000U)
3691 #define CSL_EVETPCC_CERH_E63_MAX (0x00000001U)
3693 #define CSL_EVETPCC_CERH_E41_MASK (0x00000200U)
3694 #define CSL_EVETPCC_CERH_E41_SHIFT (9U)
3695 #define CSL_EVETPCC_CERH_E41_RESETVAL (0x00000000U)
3696 #define CSL_EVETPCC_CERH_E41_MAX (0x00000001U)
3698 #define CSL_EVETPCC_CERH_E62_MASK (0x40000000U)
3699 #define CSL_EVETPCC_CERH_E62_SHIFT (30U)
3700 #define CSL_EVETPCC_CERH_E62_RESETVAL (0x00000000U)
3701 #define CSL_EVETPCC_CERH_E62_MAX (0x00000001U)
3703 #define CSL_EVETPCC_CERH_E61_MASK (0x20000000U)
3704 #define CSL_EVETPCC_CERH_E61_SHIFT (29U)
3705 #define CSL_EVETPCC_CERH_E61_RESETVAL (0x00000000U)
3706 #define CSL_EVETPCC_CERH_E61_MAX (0x00000001U)
3708 #define CSL_EVETPCC_CERH_E42_MASK (0x00000400U)
3709 #define CSL_EVETPCC_CERH_E42_SHIFT (10U)
3710 #define CSL_EVETPCC_CERH_E42_RESETVAL (0x00000000U)
3711 #define CSL_EVETPCC_CERH_E42_MAX (0x00000001U)
3713 #define CSL_EVETPCC_CERH_E32_MASK (0x00000001U)
3714 #define CSL_EVETPCC_CERH_E32_SHIFT (0U)
3715 #define CSL_EVETPCC_CERH_E32_RESETVAL (0x00000000U)
3716 #define CSL_EVETPCC_CERH_E32_MAX (0x00000001U)
3718 #define CSL_EVETPCC_CERH_E57_MASK (0x02000000U)
3719 #define CSL_EVETPCC_CERH_E57_SHIFT (25U)
3720 #define CSL_EVETPCC_CERH_E57_RESETVAL (0x00000000U)
3721 #define CSL_EVETPCC_CERH_E57_MAX (0x00000001U)
3723 #define CSL_EVETPCC_CERH_E43_MASK (0x00000800U)
3724 #define CSL_EVETPCC_CERH_E43_SHIFT (11U)
3725 #define CSL_EVETPCC_CERH_E43_RESETVAL (0x00000000U)
3726 #define CSL_EVETPCC_CERH_E43_MAX (0x00000001U)
3728 #define CSL_EVETPCC_CERH_E58_MASK (0x04000000U)
3729 #define CSL_EVETPCC_CERH_E58_SHIFT (26U)
3730 #define CSL_EVETPCC_CERH_E58_RESETVAL (0x00000000U)
3731 #define CSL_EVETPCC_CERH_E58_MAX (0x00000001U)
3733 #define CSL_EVETPCC_CERH_E44_MASK (0x00001000U)
3734 #define CSL_EVETPCC_CERH_E44_SHIFT (12U)
3735 #define CSL_EVETPCC_CERH_E44_RESETVAL (0x00000000U)
3736 #define CSL_EVETPCC_CERH_E44_MAX (0x00000001U)
3738 #define CSL_EVETPCC_CERH_E59_MASK (0x08000000U)
3739 #define CSL_EVETPCC_CERH_E59_SHIFT (27U)
3740 #define CSL_EVETPCC_CERH_E59_RESETVAL (0x00000000U)
3741 #define CSL_EVETPCC_CERH_E59_MAX (0x00000001U)
3743 #define CSL_EVETPCC_CERH_E60_MASK (0x10000000U)
3744 #define CSL_EVETPCC_CERH_E60_SHIFT (28U)
3745 #define CSL_EVETPCC_CERH_E60_RESETVAL (0x00000000U)
3746 #define CSL_EVETPCC_CERH_E60_MAX (0x00000001U)
3748 #define CSL_EVETPCC_CERH_E45_MASK (0x00002000U)
3749 #define CSL_EVETPCC_CERH_E45_SHIFT (13U)
3750 #define CSL_EVETPCC_CERH_E45_RESETVAL (0x00000000U)
3751 #define CSL_EVETPCC_CERH_E45_MAX (0x00000001U)
3753 #define CSL_EVETPCC_CERH_E33_MASK (0x00000002U)
3754 #define CSL_EVETPCC_CERH_E33_SHIFT (1U)
3755 #define CSL_EVETPCC_CERH_E33_RESETVAL (0x00000000U)
3756 #define CSL_EVETPCC_CERH_E33_MAX (0x00000001U)
3758 #define CSL_EVETPCC_CERH_E46_MASK (0x00004000U)
3759 #define CSL_EVETPCC_CERH_E46_SHIFT (14U)
3760 #define CSL_EVETPCC_CERH_E46_RESETVAL (0x00000000U)
3761 #define CSL_EVETPCC_CERH_E46_MAX (0x00000001U)
3763 #define CSL_EVETPCC_CERH_E34_MASK (0x00000004U)
3764 #define CSL_EVETPCC_CERH_E34_SHIFT (2U)
3765 #define CSL_EVETPCC_CERH_E34_RESETVAL (0x00000000U)
3766 #define CSL_EVETPCC_CERH_E34_MAX (0x00000001U)
3768 #define CSL_EVETPCC_CERH_E47_MASK (0x00008000U)
3769 #define CSL_EVETPCC_CERH_E47_SHIFT (15U)
3770 #define CSL_EVETPCC_CERH_E47_RESETVAL (0x00000000U)
3771 #define CSL_EVETPCC_CERH_E47_MAX (0x00000001U)
3773 #define CSL_EVETPCC_CERH_E53_MASK (0x00200000U)
3774 #define CSL_EVETPCC_CERH_E53_SHIFT (21U)
3775 #define CSL_EVETPCC_CERH_E53_RESETVAL (0x00000000U)
3776 #define CSL_EVETPCC_CERH_E53_MAX (0x00000001U)
3778 #define CSL_EVETPCC_CERH_E54_MASK (0x00400000U)
3779 #define CSL_EVETPCC_CERH_E54_SHIFT (22U)
3780 #define CSL_EVETPCC_CERH_E54_RESETVAL (0x00000000U)
3781 #define CSL_EVETPCC_CERH_E54_MAX (0x00000001U)
3783 #define CSL_EVETPCC_CERH_E50_MASK (0x00040000U)
3784 #define CSL_EVETPCC_CERH_E50_SHIFT (18U)
3785 #define CSL_EVETPCC_CERH_E50_RESETVAL (0x00000000U)
3786 #define CSL_EVETPCC_CERH_E50_MAX (0x00000001U)
3788 #define CSL_EVETPCC_CERH_E35_MASK (0x00000008U)
3789 #define CSL_EVETPCC_CERH_E35_SHIFT (3U)
3790 #define CSL_EVETPCC_CERH_E35_RESETVAL (0x00000000U)
3791 #define CSL_EVETPCC_CERH_E35_MAX (0x00000001U)
3793 #define CSL_EVETPCC_CERH_E48_MASK (0x00010000U)
3794 #define CSL_EVETPCC_CERH_E48_SHIFT (16U)
3795 #define CSL_EVETPCC_CERH_E48_RESETVAL (0x00000000U)
3796 #define CSL_EVETPCC_CERH_E48_MAX (0x00000001U)
3798 #define CSL_EVETPCC_CERH_E56_MASK (0x01000000U)
3799 #define CSL_EVETPCC_CERH_E56_SHIFT (24U)
3800 #define CSL_EVETPCC_CERH_E56_RESETVAL (0x00000000U)
3801 #define CSL_EVETPCC_CERH_E56_MAX (0x00000001U)
3803 #define CSL_EVETPCC_CERH_E51_MASK (0x00080000U)
3804 #define CSL_EVETPCC_CERH_E51_SHIFT (19U)
3805 #define CSL_EVETPCC_CERH_E51_RESETVAL (0x00000000U)
3806 #define CSL_EVETPCC_CERH_E51_MAX (0x00000001U)
3808 #define CSL_EVETPCC_CERH_E36_MASK (0x00000010U)
3809 #define CSL_EVETPCC_CERH_E36_SHIFT (4U)
3810 #define CSL_EVETPCC_CERH_E36_RESETVAL (0x00000000U)
3811 #define CSL_EVETPCC_CERH_E36_MAX (0x00000001U)
3813 #define CSL_EVETPCC_CERH_E55_MASK (0x00800000U)
3814 #define CSL_EVETPCC_CERH_E55_SHIFT (23U)
3815 #define CSL_EVETPCC_CERH_E55_RESETVAL (0x00000000U)
3816 #define CSL_EVETPCC_CERH_E55_MAX (0x00000001U)
3818 #define CSL_EVETPCC_CERH_E52_MASK (0x00100000U)
3819 #define CSL_EVETPCC_CERH_E52_SHIFT (20U)
3820 #define CSL_EVETPCC_CERH_E52_RESETVAL (0x00000000U)
3821 #define CSL_EVETPCC_CERH_E52_MAX (0x00000001U)
3823 #define CSL_EVETPCC_CERH_E37_MASK (0x00000020U)
3824 #define CSL_EVETPCC_CERH_E37_SHIFT (5U)
3825 #define CSL_EVETPCC_CERH_E37_RESETVAL (0x00000000U)
3826 #define CSL_EVETPCC_CERH_E37_MAX (0x00000001U)
3828 #define CSL_EVETPCC_CERH_RESETVAL (0x00000000U)
3830 /* EER */
3832 #define CSL_EVETPCC_EER_E11_MASK (0x00000800U)
3833 #define CSL_EVETPCC_EER_E11_SHIFT (11U)
3834 #define CSL_EVETPCC_EER_E11_RESETVAL (0x00000000U)
3835 #define CSL_EVETPCC_EER_E11_MAX (0x00000001U)
3837 #define CSL_EVETPCC_EER_E24_MASK (0x01000000U)
3838 #define CSL_EVETPCC_EER_E24_SHIFT (24U)
3839 #define CSL_EVETPCC_EER_E24_RESETVAL (0x00000000U)
3840 #define CSL_EVETPCC_EER_E24_MAX (0x00000001U)
3842 #define CSL_EVETPCC_EER_E10_MASK (0x00000400U)
3843 #define CSL_EVETPCC_EER_E10_SHIFT (10U)
3844 #define CSL_EVETPCC_EER_E10_RESETVAL (0x00000000U)
3845 #define CSL_EVETPCC_EER_E10_MAX (0x00000001U)
3847 #define CSL_EVETPCC_EER_E12_MASK (0x00001000U)
3848 #define CSL_EVETPCC_EER_E12_SHIFT (12U)
3849 #define CSL_EVETPCC_EER_E12_RESETVAL (0x00000000U)
3850 #define CSL_EVETPCC_EER_E12_MAX (0x00000001U)
3852 #define CSL_EVETPCC_EER_E25_MASK (0x02000000U)
3853 #define CSL_EVETPCC_EER_E25_SHIFT (25U)
3854 #define CSL_EVETPCC_EER_E25_RESETVAL (0x00000000U)
3855 #define CSL_EVETPCC_EER_E25_MAX (0x00000001U)
3857 #define CSL_EVETPCC_EER_E9_MASK (0x00000200U)
3858 #define CSL_EVETPCC_EER_E9_SHIFT (9U)
3859 #define CSL_EVETPCC_EER_E9_RESETVAL (0x00000000U)
3860 #define CSL_EVETPCC_EER_E9_MAX (0x00000001U)
3862 #define CSL_EVETPCC_EER_E21_MASK (0x00200000U)
3863 #define CSL_EVETPCC_EER_E21_SHIFT (21U)
3864 #define CSL_EVETPCC_EER_E21_RESETVAL (0x00000000U)
3865 #define CSL_EVETPCC_EER_E21_MAX (0x00000001U)
3867 #define CSL_EVETPCC_EER_E22_MASK (0x00400000U)
3868 #define CSL_EVETPCC_EER_E22_SHIFT (22U)
3869 #define CSL_EVETPCC_EER_E22_RESETVAL (0x00000000U)
3870 #define CSL_EVETPCC_EER_E22_MAX (0x00000001U)
3872 #define CSL_EVETPCC_EER_E0_MASK (0x00000001U)
3873 #define CSL_EVETPCC_EER_E0_SHIFT (0U)
3874 #define CSL_EVETPCC_EER_E0_RESETVAL (0x00000000U)
3875 #define CSL_EVETPCC_EER_E0_MAX (0x00000001U)
3877 #define CSL_EVETPCC_EER_E23_MASK (0x00800000U)
3878 #define CSL_EVETPCC_EER_E23_SHIFT (23U)
3879 #define CSL_EVETPCC_EER_E23_RESETVAL (0x00000000U)
3880 #define CSL_EVETPCC_EER_E23_MAX (0x00000001U)
3882 #define CSL_EVETPCC_EER_E19_MASK (0x00080000U)
3883 #define CSL_EVETPCC_EER_E19_SHIFT (19U)
3884 #define CSL_EVETPCC_EER_E19_RESETVAL (0x00000000U)
3885 #define CSL_EVETPCC_EER_E19_MAX (0x00000001U)
3887 #define CSL_EVETPCC_EER_E20_MASK (0x00100000U)
3888 #define CSL_EVETPCC_EER_E20_SHIFT (20U)
3889 #define CSL_EVETPCC_EER_E20_RESETVAL (0x00000000U)
3890 #define CSL_EVETPCC_EER_E20_MAX (0x00000001U)
3892 #define CSL_EVETPCC_EER_E29_MASK (0x20000000U)
3893 #define CSL_EVETPCC_EER_E29_SHIFT (29U)
3894 #define CSL_EVETPCC_EER_E29_RESETVAL (0x00000000U)
3895 #define CSL_EVETPCC_EER_E29_MAX (0x00000001U)
3897 #define CSL_EVETPCC_EER_E30_MASK (0x40000000U)
3898 #define CSL_EVETPCC_EER_E30_SHIFT (30U)
3899 #define CSL_EVETPCC_EER_E30_RESETVAL (0x00000000U)
3900 #define CSL_EVETPCC_EER_E30_MAX (0x00000001U)
3902 #define CSL_EVETPCC_EER_E18_MASK (0x00040000U)
3903 #define CSL_EVETPCC_EER_E18_SHIFT (18U)
3904 #define CSL_EVETPCC_EER_E18_RESETVAL (0x00000000U)
3905 #define CSL_EVETPCC_EER_E18_MAX (0x00000001U)
3907 #define CSL_EVETPCC_EER_E31_MASK (0x80000000U)
3908 #define CSL_EVETPCC_EER_E31_SHIFT (31U)
3909 #define CSL_EVETPCC_EER_E31_RESETVAL (0x00000000U)
3910 #define CSL_EVETPCC_EER_E31_MAX (0x00000001U)
3912 #define CSL_EVETPCC_EER_E5_MASK (0x00000020U)
3913 #define CSL_EVETPCC_EER_E5_SHIFT (5U)
3914 #define CSL_EVETPCC_EER_E5_RESETVAL (0x00000000U)
3915 #define CSL_EVETPCC_EER_E5_MAX (0x00000001U)
3917 #define CSL_EVETPCC_EER_E6_MASK (0x00000040U)
3918 #define CSL_EVETPCC_EER_E6_SHIFT (6U)
3919 #define CSL_EVETPCC_EER_E6_RESETVAL (0x00000000U)
3920 #define CSL_EVETPCC_EER_E6_MAX (0x00000001U)
3922 #define CSL_EVETPCC_EER_E8_MASK (0x00000100U)
3923 #define CSL_EVETPCC_EER_E8_SHIFT (8U)
3924 #define CSL_EVETPCC_EER_E8_RESETVAL (0x00000000U)
3925 #define CSL_EVETPCC_EER_E8_MAX (0x00000001U)
3927 #define CSL_EVETPCC_EER_E7_MASK (0x00000080U)
3928 #define CSL_EVETPCC_EER_E7_SHIFT (7U)
3929 #define CSL_EVETPCC_EER_E7_RESETVAL (0x00000000U)
3930 #define CSL_EVETPCC_EER_E7_MAX (0x00000001U)
3932 #define CSL_EVETPCC_EER_E28_MASK (0x10000000U)
3933 #define CSL_EVETPCC_EER_E28_SHIFT (28U)
3934 #define CSL_EVETPCC_EER_E28_RESETVAL (0x00000000U)
3935 #define CSL_EVETPCC_EER_E28_MAX (0x00000001U)
3937 #define CSL_EVETPCC_EER_E3_MASK (0x00000008U)
3938 #define CSL_EVETPCC_EER_E3_SHIFT (3U)
3939 #define CSL_EVETPCC_EER_E3_RESETVAL (0x00000000U)
3940 #define CSL_EVETPCC_EER_E3_MAX (0x00000001U)
3942 #define CSL_EVETPCC_EER_E2_MASK (0x00000004U)
3943 #define CSL_EVETPCC_EER_E2_SHIFT (2U)
3944 #define CSL_EVETPCC_EER_E2_RESETVAL (0x00000000U)
3945 #define CSL_EVETPCC_EER_E2_MAX (0x00000001U)
3947 #define CSL_EVETPCC_EER_E1_MASK (0x00000002U)
3948 #define CSL_EVETPCC_EER_E1_SHIFT (1U)
3949 #define CSL_EVETPCC_EER_E1_RESETVAL (0x00000000U)
3950 #define CSL_EVETPCC_EER_E1_MAX (0x00000001U)
3952 #define CSL_EVETPCC_EER_E13_MASK (0x00002000U)
3953 #define CSL_EVETPCC_EER_E13_SHIFT (13U)
3954 #define CSL_EVETPCC_EER_E13_RESETVAL (0x00000000U)
3955 #define CSL_EVETPCC_EER_E13_MAX (0x00000001U)
3957 #define CSL_EVETPCC_EER_E17_MASK (0x00020000U)
3958 #define CSL_EVETPCC_EER_E17_SHIFT (17U)
3959 #define CSL_EVETPCC_EER_E17_RESETVAL (0x00000000U)
3960 #define CSL_EVETPCC_EER_E17_MAX (0x00000001U)
3962 #define CSL_EVETPCC_EER_E26_MASK (0x04000000U)
3963 #define CSL_EVETPCC_EER_E26_SHIFT (26U)
3964 #define CSL_EVETPCC_EER_E26_RESETVAL (0x00000000U)
3965 #define CSL_EVETPCC_EER_E26_MAX (0x00000001U)
3967 #define CSL_EVETPCC_EER_E14_MASK (0x00004000U)
3968 #define CSL_EVETPCC_EER_E14_SHIFT (14U)
3969 #define CSL_EVETPCC_EER_E14_RESETVAL (0x00000000U)
3970 #define CSL_EVETPCC_EER_E14_MAX (0x00000001U)
3972 #define CSL_EVETPCC_EER_E16_MASK (0x00010000U)
3973 #define CSL_EVETPCC_EER_E16_SHIFT (16U)
3974 #define CSL_EVETPCC_EER_E16_RESETVAL (0x00000000U)
3975 #define CSL_EVETPCC_EER_E16_MAX (0x00000001U)
3977 #define CSL_EVETPCC_EER_E27_MASK (0x08000000U)
3978 #define CSL_EVETPCC_EER_E27_SHIFT (27U)
3979 #define CSL_EVETPCC_EER_E27_RESETVAL (0x00000000U)
3980 #define CSL_EVETPCC_EER_E27_MAX (0x00000001U)
3982 #define CSL_EVETPCC_EER_E4_MASK (0x00000010U)
3983 #define CSL_EVETPCC_EER_E4_SHIFT (4U)
3984 #define CSL_EVETPCC_EER_E4_RESETVAL (0x00000000U)
3985 #define CSL_EVETPCC_EER_E4_MAX (0x00000001U)
3987 #define CSL_EVETPCC_EER_E15_MASK (0x00008000U)
3988 #define CSL_EVETPCC_EER_E15_SHIFT (15U)
3989 #define CSL_EVETPCC_EER_E15_RESETVAL (0x00000000U)
3990 #define CSL_EVETPCC_EER_E15_MAX (0x00000001U)
3992 #define CSL_EVETPCC_EER_RESETVAL (0x00000000U)
3994 /* EERH */
3996 #define CSL_EVETPCC_EERH_E47_MASK (0x00008000U)
3997 #define CSL_EVETPCC_EERH_E47_SHIFT (15U)
3998 #define CSL_EVETPCC_EERH_E47_RESETVAL (0x00000000U)
3999 #define CSL_EVETPCC_EERH_E47_MAX (0x00000001U)
4001 #define CSL_EVETPCC_EERH_E45_MASK (0x00002000U)
4002 #define CSL_EVETPCC_EERH_E45_SHIFT (13U)
4003 #define CSL_EVETPCC_EERH_E45_RESETVAL (0x00000000U)
4004 #define CSL_EVETPCC_EERH_E45_MAX (0x00000001U)
4006 #define CSL_EVETPCC_EERH_E35_MASK (0x00000008U)
4007 #define CSL_EVETPCC_EERH_E35_SHIFT (3U)
4008 #define CSL_EVETPCC_EERH_E35_RESETVAL (0x00000000U)
4009 #define CSL_EVETPCC_EERH_E35_MAX (0x00000001U)
4011 #define CSL_EVETPCC_EERH_E56_MASK (0x01000000U)
4012 #define CSL_EVETPCC_EERH_E56_SHIFT (24U)
4013 #define CSL_EVETPCC_EERH_E56_RESETVAL (0x00000000U)
4014 #define CSL_EVETPCC_EERH_E56_MAX (0x00000001U)
4016 #define CSL_EVETPCC_EERH_E46_MASK (0x00004000U)
4017 #define CSL_EVETPCC_EERH_E46_SHIFT (14U)
4018 #define CSL_EVETPCC_EERH_E46_RESETVAL (0x00000000U)
4019 #define CSL_EVETPCC_EERH_E46_MAX (0x00000001U)
4021 #define CSL_EVETPCC_EERH_E36_MASK (0x00000010U)
4022 #define CSL_EVETPCC_EERH_E36_SHIFT (4U)
4023 #define CSL_EVETPCC_EERH_E36_RESETVAL (0x00000000U)
4024 #define CSL_EVETPCC_EERH_E36_MAX (0x00000001U)
4026 #define CSL_EVETPCC_EERH_E55_MASK (0x00800000U)
4027 #define CSL_EVETPCC_EERH_E55_SHIFT (23U)
4028 #define CSL_EVETPCC_EERH_E55_RESETVAL (0x00000000U)
4029 #define CSL_EVETPCC_EERH_E55_MAX (0x00000001U)
4031 #define CSL_EVETPCC_EERH_E33_MASK (0x00000002U)
4032 #define CSL_EVETPCC_EERH_E33_SHIFT (1U)
4033 #define CSL_EVETPCC_EERH_E33_RESETVAL (0x00000000U)
4034 #define CSL_EVETPCC_EERH_E33_MAX (0x00000001U)
4036 #define CSL_EVETPCC_EERH_E54_MASK (0x00400000U)
4037 #define CSL_EVETPCC_EERH_E54_SHIFT (22U)
4038 #define CSL_EVETPCC_EERH_E54_RESETVAL (0x00000000U)
4039 #define CSL_EVETPCC_EERH_E54_MAX (0x00000001U)
4041 #define CSL_EVETPCC_EERH_E43_MASK (0x00000800U)
4042 #define CSL_EVETPCC_EERH_E43_SHIFT (11U)
4043 #define CSL_EVETPCC_EERH_E43_RESETVAL (0x00000000U)
4044 #define CSL_EVETPCC_EERH_E43_MAX (0x00000001U)
4046 #define CSL_EVETPCC_EERH_E53_MASK (0x00200000U)
4047 #define CSL_EVETPCC_EERH_E53_SHIFT (21U)
4048 #define CSL_EVETPCC_EERH_E53_RESETVAL (0x00000000U)
4049 #define CSL_EVETPCC_EERH_E53_MAX (0x00000001U)
4051 #define CSL_EVETPCC_EERH_E63_MASK (0x80000000U)
4052 #define CSL_EVETPCC_EERH_E63_SHIFT (31U)
4053 #define CSL_EVETPCC_EERH_E63_RESETVAL (0x00000000U)
4054 #define CSL_EVETPCC_EERH_E63_MAX (0x00000001U)
4056 #define CSL_EVETPCC_EERH_E34_MASK (0x00000004U)
4057 #define CSL_EVETPCC_EERH_E34_SHIFT (2U)
4058 #define CSL_EVETPCC_EERH_E34_RESETVAL (0x00000000U)
4059 #define CSL_EVETPCC_EERH_E34_MAX (0x00000001U)
4061 #define CSL_EVETPCC_EERH_E44_MASK (0x00001000U)
4062 #define CSL_EVETPCC_EERH_E44_SHIFT (12U)
4063 #define CSL_EVETPCC_EERH_E44_RESETVAL (0x00000000U)
4064 #define CSL_EVETPCC_EERH_E44_MAX (0x00000001U)
4066 #define CSL_EVETPCC_EERH_E52_MASK (0x00100000U)
4067 #define CSL_EVETPCC_EERH_E52_SHIFT (20U)
4068 #define CSL_EVETPCC_EERH_E52_RESETVAL (0x00000000U)
4069 #define CSL_EVETPCC_EERH_E52_MAX (0x00000001U)
4071 #define CSL_EVETPCC_EERH_E41_MASK (0x00000200U)
4072 #define CSL_EVETPCC_EERH_E41_SHIFT (9U)
4073 #define CSL_EVETPCC_EERH_E41_RESETVAL (0x00000000U)
4074 #define CSL_EVETPCC_EERH_E41_MAX (0x00000001U)
4076 #define CSL_EVETPCC_EERH_E62_MASK (0x40000000U)
4077 #define CSL_EVETPCC_EERH_E62_SHIFT (30U)
4078 #define CSL_EVETPCC_EERH_E62_RESETVAL (0x00000000U)
4079 #define CSL_EVETPCC_EERH_E62_MAX (0x00000001U)
4081 #define CSL_EVETPCC_EERH_E32_MASK (0x00000001U)
4082 #define CSL_EVETPCC_EERH_E32_SHIFT (0U)
4083 #define CSL_EVETPCC_EERH_E32_RESETVAL (0x00000000U)
4084 #define CSL_EVETPCC_EERH_E32_MAX (0x00000001U)
4086 #define CSL_EVETPCC_EERH_E51_MASK (0x00080000U)
4087 #define CSL_EVETPCC_EERH_E51_SHIFT (19U)
4088 #define CSL_EVETPCC_EERH_E51_RESETVAL (0x00000000U)
4089 #define CSL_EVETPCC_EERH_E51_MAX (0x00000001U)
4091 #define CSL_EVETPCC_EERH_E42_MASK (0x00000400U)
4092 #define CSL_EVETPCC_EERH_E42_SHIFT (10U)
4093 #define CSL_EVETPCC_EERH_E42_RESETVAL (0x00000000U)
4094 #define CSL_EVETPCC_EERH_E42_MAX (0x00000001U)
4096 #define CSL_EVETPCC_EERH_E61_MASK (0x20000000U)
4097 #define CSL_EVETPCC_EERH_E61_SHIFT (29U)
4098 #define CSL_EVETPCC_EERH_E61_RESETVAL (0x00000000U)
4099 #define CSL_EVETPCC_EERH_E61_MAX (0x00000001U)
4101 #define CSL_EVETPCC_EERH_E50_MASK (0x00040000U)
4102 #define CSL_EVETPCC_EERH_E50_SHIFT (18U)
4103 #define CSL_EVETPCC_EERH_E50_RESETVAL (0x00000000U)
4104 #define CSL_EVETPCC_EERH_E50_MAX (0x00000001U)
4106 #define CSL_EVETPCC_EERH_E39_MASK (0x00000080U)
4107 #define CSL_EVETPCC_EERH_E39_SHIFT (7U)
4108 #define CSL_EVETPCC_EERH_E39_RESETVAL (0x00000000U)
4109 #define CSL_EVETPCC_EERH_E39_MAX (0x00000001U)
4111 #define CSL_EVETPCC_EERH_E60_MASK (0x10000000U)
4112 #define CSL_EVETPCC_EERH_E60_SHIFT (28U)
4113 #define CSL_EVETPCC_EERH_E60_RESETVAL (0x00000000U)
4114 #define CSL_EVETPCC_EERH_E60_MAX (0x00000001U)
4116 #define CSL_EVETPCC_EERH_E49_MASK (0x00020000U)
4117 #define CSL_EVETPCC_EERH_E49_SHIFT (17U)
4118 #define CSL_EVETPCC_EERH_E49_RESETVAL (0x00000000U)
4119 #define CSL_EVETPCC_EERH_E49_MAX (0x00000001U)
4121 #define CSL_EVETPCC_EERH_E40_MASK (0x00000100U)
4122 #define CSL_EVETPCC_EERH_E40_SHIFT (8U)
4123 #define CSL_EVETPCC_EERH_E40_RESETVAL (0x00000000U)
4124 #define CSL_EVETPCC_EERH_E40_MAX (0x00000001U)
4126 #define CSL_EVETPCC_EERH_E59_MASK (0x08000000U)
4127 #define CSL_EVETPCC_EERH_E59_SHIFT (27U)
4128 #define CSL_EVETPCC_EERH_E59_RESETVAL (0x00000000U)
4129 #define CSL_EVETPCC_EERH_E59_MAX (0x00000001U)
4131 #define CSL_EVETPCC_EERH_E48_MASK (0x00010000U)
4132 #define CSL_EVETPCC_EERH_E48_SHIFT (16U)
4133 #define CSL_EVETPCC_EERH_E48_RESETVAL (0x00000000U)
4134 #define CSL_EVETPCC_EERH_E48_MAX (0x00000001U)
4136 #define CSL_EVETPCC_EERH_E58_MASK (0x04000000U)
4137 #define CSL_EVETPCC_EERH_E58_SHIFT (26U)
4138 #define CSL_EVETPCC_EERH_E58_RESETVAL (0x00000000U)
4139 #define CSL_EVETPCC_EERH_E58_MAX (0x00000001U)
4141 #define CSL_EVETPCC_EERH_E37_MASK (0x00000020U)
4142 #define CSL_EVETPCC_EERH_E37_SHIFT (5U)
4143 #define CSL_EVETPCC_EERH_E37_RESETVAL (0x00000000U)
4144 #define CSL_EVETPCC_EERH_E37_MAX (0x00000001U)
4146 #define CSL_EVETPCC_EERH_E57_MASK (0x02000000U)
4147 #define CSL_EVETPCC_EERH_E57_SHIFT (25U)
4148 #define CSL_EVETPCC_EERH_E57_RESETVAL (0x00000000U)
4149 #define CSL_EVETPCC_EERH_E57_MAX (0x00000001U)
4151 #define CSL_EVETPCC_EERH_E38_MASK (0x00000040U)
4152 #define CSL_EVETPCC_EERH_E38_SHIFT (6U)
4153 #define CSL_EVETPCC_EERH_E38_RESETVAL (0x00000000U)
4154 #define CSL_EVETPCC_EERH_E38_MAX (0x00000001U)
4156 #define CSL_EVETPCC_EERH_RESETVAL (0x00000000U)
4158 /* EECR */
4160 #define CSL_EVETPCC_EECR_E30_MASK (0x40000000U)
4161 #define CSL_EVETPCC_EECR_E30_SHIFT (30U)
4162 #define CSL_EVETPCC_EECR_E30_RESETVAL (0x00000000U)
4163 #define CSL_EVETPCC_EECR_E30_MAX (0x00000001U)
4165 #define CSL_EVETPCC_EECR_E25_MASK (0x02000000U)
4166 #define CSL_EVETPCC_EECR_E25_SHIFT (25U)
4167 #define CSL_EVETPCC_EECR_E25_RESETVAL (0x00000000U)
4168 #define CSL_EVETPCC_EECR_E25_MAX (0x00000001U)
4170 #define CSL_EVETPCC_EECR_E14_MASK (0x00004000U)
4171 #define CSL_EVETPCC_EECR_E14_SHIFT (14U)
4172 #define CSL_EVETPCC_EECR_E14_RESETVAL (0x00000000U)
4173 #define CSL_EVETPCC_EECR_E14_MAX (0x00000001U)
4175 #define CSL_EVETPCC_EECR_E15_MASK (0x00008000U)
4176 #define CSL_EVETPCC_EECR_E15_SHIFT (15U)
4177 #define CSL_EVETPCC_EECR_E15_RESETVAL (0x00000000U)
4178 #define CSL_EVETPCC_EECR_E15_MAX (0x00000001U)
4180 #define CSL_EVETPCC_EECR_E5_MASK (0x00000020U)
4181 #define CSL_EVETPCC_EECR_E5_SHIFT (5U)
4182 #define CSL_EVETPCC_EECR_E5_RESETVAL (0x00000000U)
4183 #define CSL_EVETPCC_EECR_E5_MAX (0x00000001U)
4185 #define CSL_EVETPCC_EECR_E31_MASK (0x80000000U)
4186 #define CSL_EVETPCC_EECR_E31_SHIFT (31U)
4187 #define CSL_EVETPCC_EECR_E31_RESETVAL (0x00000000U)
4188 #define CSL_EVETPCC_EECR_E31_MAX (0x00000001U)
4190 #define CSL_EVETPCC_EECR_E24_MASK (0x01000000U)
4191 #define CSL_EVETPCC_EECR_E24_SHIFT (24U)
4192 #define CSL_EVETPCC_EECR_E24_RESETVAL (0x00000000U)
4193 #define CSL_EVETPCC_EECR_E24_MAX (0x00000001U)
4195 #define CSL_EVETPCC_EECR_E28_MASK (0x10000000U)
4196 #define CSL_EVETPCC_EECR_E28_SHIFT (28U)
4197 #define CSL_EVETPCC_EECR_E28_RESETVAL (0x00000000U)
4198 #define CSL_EVETPCC_EECR_E28_MAX (0x00000001U)
4200 #define CSL_EVETPCC_EECR_E6_MASK (0x00000040U)
4201 #define CSL_EVETPCC_EECR_E6_SHIFT (6U)
4202 #define CSL_EVETPCC_EECR_E6_RESETVAL (0x00000000U)
4203 #define CSL_EVETPCC_EECR_E6_MAX (0x00000001U)
4205 #define CSL_EVETPCC_EECR_E16_MASK (0x00010000U)
4206 #define CSL_EVETPCC_EECR_E16_SHIFT (16U)
4207 #define CSL_EVETPCC_EECR_E16_RESETVAL (0x00000000U)
4208 #define CSL_EVETPCC_EECR_E16_MAX (0x00000001U)
4210 #define CSL_EVETPCC_EECR_E29_MASK (0x20000000U)
4211 #define CSL_EVETPCC_EECR_E29_SHIFT (29U)
4212 #define CSL_EVETPCC_EECR_E29_RESETVAL (0x00000000U)
4213 #define CSL_EVETPCC_EECR_E29_MAX (0x00000001U)
4215 #define CSL_EVETPCC_EECR_E26_MASK (0x04000000U)
4216 #define CSL_EVETPCC_EECR_E26_SHIFT (26U)
4217 #define CSL_EVETPCC_EECR_E26_RESETVAL (0x00000000U)
4218 #define CSL_EVETPCC_EECR_E26_MAX (0x00000001U)
4220 #define CSL_EVETPCC_EECR_E8_MASK (0x00000100U)
4221 #define CSL_EVETPCC_EECR_E8_SHIFT (8U)
4222 #define CSL_EVETPCC_EECR_E8_RESETVAL (0x00000000U)
4223 #define CSL_EVETPCC_EECR_E8_MAX (0x00000001U)
4225 #define CSL_EVETPCC_EECR_E18_MASK (0x00040000U)
4226 #define CSL_EVETPCC_EECR_E18_SHIFT (18U)
4227 #define CSL_EVETPCC_EECR_E18_RESETVAL (0x00000000U)
4228 #define CSL_EVETPCC_EECR_E18_MAX (0x00000001U)
4230 #define CSL_EVETPCC_EECR_E7_MASK (0x00000080U)
4231 #define CSL_EVETPCC_EECR_E7_SHIFT (7U)
4232 #define CSL_EVETPCC_EECR_E7_RESETVAL (0x00000000U)
4233 #define CSL_EVETPCC_EECR_E7_MAX (0x00000001U)
4235 #define CSL_EVETPCC_EECR_E17_MASK (0x00020000U)
4236 #define CSL_EVETPCC_EECR_E17_SHIFT (17U)
4237 #define CSL_EVETPCC_EECR_E17_RESETVAL (0x00000000U)
4238 #define CSL_EVETPCC_EECR_E17_MAX (0x00000001U)
4240 #define CSL_EVETPCC_EECR_E10_MASK (0x00000400U)
4241 #define CSL_EVETPCC_EECR_E10_SHIFT (10U)
4242 #define CSL_EVETPCC_EECR_E10_RESETVAL (0x00000000U)
4243 #define CSL_EVETPCC_EECR_E10_MAX (0x00000001U)
4245 #define CSL_EVETPCC_EECR_E20_MASK (0x00100000U)
4246 #define CSL_EVETPCC_EECR_E20_SHIFT (20U)
4247 #define CSL_EVETPCC_EECR_E20_RESETVAL (0x00000000U)
4248 #define CSL_EVETPCC_EECR_E20_MAX (0x00000001U)
4250 #define CSL_EVETPCC_EECR_E9_MASK (0x00000200U)
4251 #define CSL_EVETPCC_EECR_E9_SHIFT (9U)
4252 #define CSL_EVETPCC_EECR_E9_RESETVAL (0x00000000U)
4253 #define CSL_EVETPCC_EECR_E9_MAX (0x00000001U)
4255 #define CSL_EVETPCC_EECR_E0_MASK (0x00000001U)
4256 #define CSL_EVETPCC_EECR_E0_SHIFT (0U)
4257 #define CSL_EVETPCC_EECR_E0_RESETVAL (0x00000000U)
4258 #define CSL_EVETPCC_EECR_E0_MAX (0x00000001U)
4260 #define CSL_EVETPCC_EECR_E19_MASK (0x00080000U)
4261 #define CSL_EVETPCC_EECR_E19_SHIFT (19U)
4262 #define CSL_EVETPCC_EECR_E19_RESETVAL (0x00000000U)
4263 #define CSL_EVETPCC_EECR_E19_MAX (0x00000001U)
4265 #define CSL_EVETPCC_EECR_E1_MASK (0x00000002U)
4266 #define CSL_EVETPCC_EECR_E1_SHIFT (1U)
4267 #define CSL_EVETPCC_EECR_E1_RESETVAL (0x00000000U)
4268 #define CSL_EVETPCC_EECR_E1_MAX (0x00000001U)
4270 #define CSL_EVETPCC_EECR_E12_MASK (0x00001000U)
4271 #define CSL_EVETPCC_EECR_E12_SHIFT (12U)
4272 #define CSL_EVETPCC_EECR_E12_RESETVAL (0x00000000U)
4273 #define CSL_EVETPCC_EECR_E12_MAX (0x00000001U)
4275 #define CSL_EVETPCC_EECR_E22_MASK (0x00400000U)
4276 #define CSL_EVETPCC_EECR_E22_SHIFT (22U)
4277 #define CSL_EVETPCC_EECR_E22_RESETVAL (0x00000000U)
4278 #define CSL_EVETPCC_EECR_E22_MAX (0x00000001U)
4280 #define CSL_EVETPCC_EECR_E2_MASK (0x00000004U)
4281 #define CSL_EVETPCC_EECR_E2_SHIFT (2U)
4282 #define CSL_EVETPCC_EECR_E2_RESETVAL (0x00000000U)
4283 #define CSL_EVETPCC_EECR_E2_MAX (0x00000001U)
4285 #define CSL_EVETPCC_EECR_E11_MASK (0x00000800U)
4286 #define CSL_EVETPCC_EECR_E11_SHIFT (11U)
4287 #define CSL_EVETPCC_EECR_E11_RESETVAL (0x00000000U)
4288 #define CSL_EVETPCC_EECR_E11_MAX (0x00000001U)
4290 #define CSL_EVETPCC_EECR_E21_MASK (0x00200000U)
4291 #define CSL_EVETPCC_EECR_E21_SHIFT (21U)
4292 #define CSL_EVETPCC_EECR_E21_RESETVAL (0x00000000U)
4293 #define CSL_EVETPCC_EECR_E21_MAX (0x00000001U)
4295 #define CSL_EVETPCC_EECR_E27_MASK (0x08000000U)
4296 #define CSL_EVETPCC_EECR_E27_SHIFT (27U)
4297 #define CSL_EVETPCC_EECR_E27_RESETVAL (0x00000000U)
4298 #define CSL_EVETPCC_EECR_E27_MAX (0x00000001U)
4300 #define CSL_EVETPCC_EECR_E3_MASK (0x00000008U)
4301 #define CSL_EVETPCC_EECR_E3_SHIFT (3U)
4302 #define CSL_EVETPCC_EECR_E3_RESETVAL (0x00000000U)
4303 #define CSL_EVETPCC_EECR_E3_MAX (0x00000001U)
4305 #define CSL_EVETPCC_EECR_E23_MASK (0x00800000U)
4306 #define CSL_EVETPCC_EECR_E23_SHIFT (23U)
4307 #define CSL_EVETPCC_EECR_E23_RESETVAL (0x00000000U)
4308 #define CSL_EVETPCC_EECR_E23_MAX (0x00000001U)
4310 #define CSL_EVETPCC_EECR_E4_MASK (0x00000010U)
4311 #define CSL_EVETPCC_EECR_E4_SHIFT (4U)
4312 #define CSL_EVETPCC_EECR_E4_RESETVAL (0x00000000U)
4313 #define CSL_EVETPCC_EECR_E4_MAX (0x00000001U)
4315 #define CSL_EVETPCC_EECR_E13_MASK (0x00002000U)
4316 #define CSL_EVETPCC_EECR_E13_SHIFT (13U)
4317 #define CSL_EVETPCC_EECR_E13_RESETVAL (0x00000000U)
4318 #define CSL_EVETPCC_EECR_E13_MAX (0x00000001U)
4320 #define CSL_EVETPCC_EECR_RESETVAL (0x00000000U)
4322 /* EECRH */
4324 #define CSL_EVETPCC_EECRH_E62_MASK (0x40000000U)
4325 #define CSL_EVETPCC_EECRH_E62_SHIFT (30U)
4326 #define CSL_EVETPCC_EECRH_E62_RESETVAL (0x00000000U)
4327 #define CSL_EVETPCC_EECRH_E62_MAX (0x00000001U)
4329 #define CSL_EVETPCC_EECRH_E37_MASK (0x00000020U)
4330 #define CSL_EVETPCC_EECRH_E37_SHIFT (5U)
4331 #define CSL_EVETPCC_EECRH_E37_RESETVAL (0x00000000U)
4332 #define CSL_EVETPCC_EECRH_E37_MAX (0x00000001U)
4334 #define CSL_EVETPCC_EECRH_E51_MASK (0x00080000U)
4335 #define CSL_EVETPCC_EECRH_E51_SHIFT (19U)
4336 #define CSL_EVETPCC_EECRH_E51_RESETVAL (0x00000000U)
4337 #define CSL_EVETPCC_EECRH_E51_MAX (0x00000001U)
4339 #define CSL_EVETPCC_EECRH_E36_MASK (0x00000010U)
4340 #define CSL_EVETPCC_EECRH_E36_SHIFT (4U)
4341 #define CSL_EVETPCC_EECRH_E36_RESETVAL (0x00000000U)
4342 #define CSL_EVETPCC_EECRH_E36_MAX (0x00000001U)
4344 #define CSL_EVETPCC_EECRH_E50_MASK (0x00040000U)
4345 #define CSL_EVETPCC_EECRH_E50_SHIFT (18U)
4346 #define CSL_EVETPCC_EECRH_E50_RESETVAL (0x00000000U)
4347 #define CSL_EVETPCC_EECRH_E50_MAX (0x00000001U)
4349 #define CSL_EVETPCC_EECRH_E35_MASK (0x00000008U)
4350 #define CSL_EVETPCC_EECRH_E35_SHIFT (3U)
4351 #define CSL_EVETPCC_EECRH_E35_RESETVAL (0x00000000U)
4352 #define CSL_EVETPCC_EECRH_E35_MAX (0x00000001U)
4354 #define CSL_EVETPCC_EECRH_E63_MASK (0x80000000U)
4355 #define CSL_EVETPCC_EECRH_E63_SHIFT (31U)
4356 #define CSL_EVETPCC_EECRH_E63_RESETVAL (0x00000000U)
4357 #define CSL_EVETPCC_EECRH_E63_MAX (0x00000001U)
4359 #define CSL_EVETPCC_EECRH_E54_MASK (0x00400000U)
4360 #define CSL_EVETPCC_EECRH_E54_SHIFT (22U)
4361 #define CSL_EVETPCC_EECRH_E54_RESETVAL (0x00000000U)
4362 #define CSL_EVETPCC_EECRH_E54_MAX (0x00000001U)
4364 #define CSL_EVETPCC_EECRH_E58_MASK (0x04000000U)
4365 #define CSL_EVETPCC_EECRH_E58_SHIFT (26U)
4366 #define CSL_EVETPCC_EECRH_E58_RESETVAL (0x00000000U)
4367 #define CSL_EVETPCC_EECRH_E58_MAX (0x00000001U)
4369 #define CSL_EVETPCC_EECRH_E48_MASK (0x00010000U)
4370 #define CSL_EVETPCC_EECRH_E48_SHIFT (16U)
4371 #define CSL_EVETPCC_EECRH_E48_RESETVAL (0x00000000U)
4372 #define CSL_EVETPCC_EECRH_E48_MAX (0x00000001U)
4374 #define CSL_EVETPCC_EECRH_E59_MASK (0x08000000U)
4375 #define CSL_EVETPCC_EECRH_E59_SHIFT (27U)
4376 #define CSL_EVETPCC_EECRH_E59_RESETVAL (0x00000000U)
4377 #define CSL_EVETPCC_EECRH_E59_MAX (0x00000001U)
4379 #define CSL_EVETPCC_EECRH_E53_MASK (0x00200000U)
4380 #define CSL_EVETPCC_EECRH_E53_SHIFT (21U)
4381 #define CSL_EVETPCC_EECRH_E53_RESETVAL (0x00000000U)
4382 #define CSL_EVETPCC_EECRH_E53_MAX (0x00000001U)
4384 #define CSL_EVETPCC_EECRH_E49_MASK (0x00020000U)
4385 #define CSL_EVETPCC_EECRH_E49_SHIFT (17U)
4386 #define CSL_EVETPCC_EECRH_E49_RESETVAL (0x00000000U)
4387 #define CSL_EVETPCC_EECRH_E49_MAX (0x00000001U)
4389 #define CSL_EVETPCC_EECRH_E60_MASK (0x10000000U)
4390 #define CSL_EVETPCC_EECRH_E60_SHIFT (28U)
4391 #define CSL_EVETPCC_EECRH_E60_RESETVAL (0x00000000U)
4392 #define CSL_EVETPCC_EECRH_E60_MAX (0x00000001U)
4394 #define CSL_EVETPCC_EECRH_E61_MASK (0x20000000U)
4395 #define CSL_EVETPCC_EECRH_E61_SHIFT (29U)
4396 #define CSL_EVETPCC_EECRH_E61_RESETVAL (0x00000000U)
4397 #define CSL_EVETPCC_EECRH_E61_MAX (0x00000001U)
4399 #define CSL_EVETPCC_EECRH_E52_MASK (0x00100000U)
4400 #define CSL_EVETPCC_EECRH_E52_SHIFT (20U)
4401 #define CSL_EVETPCC_EECRH_E52_RESETVAL (0x00000000U)
4402 #define CSL_EVETPCC_EECRH_E52_MAX (0x00000001U)
4404 #define CSL_EVETPCC_EECRH_E44_MASK (0x00001000U)
4405 #define CSL_EVETPCC_EECRH_E44_SHIFT (12U)
4406 #define CSL_EVETPCC_EECRH_E44_RESETVAL (0x00000000U)
4407 #define CSL_EVETPCC_EECRH_E44_MAX (0x00000001U)
4409 #define CSL_EVETPCC_EECRH_E34_MASK (0x00000004U)
4410 #define CSL_EVETPCC_EECRH_E34_SHIFT (2U)
4411 #define CSL_EVETPCC_EECRH_E34_RESETVAL (0x00000000U)
4412 #define CSL_EVETPCC_EECRH_E34_MAX (0x00000001U)
4414 #define CSL_EVETPCC_EECRH_E43_MASK (0x00000800U)
4415 #define CSL_EVETPCC_EECRH_E43_SHIFT (11U)
4416 #define CSL_EVETPCC_EECRH_E43_RESETVAL (0x00000000U)
4417 #define CSL_EVETPCC_EECRH_E43_MAX (0x00000001U)
4419 #define CSL_EVETPCC_EECRH_E33_MASK (0x00000002U)
4420 #define CSL_EVETPCC_EECRH_E33_SHIFT (1U)
4421 #define CSL_EVETPCC_EECRH_E33_RESETVAL (0x00000000U)
4422 #define CSL_EVETPCC_EECRH_E33_MAX (0x00000001U)
4424 #define CSL_EVETPCC_EECRH_E55_MASK (0x00800000U)
4425 #define CSL_EVETPCC_EECRH_E55_SHIFT (23U)
4426 #define CSL_EVETPCC_EECRH_E55_RESETVAL (0x00000000U)
4427 #define CSL_EVETPCC_EECRH_E55_MAX (0x00000001U)
4429 #define CSL_EVETPCC_EECRH_E42_MASK (0x00000400U)
4430 #define CSL_EVETPCC_EECRH_E42_SHIFT (10U)
4431 #define CSL_EVETPCC_EECRH_E42_RESETVAL (0x00000000U)
4432 #define CSL_EVETPCC_EECRH_E42_MAX (0x00000001U)
4434 #define CSL_EVETPCC_EECRH_E56_MASK (0x01000000U)
4435 #define CSL_EVETPCC_EECRH_E56_SHIFT (24U)
4436 #define CSL_EVETPCC_EECRH_E56_RESETVAL (0x00000000U)
4437 #define CSL_EVETPCC_EECRH_E56_MAX (0x00000001U)
4439 #define CSL_EVETPCC_EECRH_E32_MASK (0x00000001U)
4440 #define CSL_EVETPCC_EECRH_E32_SHIFT (0U)
4441 #define CSL_EVETPCC_EECRH_E32_RESETVAL (0x00000000U)
4442 #define CSL_EVETPCC_EECRH_E32_MAX (0x00000001U)
4444 #define CSL_EVETPCC_EECRH_E41_MASK (0x00000200U)
4445 #define CSL_EVETPCC_EECRH_E41_SHIFT (9U)
4446 #define CSL_EVETPCC_EECRH_E41_RESETVAL (0x00000000U)
4447 #define CSL_EVETPCC_EECRH_E41_MAX (0x00000001U)
4449 #define CSL_EVETPCC_EECRH_E57_MASK (0x02000000U)
4450 #define CSL_EVETPCC_EECRH_E57_SHIFT (25U)
4451 #define CSL_EVETPCC_EECRH_E57_RESETVAL (0x00000000U)
4452 #define CSL_EVETPCC_EECRH_E57_MAX (0x00000001U)
4454 #define CSL_EVETPCC_EECRH_E47_MASK (0x00008000U)
4455 #define CSL_EVETPCC_EECRH_E47_SHIFT (15U)
4456 #define CSL_EVETPCC_EECRH_E47_RESETVAL (0x00000000U)
4457 #define CSL_EVETPCC_EECRH_E47_MAX (0x00000001U)
4459 #define CSL_EVETPCC_EECRH_E40_MASK (0x00000100U)
4460 #define CSL_EVETPCC_EECRH_E40_SHIFT (8U)
4461 #define CSL_EVETPCC_EECRH_E40_RESETVAL (0x00000000U)
4462 #define CSL_EVETPCC_EECRH_E40_MAX (0x00000001U)
4464 #define CSL_EVETPCC_EECRH_E46_MASK (0x00004000U)
4465 #define CSL_EVETPCC_EECRH_E46_SHIFT (14U)
4466 #define CSL_EVETPCC_EECRH_E46_RESETVAL (0x00000000U)
4467 #define CSL_EVETPCC_EECRH_E46_MAX (0x00000001U)
4469 #define CSL_EVETPCC_EECRH_E39_MASK (0x00000080U)
4470 #define CSL_EVETPCC_EECRH_E39_SHIFT (7U)
4471 #define CSL_EVETPCC_EECRH_E39_RESETVAL (0x00000000U)
4472 #define CSL_EVETPCC_EECRH_E39_MAX (0x00000001U)
4474 #define CSL_EVETPCC_EECRH_E45_MASK (0x00002000U)
4475 #define CSL_EVETPCC_EECRH_E45_SHIFT (13U)
4476 #define CSL_EVETPCC_EECRH_E45_RESETVAL (0x00000000U)
4477 #define CSL_EVETPCC_EECRH_E45_MAX (0x00000001U)
4479 #define CSL_EVETPCC_EECRH_E38_MASK (0x00000040U)
4480 #define CSL_EVETPCC_EECRH_E38_SHIFT (6U)
4481 #define CSL_EVETPCC_EECRH_E38_RESETVAL (0x00000000U)
4482 #define CSL_EVETPCC_EECRH_E38_MAX (0x00000001U)
4484 #define CSL_EVETPCC_EECRH_RESETVAL (0x00000000U)
4486 /* EESR */
4488 #define CSL_EVETPCC_EESR_E15_MASK (0x00008000U)
4489 #define CSL_EVETPCC_EESR_E15_SHIFT (15U)
4490 #define CSL_EVETPCC_EESR_E15_RESETVAL (0x00000000U)
4491 #define CSL_EVETPCC_EESR_E15_MAX (0x00000001U)
4493 #define CSL_EVETPCC_EESR_E6_MASK (0x00000040U)
4494 #define CSL_EVETPCC_EESR_E6_SHIFT (6U)
4495 #define CSL_EVETPCC_EESR_E6_RESETVAL (0x00000000U)
4496 #define CSL_EVETPCC_EESR_E6_MAX (0x00000001U)
4498 #define CSL_EVETPCC_EESR_E16_MASK (0x00010000U)
4499 #define CSL_EVETPCC_EESR_E16_SHIFT (16U)
4500 #define CSL_EVETPCC_EESR_E16_RESETVAL (0x00000000U)
4501 #define CSL_EVETPCC_EESR_E16_MAX (0x00000001U)
4503 #define CSL_EVETPCC_EESR_E30_MASK (0x40000000U)
4504 #define CSL_EVETPCC_EESR_E30_SHIFT (30U)
4505 #define CSL_EVETPCC_EESR_E30_RESETVAL (0x00000000U)
4506 #define CSL_EVETPCC_EESR_E30_MAX (0x00000001U)
4508 #define CSL_EVETPCC_EESR_E7_MASK (0x00000080U)
4509 #define CSL_EVETPCC_EESR_E7_SHIFT (7U)
4510 #define CSL_EVETPCC_EESR_E7_RESETVAL (0x00000000U)
4511 #define CSL_EVETPCC_EESR_E7_MAX (0x00000001U)
4513 #define CSL_EVETPCC_EESR_E4_MASK (0x00000010U)
4514 #define CSL_EVETPCC_EESR_E4_SHIFT (4U)
4515 #define CSL_EVETPCC_EESR_E4_RESETVAL (0x00000000U)
4516 #define CSL_EVETPCC_EESR_E4_MAX (0x00000001U)
4518 #define CSL_EVETPCC_EESR_E5_MASK (0x00000020U)
4519 #define CSL_EVETPCC_EESR_E5_SHIFT (5U)
4520 #define CSL_EVETPCC_EESR_E5_RESETVAL (0x00000000U)
4521 #define CSL_EVETPCC_EESR_E5_MAX (0x00000001U)
4523 #define CSL_EVETPCC_EESR_E29_MASK (0x20000000U)
4524 #define CSL_EVETPCC_EESR_E29_SHIFT (29U)
4525 #define CSL_EVETPCC_EESR_E29_RESETVAL (0x00000000U)
4526 #define CSL_EVETPCC_EESR_E29_MAX (0x00000001U)
4528 #define CSL_EVETPCC_EESR_E0_MASK (0x00000001U)
4529 #define CSL_EVETPCC_EESR_E0_SHIFT (0U)
4530 #define CSL_EVETPCC_EESR_E0_RESETVAL (0x00000000U)
4531 #define CSL_EVETPCC_EESR_E0_MAX (0x00000001U)
4533 #define CSL_EVETPCC_EESR_E10_MASK (0x00000400U)
4534 #define CSL_EVETPCC_EESR_E10_SHIFT (10U)
4535 #define CSL_EVETPCC_EESR_E10_RESETVAL (0x00000000U)
4536 #define CSL_EVETPCC_EESR_E10_MAX (0x00000001U)
4538 #define CSL_EVETPCC_EESR_E28_MASK (0x10000000U)
4539 #define CSL_EVETPCC_EESR_E28_SHIFT (28U)
4540 #define CSL_EVETPCC_EESR_E28_RESETVAL (0x00000000U)
4541 #define CSL_EVETPCC_EESR_E28_MAX (0x00000001U)
4543 #define CSL_EVETPCC_EESR_E27_MASK (0x08000000U)
4544 #define CSL_EVETPCC_EESR_E27_SHIFT (27U)
4545 #define CSL_EVETPCC_EESR_E27_RESETVAL (0x00000000U)
4546 #define CSL_EVETPCC_EESR_E27_MAX (0x00000001U)
4548 #define CSL_EVETPCC_EESR_E26_MASK (0x04000000U)
4549 #define CSL_EVETPCC_EESR_E26_SHIFT (26U)
4550 #define CSL_EVETPCC_EESR_E26_RESETVAL (0x00000000U)
4551 #define CSL_EVETPCC_EESR_E26_MAX (0x00000001U)
4553 #define CSL_EVETPCC_EESR_E8_MASK (0x00000100U)
4554 #define CSL_EVETPCC_EESR_E8_SHIFT (8U)
4555 #define CSL_EVETPCC_EESR_E8_RESETVAL (0x00000000U)
4556 #define CSL_EVETPCC_EESR_E8_MAX (0x00000001U)
4558 #define CSL_EVETPCC_EESR_E9_MASK (0x00000200U)
4559 #define CSL_EVETPCC_EESR_E9_SHIFT (9U)
4560 #define CSL_EVETPCC_EESR_E9_RESETVAL (0x00000000U)
4561 #define CSL_EVETPCC_EESR_E9_MAX (0x00000001U)
4563 #define CSL_EVETPCC_EESR_E25_MASK (0x02000000U)
4564 #define CSL_EVETPCC_EESR_E25_SHIFT (25U)
4565 #define CSL_EVETPCC_EESR_E25_RESETVAL (0x00000000U)
4566 #define CSL_EVETPCC_EESR_E25_MAX (0x00000001U)
4568 #define CSL_EVETPCC_EESR_E24_MASK (0x01000000U)
4569 #define CSL_EVETPCC_EESR_E24_SHIFT (24U)
4570 #define CSL_EVETPCC_EESR_E24_RESETVAL (0x00000000U)
4571 #define CSL_EVETPCC_EESR_E24_MAX (0x00000001U)
4573 #define CSL_EVETPCC_EESR_E11_MASK (0x00000800U)
4574 #define CSL_EVETPCC_EESR_E11_SHIFT (11U)
4575 #define CSL_EVETPCC_EESR_E11_RESETVAL (0x00000000U)
4576 #define CSL_EVETPCC_EESR_E11_MAX (0x00000001U)
4578 #define CSL_EVETPCC_EESR_E23_MASK (0x00800000U)
4579 #define CSL_EVETPCC_EESR_E23_SHIFT (23U)
4580 #define CSL_EVETPCC_EESR_E23_RESETVAL (0x00000000U)
4581 #define CSL_EVETPCC_EESR_E23_MAX (0x00000001U)
4583 #define CSL_EVETPCC_EESR_E20_MASK (0x00100000U)
4584 #define CSL_EVETPCC_EESR_E20_SHIFT (20U)
4585 #define CSL_EVETPCC_EESR_E20_RESETVAL (0x00000000U)
4586 #define CSL_EVETPCC_EESR_E20_MAX (0x00000001U)
4588 #define CSL_EVETPCC_EESR_E22_MASK (0x00400000U)
4589 #define CSL_EVETPCC_EESR_E22_SHIFT (22U)
4590 #define CSL_EVETPCC_EESR_E22_RESETVAL (0x00000000U)
4591 #define CSL_EVETPCC_EESR_E22_MAX (0x00000001U)
4593 #define CSL_EVETPCC_EESR_E21_MASK (0x00200000U)
4594 #define CSL_EVETPCC_EESR_E21_SHIFT (21U)
4595 #define CSL_EVETPCC_EESR_E21_RESETVAL (0x00000000U)
4596 #define CSL_EVETPCC_EESR_E21_MAX (0x00000001U)
4598 #define CSL_EVETPCC_EESR_E2_MASK (0x00000004U)
4599 #define CSL_EVETPCC_EESR_E2_SHIFT (2U)
4600 #define CSL_EVETPCC_EESR_E2_RESETVAL (0x00000000U)
4601 #define CSL_EVETPCC_EESR_E2_MAX (0x00000001U)
4603 #define CSL_EVETPCC_EESR_E18_MASK (0x00040000U)
4604 #define CSL_EVETPCC_EESR_E18_SHIFT (18U)
4605 #define CSL_EVETPCC_EESR_E18_RESETVAL (0x00000000U)
4606 #define CSL_EVETPCC_EESR_E18_MAX (0x00000001U)
4608 #define CSL_EVETPCC_EESR_E3_MASK (0x00000008U)
4609 #define CSL_EVETPCC_EESR_E3_SHIFT (3U)
4610 #define CSL_EVETPCC_EESR_E3_RESETVAL (0x00000000U)
4611 #define CSL_EVETPCC_EESR_E3_MAX (0x00000001U)
4613 #define CSL_EVETPCC_EESR_E19_MASK (0x00080000U)
4614 #define CSL_EVETPCC_EESR_E19_SHIFT (19U)
4615 #define CSL_EVETPCC_EESR_E19_RESETVAL (0x00000000U)
4616 #define CSL_EVETPCC_EESR_E19_MAX (0x00000001U)
4618 #define CSL_EVETPCC_EESR_E31_MASK (0x80000000U)
4619 #define CSL_EVETPCC_EESR_E31_SHIFT (31U)
4620 #define CSL_EVETPCC_EESR_E31_RESETVAL (0x00000000U)
4621 #define CSL_EVETPCC_EESR_E31_MAX (0x00000001U)
4623 #define CSL_EVETPCC_EESR_E13_MASK (0x00002000U)
4624 #define CSL_EVETPCC_EESR_E13_SHIFT (13U)
4625 #define CSL_EVETPCC_EESR_E13_RESETVAL (0x00000000U)
4626 #define CSL_EVETPCC_EESR_E13_MAX (0x00000001U)
4628 #define CSL_EVETPCC_EESR_E12_MASK (0x00001000U)
4629 #define CSL_EVETPCC_EESR_E12_SHIFT (12U)
4630 #define CSL_EVETPCC_EESR_E12_RESETVAL (0x00000000U)
4631 #define CSL_EVETPCC_EESR_E12_MAX (0x00000001U)
4633 #define CSL_EVETPCC_EESR_E14_MASK (0x00004000U)
4634 #define CSL_EVETPCC_EESR_E14_SHIFT (14U)
4635 #define CSL_EVETPCC_EESR_E14_RESETVAL (0x00000000U)
4636 #define CSL_EVETPCC_EESR_E14_MAX (0x00000001U)
4638 #define CSL_EVETPCC_EESR_E1_MASK (0x00000002U)
4639 #define CSL_EVETPCC_EESR_E1_SHIFT (1U)
4640 #define CSL_EVETPCC_EESR_E1_RESETVAL (0x00000000U)
4641 #define CSL_EVETPCC_EESR_E1_MAX (0x00000001U)
4643 #define CSL_EVETPCC_EESR_E17_MASK (0x00020000U)
4644 #define CSL_EVETPCC_EESR_E17_SHIFT (17U)
4645 #define CSL_EVETPCC_EESR_E17_RESETVAL (0x00000000U)
4646 #define CSL_EVETPCC_EESR_E17_MAX (0x00000001U)
4648 #define CSL_EVETPCC_EESR_RESETVAL (0x00000000U)
4650 /* EESRH */
4652 #define CSL_EVETPCC_EESRH_E33_MASK (0x00000002U)
4653 #define CSL_EVETPCC_EESRH_E33_SHIFT (1U)
4654 #define CSL_EVETPCC_EESRH_E33_RESETVAL (0x00000000U)
4655 #define CSL_EVETPCC_EESRH_E33_MAX (0x00000001U)
4657 #define CSL_EVETPCC_EESRH_E35_MASK (0x00000008U)
4658 #define CSL_EVETPCC_EESRH_E35_SHIFT (3U)
4659 #define CSL_EVETPCC_EESRH_E35_RESETVAL (0x00000000U)
4660 #define CSL_EVETPCC_EESRH_E35_MAX (0x00000001U)
4662 #define CSL_EVETPCC_EESRH_E44_MASK (0x00001000U)
4663 #define CSL_EVETPCC_EESRH_E44_SHIFT (12U)
4664 #define CSL_EVETPCC_EESRH_E44_RESETVAL (0x00000000U)
4665 #define CSL_EVETPCC_EESRH_E44_MAX (0x00000001U)
4667 #define CSL_EVETPCC_EESRH_E32_MASK (0x00000001U)
4668 #define CSL_EVETPCC_EESRH_E32_SHIFT (0U)
4669 #define CSL_EVETPCC_EESRH_E32_RESETVAL (0x00000000U)
4670 #define CSL_EVETPCC_EESRH_E32_MAX (0x00000001U)
4672 #define CSL_EVETPCC_EESRH_E43_MASK (0x00000800U)
4673 #define CSL_EVETPCC_EESRH_E43_SHIFT (11U)
4674 #define CSL_EVETPCC_EESRH_E43_RESETVAL (0x00000000U)
4675 #define CSL_EVETPCC_EESRH_E43_MAX (0x00000001U)
4677 #define CSL_EVETPCC_EESRH_E55_MASK (0x00800000U)
4678 #define CSL_EVETPCC_EESRH_E55_SHIFT (23U)
4679 #define CSL_EVETPCC_EESRH_E55_RESETVAL (0x00000000U)
4680 #define CSL_EVETPCC_EESRH_E55_MAX (0x00000001U)
4682 #define CSL_EVETPCC_EESRH_E42_MASK (0x00000400U)
4683 #define CSL_EVETPCC_EESRH_E42_SHIFT (10U)
4684 #define CSL_EVETPCC_EESRH_E42_RESETVAL (0x00000000U)
4685 #define CSL_EVETPCC_EESRH_E42_MAX (0x00000001U)
4687 #define CSL_EVETPCC_EESRH_E54_MASK (0x00400000U)
4688 #define CSL_EVETPCC_EESRH_E54_SHIFT (22U)
4689 #define CSL_EVETPCC_EESRH_E54_RESETVAL (0x00000000U)
4690 #define CSL_EVETPCC_EESRH_E54_MAX (0x00000001U)
4692 #define CSL_EVETPCC_EESRH_E53_MASK (0x00200000U)
4693 #define CSL_EVETPCC_EESRH_E53_SHIFT (21U)
4694 #define CSL_EVETPCC_EESRH_E53_RESETVAL (0x00000000U)
4695 #define CSL_EVETPCC_EESRH_E53_MAX (0x00000001U)
4697 #define CSL_EVETPCC_EESRH_E56_MASK (0x01000000U)
4698 #define CSL_EVETPCC_EESRH_E56_SHIFT (24U)
4699 #define CSL_EVETPCC_EESRH_E56_RESETVAL (0x00000000U)
4700 #define CSL_EVETPCC_EESRH_E56_MAX (0x00000001U)
4702 #define CSL_EVETPCC_EESRH_E41_MASK (0x00000200U)
4703 #define CSL_EVETPCC_EESRH_E41_SHIFT (9U)
4704 #define CSL_EVETPCC_EESRH_E41_RESETVAL (0x00000000U)
4705 #define CSL_EVETPCC_EESRH_E41_MAX (0x00000001U)
4707 #define CSL_EVETPCC_EESRH_E40_MASK (0x00000100U)
4708 #define CSL_EVETPCC_EESRH_E40_SHIFT (8U)
4709 #define CSL_EVETPCC_EESRH_E40_RESETVAL (0x00000000U)
4710 #define CSL_EVETPCC_EESRH_E40_MAX (0x00000001U)
4712 #define CSL_EVETPCC_EESRH_E57_MASK (0x02000000U)
4713 #define CSL_EVETPCC_EESRH_E57_SHIFT (25U)
4714 #define CSL_EVETPCC_EESRH_E57_RESETVAL (0x00000000U)
4715 #define CSL_EVETPCC_EESRH_E57_MAX (0x00000001U)
4717 #define CSL_EVETPCC_EESRH_E52_MASK (0x00100000U)
4718 #define CSL_EVETPCC_EESRH_E52_SHIFT (20U)
4719 #define CSL_EVETPCC_EESRH_E52_RESETVAL (0x00000000U)
4720 #define CSL_EVETPCC_EESRH_E52_MAX (0x00000001U)
4722 #define CSL_EVETPCC_EESRH_E34_MASK (0x00000004U)
4723 #define CSL_EVETPCC_EESRH_E34_SHIFT (2U)
4724 #define CSL_EVETPCC_EESRH_E34_RESETVAL (0x00000000U)
4725 #define CSL_EVETPCC_EESRH_E34_MAX (0x00000001U)
4727 #define CSL_EVETPCC_EESRH_E39_MASK (0x00000080U)
4728 #define CSL_EVETPCC_EESRH_E39_SHIFT (7U)
4729 #define CSL_EVETPCC_EESRH_E39_RESETVAL (0x00000000U)
4730 #define CSL_EVETPCC_EESRH_E39_MAX (0x00000001U)
4732 #define CSL_EVETPCC_EESRH_E58_MASK (0x04000000U)
4733 #define CSL_EVETPCC_EESRH_E58_SHIFT (26U)
4734 #define CSL_EVETPCC_EESRH_E58_RESETVAL (0x00000000U)
4735 #define CSL_EVETPCC_EESRH_E58_MAX (0x00000001U)
4737 #define CSL_EVETPCC_EESRH_E51_MASK (0x00080000U)
4738 #define CSL_EVETPCC_EESRH_E51_SHIFT (19U)
4739 #define CSL_EVETPCC_EESRH_E51_RESETVAL (0x00000000U)
4740 #define CSL_EVETPCC_EESRH_E51_MAX (0x00000001U)
4742 #define CSL_EVETPCC_EESRH_E36_MASK (0x00000010U)
4743 #define CSL_EVETPCC_EESRH_E36_SHIFT (4U)
4744 #define CSL_EVETPCC_EESRH_E36_RESETVAL (0x00000000U)
4745 #define CSL_EVETPCC_EESRH_E36_MAX (0x00000001U)
4747 #define CSL_EVETPCC_EESRH_E38_MASK (0x00000040U)
4748 #define CSL_EVETPCC_EESRH_E38_SHIFT (6U)
4749 #define CSL_EVETPCC_EESRH_E38_RESETVAL (0x00000000U)
4750 #define CSL_EVETPCC_EESRH_E38_MAX (0x00000001U)
4752 #define CSL_EVETPCC_EESRH_E59_MASK (0x08000000U)
4753 #define CSL_EVETPCC_EESRH_E59_SHIFT (27U)
4754 #define CSL_EVETPCC_EESRH_E59_RESETVAL (0x00000000U)
4755 #define CSL_EVETPCC_EESRH_E59_MAX (0x00000001U)
4757 #define CSL_EVETPCC_EESRH_E50_MASK (0x00040000U)
4758 #define CSL_EVETPCC_EESRH_E50_SHIFT (18U)
4759 #define CSL_EVETPCC_EESRH_E50_RESETVAL (0x00000000U)
4760 #define CSL_EVETPCC_EESRH_E50_MAX (0x00000001U)
4762 #define CSL_EVETPCC_EESRH_E37_MASK (0x00000020U)
4763 #define CSL_EVETPCC_EESRH_E37_SHIFT (5U)
4764 #define CSL_EVETPCC_EESRH_E37_RESETVAL (0x00000000U)
4765 #define CSL_EVETPCC_EESRH_E37_MAX (0x00000001U)
4767 #define CSL_EVETPCC_EESRH_E60_MASK (0x10000000U)
4768 #define CSL_EVETPCC_EESRH_E60_SHIFT (28U)
4769 #define CSL_EVETPCC_EESRH_E60_RESETVAL (0x00000000U)
4770 #define CSL_EVETPCC_EESRH_E60_MAX (0x00000001U)
4772 #define CSL_EVETPCC_EESRH_E49_MASK (0x00020000U)
4773 #define CSL_EVETPCC_EESRH_E49_SHIFT (17U)
4774 #define CSL_EVETPCC_EESRH_E49_RESETVAL (0x00000000U)
4775 #define CSL_EVETPCC_EESRH_E49_MAX (0x00000001U)
4777 #define CSL_EVETPCC_EESRH_E61_MASK (0x20000000U)
4778 #define CSL_EVETPCC_EESRH_E61_SHIFT (29U)
4779 #define CSL_EVETPCC_EESRH_E61_RESETVAL (0x00000000U)
4780 #define CSL_EVETPCC_EESRH_E61_MAX (0x00000001U)
4782 #define CSL_EVETPCC_EESRH_E48_MASK (0x00010000U)
4783 #define CSL_EVETPCC_EESRH_E48_SHIFT (16U)
4784 #define CSL_EVETPCC_EESRH_E48_RESETVAL (0x00000000U)
4785 #define CSL_EVETPCC_EESRH_E48_MAX (0x00000001U)
4787 #define CSL_EVETPCC_EESRH_E62_MASK (0x40000000U)
4788 #define CSL_EVETPCC_EESRH_E62_SHIFT (30U)
4789 #define CSL_EVETPCC_EESRH_E62_RESETVAL (0x00000000U)
4790 #define CSL_EVETPCC_EESRH_E62_MAX (0x00000001U)
4792 #define CSL_EVETPCC_EESRH_E47_MASK (0x00008000U)
4793 #define CSL_EVETPCC_EESRH_E47_SHIFT (15U)
4794 #define CSL_EVETPCC_EESRH_E47_RESETVAL (0x00000000U)
4795 #define CSL_EVETPCC_EESRH_E47_MAX (0x00000001U)
4797 #define CSL_EVETPCC_EESRH_E63_MASK (0x80000000U)
4798 #define CSL_EVETPCC_EESRH_E63_SHIFT (31U)
4799 #define CSL_EVETPCC_EESRH_E63_RESETVAL (0x00000000U)
4800 #define CSL_EVETPCC_EESRH_E63_MAX (0x00000001U)
4802 #define CSL_EVETPCC_EESRH_E46_MASK (0x00004000U)
4803 #define CSL_EVETPCC_EESRH_E46_SHIFT (14U)
4804 #define CSL_EVETPCC_EESRH_E46_RESETVAL (0x00000000U)
4805 #define CSL_EVETPCC_EESRH_E46_MAX (0x00000001U)
4807 #define CSL_EVETPCC_EESRH_E45_MASK (0x00002000U)
4808 #define CSL_EVETPCC_EESRH_E45_SHIFT (13U)
4809 #define CSL_EVETPCC_EESRH_E45_RESETVAL (0x00000000U)
4810 #define CSL_EVETPCC_EESRH_E45_MAX (0x00000001U)
4812 #define CSL_EVETPCC_EESRH_RESETVAL (0x00000000U)
4814 /* SER */
4816 #define CSL_EVETPCC_SER_E0_MASK (0x00000001U)
4817 #define CSL_EVETPCC_SER_E0_SHIFT (0U)
4818 #define CSL_EVETPCC_SER_E0_RESETVAL (0x00000000U)
4819 #define CSL_EVETPCC_SER_E0_MAX (0x00000001U)
4821 #define CSL_EVETPCC_SER_E13_MASK (0x00002000U)
4822 #define CSL_EVETPCC_SER_E13_SHIFT (13U)
4823 #define CSL_EVETPCC_SER_E13_RESETVAL (0x00000000U)
4824 #define CSL_EVETPCC_SER_E13_MAX (0x00000001U)
4826 #define CSL_EVETPCC_SER_E21_MASK (0x00200000U)
4827 #define CSL_EVETPCC_SER_E21_SHIFT (21U)
4828 #define CSL_EVETPCC_SER_E21_RESETVAL (0x00000000U)
4829 #define CSL_EVETPCC_SER_E21_MAX (0x00000001U)
4831 #define CSL_EVETPCC_SER_E14_MASK (0x00004000U)
4832 #define CSL_EVETPCC_SER_E14_SHIFT (14U)
4833 #define CSL_EVETPCC_SER_E14_RESETVAL (0x00000000U)
4834 #define CSL_EVETPCC_SER_E14_MAX (0x00000001U)
4836 #define CSL_EVETPCC_SER_E31_MASK (0x80000000U)
4837 #define CSL_EVETPCC_SER_E31_SHIFT (31U)
4838 #define CSL_EVETPCC_SER_E31_RESETVAL (0x00000000U)
4839 #define CSL_EVETPCC_SER_E31_MAX (0x00000001U)
4841 #define CSL_EVETPCC_SER_E1_MASK (0x00000002U)
4842 #define CSL_EVETPCC_SER_E1_SHIFT (1U)
4843 #define CSL_EVETPCC_SER_E1_RESETVAL (0x00000000U)
4844 #define CSL_EVETPCC_SER_E1_MAX (0x00000001U)
4846 #define CSL_EVETPCC_SER_E11_MASK (0x00000800U)
4847 #define CSL_EVETPCC_SER_E11_SHIFT (11U)
4848 #define CSL_EVETPCC_SER_E11_RESETVAL (0x00000000U)
4849 #define CSL_EVETPCC_SER_E11_MAX (0x00000001U)
4851 #define CSL_EVETPCC_SER_E19_MASK (0x00080000U)
4852 #define CSL_EVETPCC_SER_E19_SHIFT (19U)
4853 #define CSL_EVETPCC_SER_E19_RESETVAL (0x00000000U)
4854 #define CSL_EVETPCC_SER_E19_MAX (0x00000001U)
4856 #define CSL_EVETPCC_SER_E20_MASK (0x00100000U)
4857 #define CSL_EVETPCC_SER_E20_SHIFT (20U)
4858 #define CSL_EVETPCC_SER_E20_RESETVAL (0x00000000U)
4859 #define CSL_EVETPCC_SER_E20_MAX (0x00000001U)
4861 #define CSL_EVETPCC_SER_E12_MASK (0x00001000U)
4862 #define CSL_EVETPCC_SER_E12_SHIFT (12U)
4863 #define CSL_EVETPCC_SER_E12_RESETVAL (0x00000000U)
4864 #define CSL_EVETPCC_SER_E12_MAX (0x00000001U)
4866 #define CSL_EVETPCC_SER_E3_MASK (0x00000008U)
4867 #define CSL_EVETPCC_SER_E3_SHIFT (3U)
4868 #define CSL_EVETPCC_SER_E3_RESETVAL (0x00000000U)
4869 #define CSL_EVETPCC_SER_E3_MAX (0x00000001U)
4871 #define CSL_EVETPCC_SER_E4_MASK (0x00000010U)
4872 #define CSL_EVETPCC_SER_E4_SHIFT (4U)
4873 #define CSL_EVETPCC_SER_E4_RESETVAL (0x00000000U)
4874 #define CSL_EVETPCC_SER_E4_MAX (0x00000001U)
4876 #define CSL_EVETPCC_SER_E24_MASK (0x01000000U)
4877 #define CSL_EVETPCC_SER_E24_SHIFT (24U)
4878 #define CSL_EVETPCC_SER_E24_RESETVAL (0x00000000U)
4879 #define CSL_EVETPCC_SER_E24_MAX (0x00000001U)
4881 #define CSL_EVETPCC_SER_E2_MASK (0x00000004U)
4882 #define CSL_EVETPCC_SER_E2_SHIFT (2U)
4883 #define CSL_EVETPCC_SER_E2_RESETVAL (0x00000000U)
4884 #define CSL_EVETPCC_SER_E2_MAX (0x00000001U)
4886 #define CSL_EVETPCC_SER_E22_MASK (0x00400000U)
4887 #define CSL_EVETPCC_SER_E22_SHIFT (22U)
4888 #define CSL_EVETPCC_SER_E22_RESETVAL (0x00000000U)
4889 #define CSL_EVETPCC_SER_E22_MAX (0x00000001U)
4891 #define CSL_EVETPCC_SER_E23_MASK (0x00800000U)
4892 #define CSL_EVETPCC_SER_E23_SHIFT (23U)
4893 #define CSL_EVETPCC_SER_E23_RESETVAL (0x00000000U)
4894 #define CSL_EVETPCC_SER_E23_MAX (0x00000001U)
4896 #define CSL_EVETPCC_SER_E25_MASK (0x02000000U)
4897 #define CSL_EVETPCC_SER_E25_SHIFT (25U)
4898 #define CSL_EVETPCC_SER_E25_RESETVAL (0x00000000U)
4899 #define CSL_EVETPCC_SER_E25_MAX (0x00000001U)
4901 #define CSL_EVETPCC_SER_E26_MASK (0x04000000U)
4902 #define CSL_EVETPCC_SER_E26_SHIFT (26U)
4903 #define CSL_EVETPCC_SER_E26_RESETVAL (0x00000000U)
4904 #define CSL_EVETPCC_SER_E26_MAX (0x00000001U)
4906 #define CSL_EVETPCC_SER_E6_MASK (0x00000040U)
4907 #define CSL_EVETPCC_SER_E6_SHIFT (6U)
4908 #define CSL_EVETPCC_SER_E6_RESETVAL (0x00000000U)
4909 #define CSL_EVETPCC_SER_E6_MAX (0x00000001U)
4911 #define CSL_EVETPCC_SER_E5_MASK (0x00000020U)
4912 #define CSL_EVETPCC_SER_E5_SHIFT (5U)
4913 #define CSL_EVETPCC_SER_E5_RESETVAL (0x00000000U)
4914 #define CSL_EVETPCC_SER_E5_MAX (0x00000001U)
4916 #define CSL_EVETPCC_SER_E8_MASK (0x00000100U)
4917 #define CSL_EVETPCC_SER_E8_SHIFT (8U)
4918 #define CSL_EVETPCC_SER_E8_RESETVAL (0x00000000U)
4919 #define CSL_EVETPCC_SER_E8_MAX (0x00000001U)
4921 #define CSL_EVETPCC_SER_E17_MASK (0x00020000U)
4922 #define CSL_EVETPCC_SER_E17_SHIFT (17U)
4923 #define CSL_EVETPCC_SER_E17_RESETVAL (0x00000000U)
4924 #define CSL_EVETPCC_SER_E17_MAX (0x00000001U)
4926 #define CSL_EVETPCC_SER_E29_MASK (0x20000000U)
4927 #define CSL_EVETPCC_SER_E29_SHIFT (29U)
4928 #define CSL_EVETPCC_SER_E29_RESETVAL (0x00000000U)
4929 #define CSL_EVETPCC_SER_E29_MAX (0x00000001U)
4931 #define CSL_EVETPCC_SER_E18_MASK (0x00040000U)
4932 #define CSL_EVETPCC_SER_E18_SHIFT (18U)
4933 #define CSL_EVETPCC_SER_E18_RESETVAL (0x00000000U)
4934 #define CSL_EVETPCC_SER_E18_MAX (0x00000001U)
4936 #define CSL_EVETPCC_SER_E30_MASK (0x40000000U)
4937 #define CSL_EVETPCC_SER_E30_SHIFT (30U)
4938 #define CSL_EVETPCC_SER_E30_RESETVAL (0x00000000U)
4939 #define CSL_EVETPCC_SER_E30_MAX (0x00000001U)
4941 #define CSL_EVETPCC_SER_E7_MASK (0x00000080U)
4942 #define CSL_EVETPCC_SER_E7_SHIFT (7U)
4943 #define CSL_EVETPCC_SER_E7_RESETVAL (0x00000000U)
4944 #define CSL_EVETPCC_SER_E7_MAX (0x00000001U)
4946 #define CSL_EVETPCC_SER_E10_MASK (0x00000400U)
4947 #define CSL_EVETPCC_SER_E10_SHIFT (10U)
4948 #define CSL_EVETPCC_SER_E10_RESETVAL (0x00000000U)
4949 #define CSL_EVETPCC_SER_E10_MAX (0x00000001U)
4951 #define CSL_EVETPCC_SER_E15_MASK (0x00008000U)
4952 #define CSL_EVETPCC_SER_E15_SHIFT (15U)
4953 #define CSL_EVETPCC_SER_E15_RESETVAL (0x00000000U)
4954 #define CSL_EVETPCC_SER_E15_MAX (0x00000001U)
4956 #define CSL_EVETPCC_SER_E27_MASK (0x08000000U)
4957 #define CSL_EVETPCC_SER_E27_SHIFT (27U)
4958 #define CSL_EVETPCC_SER_E27_RESETVAL (0x00000000U)
4959 #define CSL_EVETPCC_SER_E27_MAX (0x00000001U)
4961 #define CSL_EVETPCC_SER_E9_MASK (0x00000200U)
4962 #define CSL_EVETPCC_SER_E9_SHIFT (9U)
4963 #define CSL_EVETPCC_SER_E9_RESETVAL (0x00000000U)
4964 #define CSL_EVETPCC_SER_E9_MAX (0x00000001U)
4966 #define CSL_EVETPCC_SER_E16_MASK (0x00010000U)
4967 #define CSL_EVETPCC_SER_E16_SHIFT (16U)
4968 #define CSL_EVETPCC_SER_E16_RESETVAL (0x00000000U)
4969 #define CSL_EVETPCC_SER_E16_MAX (0x00000001U)
4971 #define CSL_EVETPCC_SER_E28_MASK (0x10000000U)
4972 #define CSL_EVETPCC_SER_E28_SHIFT (28U)
4973 #define CSL_EVETPCC_SER_E28_RESETVAL (0x00000000U)
4974 #define CSL_EVETPCC_SER_E28_MAX (0x00000001U)
4976 #define CSL_EVETPCC_SER_RESETVAL (0x00000000U)
4978 /* SERH */
4980 #define CSL_EVETPCC_SERH_E53_MASK (0x00200000U)
4981 #define CSL_EVETPCC_SERH_E53_SHIFT (21U)
4982 #define CSL_EVETPCC_SERH_E53_RESETVAL (0x00000000U)
4983 #define CSL_EVETPCC_SERH_E53_MAX (0x00000001U)
4985 #define CSL_EVETPCC_SERH_E42_MASK (0x00000400U)
4986 #define CSL_EVETPCC_SERH_E42_SHIFT (10U)
4987 #define CSL_EVETPCC_SERH_E42_RESETVAL (0x00000000U)
4988 #define CSL_EVETPCC_SERH_E42_MAX (0x00000001U)
4990 #define CSL_EVETPCC_SERH_E52_MASK (0x00100000U)
4991 #define CSL_EVETPCC_SERH_E52_SHIFT (20U)
4992 #define CSL_EVETPCC_SERH_E52_RESETVAL (0x00000000U)
4993 #define CSL_EVETPCC_SERH_E52_MAX (0x00000001U)
4995 #define CSL_EVETPCC_SERH_E43_MASK (0x00000800U)
4996 #define CSL_EVETPCC_SERH_E43_SHIFT (11U)
4997 #define CSL_EVETPCC_SERH_E43_RESETVAL (0x00000000U)
4998 #define CSL_EVETPCC_SERH_E43_MAX (0x00000001U)
5000 #define CSL_EVETPCC_SERH_E32_MASK (0x00000001U)
5001 #define CSL_EVETPCC_SERH_E32_SHIFT (0U)
5002 #define CSL_EVETPCC_SERH_E32_RESETVAL (0x00000000U)
5003 #define CSL_EVETPCC_SERH_E32_MAX (0x00000001U)
5005 #define CSL_EVETPCC_SERH_E44_MASK (0x00001000U)
5006 #define CSL_EVETPCC_SERH_E44_SHIFT (12U)
5007 #define CSL_EVETPCC_SERH_E44_RESETVAL (0x00000000U)
5008 #define CSL_EVETPCC_SERH_E44_MAX (0x00000001U)
5010 #define CSL_EVETPCC_SERH_E55_MASK (0x00800000U)
5011 #define CSL_EVETPCC_SERH_E55_SHIFT (23U)
5012 #define CSL_EVETPCC_SERH_E55_RESETVAL (0x00000000U)
5013 #define CSL_EVETPCC_SERH_E55_MAX (0x00000001U)
5015 #define CSL_EVETPCC_SERH_E45_MASK (0x00002000U)
5016 #define CSL_EVETPCC_SERH_E45_SHIFT (13U)
5017 #define CSL_EVETPCC_SERH_E45_RESETVAL (0x00000000U)
5018 #define CSL_EVETPCC_SERH_E45_MAX (0x00000001U)
5020 #define CSL_EVETPCC_SERH_E54_MASK (0x00400000U)
5021 #define CSL_EVETPCC_SERH_E54_SHIFT (22U)
5022 #define CSL_EVETPCC_SERH_E54_RESETVAL (0x00000000U)
5023 #define CSL_EVETPCC_SERH_E54_MAX (0x00000001U)
5025 #define CSL_EVETPCC_SERH_E46_MASK (0x00004000U)
5026 #define CSL_EVETPCC_SERH_E46_SHIFT (14U)
5027 #define CSL_EVETPCC_SERH_E46_RESETVAL (0x00000000U)
5028 #define CSL_EVETPCC_SERH_E46_MAX (0x00000001U)
5030 #define CSL_EVETPCC_SERH_E56_MASK (0x01000000U)
5031 #define CSL_EVETPCC_SERH_E56_SHIFT (24U)
5032 #define CSL_EVETPCC_SERH_E56_RESETVAL (0x00000000U)
5033 #define CSL_EVETPCC_SERH_E56_MAX (0x00000001U)
5035 #define CSL_EVETPCC_SERH_E58_MASK (0x04000000U)
5036 #define CSL_EVETPCC_SERH_E58_SHIFT (26U)
5037 #define CSL_EVETPCC_SERH_E58_RESETVAL (0x00000000U)
5038 #define CSL_EVETPCC_SERH_E58_MAX (0x00000001U)
5040 #define CSL_EVETPCC_SERH_E57_MASK (0x02000000U)
5041 #define CSL_EVETPCC_SERH_E57_SHIFT (25U)
5042 #define CSL_EVETPCC_SERH_E57_RESETVAL (0x00000000U)
5043 #define CSL_EVETPCC_SERH_E57_MAX (0x00000001U)
5045 #define CSL_EVETPCC_SERH_E60_MASK (0x10000000U)
5046 #define CSL_EVETPCC_SERH_E60_SHIFT (28U)
5047 #define CSL_EVETPCC_SERH_E60_RESETVAL (0x00000000U)
5048 #define CSL_EVETPCC_SERH_E60_MAX (0x00000001U)
5050 #define CSL_EVETPCC_SERH_E59_MASK (0x08000000U)
5051 #define CSL_EVETPCC_SERH_E59_SHIFT (27U)
5052 #define CSL_EVETPCC_SERH_E59_RESETVAL (0x00000000U)
5053 #define CSL_EVETPCC_SERH_E59_MAX (0x00000001U)
5055 #define CSL_EVETPCC_SERH_E61_MASK (0x20000000U)
5056 #define CSL_EVETPCC_SERH_E61_SHIFT (29U)
5057 #define CSL_EVETPCC_SERH_E61_RESETVAL (0x00000000U)
5058 #define CSL_EVETPCC_SERH_E61_MAX (0x00000001U)
5060 #define CSL_EVETPCC_SERH_E37_MASK (0x00000020U)
5061 #define CSL_EVETPCC_SERH_E37_SHIFT (5U)
5062 #define CSL_EVETPCC_SERH_E37_RESETVAL (0x00000000U)
5063 #define CSL_EVETPCC_SERH_E37_MAX (0x00000001U)
5065 #define CSL_EVETPCC_SERH_E47_MASK (0x00008000U)
5066 #define CSL_EVETPCC_SERH_E47_SHIFT (15U)
5067 #define CSL_EVETPCC_SERH_E47_RESETVAL (0x00000000U)
5068 #define CSL_EVETPCC_SERH_E47_MAX (0x00000001U)
5070 #define CSL_EVETPCC_SERH_E38_MASK (0x00000040U)
5071 #define CSL_EVETPCC_SERH_E38_SHIFT (6U)
5072 #define CSL_EVETPCC_SERH_E38_RESETVAL (0x00000000U)
5073 #define CSL_EVETPCC_SERH_E38_MAX (0x00000001U)
5075 #define CSL_EVETPCC_SERH_E35_MASK (0x00000008U)
5076 #define CSL_EVETPCC_SERH_E35_SHIFT (3U)
5077 #define CSL_EVETPCC_SERH_E35_RESETVAL (0x00000000U)
5078 #define CSL_EVETPCC_SERH_E35_MAX (0x00000001U)
5080 #define CSL_EVETPCC_SERH_E48_MASK (0x00010000U)
5081 #define CSL_EVETPCC_SERH_E48_SHIFT (16U)
5082 #define CSL_EVETPCC_SERH_E48_RESETVAL (0x00000000U)
5083 #define CSL_EVETPCC_SERH_E48_MAX (0x00000001U)
5085 #define CSL_EVETPCC_SERH_E62_MASK (0x40000000U)
5086 #define CSL_EVETPCC_SERH_E62_SHIFT (30U)
5087 #define CSL_EVETPCC_SERH_E62_RESETVAL (0x00000000U)
5088 #define CSL_EVETPCC_SERH_E62_MAX (0x00000001U)
5090 #define CSL_EVETPCC_SERH_E39_MASK (0x00000080U)
5091 #define CSL_EVETPCC_SERH_E39_SHIFT (7U)
5092 #define CSL_EVETPCC_SERH_E39_RESETVAL (0x00000000U)
5093 #define CSL_EVETPCC_SERH_E39_MAX (0x00000001U)
5095 #define CSL_EVETPCC_SERH_E63_MASK (0x80000000U)
5096 #define CSL_EVETPCC_SERH_E63_SHIFT (31U)
5097 #define CSL_EVETPCC_SERH_E63_RESETVAL (0x00000000U)
5098 #define CSL_EVETPCC_SERH_E63_MAX (0x00000001U)
5100 #define CSL_EVETPCC_SERH_E36_MASK (0x00000010U)
5101 #define CSL_EVETPCC_SERH_E36_SHIFT (4U)
5102 #define CSL_EVETPCC_SERH_E36_RESETVAL (0x00000000U)
5103 #define CSL_EVETPCC_SERH_E36_MAX (0x00000001U)
5105 #define CSL_EVETPCC_SERH_E49_MASK (0x00020000U)
5106 #define CSL_EVETPCC_SERH_E49_SHIFT (17U)
5107 #define CSL_EVETPCC_SERH_E49_RESETVAL (0x00000000U)
5108 #define CSL_EVETPCC_SERH_E49_MAX (0x00000001U)
5110 #define CSL_EVETPCC_SERH_E40_MASK (0x00000100U)
5111 #define CSL_EVETPCC_SERH_E40_SHIFT (8U)
5112 #define CSL_EVETPCC_SERH_E40_RESETVAL (0x00000000U)
5113 #define CSL_EVETPCC_SERH_E40_MAX (0x00000001U)
5115 #define CSL_EVETPCC_SERH_E33_MASK (0x00000002U)
5116 #define CSL_EVETPCC_SERH_E33_SHIFT (1U)
5117 #define CSL_EVETPCC_SERH_E33_RESETVAL (0x00000000U)
5118 #define CSL_EVETPCC_SERH_E33_MAX (0x00000001U)
5120 #define CSL_EVETPCC_SERH_E50_MASK (0x00040000U)
5121 #define CSL_EVETPCC_SERH_E50_SHIFT (18U)
5122 #define CSL_EVETPCC_SERH_E50_RESETVAL (0x00000000U)
5123 #define CSL_EVETPCC_SERH_E50_MAX (0x00000001U)
5125 #define CSL_EVETPCC_SERH_E41_MASK (0x00000200U)
5126 #define CSL_EVETPCC_SERH_E41_SHIFT (9U)
5127 #define CSL_EVETPCC_SERH_E41_RESETVAL (0x00000000U)
5128 #define CSL_EVETPCC_SERH_E41_MAX (0x00000001U)
5130 #define CSL_EVETPCC_SERH_E34_MASK (0x00000004U)
5131 #define CSL_EVETPCC_SERH_E34_SHIFT (2U)
5132 #define CSL_EVETPCC_SERH_E34_RESETVAL (0x00000000U)
5133 #define CSL_EVETPCC_SERH_E34_MAX (0x00000001U)
5135 #define CSL_EVETPCC_SERH_E51_MASK (0x00080000U)
5136 #define CSL_EVETPCC_SERH_E51_SHIFT (19U)
5137 #define CSL_EVETPCC_SERH_E51_RESETVAL (0x00000000U)
5138 #define CSL_EVETPCC_SERH_E51_MAX (0x00000001U)
5140 #define CSL_EVETPCC_SERH_RESETVAL (0x00000000U)
5142 /* SECR */
5144 #define CSL_EVETPCC_SECR_E21_MASK (0x00200000U)
5145 #define CSL_EVETPCC_SECR_E21_SHIFT (21U)
5146 #define CSL_EVETPCC_SECR_E21_RESETVAL (0x00000000U)
5147 #define CSL_EVETPCC_SECR_E21_MAX (0x00000001U)
5149 #define CSL_EVETPCC_SECR_E29_MASK (0x20000000U)
5150 #define CSL_EVETPCC_SECR_E29_SHIFT (29U)
5151 #define CSL_EVETPCC_SECR_E29_RESETVAL (0x00000000U)
5152 #define CSL_EVETPCC_SECR_E29_MAX (0x00000001U)
5154 #define CSL_EVETPCC_SECR_E20_MASK (0x00100000U)
5155 #define CSL_EVETPCC_SECR_E20_SHIFT (20U)
5156 #define CSL_EVETPCC_SECR_E20_RESETVAL (0x00000000U)
5157 #define CSL_EVETPCC_SECR_E20_MAX (0x00000001U)
5159 #define CSL_EVETPCC_SECR_E0_MASK (0x00000001U)
5160 #define CSL_EVETPCC_SECR_E0_SHIFT (0U)
5161 #define CSL_EVETPCC_SECR_E0_RESETVAL (0x00000000U)
5162 #define CSL_EVETPCC_SECR_E0_MAX (0x00000001U)
5164 #define CSL_EVETPCC_SECR_E10_MASK (0x00000400U)
5165 #define CSL_EVETPCC_SECR_E10_SHIFT (10U)
5166 #define CSL_EVETPCC_SECR_E10_RESETVAL (0x00000000U)
5167 #define CSL_EVETPCC_SECR_E10_MAX (0x00000001U)
5169 #define CSL_EVETPCC_SECR_E9_MASK (0x00000200U)
5170 #define CSL_EVETPCC_SECR_E9_SHIFT (9U)
5171 #define CSL_EVETPCC_SECR_E9_RESETVAL (0x00000000U)
5172 #define CSL_EVETPCC_SECR_E9_MAX (0x00000001U)
5174 #define CSL_EVETPCC_SECR_E27_MASK (0x08000000U)
5175 #define CSL_EVETPCC_SECR_E27_SHIFT (27U)
5176 #define CSL_EVETPCC_SECR_E27_RESETVAL (0x00000000U)
5177 #define CSL_EVETPCC_SECR_E27_MAX (0x00000001U)
5179 #define CSL_EVETPCC_SECR_E2_MASK (0x00000004U)
5180 #define CSL_EVETPCC_SECR_E2_SHIFT (2U)
5181 #define CSL_EVETPCC_SECR_E2_RESETVAL (0x00000000U)
5182 #define CSL_EVETPCC_SECR_E2_MAX (0x00000001U)
5184 #define CSL_EVETPCC_SECR_E12_MASK (0x00001000U)
5185 #define CSL_EVETPCC_SECR_E12_SHIFT (12U)
5186 #define CSL_EVETPCC_SECR_E12_RESETVAL (0x00000000U)
5187 #define CSL_EVETPCC_SECR_E12_MAX (0x00000001U)
5189 #define CSL_EVETPCC_SECR_E28_MASK (0x10000000U)
5190 #define CSL_EVETPCC_SECR_E28_SHIFT (28U)
5191 #define CSL_EVETPCC_SECR_E28_RESETVAL (0x00000000U)
5192 #define CSL_EVETPCC_SECR_E28_MAX (0x00000001U)
5194 #define CSL_EVETPCC_SECR_E1_MASK (0x00000002U)
5195 #define CSL_EVETPCC_SECR_E1_SHIFT (1U)
5196 #define CSL_EVETPCC_SECR_E1_RESETVAL (0x00000000U)
5197 #define CSL_EVETPCC_SECR_E1_MAX (0x00000001U)
5199 #define CSL_EVETPCC_SECR_E11_MASK (0x00000800U)
5200 #define CSL_EVETPCC_SECR_E11_SHIFT (11U)
5201 #define CSL_EVETPCC_SECR_E11_RESETVAL (0x00000000U)
5202 #define CSL_EVETPCC_SECR_E11_MAX (0x00000001U)
5204 #define CSL_EVETPCC_SECR_E25_MASK (0x02000000U)
5205 #define CSL_EVETPCC_SECR_E25_SHIFT (25U)
5206 #define CSL_EVETPCC_SECR_E25_RESETVAL (0x00000000U)
5207 #define CSL_EVETPCC_SECR_E25_MAX (0x00000001U)
5209 #define CSL_EVETPCC_SECR_E4_MASK (0x00000010U)
5210 #define CSL_EVETPCC_SECR_E4_SHIFT (4U)
5211 #define CSL_EVETPCC_SECR_E4_RESETVAL (0x00000000U)
5212 #define CSL_EVETPCC_SECR_E4_MAX (0x00000001U)
5214 #define CSL_EVETPCC_SECR_E14_MASK (0x00004000U)
5215 #define CSL_EVETPCC_SECR_E14_SHIFT (14U)
5216 #define CSL_EVETPCC_SECR_E14_RESETVAL (0x00000000U)
5217 #define CSL_EVETPCC_SECR_E14_MAX (0x00000001U)
5219 #define CSL_EVETPCC_SECR_E26_MASK (0x04000000U)
5220 #define CSL_EVETPCC_SECR_E26_SHIFT (26U)
5221 #define CSL_EVETPCC_SECR_E26_RESETVAL (0x00000000U)
5222 #define CSL_EVETPCC_SECR_E26_MAX (0x00000001U)
5224 #define CSL_EVETPCC_SECR_E3_MASK (0x00000008U)
5225 #define CSL_EVETPCC_SECR_E3_SHIFT (3U)
5226 #define CSL_EVETPCC_SECR_E3_RESETVAL (0x00000000U)
5227 #define CSL_EVETPCC_SECR_E3_MAX (0x00000001U)
5229 #define CSL_EVETPCC_SECR_E13_MASK (0x00002000U)
5230 #define CSL_EVETPCC_SECR_E13_SHIFT (13U)
5231 #define CSL_EVETPCC_SECR_E13_RESETVAL (0x00000000U)
5232 #define CSL_EVETPCC_SECR_E13_MAX (0x00000001U)
5234 #define CSL_EVETPCC_SECR_E6_MASK (0x00000040U)
5235 #define CSL_EVETPCC_SECR_E6_SHIFT (6U)
5236 #define CSL_EVETPCC_SECR_E6_RESETVAL (0x00000000U)
5237 #define CSL_EVETPCC_SECR_E6_MAX (0x00000001U)
5239 #define CSL_EVETPCC_SECR_E16_MASK (0x00010000U)
5240 #define CSL_EVETPCC_SECR_E16_SHIFT (16U)
5241 #define CSL_EVETPCC_SECR_E16_RESETVAL (0x00000000U)
5242 #define CSL_EVETPCC_SECR_E16_MAX (0x00000001U)
5244 #define CSL_EVETPCC_SECR_E24_MASK (0x01000000U)
5245 #define CSL_EVETPCC_SECR_E24_SHIFT (24U)
5246 #define CSL_EVETPCC_SECR_E24_RESETVAL (0x00000000U)
5247 #define CSL_EVETPCC_SECR_E24_MAX (0x00000001U)
5249 #define CSL_EVETPCC_SECR_E5_MASK (0x00000020U)
5250 #define CSL_EVETPCC_SECR_E5_SHIFT (5U)
5251 #define CSL_EVETPCC_SECR_E5_RESETVAL (0x00000000U)
5252 #define CSL_EVETPCC_SECR_E5_MAX (0x00000001U)
5254 #define CSL_EVETPCC_SECR_E15_MASK (0x00008000U)
5255 #define CSL_EVETPCC_SECR_E15_SHIFT (15U)
5256 #define CSL_EVETPCC_SECR_E15_RESETVAL (0x00000000U)
5257 #define CSL_EVETPCC_SECR_E15_MAX (0x00000001U)
5259 #define CSL_EVETPCC_SECR_E18_MASK (0x00040000U)
5260 #define CSL_EVETPCC_SECR_E18_SHIFT (18U)
5261 #define CSL_EVETPCC_SECR_E18_RESETVAL (0x00000000U)
5262 #define CSL_EVETPCC_SECR_E18_MAX (0x00000001U)
5264 #define CSL_EVETPCC_SECR_E31_MASK (0x80000000U)
5265 #define CSL_EVETPCC_SECR_E31_SHIFT (31U)
5266 #define CSL_EVETPCC_SECR_E31_RESETVAL (0x00000000U)
5267 #define CSL_EVETPCC_SECR_E31_MAX (0x00000001U)
5269 #define CSL_EVETPCC_SECR_E8_MASK (0x00000100U)
5270 #define CSL_EVETPCC_SECR_E8_SHIFT (8U)
5271 #define CSL_EVETPCC_SECR_E8_RESETVAL (0x00000000U)
5272 #define CSL_EVETPCC_SECR_E8_MAX (0x00000001U)
5274 #define CSL_EVETPCC_SECR_E22_MASK (0x00400000U)
5275 #define CSL_EVETPCC_SECR_E22_SHIFT (22U)
5276 #define CSL_EVETPCC_SECR_E22_RESETVAL (0x00000000U)
5277 #define CSL_EVETPCC_SECR_E22_MAX (0x00000001U)
5279 #define CSL_EVETPCC_SECR_E7_MASK (0x00000080U)
5280 #define CSL_EVETPCC_SECR_E7_SHIFT (7U)
5281 #define CSL_EVETPCC_SECR_E7_RESETVAL (0x00000000U)
5282 #define CSL_EVETPCC_SECR_E7_MAX (0x00000001U)
5284 #define CSL_EVETPCC_SECR_E19_MASK (0x00080000U)
5285 #define CSL_EVETPCC_SECR_E19_SHIFT (19U)
5286 #define CSL_EVETPCC_SECR_E19_RESETVAL (0x00000000U)
5287 #define CSL_EVETPCC_SECR_E19_MAX (0x00000001U)
5289 #define CSL_EVETPCC_SECR_E17_MASK (0x00020000U)
5290 #define CSL_EVETPCC_SECR_E17_SHIFT (17U)
5291 #define CSL_EVETPCC_SECR_E17_RESETVAL (0x00000000U)
5292 #define CSL_EVETPCC_SECR_E17_MAX (0x00000001U)
5294 #define CSL_EVETPCC_SECR_E23_MASK (0x00800000U)
5295 #define CSL_EVETPCC_SECR_E23_SHIFT (23U)
5296 #define CSL_EVETPCC_SECR_E23_RESETVAL (0x00000000U)
5297 #define CSL_EVETPCC_SECR_E23_MAX (0x00000001U)
5299 #define CSL_EVETPCC_SECR_E30_MASK (0x40000000U)
5300 #define CSL_EVETPCC_SECR_E30_SHIFT (30U)
5301 #define CSL_EVETPCC_SECR_E30_RESETVAL (0x00000000U)
5302 #define CSL_EVETPCC_SECR_E30_MAX (0x00000001U)
5304 #define CSL_EVETPCC_SECR_RESETVAL (0x00000000U)
5306 /* SECRH */
5308 #define CSL_EVETPCC_SECRH_E34_MASK (0x00000004U)
5309 #define CSL_EVETPCC_SECRH_E34_SHIFT (2U)
5310 #define CSL_EVETPCC_SECRH_E34_RESETVAL (0x00000000U)
5311 #define CSL_EVETPCC_SECRH_E34_MAX (0x00000001U)
5313 #define CSL_EVETPCC_SECRH_E44_MASK (0x00001000U)
5314 #define CSL_EVETPCC_SECRH_E44_SHIFT (12U)
5315 #define CSL_EVETPCC_SECRH_E44_RESETVAL (0x00000000U)
5316 #define CSL_EVETPCC_SECRH_E44_MAX (0x00000001U)
5318 #define CSL_EVETPCC_SECRH_E54_MASK (0x00400000U)
5319 #define CSL_EVETPCC_SECRH_E54_SHIFT (22U)
5320 #define CSL_EVETPCC_SECRH_E54_RESETVAL (0x00000000U)
5321 #define CSL_EVETPCC_SECRH_E54_MAX (0x00000001U)
5323 #define CSL_EVETPCC_SECRH_E33_MASK (0x00000002U)
5324 #define CSL_EVETPCC_SECRH_E33_SHIFT (1U)
5325 #define CSL_EVETPCC_SECRH_E33_RESETVAL (0x00000000U)
5326 #define CSL_EVETPCC_SECRH_E33_MAX (0x00000001U)
5328 #define CSL_EVETPCC_SECRH_E43_MASK (0x00000800U)
5329 #define CSL_EVETPCC_SECRH_E43_SHIFT (11U)
5330 #define CSL_EVETPCC_SECRH_E43_RESETVAL (0x00000000U)
5331 #define CSL_EVETPCC_SECRH_E43_MAX (0x00000001U)
5333 #define CSL_EVETPCC_SECRH_E53_MASK (0x00200000U)
5334 #define CSL_EVETPCC_SECRH_E53_SHIFT (21U)
5335 #define CSL_EVETPCC_SECRH_E53_RESETVAL (0x00000000U)
5336 #define CSL_EVETPCC_SECRH_E53_MAX (0x00000001U)
5338 #define CSL_EVETPCC_SECRH_E58_MASK (0x04000000U)
5339 #define CSL_EVETPCC_SECRH_E58_SHIFT (26U)
5340 #define CSL_EVETPCC_SECRH_E58_RESETVAL (0x00000000U)
5341 #define CSL_EVETPCC_SECRH_E58_MAX (0x00000001U)
5343 #define CSL_EVETPCC_SECRH_E32_MASK (0x00000001U)
5344 #define CSL_EVETPCC_SECRH_E32_SHIFT (0U)
5345 #define CSL_EVETPCC_SECRH_E32_RESETVAL (0x00000000U)
5346 #define CSL_EVETPCC_SECRH_E32_MAX (0x00000001U)
5348 #define CSL_EVETPCC_SECRH_E63_MASK (0x80000000U)
5349 #define CSL_EVETPCC_SECRH_E63_SHIFT (31U)
5350 #define CSL_EVETPCC_SECRH_E63_RESETVAL (0x00000000U)
5351 #define CSL_EVETPCC_SECRH_E63_MAX (0x00000001U)
5353 #define CSL_EVETPCC_SECRH_E57_MASK (0x02000000U)
5354 #define CSL_EVETPCC_SECRH_E57_SHIFT (25U)
5355 #define CSL_EVETPCC_SECRH_E57_RESETVAL (0x00000000U)
5356 #define CSL_EVETPCC_SECRH_E57_MAX (0x00000001U)
5358 #define CSL_EVETPCC_SECRH_E56_MASK (0x01000000U)
5359 #define CSL_EVETPCC_SECRH_E56_SHIFT (24U)
5360 #define CSL_EVETPCC_SECRH_E56_RESETVAL (0x00000000U)
5361 #define CSL_EVETPCC_SECRH_E56_MAX (0x00000001U)
5363 #define CSL_EVETPCC_SECRH_E55_MASK (0x00800000U)
5364 #define CSL_EVETPCC_SECRH_E55_SHIFT (23U)
5365 #define CSL_EVETPCC_SECRH_E55_RESETVAL (0x00000000U)
5366 #define CSL_EVETPCC_SECRH_E55_MAX (0x00000001U)
5368 #define CSL_EVETPCC_SECRH_E52_MASK (0x00100000U)
5369 #define CSL_EVETPCC_SECRH_E52_SHIFT (20U)
5370 #define CSL_EVETPCC_SECRH_E52_RESETVAL (0x00000000U)
5371 #define CSL_EVETPCC_SECRH_E52_MAX (0x00000001U)
5373 #define CSL_EVETPCC_SECRH_E42_MASK (0x00000400U)
5374 #define CSL_EVETPCC_SECRH_E42_SHIFT (10U)
5375 #define CSL_EVETPCC_SECRH_E42_RESETVAL (0x00000000U)
5376 #define CSL_EVETPCC_SECRH_E42_MAX (0x00000001U)
5378 #define CSL_EVETPCC_SECRH_E51_MASK (0x00080000U)
5379 #define CSL_EVETPCC_SECRH_E51_SHIFT (19U)
5380 #define CSL_EVETPCC_SECRH_E51_RESETVAL (0x00000000U)
5381 #define CSL_EVETPCC_SECRH_E51_MAX (0x00000001U)
5383 #define CSL_EVETPCC_SECRH_E41_MASK (0x00000200U)
5384 #define CSL_EVETPCC_SECRH_E41_SHIFT (9U)
5385 #define CSL_EVETPCC_SECRH_E41_RESETVAL (0x00000000U)
5386 #define CSL_EVETPCC_SECRH_E41_MAX (0x00000001U)
5388 #define CSL_EVETPCC_SECRH_E50_MASK (0x00040000U)
5389 #define CSL_EVETPCC_SECRH_E50_SHIFT (18U)
5390 #define CSL_EVETPCC_SECRH_E50_RESETVAL (0x00000000U)
5391 #define CSL_EVETPCC_SECRH_E50_MAX (0x00000001U)
5393 #define CSL_EVETPCC_SECRH_E40_MASK (0x00000100U)
5394 #define CSL_EVETPCC_SECRH_E40_SHIFT (8U)
5395 #define CSL_EVETPCC_SECRH_E40_RESETVAL (0x00000000U)
5396 #define CSL_EVETPCC_SECRH_E40_MAX (0x00000001U)
5398 #define CSL_EVETPCC_SECRH_E49_MASK (0x00020000U)
5399 #define CSL_EVETPCC_SECRH_E49_SHIFT (17U)
5400 #define CSL_EVETPCC_SECRH_E49_RESETVAL (0x00000000U)
5401 #define CSL_EVETPCC_SECRH_E49_MAX (0x00000001U)
5403 #define CSL_EVETPCC_SECRH_E39_MASK (0x00000080U)
5404 #define CSL_EVETPCC_SECRH_E39_SHIFT (7U)
5405 #define CSL_EVETPCC_SECRH_E39_RESETVAL (0x00000000U)
5406 #define CSL_EVETPCC_SECRH_E39_MAX (0x00000001U)
5408 #define CSL_EVETPCC_SECRH_E48_MASK (0x00010000U)
5409 #define CSL_EVETPCC_SECRH_E48_SHIFT (16U)
5410 #define CSL_EVETPCC_SECRH_E48_RESETVAL (0x00000000U)
5411 #define CSL_EVETPCC_SECRH_E48_MAX (0x00000001U)
5413 #define CSL_EVETPCC_SECRH_E38_MASK (0x00000040U)
5414 #define CSL_EVETPCC_SECRH_E38_SHIFT (6U)
5415 #define CSL_EVETPCC_SECRH_E38_RESETVAL (0x00000000U)
5416 #define CSL_EVETPCC_SECRH_E38_MAX (0x00000001U)
5418 #define CSL_EVETPCC_SECRH_E59_MASK (0x08000000U)
5419 #define CSL_EVETPCC_SECRH_E59_SHIFT (27U)
5420 #define CSL_EVETPCC_SECRH_E59_RESETVAL (0x00000000U)
5421 #define CSL_EVETPCC_SECRH_E59_MAX (0x00000001U)
5423 #define CSL_EVETPCC_SECRH_E47_MASK (0x00008000U)
5424 #define CSL_EVETPCC_SECRH_E47_SHIFT (15U)
5425 #define CSL_EVETPCC_SECRH_E47_RESETVAL (0x00000000U)
5426 #define CSL_EVETPCC_SECRH_E47_MAX (0x00000001U)
5428 #define CSL_EVETPCC_SECRH_E37_MASK (0x00000020U)
5429 #define CSL_EVETPCC_SECRH_E37_SHIFT (5U)
5430 #define CSL_EVETPCC_SECRH_E37_RESETVAL (0x00000000U)
5431 #define CSL_EVETPCC_SECRH_E37_MAX (0x00000001U)
5433 #define CSL_EVETPCC_SECRH_E60_MASK (0x10000000U)
5434 #define CSL_EVETPCC_SECRH_E60_SHIFT (28U)
5435 #define CSL_EVETPCC_SECRH_E60_RESETVAL (0x00000000U)
5436 #define CSL_EVETPCC_SECRH_E60_MAX (0x00000001U)
5438 #define CSL_EVETPCC_SECRH_E36_MASK (0x00000010U)
5439 #define CSL_EVETPCC_SECRH_E36_SHIFT (4U)
5440 #define CSL_EVETPCC_SECRH_E36_RESETVAL (0x00000000U)
5441 #define CSL_EVETPCC_SECRH_E36_MAX (0x00000001U)
5443 #define CSL_EVETPCC_SECRH_E46_MASK (0x00004000U)
5444 #define CSL_EVETPCC_SECRH_E46_SHIFT (14U)
5445 #define CSL_EVETPCC_SECRH_E46_RESETVAL (0x00000000U)
5446 #define CSL_EVETPCC_SECRH_E46_MAX (0x00000001U)
5448 #define CSL_EVETPCC_SECRH_E61_MASK (0x20000000U)
5449 #define CSL_EVETPCC_SECRH_E61_SHIFT (29U)
5450 #define CSL_EVETPCC_SECRH_E61_RESETVAL (0x00000000U)
5451 #define CSL_EVETPCC_SECRH_E61_MAX (0x00000001U)
5453 #define CSL_EVETPCC_SECRH_E35_MASK (0x00000008U)
5454 #define CSL_EVETPCC_SECRH_E35_SHIFT (3U)
5455 #define CSL_EVETPCC_SECRH_E35_RESETVAL (0x00000000U)
5456 #define CSL_EVETPCC_SECRH_E35_MAX (0x00000001U)
5458 #define CSL_EVETPCC_SECRH_E62_MASK (0x40000000U)
5459 #define CSL_EVETPCC_SECRH_E62_SHIFT (30U)
5460 #define CSL_EVETPCC_SECRH_E62_RESETVAL (0x00000000U)
5461 #define CSL_EVETPCC_SECRH_E62_MAX (0x00000001U)
5463 #define CSL_EVETPCC_SECRH_E45_MASK (0x00002000U)
5464 #define CSL_EVETPCC_SECRH_E45_SHIFT (13U)
5465 #define CSL_EVETPCC_SECRH_E45_RESETVAL (0x00000000U)
5466 #define CSL_EVETPCC_SECRH_E45_MAX (0x00000001U)
5468 #define CSL_EVETPCC_SECRH_RESETVAL (0x00000000U)
5470 /* IER */
5472 #define CSL_EVETPCC_IER_I15_MASK (0x00008000U)
5473 #define CSL_EVETPCC_IER_I15_SHIFT (15U)
5474 #define CSL_EVETPCC_IER_I15_RESETVAL (0x00000000U)
5475 #define CSL_EVETPCC_IER_I15_MAX (0x00000001U)
5477 #define CSL_EVETPCC_IER_I30_MASK (0x40000000U)
5478 #define CSL_EVETPCC_IER_I30_SHIFT (30U)
5479 #define CSL_EVETPCC_IER_I30_RESETVAL (0x00000000U)
5480 #define CSL_EVETPCC_IER_I30_MAX (0x00000001U)
5482 #define CSL_EVETPCC_IER_I14_MASK (0x00004000U)
5483 #define CSL_EVETPCC_IER_I14_SHIFT (14U)
5484 #define CSL_EVETPCC_IER_I14_RESETVAL (0x00000000U)
5485 #define CSL_EVETPCC_IER_I14_MAX (0x00000001U)
5487 #define CSL_EVETPCC_IER_I29_MASK (0x20000000U)
5488 #define CSL_EVETPCC_IER_I29_SHIFT (29U)
5489 #define CSL_EVETPCC_IER_I29_RESETVAL (0x00000000U)
5490 #define CSL_EVETPCC_IER_I29_MAX (0x00000001U)
5492 #define CSL_EVETPCC_IER_I7_MASK (0x00000080U)
5493 #define CSL_EVETPCC_IER_I7_SHIFT (7U)
5494 #define CSL_EVETPCC_IER_I7_RESETVAL (0x00000000U)
5495 #define CSL_EVETPCC_IER_I7_MAX (0x00000001U)
5497 #define CSL_EVETPCC_IER_I28_MASK (0x10000000U)
5498 #define CSL_EVETPCC_IER_I28_SHIFT (28U)
5499 #define CSL_EVETPCC_IER_I28_RESETVAL (0x00000000U)
5500 #define CSL_EVETPCC_IER_I28_MAX (0x00000001U)
5502 #define CSL_EVETPCC_IER_I17_MASK (0x00020000U)
5503 #define CSL_EVETPCC_IER_I17_SHIFT (17U)
5504 #define CSL_EVETPCC_IER_I17_RESETVAL (0x00000000U)
5505 #define CSL_EVETPCC_IER_I17_MAX (0x00000001U)
5507 #define CSL_EVETPCC_IER_I16_MASK (0x00010000U)
5508 #define CSL_EVETPCC_IER_I16_SHIFT (16U)
5509 #define CSL_EVETPCC_IER_I16_RESETVAL (0x00000000U)
5510 #define CSL_EVETPCC_IER_I16_MAX (0x00000001U)
5512 #define CSL_EVETPCC_IER_I27_MASK (0x08000000U)
5513 #define CSL_EVETPCC_IER_I27_SHIFT (27U)
5514 #define CSL_EVETPCC_IER_I27_RESETVAL (0x00000000U)
5515 #define CSL_EVETPCC_IER_I27_MAX (0x00000001U)
5517 #define CSL_EVETPCC_IER_I0_MASK (0x00000001U)
5518 #define CSL_EVETPCC_IER_I0_SHIFT (0U)
5519 #define CSL_EVETPCC_IER_I0_RESETVAL (0x00000000U)
5520 #define CSL_EVETPCC_IER_I0_MAX (0x00000001U)
5522 #define CSL_EVETPCC_IER_I1_MASK (0x00000002U)
5523 #define CSL_EVETPCC_IER_I1_SHIFT (1U)
5524 #define CSL_EVETPCC_IER_I1_RESETVAL (0x00000000U)
5525 #define CSL_EVETPCC_IER_I1_MAX (0x00000001U)
5527 #define CSL_EVETPCC_IER_I13_MASK (0x00002000U)
5528 #define CSL_EVETPCC_IER_I13_SHIFT (13U)
5529 #define CSL_EVETPCC_IER_I13_RESETVAL (0x00000000U)
5530 #define CSL_EVETPCC_IER_I13_MAX (0x00000001U)
5532 #define CSL_EVETPCC_IER_I2_MASK (0x00000004U)
5533 #define CSL_EVETPCC_IER_I2_SHIFT (2U)
5534 #define CSL_EVETPCC_IER_I2_RESETVAL (0x00000000U)
5535 #define CSL_EVETPCC_IER_I2_MAX (0x00000001U)
5537 #define CSL_EVETPCC_IER_I31_MASK (0x80000000U)
5538 #define CSL_EVETPCC_IER_I31_SHIFT (31U)
5539 #define CSL_EVETPCC_IER_I31_RESETVAL (0x00000000U)
5540 #define CSL_EVETPCC_IER_I31_MAX (0x00000001U)
5542 #define CSL_EVETPCC_IER_I22_MASK (0x00400000U)
5543 #define CSL_EVETPCC_IER_I22_SHIFT (22U)
5544 #define CSL_EVETPCC_IER_I22_RESETVAL (0x00000000U)
5545 #define CSL_EVETPCC_IER_I22_MAX (0x00000001U)
5547 #define CSL_EVETPCC_IER_I3_MASK (0x00000008U)
5548 #define CSL_EVETPCC_IER_I3_SHIFT (3U)
5549 #define CSL_EVETPCC_IER_I3_RESETVAL (0x00000000U)
5550 #define CSL_EVETPCC_IER_I3_MAX (0x00000001U)
5552 #define CSL_EVETPCC_IER_I26_MASK (0x04000000U)
5553 #define CSL_EVETPCC_IER_I26_SHIFT (26U)
5554 #define CSL_EVETPCC_IER_I26_RESETVAL (0x00000000U)
5555 #define CSL_EVETPCC_IER_I26_MAX (0x00000001U)
5557 #define CSL_EVETPCC_IER_I5_MASK (0x00000020U)
5558 #define CSL_EVETPCC_IER_I5_SHIFT (5U)
5559 #define CSL_EVETPCC_IER_I5_RESETVAL (0x00000000U)
5560 #define CSL_EVETPCC_IER_I5_MAX (0x00000001U)
5562 #define CSL_EVETPCC_IER_I19_MASK (0x00080000U)
5563 #define CSL_EVETPCC_IER_I19_SHIFT (19U)
5564 #define CSL_EVETPCC_IER_I19_RESETVAL (0x00000000U)
5565 #define CSL_EVETPCC_IER_I19_MAX (0x00000001U)
5567 #define CSL_EVETPCC_IER_I8_MASK (0x00000100U)
5568 #define CSL_EVETPCC_IER_I8_SHIFT (8U)
5569 #define CSL_EVETPCC_IER_I8_RESETVAL (0x00000000U)
5570 #define CSL_EVETPCC_IER_I8_MAX (0x00000001U)
5572 #define CSL_EVETPCC_IER_I25_MASK (0x02000000U)
5573 #define CSL_EVETPCC_IER_I25_SHIFT (25U)
5574 #define CSL_EVETPCC_IER_I25_RESETVAL (0x00000000U)
5575 #define CSL_EVETPCC_IER_I25_MAX (0x00000001U)
5577 #define CSL_EVETPCC_IER_I4_MASK (0x00000010U)
5578 #define CSL_EVETPCC_IER_I4_SHIFT (4U)
5579 #define CSL_EVETPCC_IER_I4_RESETVAL (0x00000000U)
5580 #define CSL_EVETPCC_IER_I4_MAX (0x00000001U)
5582 #define CSL_EVETPCC_IER_I18_MASK (0x00040000U)
5583 #define CSL_EVETPCC_IER_I18_SHIFT (18U)
5584 #define CSL_EVETPCC_IER_I18_RESETVAL (0x00000000U)
5585 #define CSL_EVETPCC_IER_I18_MAX (0x00000001U)
5587 #define CSL_EVETPCC_IER_I9_MASK (0x00000200U)
5588 #define CSL_EVETPCC_IER_I9_SHIFT (9U)
5589 #define CSL_EVETPCC_IER_I9_RESETVAL (0x00000000U)
5590 #define CSL_EVETPCC_IER_I9_MAX (0x00000001U)
5592 #define CSL_EVETPCC_IER_I21_MASK (0x00200000U)
5593 #define CSL_EVETPCC_IER_I21_SHIFT (21U)
5594 #define CSL_EVETPCC_IER_I21_RESETVAL (0x00000000U)
5595 #define CSL_EVETPCC_IER_I21_MAX (0x00000001U)
5597 #define CSL_EVETPCC_IER_I24_MASK (0x01000000U)
5598 #define CSL_EVETPCC_IER_I24_SHIFT (24U)
5599 #define CSL_EVETPCC_IER_I24_RESETVAL (0x00000000U)
5600 #define CSL_EVETPCC_IER_I24_MAX (0x00000001U)
5602 #define CSL_EVETPCC_IER_I10_MASK (0x00000400U)
5603 #define CSL_EVETPCC_IER_I10_SHIFT (10U)
5604 #define CSL_EVETPCC_IER_I10_RESETVAL (0x00000000U)
5605 #define CSL_EVETPCC_IER_I10_MAX (0x00000001U)
5607 #define CSL_EVETPCC_IER_I12_MASK (0x00001000U)
5608 #define CSL_EVETPCC_IER_I12_SHIFT (12U)
5609 #define CSL_EVETPCC_IER_I12_RESETVAL (0x00000000U)
5610 #define CSL_EVETPCC_IER_I12_MAX (0x00000001U)
5612 #define CSL_EVETPCC_IER_I23_MASK (0x00800000U)
5613 #define CSL_EVETPCC_IER_I23_SHIFT (23U)
5614 #define CSL_EVETPCC_IER_I23_RESETVAL (0x00000000U)
5615 #define CSL_EVETPCC_IER_I23_MAX (0x00000001U)
5617 #define CSL_EVETPCC_IER_I20_MASK (0x00100000U)
5618 #define CSL_EVETPCC_IER_I20_SHIFT (20U)
5619 #define CSL_EVETPCC_IER_I20_RESETVAL (0x00000000U)
5620 #define CSL_EVETPCC_IER_I20_MAX (0x00000001U)
5622 #define CSL_EVETPCC_IER_I6_MASK (0x00000040U)
5623 #define CSL_EVETPCC_IER_I6_SHIFT (6U)
5624 #define CSL_EVETPCC_IER_I6_RESETVAL (0x00000000U)
5625 #define CSL_EVETPCC_IER_I6_MAX (0x00000001U)
5627 #define CSL_EVETPCC_IER_I11_MASK (0x00000800U)
5628 #define CSL_EVETPCC_IER_I11_SHIFT (11U)
5629 #define CSL_EVETPCC_IER_I11_RESETVAL (0x00000000U)
5630 #define CSL_EVETPCC_IER_I11_MAX (0x00000001U)
5632 #define CSL_EVETPCC_IER_RESETVAL (0x00000000U)
5634 /* IERH */
5636 #define CSL_EVETPCC_IERH_I48_MASK (0x00010000U)
5637 #define CSL_EVETPCC_IERH_I48_SHIFT (16U)
5638 #define CSL_EVETPCC_IERH_I48_RESETVAL (0x00000000U)
5639 #define CSL_EVETPCC_IERH_I48_MAX (0x00000001U)
5641 #define CSL_EVETPCC_IERH_I35_MASK (0x00000008U)
5642 #define CSL_EVETPCC_IERH_I35_SHIFT (3U)
5643 #define CSL_EVETPCC_IERH_I35_RESETVAL (0x00000000U)
5644 #define CSL_EVETPCC_IERH_I35_MAX (0x00000001U)
5646 #define CSL_EVETPCC_IERH_I34_MASK (0x00000004U)
5647 #define CSL_EVETPCC_IERH_I34_SHIFT (2U)
5648 #define CSL_EVETPCC_IERH_I34_RESETVAL (0x00000000U)
5649 #define CSL_EVETPCC_IERH_I34_MAX (0x00000001U)
5651 #define CSL_EVETPCC_IERH_I46_MASK (0x00004000U)
5652 #define CSL_EVETPCC_IERH_I46_SHIFT (14U)
5653 #define CSL_EVETPCC_IERH_I46_RESETVAL (0x00000000U)
5654 #define CSL_EVETPCC_IERH_I46_MAX (0x00000001U)
5656 #define CSL_EVETPCC_IERH_I59_MASK (0x08000000U)
5657 #define CSL_EVETPCC_IERH_I59_SHIFT (27U)
5658 #define CSL_EVETPCC_IERH_I59_RESETVAL (0x00000000U)
5659 #define CSL_EVETPCC_IERH_I59_MAX (0x00000001U)
5661 #define CSL_EVETPCC_IERH_I33_MASK (0x00000002U)
5662 #define CSL_EVETPCC_IERH_I33_SHIFT (1U)
5663 #define CSL_EVETPCC_IERH_I33_RESETVAL (0x00000000U)
5664 #define CSL_EVETPCC_IERH_I33_MAX (0x00000001U)
5666 #define CSL_EVETPCC_IERH_I45_MASK (0x00002000U)
5667 #define CSL_EVETPCC_IERH_I45_SHIFT (13U)
5668 #define CSL_EVETPCC_IERH_I45_RESETVAL (0x00000000U)
5669 #define CSL_EVETPCC_IERH_I45_MAX (0x00000001U)
5671 #define CSL_EVETPCC_IERH_I60_MASK (0x10000000U)
5672 #define CSL_EVETPCC_IERH_I60_SHIFT (28U)
5673 #define CSL_EVETPCC_IERH_I60_RESETVAL (0x00000000U)
5674 #define CSL_EVETPCC_IERH_I60_MAX (0x00000001U)
5676 #define CSL_EVETPCC_IERH_I32_MASK (0x00000001U)
5677 #define CSL_EVETPCC_IERH_I32_SHIFT (0U)
5678 #define CSL_EVETPCC_IERH_I32_RESETVAL (0x00000000U)
5679 #define CSL_EVETPCC_IERH_I32_MAX (0x00000001U)
5681 #define CSL_EVETPCC_IERH_I44_MASK (0x00001000U)
5682 #define CSL_EVETPCC_IERH_I44_SHIFT (12U)
5683 #define CSL_EVETPCC_IERH_I44_RESETVAL (0x00000000U)
5684 #define CSL_EVETPCC_IERH_I44_MAX (0x00000001U)
5686 #define CSL_EVETPCC_IERH_I61_MASK (0x20000000U)
5687 #define CSL_EVETPCC_IERH_I61_SHIFT (29U)
5688 #define CSL_EVETPCC_IERH_I61_RESETVAL (0x00000000U)
5689 #define CSL_EVETPCC_IERH_I61_MAX (0x00000001U)
5691 #define CSL_EVETPCC_IERH_I43_MASK (0x00000800U)
5692 #define CSL_EVETPCC_IERH_I43_SHIFT (11U)
5693 #define CSL_EVETPCC_IERH_I43_RESETVAL (0x00000000U)
5694 #define CSL_EVETPCC_IERH_I43_MAX (0x00000001U)
5696 #define CSL_EVETPCC_IERH_I49_MASK (0x00020000U)
5697 #define CSL_EVETPCC_IERH_I49_SHIFT (17U)
5698 #define CSL_EVETPCC_IERH_I49_RESETVAL (0x00000000U)
5699 #define CSL_EVETPCC_IERH_I49_MAX (0x00000001U)
5701 #define CSL_EVETPCC_IERH_I62_MASK (0x40000000U)
5702 #define CSL_EVETPCC_IERH_I62_SHIFT (30U)
5703 #define CSL_EVETPCC_IERH_I62_RESETVAL (0x00000000U)
5704 #define CSL_EVETPCC_IERH_I62_MAX (0x00000001U)
5706 #define CSL_EVETPCC_IERH_I50_MASK (0x00040000U)
5707 #define CSL_EVETPCC_IERH_I50_SHIFT (18U)
5708 #define CSL_EVETPCC_IERH_I50_RESETVAL (0x00000000U)
5709 #define CSL_EVETPCC_IERH_I50_MAX (0x00000001U)
5711 #define CSL_EVETPCC_IERH_I42_MASK (0x00000400U)
5712 #define CSL_EVETPCC_IERH_I42_SHIFT (10U)
5713 #define CSL_EVETPCC_IERH_I42_RESETVAL (0x00000000U)
5714 #define CSL_EVETPCC_IERH_I42_MAX (0x00000001U)
5716 #define CSL_EVETPCC_IERH_I63_MASK (0x80000000U)
5717 #define CSL_EVETPCC_IERH_I63_SHIFT (31U)
5718 #define CSL_EVETPCC_IERH_I63_RESETVAL (0x00000000U)
5719 #define CSL_EVETPCC_IERH_I63_MAX (0x00000001U)
5721 #define CSL_EVETPCC_IERH_I51_MASK (0x00080000U)
5722 #define CSL_EVETPCC_IERH_I51_SHIFT (19U)
5723 #define CSL_EVETPCC_IERH_I51_RESETVAL (0x00000000U)
5724 #define CSL_EVETPCC_IERH_I51_MAX (0x00000001U)
5726 #define CSL_EVETPCC_IERH_I41_MASK (0x00000200U)
5727 #define CSL_EVETPCC_IERH_I41_SHIFT (9U)
5728 #define CSL_EVETPCC_IERH_I41_RESETVAL (0x00000000U)
5729 #define CSL_EVETPCC_IERH_I41_MAX (0x00000001U)
5731 #define CSL_EVETPCC_IERH_I52_MASK (0x00100000U)
5732 #define CSL_EVETPCC_IERH_I52_SHIFT (20U)
5733 #define CSL_EVETPCC_IERH_I52_RESETVAL (0x00000000U)
5734 #define CSL_EVETPCC_IERH_I52_MAX (0x00000001U)
5736 #define CSL_EVETPCC_IERH_I40_MASK (0x00000100U)
5737 #define CSL_EVETPCC_IERH_I40_SHIFT (8U)
5738 #define CSL_EVETPCC_IERH_I40_RESETVAL (0x00000000U)
5739 #define CSL_EVETPCC_IERH_I40_MAX (0x00000001U)
5741 #define CSL_EVETPCC_IERH_I53_MASK (0x00200000U)
5742 #define CSL_EVETPCC_IERH_I53_SHIFT (21U)
5743 #define CSL_EVETPCC_IERH_I53_RESETVAL (0x00000000U)
5744 #define CSL_EVETPCC_IERH_I53_MAX (0x00000001U)
5746 #define CSL_EVETPCC_IERH_I39_MASK (0x00000080U)
5747 #define CSL_EVETPCC_IERH_I39_SHIFT (7U)
5748 #define CSL_EVETPCC_IERH_I39_RESETVAL (0x00000000U)
5749 #define CSL_EVETPCC_IERH_I39_MAX (0x00000001U)
5751 #define CSL_EVETPCC_IERH_I54_MASK (0x00400000U)
5752 #define CSL_EVETPCC_IERH_I54_SHIFT (22U)
5753 #define CSL_EVETPCC_IERH_I54_RESETVAL (0x00000000U)
5754 #define CSL_EVETPCC_IERH_I54_MAX (0x00000001U)
5756 #define CSL_EVETPCC_IERH_I55_MASK (0x00800000U)
5757 #define CSL_EVETPCC_IERH_I55_SHIFT (23U)
5758 #define CSL_EVETPCC_IERH_I55_RESETVAL (0x00000000U)
5759 #define CSL_EVETPCC_IERH_I55_MAX (0x00000001U)
5761 #define CSL_EVETPCC_IERH_I56_MASK (0x01000000U)
5762 #define CSL_EVETPCC_IERH_I56_SHIFT (24U)
5763 #define CSL_EVETPCC_IERH_I56_RESETVAL (0x00000000U)
5764 #define CSL_EVETPCC_IERH_I56_MAX (0x00000001U)
5766 #define CSL_EVETPCC_IERH_I38_MASK (0x00000040U)
5767 #define CSL_EVETPCC_IERH_I38_SHIFT (6U)
5768 #define CSL_EVETPCC_IERH_I38_RESETVAL (0x00000000U)
5769 #define CSL_EVETPCC_IERH_I38_MAX (0x00000001U)
5771 #define CSL_EVETPCC_IERH_I57_MASK (0x02000000U)
5772 #define CSL_EVETPCC_IERH_I57_SHIFT (25U)
5773 #define CSL_EVETPCC_IERH_I57_RESETVAL (0x00000000U)
5774 #define CSL_EVETPCC_IERH_I57_MAX (0x00000001U)
5776 #define CSL_EVETPCC_IERH_I58_MASK (0x04000000U)
5777 #define CSL_EVETPCC_IERH_I58_SHIFT (26U)
5778 #define CSL_EVETPCC_IERH_I58_RESETVAL (0x00000000U)
5779 #define CSL_EVETPCC_IERH_I58_MAX (0x00000001U)
5781 #define CSL_EVETPCC_IERH_I37_MASK (0x00000020U)
5782 #define CSL_EVETPCC_IERH_I37_SHIFT (5U)
5783 #define CSL_EVETPCC_IERH_I37_RESETVAL (0x00000000U)
5784 #define CSL_EVETPCC_IERH_I37_MAX (0x00000001U)
5786 #define CSL_EVETPCC_IERH_I47_MASK (0x00008000U)
5787 #define CSL_EVETPCC_IERH_I47_SHIFT (15U)
5788 #define CSL_EVETPCC_IERH_I47_RESETVAL (0x00000000U)
5789 #define CSL_EVETPCC_IERH_I47_MAX (0x00000001U)
5791 #define CSL_EVETPCC_IERH_I36_MASK (0x00000010U)
5792 #define CSL_EVETPCC_IERH_I36_SHIFT (4U)
5793 #define CSL_EVETPCC_IERH_I36_RESETVAL (0x00000000U)
5794 #define CSL_EVETPCC_IERH_I36_MAX (0x00000001U)
5796 #define CSL_EVETPCC_IERH_RESETVAL (0x00000000U)
5798 /* IECR */
5800 #define CSL_EVETPCC_IECR_I27_MASK (0x08000000U)
5801 #define CSL_EVETPCC_IECR_I27_SHIFT (27U)
5802 #define CSL_EVETPCC_IECR_I27_RESETVAL (0x00000000U)
5803 #define CSL_EVETPCC_IECR_I27_MAX (0x00000001U)
5805 #define CSL_EVETPCC_IECR_I28_MASK (0x10000000U)
5806 #define CSL_EVETPCC_IECR_I28_SHIFT (28U)
5807 #define CSL_EVETPCC_IECR_I28_RESETVAL (0x00000000U)
5808 #define CSL_EVETPCC_IECR_I28_MAX (0x00000001U)
5810 #define CSL_EVETPCC_IECR_I25_MASK (0x02000000U)
5811 #define CSL_EVETPCC_IECR_I25_SHIFT (25U)
5812 #define CSL_EVETPCC_IECR_I25_RESETVAL (0x00000000U)
5813 #define CSL_EVETPCC_IECR_I25_MAX (0x00000001U)
5815 #define CSL_EVETPCC_IECR_I16_MASK (0x00010000U)
5816 #define CSL_EVETPCC_IECR_I16_SHIFT (16U)
5817 #define CSL_EVETPCC_IECR_I16_RESETVAL (0x00000000U)
5818 #define CSL_EVETPCC_IECR_I16_MAX (0x00000001U)
5820 #define CSL_EVETPCC_IECR_I26_MASK (0x04000000U)
5821 #define CSL_EVETPCC_IECR_I26_SHIFT (26U)
5822 #define CSL_EVETPCC_IECR_I26_RESETVAL (0x00000000U)
5823 #define CSL_EVETPCC_IECR_I26_MAX (0x00000001U)
5825 #define CSL_EVETPCC_IECR_I15_MASK (0x00008000U)
5826 #define CSL_EVETPCC_IECR_I15_SHIFT (15U)
5827 #define CSL_EVETPCC_IECR_I15_RESETVAL (0x00000000U)
5828 #define CSL_EVETPCC_IECR_I15_MAX (0x00000001U)
5830 #define CSL_EVETPCC_IECR_I14_MASK (0x00004000U)
5831 #define CSL_EVETPCC_IECR_I14_SHIFT (14U)
5832 #define CSL_EVETPCC_IECR_I14_RESETVAL (0x00000000U)
5833 #define CSL_EVETPCC_IECR_I14_MAX (0x00000001U)
5835 #define CSL_EVETPCC_IECR_I13_MASK (0x00002000U)
5836 #define CSL_EVETPCC_IECR_I13_SHIFT (13U)
5837 #define CSL_EVETPCC_IECR_I13_RESETVAL (0x00000000U)
5838 #define CSL_EVETPCC_IECR_I13_MAX (0x00000001U)
5840 #define CSL_EVETPCC_IECR_I0_MASK (0x00000001U)
5841 #define CSL_EVETPCC_IECR_I0_SHIFT (0U)
5842 #define CSL_EVETPCC_IECR_I0_RESETVAL (0x00000000U)
5843 #define CSL_EVETPCC_IECR_I0_MAX (0x00000001U)
5845 #define CSL_EVETPCC_IECR_I22_MASK (0x00400000U)
5846 #define CSL_EVETPCC_IECR_I22_SHIFT (22U)
5847 #define CSL_EVETPCC_IECR_I22_RESETVAL (0x00000000U)
5848 #define CSL_EVETPCC_IECR_I22_MAX (0x00000001U)
5850 #define CSL_EVETPCC_IECR_I10_MASK (0x00000400U)
5851 #define CSL_EVETPCC_IECR_I10_SHIFT (10U)
5852 #define CSL_EVETPCC_IECR_I10_RESETVAL (0x00000000U)
5853 #define CSL_EVETPCC_IECR_I10_MAX (0x00000001U)
5855 #define CSL_EVETPCC_IECR_I21_MASK (0x00200000U)
5856 #define CSL_EVETPCC_IECR_I21_SHIFT (21U)
5857 #define CSL_EVETPCC_IECR_I21_RESETVAL (0x00000000U)
5858 #define CSL_EVETPCC_IECR_I21_MAX (0x00000001U)
5860 #define CSL_EVETPCC_IECR_I9_MASK (0x00000200U)
5861 #define CSL_EVETPCC_IECR_I9_SHIFT (9U)
5862 #define CSL_EVETPCC_IECR_I9_RESETVAL (0x00000000U)
5863 #define CSL_EVETPCC_IECR_I9_MAX (0x00000001U)
5865 #define CSL_EVETPCC_IECR_I1_MASK (0x00000002U)
5866 #define CSL_EVETPCC_IECR_I1_SHIFT (1U)
5867 #define CSL_EVETPCC_IECR_I1_RESETVAL (0x00000000U)
5868 #define CSL_EVETPCC_IECR_I1_MAX (0x00000001U)
5870 #define CSL_EVETPCC_IECR_I24_MASK (0x01000000U)
5871 #define CSL_EVETPCC_IECR_I24_SHIFT (24U)
5872 #define CSL_EVETPCC_IECR_I24_RESETVAL (0x00000000U)
5873 #define CSL_EVETPCC_IECR_I24_MAX (0x00000001U)
5875 #define CSL_EVETPCC_IECR_I3_MASK (0x00000008U)
5876 #define CSL_EVETPCC_IECR_I3_SHIFT (3U)
5877 #define CSL_EVETPCC_IECR_I3_RESETVAL (0x00000000U)
5878 #define CSL_EVETPCC_IECR_I3_MAX (0x00000001U)
5880 #define CSL_EVETPCC_IECR_I2_MASK (0x00000004U)
5881 #define CSL_EVETPCC_IECR_I2_SHIFT (2U)
5882 #define CSL_EVETPCC_IECR_I2_RESETVAL (0x00000000U)
5883 #define CSL_EVETPCC_IECR_I2_MAX (0x00000001U)
5885 #define CSL_EVETPCC_IECR_I12_MASK (0x00001000U)
5886 #define CSL_EVETPCC_IECR_I12_SHIFT (12U)
5887 #define CSL_EVETPCC_IECR_I12_RESETVAL (0x00000000U)
5888 #define CSL_EVETPCC_IECR_I12_MAX (0x00000001U)
5890 #define CSL_EVETPCC_IECR_I23_MASK (0x00800000U)
5891 #define CSL_EVETPCC_IECR_I23_SHIFT (23U)
5892 #define CSL_EVETPCC_IECR_I23_RESETVAL (0x00000000U)
5893 #define CSL_EVETPCC_IECR_I23_MAX (0x00000001U)
5895 #define CSL_EVETPCC_IECR_I4_MASK (0x00000010U)
5896 #define CSL_EVETPCC_IECR_I4_SHIFT (4U)
5897 #define CSL_EVETPCC_IECR_I4_RESETVAL (0x00000000U)
5898 #define CSL_EVETPCC_IECR_I4_MAX (0x00000001U)
5900 #define CSL_EVETPCC_IECR_I11_MASK (0x00000800U)
5901 #define CSL_EVETPCC_IECR_I11_SHIFT (11U)
5902 #define CSL_EVETPCC_IECR_I11_RESETVAL (0x00000000U)
5903 #define CSL_EVETPCC_IECR_I11_MAX (0x00000001U)
5905 #define CSL_EVETPCC_IECR_I6_MASK (0x00000040U)
5906 #define CSL_EVETPCC_IECR_I6_SHIFT (6U)
5907 #define CSL_EVETPCC_IECR_I6_RESETVAL (0x00000000U)
5908 #define CSL_EVETPCC_IECR_I6_MAX (0x00000001U)
5910 #define CSL_EVETPCC_IECR_I31_MASK (0x80000000U)
5911 #define CSL_EVETPCC_IECR_I31_SHIFT (31U)
5912 #define CSL_EVETPCC_IECR_I31_RESETVAL (0x00000000U)
5913 #define CSL_EVETPCC_IECR_I31_MAX (0x00000001U)
5915 #define CSL_EVETPCC_IECR_I18_MASK (0x00040000U)
5916 #define CSL_EVETPCC_IECR_I18_SHIFT (18U)
5917 #define CSL_EVETPCC_IECR_I18_RESETVAL (0x00000000U)
5918 #define CSL_EVETPCC_IECR_I18_MAX (0x00000001U)
5920 #define CSL_EVETPCC_IECR_I17_MASK (0x00020000U)
5921 #define CSL_EVETPCC_IECR_I17_SHIFT (17U)
5922 #define CSL_EVETPCC_IECR_I17_RESETVAL (0x00000000U)
5923 #define CSL_EVETPCC_IECR_I17_MAX (0x00000001U)
5925 #define CSL_EVETPCC_IECR_I5_MASK (0x00000020U)
5926 #define CSL_EVETPCC_IECR_I5_SHIFT (5U)
5927 #define CSL_EVETPCC_IECR_I5_RESETVAL (0x00000000U)
5928 #define CSL_EVETPCC_IECR_I5_MAX (0x00000001U)
5930 #define CSL_EVETPCC_IECR_I20_MASK (0x00100000U)
5931 #define CSL_EVETPCC_IECR_I20_SHIFT (20U)
5932 #define CSL_EVETPCC_IECR_I20_RESETVAL (0x00000000U)
5933 #define CSL_EVETPCC_IECR_I20_MAX (0x00000001U)
5935 #define CSL_EVETPCC_IECR_I29_MASK (0x20000000U)
5936 #define CSL_EVETPCC_IECR_I29_SHIFT (29U)
5937 #define CSL_EVETPCC_IECR_I29_RESETVAL (0x00000000U)
5938 #define CSL_EVETPCC_IECR_I29_MAX (0x00000001U)
5940 #define CSL_EVETPCC_IECR_I8_MASK (0x00000100U)
5941 #define CSL_EVETPCC_IECR_I8_SHIFT (8U)
5942 #define CSL_EVETPCC_IECR_I8_RESETVAL (0x00000000U)
5943 #define CSL_EVETPCC_IECR_I8_MAX (0x00000001U)
5945 #define CSL_EVETPCC_IECR_I19_MASK (0x00080000U)
5946 #define CSL_EVETPCC_IECR_I19_SHIFT (19U)
5947 #define CSL_EVETPCC_IECR_I19_RESETVAL (0x00000000U)
5948 #define CSL_EVETPCC_IECR_I19_MAX (0x00000001U)
5950 #define CSL_EVETPCC_IECR_I30_MASK (0x40000000U)
5951 #define CSL_EVETPCC_IECR_I30_SHIFT (30U)
5952 #define CSL_EVETPCC_IECR_I30_RESETVAL (0x00000000U)
5953 #define CSL_EVETPCC_IECR_I30_MAX (0x00000001U)
5955 #define CSL_EVETPCC_IECR_I7_MASK (0x00000080U)
5956 #define CSL_EVETPCC_IECR_I7_SHIFT (7U)
5957 #define CSL_EVETPCC_IECR_I7_RESETVAL (0x00000000U)
5958 #define CSL_EVETPCC_IECR_I7_MAX (0x00000001U)
5960 #define CSL_EVETPCC_IECR_RESETVAL (0x00000000U)
5962 /* IECRH */
5964 #define CSL_EVETPCC_IECRH_I35_MASK (0x00000008U)
5965 #define CSL_EVETPCC_IECRH_I35_SHIFT (3U)
5966 #define CSL_EVETPCC_IECRH_I35_RESETVAL (0x00000000U)
5967 #define CSL_EVETPCC_IECRH_I35_MAX (0x00000001U)
5969 #define CSL_EVETPCC_IECRH_I48_MASK (0x00010000U)
5970 #define CSL_EVETPCC_IECRH_I48_SHIFT (16U)
5971 #define CSL_EVETPCC_IECRH_I48_RESETVAL (0x00000000U)
5972 #define CSL_EVETPCC_IECRH_I48_MAX (0x00000001U)
5974 #define CSL_EVETPCC_IECRH_I56_MASK (0x01000000U)
5975 #define CSL_EVETPCC_IECRH_I56_SHIFT (24U)
5976 #define CSL_EVETPCC_IECRH_I56_RESETVAL (0x00000000U)
5977 #define CSL_EVETPCC_IECRH_I56_MAX (0x00000001U)
5979 #define CSL_EVETPCC_IECRH_I34_MASK (0x00000004U)
5980 #define CSL_EVETPCC_IECRH_I34_SHIFT (2U)
5981 #define CSL_EVETPCC_IECRH_I34_RESETVAL (0x00000000U)
5982 #define CSL_EVETPCC_IECRH_I34_MAX (0x00000001U)
5984 #define CSL_EVETPCC_IECRH_I47_MASK (0x00008000U)
5985 #define CSL_EVETPCC_IECRH_I47_SHIFT (15U)
5986 #define CSL_EVETPCC_IECRH_I47_RESETVAL (0x00000000U)
5987 #define CSL_EVETPCC_IECRH_I47_MAX (0x00000001U)
5989 #define CSL_EVETPCC_IECRH_I46_MASK (0x00004000U)
5990 #define CSL_EVETPCC_IECRH_I46_SHIFT (14U)
5991 #define CSL_EVETPCC_IECRH_I46_RESETVAL (0x00000000U)
5992 #define CSL_EVETPCC_IECRH_I46_MAX (0x00000001U)
5994 #define CSL_EVETPCC_IECRH_I55_MASK (0x00800000U)
5995 #define CSL_EVETPCC_IECRH_I55_SHIFT (23U)
5996 #define CSL_EVETPCC_IECRH_I55_RESETVAL (0x00000000U)
5997 #define CSL_EVETPCC_IECRH_I55_MAX (0x00000001U)
5999 #define CSL_EVETPCC_IECRH_I45_MASK (0x00002000U)
6000 #define CSL_EVETPCC_IECRH_I45_SHIFT (13U)
6001 #define CSL_EVETPCC_IECRH_I45_RESETVAL (0x00000000U)
6002 #define CSL_EVETPCC_IECRH_I45_MAX (0x00000001U)
6004 #define CSL_EVETPCC_IECRH_I58_MASK (0x04000000U)
6005 #define CSL_EVETPCC_IECRH_I58_SHIFT (26U)
6006 #define CSL_EVETPCC_IECRH_I58_RESETVAL (0x00000000U)
6007 #define CSL_EVETPCC_IECRH_I58_MAX (0x00000001U)
6009 #define CSL_EVETPCC_IECRH_I32_MASK (0x00000001U)
6010 #define CSL_EVETPCC_IECRH_I32_SHIFT (0U)
6011 #define CSL_EVETPCC_IECRH_I32_RESETVAL (0x00000000U)
6012 #define CSL_EVETPCC_IECRH_I32_MAX (0x00000001U)
6014 #define CSL_EVETPCC_IECRH_I44_MASK (0x00001000U)
6015 #define CSL_EVETPCC_IECRH_I44_SHIFT (12U)
6016 #define CSL_EVETPCC_IECRH_I44_RESETVAL (0x00000000U)
6017 #define CSL_EVETPCC_IECRH_I44_MAX (0x00000001U)
6019 #define CSL_EVETPCC_IECRH_I33_MASK (0x00000002U)
6020 #define CSL_EVETPCC_IECRH_I33_SHIFT (1U)
6021 #define CSL_EVETPCC_IECRH_I33_RESETVAL (0x00000000U)
6022 #define CSL_EVETPCC_IECRH_I33_MAX (0x00000001U)
6024 #define CSL_EVETPCC_IECRH_I57_MASK (0x02000000U)
6025 #define CSL_EVETPCC_IECRH_I57_SHIFT (25U)
6026 #define CSL_EVETPCC_IECRH_I57_RESETVAL (0x00000000U)
6027 #define CSL_EVETPCC_IECRH_I57_MAX (0x00000001U)
6029 #define CSL_EVETPCC_IECRH_I43_MASK (0x00000800U)
6030 #define CSL_EVETPCC_IECRH_I43_SHIFT (11U)
6031 #define CSL_EVETPCC_IECRH_I43_RESETVAL (0x00000000U)
6032 #define CSL_EVETPCC_IECRH_I43_MAX (0x00000001U)
6034 #define CSL_EVETPCC_IECRH_I60_MASK (0x10000000U)
6035 #define CSL_EVETPCC_IECRH_I60_SHIFT (28U)
6036 #define CSL_EVETPCC_IECRH_I60_RESETVAL (0x00000000U)
6037 #define CSL_EVETPCC_IECRH_I60_MAX (0x00000001U)
6039 #define CSL_EVETPCC_IECRH_I42_MASK (0x00000400U)
6040 #define CSL_EVETPCC_IECRH_I42_SHIFT (10U)
6041 #define CSL_EVETPCC_IECRH_I42_RESETVAL (0x00000000U)
6042 #define CSL_EVETPCC_IECRH_I42_MAX (0x00000001U)
6044 #define CSL_EVETPCC_IECRH_I59_MASK (0x08000000U)
6045 #define CSL_EVETPCC_IECRH_I59_SHIFT (27U)
6046 #define CSL_EVETPCC_IECRH_I59_RESETVAL (0x00000000U)
6047 #define CSL_EVETPCC_IECRH_I59_MAX (0x00000001U)
6049 #define CSL_EVETPCC_IECRH_I41_MASK (0x00000200U)
6050 #define CSL_EVETPCC_IECRH_I41_SHIFT (9U)
6051 #define CSL_EVETPCC_IECRH_I41_RESETVAL (0x00000000U)
6052 #define CSL_EVETPCC_IECRH_I41_MAX (0x00000001U)
6054 #define CSL_EVETPCC_IECRH_I62_MASK (0x40000000U)
6055 #define CSL_EVETPCC_IECRH_I62_SHIFT (30U)
6056 #define CSL_EVETPCC_IECRH_I62_RESETVAL (0x00000000U)
6057 #define CSL_EVETPCC_IECRH_I62_MAX (0x00000001U)
6059 #define CSL_EVETPCC_IECRH_I61_MASK (0x20000000U)
6060 #define CSL_EVETPCC_IECRH_I61_SHIFT (29U)
6061 #define CSL_EVETPCC_IECRH_I61_RESETVAL (0x00000000U)
6062 #define CSL_EVETPCC_IECRH_I61_MAX (0x00000001U)
6064 #define CSL_EVETPCC_IECRH_I52_MASK (0x00100000U)
6065 #define CSL_EVETPCC_IECRH_I52_SHIFT (20U)
6066 #define CSL_EVETPCC_IECRH_I52_RESETVAL (0x00000000U)
6067 #define CSL_EVETPCC_IECRH_I52_MAX (0x00000001U)
6069 #define CSL_EVETPCC_IECRH_I38_MASK (0x00000040U)
6070 #define CSL_EVETPCC_IECRH_I38_SHIFT (6U)
6071 #define CSL_EVETPCC_IECRH_I38_RESETVAL (0x00000000U)
6072 #define CSL_EVETPCC_IECRH_I38_MAX (0x00000001U)
6074 #define CSL_EVETPCC_IECRH_I40_MASK (0x00000100U)
6075 #define CSL_EVETPCC_IECRH_I40_SHIFT (8U)
6076 #define CSL_EVETPCC_IECRH_I40_RESETVAL (0x00000000U)
6077 #define CSL_EVETPCC_IECRH_I40_MAX (0x00000001U)
6079 #define CSL_EVETPCC_IECRH_I51_MASK (0x00080000U)
6080 #define CSL_EVETPCC_IECRH_I51_SHIFT (19U)
6081 #define CSL_EVETPCC_IECRH_I51_RESETVAL (0x00000000U)
6082 #define CSL_EVETPCC_IECRH_I51_MAX (0x00000001U)
6084 #define CSL_EVETPCC_IECRH_I50_MASK (0x00040000U)
6085 #define CSL_EVETPCC_IECRH_I50_SHIFT (18U)
6086 #define CSL_EVETPCC_IECRH_I50_RESETVAL (0x00000000U)
6087 #define CSL_EVETPCC_IECRH_I50_MAX (0x00000001U)
6089 #define CSL_EVETPCC_IECRH_I63_MASK (0x80000000U)
6090 #define CSL_EVETPCC_IECRH_I63_SHIFT (31U)
6091 #define CSL_EVETPCC_IECRH_I63_RESETVAL (0x00000000U)
6092 #define CSL_EVETPCC_IECRH_I63_MAX (0x00000001U)
6094 #define CSL_EVETPCC_IECRH_I39_MASK (0x00000080U)
6095 #define CSL_EVETPCC_IECRH_I39_SHIFT (7U)
6096 #define CSL_EVETPCC_IECRH_I39_RESETVAL (0x00000000U)
6097 #define CSL_EVETPCC_IECRH_I39_MAX (0x00000001U)
6099 #define CSL_EVETPCC_IECRH_I54_MASK (0x00400000U)
6100 #define CSL_EVETPCC_IECRH_I54_SHIFT (22U)
6101 #define CSL_EVETPCC_IECRH_I54_RESETVAL (0x00000000U)
6102 #define CSL_EVETPCC_IECRH_I54_MAX (0x00000001U)
6104 #define CSL_EVETPCC_IECRH_I36_MASK (0x00000010U)
6105 #define CSL_EVETPCC_IECRH_I36_SHIFT (4U)
6106 #define CSL_EVETPCC_IECRH_I36_RESETVAL (0x00000000U)
6107 #define CSL_EVETPCC_IECRH_I36_MAX (0x00000001U)
6109 #define CSL_EVETPCC_IECRH_I53_MASK (0x00200000U)
6110 #define CSL_EVETPCC_IECRH_I53_SHIFT (21U)
6111 #define CSL_EVETPCC_IECRH_I53_RESETVAL (0x00000000U)
6112 #define CSL_EVETPCC_IECRH_I53_MAX (0x00000001U)
6114 #define CSL_EVETPCC_IECRH_I49_MASK (0x00020000U)
6115 #define CSL_EVETPCC_IECRH_I49_SHIFT (17U)
6116 #define CSL_EVETPCC_IECRH_I49_RESETVAL (0x00000000U)
6117 #define CSL_EVETPCC_IECRH_I49_MAX (0x00000001U)
6119 #define CSL_EVETPCC_IECRH_I37_MASK (0x00000020U)
6120 #define CSL_EVETPCC_IECRH_I37_SHIFT (5U)
6121 #define CSL_EVETPCC_IECRH_I37_RESETVAL (0x00000000U)
6122 #define CSL_EVETPCC_IECRH_I37_MAX (0x00000001U)
6124 #define CSL_EVETPCC_IECRH_RESETVAL (0x00000000U)
6126 /* IESR */
6128 #define CSL_EVETPCC_IESR_I22_MASK (0x00400000U)
6129 #define CSL_EVETPCC_IESR_I22_SHIFT (22U)
6130 #define CSL_EVETPCC_IESR_I22_RESETVAL (0x00000000U)
6131 #define CSL_EVETPCC_IESR_I22_MAX (0x00000001U)
6133 #define CSL_EVETPCC_IESR_I11_MASK (0x00000800U)
6134 #define CSL_EVETPCC_IESR_I11_SHIFT (11U)
6135 #define CSL_EVETPCC_IESR_I11_RESETVAL (0x00000000U)
6136 #define CSL_EVETPCC_IESR_I11_MAX (0x00000001U)
6138 #define CSL_EVETPCC_IESR_I23_MASK (0x00800000U)
6139 #define CSL_EVETPCC_IESR_I23_SHIFT (23U)
6140 #define CSL_EVETPCC_IESR_I23_RESETVAL (0x00000000U)
6141 #define CSL_EVETPCC_IESR_I23_MAX (0x00000001U)
6143 #define CSL_EVETPCC_IESR_I0_MASK (0x00000001U)
6144 #define CSL_EVETPCC_IESR_I0_SHIFT (0U)
6145 #define CSL_EVETPCC_IESR_I0_RESETVAL (0x00000000U)
6146 #define CSL_EVETPCC_IESR_I0_MAX (0x00000001U)
6148 #define CSL_EVETPCC_IESR_I21_MASK (0x00200000U)
6149 #define CSL_EVETPCC_IESR_I21_SHIFT (21U)
6150 #define CSL_EVETPCC_IESR_I21_RESETVAL (0x00000000U)
6151 #define CSL_EVETPCC_IESR_I21_MAX (0x00000001U)
6153 #define CSL_EVETPCC_IESR_I10_MASK (0x00000400U)
6154 #define CSL_EVETPCC_IESR_I10_SHIFT (10U)
6155 #define CSL_EVETPCC_IESR_I10_RESETVAL (0x00000000U)
6156 #define CSL_EVETPCC_IESR_I10_MAX (0x00000001U)
6158 #define CSL_EVETPCC_IESR_I31_MASK (0x80000000U)
6159 #define CSL_EVETPCC_IESR_I31_SHIFT (31U)
6160 #define CSL_EVETPCC_IESR_I31_RESETVAL (0x00000000U)
6161 #define CSL_EVETPCC_IESR_I31_MAX (0x00000001U)
6163 #define CSL_EVETPCC_IESR_I8_MASK (0x00000100U)
6164 #define CSL_EVETPCC_IESR_I8_SHIFT (8U)
6165 #define CSL_EVETPCC_IESR_I8_RESETVAL (0x00000000U)
6166 #define CSL_EVETPCC_IESR_I8_MAX (0x00000001U)
6168 #define CSL_EVETPCC_IESR_I20_MASK (0x00100000U)
6169 #define CSL_EVETPCC_IESR_I20_SHIFT (20U)
6170 #define CSL_EVETPCC_IESR_I20_RESETVAL (0x00000000U)
6171 #define CSL_EVETPCC_IESR_I20_MAX (0x00000001U)
6173 #define CSL_EVETPCC_IESR_I9_MASK (0x00000200U)
6174 #define CSL_EVETPCC_IESR_I9_SHIFT (9U)
6175 #define CSL_EVETPCC_IESR_I9_RESETVAL (0x00000000U)
6176 #define CSL_EVETPCC_IESR_I9_MAX (0x00000001U)
6178 #define CSL_EVETPCC_IESR_I6_MASK (0x00000040U)
6179 #define CSL_EVETPCC_IESR_I6_SHIFT (6U)
6180 #define CSL_EVETPCC_IESR_I6_RESETVAL (0x00000000U)
6181 #define CSL_EVETPCC_IESR_I6_MAX (0x00000001U)
6183 #define CSL_EVETPCC_IESR_I30_MASK (0x40000000U)
6184 #define CSL_EVETPCC_IESR_I30_SHIFT (30U)
6185 #define CSL_EVETPCC_IESR_I30_RESETVAL (0x00000000U)
6186 #define CSL_EVETPCC_IESR_I30_MAX (0x00000001U)
6188 #define CSL_EVETPCC_IESR_I17_MASK (0x00020000U)
6189 #define CSL_EVETPCC_IESR_I17_SHIFT (17U)
6190 #define CSL_EVETPCC_IESR_I17_RESETVAL (0x00000000U)
6191 #define CSL_EVETPCC_IESR_I17_MAX (0x00000001U)
6193 #define CSL_EVETPCC_IESR_I7_MASK (0x00000080U)
6194 #define CSL_EVETPCC_IESR_I7_SHIFT (7U)
6195 #define CSL_EVETPCC_IESR_I7_RESETVAL (0x00000000U)
6196 #define CSL_EVETPCC_IESR_I7_MAX (0x00000001U)
6198 #define CSL_EVETPCC_IESR_I16_MASK (0x00010000U)
6199 #define CSL_EVETPCC_IESR_I16_SHIFT (16U)
6200 #define CSL_EVETPCC_IESR_I16_RESETVAL (0x00000000U)
6201 #define CSL_EVETPCC_IESR_I16_MAX (0x00000001U)
6203 #define CSL_EVETPCC_IESR_I28_MASK (0x10000000U)
6204 #define CSL_EVETPCC_IESR_I28_SHIFT (28U)
6205 #define CSL_EVETPCC_IESR_I28_RESETVAL (0x00000000U)
6206 #define CSL_EVETPCC_IESR_I28_MAX (0x00000001U)
6208 #define CSL_EVETPCC_IESR_I4_MASK (0x00000010U)
6209 #define CSL_EVETPCC_IESR_I4_SHIFT (4U)
6210 #define CSL_EVETPCC_IESR_I4_RESETVAL (0x00000000U)
6211 #define CSL_EVETPCC_IESR_I4_MAX (0x00000001U)
6213 #define CSL_EVETPCC_IESR_I29_MASK (0x20000000U)
6214 #define CSL_EVETPCC_IESR_I29_SHIFT (29U)
6215 #define CSL_EVETPCC_IESR_I29_RESETVAL (0x00000000U)
6216 #define CSL_EVETPCC_IESR_I29_MAX (0x00000001U)
6218 #define CSL_EVETPCC_IESR_I19_MASK (0x00080000U)
6219 #define CSL_EVETPCC_IESR_I19_SHIFT (19U)
6220 #define CSL_EVETPCC_IESR_I19_RESETVAL (0x00000000U)
6221 #define CSL_EVETPCC_IESR_I19_MAX (0x00000001U)
6223 #define CSL_EVETPCC_IESR_I5_MASK (0x00000020U)
6224 #define CSL_EVETPCC_IESR_I5_SHIFT (5U)
6225 #define CSL_EVETPCC_IESR_I5_RESETVAL (0x00000000U)
6226 #define CSL_EVETPCC_IESR_I5_MAX (0x00000001U)
6228 #define CSL_EVETPCC_IESR_I18_MASK (0x00040000U)
6229 #define CSL_EVETPCC_IESR_I18_SHIFT (18U)
6230 #define CSL_EVETPCC_IESR_I18_RESETVAL (0x00000000U)
6231 #define CSL_EVETPCC_IESR_I18_MAX (0x00000001U)
6233 #define CSL_EVETPCC_IESR_I26_MASK (0x04000000U)
6234 #define CSL_EVETPCC_IESR_I26_SHIFT (26U)
6235 #define CSL_EVETPCC_IESR_I26_RESETVAL (0x00000000U)
6236 #define CSL_EVETPCC_IESR_I26_MAX (0x00000001U)
6238 #define CSL_EVETPCC_IESR_I2_MASK (0x00000004U)
6239 #define CSL_EVETPCC_IESR_I2_SHIFT (2U)
6240 #define CSL_EVETPCC_IESR_I2_RESETVAL (0x00000000U)
6241 #define CSL_EVETPCC_IESR_I2_MAX (0x00000001U)
6243 #define CSL_EVETPCC_IESR_I13_MASK (0x00002000U)
6244 #define CSL_EVETPCC_IESR_I13_SHIFT (13U)
6245 #define CSL_EVETPCC_IESR_I13_RESETVAL (0x00000000U)
6246 #define CSL_EVETPCC_IESR_I13_MAX (0x00000001U)
6248 #define CSL_EVETPCC_IESR_I3_MASK (0x00000008U)
6249 #define CSL_EVETPCC_IESR_I3_SHIFT (3U)
6250 #define CSL_EVETPCC_IESR_I3_RESETVAL (0x00000000U)
6251 #define CSL_EVETPCC_IESR_I3_MAX (0x00000001U)
6253 #define CSL_EVETPCC_IESR_I27_MASK (0x08000000U)
6254 #define CSL_EVETPCC_IESR_I27_SHIFT (27U)
6255 #define CSL_EVETPCC_IESR_I27_RESETVAL (0x00000000U)
6256 #define CSL_EVETPCC_IESR_I27_MAX (0x00000001U)
6258 #define CSL_EVETPCC_IESR_I12_MASK (0x00001000U)
6259 #define CSL_EVETPCC_IESR_I12_SHIFT (12U)
6260 #define CSL_EVETPCC_IESR_I12_RESETVAL (0x00000000U)
6261 #define CSL_EVETPCC_IESR_I12_MAX (0x00000001U)
6263 #define CSL_EVETPCC_IESR_I24_MASK (0x01000000U)
6264 #define CSL_EVETPCC_IESR_I24_SHIFT (24U)
6265 #define CSL_EVETPCC_IESR_I24_RESETVAL (0x00000000U)
6266 #define CSL_EVETPCC_IESR_I24_MAX (0x00000001U)
6268 #define CSL_EVETPCC_IESR_I15_MASK (0x00008000U)
6269 #define CSL_EVETPCC_IESR_I15_SHIFT (15U)
6270 #define CSL_EVETPCC_IESR_I15_RESETVAL (0x00000000U)
6271 #define CSL_EVETPCC_IESR_I15_MAX (0x00000001U)
6273 #define CSL_EVETPCC_IESR_I1_MASK (0x00000002U)
6274 #define CSL_EVETPCC_IESR_I1_SHIFT (1U)
6275 #define CSL_EVETPCC_IESR_I1_RESETVAL (0x00000000U)
6276 #define CSL_EVETPCC_IESR_I1_MAX (0x00000001U)
6278 #define CSL_EVETPCC_IESR_I25_MASK (0x02000000U)
6279 #define CSL_EVETPCC_IESR_I25_SHIFT (25U)
6280 #define CSL_EVETPCC_IESR_I25_RESETVAL (0x00000000U)
6281 #define CSL_EVETPCC_IESR_I25_MAX (0x00000001U)
6283 #define CSL_EVETPCC_IESR_I14_MASK (0x00004000U)
6284 #define CSL_EVETPCC_IESR_I14_SHIFT (14U)
6285 #define CSL_EVETPCC_IESR_I14_RESETVAL (0x00000000U)
6286 #define CSL_EVETPCC_IESR_I14_MAX (0x00000001U)
6288 #define CSL_EVETPCC_IESR_RESETVAL (0x00000000U)
6290 /* IESRH */
6292 #define CSL_EVETPCC_IESRH_I52_MASK (0x00100000U)
6293 #define CSL_EVETPCC_IESRH_I52_SHIFT (20U)
6294 #define CSL_EVETPCC_IESRH_I52_RESETVAL (0x00000000U)
6295 #define CSL_EVETPCC_IESRH_I52_MAX (0x00000001U)
6297 #define CSL_EVETPCC_IESRH_I41_MASK (0x00000200U)
6298 #define CSL_EVETPCC_IESRH_I41_SHIFT (9U)
6299 #define CSL_EVETPCC_IESRH_I41_RESETVAL (0x00000000U)
6300 #define CSL_EVETPCC_IESRH_I41_MAX (0x00000001U)
6302 #define CSL_EVETPCC_IESRH_I53_MASK (0x00200000U)
6303 #define CSL_EVETPCC_IESRH_I53_SHIFT (21U)
6304 #define CSL_EVETPCC_IESRH_I53_RESETVAL (0x00000000U)
6305 #define CSL_EVETPCC_IESRH_I53_MAX (0x00000001U)
6307 #define CSL_EVETPCC_IESRH_I42_MASK (0x00000400U)
6308 #define CSL_EVETPCC_IESRH_I42_SHIFT (10U)
6309 #define CSL_EVETPCC_IESRH_I42_RESETVAL (0x00000000U)
6310 #define CSL_EVETPCC_IESRH_I42_MAX (0x00000001U)
6312 #define CSL_EVETPCC_IESRH_I54_MASK (0x00400000U)
6313 #define CSL_EVETPCC_IESRH_I54_SHIFT (22U)
6314 #define CSL_EVETPCC_IESRH_I54_RESETVAL (0x00000000U)
6315 #define CSL_EVETPCC_IESRH_I54_MAX (0x00000001U)
6317 #define CSL_EVETPCC_IESRH_I43_MASK (0x00000800U)
6318 #define CSL_EVETPCC_IESRH_I43_SHIFT (11U)
6319 #define CSL_EVETPCC_IESRH_I43_RESETVAL (0x00000000U)
6320 #define CSL_EVETPCC_IESRH_I43_MAX (0x00000001U)
6322 #define CSL_EVETPCC_IESRH_I55_MASK (0x00800000U)
6323 #define CSL_EVETPCC_IESRH_I55_SHIFT (23U)
6324 #define CSL_EVETPCC_IESRH_I55_RESETVAL (0x00000000U)
6325 #define CSL_EVETPCC_IESRH_I55_MAX (0x00000001U)
6327 #define CSL_EVETPCC_IESRH_I44_MASK (0x00001000U)
6328 #define CSL_EVETPCC_IESRH_I44_SHIFT (12U)
6329 #define CSL_EVETPCC_IESRH_I44_RESETVAL (0x00000000U)
6330 #define CSL_EVETPCC_IESRH_I44_MAX (0x00000001U)
6332 #define CSL_EVETPCC_IESRH_I33_MASK (0x00000002U)
6333 #define CSL_EVETPCC_IESRH_I33_SHIFT (1U)
6334 #define CSL_EVETPCC_IESRH_I33_RESETVAL (0x00000000U)
6335 #define CSL_EVETPCC_IESRH_I33_MAX (0x00000001U)
6337 #define CSL_EVETPCC_IESRH_I56_MASK (0x01000000U)
6338 #define CSL_EVETPCC_IESRH_I56_SHIFT (24U)
6339 #define CSL_EVETPCC_IESRH_I56_RESETVAL (0x00000000U)
6340 #define CSL_EVETPCC_IESRH_I56_MAX (0x00000001U)
6342 #define CSL_EVETPCC_IESRH_I45_MASK (0x00002000U)
6343 #define CSL_EVETPCC_IESRH_I45_SHIFT (13U)
6344 #define CSL_EVETPCC_IESRH_I45_RESETVAL (0x00000000U)
6345 #define CSL_EVETPCC_IESRH_I45_MAX (0x00000001U)
6347 #define CSL_EVETPCC_IESRH_I57_MASK (0x02000000U)
6348 #define CSL_EVETPCC_IESRH_I57_SHIFT (25U)
6349 #define CSL_EVETPCC_IESRH_I57_RESETVAL (0x00000000U)
6350 #define CSL_EVETPCC_IESRH_I57_MAX (0x00000001U)
6352 #define CSL_EVETPCC_IESRH_I32_MASK (0x00000001U)
6353 #define CSL_EVETPCC_IESRH_I32_SHIFT (0U)
6354 #define CSL_EVETPCC_IESRH_I32_RESETVAL (0x00000000U)
6355 #define CSL_EVETPCC_IESRH_I32_MAX (0x00000001U)
6357 #define CSL_EVETPCC_IESRH_I46_MASK (0x00004000U)
6358 #define CSL_EVETPCC_IESRH_I46_SHIFT (14U)
6359 #define CSL_EVETPCC_IESRH_I46_RESETVAL (0x00000000U)
6360 #define CSL_EVETPCC_IESRH_I46_MAX (0x00000001U)
6362 #define CSL_EVETPCC_IESRH_I35_MASK (0x00000008U)
6363 #define CSL_EVETPCC_IESRH_I35_SHIFT (3U)
6364 #define CSL_EVETPCC_IESRH_I35_RESETVAL (0x00000000U)
6365 #define CSL_EVETPCC_IESRH_I35_MAX (0x00000001U)
6367 #define CSL_EVETPCC_IESRH_I58_MASK (0x04000000U)
6368 #define CSL_EVETPCC_IESRH_I58_SHIFT (26U)
6369 #define CSL_EVETPCC_IESRH_I58_RESETVAL (0x00000000U)
6370 #define CSL_EVETPCC_IESRH_I58_MAX (0x00000001U)
6372 #define CSL_EVETPCC_IESRH_I47_MASK (0x00008000U)
6373 #define CSL_EVETPCC_IESRH_I47_SHIFT (15U)
6374 #define CSL_EVETPCC_IESRH_I47_RESETVAL (0x00000000U)
6375 #define CSL_EVETPCC_IESRH_I47_MAX (0x00000001U)
6377 #define CSL_EVETPCC_IESRH_I34_MASK (0x00000004U)
6378 #define CSL_EVETPCC_IESRH_I34_SHIFT (2U)
6379 #define CSL_EVETPCC_IESRH_I34_RESETVAL (0x00000000U)
6380 #define CSL_EVETPCC_IESRH_I34_MAX (0x00000001U)
6382 #define CSL_EVETPCC_IESRH_I59_MASK (0x08000000U)
6383 #define CSL_EVETPCC_IESRH_I59_SHIFT (27U)
6384 #define CSL_EVETPCC_IESRH_I59_RESETVAL (0x00000000U)
6385 #define CSL_EVETPCC_IESRH_I59_MAX (0x00000001U)
6387 #define CSL_EVETPCC_IESRH_I48_MASK (0x00010000U)
6388 #define CSL_EVETPCC_IESRH_I48_SHIFT (16U)
6389 #define CSL_EVETPCC_IESRH_I48_RESETVAL (0x00000000U)
6390 #define CSL_EVETPCC_IESRH_I48_MAX (0x00000001U)
6392 #define CSL_EVETPCC_IESRH_I60_MASK (0x10000000U)
6393 #define CSL_EVETPCC_IESRH_I60_SHIFT (28U)
6394 #define CSL_EVETPCC_IESRH_I60_RESETVAL (0x00000000U)
6395 #define CSL_EVETPCC_IESRH_I60_MAX (0x00000001U)
6397 #define CSL_EVETPCC_IESRH_I37_MASK (0x00000020U)
6398 #define CSL_EVETPCC_IESRH_I37_SHIFT (5U)
6399 #define CSL_EVETPCC_IESRH_I37_RESETVAL (0x00000000U)
6400 #define CSL_EVETPCC_IESRH_I37_MAX (0x00000001U)
6402 #define CSL_EVETPCC_IESRH_I49_MASK (0x00020000U)
6403 #define CSL_EVETPCC_IESRH_I49_SHIFT (17U)
6404 #define CSL_EVETPCC_IESRH_I49_RESETVAL (0x00000000U)
6405 #define CSL_EVETPCC_IESRH_I49_MAX (0x00000001U)
6407 #define CSL_EVETPCC_IESRH_I36_MASK (0x00000010U)
6408 #define CSL_EVETPCC_IESRH_I36_SHIFT (4U)
6409 #define CSL_EVETPCC_IESRH_I36_RESETVAL (0x00000000U)
6410 #define CSL_EVETPCC_IESRH_I36_MAX (0x00000001U)
6412 #define CSL_EVETPCC_IESRH_I50_MASK (0x00040000U)
6413 #define CSL_EVETPCC_IESRH_I50_SHIFT (18U)
6414 #define CSL_EVETPCC_IESRH_I50_RESETVAL (0x00000000U)
6415 #define CSL_EVETPCC_IESRH_I50_MAX (0x00000001U)
6417 #define CSL_EVETPCC_IESRH_I39_MASK (0x00000080U)
6418 #define CSL_EVETPCC_IESRH_I39_SHIFT (7U)
6419 #define CSL_EVETPCC_IESRH_I39_RESETVAL (0x00000000U)
6420 #define CSL_EVETPCC_IESRH_I39_MAX (0x00000001U)
6422 #define CSL_EVETPCC_IESRH_I38_MASK (0x00000040U)
6423 #define CSL_EVETPCC_IESRH_I38_SHIFT (6U)
6424 #define CSL_EVETPCC_IESRH_I38_RESETVAL (0x00000000U)
6425 #define CSL_EVETPCC_IESRH_I38_MAX (0x00000001U)
6427 #define CSL_EVETPCC_IESRH_I63_MASK (0x80000000U)
6428 #define CSL_EVETPCC_IESRH_I63_SHIFT (31U)
6429 #define CSL_EVETPCC_IESRH_I63_RESETVAL (0x00000000U)
6430 #define CSL_EVETPCC_IESRH_I63_MAX (0x00000001U)
6432 #define CSL_EVETPCC_IESRH_I62_MASK (0x40000000U)
6433 #define CSL_EVETPCC_IESRH_I62_SHIFT (30U)
6434 #define CSL_EVETPCC_IESRH_I62_RESETVAL (0x00000000U)
6435 #define CSL_EVETPCC_IESRH_I62_MAX (0x00000001U)
6437 #define CSL_EVETPCC_IESRH_I40_MASK (0x00000100U)
6438 #define CSL_EVETPCC_IESRH_I40_SHIFT (8U)
6439 #define CSL_EVETPCC_IESRH_I40_RESETVAL (0x00000000U)
6440 #define CSL_EVETPCC_IESRH_I40_MAX (0x00000001U)
6442 #define CSL_EVETPCC_IESRH_I61_MASK (0x20000000U)
6443 #define CSL_EVETPCC_IESRH_I61_SHIFT (29U)
6444 #define CSL_EVETPCC_IESRH_I61_RESETVAL (0x00000000U)
6445 #define CSL_EVETPCC_IESRH_I61_MAX (0x00000001U)
6447 #define CSL_EVETPCC_IESRH_I51_MASK (0x00080000U)
6448 #define CSL_EVETPCC_IESRH_I51_SHIFT (19U)
6449 #define CSL_EVETPCC_IESRH_I51_RESETVAL (0x00000000U)
6450 #define CSL_EVETPCC_IESRH_I51_MAX (0x00000001U)
6452 #define CSL_EVETPCC_IESRH_RESETVAL (0x00000000U)
6454 /* IPR */
6456 #define CSL_EVETPCC_IPR_I15_MASK (0x00008000U)
6457 #define CSL_EVETPCC_IPR_I15_SHIFT (15U)
6458 #define CSL_EVETPCC_IPR_I15_RESETVAL (0x00000000U)
6459 #define CSL_EVETPCC_IPR_I15_MAX (0x00000001U)
6461 #define CSL_EVETPCC_IPR_I27_MASK (0x08000000U)
6462 #define CSL_EVETPCC_IPR_I27_SHIFT (27U)
6463 #define CSL_EVETPCC_IPR_I27_RESETVAL (0x00000000U)
6464 #define CSL_EVETPCC_IPR_I27_MAX (0x00000001U)
6466 #define CSL_EVETPCC_IPR_I3_MASK (0x00000008U)
6467 #define CSL_EVETPCC_IPR_I3_SHIFT (3U)
6468 #define CSL_EVETPCC_IPR_I3_RESETVAL (0x00000000U)
6469 #define CSL_EVETPCC_IPR_I3_MAX (0x00000001U)
6471 #define CSL_EVETPCC_IPR_I14_MASK (0x00004000U)
6472 #define CSL_EVETPCC_IPR_I14_SHIFT (14U)
6473 #define CSL_EVETPCC_IPR_I14_RESETVAL (0x00000000U)
6474 #define CSL_EVETPCC_IPR_I14_MAX (0x00000001U)
6476 #define CSL_EVETPCC_IPR_I2_MASK (0x00000004U)
6477 #define CSL_EVETPCC_IPR_I2_SHIFT (2U)
6478 #define CSL_EVETPCC_IPR_I2_RESETVAL (0x00000000U)
6479 #define CSL_EVETPCC_IPR_I2_MAX (0x00000001U)
6481 #define CSL_EVETPCC_IPR_I1_MASK (0x00000002U)
6482 #define CSL_EVETPCC_IPR_I1_SHIFT (1U)
6483 #define CSL_EVETPCC_IPR_I1_RESETVAL (0x00000000U)
6484 #define CSL_EVETPCC_IPR_I1_MAX (0x00000001U)
6486 #define CSL_EVETPCC_IPR_I13_MASK (0x00002000U)
6487 #define CSL_EVETPCC_IPR_I13_SHIFT (13U)
6488 #define CSL_EVETPCC_IPR_I13_RESETVAL (0x00000000U)
6489 #define CSL_EVETPCC_IPR_I13_MAX (0x00000001U)
6491 #define CSL_EVETPCC_IPR_I28_MASK (0x10000000U)
6492 #define CSL_EVETPCC_IPR_I28_SHIFT (28U)
6493 #define CSL_EVETPCC_IPR_I28_RESETVAL (0x00000000U)
6494 #define CSL_EVETPCC_IPR_I28_MAX (0x00000001U)
6496 #define CSL_EVETPCC_IPR_I17_MASK (0x00020000U)
6497 #define CSL_EVETPCC_IPR_I17_SHIFT (17U)
6498 #define CSL_EVETPCC_IPR_I17_RESETVAL (0x00000000U)
6499 #define CSL_EVETPCC_IPR_I17_MAX (0x00000001U)
6501 #define CSL_EVETPCC_IPR_I0_MASK (0x00000001U)
6502 #define CSL_EVETPCC_IPR_I0_SHIFT (0U)
6503 #define CSL_EVETPCC_IPR_I0_RESETVAL (0x00000000U)
6504 #define CSL_EVETPCC_IPR_I0_MAX (0x00000001U)
6506 #define CSL_EVETPCC_IPR_I12_MASK (0x00001000U)
6507 #define CSL_EVETPCC_IPR_I12_SHIFT (12U)
6508 #define CSL_EVETPCC_IPR_I12_RESETVAL (0x00000000U)
6509 #define CSL_EVETPCC_IPR_I12_MAX (0x00000001U)
6511 #define CSL_EVETPCC_IPR_I29_MASK (0x20000000U)
6512 #define CSL_EVETPCC_IPR_I29_SHIFT (29U)
6513 #define CSL_EVETPCC_IPR_I29_RESETVAL (0x00000000U)
6514 #define CSL_EVETPCC_IPR_I29_MAX (0x00000001U)
6516 #define CSL_EVETPCC_IPR_I6_MASK (0x00000040U)
6517 #define CSL_EVETPCC_IPR_I6_SHIFT (6U)
6518 #define CSL_EVETPCC_IPR_I6_RESETVAL (0x00000000U)
6519 #define CSL_EVETPCC_IPR_I6_MAX (0x00000001U)
6521 #define CSL_EVETPCC_IPR_I26_MASK (0x04000000U)
6522 #define CSL_EVETPCC_IPR_I26_SHIFT (26U)
6523 #define CSL_EVETPCC_IPR_I26_RESETVAL (0x00000000U)
6524 #define CSL_EVETPCC_IPR_I26_MAX (0x00000001U)
6526 #define CSL_EVETPCC_IPR_I5_MASK (0x00000020U)
6527 #define CSL_EVETPCC_IPR_I5_SHIFT (5U)
6528 #define CSL_EVETPCC_IPR_I5_RESETVAL (0x00000000U)
6529 #define CSL_EVETPCC_IPR_I5_MAX (0x00000001U)
6531 #define CSL_EVETPCC_IPR_I4_MASK (0x00000010U)
6532 #define CSL_EVETPCC_IPR_I4_SHIFT (4U)
6533 #define CSL_EVETPCC_IPR_I4_RESETVAL (0x00000000U)
6534 #define CSL_EVETPCC_IPR_I4_MAX (0x00000001U)
6536 #define CSL_EVETPCC_IPR_I16_MASK (0x00010000U)
6537 #define CSL_EVETPCC_IPR_I16_SHIFT (16U)
6538 #define CSL_EVETPCC_IPR_I16_RESETVAL (0x00000000U)
6539 #define CSL_EVETPCC_IPR_I16_MAX (0x00000001U)
6541 #define CSL_EVETPCC_IPR_I23_MASK (0x00800000U)
6542 #define CSL_EVETPCC_IPR_I23_SHIFT (23U)
6543 #define CSL_EVETPCC_IPR_I23_RESETVAL (0x00000000U)
6544 #define CSL_EVETPCC_IPR_I23_MAX (0x00000001U)
6546 #define CSL_EVETPCC_IPR_I7_MASK (0x00000080U)
6547 #define CSL_EVETPCC_IPR_I7_SHIFT (7U)
6548 #define CSL_EVETPCC_IPR_I7_RESETVAL (0x00000000U)
6549 #define CSL_EVETPCC_IPR_I7_MAX (0x00000001U)
6551 #define CSL_EVETPCC_IPR_I22_MASK (0x00400000U)
6552 #define CSL_EVETPCC_IPR_I22_SHIFT (22U)
6553 #define CSL_EVETPCC_IPR_I22_RESETVAL (0x00000000U)
6554 #define CSL_EVETPCC_IPR_I22_MAX (0x00000001U)
6556 #define CSL_EVETPCC_IPR_I25_MASK (0x02000000U)
6557 #define CSL_EVETPCC_IPR_I25_SHIFT (25U)
6558 #define CSL_EVETPCC_IPR_I25_RESETVAL (0x00000000U)
6559 #define CSL_EVETPCC_IPR_I25_MAX (0x00000001U)
6561 #define CSL_EVETPCC_IPR_I24_MASK (0x01000000U)
6562 #define CSL_EVETPCC_IPR_I24_SHIFT (24U)
6563 #define CSL_EVETPCC_IPR_I24_RESETVAL (0x00000000U)
6564 #define CSL_EVETPCC_IPR_I24_MAX (0x00000001U)
6566 #define CSL_EVETPCC_IPR_I19_MASK (0x00080000U)
6567 #define CSL_EVETPCC_IPR_I19_SHIFT (19U)
6568 #define CSL_EVETPCC_IPR_I19_RESETVAL (0x00000000U)
6569 #define CSL_EVETPCC_IPR_I19_MAX (0x00000001U)
6571 #define CSL_EVETPCC_IPR_I30_MASK (0x40000000U)
6572 #define CSL_EVETPCC_IPR_I30_SHIFT (30U)
6573 #define CSL_EVETPCC_IPR_I30_RESETVAL (0x00000000U)
6574 #define CSL_EVETPCC_IPR_I30_MAX (0x00000001U)
6576 #define CSL_EVETPCC_IPR_I11_MASK (0x00000800U)
6577 #define CSL_EVETPCC_IPR_I11_SHIFT (11U)
6578 #define CSL_EVETPCC_IPR_I11_RESETVAL (0x00000000U)
6579 #define CSL_EVETPCC_IPR_I11_MAX (0x00000001U)
6581 #define CSL_EVETPCC_IPR_I18_MASK (0x00040000U)
6582 #define CSL_EVETPCC_IPR_I18_SHIFT (18U)
6583 #define CSL_EVETPCC_IPR_I18_RESETVAL (0x00000000U)
6584 #define CSL_EVETPCC_IPR_I18_MAX (0x00000001U)
6586 #define CSL_EVETPCC_IPR_I31_MASK (0x80000000U)
6587 #define CSL_EVETPCC_IPR_I31_SHIFT (31U)
6588 #define CSL_EVETPCC_IPR_I31_RESETVAL (0x00000000U)
6589 #define CSL_EVETPCC_IPR_I31_MAX (0x00000001U)
6591 #define CSL_EVETPCC_IPR_I10_MASK (0x00000400U)
6592 #define CSL_EVETPCC_IPR_I10_SHIFT (10U)
6593 #define CSL_EVETPCC_IPR_I10_RESETVAL (0x00000000U)
6594 #define CSL_EVETPCC_IPR_I10_MAX (0x00000001U)
6596 #define CSL_EVETPCC_IPR_I9_MASK (0x00000200U)
6597 #define CSL_EVETPCC_IPR_I9_SHIFT (9U)
6598 #define CSL_EVETPCC_IPR_I9_RESETVAL (0x00000000U)
6599 #define CSL_EVETPCC_IPR_I9_MAX (0x00000001U)
6601 #define CSL_EVETPCC_IPR_I21_MASK (0x00200000U)
6602 #define CSL_EVETPCC_IPR_I21_SHIFT (21U)
6603 #define CSL_EVETPCC_IPR_I21_RESETVAL (0x00000000U)
6604 #define CSL_EVETPCC_IPR_I21_MAX (0x00000001U)
6606 #define CSL_EVETPCC_IPR_I8_MASK (0x00000100U)
6607 #define CSL_EVETPCC_IPR_I8_SHIFT (8U)
6608 #define CSL_EVETPCC_IPR_I8_RESETVAL (0x00000000U)
6609 #define CSL_EVETPCC_IPR_I8_MAX (0x00000001U)
6611 #define CSL_EVETPCC_IPR_I20_MASK (0x00100000U)
6612 #define CSL_EVETPCC_IPR_I20_SHIFT (20U)
6613 #define CSL_EVETPCC_IPR_I20_RESETVAL (0x00000000U)
6614 #define CSL_EVETPCC_IPR_I20_MAX (0x00000001U)
6616 #define CSL_EVETPCC_IPR_RESETVAL (0x00000000U)
6618 /* IPRH */
6620 #define CSL_EVETPCC_IPRH_I53_MASK (0x00200000U)
6621 #define CSL_EVETPCC_IPRH_I53_SHIFT (21U)
6622 #define CSL_EVETPCC_IPRH_I53_RESETVAL (0x00000000U)
6623 #define CSL_EVETPCC_IPRH_I53_MAX (0x00000001U)
6625 #define CSL_EVETPCC_IPRH_I41_MASK (0x00000200U)
6626 #define CSL_EVETPCC_IPRH_I41_SHIFT (9U)
6627 #define CSL_EVETPCC_IPRH_I41_RESETVAL (0x00000000U)
6628 #define CSL_EVETPCC_IPRH_I41_MAX (0x00000001U)
6630 #define CSL_EVETPCC_IPRH_I52_MASK (0x00100000U)
6631 #define CSL_EVETPCC_IPRH_I52_SHIFT (20U)
6632 #define CSL_EVETPCC_IPRH_I52_RESETVAL (0x00000000U)
6633 #define CSL_EVETPCC_IPRH_I52_MAX (0x00000001U)
6635 #define CSL_EVETPCC_IPRH_I40_MASK (0x00000100U)
6636 #define CSL_EVETPCC_IPRH_I40_SHIFT (8U)
6637 #define CSL_EVETPCC_IPRH_I40_RESETVAL (0x00000000U)
6638 #define CSL_EVETPCC_IPRH_I40_MAX (0x00000001U)
6640 #define CSL_EVETPCC_IPRH_I51_MASK (0x00080000U)
6641 #define CSL_EVETPCC_IPRH_I51_SHIFT (19U)
6642 #define CSL_EVETPCC_IPRH_I51_RESETVAL (0x00000000U)
6643 #define CSL_EVETPCC_IPRH_I51_MAX (0x00000001U)
6645 #define CSL_EVETPCC_IPRH_I39_MASK (0x00000080U)
6646 #define CSL_EVETPCC_IPRH_I39_SHIFT (7U)
6647 #define CSL_EVETPCC_IPRH_I39_RESETVAL (0x00000000U)
6648 #define CSL_EVETPCC_IPRH_I39_MAX (0x00000001U)
6650 #define CSL_EVETPCC_IPRH_I32_MASK (0x00000001U)
6651 #define CSL_EVETPCC_IPRH_I32_SHIFT (0U)
6652 #define CSL_EVETPCC_IPRH_I32_RESETVAL (0x00000000U)
6653 #define CSL_EVETPCC_IPRH_I32_MAX (0x00000001U)
6655 #define CSL_EVETPCC_IPRH_I50_MASK (0x00040000U)
6656 #define CSL_EVETPCC_IPRH_I50_SHIFT (18U)
6657 #define CSL_EVETPCC_IPRH_I50_RESETVAL (0x00000000U)
6658 #define CSL_EVETPCC_IPRH_I50_MAX (0x00000001U)
6660 #define CSL_EVETPCC_IPRH_I33_MASK (0x00000002U)
6661 #define CSL_EVETPCC_IPRH_I33_SHIFT (1U)
6662 #define CSL_EVETPCC_IPRH_I33_RESETVAL (0x00000000U)
6663 #define CSL_EVETPCC_IPRH_I33_MAX (0x00000001U)
6665 #define CSL_EVETPCC_IPRH_I34_MASK (0x00000004U)
6666 #define CSL_EVETPCC_IPRH_I34_SHIFT (2U)
6667 #define CSL_EVETPCC_IPRH_I34_RESETVAL (0x00000000U)
6668 #define CSL_EVETPCC_IPRH_I34_MAX (0x00000001U)
6670 #define CSL_EVETPCC_IPRH_I49_MASK (0x00020000U)
6671 #define CSL_EVETPCC_IPRH_I49_SHIFT (17U)
6672 #define CSL_EVETPCC_IPRH_I49_RESETVAL (0x00000000U)
6673 #define CSL_EVETPCC_IPRH_I49_MAX (0x00000001U)
6675 #define CSL_EVETPCC_IPRH_I60_MASK (0x10000000U)
6676 #define CSL_EVETPCC_IPRH_I60_SHIFT (28U)
6677 #define CSL_EVETPCC_IPRH_I60_RESETVAL (0x00000000U)
6678 #define CSL_EVETPCC_IPRH_I60_MAX (0x00000001U)
6680 #define CSL_EVETPCC_IPRH_I47_MASK (0x00008000U)
6681 #define CSL_EVETPCC_IPRH_I47_SHIFT (15U)
6682 #define CSL_EVETPCC_IPRH_I47_RESETVAL (0x00000000U)
6683 #define CSL_EVETPCC_IPRH_I47_MAX (0x00000001U)
6685 #define CSL_EVETPCC_IPRH_I35_MASK (0x00000008U)
6686 #define CSL_EVETPCC_IPRH_I35_SHIFT (3U)
6687 #define CSL_EVETPCC_IPRH_I35_RESETVAL (0x00000000U)
6688 #define CSL_EVETPCC_IPRH_I35_MAX (0x00000001U)
6690 #define CSL_EVETPCC_IPRH_I36_MASK (0x00000010U)
6691 #define CSL_EVETPCC_IPRH_I36_SHIFT (4U)
6692 #define CSL_EVETPCC_IPRH_I36_RESETVAL (0x00000000U)
6693 #define CSL_EVETPCC_IPRH_I36_MAX (0x00000001U)
6695 #define CSL_EVETPCC_IPRH_I59_MASK (0x08000000U)
6696 #define CSL_EVETPCC_IPRH_I59_SHIFT (27U)
6697 #define CSL_EVETPCC_IPRH_I59_RESETVAL (0x00000000U)
6698 #define CSL_EVETPCC_IPRH_I59_MAX (0x00000001U)
6700 #define CSL_EVETPCC_IPRH_I48_MASK (0x00010000U)
6701 #define CSL_EVETPCC_IPRH_I48_SHIFT (16U)
6702 #define CSL_EVETPCC_IPRH_I48_RESETVAL (0x00000000U)
6703 #define CSL_EVETPCC_IPRH_I48_MAX (0x00000001U)
6705 #define CSL_EVETPCC_IPRH_I37_MASK (0x00000020U)
6706 #define CSL_EVETPCC_IPRH_I37_SHIFT (5U)
6707 #define CSL_EVETPCC_IPRH_I37_RESETVAL (0x00000000U)
6708 #define CSL_EVETPCC_IPRH_I37_MAX (0x00000001U)
6710 #define CSL_EVETPCC_IPRH_I61_MASK (0x20000000U)
6711 #define CSL_EVETPCC_IPRH_I61_SHIFT (29U)
6712 #define CSL_EVETPCC_IPRH_I61_RESETVAL (0x00000000U)
6713 #define CSL_EVETPCC_IPRH_I61_MAX (0x00000001U)
6715 #define CSL_EVETPCC_IPRH_I38_MASK (0x00000040U)
6716 #define CSL_EVETPCC_IPRH_I38_SHIFT (6U)
6717 #define CSL_EVETPCC_IPRH_I38_RESETVAL (0x00000000U)
6718 #define CSL_EVETPCC_IPRH_I38_MAX (0x00000001U)
6720 #define CSL_EVETPCC_IPRH_I58_MASK (0x04000000U)
6721 #define CSL_EVETPCC_IPRH_I58_SHIFT (26U)
6722 #define CSL_EVETPCC_IPRH_I58_RESETVAL (0x00000000U)
6723 #define CSL_EVETPCC_IPRH_I58_MAX (0x00000001U)
6725 #define CSL_EVETPCC_IPRH_I46_MASK (0x00004000U)
6726 #define CSL_EVETPCC_IPRH_I46_SHIFT (14U)
6727 #define CSL_EVETPCC_IPRH_I46_RESETVAL (0x00000000U)
6728 #define CSL_EVETPCC_IPRH_I46_MAX (0x00000001U)
6730 #define CSL_EVETPCC_IPRH_I45_MASK (0x00002000U)
6731 #define CSL_EVETPCC_IPRH_I45_SHIFT (13U)
6732 #define CSL_EVETPCC_IPRH_I45_RESETVAL (0x00000000U)
6733 #define CSL_EVETPCC_IPRH_I45_MAX (0x00000001U)
6735 #define CSL_EVETPCC_IPRH_I57_MASK (0x02000000U)
6736 #define CSL_EVETPCC_IPRH_I57_SHIFT (25U)
6737 #define CSL_EVETPCC_IPRH_I57_RESETVAL (0x00000000U)
6738 #define CSL_EVETPCC_IPRH_I57_MAX (0x00000001U)
6740 #define CSL_EVETPCC_IPRH_I44_MASK (0x00001000U)
6741 #define CSL_EVETPCC_IPRH_I44_SHIFT (12U)
6742 #define CSL_EVETPCC_IPRH_I44_RESETVAL (0x00000000U)
6743 #define CSL_EVETPCC_IPRH_I44_MAX (0x00000001U)
6745 #define CSL_EVETPCC_IPRH_I56_MASK (0x01000000U)
6746 #define CSL_EVETPCC_IPRH_I56_SHIFT (24U)
6747 #define CSL_EVETPCC_IPRH_I56_RESETVAL (0x00000000U)
6748 #define CSL_EVETPCC_IPRH_I56_MAX (0x00000001U)
6750 #define CSL_EVETPCC_IPRH_I63_MASK (0x80000000U)
6751 #define CSL_EVETPCC_IPRH_I63_SHIFT (31U)
6752 #define CSL_EVETPCC_IPRH_I63_RESETVAL (0x00000000U)
6753 #define CSL_EVETPCC_IPRH_I63_MAX (0x00000001U)
6755 #define CSL_EVETPCC_IPRH_I43_MASK (0x00000800U)
6756 #define CSL_EVETPCC_IPRH_I43_SHIFT (11U)
6757 #define CSL_EVETPCC_IPRH_I43_RESETVAL (0x00000000U)
6758 #define CSL_EVETPCC_IPRH_I43_MAX (0x00000001U)
6760 #define CSL_EVETPCC_IPRH_I55_MASK (0x00800000U)
6761 #define CSL_EVETPCC_IPRH_I55_SHIFT (23U)
6762 #define CSL_EVETPCC_IPRH_I55_RESETVAL (0x00000000U)
6763 #define CSL_EVETPCC_IPRH_I55_MAX (0x00000001U)
6765 #define CSL_EVETPCC_IPRH_I62_MASK (0x40000000U)
6766 #define CSL_EVETPCC_IPRH_I62_SHIFT (30U)
6767 #define CSL_EVETPCC_IPRH_I62_RESETVAL (0x00000000U)
6768 #define CSL_EVETPCC_IPRH_I62_MAX (0x00000001U)
6770 #define CSL_EVETPCC_IPRH_I42_MASK (0x00000400U)
6771 #define CSL_EVETPCC_IPRH_I42_SHIFT (10U)
6772 #define CSL_EVETPCC_IPRH_I42_RESETVAL (0x00000000U)
6773 #define CSL_EVETPCC_IPRH_I42_MAX (0x00000001U)
6775 #define CSL_EVETPCC_IPRH_I54_MASK (0x00400000U)
6776 #define CSL_EVETPCC_IPRH_I54_SHIFT (22U)
6777 #define CSL_EVETPCC_IPRH_I54_RESETVAL (0x00000000U)
6778 #define CSL_EVETPCC_IPRH_I54_MAX (0x00000001U)
6780 #define CSL_EVETPCC_IPRH_RESETVAL (0x00000000U)
6782 /* ICR */
6784 #define CSL_EVETPCC_ICR_I17_MASK (0x00020000U)
6785 #define CSL_EVETPCC_ICR_I17_SHIFT (17U)
6786 #define CSL_EVETPCC_ICR_I17_RESETVAL (0x00000000U)
6787 #define CSL_EVETPCC_ICR_I17_MAX (0x00000001U)
6789 #define CSL_EVETPCC_ICR_I30_MASK (0x40000000U)
6790 #define CSL_EVETPCC_ICR_I30_SHIFT (30U)
6791 #define CSL_EVETPCC_ICR_I30_RESETVAL (0x00000000U)
6792 #define CSL_EVETPCC_ICR_I30_MAX (0x00000001U)
6794 #define CSL_EVETPCC_ICR_I7_MASK (0x00000080U)
6795 #define CSL_EVETPCC_ICR_I7_SHIFT (7U)
6796 #define CSL_EVETPCC_ICR_I7_RESETVAL (0x00000000U)
6797 #define CSL_EVETPCC_ICR_I7_MAX (0x00000001U)
6799 #define CSL_EVETPCC_ICR_I19_MASK (0x00080000U)
6800 #define CSL_EVETPCC_ICR_I19_SHIFT (19U)
6801 #define CSL_EVETPCC_ICR_I19_RESETVAL (0x00000000U)
6802 #define CSL_EVETPCC_ICR_I19_MAX (0x00000001U)
6804 #define CSL_EVETPCC_ICR_I16_MASK (0x00010000U)
6805 #define CSL_EVETPCC_ICR_I16_SHIFT (16U)
6806 #define CSL_EVETPCC_ICR_I16_RESETVAL (0x00000000U)
6807 #define CSL_EVETPCC_ICR_I16_MAX (0x00000001U)
6809 #define CSL_EVETPCC_ICR_I6_MASK (0x00000040U)
6810 #define CSL_EVETPCC_ICR_I6_SHIFT (6U)
6811 #define CSL_EVETPCC_ICR_I6_RESETVAL (0x00000000U)
6812 #define CSL_EVETPCC_ICR_I6_MAX (0x00000001U)
6814 #define CSL_EVETPCC_ICR_I31_MASK (0x80000000U)
6815 #define CSL_EVETPCC_ICR_I31_SHIFT (31U)
6816 #define CSL_EVETPCC_ICR_I31_RESETVAL (0x00000000U)
6817 #define CSL_EVETPCC_ICR_I31_MAX (0x00000001U)
6819 #define CSL_EVETPCC_ICR_I20_MASK (0x00100000U)
6820 #define CSL_EVETPCC_ICR_I20_SHIFT (20U)
6821 #define CSL_EVETPCC_ICR_I20_RESETVAL (0x00000000U)
6822 #define CSL_EVETPCC_ICR_I20_MAX (0x00000001U)
6824 #define CSL_EVETPCC_ICR_I18_MASK (0x00040000U)
6825 #define CSL_EVETPCC_ICR_I18_SHIFT (18U)
6826 #define CSL_EVETPCC_ICR_I18_RESETVAL (0x00000000U)
6827 #define CSL_EVETPCC_ICR_I18_MAX (0x00000001U)
6829 #define CSL_EVETPCC_ICR_I21_MASK (0x00200000U)
6830 #define CSL_EVETPCC_ICR_I21_SHIFT (21U)
6831 #define CSL_EVETPCC_ICR_I21_RESETVAL (0x00000000U)
6832 #define CSL_EVETPCC_ICR_I21_MAX (0x00000001U)
6834 #define CSL_EVETPCC_ICR_I8_MASK (0x00000100U)
6835 #define CSL_EVETPCC_ICR_I8_SHIFT (8U)
6836 #define CSL_EVETPCC_ICR_I8_RESETVAL (0x00000000U)
6837 #define CSL_EVETPCC_ICR_I8_MAX (0x00000001U)
6839 #define CSL_EVETPCC_ICR_I22_MASK (0x00400000U)
6840 #define CSL_EVETPCC_ICR_I22_SHIFT (22U)
6841 #define CSL_EVETPCC_ICR_I22_RESETVAL (0x00000000U)
6842 #define CSL_EVETPCC_ICR_I22_MAX (0x00000001U)
6844 #define CSL_EVETPCC_ICR_I13_MASK (0x00002000U)
6845 #define CSL_EVETPCC_ICR_I13_SHIFT (13U)
6846 #define CSL_EVETPCC_ICR_I13_RESETVAL (0x00000000U)
6847 #define CSL_EVETPCC_ICR_I13_MAX (0x00000001U)
6849 #define CSL_EVETPCC_ICR_I3_MASK (0x00000008U)
6850 #define CSL_EVETPCC_ICR_I3_SHIFT (3U)
6851 #define CSL_EVETPCC_ICR_I3_RESETVAL (0x00000000U)
6852 #define CSL_EVETPCC_ICR_I3_MAX (0x00000001U)
6854 #define CSL_EVETPCC_ICR_I23_MASK (0x00800000U)
6855 #define CSL_EVETPCC_ICR_I23_SHIFT (23U)
6856 #define CSL_EVETPCC_ICR_I23_RESETVAL (0x00000000U)
6857 #define CSL_EVETPCC_ICR_I23_MAX (0x00000001U)
6859 #define CSL_EVETPCC_ICR_I12_MASK (0x00001000U)
6860 #define CSL_EVETPCC_ICR_I12_SHIFT (12U)
6861 #define CSL_EVETPCC_ICR_I12_RESETVAL (0x00000000U)
6862 #define CSL_EVETPCC_ICR_I12_MAX (0x00000001U)
6864 #define CSL_EVETPCC_ICR_I2_MASK (0x00000004U)
6865 #define CSL_EVETPCC_ICR_I2_SHIFT (2U)
6866 #define CSL_EVETPCC_ICR_I2_RESETVAL (0x00000000U)
6867 #define CSL_EVETPCC_ICR_I2_MAX (0x00000001U)
6869 #define CSL_EVETPCC_ICR_I24_MASK (0x01000000U)
6870 #define CSL_EVETPCC_ICR_I24_SHIFT (24U)
6871 #define CSL_EVETPCC_ICR_I24_RESETVAL (0x00000000U)
6872 #define CSL_EVETPCC_ICR_I24_MAX (0x00000001U)
6874 #define CSL_EVETPCC_ICR_I15_MASK (0x00008000U)
6875 #define CSL_EVETPCC_ICR_I15_SHIFT (15U)
6876 #define CSL_EVETPCC_ICR_I15_RESETVAL (0x00000000U)
6877 #define CSL_EVETPCC_ICR_I15_MAX (0x00000001U)
6879 #define CSL_EVETPCC_ICR_I25_MASK (0x02000000U)
6880 #define CSL_EVETPCC_ICR_I25_SHIFT (25U)
6881 #define CSL_EVETPCC_ICR_I25_RESETVAL (0x00000000U)
6882 #define CSL_EVETPCC_ICR_I25_MAX (0x00000001U)
6884 #define CSL_EVETPCC_ICR_I5_MASK (0x00000020U)
6885 #define CSL_EVETPCC_ICR_I5_SHIFT (5U)
6886 #define CSL_EVETPCC_ICR_I5_RESETVAL (0x00000000U)
6887 #define CSL_EVETPCC_ICR_I5_MAX (0x00000001U)
6889 #define CSL_EVETPCC_ICR_I14_MASK (0x00004000U)
6890 #define CSL_EVETPCC_ICR_I14_SHIFT (14U)
6891 #define CSL_EVETPCC_ICR_I14_RESETVAL (0x00000000U)
6892 #define CSL_EVETPCC_ICR_I14_MAX (0x00000001U)
6894 #define CSL_EVETPCC_ICR_I4_MASK (0x00000010U)
6895 #define CSL_EVETPCC_ICR_I4_SHIFT (4U)
6896 #define CSL_EVETPCC_ICR_I4_RESETVAL (0x00000000U)
6897 #define CSL_EVETPCC_ICR_I4_MAX (0x00000001U)
6899 #define CSL_EVETPCC_ICR_I9_MASK (0x00000200U)
6900 #define CSL_EVETPCC_ICR_I9_SHIFT (9U)
6901 #define CSL_EVETPCC_ICR_I9_RESETVAL (0x00000000U)
6902 #define CSL_EVETPCC_ICR_I9_MAX (0x00000001U)
6904 #define CSL_EVETPCC_ICR_I27_MASK (0x08000000U)
6905 #define CSL_EVETPCC_ICR_I27_SHIFT (27U)
6906 #define CSL_EVETPCC_ICR_I27_RESETVAL (0x00000000U)
6907 #define CSL_EVETPCC_ICR_I27_MAX (0x00000001U)
6909 #define CSL_EVETPCC_ICR_I26_MASK (0x04000000U)
6910 #define CSL_EVETPCC_ICR_I26_SHIFT (26U)
6911 #define CSL_EVETPCC_ICR_I26_RESETVAL (0x00000000U)
6912 #define CSL_EVETPCC_ICR_I26_MAX (0x00000001U)
6914 #define CSL_EVETPCC_ICR_I11_MASK (0x00000800U)
6915 #define CSL_EVETPCC_ICR_I11_SHIFT (11U)
6916 #define CSL_EVETPCC_ICR_I11_RESETVAL (0x00000000U)
6917 #define CSL_EVETPCC_ICR_I11_MAX (0x00000001U)
6919 #define CSL_EVETPCC_ICR_I1_MASK (0x00000002U)
6920 #define CSL_EVETPCC_ICR_I1_SHIFT (1U)
6921 #define CSL_EVETPCC_ICR_I1_RESETVAL (0x00000000U)
6922 #define CSL_EVETPCC_ICR_I1_MAX (0x00000001U)
6924 #define CSL_EVETPCC_ICR_I10_MASK (0x00000400U)
6925 #define CSL_EVETPCC_ICR_I10_SHIFT (10U)
6926 #define CSL_EVETPCC_ICR_I10_RESETVAL (0x00000000U)
6927 #define CSL_EVETPCC_ICR_I10_MAX (0x00000001U)
6929 #define CSL_EVETPCC_ICR_I28_MASK (0x10000000U)
6930 #define CSL_EVETPCC_ICR_I28_SHIFT (28U)
6931 #define CSL_EVETPCC_ICR_I28_RESETVAL (0x00000000U)
6932 #define CSL_EVETPCC_ICR_I28_MAX (0x00000001U)
6934 #define CSL_EVETPCC_ICR_I0_MASK (0x00000001U)
6935 #define CSL_EVETPCC_ICR_I0_SHIFT (0U)
6936 #define CSL_EVETPCC_ICR_I0_RESETVAL (0x00000000U)
6937 #define CSL_EVETPCC_ICR_I0_MAX (0x00000001U)
6939 #define CSL_EVETPCC_ICR_I29_MASK (0x20000000U)
6940 #define CSL_EVETPCC_ICR_I29_SHIFT (29U)
6941 #define CSL_EVETPCC_ICR_I29_RESETVAL (0x00000000U)
6942 #define CSL_EVETPCC_ICR_I29_MAX (0x00000001U)
6944 #define CSL_EVETPCC_ICR_RESETVAL (0x00000000U)
6946 /* ICRH */
6948 #define CSL_EVETPCC_ICRH_I37_MASK (0x00000020U)
6949 #define CSL_EVETPCC_ICRH_I37_SHIFT (5U)
6950 #define CSL_EVETPCC_ICRH_I37_RESETVAL (0x00000000U)
6951 #define CSL_EVETPCC_ICRH_I37_MAX (0x00000001U)
6953 #define CSL_EVETPCC_ICRH_I47_MASK (0x00008000U)
6954 #define CSL_EVETPCC_ICRH_I47_SHIFT (15U)
6955 #define CSL_EVETPCC_ICRH_I47_RESETVAL (0x00000000U)
6956 #define CSL_EVETPCC_ICRH_I47_MAX (0x00000001U)
6958 #define CSL_EVETPCC_ICRH_I53_MASK (0x00200000U)
6959 #define CSL_EVETPCC_ICRH_I53_SHIFT (21U)
6960 #define CSL_EVETPCC_ICRH_I53_RESETVAL (0x00000000U)
6961 #define CSL_EVETPCC_ICRH_I53_MAX (0x00000001U)
6963 #define CSL_EVETPCC_ICRH_I36_MASK (0x00000010U)
6964 #define CSL_EVETPCC_ICRH_I36_SHIFT (4U)
6965 #define CSL_EVETPCC_ICRH_I36_RESETVAL (0x00000000U)
6966 #define CSL_EVETPCC_ICRH_I36_MAX (0x00000001U)
6968 #define CSL_EVETPCC_ICRH_I63_MASK (0x80000000U)
6969 #define CSL_EVETPCC_ICRH_I63_SHIFT (31U)
6970 #define CSL_EVETPCC_ICRH_I63_RESETVAL (0x00000000U)
6971 #define CSL_EVETPCC_ICRH_I63_MAX (0x00000001U)
6973 #define CSL_EVETPCC_ICRH_I46_MASK (0x00004000U)
6974 #define CSL_EVETPCC_ICRH_I46_SHIFT (14U)
6975 #define CSL_EVETPCC_ICRH_I46_RESETVAL (0x00000000U)
6976 #define CSL_EVETPCC_ICRH_I46_MAX (0x00000001U)
6978 #define CSL_EVETPCC_ICRH_I39_MASK (0x00000080U)
6979 #define CSL_EVETPCC_ICRH_I39_SHIFT (7U)
6980 #define CSL_EVETPCC_ICRH_I39_RESETVAL (0x00000000U)
6981 #define CSL_EVETPCC_ICRH_I39_MAX (0x00000001U)
6983 #define CSL_EVETPCC_ICRH_I49_MASK (0x00020000U)
6984 #define CSL_EVETPCC_ICRH_I49_SHIFT (17U)
6985 #define CSL_EVETPCC_ICRH_I49_RESETVAL (0x00000000U)
6986 #define CSL_EVETPCC_ICRH_I49_MAX (0x00000001U)
6988 #define CSL_EVETPCC_ICRH_I38_MASK (0x00000040U)
6989 #define CSL_EVETPCC_ICRH_I38_SHIFT (6U)
6990 #define CSL_EVETPCC_ICRH_I38_RESETVAL (0x00000000U)
6991 #define CSL_EVETPCC_ICRH_I38_MAX (0x00000001U)
6993 #define CSL_EVETPCC_ICRH_I48_MASK (0x00010000U)
6994 #define CSL_EVETPCC_ICRH_I48_SHIFT (16U)
6995 #define CSL_EVETPCC_ICRH_I48_RESETVAL (0x00000000U)
6996 #define CSL_EVETPCC_ICRH_I48_MAX (0x00000001U)
6998 #define CSL_EVETPCC_ICRH_I41_MASK (0x00000200U)
6999 #define CSL_EVETPCC_ICRH_I41_SHIFT (9U)
7000 #define CSL_EVETPCC_ICRH_I41_RESETVAL (0x00000000U)
7001 #define CSL_EVETPCC_ICRH_I41_MAX (0x00000001U)
7003 #define CSL_EVETPCC_ICRH_I51_MASK (0x00080000U)
7004 #define CSL_EVETPCC_ICRH_I51_SHIFT (19U)
7005 #define CSL_EVETPCC_ICRH_I51_RESETVAL (0x00000000U)
7006 #define CSL_EVETPCC_ICRH_I51_MAX (0x00000001U)
7008 #define CSL_EVETPCC_ICRH_I40_MASK (0x00000100U)
7009 #define CSL_EVETPCC_ICRH_I40_SHIFT (8U)
7010 #define CSL_EVETPCC_ICRH_I40_RESETVAL (0x00000000U)
7011 #define CSL_EVETPCC_ICRH_I40_MAX (0x00000001U)
7013 #define CSL_EVETPCC_ICRH_I50_MASK (0x00040000U)
7014 #define CSL_EVETPCC_ICRH_I50_SHIFT (18U)
7015 #define CSL_EVETPCC_ICRH_I50_RESETVAL (0x00000000U)
7016 #define CSL_EVETPCC_ICRH_I50_MAX (0x00000001U)
7018 #define CSL_EVETPCC_ICRH_I42_MASK (0x00000400U)
7019 #define CSL_EVETPCC_ICRH_I42_SHIFT (10U)
7020 #define CSL_EVETPCC_ICRH_I42_RESETVAL (0x00000000U)
7021 #define CSL_EVETPCC_ICRH_I42_MAX (0x00000001U)
7023 #define CSL_EVETPCC_ICRH_I62_MASK (0x40000000U)
7024 #define CSL_EVETPCC_ICRH_I62_SHIFT (30U)
7025 #define CSL_EVETPCC_ICRH_I62_RESETVAL (0x00000000U)
7026 #define CSL_EVETPCC_ICRH_I62_MAX (0x00000001U)
7028 #define CSL_EVETPCC_ICRH_I52_MASK (0x00100000U)
7029 #define CSL_EVETPCC_ICRH_I52_SHIFT (20U)
7030 #define CSL_EVETPCC_ICRH_I52_RESETVAL (0x00000000U)
7031 #define CSL_EVETPCC_ICRH_I52_MAX (0x00000001U)
7033 #define CSL_EVETPCC_ICRH_I61_MASK (0x20000000U)
7034 #define CSL_EVETPCC_ICRH_I61_SHIFT (29U)
7035 #define CSL_EVETPCC_ICRH_I61_RESETVAL (0x00000000U)
7036 #define CSL_EVETPCC_ICRH_I61_MAX (0x00000001U)
7038 #define CSL_EVETPCC_ICRH_I32_MASK (0x00000001U)
7039 #define CSL_EVETPCC_ICRH_I32_SHIFT (0U)
7040 #define CSL_EVETPCC_ICRH_I32_RESETVAL (0x00000000U)
7041 #define CSL_EVETPCC_ICRH_I32_MAX (0x00000001U)
7043 #define CSL_EVETPCC_ICRH_I60_MASK (0x10000000U)
7044 #define CSL_EVETPCC_ICRH_I60_SHIFT (28U)
7045 #define CSL_EVETPCC_ICRH_I60_RESETVAL (0x00000000U)
7046 #define CSL_EVETPCC_ICRH_I60_MAX (0x00000001U)
7048 #define CSL_EVETPCC_ICRH_I59_MASK (0x08000000U)
7049 #define CSL_EVETPCC_ICRH_I59_SHIFT (27U)
7050 #define CSL_EVETPCC_ICRH_I59_RESETVAL (0x00000000U)
7051 #define CSL_EVETPCC_ICRH_I59_MAX (0x00000001U)
7053 #define CSL_EVETPCC_ICRH_I58_MASK (0x04000000U)
7054 #define CSL_EVETPCC_ICRH_I58_SHIFT (26U)
7055 #define CSL_EVETPCC_ICRH_I58_RESETVAL (0x00000000U)
7056 #define CSL_EVETPCC_ICRH_I58_MAX (0x00000001U)
7058 #define CSL_EVETPCC_ICRH_I57_MASK (0x02000000U)
7059 #define CSL_EVETPCC_ICRH_I57_SHIFT (25U)
7060 #define CSL_EVETPCC_ICRH_I57_RESETVAL (0x00000000U)
7061 #define CSL_EVETPCC_ICRH_I57_MAX (0x00000001U)
7063 #define CSL_EVETPCC_ICRH_I33_MASK (0x00000002U)
7064 #define CSL_EVETPCC_ICRH_I33_SHIFT (1U)
7065 #define CSL_EVETPCC_ICRH_I33_RESETVAL (0x00000000U)
7066 #define CSL_EVETPCC_ICRH_I33_MAX (0x00000001U)
7068 #define CSL_EVETPCC_ICRH_I43_MASK (0x00000800U)
7069 #define CSL_EVETPCC_ICRH_I43_SHIFT (11U)
7070 #define CSL_EVETPCC_ICRH_I43_RESETVAL (0x00000000U)
7071 #define CSL_EVETPCC_ICRH_I43_MAX (0x00000001U)
7073 #define CSL_EVETPCC_ICRH_I56_MASK (0x01000000U)
7074 #define CSL_EVETPCC_ICRH_I56_SHIFT (24U)
7075 #define CSL_EVETPCC_ICRH_I56_RESETVAL (0x00000000U)
7076 #define CSL_EVETPCC_ICRH_I56_MAX (0x00000001U)
7078 #define CSL_EVETPCC_ICRH_I35_MASK (0x00000008U)
7079 #define CSL_EVETPCC_ICRH_I35_SHIFT (3U)
7080 #define CSL_EVETPCC_ICRH_I35_RESETVAL (0x00000000U)
7081 #define CSL_EVETPCC_ICRH_I35_MAX (0x00000001U)
7083 #define CSL_EVETPCC_ICRH_I55_MASK (0x00800000U)
7084 #define CSL_EVETPCC_ICRH_I55_SHIFT (23U)
7085 #define CSL_EVETPCC_ICRH_I55_RESETVAL (0x00000000U)
7086 #define CSL_EVETPCC_ICRH_I55_MAX (0x00000001U)
7088 #define CSL_EVETPCC_ICRH_I45_MASK (0x00002000U)
7089 #define CSL_EVETPCC_ICRH_I45_SHIFT (13U)
7090 #define CSL_EVETPCC_ICRH_I45_RESETVAL (0x00000000U)
7091 #define CSL_EVETPCC_ICRH_I45_MAX (0x00000001U)
7093 #define CSL_EVETPCC_ICRH_I34_MASK (0x00000004U)
7094 #define CSL_EVETPCC_ICRH_I34_SHIFT (2U)
7095 #define CSL_EVETPCC_ICRH_I34_RESETVAL (0x00000000U)
7096 #define CSL_EVETPCC_ICRH_I34_MAX (0x00000001U)
7098 #define CSL_EVETPCC_ICRH_I54_MASK (0x00400000U)
7099 #define CSL_EVETPCC_ICRH_I54_SHIFT (22U)
7100 #define CSL_EVETPCC_ICRH_I54_RESETVAL (0x00000000U)
7101 #define CSL_EVETPCC_ICRH_I54_MAX (0x00000001U)
7103 #define CSL_EVETPCC_ICRH_I44_MASK (0x00001000U)
7104 #define CSL_EVETPCC_ICRH_I44_SHIFT (12U)
7105 #define CSL_EVETPCC_ICRH_I44_RESETVAL (0x00000000U)
7106 #define CSL_EVETPCC_ICRH_I44_MAX (0x00000001U)
7108 #define CSL_EVETPCC_ICRH_RESETVAL (0x00000000U)
7110 /* IEVAL */
7112 #define CSL_EVETPCC_IEVAL_SET_MASK (0x00000002U)
7113 #define CSL_EVETPCC_IEVAL_SET_SHIFT (1U)
7114 #define CSL_EVETPCC_IEVAL_SET_RESETVAL (0x00000000U)
7115 #define CSL_EVETPCC_IEVAL_SET_MAX (0x00000001U)
7117 #define CSL_EVETPCC_IEVAL_EVAL_MASK (0x00000001U)
7118 #define CSL_EVETPCC_IEVAL_EVAL_SHIFT (0U)
7119 #define CSL_EVETPCC_IEVAL_EVAL_RESETVAL (0x00000000U)
7120 #define CSL_EVETPCC_IEVAL_EVAL_MAX (0x00000001U)
7122 #define CSL_EVETPCC_IEVAL_RESETVAL (0x00000000U)
7124 /* QER */
7126 #define CSL_EVETPCC_QER_E7_MASK (0x00000080U)
7127 #define CSL_EVETPCC_QER_E7_SHIFT (7U)
7128 #define CSL_EVETPCC_QER_E7_RESETVAL (0x00000000U)
7129 #define CSL_EVETPCC_QER_E7_MAX (0x00000001U)
7131 #define CSL_EVETPCC_QER_E6_MASK (0x00000040U)
7132 #define CSL_EVETPCC_QER_E6_SHIFT (6U)
7133 #define CSL_EVETPCC_QER_E6_RESETVAL (0x00000000U)
7134 #define CSL_EVETPCC_QER_E6_MAX (0x00000001U)
7136 #define CSL_EVETPCC_QER_E5_MASK (0x00000020U)
7137 #define CSL_EVETPCC_QER_E5_SHIFT (5U)
7138 #define CSL_EVETPCC_QER_E5_RESETVAL (0x00000000U)
7139 #define CSL_EVETPCC_QER_E5_MAX (0x00000001U)
7141 #define CSL_EVETPCC_QER_E3_MASK (0x00000008U)
7142 #define CSL_EVETPCC_QER_E3_SHIFT (3U)
7143 #define CSL_EVETPCC_QER_E3_RESETVAL (0x00000000U)
7144 #define CSL_EVETPCC_QER_E3_MAX (0x00000001U)
7146 #define CSL_EVETPCC_QER_E4_MASK (0x00000010U)
7147 #define CSL_EVETPCC_QER_E4_SHIFT (4U)
7148 #define CSL_EVETPCC_QER_E4_RESETVAL (0x00000000U)
7149 #define CSL_EVETPCC_QER_E4_MAX (0x00000001U)
7151 #define CSL_EVETPCC_QER_E1_MASK (0x00000002U)
7152 #define CSL_EVETPCC_QER_E1_SHIFT (1U)
7153 #define CSL_EVETPCC_QER_E1_RESETVAL (0x00000000U)
7154 #define CSL_EVETPCC_QER_E1_MAX (0x00000001U)
7156 #define CSL_EVETPCC_QER_E2_MASK (0x00000004U)
7157 #define CSL_EVETPCC_QER_E2_SHIFT (2U)
7158 #define CSL_EVETPCC_QER_E2_RESETVAL (0x00000000U)
7159 #define CSL_EVETPCC_QER_E2_MAX (0x00000001U)
7161 #define CSL_EVETPCC_QER_E0_MASK (0x00000001U)
7162 #define CSL_EVETPCC_QER_E0_SHIFT (0U)
7163 #define CSL_EVETPCC_QER_E0_RESETVAL (0x00000000U)
7164 #define CSL_EVETPCC_QER_E0_MAX (0x00000001U)
7166 #define CSL_EVETPCC_QER_RESETVAL (0x00000000U)
7168 /* QEER */
7170 #define CSL_EVETPCC_QEER_E6_MASK (0x00000040U)
7171 #define CSL_EVETPCC_QEER_E6_SHIFT (6U)
7172 #define CSL_EVETPCC_QEER_E6_RESETVAL (0x00000000U)
7173 #define CSL_EVETPCC_QEER_E6_MAX (0x00000001U)
7175 #define CSL_EVETPCC_QEER_E5_MASK (0x00000020U)
7176 #define CSL_EVETPCC_QEER_E5_SHIFT (5U)
7177 #define CSL_EVETPCC_QEER_E5_RESETVAL (0x00000000U)
7178 #define CSL_EVETPCC_QEER_E5_MAX (0x00000001U)
7180 #define CSL_EVETPCC_QEER_E7_MASK (0x00000080U)
7181 #define CSL_EVETPCC_QEER_E7_SHIFT (7U)
7182 #define CSL_EVETPCC_QEER_E7_RESETVAL (0x00000000U)
7183 #define CSL_EVETPCC_QEER_E7_MAX (0x00000001U)
7185 #define CSL_EVETPCC_QEER_E0_MASK (0x00000001U)
7186 #define CSL_EVETPCC_QEER_E0_SHIFT (0U)
7187 #define CSL_EVETPCC_QEER_E0_RESETVAL (0x00000000U)
7188 #define CSL_EVETPCC_QEER_E0_MAX (0x00000001U)
7190 #define CSL_EVETPCC_QEER_E2_MASK (0x00000004U)
7191 #define CSL_EVETPCC_QEER_E2_SHIFT (2U)
7192 #define CSL_EVETPCC_QEER_E2_RESETVAL (0x00000000U)
7193 #define CSL_EVETPCC_QEER_E2_MAX (0x00000001U)
7195 #define CSL_EVETPCC_QEER_E1_MASK (0x00000002U)
7196 #define CSL_EVETPCC_QEER_E1_SHIFT (1U)
7197 #define CSL_EVETPCC_QEER_E1_RESETVAL (0x00000000U)
7198 #define CSL_EVETPCC_QEER_E1_MAX (0x00000001U)
7200 #define CSL_EVETPCC_QEER_E4_MASK (0x00000010U)
7201 #define CSL_EVETPCC_QEER_E4_SHIFT (4U)
7202 #define CSL_EVETPCC_QEER_E4_RESETVAL (0x00000000U)
7203 #define CSL_EVETPCC_QEER_E4_MAX (0x00000001U)
7205 #define CSL_EVETPCC_QEER_E3_MASK (0x00000008U)
7206 #define CSL_EVETPCC_QEER_E3_SHIFT (3U)
7207 #define CSL_EVETPCC_QEER_E3_RESETVAL (0x00000000U)
7208 #define CSL_EVETPCC_QEER_E3_MAX (0x00000001U)
7210 #define CSL_EVETPCC_QEER_RESETVAL (0x00000000U)
7212 /* QEECR */
7214 #define CSL_EVETPCC_QEECR_E3_MASK (0x00000008U)
7215 #define CSL_EVETPCC_QEECR_E3_SHIFT (3U)
7216 #define CSL_EVETPCC_QEECR_E3_RESETVAL (0x00000000U)
7217 #define CSL_EVETPCC_QEECR_E3_MAX (0x00000001U)
7219 #define CSL_EVETPCC_QEECR_E2_MASK (0x00000004U)
7220 #define CSL_EVETPCC_QEECR_E2_SHIFT (2U)
7221 #define CSL_EVETPCC_QEECR_E2_RESETVAL (0x00000000U)
7222 #define CSL_EVETPCC_QEECR_E2_MAX (0x00000001U)
7224 #define CSL_EVETPCC_QEECR_E1_MASK (0x00000002U)
7225 #define CSL_EVETPCC_QEECR_E1_SHIFT (1U)
7226 #define CSL_EVETPCC_QEECR_E1_RESETVAL (0x00000000U)
7227 #define CSL_EVETPCC_QEECR_E1_MAX (0x00000001U)
7229 #define CSL_EVETPCC_QEECR_E4_MASK (0x00000010U)
7230 #define CSL_EVETPCC_QEECR_E4_SHIFT (4U)
7231 #define CSL_EVETPCC_QEECR_E4_RESETVAL (0x00000000U)
7232 #define CSL_EVETPCC_QEECR_E4_MAX (0x00000001U)
7234 #define CSL_EVETPCC_QEECR_E0_MASK (0x00000001U)
7235 #define CSL_EVETPCC_QEECR_E0_SHIFT (0U)
7236 #define CSL_EVETPCC_QEECR_E0_RESETVAL (0x00000000U)
7237 #define CSL_EVETPCC_QEECR_E0_MAX (0x00000001U)
7239 #define CSL_EVETPCC_QEECR_E6_MASK (0x00000040U)
7240 #define CSL_EVETPCC_QEECR_E6_SHIFT (6U)
7241 #define CSL_EVETPCC_QEECR_E6_RESETVAL (0x00000000U)
7242 #define CSL_EVETPCC_QEECR_E6_MAX (0x00000001U)
7244 #define CSL_EVETPCC_QEECR_E5_MASK (0x00000020U)
7245 #define CSL_EVETPCC_QEECR_E5_SHIFT (5U)
7246 #define CSL_EVETPCC_QEECR_E5_RESETVAL (0x00000000U)
7247 #define CSL_EVETPCC_QEECR_E5_MAX (0x00000001U)
7249 #define CSL_EVETPCC_QEECR_E7_MASK (0x00000080U)
7250 #define CSL_EVETPCC_QEECR_E7_SHIFT (7U)
7251 #define CSL_EVETPCC_QEECR_E7_RESETVAL (0x00000000U)
7252 #define CSL_EVETPCC_QEECR_E7_MAX (0x00000001U)
7254 #define CSL_EVETPCC_QEECR_RESETVAL (0x00000000U)
7256 /* QEESR */
7258 #define CSL_EVETPCC_QEESR_E5_MASK (0x00000020U)
7259 #define CSL_EVETPCC_QEESR_E5_SHIFT (5U)
7260 #define CSL_EVETPCC_QEESR_E5_RESETVAL (0x00000000U)
7261 #define CSL_EVETPCC_QEESR_E5_MAX (0x00000001U)
7263 #define CSL_EVETPCC_QEESR_E3_MASK (0x00000008U)
7264 #define CSL_EVETPCC_QEESR_E3_SHIFT (3U)
7265 #define CSL_EVETPCC_QEESR_E3_RESETVAL (0x00000000U)
7266 #define CSL_EVETPCC_QEESR_E3_MAX (0x00000001U)
7268 #define CSL_EVETPCC_QEESR_E6_MASK (0x00000040U)
7269 #define CSL_EVETPCC_QEESR_E6_SHIFT (6U)
7270 #define CSL_EVETPCC_QEESR_E6_RESETVAL (0x00000000U)
7271 #define CSL_EVETPCC_QEESR_E6_MAX (0x00000001U)
7273 #define CSL_EVETPCC_QEESR_E4_MASK (0x00000010U)
7274 #define CSL_EVETPCC_QEESR_E4_SHIFT (4U)
7275 #define CSL_EVETPCC_QEESR_E4_RESETVAL (0x00000000U)
7276 #define CSL_EVETPCC_QEESR_E4_MAX (0x00000001U)
7278 #define CSL_EVETPCC_QEESR_E1_MASK (0x00000002U)
7279 #define CSL_EVETPCC_QEESR_E1_SHIFT (1U)
7280 #define CSL_EVETPCC_QEESR_E1_RESETVAL (0x00000000U)
7281 #define CSL_EVETPCC_QEESR_E1_MAX (0x00000001U)
7283 #define CSL_EVETPCC_QEESR_E2_MASK (0x00000004U)
7284 #define CSL_EVETPCC_QEESR_E2_SHIFT (2U)
7285 #define CSL_EVETPCC_QEESR_E2_RESETVAL (0x00000000U)
7286 #define CSL_EVETPCC_QEESR_E2_MAX (0x00000001U)
7288 #define CSL_EVETPCC_QEESR_E0_MASK (0x00000001U)
7289 #define CSL_EVETPCC_QEESR_E0_SHIFT (0U)
7290 #define CSL_EVETPCC_QEESR_E0_RESETVAL (0x00000000U)
7291 #define CSL_EVETPCC_QEESR_E0_MAX (0x00000001U)
7293 #define CSL_EVETPCC_QEESR_E7_MASK (0x00000080U)
7294 #define CSL_EVETPCC_QEESR_E7_SHIFT (7U)
7295 #define CSL_EVETPCC_QEESR_E7_RESETVAL (0x00000000U)
7296 #define CSL_EVETPCC_QEESR_E7_MAX (0x00000001U)
7298 #define CSL_EVETPCC_QEESR_RESETVAL (0x00000000U)
7300 /* QSER */
7302 #define CSL_EVETPCC_QSER_E4_MASK (0x00000010U)
7303 #define CSL_EVETPCC_QSER_E4_SHIFT (4U)
7304 #define CSL_EVETPCC_QSER_E4_RESETVAL (0x00000000U)
7305 #define CSL_EVETPCC_QSER_E4_MAX (0x00000001U)
7307 #define CSL_EVETPCC_QSER_E3_MASK (0x00000008U)
7308 #define CSL_EVETPCC_QSER_E3_SHIFT (3U)
7309 #define CSL_EVETPCC_QSER_E3_RESETVAL (0x00000000U)
7310 #define CSL_EVETPCC_QSER_E3_MAX (0x00000001U)
7312 #define CSL_EVETPCC_QSER_E2_MASK (0x00000004U)
7313 #define CSL_EVETPCC_QSER_E2_SHIFT (2U)
7314 #define CSL_EVETPCC_QSER_E2_RESETVAL (0x00000000U)
7315 #define CSL_EVETPCC_QSER_E2_MAX (0x00000001U)
7317 #define CSL_EVETPCC_QSER_E1_MASK (0x00000002U)
7318 #define CSL_EVETPCC_QSER_E1_SHIFT (1U)
7319 #define CSL_EVETPCC_QSER_E1_RESETVAL (0x00000000U)
7320 #define CSL_EVETPCC_QSER_E1_MAX (0x00000001U)
7322 #define CSL_EVETPCC_QSER_E0_MASK (0x00000001U)
7323 #define CSL_EVETPCC_QSER_E0_SHIFT (0U)
7324 #define CSL_EVETPCC_QSER_E0_RESETVAL (0x00000000U)
7325 #define CSL_EVETPCC_QSER_E0_MAX (0x00000001U)
7327 #define CSL_EVETPCC_QSER_E7_MASK (0x00000080U)
7328 #define CSL_EVETPCC_QSER_E7_SHIFT (7U)
7329 #define CSL_EVETPCC_QSER_E7_RESETVAL (0x00000000U)
7330 #define CSL_EVETPCC_QSER_E7_MAX (0x00000001U)
7332 #define CSL_EVETPCC_QSER_E5_MASK (0x00000020U)
7333 #define CSL_EVETPCC_QSER_E5_SHIFT (5U)
7334 #define CSL_EVETPCC_QSER_E5_RESETVAL (0x00000000U)
7335 #define CSL_EVETPCC_QSER_E5_MAX (0x00000001U)
7337 #define CSL_EVETPCC_QSER_E6_MASK (0x00000040U)
7338 #define CSL_EVETPCC_QSER_E6_SHIFT (6U)
7339 #define CSL_EVETPCC_QSER_E6_RESETVAL (0x00000000U)
7340 #define CSL_EVETPCC_QSER_E6_MAX (0x00000001U)
7342 #define CSL_EVETPCC_QSER_RESETVAL (0x00000000U)
7344 /* QSECR */
7346 #define CSL_EVETPCC_QSECR_E5_MASK (0x00000020U)
7347 #define CSL_EVETPCC_QSECR_E5_SHIFT (5U)
7348 #define CSL_EVETPCC_QSECR_E5_RESETVAL (0x00000000U)
7349 #define CSL_EVETPCC_QSECR_E5_MAX (0x00000001U)
7351 #define CSL_EVETPCC_QSECR_E6_MASK (0x00000040U)
7352 #define CSL_EVETPCC_QSECR_E6_SHIFT (6U)
7353 #define CSL_EVETPCC_QSECR_E6_RESETVAL (0x00000000U)
7354 #define CSL_EVETPCC_QSECR_E6_MAX (0x00000001U)
7356 #define CSL_EVETPCC_QSECR_E7_MASK (0x00000080U)
7357 #define CSL_EVETPCC_QSECR_E7_SHIFT (7U)
7358 #define CSL_EVETPCC_QSECR_E7_RESETVAL (0x00000000U)
7359 #define CSL_EVETPCC_QSECR_E7_MAX (0x00000001U)
7361 #define CSL_EVETPCC_QSECR_E0_MASK (0x00000001U)
7362 #define CSL_EVETPCC_QSECR_E0_SHIFT (0U)
7363 #define CSL_EVETPCC_QSECR_E0_RESETVAL (0x00000000U)
7364 #define CSL_EVETPCC_QSECR_E0_MAX (0x00000001U)
7366 #define CSL_EVETPCC_QSECR_E2_MASK (0x00000004U)
7367 #define CSL_EVETPCC_QSECR_E2_SHIFT (2U)
7368 #define CSL_EVETPCC_QSECR_E2_RESETVAL (0x00000000U)
7369 #define CSL_EVETPCC_QSECR_E2_MAX (0x00000001U)
7371 #define CSL_EVETPCC_QSECR_E1_MASK (0x00000002U)
7372 #define CSL_EVETPCC_QSECR_E1_SHIFT (1U)
7373 #define CSL_EVETPCC_QSECR_E1_RESETVAL (0x00000000U)
7374 #define CSL_EVETPCC_QSECR_E1_MAX (0x00000001U)
7376 #define CSL_EVETPCC_QSECR_E4_MASK (0x00000010U)
7377 #define CSL_EVETPCC_QSECR_E4_SHIFT (4U)
7378 #define CSL_EVETPCC_QSECR_E4_RESETVAL (0x00000000U)
7379 #define CSL_EVETPCC_QSECR_E4_MAX (0x00000001U)
7381 #define CSL_EVETPCC_QSECR_E3_MASK (0x00000008U)
7382 #define CSL_EVETPCC_QSECR_E3_SHIFT (3U)
7383 #define CSL_EVETPCC_QSECR_E3_RESETVAL (0x00000000U)
7384 #define CSL_EVETPCC_QSECR_E3_MAX (0x00000001U)
7386 #define CSL_EVETPCC_QSECR_RESETVAL (0x00000000U)
7388 /* IEVAL_RN */
7390 #define CSL_EVETPCC_IEVAL_RN_SET_MASK (0x00000002U)
7391 #define CSL_EVETPCC_IEVAL_RN_SET_SHIFT (1U)
7392 #define CSL_EVETPCC_IEVAL_RN_SET_RESETVAL (0x00000000U)
7393 #define CSL_EVETPCC_IEVAL_RN_SET_MAX (0x00000001U)
7395 #define CSL_EVETPCC_IEVAL_RN_EVAL_MASK (0x00000001U)
7396 #define CSL_EVETPCC_IEVAL_RN_EVAL_SHIFT (0U)
7397 #define CSL_EVETPCC_IEVAL_RN_EVAL_RESETVAL (0x00000000U)
7398 #define CSL_EVETPCC_IEVAL_RN_EVAL_MAX (0x00000001U)
7400 #define CSL_EVETPCC_IEVAL_RN_RESETVAL (0x00000000U)
7402 /* IESRH_RN */
7404 #define CSL_EVETPCC_IESRH_RN_I52_MASK (0x00100000U)
7405 #define CSL_EVETPCC_IESRH_RN_I52_SHIFT (20U)
7406 #define CSL_EVETPCC_IESRH_RN_I52_RESETVAL (0x00000000U)
7407 #define CSL_EVETPCC_IESRH_RN_I52_MAX (0x00000001U)
7409 #define CSL_EVETPCC_IESRH_RN_I41_MASK (0x00000200U)
7410 #define CSL_EVETPCC_IESRH_RN_I41_SHIFT (9U)
7411 #define CSL_EVETPCC_IESRH_RN_I41_RESETVAL (0x00000000U)
7412 #define CSL_EVETPCC_IESRH_RN_I41_MAX (0x00000001U)
7414 #define CSL_EVETPCC_IESRH_RN_I53_MASK (0x00200000U)
7415 #define CSL_EVETPCC_IESRH_RN_I53_SHIFT (21U)
7416 #define CSL_EVETPCC_IESRH_RN_I53_RESETVAL (0x00000000U)
7417 #define CSL_EVETPCC_IESRH_RN_I53_MAX (0x00000001U)
7419 #define CSL_EVETPCC_IESRH_RN_I42_MASK (0x00000400U)
7420 #define CSL_EVETPCC_IESRH_RN_I42_SHIFT (10U)
7421 #define CSL_EVETPCC_IESRH_RN_I42_RESETVAL (0x00000000U)
7422 #define CSL_EVETPCC_IESRH_RN_I42_MAX (0x00000001U)
7424 #define CSL_EVETPCC_IESRH_RN_I54_MASK (0x00400000U)
7425 #define CSL_EVETPCC_IESRH_RN_I54_SHIFT (22U)
7426 #define CSL_EVETPCC_IESRH_RN_I54_RESETVAL (0x00000000U)
7427 #define CSL_EVETPCC_IESRH_RN_I54_MAX (0x00000001U)
7429 #define CSL_EVETPCC_IESRH_RN_I43_MASK (0x00000800U)
7430 #define CSL_EVETPCC_IESRH_RN_I43_SHIFT (11U)
7431 #define CSL_EVETPCC_IESRH_RN_I43_RESETVAL (0x00000000U)
7432 #define CSL_EVETPCC_IESRH_RN_I43_MAX (0x00000001U)
7434 #define CSL_EVETPCC_IESRH_RN_I55_MASK (0x00800000U)
7435 #define CSL_EVETPCC_IESRH_RN_I55_SHIFT (23U)
7436 #define CSL_EVETPCC_IESRH_RN_I55_RESETVAL (0x00000000U)
7437 #define CSL_EVETPCC_IESRH_RN_I55_MAX (0x00000001U)
7439 #define CSL_EVETPCC_IESRH_RN_I44_MASK (0x00001000U)
7440 #define CSL_EVETPCC_IESRH_RN_I44_SHIFT (12U)
7441 #define CSL_EVETPCC_IESRH_RN_I44_RESETVAL (0x00000000U)
7442 #define CSL_EVETPCC_IESRH_RN_I44_MAX (0x00000001U)
7444 #define CSL_EVETPCC_IESRH_RN_I33_MASK (0x00000002U)
7445 #define CSL_EVETPCC_IESRH_RN_I33_SHIFT (1U)
7446 #define CSL_EVETPCC_IESRH_RN_I33_RESETVAL (0x00000000U)
7447 #define CSL_EVETPCC_IESRH_RN_I33_MAX (0x00000001U)
7449 #define CSL_EVETPCC_IESRH_RN_I56_MASK (0x01000000U)
7450 #define CSL_EVETPCC_IESRH_RN_I56_SHIFT (24U)
7451 #define CSL_EVETPCC_IESRH_RN_I56_RESETVAL (0x00000000U)
7452 #define CSL_EVETPCC_IESRH_RN_I56_MAX (0x00000001U)
7454 #define CSL_EVETPCC_IESRH_RN_I45_MASK (0x00002000U)
7455 #define CSL_EVETPCC_IESRH_RN_I45_SHIFT (13U)
7456 #define CSL_EVETPCC_IESRH_RN_I45_RESETVAL (0x00000000U)
7457 #define CSL_EVETPCC_IESRH_RN_I45_MAX (0x00000001U)
7459 #define CSL_EVETPCC_IESRH_RN_I57_MASK (0x02000000U)
7460 #define CSL_EVETPCC_IESRH_RN_I57_SHIFT (25U)
7461 #define CSL_EVETPCC_IESRH_RN_I57_RESETVAL (0x00000000U)
7462 #define CSL_EVETPCC_IESRH_RN_I57_MAX (0x00000001U)
7464 #define CSL_EVETPCC_IESRH_RN_I32_MASK (0x00000001U)
7465 #define CSL_EVETPCC_IESRH_RN_I32_SHIFT (0U)
7466 #define CSL_EVETPCC_IESRH_RN_I32_RESETVAL (0x00000000U)
7467 #define CSL_EVETPCC_IESRH_RN_I32_MAX (0x00000001U)
7469 #define CSL_EVETPCC_IESRH_RN_I46_MASK (0x00004000U)
7470 #define CSL_EVETPCC_IESRH_RN_I46_SHIFT (14U)
7471 #define CSL_EVETPCC_IESRH_RN_I46_RESETVAL (0x00000000U)
7472 #define CSL_EVETPCC_IESRH_RN_I46_MAX (0x00000001U)
7474 #define CSL_EVETPCC_IESRH_RN_I35_MASK (0x00000008U)
7475 #define CSL_EVETPCC_IESRH_RN_I35_SHIFT (3U)
7476 #define CSL_EVETPCC_IESRH_RN_I35_RESETVAL (0x00000000U)
7477 #define CSL_EVETPCC_IESRH_RN_I35_MAX (0x00000001U)
7479 #define CSL_EVETPCC_IESRH_RN_I58_MASK (0x04000000U)
7480 #define CSL_EVETPCC_IESRH_RN_I58_SHIFT (26U)
7481 #define CSL_EVETPCC_IESRH_RN_I58_RESETVAL (0x00000000U)
7482 #define CSL_EVETPCC_IESRH_RN_I58_MAX (0x00000001U)
7484 #define CSL_EVETPCC_IESRH_RN_I47_MASK (0x00008000U)
7485 #define CSL_EVETPCC_IESRH_RN_I47_SHIFT (15U)
7486 #define CSL_EVETPCC_IESRH_RN_I47_RESETVAL (0x00000000U)
7487 #define CSL_EVETPCC_IESRH_RN_I47_MAX (0x00000001U)
7489 #define CSL_EVETPCC_IESRH_RN_I34_MASK (0x00000004U)
7490 #define CSL_EVETPCC_IESRH_RN_I34_SHIFT (2U)
7491 #define CSL_EVETPCC_IESRH_RN_I34_RESETVAL (0x00000000U)
7492 #define CSL_EVETPCC_IESRH_RN_I34_MAX (0x00000001U)
7494 #define CSL_EVETPCC_IESRH_RN_I59_MASK (0x08000000U)
7495 #define CSL_EVETPCC_IESRH_RN_I59_SHIFT (27U)
7496 #define CSL_EVETPCC_IESRH_RN_I59_RESETVAL (0x00000000U)
7497 #define CSL_EVETPCC_IESRH_RN_I59_MAX (0x00000001U)
7499 #define CSL_EVETPCC_IESRH_RN_I48_MASK (0x00010000U)
7500 #define CSL_EVETPCC_IESRH_RN_I48_SHIFT (16U)
7501 #define CSL_EVETPCC_IESRH_RN_I48_RESETVAL (0x00000000U)
7502 #define CSL_EVETPCC_IESRH_RN_I48_MAX (0x00000001U)
7504 #define CSL_EVETPCC_IESRH_RN_I60_MASK (0x10000000U)
7505 #define CSL_EVETPCC_IESRH_RN_I60_SHIFT (28U)
7506 #define CSL_EVETPCC_IESRH_RN_I60_RESETVAL (0x00000000U)
7507 #define CSL_EVETPCC_IESRH_RN_I60_MAX (0x00000001U)
7509 #define CSL_EVETPCC_IESRH_RN_I37_MASK (0x00000020U)
7510 #define CSL_EVETPCC_IESRH_RN_I37_SHIFT (5U)
7511 #define CSL_EVETPCC_IESRH_RN_I37_RESETVAL (0x00000000U)
7512 #define CSL_EVETPCC_IESRH_RN_I37_MAX (0x00000001U)
7514 #define CSL_EVETPCC_IESRH_RN_I49_MASK (0x00020000U)
7515 #define CSL_EVETPCC_IESRH_RN_I49_SHIFT (17U)
7516 #define CSL_EVETPCC_IESRH_RN_I49_RESETVAL (0x00000000U)
7517 #define CSL_EVETPCC_IESRH_RN_I49_MAX (0x00000001U)
7519 #define CSL_EVETPCC_IESRH_RN_I36_MASK (0x00000010U)
7520 #define CSL_EVETPCC_IESRH_RN_I36_SHIFT (4U)
7521 #define CSL_EVETPCC_IESRH_RN_I36_RESETVAL (0x00000000U)
7522 #define CSL_EVETPCC_IESRH_RN_I36_MAX (0x00000001U)
7524 #define CSL_EVETPCC_IESRH_RN_I50_MASK (0x00040000U)
7525 #define CSL_EVETPCC_IESRH_RN_I50_SHIFT (18U)
7526 #define CSL_EVETPCC_IESRH_RN_I50_RESETVAL (0x00000000U)
7527 #define CSL_EVETPCC_IESRH_RN_I50_MAX (0x00000001U)
7529 #define CSL_EVETPCC_IESRH_RN_I39_MASK (0x00000080U)
7530 #define CSL_EVETPCC_IESRH_RN_I39_SHIFT (7U)
7531 #define CSL_EVETPCC_IESRH_RN_I39_RESETVAL (0x00000000U)
7532 #define CSL_EVETPCC_IESRH_RN_I39_MAX (0x00000001U)
7534 #define CSL_EVETPCC_IESRH_RN_I38_MASK (0x00000040U)
7535 #define CSL_EVETPCC_IESRH_RN_I38_SHIFT (6U)
7536 #define CSL_EVETPCC_IESRH_RN_I38_RESETVAL (0x00000000U)
7537 #define CSL_EVETPCC_IESRH_RN_I38_MAX (0x00000001U)
7539 #define CSL_EVETPCC_IESRH_RN_I63_MASK (0x80000000U)
7540 #define CSL_EVETPCC_IESRH_RN_I63_SHIFT (31U)
7541 #define CSL_EVETPCC_IESRH_RN_I63_RESETVAL (0x00000000U)
7542 #define CSL_EVETPCC_IESRH_RN_I63_MAX (0x00000001U)
7544 #define CSL_EVETPCC_IESRH_RN_I62_MASK (0x40000000U)
7545 #define CSL_EVETPCC_IESRH_RN_I62_SHIFT (30U)
7546 #define CSL_EVETPCC_IESRH_RN_I62_RESETVAL (0x00000000U)
7547 #define CSL_EVETPCC_IESRH_RN_I62_MAX (0x00000001U)
7549 #define CSL_EVETPCC_IESRH_RN_I40_MASK (0x00000100U)
7550 #define CSL_EVETPCC_IESRH_RN_I40_SHIFT (8U)
7551 #define CSL_EVETPCC_IESRH_RN_I40_RESETVAL (0x00000000U)
7552 #define CSL_EVETPCC_IESRH_RN_I40_MAX (0x00000001U)
7554 #define CSL_EVETPCC_IESRH_RN_I61_MASK (0x20000000U)
7555 #define CSL_EVETPCC_IESRH_RN_I61_SHIFT (29U)
7556 #define CSL_EVETPCC_IESRH_RN_I61_RESETVAL (0x00000000U)
7557 #define CSL_EVETPCC_IESRH_RN_I61_MAX (0x00000001U)
7559 #define CSL_EVETPCC_IESRH_RN_I51_MASK (0x00080000U)
7560 #define CSL_EVETPCC_IESRH_RN_I51_SHIFT (19U)
7561 #define CSL_EVETPCC_IESRH_RN_I51_RESETVAL (0x00000000U)
7562 #define CSL_EVETPCC_IESRH_RN_I51_MAX (0x00000001U)
7564 #define CSL_EVETPCC_IESRH_RN_RESETVAL (0x00000000U)
7566 /* SER_RN */
7568 #define CSL_EVETPCC_SER_RN_E0_MASK (0x00000001U)
7569 #define CSL_EVETPCC_SER_RN_E0_SHIFT (0U)
7570 #define CSL_EVETPCC_SER_RN_E0_RESETVAL (0x00000000U)
7571 #define CSL_EVETPCC_SER_RN_E0_MAX (0x00000001U)
7573 #define CSL_EVETPCC_SER_RN_E13_MASK (0x00002000U)
7574 #define CSL_EVETPCC_SER_RN_E13_SHIFT (13U)
7575 #define CSL_EVETPCC_SER_RN_E13_RESETVAL (0x00000000U)
7576 #define CSL_EVETPCC_SER_RN_E13_MAX (0x00000001U)
7578 #define CSL_EVETPCC_SER_RN_E21_MASK (0x00200000U)
7579 #define CSL_EVETPCC_SER_RN_E21_SHIFT (21U)
7580 #define CSL_EVETPCC_SER_RN_E21_RESETVAL (0x00000000U)
7581 #define CSL_EVETPCC_SER_RN_E21_MAX (0x00000001U)
7583 #define CSL_EVETPCC_SER_RN_E14_MASK (0x00004000U)
7584 #define CSL_EVETPCC_SER_RN_E14_SHIFT (14U)
7585 #define CSL_EVETPCC_SER_RN_E14_RESETVAL (0x00000000U)
7586 #define CSL_EVETPCC_SER_RN_E14_MAX (0x00000001U)
7588 #define CSL_EVETPCC_SER_RN_E31_MASK (0x80000000U)
7589 #define CSL_EVETPCC_SER_RN_E31_SHIFT (31U)
7590 #define CSL_EVETPCC_SER_RN_E31_RESETVAL (0x00000000U)
7591 #define CSL_EVETPCC_SER_RN_E31_MAX (0x00000001U)
7593 #define CSL_EVETPCC_SER_RN_E1_MASK (0x00000002U)
7594 #define CSL_EVETPCC_SER_RN_E1_SHIFT (1U)
7595 #define CSL_EVETPCC_SER_RN_E1_RESETVAL (0x00000000U)
7596 #define CSL_EVETPCC_SER_RN_E1_MAX (0x00000001U)
7598 #define CSL_EVETPCC_SER_RN_E11_MASK (0x00000800U)
7599 #define CSL_EVETPCC_SER_RN_E11_SHIFT (11U)
7600 #define CSL_EVETPCC_SER_RN_E11_RESETVAL (0x00000000U)
7601 #define CSL_EVETPCC_SER_RN_E11_MAX (0x00000001U)
7603 #define CSL_EVETPCC_SER_RN_E19_MASK (0x00080000U)
7604 #define CSL_EVETPCC_SER_RN_E19_SHIFT (19U)
7605 #define CSL_EVETPCC_SER_RN_E19_RESETVAL (0x00000000U)
7606 #define CSL_EVETPCC_SER_RN_E19_MAX (0x00000001U)
7608 #define CSL_EVETPCC_SER_RN_E20_MASK (0x00100000U)
7609 #define CSL_EVETPCC_SER_RN_E20_SHIFT (20U)
7610 #define CSL_EVETPCC_SER_RN_E20_RESETVAL (0x00000000U)
7611 #define CSL_EVETPCC_SER_RN_E20_MAX (0x00000001U)
7613 #define CSL_EVETPCC_SER_RN_E12_MASK (0x00001000U)
7614 #define CSL_EVETPCC_SER_RN_E12_SHIFT (12U)
7615 #define CSL_EVETPCC_SER_RN_E12_RESETVAL (0x00000000U)
7616 #define CSL_EVETPCC_SER_RN_E12_MAX (0x00000001U)
7618 #define CSL_EVETPCC_SER_RN_E3_MASK (0x00000008U)
7619 #define CSL_EVETPCC_SER_RN_E3_SHIFT (3U)
7620 #define CSL_EVETPCC_SER_RN_E3_RESETVAL (0x00000000U)
7621 #define CSL_EVETPCC_SER_RN_E3_MAX (0x00000001U)
7623 #define CSL_EVETPCC_SER_RN_E4_MASK (0x00000010U)
7624 #define CSL_EVETPCC_SER_RN_E4_SHIFT (4U)
7625 #define CSL_EVETPCC_SER_RN_E4_RESETVAL (0x00000000U)
7626 #define CSL_EVETPCC_SER_RN_E4_MAX (0x00000001U)
7628 #define CSL_EVETPCC_SER_RN_E24_MASK (0x01000000U)
7629 #define CSL_EVETPCC_SER_RN_E24_SHIFT (24U)
7630 #define CSL_EVETPCC_SER_RN_E24_RESETVAL (0x00000000U)
7631 #define CSL_EVETPCC_SER_RN_E24_MAX (0x00000001U)
7633 #define CSL_EVETPCC_SER_RN_E2_MASK (0x00000004U)
7634 #define CSL_EVETPCC_SER_RN_E2_SHIFT (2U)
7635 #define CSL_EVETPCC_SER_RN_E2_RESETVAL (0x00000000U)
7636 #define CSL_EVETPCC_SER_RN_E2_MAX (0x00000001U)
7638 #define CSL_EVETPCC_SER_RN_E22_MASK (0x00400000U)
7639 #define CSL_EVETPCC_SER_RN_E22_SHIFT (22U)
7640 #define CSL_EVETPCC_SER_RN_E22_RESETVAL (0x00000000U)
7641 #define CSL_EVETPCC_SER_RN_E22_MAX (0x00000001U)
7643 #define CSL_EVETPCC_SER_RN_E23_MASK (0x00800000U)
7644 #define CSL_EVETPCC_SER_RN_E23_SHIFT (23U)
7645 #define CSL_EVETPCC_SER_RN_E23_RESETVAL (0x00000000U)
7646 #define CSL_EVETPCC_SER_RN_E23_MAX (0x00000001U)
7648 #define CSL_EVETPCC_SER_RN_E25_MASK (0x02000000U)
7649 #define CSL_EVETPCC_SER_RN_E25_SHIFT (25U)
7650 #define CSL_EVETPCC_SER_RN_E25_RESETVAL (0x00000000U)
7651 #define CSL_EVETPCC_SER_RN_E25_MAX (0x00000001U)
7653 #define CSL_EVETPCC_SER_RN_E26_MASK (0x04000000U)
7654 #define CSL_EVETPCC_SER_RN_E26_SHIFT (26U)
7655 #define CSL_EVETPCC_SER_RN_E26_RESETVAL (0x00000000U)
7656 #define CSL_EVETPCC_SER_RN_E26_MAX (0x00000001U)
7658 #define CSL_EVETPCC_SER_RN_E6_MASK (0x00000040U)
7659 #define CSL_EVETPCC_SER_RN_E6_SHIFT (6U)
7660 #define CSL_EVETPCC_SER_RN_E6_RESETVAL (0x00000000U)
7661 #define CSL_EVETPCC_SER_RN_E6_MAX (0x00000001U)
7663 #define CSL_EVETPCC_SER_RN_E5_MASK (0x00000020U)
7664 #define CSL_EVETPCC_SER_RN_E5_SHIFT (5U)
7665 #define CSL_EVETPCC_SER_RN_E5_RESETVAL (0x00000000U)
7666 #define CSL_EVETPCC_SER_RN_E5_MAX (0x00000001U)
7668 #define CSL_EVETPCC_SER_RN_E8_MASK (0x00000100U)
7669 #define CSL_EVETPCC_SER_RN_E8_SHIFT (8U)
7670 #define CSL_EVETPCC_SER_RN_E8_RESETVAL (0x00000000U)
7671 #define CSL_EVETPCC_SER_RN_E8_MAX (0x00000001U)
7673 #define CSL_EVETPCC_SER_RN_E17_MASK (0x00020000U)
7674 #define CSL_EVETPCC_SER_RN_E17_SHIFT (17U)
7675 #define CSL_EVETPCC_SER_RN_E17_RESETVAL (0x00000000U)
7676 #define CSL_EVETPCC_SER_RN_E17_MAX (0x00000001U)
7678 #define CSL_EVETPCC_SER_RN_E29_MASK (0x20000000U)
7679 #define CSL_EVETPCC_SER_RN_E29_SHIFT (29U)
7680 #define CSL_EVETPCC_SER_RN_E29_RESETVAL (0x00000000U)
7681 #define CSL_EVETPCC_SER_RN_E29_MAX (0x00000001U)
7683 #define CSL_EVETPCC_SER_RN_E18_MASK (0x00040000U)
7684 #define CSL_EVETPCC_SER_RN_E18_SHIFT (18U)
7685 #define CSL_EVETPCC_SER_RN_E18_RESETVAL (0x00000000U)
7686 #define CSL_EVETPCC_SER_RN_E18_MAX (0x00000001U)
7688 #define CSL_EVETPCC_SER_RN_E30_MASK (0x40000000U)
7689 #define CSL_EVETPCC_SER_RN_E30_SHIFT (30U)
7690 #define CSL_EVETPCC_SER_RN_E30_RESETVAL (0x00000000U)
7691 #define CSL_EVETPCC_SER_RN_E30_MAX (0x00000001U)
7693 #define CSL_EVETPCC_SER_RN_E7_MASK (0x00000080U)
7694 #define CSL_EVETPCC_SER_RN_E7_SHIFT (7U)
7695 #define CSL_EVETPCC_SER_RN_E7_RESETVAL (0x00000000U)
7696 #define CSL_EVETPCC_SER_RN_E7_MAX (0x00000001U)
7698 #define CSL_EVETPCC_SER_RN_E10_MASK (0x00000400U)
7699 #define CSL_EVETPCC_SER_RN_E10_SHIFT (10U)
7700 #define CSL_EVETPCC_SER_RN_E10_RESETVAL (0x00000000U)
7701 #define CSL_EVETPCC_SER_RN_E10_MAX (0x00000001U)
7703 #define CSL_EVETPCC_SER_RN_E15_MASK (0x00008000U)
7704 #define CSL_EVETPCC_SER_RN_E15_SHIFT (15U)
7705 #define CSL_EVETPCC_SER_RN_E15_RESETVAL (0x00000000U)
7706 #define CSL_EVETPCC_SER_RN_E15_MAX (0x00000001U)
7708 #define CSL_EVETPCC_SER_RN_E27_MASK (0x08000000U)
7709 #define CSL_EVETPCC_SER_RN_E27_SHIFT (27U)
7710 #define CSL_EVETPCC_SER_RN_E27_RESETVAL (0x00000000U)
7711 #define CSL_EVETPCC_SER_RN_E27_MAX (0x00000001U)
7713 #define CSL_EVETPCC_SER_RN_E9_MASK (0x00000200U)
7714 #define CSL_EVETPCC_SER_RN_E9_SHIFT (9U)
7715 #define CSL_EVETPCC_SER_RN_E9_RESETVAL (0x00000000U)
7716 #define CSL_EVETPCC_SER_RN_E9_MAX (0x00000001U)
7718 #define CSL_EVETPCC_SER_RN_E16_MASK (0x00010000U)
7719 #define CSL_EVETPCC_SER_RN_E16_SHIFT (16U)
7720 #define CSL_EVETPCC_SER_RN_E16_RESETVAL (0x00000000U)
7721 #define CSL_EVETPCC_SER_RN_E16_MAX (0x00000001U)
7723 #define CSL_EVETPCC_SER_RN_E28_MASK (0x10000000U)
7724 #define CSL_EVETPCC_SER_RN_E28_SHIFT (28U)
7725 #define CSL_EVETPCC_SER_RN_E28_RESETVAL (0x00000000U)
7726 #define CSL_EVETPCC_SER_RN_E28_MAX (0x00000001U)
7728 #define CSL_EVETPCC_SER_RN_RESETVAL (0x00000000U)
7730 /* SERH_RN */
7732 #define CSL_EVETPCC_SERH_RN_E53_MASK (0x00200000U)
7733 #define CSL_EVETPCC_SERH_RN_E53_SHIFT (21U)
7734 #define CSL_EVETPCC_SERH_RN_E53_RESETVAL (0x00000000U)
7735 #define CSL_EVETPCC_SERH_RN_E53_MAX (0x00000001U)
7737 #define CSL_EVETPCC_SERH_RN_E42_MASK (0x00000400U)
7738 #define CSL_EVETPCC_SERH_RN_E42_SHIFT (10U)
7739 #define CSL_EVETPCC_SERH_RN_E42_RESETVAL (0x00000000U)
7740 #define CSL_EVETPCC_SERH_RN_E42_MAX (0x00000001U)
7742 #define CSL_EVETPCC_SERH_RN_E52_MASK (0x00100000U)
7743 #define CSL_EVETPCC_SERH_RN_E52_SHIFT (20U)
7744 #define CSL_EVETPCC_SERH_RN_E52_RESETVAL (0x00000000U)
7745 #define CSL_EVETPCC_SERH_RN_E52_MAX (0x00000001U)
7747 #define CSL_EVETPCC_SERH_RN_E43_MASK (0x00000800U)
7748 #define CSL_EVETPCC_SERH_RN_E43_SHIFT (11U)
7749 #define CSL_EVETPCC_SERH_RN_E43_RESETVAL (0x00000000U)
7750 #define CSL_EVETPCC_SERH_RN_E43_MAX (0x00000001U)
7752 #define CSL_EVETPCC_SERH_RN_E32_MASK (0x00000001U)
7753 #define CSL_EVETPCC_SERH_RN_E32_SHIFT (0U)
7754 #define CSL_EVETPCC_SERH_RN_E32_RESETVAL (0x00000000U)
7755 #define CSL_EVETPCC_SERH_RN_E32_MAX (0x00000001U)
7757 #define CSL_EVETPCC_SERH_RN_E44_MASK (0x00001000U)
7758 #define CSL_EVETPCC_SERH_RN_E44_SHIFT (12U)
7759 #define CSL_EVETPCC_SERH_RN_E44_RESETVAL (0x00000000U)
7760 #define CSL_EVETPCC_SERH_RN_E44_MAX (0x00000001U)
7762 #define CSL_EVETPCC_SERH_RN_E55_MASK (0x00800000U)
7763 #define CSL_EVETPCC_SERH_RN_E55_SHIFT (23U)
7764 #define CSL_EVETPCC_SERH_RN_E55_RESETVAL (0x00000000U)
7765 #define CSL_EVETPCC_SERH_RN_E55_MAX (0x00000001U)
7767 #define CSL_EVETPCC_SERH_RN_E45_MASK (0x00002000U)
7768 #define CSL_EVETPCC_SERH_RN_E45_SHIFT (13U)
7769 #define CSL_EVETPCC_SERH_RN_E45_RESETVAL (0x00000000U)
7770 #define CSL_EVETPCC_SERH_RN_E45_MAX (0x00000001U)
7772 #define CSL_EVETPCC_SERH_RN_E54_MASK (0x00400000U)
7773 #define CSL_EVETPCC_SERH_RN_E54_SHIFT (22U)
7774 #define CSL_EVETPCC_SERH_RN_E54_RESETVAL (0x00000000U)
7775 #define CSL_EVETPCC_SERH_RN_E54_MAX (0x00000001U)
7777 #define CSL_EVETPCC_SERH_RN_E46_MASK (0x00004000U)
7778 #define CSL_EVETPCC_SERH_RN_E46_SHIFT (14U)
7779 #define CSL_EVETPCC_SERH_RN_E46_RESETVAL (0x00000000U)
7780 #define CSL_EVETPCC_SERH_RN_E46_MAX (0x00000001U)
7782 #define CSL_EVETPCC_SERH_RN_E56_MASK (0x01000000U)
7783 #define CSL_EVETPCC_SERH_RN_E56_SHIFT (24U)
7784 #define CSL_EVETPCC_SERH_RN_E56_RESETVAL (0x00000000U)
7785 #define CSL_EVETPCC_SERH_RN_E56_MAX (0x00000001U)
7787 #define CSL_EVETPCC_SERH_RN_E58_MASK (0x04000000U)
7788 #define CSL_EVETPCC_SERH_RN_E58_SHIFT (26U)
7789 #define CSL_EVETPCC_SERH_RN_E58_RESETVAL (0x00000000U)
7790 #define CSL_EVETPCC_SERH_RN_E58_MAX (0x00000001U)
7792 #define CSL_EVETPCC_SERH_RN_E57_MASK (0x02000000U)
7793 #define CSL_EVETPCC_SERH_RN_E57_SHIFT (25U)
7794 #define CSL_EVETPCC_SERH_RN_E57_RESETVAL (0x00000000U)
7795 #define CSL_EVETPCC_SERH_RN_E57_MAX (0x00000001U)
7797 #define CSL_EVETPCC_SERH_RN_E60_MASK (0x10000000U)
7798 #define CSL_EVETPCC_SERH_RN_E60_SHIFT (28U)
7799 #define CSL_EVETPCC_SERH_RN_E60_RESETVAL (0x00000000U)
7800 #define CSL_EVETPCC_SERH_RN_E60_MAX (0x00000001U)
7802 #define CSL_EVETPCC_SERH_RN_E59_MASK (0x08000000U)
7803 #define CSL_EVETPCC_SERH_RN_E59_SHIFT (27U)
7804 #define CSL_EVETPCC_SERH_RN_E59_RESETVAL (0x00000000U)
7805 #define CSL_EVETPCC_SERH_RN_E59_MAX (0x00000001U)
7807 #define CSL_EVETPCC_SERH_RN_E61_MASK (0x20000000U)
7808 #define CSL_EVETPCC_SERH_RN_E61_SHIFT (29U)
7809 #define CSL_EVETPCC_SERH_RN_E61_RESETVAL (0x00000000U)
7810 #define CSL_EVETPCC_SERH_RN_E61_MAX (0x00000001U)
7812 #define CSL_EVETPCC_SERH_RN_E37_MASK (0x00000020U)
7813 #define CSL_EVETPCC_SERH_RN_E37_SHIFT (5U)
7814 #define CSL_EVETPCC_SERH_RN_E37_RESETVAL (0x00000000U)
7815 #define CSL_EVETPCC_SERH_RN_E37_MAX (0x00000001U)
7817 #define CSL_EVETPCC_SERH_RN_E47_MASK (0x00008000U)
7818 #define CSL_EVETPCC_SERH_RN_E47_SHIFT (15U)
7819 #define CSL_EVETPCC_SERH_RN_E47_RESETVAL (0x00000000U)
7820 #define CSL_EVETPCC_SERH_RN_E47_MAX (0x00000001U)
7822 #define CSL_EVETPCC_SERH_RN_E38_MASK (0x00000040U)
7823 #define CSL_EVETPCC_SERH_RN_E38_SHIFT (6U)
7824 #define CSL_EVETPCC_SERH_RN_E38_RESETVAL (0x00000000U)
7825 #define CSL_EVETPCC_SERH_RN_E38_MAX (0x00000001U)
7827 #define CSL_EVETPCC_SERH_RN_E35_MASK (0x00000008U)
7828 #define CSL_EVETPCC_SERH_RN_E35_SHIFT (3U)
7829 #define CSL_EVETPCC_SERH_RN_E35_RESETVAL (0x00000000U)
7830 #define CSL_EVETPCC_SERH_RN_E35_MAX (0x00000001U)
7832 #define CSL_EVETPCC_SERH_RN_E48_MASK (0x00010000U)
7833 #define CSL_EVETPCC_SERH_RN_E48_SHIFT (16U)
7834 #define CSL_EVETPCC_SERH_RN_E48_RESETVAL (0x00000000U)
7835 #define CSL_EVETPCC_SERH_RN_E48_MAX (0x00000001U)
7837 #define CSL_EVETPCC_SERH_RN_E62_MASK (0x40000000U)
7838 #define CSL_EVETPCC_SERH_RN_E62_SHIFT (30U)
7839 #define CSL_EVETPCC_SERH_RN_E62_RESETVAL (0x00000000U)
7840 #define CSL_EVETPCC_SERH_RN_E62_MAX (0x00000001U)
7842 #define CSL_EVETPCC_SERH_RN_E39_MASK (0x00000080U)
7843 #define CSL_EVETPCC_SERH_RN_E39_SHIFT (7U)
7844 #define CSL_EVETPCC_SERH_RN_E39_RESETVAL (0x00000000U)
7845 #define CSL_EVETPCC_SERH_RN_E39_MAX (0x00000001U)
7847 #define CSL_EVETPCC_SERH_RN_E63_MASK (0x80000000U)
7848 #define CSL_EVETPCC_SERH_RN_E63_SHIFT (31U)
7849 #define CSL_EVETPCC_SERH_RN_E63_RESETVAL (0x00000000U)
7850 #define CSL_EVETPCC_SERH_RN_E63_MAX (0x00000001U)
7852 #define CSL_EVETPCC_SERH_RN_E36_MASK (0x00000010U)
7853 #define CSL_EVETPCC_SERH_RN_E36_SHIFT (4U)
7854 #define CSL_EVETPCC_SERH_RN_E36_RESETVAL (0x00000000U)
7855 #define CSL_EVETPCC_SERH_RN_E36_MAX (0x00000001U)
7857 #define CSL_EVETPCC_SERH_RN_E49_MASK (0x00020000U)
7858 #define CSL_EVETPCC_SERH_RN_E49_SHIFT (17U)
7859 #define CSL_EVETPCC_SERH_RN_E49_RESETVAL (0x00000000U)
7860 #define CSL_EVETPCC_SERH_RN_E49_MAX (0x00000001U)
7862 #define CSL_EVETPCC_SERH_RN_E40_MASK (0x00000100U)
7863 #define CSL_EVETPCC_SERH_RN_E40_SHIFT (8U)
7864 #define CSL_EVETPCC_SERH_RN_E40_RESETVAL (0x00000000U)
7865 #define CSL_EVETPCC_SERH_RN_E40_MAX (0x00000001U)
7867 #define CSL_EVETPCC_SERH_RN_E33_MASK (0x00000002U)
7868 #define CSL_EVETPCC_SERH_RN_E33_SHIFT (1U)
7869 #define CSL_EVETPCC_SERH_RN_E33_RESETVAL (0x00000000U)
7870 #define CSL_EVETPCC_SERH_RN_E33_MAX (0x00000001U)
7872 #define CSL_EVETPCC_SERH_RN_E50_MASK (0x00040000U)
7873 #define CSL_EVETPCC_SERH_RN_E50_SHIFT (18U)
7874 #define CSL_EVETPCC_SERH_RN_E50_RESETVAL (0x00000000U)
7875 #define CSL_EVETPCC_SERH_RN_E50_MAX (0x00000001U)
7877 #define CSL_EVETPCC_SERH_RN_E41_MASK (0x00000200U)
7878 #define CSL_EVETPCC_SERH_RN_E41_SHIFT (9U)
7879 #define CSL_EVETPCC_SERH_RN_E41_RESETVAL (0x00000000U)
7880 #define CSL_EVETPCC_SERH_RN_E41_MAX (0x00000001U)
7882 #define CSL_EVETPCC_SERH_RN_E34_MASK (0x00000004U)
7883 #define CSL_EVETPCC_SERH_RN_E34_SHIFT (2U)
7884 #define CSL_EVETPCC_SERH_RN_E34_RESETVAL (0x00000000U)
7885 #define CSL_EVETPCC_SERH_RN_E34_MAX (0x00000001U)
7887 #define CSL_EVETPCC_SERH_RN_E51_MASK (0x00080000U)
7888 #define CSL_EVETPCC_SERH_RN_E51_SHIFT (19U)
7889 #define CSL_EVETPCC_SERH_RN_E51_RESETVAL (0x00000000U)
7890 #define CSL_EVETPCC_SERH_RN_E51_MAX (0x00000001U)
7892 #define CSL_EVETPCC_SERH_RN_RESETVAL (0x00000000U)
7894 /* ESR_RN */
7896 #define CSL_EVETPCC_ESR_RN_E3_MASK (0x00000008U)
7897 #define CSL_EVETPCC_ESR_RN_E3_SHIFT (3U)
7898 #define CSL_EVETPCC_ESR_RN_E3_RESETVAL (0x00000000U)
7899 #define CSL_EVETPCC_ESR_RN_E3_MAX (0x00000001U)
7901 #define CSL_EVETPCC_ESR_RN_E6_MASK (0x00000040U)
7902 #define CSL_EVETPCC_ESR_RN_E6_SHIFT (6U)
7903 #define CSL_EVETPCC_ESR_RN_E6_RESETVAL (0x00000000U)
7904 #define CSL_EVETPCC_ESR_RN_E6_MAX (0x00000001U)
7906 #define CSL_EVETPCC_ESR_RN_E20_MASK (0x00100000U)
7907 #define CSL_EVETPCC_ESR_RN_E20_SHIFT (20U)
7908 #define CSL_EVETPCC_ESR_RN_E20_RESETVAL (0x00000000U)
7909 #define CSL_EVETPCC_ESR_RN_E20_MAX (0x00000001U)
7911 #define CSL_EVETPCC_ESR_RN_E1_MASK (0x00000002U)
7912 #define CSL_EVETPCC_ESR_RN_E1_SHIFT (1U)
7913 #define CSL_EVETPCC_ESR_RN_E1_RESETVAL (0x00000000U)
7914 #define CSL_EVETPCC_ESR_RN_E1_MAX (0x00000001U)
7916 #define CSL_EVETPCC_ESR_RN_E4_MASK (0x00000010U)
7917 #define CSL_EVETPCC_ESR_RN_E4_SHIFT (4U)
7918 #define CSL_EVETPCC_ESR_RN_E4_RESETVAL (0x00000000U)
7919 #define CSL_EVETPCC_ESR_RN_E4_MAX (0x00000001U)
7921 #define CSL_EVETPCC_ESR_RN_E18_MASK (0x00040000U)
7922 #define CSL_EVETPCC_ESR_RN_E18_SHIFT (18U)
7923 #define CSL_EVETPCC_ESR_RN_E18_RESETVAL (0x00000000U)
7924 #define CSL_EVETPCC_ESR_RN_E18_MAX (0x00000001U)
7926 #define CSL_EVETPCC_ESR_RN_E7_MASK (0x00000080U)
7927 #define CSL_EVETPCC_ESR_RN_E7_SHIFT (7U)
7928 #define CSL_EVETPCC_ESR_RN_E7_RESETVAL (0x00000000U)
7929 #define CSL_EVETPCC_ESR_RN_E7_MAX (0x00000001U)
7931 #define CSL_EVETPCC_ESR_RN_E11_MASK (0x00000800U)
7932 #define CSL_EVETPCC_ESR_RN_E11_SHIFT (11U)
7933 #define CSL_EVETPCC_ESR_RN_E11_RESETVAL (0x00000000U)
7934 #define CSL_EVETPCC_ESR_RN_E11_MAX (0x00000001U)
7936 #define CSL_EVETPCC_ESR_RN_E10_MASK (0x00000400U)
7937 #define CSL_EVETPCC_ESR_RN_E10_SHIFT (10U)
7938 #define CSL_EVETPCC_ESR_RN_E10_RESETVAL (0x00000000U)
7939 #define CSL_EVETPCC_ESR_RN_E10_MAX (0x00000001U)
7941 #define CSL_EVETPCC_ESR_RN_E5_MASK (0x00000020U)
7942 #define CSL_EVETPCC_ESR_RN_E5_SHIFT (5U)
7943 #define CSL_EVETPCC_ESR_RN_E5_RESETVAL (0x00000000U)
7944 #define CSL_EVETPCC_ESR_RN_E5_MAX (0x00000001U)
7946 #define CSL_EVETPCC_ESR_RN_E8_MASK (0x00000100U)
7947 #define CSL_EVETPCC_ESR_RN_E8_SHIFT (8U)
7948 #define CSL_EVETPCC_ESR_RN_E8_RESETVAL (0x00000000U)
7949 #define CSL_EVETPCC_ESR_RN_E8_MAX (0x00000001U)
7951 #define CSL_EVETPCC_ESR_RN_E22_MASK (0x00400000U)
7952 #define CSL_EVETPCC_ESR_RN_E22_SHIFT (22U)
7953 #define CSL_EVETPCC_ESR_RN_E22_RESETVAL (0x00000000U)
7954 #define CSL_EVETPCC_ESR_RN_E22_MAX (0x00000001U)
7956 #define CSL_EVETPCC_ESR_RN_E21_MASK (0x00200000U)
7957 #define CSL_EVETPCC_ESR_RN_E21_SHIFT (21U)
7958 #define CSL_EVETPCC_ESR_RN_E21_RESETVAL (0x00000000U)
7959 #define CSL_EVETPCC_ESR_RN_E21_MAX (0x00000001U)
7961 #define CSL_EVETPCC_ESR_RN_E23_MASK (0x00800000U)
7962 #define CSL_EVETPCC_ESR_RN_E23_SHIFT (23U)
7963 #define CSL_EVETPCC_ESR_RN_E23_RESETVAL (0x00000000U)
7964 #define CSL_EVETPCC_ESR_RN_E23_MAX (0x00000001U)
7966 #define CSL_EVETPCC_ESR_RN_E31_MASK (0x80000000U)
7967 #define CSL_EVETPCC_ESR_RN_E31_SHIFT (31U)
7968 #define CSL_EVETPCC_ESR_RN_E31_RESETVAL (0x00000000U)
7969 #define CSL_EVETPCC_ESR_RN_E31_MAX (0x00000001U)
7971 #define CSL_EVETPCC_ESR_RN_E15_MASK (0x00008000U)
7972 #define CSL_EVETPCC_ESR_RN_E15_SHIFT (15U)
7973 #define CSL_EVETPCC_ESR_RN_E15_RESETVAL (0x00000000U)
7974 #define CSL_EVETPCC_ESR_RN_E15_MAX (0x00000001U)
7976 #define CSL_EVETPCC_ESR_RN_E26_MASK (0x04000000U)
7977 #define CSL_EVETPCC_ESR_RN_E26_SHIFT (26U)
7978 #define CSL_EVETPCC_ESR_RN_E26_RESETVAL (0x00000000U)
7979 #define CSL_EVETPCC_ESR_RN_E26_MAX (0x00000001U)
7981 #define CSL_EVETPCC_ESR_RN_E24_MASK (0x01000000U)
7982 #define CSL_EVETPCC_ESR_RN_E24_SHIFT (24U)
7983 #define CSL_EVETPCC_ESR_RN_E24_RESETVAL (0x00000000U)
7984 #define CSL_EVETPCC_ESR_RN_E24_MAX (0x00000001U)
7986 #define CSL_EVETPCC_ESR_RN_E12_MASK (0x00001000U)
7987 #define CSL_EVETPCC_ESR_RN_E12_SHIFT (12U)
7988 #define CSL_EVETPCC_ESR_RN_E12_RESETVAL (0x00000000U)
7989 #define CSL_EVETPCC_ESR_RN_E12_MAX (0x00000001U)
7991 #define CSL_EVETPCC_ESR_RN_E13_MASK (0x00002000U)
7992 #define CSL_EVETPCC_ESR_RN_E13_SHIFT (13U)
7993 #define CSL_EVETPCC_ESR_RN_E13_RESETVAL (0x00000000U)
7994 #define CSL_EVETPCC_ESR_RN_E13_MAX (0x00000001U)
7996 #define CSL_EVETPCC_ESR_RN_E9_MASK (0x00000200U)
7997 #define CSL_EVETPCC_ESR_RN_E9_SHIFT (9U)
7998 #define CSL_EVETPCC_ESR_RN_E9_RESETVAL (0x00000000U)
7999 #define CSL_EVETPCC_ESR_RN_E9_MAX (0x00000001U)
8001 #define CSL_EVETPCC_ESR_RN_E28_MASK (0x10000000U)
8002 #define CSL_EVETPCC_ESR_RN_E28_SHIFT (28U)
8003 #define CSL_EVETPCC_ESR_RN_E28_RESETVAL (0x00000000U)
8004 #define CSL_EVETPCC_ESR_RN_E28_MAX (0x00000001U)
8006 #define CSL_EVETPCC_ESR_RN_E25_MASK (0x02000000U)
8007 #define CSL_EVETPCC_ESR_RN_E25_SHIFT (25U)
8008 #define CSL_EVETPCC_ESR_RN_E25_RESETVAL (0x00000000U)
8009 #define CSL_EVETPCC_ESR_RN_E25_MAX (0x00000001U)
8011 #define CSL_EVETPCC_ESR_RN_E0_MASK (0x00000001U)
8012 #define CSL_EVETPCC_ESR_RN_E0_SHIFT (0U)
8013 #define CSL_EVETPCC_ESR_RN_E0_RESETVAL (0x00000000U)
8014 #define CSL_EVETPCC_ESR_RN_E0_MAX (0x00000001U)
8016 #define CSL_EVETPCC_ESR_RN_E19_MASK (0x00080000U)
8017 #define CSL_EVETPCC_ESR_RN_E19_SHIFT (19U)
8018 #define CSL_EVETPCC_ESR_RN_E19_RESETVAL (0x00000000U)
8019 #define CSL_EVETPCC_ESR_RN_E19_MAX (0x00000001U)
8021 #define CSL_EVETPCC_ESR_RN_E16_MASK (0x00010000U)
8022 #define CSL_EVETPCC_ESR_RN_E16_SHIFT (16U)
8023 #define CSL_EVETPCC_ESR_RN_E16_RESETVAL (0x00000000U)
8024 #define CSL_EVETPCC_ESR_RN_E16_MAX (0x00000001U)
8026 #define CSL_EVETPCC_ESR_RN_E2_MASK (0x00000004U)
8027 #define CSL_EVETPCC_ESR_RN_E2_SHIFT (2U)
8028 #define CSL_EVETPCC_ESR_RN_E2_RESETVAL (0x00000000U)
8029 #define CSL_EVETPCC_ESR_RN_E2_MAX (0x00000001U)
8031 #define CSL_EVETPCC_ESR_RN_E27_MASK (0x08000000U)
8032 #define CSL_EVETPCC_ESR_RN_E27_SHIFT (27U)
8033 #define CSL_EVETPCC_ESR_RN_E27_RESETVAL (0x00000000U)
8034 #define CSL_EVETPCC_ESR_RN_E27_MAX (0x00000001U)
8036 #define CSL_EVETPCC_ESR_RN_E17_MASK (0x00020000U)
8037 #define CSL_EVETPCC_ESR_RN_E17_SHIFT (17U)
8038 #define CSL_EVETPCC_ESR_RN_E17_RESETVAL (0x00000000U)
8039 #define CSL_EVETPCC_ESR_RN_E17_MAX (0x00000001U)
8041 #define CSL_EVETPCC_ESR_RN_E30_MASK (0x40000000U)
8042 #define CSL_EVETPCC_ESR_RN_E30_SHIFT (30U)
8043 #define CSL_EVETPCC_ESR_RN_E30_RESETVAL (0x00000000U)
8044 #define CSL_EVETPCC_ESR_RN_E30_MAX (0x00000001U)
8046 #define CSL_EVETPCC_ESR_RN_E14_MASK (0x00004000U)
8047 #define CSL_EVETPCC_ESR_RN_E14_SHIFT (14U)
8048 #define CSL_EVETPCC_ESR_RN_E14_RESETVAL (0x00000000U)
8049 #define CSL_EVETPCC_ESR_RN_E14_MAX (0x00000001U)
8051 #define CSL_EVETPCC_ESR_RN_E29_MASK (0x20000000U)
8052 #define CSL_EVETPCC_ESR_RN_E29_SHIFT (29U)
8053 #define CSL_EVETPCC_ESR_RN_E29_RESETVAL (0x00000000U)
8054 #define CSL_EVETPCC_ESR_RN_E29_MAX (0x00000001U)
8056 #define CSL_EVETPCC_ESR_RN_RESETVAL (0x00000000U)
8058 /* EECR_RN */
8060 #define CSL_EVETPCC_EECR_RN_E30_MASK (0x40000000U)
8061 #define CSL_EVETPCC_EECR_RN_E30_SHIFT (30U)
8062 #define CSL_EVETPCC_EECR_RN_E30_RESETVAL (0x00000000U)
8063 #define CSL_EVETPCC_EECR_RN_E30_MAX (0x00000001U)
8065 #define CSL_EVETPCC_EECR_RN_E25_MASK (0x02000000U)
8066 #define CSL_EVETPCC_EECR_RN_E25_SHIFT (25U)
8067 #define CSL_EVETPCC_EECR_RN_E25_RESETVAL (0x00000000U)
8068 #define CSL_EVETPCC_EECR_RN_E25_MAX (0x00000001U)
8070 #define CSL_EVETPCC_EECR_RN_E14_MASK (0x00004000U)
8071 #define CSL_EVETPCC_EECR_RN_E14_SHIFT (14U)
8072 #define CSL_EVETPCC_EECR_RN_E14_RESETVAL (0x00000000U)
8073 #define CSL_EVETPCC_EECR_RN_E14_MAX (0x00000001U)
8075 #define CSL_EVETPCC_EECR_RN_E15_MASK (0x00008000U)
8076 #define CSL_EVETPCC_EECR_RN_E15_SHIFT (15U)
8077 #define CSL_EVETPCC_EECR_RN_E15_RESETVAL (0x00000000U)
8078 #define CSL_EVETPCC_EECR_RN_E15_MAX (0x00000001U)
8080 #define CSL_EVETPCC_EECR_RN_E5_MASK (0x00000020U)
8081 #define CSL_EVETPCC_EECR_RN_E5_SHIFT (5U)
8082 #define CSL_EVETPCC_EECR_RN_E5_RESETVAL (0x00000000U)
8083 #define CSL_EVETPCC_EECR_RN_E5_MAX (0x00000001U)
8085 #define CSL_EVETPCC_EECR_RN_E31_MASK (0x80000000U)
8086 #define CSL_EVETPCC_EECR_RN_E31_SHIFT (31U)
8087 #define CSL_EVETPCC_EECR_RN_E31_RESETVAL (0x00000000U)
8088 #define CSL_EVETPCC_EECR_RN_E31_MAX (0x00000001U)
8090 #define CSL_EVETPCC_EECR_RN_E24_MASK (0x01000000U)
8091 #define CSL_EVETPCC_EECR_RN_E24_SHIFT (24U)
8092 #define CSL_EVETPCC_EECR_RN_E24_RESETVAL (0x00000000U)
8093 #define CSL_EVETPCC_EECR_RN_E24_MAX (0x00000001U)
8095 #define CSL_EVETPCC_EECR_RN_E28_MASK (0x10000000U)
8096 #define CSL_EVETPCC_EECR_RN_E28_SHIFT (28U)
8097 #define CSL_EVETPCC_EECR_RN_E28_RESETVAL (0x00000000U)
8098 #define CSL_EVETPCC_EECR_RN_E28_MAX (0x00000001U)
8100 #define CSL_EVETPCC_EECR_RN_E6_MASK (0x00000040U)
8101 #define CSL_EVETPCC_EECR_RN_E6_SHIFT (6U)
8102 #define CSL_EVETPCC_EECR_RN_E6_RESETVAL (0x00000000U)
8103 #define CSL_EVETPCC_EECR_RN_E6_MAX (0x00000001U)
8105 #define CSL_EVETPCC_EECR_RN_E16_MASK (0x00010000U)
8106 #define CSL_EVETPCC_EECR_RN_E16_SHIFT (16U)
8107 #define CSL_EVETPCC_EECR_RN_E16_RESETVAL (0x00000000U)
8108 #define CSL_EVETPCC_EECR_RN_E16_MAX (0x00000001U)
8110 #define CSL_EVETPCC_EECR_RN_E29_MASK (0x20000000U)
8111 #define CSL_EVETPCC_EECR_RN_E29_SHIFT (29U)
8112 #define CSL_EVETPCC_EECR_RN_E29_RESETVAL (0x00000000U)
8113 #define CSL_EVETPCC_EECR_RN_E29_MAX (0x00000001U)
8115 #define CSL_EVETPCC_EECR_RN_E26_MASK (0x04000000U)
8116 #define CSL_EVETPCC_EECR_RN_E26_SHIFT (26U)
8117 #define CSL_EVETPCC_EECR_RN_E26_RESETVAL (0x00000000U)
8118 #define CSL_EVETPCC_EECR_RN_E26_MAX (0x00000001U)
8120 #define CSL_EVETPCC_EECR_RN_E8_MASK (0x00000100U)
8121 #define CSL_EVETPCC_EECR_RN_E8_SHIFT (8U)
8122 #define CSL_EVETPCC_EECR_RN_E8_RESETVAL (0x00000000U)
8123 #define CSL_EVETPCC_EECR_RN_E8_MAX (0x00000001U)
8125 #define CSL_EVETPCC_EECR_RN_E18_MASK (0x00040000U)
8126 #define CSL_EVETPCC_EECR_RN_E18_SHIFT (18U)
8127 #define CSL_EVETPCC_EECR_RN_E18_RESETVAL (0x00000000U)
8128 #define CSL_EVETPCC_EECR_RN_E18_MAX (0x00000001U)
8130 #define CSL_EVETPCC_EECR_RN_E7_MASK (0x00000080U)
8131 #define CSL_EVETPCC_EECR_RN_E7_SHIFT (7U)
8132 #define CSL_EVETPCC_EECR_RN_E7_RESETVAL (0x00000000U)
8133 #define CSL_EVETPCC_EECR_RN_E7_MAX (0x00000001U)
8135 #define CSL_EVETPCC_EECR_RN_E17_MASK (0x00020000U)
8136 #define CSL_EVETPCC_EECR_RN_E17_SHIFT (17U)
8137 #define CSL_EVETPCC_EECR_RN_E17_RESETVAL (0x00000000U)
8138 #define CSL_EVETPCC_EECR_RN_E17_MAX (0x00000001U)
8140 #define CSL_EVETPCC_EECR_RN_E10_MASK (0x00000400U)
8141 #define CSL_EVETPCC_EECR_RN_E10_SHIFT (10U)
8142 #define CSL_EVETPCC_EECR_RN_E10_RESETVAL (0x00000000U)
8143 #define CSL_EVETPCC_EECR_RN_E10_MAX (0x00000001U)
8145 #define CSL_EVETPCC_EECR_RN_E20_MASK (0x00100000U)
8146 #define CSL_EVETPCC_EECR_RN_E20_SHIFT (20U)
8147 #define CSL_EVETPCC_EECR_RN_E20_RESETVAL (0x00000000U)
8148 #define CSL_EVETPCC_EECR_RN_E20_MAX (0x00000001U)
8150 #define CSL_EVETPCC_EECR_RN_E9_MASK (0x00000200U)
8151 #define CSL_EVETPCC_EECR_RN_E9_SHIFT (9U)
8152 #define CSL_EVETPCC_EECR_RN_E9_RESETVAL (0x00000000U)
8153 #define CSL_EVETPCC_EECR_RN_E9_MAX (0x00000001U)
8155 #define CSL_EVETPCC_EECR_RN_E0_MASK (0x00000001U)
8156 #define CSL_EVETPCC_EECR_RN_E0_SHIFT (0U)
8157 #define CSL_EVETPCC_EECR_RN_E0_RESETVAL (0x00000000U)
8158 #define CSL_EVETPCC_EECR_RN_E0_MAX (0x00000001U)
8160 #define CSL_EVETPCC_EECR_RN_E19_MASK (0x00080000U)
8161 #define CSL_EVETPCC_EECR_RN_E19_SHIFT (19U)
8162 #define CSL_EVETPCC_EECR_RN_E19_RESETVAL (0x00000000U)
8163 #define CSL_EVETPCC_EECR_RN_E19_MAX (0x00000001U)
8165 #define CSL_EVETPCC_EECR_RN_E1_MASK (0x00000002U)
8166 #define CSL_EVETPCC_EECR_RN_E1_SHIFT (1U)
8167 #define CSL_EVETPCC_EECR_RN_E1_RESETVAL (0x00000000U)
8168 #define CSL_EVETPCC_EECR_RN_E1_MAX (0x00000001U)
8170 #define CSL_EVETPCC_EECR_RN_E12_MASK (0x00001000U)
8171 #define CSL_EVETPCC_EECR_RN_E12_SHIFT (12U)
8172 #define CSL_EVETPCC_EECR_RN_E12_RESETVAL (0x00000000U)
8173 #define CSL_EVETPCC_EECR_RN_E12_MAX (0x00000001U)
8175 #define CSL_EVETPCC_EECR_RN_E22_MASK (0x00400000U)
8176 #define CSL_EVETPCC_EECR_RN_E22_SHIFT (22U)
8177 #define CSL_EVETPCC_EECR_RN_E22_RESETVAL (0x00000000U)
8178 #define CSL_EVETPCC_EECR_RN_E22_MAX (0x00000001U)
8180 #define CSL_EVETPCC_EECR_RN_E2_MASK (0x00000004U)
8181 #define CSL_EVETPCC_EECR_RN_E2_SHIFT (2U)
8182 #define CSL_EVETPCC_EECR_RN_E2_RESETVAL (0x00000000U)
8183 #define CSL_EVETPCC_EECR_RN_E2_MAX (0x00000001U)
8185 #define CSL_EVETPCC_EECR_RN_E11_MASK (0x00000800U)
8186 #define CSL_EVETPCC_EECR_RN_E11_SHIFT (11U)
8187 #define CSL_EVETPCC_EECR_RN_E11_RESETVAL (0x00000000U)
8188 #define CSL_EVETPCC_EECR_RN_E11_MAX (0x00000001U)
8190 #define CSL_EVETPCC_EECR_RN_E21_MASK (0x00200000U)
8191 #define CSL_EVETPCC_EECR_RN_E21_SHIFT (21U)
8192 #define CSL_EVETPCC_EECR_RN_E21_RESETVAL (0x00000000U)
8193 #define CSL_EVETPCC_EECR_RN_E21_MAX (0x00000001U)
8195 #define CSL_EVETPCC_EECR_RN_E27_MASK (0x08000000U)
8196 #define CSL_EVETPCC_EECR_RN_E27_SHIFT (27U)
8197 #define CSL_EVETPCC_EECR_RN_E27_RESETVAL (0x00000000U)
8198 #define CSL_EVETPCC_EECR_RN_E27_MAX (0x00000001U)
8200 #define CSL_EVETPCC_EECR_RN_E3_MASK (0x00000008U)
8201 #define CSL_EVETPCC_EECR_RN_E3_SHIFT (3U)
8202 #define CSL_EVETPCC_EECR_RN_E3_RESETVAL (0x00000000U)
8203 #define CSL_EVETPCC_EECR_RN_E3_MAX (0x00000001U)
8205 #define CSL_EVETPCC_EECR_RN_E23_MASK (0x00800000U)
8206 #define CSL_EVETPCC_EECR_RN_E23_SHIFT (23U)
8207 #define CSL_EVETPCC_EECR_RN_E23_RESETVAL (0x00000000U)
8208 #define CSL_EVETPCC_EECR_RN_E23_MAX (0x00000001U)
8210 #define CSL_EVETPCC_EECR_RN_E4_MASK (0x00000010U)
8211 #define CSL_EVETPCC_EECR_RN_E4_SHIFT (4U)
8212 #define CSL_EVETPCC_EECR_RN_E4_RESETVAL (0x00000000U)
8213 #define CSL_EVETPCC_EECR_RN_E4_MAX (0x00000001U)
8215 #define CSL_EVETPCC_EECR_RN_E13_MASK (0x00002000U)
8216 #define CSL_EVETPCC_EECR_RN_E13_SHIFT (13U)
8217 #define CSL_EVETPCC_EECR_RN_E13_RESETVAL (0x00000000U)
8218 #define CSL_EVETPCC_EECR_RN_E13_MAX (0x00000001U)
8220 #define CSL_EVETPCC_EECR_RN_RESETVAL (0x00000000U)
8222 /* ER_RN */
8224 #define CSL_EVETPCC_ER_RN_E22_MASK (0x00400000U)
8225 #define CSL_EVETPCC_ER_RN_E22_SHIFT (22U)
8226 #define CSL_EVETPCC_ER_RN_E22_RESETVAL (0x00000000U)
8227 #define CSL_EVETPCC_ER_RN_E22_MAX (0x00000001U)
8229 #define CSL_EVETPCC_ER_RN_E2_MASK (0x00000004U)
8230 #define CSL_EVETPCC_ER_RN_E2_SHIFT (2U)
8231 #define CSL_EVETPCC_ER_RN_E2_RESETVAL (0x00000000U)
8232 #define CSL_EVETPCC_ER_RN_E2_MAX (0x00000001U)
8234 #define CSL_EVETPCC_ER_RN_E19_MASK (0x00080000U)
8235 #define CSL_EVETPCC_ER_RN_E19_SHIFT (19U)
8236 #define CSL_EVETPCC_ER_RN_E19_RESETVAL (0x00000000U)
8237 #define CSL_EVETPCC_ER_RN_E19_MAX (0x00000001U)
8239 #define CSL_EVETPCC_ER_RN_E5_MASK (0x00000020U)
8240 #define CSL_EVETPCC_ER_RN_E5_SHIFT (5U)
8241 #define CSL_EVETPCC_ER_RN_E5_RESETVAL (0x00000000U)
8242 #define CSL_EVETPCC_ER_RN_E5_MAX (0x00000001U)
8244 #define CSL_EVETPCC_ER_RN_E29_MASK (0x20000000U)
8245 #define CSL_EVETPCC_ER_RN_E29_SHIFT (29U)
8246 #define CSL_EVETPCC_ER_RN_E29_RESETVAL (0x00000000U)
8247 #define CSL_EVETPCC_ER_RN_E29_MAX (0x00000001U)
8249 #define CSL_EVETPCC_ER_RN_E18_MASK (0x00040000U)
8250 #define CSL_EVETPCC_ER_RN_E18_SHIFT (18U)
8251 #define CSL_EVETPCC_ER_RN_E18_RESETVAL (0x00000000U)
8252 #define CSL_EVETPCC_ER_RN_E18_MAX (0x00000001U)
8254 #define CSL_EVETPCC_ER_RN_E6_MASK (0x00000040U)
8255 #define CSL_EVETPCC_ER_RN_E6_SHIFT (6U)
8256 #define CSL_EVETPCC_ER_RN_E6_RESETVAL (0x00000000U)
8257 #define CSL_EVETPCC_ER_RN_E6_MAX (0x00000001U)
8259 #define CSL_EVETPCC_ER_RN_E21_MASK (0x00200000U)
8260 #define CSL_EVETPCC_ER_RN_E21_SHIFT (21U)
8261 #define CSL_EVETPCC_ER_RN_E21_RESETVAL (0x00000000U)
8262 #define CSL_EVETPCC_ER_RN_E21_MAX (0x00000001U)
8264 #define CSL_EVETPCC_ER_RN_E3_MASK (0x00000008U)
8265 #define CSL_EVETPCC_ER_RN_E3_SHIFT (3U)
8266 #define CSL_EVETPCC_ER_RN_E3_RESETVAL (0x00000000U)
8267 #define CSL_EVETPCC_ER_RN_E3_MAX (0x00000001U)
8269 #define CSL_EVETPCC_ER_RN_E31_MASK (0x80000000U)
8270 #define CSL_EVETPCC_ER_RN_E31_SHIFT (31U)
8271 #define CSL_EVETPCC_ER_RN_E31_RESETVAL (0x00000000U)
8272 #define CSL_EVETPCC_ER_RN_E31_MAX (0x00000001U)
8274 #define CSL_EVETPCC_ER_RN_E20_MASK (0x00100000U)
8275 #define CSL_EVETPCC_ER_RN_E20_SHIFT (20U)
8276 #define CSL_EVETPCC_ER_RN_E20_RESETVAL (0x00000000U)
8277 #define CSL_EVETPCC_ER_RN_E20_MAX (0x00000001U)
8279 #define CSL_EVETPCC_ER_RN_E4_MASK (0x00000010U)
8280 #define CSL_EVETPCC_ER_RN_E4_SHIFT (4U)
8281 #define CSL_EVETPCC_ER_RN_E4_RESETVAL (0x00000000U)
8282 #define CSL_EVETPCC_ER_RN_E4_MAX (0x00000001U)
8284 #define CSL_EVETPCC_ER_RN_E9_MASK (0x00000200U)
8285 #define CSL_EVETPCC_ER_RN_E9_SHIFT (9U)
8286 #define CSL_EVETPCC_ER_RN_E9_RESETVAL (0x00000000U)
8287 #define CSL_EVETPCC_ER_RN_E9_MAX (0x00000001U)
8289 #define CSL_EVETPCC_ER_RN_E28_MASK (0x10000000U)
8290 #define CSL_EVETPCC_ER_RN_E28_SHIFT (28U)
8291 #define CSL_EVETPCC_ER_RN_E28_RESETVAL (0x00000000U)
8292 #define CSL_EVETPCC_ER_RN_E28_MAX (0x00000001U)
8294 #define CSL_EVETPCC_ER_RN_E14_MASK (0x00004000U)
8295 #define CSL_EVETPCC_ER_RN_E14_SHIFT (14U)
8296 #define CSL_EVETPCC_ER_RN_E14_RESETVAL (0x00000000U)
8297 #define CSL_EVETPCC_ER_RN_E14_MAX (0x00000001U)
8299 #define CSL_EVETPCC_ER_RN_E10_MASK (0x00000400U)
8300 #define CSL_EVETPCC_ER_RN_E10_SHIFT (10U)
8301 #define CSL_EVETPCC_ER_RN_E10_RESETVAL (0x00000000U)
8302 #define CSL_EVETPCC_ER_RN_E10_MAX (0x00000001U)
8304 #define CSL_EVETPCC_ER_RN_E27_MASK (0x08000000U)
8305 #define CSL_EVETPCC_ER_RN_E27_SHIFT (27U)
8306 #define CSL_EVETPCC_ER_RN_E27_RESETVAL (0x00000000U)
8307 #define CSL_EVETPCC_ER_RN_E27_MAX (0x00000001U)
8309 #define CSL_EVETPCC_ER_RN_E7_MASK (0x00000080U)
8310 #define CSL_EVETPCC_ER_RN_E7_SHIFT (7U)
8311 #define CSL_EVETPCC_ER_RN_E7_RESETVAL (0x00000000U)
8312 #define CSL_EVETPCC_ER_RN_E7_MAX (0x00000001U)
8314 #define CSL_EVETPCC_ER_RN_E17_MASK (0x00020000U)
8315 #define CSL_EVETPCC_ER_RN_E17_SHIFT (17U)
8316 #define CSL_EVETPCC_ER_RN_E17_RESETVAL (0x00000000U)
8317 #define CSL_EVETPCC_ER_RN_E17_MAX (0x00000001U)
8319 #define CSL_EVETPCC_ER_RN_E8_MASK (0x00000100U)
8320 #define CSL_EVETPCC_ER_RN_E8_SHIFT (8U)
8321 #define CSL_EVETPCC_ER_RN_E8_RESETVAL (0x00000000U)
8322 #define CSL_EVETPCC_ER_RN_E8_MAX (0x00000001U)
8324 #define CSL_EVETPCC_ER_RN_E16_MASK (0x00010000U)
8325 #define CSL_EVETPCC_ER_RN_E16_SHIFT (16U)
8326 #define CSL_EVETPCC_ER_RN_E16_RESETVAL (0x00000000U)
8327 #define CSL_EVETPCC_ER_RN_E16_MAX (0x00000001U)
8329 #define CSL_EVETPCC_ER_RN_E30_MASK (0x40000000U)
8330 #define CSL_EVETPCC_ER_RN_E30_SHIFT (30U)
8331 #define CSL_EVETPCC_ER_RN_E30_RESETVAL (0x00000000U)
8332 #define CSL_EVETPCC_ER_RN_E30_MAX (0x00000001U)
8334 #define CSL_EVETPCC_ER_RN_E24_MASK (0x01000000U)
8335 #define CSL_EVETPCC_ER_RN_E24_SHIFT (24U)
8336 #define CSL_EVETPCC_ER_RN_E24_RESETVAL (0x00000000U)
8337 #define CSL_EVETPCC_ER_RN_E24_MAX (0x00000001U)
8339 #define CSL_EVETPCC_ER_RN_E23_MASK (0x00800000U)
8340 #define CSL_EVETPCC_ER_RN_E23_SHIFT (23U)
8341 #define CSL_EVETPCC_ER_RN_E23_RESETVAL (0x00000000U)
8342 #define CSL_EVETPCC_ER_RN_E23_MAX (0x00000001U)
8344 #define CSL_EVETPCC_ER_RN_E0_MASK (0x00000001U)
8345 #define CSL_EVETPCC_ER_RN_E0_SHIFT (0U)
8346 #define CSL_EVETPCC_ER_RN_E0_RESETVAL (0x00000000U)
8347 #define CSL_EVETPCC_ER_RN_E0_MAX (0x00000001U)
8349 #define CSL_EVETPCC_ER_RN_E13_MASK (0x00002000U)
8350 #define CSL_EVETPCC_ER_RN_E13_SHIFT (13U)
8351 #define CSL_EVETPCC_ER_RN_E13_RESETVAL (0x00000000U)
8352 #define CSL_EVETPCC_ER_RN_E13_MAX (0x00000001U)
8354 #define CSL_EVETPCC_ER_RN_E11_MASK (0x00000800U)
8355 #define CSL_EVETPCC_ER_RN_E11_SHIFT (11U)
8356 #define CSL_EVETPCC_ER_RN_E11_RESETVAL (0x00000000U)
8357 #define CSL_EVETPCC_ER_RN_E11_MAX (0x00000001U)
8359 #define CSL_EVETPCC_ER_RN_E26_MASK (0x04000000U)
8360 #define CSL_EVETPCC_ER_RN_E26_SHIFT (26U)
8361 #define CSL_EVETPCC_ER_RN_E26_RESETVAL (0x00000000U)
8362 #define CSL_EVETPCC_ER_RN_E26_MAX (0x00000001U)
8364 #define CSL_EVETPCC_ER_RN_E1_MASK (0x00000002U)
8365 #define CSL_EVETPCC_ER_RN_E1_SHIFT (1U)
8366 #define CSL_EVETPCC_ER_RN_E1_RESETVAL (0x00000000U)
8367 #define CSL_EVETPCC_ER_RN_E1_MAX (0x00000001U)
8369 #define CSL_EVETPCC_ER_RN_E12_MASK (0x00001000U)
8370 #define CSL_EVETPCC_ER_RN_E12_SHIFT (12U)
8371 #define CSL_EVETPCC_ER_RN_E12_RESETVAL (0x00000000U)
8372 #define CSL_EVETPCC_ER_RN_E12_MAX (0x00000001U)
8374 #define CSL_EVETPCC_ER_RN_E25_MASK (0x02000000U)
8375 #define CSL_EVETPCC_ER_RN_E25_SHIFT (25U)
8376 #define CSL_EVETPCC_ER_RN_E25_RESETVAL (0x00000000U)
8377 #define CSL_EVETPCC_ER_RN_E25_MAX (0x00000001U)
8379 #define CSL_EVETPCC_ER_RN_E15_MASK (0x00008000U)
8380 #define CSL_EVETPCC_ER_RN_E15_SHIFT (15U)
8381 #define CSL_EVETPCC_ER_RN_E15_RESETVAL (0x00000000U)
8382 #define CSL_EVETPCC_ER_RN_E15_MAX (0x00000001U)
8384 #define CSL_EVETPCC_ER_RN_RESETVAL (0x00000000U)
8386 /* ICRH_RN */
8388 #define CSL_EVETPCC_ICRH_RN_I37_MASK (0x00000020U)
8389 #define CSL_EVETPCC_ICRH_RN_I37_SHIFT (5U)
8390 #define CSL_EVETPCC_ICRH_RN_I37_RESETVAL (0x00000000U)
8391 #define CSL_EVETPCC_ICRH_RN_I37_MAX (0x00000001U)
8393 #define CSL_EVETPCC_ICRH_RN_I47_MASK (0x00008000U)
8394 #define CSL_EVETPCC_ICRH_RN_I47_SHIFT (15U)
8395 #define CSL_EVETPCC_ICRH_RN_I47_RESETVAL (0x00000000U)
8396 #define CSL_EVETPCC_ICRH_RN_I47_MAX (0x00000001U)
8398 #define CSL_EVETPCC_ICRH_RN_I53_MASK (0x00200000U)
8399 #define CSL_EVETPCC_ICRH_RN_I53_SHIFT (21U)
8400 #define CSL_EVETPCC_ICRH_RN_I53_RESETVAL (0x00000000U)
8401 #define CSL_EVETPCC_ICRH_RN_I53_MAX (0x00000001U)
8403 #define CSL_EVETPCC_ICRH_RN_I36_MASK (0x00000010U)
8404 #define CSL_EVETPCC_ICRH_RN_I36_SHIFT (4U)
8405 #define CSL_EVETPCC_ICRH_RN_I36_RESETVAL (0x00000000U)
8406 #define CSL_EVETPCC_ICRH_RN_I36_MAX (0x00000001U)
8408 #define CSL_EVETPCC_ICRH_RN_I63_MASK (0x80000000U)
8409 #define CSL_EVETPCC_ICRH_RN_I63_SHIFT (31U)
8410 #define CSL_EVETPCC_ICRH_RN_I63_RESETVAL (0x00000000U)
8411 #define CSL_EVETPCC_ICRH_RN_I63_MAX (0x00000001U)
8413 #define CSL_EVETPCC_ICRH_RN_I46_MASK (0x00004000U)
8414 #define CSL_EVETPCC_ICRH_RN_I46_SHIFT (14U)
8415 #define CSL_EVETPCC_ICRH_RN_I46_RESETVAL (0x00000000U)
8416 #define CSL_EVETPCC_ICRH_RN_I46_MAX (0x00000001U)
8418 #define CSL_EVETPCC_ICRH_RN_I39_MASK (0x00000080U)
8419 #define CSL_EVETPCC_ICRH_RN_I39_SHIFT (7U)
8420 #define CSL_EVETPCC_ICRH_RN_I39_RESETVAL (0x00000000U)
8421 #define CSL_EVETPCC_ICRH_RN_I39_MAX (0x00000001U)
8423 #define CSL_EVETPCC_ICRH_RN_I49_MASK (0x00020000U)
8424 #define CSL_EVETPCC_ICRH_RN_I49_SHIFT (17U)
8425 #define CSL_EVETPCC_ICRH_RN_I49_RESETVAL (0x00000000U)
8426 #define CSL_EVETPCC_ICRH_RN_I49_MAX (0x00000001U)
8428 #define CSL_EVETPCC_ICRH_RN_I38_MASK (0x00000040U)
8429 #define CSL_EVETPCC_ICRH_RN_I38_SHIFT (6U)
8430 #define CSL_EVETPCC_ICRH_RN_I38_RESETVAL (0x00000000U)
8431 #define CSL_EVETPCC_ICRH_RN_I38_MAX (0x00000001U)
8433 #define CSL_EVETPCC_ICRH_RN_I48_MASK (0x00010000U)
8434 #define CSL_EVETPCC_ICRH_RN_I48_SHIFT (16U)
8435 #define CSL_EVETPCC_ICRH_RN_I48_RESETVAL (0x00000000U)
8436 #define CSL_EVETPCC_ICRH_RN_I48_MAX (0x00000001U)
8438 #define CSL_EVETPCC_ICRH_RN_I41_MASK (0x00000200U)
8439 #define CSL_EVETPCC_ICRH_RN_I41_SHIFT (9U)
8440 #define CSL_EVETPCC_ICRH_RN_I41_RESETVAL (0x00000000U)
8441 #define CSL_EVETPCC_ICRH_RN_I41_MAX (0x00000001U)
8443 #define CSL_EVETPCC_ICRH_RN_I51_MASK (0x00080000U)
8444 #define CSL_EVETPCC_ICRH_RN_I51_SHIFT (19U)
8445 #define CSL_EVETPCC_ICRH_RN_I51_RESETVAL (0x00000000U)
8446 #define CSL_EVETPCC_ICRH_RN_I51_MAX (0x00000001U)
8448 #define CSL_EVETPCC_ICRH_RN_I40_MASK (0x00000100U)
8449 #define CSL_EVETPCC_ICRH_RN_I40_SHIFT (8U)
8450 #define CSL_EVETPCC_ICRH_RN_I40_RESETVAL (0x00000000U)
8451 #define CSL_EVETPCC_ICRH_RN_I40_MAX (0x00000001U)
8453 #define CSL_EVETPCC_ICRH_RN_I50_MASK (0x00040000U)
8454 #define CSL_EVETPCC_ICRH_RN_I50_SHIFT (18U)
8455 #define CSL_EVETPCC_ICRH_RN_I50_RESETVAL (0x00000000U)
8456 #define CSL_EVETPCC_ICRH_RN_I50_MAX (0x00000001U)
8458 #define CSL_EVETPCC_ICRH_RN_I42_MASK (0x00000400U)
8459 #define CSL_EVETPCC_ICRH_RN_I42_SHIFT (10U)
8460 #define CSL_EVETPCC_ICRH_RN_I42_RESETVAL (0x00000000U)
8461 #define CSL_EVETPCC_ICRH_RN_I42_MAX (0x00000001U)
8463 #define CSL_EVETPCC_ICRH_RN_I62_MASK (0x40000000U)
8464 #define CSL_EVETPCC_ICRH_RN_I62_SHIFT (30U)
8465 #define CSL_EVETPCC_ICRH_RN_I62_RESETVAL (0x00000000U)
8466 #define CSL_EVETPCC_ICRH_RN_I62_MAX (0x00000001U)
8468 #define CSL_EVETPCC_ICRH_RN_I52_MASK (0x00100000U)
8469 #define CSL_EVETPCC_ICRH_RN_I52_SHIFT (20U)
8470 #define CSL_EVETPCC_ICRH_RN_I52_RESETVAL (0x00000000U)
8471 #define CSL_EVETPCC_ICRH_RN_I52_MAX (0x00000001U)
8473 #define CSL_EVETPCC_ICRH_RN_I61_MASK (0x20000000U)
8474 #define CSL_EVETPCC_ICRH_RN_I61_SHIFT (29U)
8475 #define CSL_EVETPCC_ICRH_RN_I61_RESETVAL (0x00000000U)
8476 #define CSL_EVETPCC_ICRH_RN_I61_MAX (0x00000001U)
8478 #define CSL_EVETPCC_ICRH_RN_I32_MASK (0x00000001U)
8479 #define CSL_EVETPCC_ICRH_RN_I32_SHIFT (0U)
8480 #define CSL_EVETPCC_ICRH_RN_I32_RESETVAL (0x00000000U)
8481 #define CSL_EVETPCC_ICRH_RN_I32_MAX (0x00000001U)
8483 #define CSL_EVETPCC_ICRH_RN_I60_MASK (0x10000000U)
8484 #define CSL_EVETPCC_ICRH_RN_I60_SHIFT (28U)
8485 #define CSL_EVETPCC_ICRH_RN_I60_RESETVAL (0x00000000U)
8486 #define CSL_EVETPCC_ICRH_RN_I60_MAX (0x00000001U)
8488 #define CSL_EVETPCC_ICRH_RN_I59_MASK (0x08000000U)
8489 #define CSL_EVETPCC_ICRH_RN_I59_SHIFT (27U)
8490 #define CSL_EVETPCC_ICRH_RN_I59_RESETVAL (0x00000000U)
8491 #define CSL_EVETPCC_ICRH_RN_I59_MAX (0x00000001U)
8493 #define CSL_EVETPCC_ICRH_RN_I58_MASK (0x04000000U)
8494 #define CSL_EVETPCC_ICRH_RN_I58_SHIFT (26U)
8495 #define CSL_EVETPCC_ICRH_RN_I58_RESETVAL (0x00000000U)
8496 #define CSL_EVETPCC_ICRH_RN_I58_MAX (0x00000001U)
8498 #define CSL_EVETPCC_ICRH_RN_I57_MASK (0x02000000U)
8499 #define CSL_EVETPCC_ICRH_RN_I57_SHIFT (25U)
8500 #define CSL_EVETPCC_ICRH_RN_I57_RESETVAL (0x00000000U)
8501 #define CSL_EVETPCC_ICRH_RN_I57_MAX (0x00000001U)
8503 #define CSL_EVETPCC_ICRH_RN_I33_MASK (0x00000002U)
8504 #define CSL_EVETPCC_ICRH_RN_I33_SHIFT (1U)
8505 #define CSL_EVETPCC_ICRH_RN_I33_RESETVAL (0x00000000U)
8506 #define CSL_EVETPCC_ICRH_RN_I33_MAX (0x00000001U)
8508 #define CSL_EVETPCC_ICRH_RN_I43_MASK (0x00000800U)
8509 #define CSL_EVETPCC_ICRH_RN_I43_SHIFT (11U)
8510 #define CSL_EVETPCC_ICRH_RN_I43_RESETVAL (0x00000000U)
8511 #define CSL_EVETPCC_ICRH_RN_I43_MAX (0x00000001U)
8513 #define CSL_EVETPCC_ICRH_RN_I56_MASK (0x01000000U)
8514 #define CSL_EVETPCC_ICRH_RN_I56_SHIFT (24U)
8515 #define CSL_EVETPCC_ICRH_RN_I56_RESETVAL (0x00000000U)
8516 #define CSL_EVETPCC_ICRH_RN_I56_MAX (0x00000001U)
8518 #define CSL_EVETPCC_ICRH_RN_I35_MASK (0x00000008U)
8519 #define CSL_EVETPCC_ICRH_RN_I35_SHIFT (3U)
8520 #define CSL_EVETPCC_ICRH_RN_I35_RESETVAL (0x00000000U)
8521 #define CSL_EVETPCC_ICRH_RN_I35_MAX (0x00000001U)
8523 #define CSL_EVETPCC_ICRH_RN_I55_MASK (0x00800000U)
8524 #define CSL_EVETPCC_ICRH_RN_I55_SHIFT (23U)
8525 #define CSL_EVETPCC_ICRH_RN_I55_RESETVAL (0x00000000U)
8526 #define CSL_EVETPCC_ICRH_RN_I55_MAX (0x00000001U)
8528 #define CSL_EVETPCC_ICRH_RN_I45_MASK (0x00002000U)
8529 #define CSL_EVETPCC_ICRH_RN_I45_SHIFT (13U)
8530 #define CSL_EVETPCC_ICRH_RN_I45_RESETVAL (0x00000000U)
8531 #define CSL_EVETPCC_ICRH_RN_I45_MAX (0x00000001U)
8533 #define CSL_EVETPCC_ICRH_RN_I34_MASK (0x00000004U)
8534 #define CSL_EVETPCC_ICRH_RN_I34_SHIFT (2U)
8535 #define CSL_EVETPCC_ICRH_RN_I34_RESETVAL (0x00000000U)
8536 #define CSL_EVETPCC_ICRH_RN_I34_MAX (0x00000001U)
8538 #define CSL_EVETPCC_ICRH_RN_I54_MASK (0x00400000U)
8539 #define CSL_EVETPCC_ICRH_RN_I54_SHIFT (22U)
8540 #define CSL_EVETPCC_ICRH_RN_I54_RESETVAL (0x00000000U)
8541 #define CSL_EVETPCC_ICRH_RN_I54_MAX (0x00000001U)
8543 #define CSL_EVETPCC_ICRH_RN_I44_MASK (0x00001000U)
8544 #define CSL_EVETPCC_ICRH_RN_I44_SHIFT (12U)
8545 #define CSL_EVETPCC_ICRH_RN_I44_RESETVAL (0x00000000U)
8546 #define CSL_EVETPCC_ICRH_RN_I44_MAX (0x00000001U)
8548 #define CSL_EVETPCC_ICRH_RN_RESETVAL (0x00000000U)
8550 /* EECRH_RN */
8552 #define CSL_EVETPCC_EECRH_RN_E62_MASK (0x40000000U)
8553 #define CSL_EVETPCC_EECRH_RN_E62_SHIFT (30U)
8554 #define CSL_EVETPCC_EECRH_RN_E62_RESETVAL (0x00000000U)
8555 #define CSL_EVETPCC_EECRH_RN_E62_MAX (0x00000001U)
8557 #define CSL_EVETPCC_EECRH_RN_E37_MASK (0x00000020U)
8558 #define CSL_EVETPCC_EECRH_RN_E37_SHIFT (5U)
8559 #define CSL_EVETPCC_EECRH_RN_E37_RESETVAL (0x00000000U)
8560 #define CSL_EVETPCC_EECRH_RN_E37_MAX (0x00000001U)
8562 #define CSL_EVETPCC_EECRH_RN_E51_MASK (0x00080000U)
8563 #define CSL_EVETPCC_EECRH_RN_E51_SHIFT (19U)
8564 #define CSL_EVETPCC_EECRH_RN_E51_RESETVAL (0x00000000U)
8565 #define CSL_EVETPCC_EECRH_RN_E51_MAX (0x00000001U)
8567 #define CSL_EVETPCC_EECRH_RN_E36_MASK (0x00000010U)
8568 #define CSL_EVETPCC_EECRH_RN_E36_SHIFT (4U)
8569 #define CSL_EVETPCC_EECRH_RN_E36_RESETVAL (0x00000000U)
8570 #define CSL_EVETPCC_EECRH_RN_E36_MAX (0x00000001U)
8572 #define CSL_EVETPCC_EECRH_RN_E50_MASK (0x00040000U)
8573 #define CSL_EVETPCC_EECRH_RN_E50_SHIFT (18U)
8574 #define CSL_EVETPCC_EECRH_RN_E50_RESETVAL (0x00000000U)
8575 #define CSL_EVETPCC_EECRH_RN_E50_MAX (0x00000001U)
8577 #define CSL_EVETPCC_EECRH_RN_E35_MASK (0x00000008U)
8578 #define CSL_EVETPCC_EECRH_RN_E35_SHIFT (3U)
8579 #define CSL_EVETPCC_EECRH_RN_E35_RESETVAL (0x00000000U)
8580 #define CSL_EVETPCC_EECRH_RN_E35_MAX (0x00000001U)
8582 #define CSL_EVETPCC_EECRH_RN_E63_MASK (0x80000000U)
8583 #define CSL_EVETPCC_EECRH_RN_E63_SHIFT (31U)
8584 #define CSL_EVETPCC_EECRH_RN_E63_RESETVAL (0x00000000U)
8585 #define CSL_EVETPCC_EECRH_RN_E63_MAX (0x00000001U)
8587 #define CSL_EVETPCC_EECRH_RN_E54_MASK (0x00400000U)
8588 #define CSL_EVETPCC_EECRH_RN_E54_SHIFT (22U)
8589 #define CSL_EVETPCC_EECRH_RN_E54_RESETVAL (0x00000000U)
8590 #define CSL_EVETPCC_EECRH_RN_E54_MAX (0x00000001U)
8592 #define CSL_EVETPCC_EECRH_RN_E58_MASK (0x04000000U)
8593 #define CSL_EVETPCC_EECRH_RN_E58_SHIFT (26U)
8594 #define CSL_EVETPCC_EECRH_RN_E58_RESETVAL (0x00000000U)
8595 #define CSL_EVETPCC_EECRH_RN_E58_MAX (0x00000001U)
8597 #define CSL_EVETPCC_EECRH_RN_E48_MASK (0x00010000U)
8598 #define CSL_EVETPCC_EECRH_RN_E48_SHIFT (16U)
8599 #define CSL_EVETPCC_EECRH_RN_E48_RESETVAL (0x00000000U)
8600 #define CSL_EVETPCC_EECRH_RN_E48_MAX (0x00000001U)
8602 #define CSL_EVETPCC_EECRH_RN_E59_MASK (0x08000000U)
8603 #define CSL_EVETPCC_EECRH_RN_E59_SHIFT (27U)
8604 #define CSL_EVETPCC_EECRH_RN_E59_RESETVAL (0x00000000U)
8605 #define CSL_EVETPCC_EECRH_RN_E59_MAX (0x00000001U)
8607 #define CSL_EVETPCC_EECRH_RN_E53_MASK (0x00200000U)
8608 #define CSL_EVETPCC_EECRH_RN_E53_SHIFT (21U)
8609 #define CSL_EVETPCC_EECRH_RN_E53_RESETVAL (0x00000000U)
8610 #define CSL_EVETPCC_EECRH_RN_E53_MAX (0x00000001U)
8612 #define CSL_EVETPCC_EECRH_RN_E49_MASK (0x00020000U)
8613 #define CSL_EVETPCC_EECRH_RN_E49_SHIFT (17U)
8614 #define CSL_EVETPCC_EECRH_RN_E49_RESETVAL (0x00000000U)
8615 #define CSL_EVETPCC_EECRH_RN_E49_MAX (0x00000001U)
8617 #define CSL_EVETPCC_EECRH_RN_E60_MASK (0x10000000U)
8618 #define CSL_EVETPCC_EECRH_RN_E60_SHIFT (28U)
8619 #define CSL_EVETPCC_EECRH_RN_E60_RESETVAL (0x00000000U)
8620 #define CSL_EVETPCC_EECRH_RN_E60_MAX (0x00000001U)
8622 #define CSL_EVETPCC_EECRH_RN_E61_MASK (0x20000000U)
8623 #define CSL_EVETPCC_EECRH_RN_E61_SHIFT (29U)
8624 #define CSL_EVETPCC_EECRH_RN_E61_RESETVAL (0x00000000U)
8625 #define CSL_EVETPCC_EECRH_RN_E61_MAX (0x00000001U)
8627 #define CSL_EVETPCC_EECRH_RN_E52_MASK (0x00100000U)
8628 #define CSL_EVETPCC_EECRH_RN_E52_SHIFT (20U)
8629 #define CSL_EVETPCC_EECRH_RN_E52_RESETVAL (0x00000000U)
8630 #define CSL_EVETPCC_EECRH_RN_E52_MAX (0x00000001U)
8632 #define CSL_EVETPCC_EECRH_RN_E44_MASK (0x00001000U)
8633 #define CSL_EVETPCC_EECRH_RN_E44_SHIFT (12U)
8634 #define CSL_EVETPCC_EECRH_RN_E44_RESETVAL (0x00000000U)
8635 #define CSL_EVETPCC_EECRH_RN_E44_MAX (0x00000001U)
8637 #define CSL_EVETPCC_EECRH_RN_E34_MASK (0x00000004U)
8638 #define CSL_EVETPCC_EECRH_RN_E34_SHIFT (2U)
8639 #define CSL_EVETPCC_EECRH_RN_E34_RESETVAL (0x00000000U)
8640 #define CSL_EVETPCC_EECRH_RN_E34_MAX (0x00000001U)
8642 #define CSL_EVETPCC_EECRH_RN_E43_MASK (0x00000800U)
8643 #define CSL_EVETPCC_EECRH_RN_E43_SHIFT (11U)
8644 #define CSL_EVETPCC_EECRH_RN_E43_RESETVAL (0x00000000U)
8645 #define CSL_EVETPCC_EECRH_RN_E43_MAX (0x00000001U)
8647 #define CSL_EVETPCC_EECRH_RN_E33_MASK (0x00000002U)
8648 #define CSL_EVETPCC_EECRH_RN_E33_SHIFT (1U)
8649 #define CSL_EVETPCC_EECRH_RN_E33_RESETVAL (0x00000000U)
8650 #define CSL_EVETPCC_EECRH_RN_E33_MAX (0x00000001U)
8652 #define CSL_EVETPCC_EECRH_RN_E55_MASK (0x00800000U)
8653 #define CSL_EVETPCC_EECRH_RN_E55_SHIFT (23U)
8654 #define CSL_EVETPCC_EECRH_RN_E55_RESETVAL (0x00000000U)
8655 #define CSL_EVETPCC_EECRH_RN_E55_MAX (0x00000001U)
8657 #define CSL_EVETPCC_EECRH_RN_E42_MASK (0x00000400U)
8658 #define CSL_EVETPCC_EECRH_RN_E42_SHIFT (10U)
8659 #define CSL_EVETPCC_EECRH_RN_E42_RESETVAL (0x00000000U)
8660 #define CSL_EVETPCC_EECRH_RN_E42_MAX (0x00000001U)
8662 #define CSL_EVETPCC_EECRH_RN_E56_MASK (0x01000000U)
8663 #define CSL_EVETPCC_EECRH_RN_E56_SHIFT (24U)
8664 #define CSL_EVETPCC_EECRH_RN_E56_RESETVAL (0x00000000U)
8665 #define CSL_EVETPCC_EECRH_RN_E56_MAX (0x00000001U)
8667 #define CSL_EVETPCC_EECRH_RN_E32_MASK (0x00000001U)
8668 #define CSL_EVETPCC_EECRH_RN_E32_SHIFT (0U)
8669 #define CSL_EVETPCC_EECRH_RN_E32_RESETVAL (0x00000000U)
8670 #define CSL_EVETPCC_EECRH_RN_E32_MAX (0x00000001U)
8672 #define CSL_EVETPCC_EECRH_RN_E41_MASK (0x00000200U)
8673 #define CSL_EVETPCC_EECRH_RN_E41_SHIFT (9U)
8674 #define CSL_EVETPCC_EECRH_RN_E41_RESETVAL (0x00000000U)
8675 #define CSL_EVETPCC_EECRH_RN_E41_MAX (0x00000001U)
8677 #define CSL_EVETPCC_EECRH_RN_E57_MASK (0x02000000U)
8678 #define CSL_EVETPCC_EECRH_RN_E57_SHIFT (25U)
8679 #define CSL_EVETPCC_EECRH_RN_E57_RESETVAL (0x00000000U)
8680 #define CSL_EVETPCC_EECRH_RN_E57_MAX (0x00000001U)
8682 #define CSL_EVETPCC_EECRH_RN_E47_MASK (0x00008000U)
8683 #define CSL_EVETPCC_EECRH_RN_E47_SHIFT (15U)
8684 #define CSL_EVETPCC_EECRH_RN_E47_RESETVAL (0x00000000U)
8685 #define CSL_EVETPCC_EECRH_RN_E47_MAX (0x00000001U)
8687 #define CSL_EVETPCC_EECRH_RN_E40_MASK (0x00000100U)
8688 #define CSL_EVETPCC_EECRH_RN_E40_SHIFT (8U)
8689 #define CSL_EVETPCC_EECRH_RN_E40_RESETVAL (0x00000000U)
8690 #define CSL_EVETPCC_EECRH_RN_E40_MAX (0x00000001U)
8692 #define CSL_EVETPCC_EECRH_RN_E46_MASK (0x00004000U)
8693 #define CSL_EVETPCC_EECRH_RN_E46_SHIFT (14U)
8694 #define CSL_EVETPCC_EECRH_RN_E46_RESETVAL (0x00000000U)
8695 #define CSL_EVETPCC_EECRH_RN_E46_MAX (0x00000001U)
8697 #define CSL_EVETPCC_EECRH_RN_E39_MASK (0x00000080U)
8698 #define CSL_EVETPCC_EECRH_RN_E39_SHIFT (7U)
8699 #define CSL_EVETPCC_EECRH_RN_E39_RESETVAL (0x00000000U)
8700 #define CSL_EVETPCC_EECRH_RN_E39_MAX (0x00000001U)
8702 #define CSL_EVETPCC_EECRH_RN_E45_MASK (0x00002000U)
8703 #define CSL_EVETPCC_EECRH_RN_E45_SHIFT (13U)
8704 #define CSL_EVETPCC_EECRH_RN_E45_RESETVAL (0x00000000U)
8705 #define CSL_EVETPCC_EECRH_RN_E45_MAX (0x00000001U)
8707 #define CSL_EVETPCC_EECRH_RN_E38_MASK (0x00000040U)
8708 #define CSL_EVETPCC_EECRH_RN_E38_SHIFT (6U)
8709 #define CSL_EVETPCC_EECRH_RN_E38_RESETVAL (0x00000000U)
8710 #define CSL_EVETPCC_EECRH_RN_E38_MAX (0x00000001U)
8712 #define CSL_EVETPCC_EECRH_RN_RESETVAL (0x00000000U)
8714 /* IESR_RN */
8716 #define CSL_EVETPCC_IESR_RN_I22_MASK (0x00400000U)
8717 #define CSL_EVETPCC_IESR_RN_I22_SHIFT (22U)
8718 #define CSL_EVETPCC_IESR_RN_I22_RESETVAL (0x00000000U)
8719 #define CSL_EVETPCC_IESR_RN_I22_MAX (0x00000001U)
8721 #define CSL_EVETPCC_IESR_RN_I11_MASK (0x00000800U)
8722 #define CSL_EVETPCC_IESR_RN_I11_SHIFT (11U)
8723 #define CSL_EVETPCC_IESR_RN_I11_RESETVAL (0x00000000U)
8724 #define CSL_EVETPCC_IESR_RN_I11_MAX (0x00000001U)
8726 #define CSL_EVETPCC_IESR_RN_I23_MASK (0x00800000U)
8727 #define CSL_EVETPCC_IESR_RN_I23_SHIFT (23U)
8728 #define CSL_EVETPCC_IESR_RN_I23_RESETVAL (0x00000000U)
8729 #define CSL_EVETPCC_IESR_RN_I23_MAX (0x00000001U)
8731 #define CSL_EVETPCC_IESR_RN_I0_MASK (0x00000001U)
8732 #define CSL_EVETPCC_IESR_RN_I0_SHIFT (0U)
8733 #define CSL_EVETPCC_IESR_RN_I0_RESETVAL (0x00000000U)
8734 #define CSL_EVETPCC_IESR_RN_I0_MAX (0x00000001U)
8736 #define CSL_EVETPCC_IESR_RN_I21_MASK (0x00200000U)
8737 #define CSL_EVETPCC_IESR_RN_I21_SHIFT (21U)
8738 #define CSL_EVETPCC_IESR_RN_I21_RESETVAL (0x00000000U)
8739 #define CSL_EVETPCC_IESR_RN_I21_MAX (0x00000001U)
8741 #define CSL_EVETPCC_IESR_RN_I10_MASK (0x00000400U)
8742 #define CSL_EVETPCC_IESR_RN_I10_SHIFT (10U)
8743 #define CSL_EVETPCC_IESR_RN_I10_RESETVAL (0x00000000U)
8744 #define CSL_EVETPCC_IESR_RN_I10_MAX (0x00000001U)
8746 #define CSL_EVETPCC_IESR_RN_I31_MASK (0x80000000U)
8747 #define CSL_EVETPCC_IESR_RN_I31_SHIFT (31U)
8748 #define CSL_EVETPCC_IESR_RN_I31_RESETVAL (0x00000000U)
8749 #define CSL_EVETPCC_IESR_RN_I31_MAX (0x00000001U)
8751 #define CSL_EVETPCC_IESR_RN_I8_MASK (0x00000100U)
8752 #define CSL_EVETPCC_IESR_RN_I8_SHIFT (8U)
8753 #define CSL_EVETPCC_IESR_RN_I8_RESETVAL (0x00000000U)
8754 #define CSL_EVETPCC_IESR_RN_I8_MAX (0x00000001U)
8756 #define CSL_EVETPCC_IESR_RN_I20_MASK (0x00100000U)
8757 #define CSL_EVETPCC_IESR_RN_I20_SHIFT (20U)
8758 #define CSL_EVETPCC_IESR_RN_I20_RESETVAL (0x00000000U)
8759 #define CSL_EVETPCC_IESR_RN_I20_MAX (0x00000001U)
8761 #define CSL_EVETPCC_IESR_RN_I9_MASK (0x00000200U)
8762 #define CSL_EVETPCC_IESR_RN_I9_SHIFT (9U)
8763 #define CSL_EVETPCC_IESR_RN_I9_RESETVAL (0x00000000U)
8764 #define CSL_EVETPCC_IESR_RN_I9_MAX (0x00000001U)
8766 #define CSL_EVETPCC_IESR_RN_I6_MASK (0x00000040U)
8767 #define CSL_EVETPCC_IESR_RN_I6_SHIFT (6U)
8768 #define CSL_EVETPCC_IESR_RN_I6_RESETVAL (0x00000000U)
8769 #define CSL_EVETPCC_IESR_RN_I6_MAX (0x00000001U)
8771 #define CSL_EVETPCC_IESR_RN_I30_MASK (0x40000000U)
8772 #define CSL_EVETPCC_IESR_RN_I30_SHIFT (30U)
8773 #define CSL_EVETPCC_IESR_RN_I30_RESETVAL (0x00000000U)
8774 #define CSL_EVETPCC_IESR_RN_I30_MAX (0x00000001U)
8776 #define CSL_EVETPCC_IESR_RN_I17_MASK (0x00020000U)
8777 #define CSL_EVETPCC_IESR_RN_I17_SHIFT (17U)
8778 #define CSL_EVETPCC_IESR_RN_I17_RESETVAL (0x00000000U)
8779 #define CSL_EVETPCC_IESR_RN_I17_MAX (0x00000001U)
8781 #define CSL_EVETPCC_IESR_RN_I7_MASK (0x00000080U)
8782 #define CSL_EVETPCC_IESR_RN_I7_SHIFT (7U)
8783 #define CSL_EVETPCC_IESR_RN_I7_RESETVAL (0x00000000U)
8784 #define CSL_EVETPCC_IESR_RN_I7_MAX (0x00000001U)
8786 #define CSL_EVETPCC_IESR_RN_I16_MASK (0x00010000U)
8787 #define CSL_EVETPCC_IESR_RN_I16_SHIFT (16U)
8788 #define CSL_EVETPCC_IESR_RN_I16_RESETVAL (0x00000000U)
8789 #define CSL_EVETPCC_IESR_RN_I16_MAX (0x00000001U)
8791 #define CSL_EVETPCC_IESR_RN_I28_MASK (0x10000000U)
8792 #define CSL_EVETPCC_IESR_RN_I28_SHIFT (28U)
8793 #define CSL_EVETPCC_IESR_RN_I28_RESETVAL (0x00000000U)
8794 #define CSL_EVETPCC_IESR_RN_I28_MAX (0x00000001U)
8796 #define CSL_EVETPCC_IESR_RN_I4_MASK (0x00000010U)
8797 #define CSL_EVETPCC_IESR_RN_I4_SHIFT (4U)
8798 #define CSL_EVETPCC_IESR_RN_I4_RESETVAL (0x00000000U)
8799 #define CSL_EVETPCC_IESR_RN_I4_MAX (0x00000001U)
8801 #define CSL_EVETPCC_IESR_RN_I29_MASK (0x20000000U)
8802 #define CSL_EVETPCC_IESR_RN_I29_SHIFT (29U)
8803 #define CSL_EVETPCC_IESR_RN_I29_RESETVAL (0x00000000U)
8804 #define CSL_EVETPCC_IESR_RN_I29_MAX (0x00000001U)
8806 #define CSL_EVETPCC_IESR_RN_I19_MASK (0x00080000U)
8807 #define CSL_EVETPCC_IESR_RN_I19_SHIFT (19U)
8808 #define CSL_EVETPCC_IESR_RN_I19_RESETVAL (0x00000000U)
8809 #define CSL_EVETPCC_IESR_RN_I19_MAX (0x00000001U)
8811 #define CSL_EVETPCC_IESR_RN_I5_MASK (0x00000020U)
8812 #define CSL_EVETPCC_IESR_RN_I5_SHIFT (5U)
8813 #define CSL_EVETPCC_IESR_RN_I5_RESETVAL (0x00000000U)
8814 #define CSL_EVETPCC_IESR_RN_I5_MAX (0x00000001U)
8816 #define CSL_EVETPCC_IESR_RN_I18_MASK (0x00040000U)
8817 #define CSL_EVETPCC_IESR_RN_I18_SHIFT (18U)
8818 #define CSL_EVETPCC_IESR_RN_I18_RESETVAL (0x00000000U)
8819 #define CSL_EVETPCC_IESR_RN_I18_MAX (0x00000001U)
8821 #define CSL_EVETPCC_IESR_RN_I26_MASK (0x04000000U)
8822 #define CSL_EVETPCC_IESR_RN_I26_SHIFT (26U)
8823 #define CSL_EVETPCC_IESR_RN_I26_RESETVAL (0x00000000U)
8824 #define CSL_EVETPCC_IESR_RN_I26_MAX (0x00000001U)
8826 #define CSL_EVETPCC_IESR_RN_I2_MASK (0x00000004U)
8827 #define CSL_EVETPCC_IESR_RN_I2_SHIFT (2U)
8828 #define CSL_EVETPCC_IESR_RN_I2_RESETVAL (0x00000000U)
8829 #define CSL_EVETPCC_IESR_RN_I2_MAX (0x00000001U)
8831 #define CSL_EVETPCC_IESR_RN_I13_MASK (0x00002000U)
8832 #define CSL_EVETPCC_IESR_RN_I13_SHIFT (13U)
8833 #define CSL_EVETPCC_IESR_RN_I13_RESETVAL (0x00000000U)
8834 #define CSL_EVETPCC_IESR_RN_I13_MAX (0x00000001U)
8836 #define CSL_EVETPCC_IESR_RN_I3_MASK (0x00000008U)
8837 #define CSL_EVETPCC_IESR_RN_I3_SHIFT (3U)
8838 #define CSL_EVETPCC_IESR_RN_I3_RESETVAL (0x00000000U)
8839 #define CSL_EVETPCC_IESR_RN_I3_MAX (0x00000001U)
8841 #define CSL_EVETPCC_IESR_RN_I27_MASK (0x08000000U)
8842 #define CSL_EVETPCC_IESR_RN_I27_SHIFT (27U)
8843 #define CSL_EVETPCC_IESR_RN_I27_RESETVAL (0x00000000U)
8844 #define CSL_EVETPCC_IESR_RN_I27_MAX (0x00000001U)
8846 #define CSL_EVETPCC_IESR_RN_I12_MASK (0x00001000U)
8847 #define CSL_EVETPCC_IESR_RN_I12_SHIFT (12U)
8848 #define CSL_EVETPCC_IESR_RN_I12_RESETVAL (0x00000000U)
8849 #define CSL_EVETPCC_IESR_RN_I12_MAX (0x00000001U)
8851 #define CSL_EVETPCC_IESR_RN_I24_MASK (0x01000000U)
8852 #define CSL_EVETPCC_IESR_RN_I24_SHIFT (24U)
8853 #define CSL_EVETPCC_IESR_RN_I24_RESETVAL (0x00000000U)
8854 #define CSL_EVETPCC_IESR_RN_I24_MAX (0x00000001U)
8856 #define CSL_EVETPCC_IESR_RN_I15_MASK (0x00008000U)
8857 #define CSL_EVETPCC_IESR_RN_I15_SHIFT (15U)
8858 #define CSL_EVETPCC_IESR_RN_I15_RESETVAL (0x00000000U)
8859 #define CSL_EVETPCC_IESR_RN_I15_MAX (0x00000001U)
8861 #define CSL_EVETPCC_IESR_RN_I1_MASK (0x00000002U)
8862 #define CSL_EVETPCC_IESR_RN_I1_SHIFT (1U)
8863 #define CSL_EVETPCC_IESR_RN_I1_RESETVAL (0x00000000U)
8864 #define CSL_EVETPCC_IESR_RN_I1_MAX (0x00000001U)
8866 #define CSL_EVETPCC_IESR_RN_I25_MASK (0x02000000U)
8867 #define CSL_EVETPCC_IESR_RN_I25_SHIFT (25U)
8868 #define CSL_EVETPCC_IESR_RN_I25_RESETVAL (0x00000000U)
8869 #define CSL_EVETPCC_IESR_RN_I25_MAX (0x00000001U)
8871 #define CSL_EVETPCC_IESR_RN_I14_MASK (0x00004000U)
8872 #define CSL_EVETPCC_IESR_RN_I14_SHIFT (14U)
8873 #define CSL_EVETPCC_IESR_RN_I14_RESETVAL (0x00000000U)
8874 #define CSL_EVETPCC_IESR_RN_I14_MAX (0x00000001U)
8876 #define CSL_EVETPCC_IESR_RN_RESETVAL (0x00000000U)
8878 /* SECR_RN */
8880 #define CSL_EVETPCC_SECR_RN_E21_MASK (0x00200000U)
8881 #define CSL_EVETPCC_SECR_RN_E21_SHIFT (21U)
8882 #define CSL_EVETPCC_SECR_RN_E21_RESETVAL (0x00000000U)
8883 #define CSL_EVETPCC_SECR_RN_E21_MAX (0x00000001U)
8885 #define CSL_EVETPCC_SECR_RN_E29_MASK (0x20000000U)
8886 #define CSL_EVETPCC_SECR_RN_E29_SHIFT (29U)
8887 #define CSL_EVETPCC_SECR_RN_E29_RESETVAL (0x00000000U)
8888 #define CSL_EVETPCC_SECR_RN_E29_MAX (0x00000001U)
8890 #define CSL_EVETPCC_SECR_RN_E20_MASK (0x00100000U)
8891 #define CSL_EVETPCC_SECR_RN_E20_SHIFT (20U)
8892 #define CSL_EVETPCC_SECR_RN_E20_RESETVAL (0x00000000U)
8893 #define CSL_EVETPCC_SECR_RN_E20_MAX (0x00000001U)
8895 #define CSL_EVETPCC_SECR_RN_E0_MASK (0x00000001U)
8896 #define CSL_EVETPCC_SECR_RN_E0_SHIFT (0U)
8897 #define CSL_EVETPCC_SECR_RN_E0_RESETVAL (0x00000000U)
8898 #define CSL_EVETPCC_SECR_RN_E0_MAX (0x00000001U)
8900 #define CSL_EVETPCC_SECR_RN_E10_MASK (0x00000400U)
8901 #define CSL_EVETPCC_SECR_RN_E10_SHIFT (10U)
8902 #define CSL_EVETPCC_SECR_RN_E10_RESETVAL (0x00000000U)
8903 #define CSL_EVETPCC_SECR_RN_E10_MAX (0x00000001U)
8905 #define CSL_EVETPCC_SECR_RN_E9_MASK (0x00000200U)
8906 #define CSL_EVETPCC_SECR_RN_E9_SHIFT (9U)
8907 #define CSL_EVETPCC_SECR_RN_E9_RESETVAL (0x00000000U)
8908 #define CSL_EVETPCC_SECR_RN_E9_MAX (0x00000001U)
8910 #define CSL_EVETPCC_SECR_RN_E27_MASK (0x08000000U)
8911 #define CSL_EVETPCC_SECR_RN_E27_SHIFT (27U)
8912 #define CSL_EVETPCC_SECR_RN_E27_RESETVAL (0x00000000U)
8913 #define CSL_EVETPCC_SECR_RN_E27_MAX (0x00000001U)
8915 #define CSL_EVETPCC_SECR_RN_E2_MASK (0x00000004U)
8916 #define CSL_EVETPCC_SECR_RN_E2_SHIFT (2U)
8917 #define CSL_EVETPCC_SECR_RN_E2_RESETVAL (0x00000000U)
8918 #define CSL_EVETPCC_SECR_RN_E2_MAX (0x00000001U)
8920 #define CSL_EVETPCC_SECR_RN_E12_MASK (0x00001000U)
8921 #define CSL_EVETPCC_SECR_RN_E12_SHIFT (12U)
8922 #define CSL_EVETPCC_SECR_RN_E12_RESETVAL (0x00000000U)
8923 #define CSL_EVETPCC_SECR_RN_E12_MAX (0x00000001U)
8925 #define CSL_EVETPCC_SECR_RN_E28_MASK (0x10000000U)
8926 #define CSL_EVETPCC_SECR_RN_E28_SHIFT (28U)
8927 #define CSL_EVETPCC_SECR_RN_E28_RESETVAL (0x00000000U)
8928 #define CSL_EVETPCC_SECR_RN_E28_MAX (0x00000001U)
8930 #define CSL_EVETPCC_SECR_RN_E1_MASK (0x00000002U)
8931 #define CSL_EVETPCC_SECR_RN_E1_SHIFT (1U)
8932 #define CSL_EVETPCC_SECR_RN_E1_RESETVAL (0x00000000U)
8933 #define CSL_EVETPCC_SECR_RN_E1_MAX (0x00000001U)
8935 #define CSL_EVETPCC_SECR_RN_E11_MASK (0x00000800U)
8936 #define CSL_EVETPCC_SECR_RN_E11_SHIFT (11U)
8937 #define CSL_EVETPCC_SECR_RN_E11_RESETVAL (0x00000000U)
8938 #define CSL_EVETPCC_SECR_RN_E11_MAX (0x00000001U)
8940 #define CSL_EVETPCC_SECR_RN_E25_MASK (0x02000000U)
8941 #define CSL_EVETPCC_SECR_RN_E25_SHIFT (25U)
8942 #define CSL_EVETPCC_SECR_RN_E25_RESETVAL (0x00000000U)
8943 #define CSL_EVETPCC_SECR_RN_E25_MAX (0x00000001U)
8945 #define CSL_EVETPCC_SECR_RN_E4_MASK (0x00000010U)
8946 #define CSL_EVETPCC_SECR_RN_E4_SHIFT (4U)
8947 #define CSL_EVETPCC_SECR_RN_E4_RESETVAL (0x00000000U)
8948 #define CSL_EVETPCC_SECR_RN_E4_MAX (0x00000001U)
8950 #define CSL_EVETPCC_SECR_RN_E14_MASK (0x00004000U)
8951 #define CSL_EVETPCC_SECR_RN_E14_SHIFT (14U)
8952 #define CSL_EVETPCC_SECR_RN_E14_RESETVAL (0x00000000U)
8953 #define CSL_EVETPCC_SECR_RN_E14_MAX (0x00000001U)
8955 #define CSL_EVETPCC_SECR_RN_E26_MASK (0x04000000U)
8956 #define CSL_EVETPCC_SECR_RN_E26_SHIFT (26U)
8957 #define CSL_EVETPCC_SECR_RN_E26_RESETVAL (0x00000000U)
8958 #define CSL_EVETPCC_SECR_RN_E26_MAX (0x00000001U)
8960 #define CSL_EVETPCC_SECR_RN_E3_MASK (0x00000008U)
8961 #define CSL_EVETPCC_SECR_RN_E3_SHIFT (3U)
8962 #define CSL_EVETPCC_SECR_RN_E3_RESETVAL (0x00000000U)
8963 #define CSL_EVETPCC_SECR_RN_E3_MAX (0x00000001U)
8965 #define CSL_EVETPCC_SECR_RN_E13_MASK (0x00002000U)
8966 #define CSL_EVETPCC_SECR_RN_E13_SHIFT (13U)
8967 #define CSL_EVETPCC_SECR_RN_E13_RESETVAL (0x00000000U)
8968 #define CSL_EVETPCC_SECR_RN_E13_MAX (0x00000001U)
8970 #define CSL_EVETPCC_SECR_RN_E6_MASK (0x00000040U)
8971 #define CSL_EVETPCC_SECR_RN_E6_SHIFT (6U)
8972 #define CSL_EVETPCC_SECR_RN_E6_RESETVAL (0x00000000U)
8973 #define CSL_EVETPCC_SECR_RN_E6_MAX (0x00000001U)
8975 #define CSL_EVETPCC_SECR_RN_E16_MASK (0x00010000U)
8976 #define CSL_EVETPCC_SECR_RN_E16_SHIFT (16U)
8977 #define CSL_EVETPCC_SECR_RN_E16_RESETVAL (0x00000000U)
8978 #define CSL_EVETPCC_SECR_RN_E16_MAX (0x00000001U)
8980 #define CSL_EVETPCC_SECR_RN_E24_MASK (0x01000000U)
8981 #define CSL_EVETPCC_SECR_RN_E24_SHIFT (24U)
8982 #define CSL_EVETPCC_SECR_RN_E24_RESETVAL (0x00000000U)
8983 #define CSL_EVETPCC_SECR_RN_E24_MAX (0x00000001U)
8985 #define CSL_EVETPCC_SECR_RN_E5_MASK (0x00000020U)
8986 #define CSL_EVETPCC_SECR_RN_E5_SHIFT (5U)
8987 #define CSL_EVETPCC_SECR_RN_E5_RESETVAL (0x00000000U)
8988 #define CSL_EVETPCC_SECR_RN_E5_MAX (0x00000001U)
8990 #define CSL_EVETPCC_SECR_RN_E15_MASK (0x00008000U)
8991 #define CSL_EVETPCC_SECR_RN_E15_SHIFT (15U)
8992 #define CSL_EVETPCC_SECR_RN_E15_RESETVAL (0x00000000U)
8993 #define CSL_EVETPCC_SECR_RN_E15_MAX (0x00000001U)
8995 #define CSL_EVETPCC_SECR_RN_E18_MASK (0x00040000U)
8996 #define CSL_EVETPCC_SECR_RN_E18_SHIFT (18U)
8997 #define CSL_EVETPCC_SECR_RN_E18_RESETVAL (0x00000000U)
8998 #define CSL_EVETPCC_SECR_RN_E18_MAX (0x00000001U)
9000 #define CSL_EVETPCC_SECR_RN_E31_MASK (0x80000000U)
9001 #define CSL_EVETPCC_SECR_RN_E31_SHIFT (31U)
9002 #define CSL_EVETPCC_SECR_RN_E31_RESETVAL (0x00000000U)
9003 #define CSL_EVETPCC_SECR_RN_E31_MAX (0x00000001U)
9005 #define CSL_EVETPCC_SECR_RN_E8_MASK (0x00000100U)
9006 #define CSL_EVETPCC_SECR_RN_E8_SHIFT (8U)
9007 #define CSL_EVETPCC_SECR_RN_E8_RESETVAL (0x00000000U)
9008 #define CSL_EVETPCC_SECR_RN_E8_MAX (0x00000001U)
9010 #define CSL_EVETPCC_SECR_RN_E22_MASK (0x00400000U)
9011 #define CSL_EVETPCC_SECR_RN_E22_SHIFT (22U)
9012 #define CSL_EVETPCC_SECR_RN_E22_RESETVAL (0x00000000U)
9013 #define CSL_EVETPCC_SECR_RN_E22_MAX (0x00000001U)
9015 #define CSL_EVETPCC_SECR_RN_E7_MASK (0x00000080U)
9016 #define CSL_EVETPCC_SECR_RN_E7_SHIFT (7U)
9017 #define CSL_EVETPCC_SECR_RN_E7_RESETVAL (0x00000000U)
9018 #define CSL_EVETPCC_SECR_RN_E7_MAX (0x00000001U)
9020 #define CSL_EVETPCC_SECR_RN_E19_MASK (0x00080000U)
9021 #define CSL_EVETPCC_SECR_RN_E19_SHIFT (19U)
9022 #define CSL_EVETPCC_SECR_RN_E19_RESETVAL (0x00000000U)
9023 #define CSL_EVETPCC_SECR_RN_E19_MAX (0x00000001U)
9025 #define CSL_EVETPCC_SECR_RN_E17_MASK (0x00020000U)
9026 #define CSL_EVETPCC_SECR_RN_E17_SHIFT (17U)
9027 #define CSL_EVETPCC_SECR_RN_E17_RESETVAL (0x00000000U)
9028 #define CSL_EVETPCC_SECR_RN_E17_MAX (0x00000001U)
9030 #define CSL_EVETPCC_SECR_RN_E23_MASK (0x00800000U)
9031 #define CSL_EVETPCC_SECR_RN_E23_SHIFT (23U)
9032 #define CSL_EVETPCC_SECR_RN_E23_RESETVAL (0x00000000U)
9033 #define CSL_EVETPCC_SECR_RN_E23_MAX (0x00000001U)
9035 #define CSL_EVETPCC_SECR_RN_E30_MASK (0x40000000U)
9036 #define CSL_EVETPCC_SECR_RN_E30_SHIFT (30U)
9037 #define CSL_EVETPCC_SECR_RN_E30_RESETVAL (0x00000000U)
9038 #define CSL_EVETPCC_SECR_RN_E30_MAX (0x00000001U)
9040 #define CSL_EVETPCC_SECR_RN_RESETVAL (0x00000000U)
9042 /* EESR_RN */
9044 #define CSL_EVETPCC_EESR_RN_E15_MASK (0x00008000U)
9045 #define CSL_EVETPCC_EESR_RN_E15_SHIFT (15U)
9046 #define CSL_EVETPCC_EESR_RN_E15_RESETVAL (0x00000000U)
9047 #define CSL_EVETPCC_EESR_RN_E15_MAX (0x00000001U)
9049 #define CSL_EVETPCC_EESR_RN_E6_MASK (0x00000040U)
9050 #define CSL_EVETPCC_EESR_RN_E6_SHIFT (6U)
9051 #define CSL_EVETPCC_EESR_RN_E6_RESETVAL (0x00000000U)
9052 #define CSL_EVETPCC_EESR_RN_E6_MAX (0x00000001U)
9054 #define CSL_EVETPCC_EESR_RN_E16_MASK (0x00010000U)
9055 #define CSL_EVETPCC_EESR_RN_E16_SHIFT (16U)
9056 #define CSL_EVETPCC_EESR_RN_E16_RESETVAL (0x00000000U)
9057 #define CSL_EVETPCC_EESR_RN_E16_MAX (0x00000001U)
9059 #define CSL_EVETPCC_EESR_RN_E30_MASK (0x40000000U)
9060 #define CSL_EVETPCC_EESR_RN_E30_SHIFT (30U)
9061 #define CSL_EVETPCC_EESR_RN_E30_RESETVAL (0x00000000U)
9062 #define CSL_EVETPCC_EESR_RN_E30_MAX (0x00000001U)
9064 #define CSL_EVETPCC_EESR_RN_E7_MASK (0x00000080U)
9065 #define CSL_EVETPCC_EESR_RN_E7_SHIFT (7U)
9066 #define CSL_EVETPCC_EESR_RN_E7_RESETVAL (0x00000000U)
9067 #define CSL_EVETPCC_EESR_RN_E7_MAX (0x00000001U)
9069 #define CSL_EVETPCC_EESR_RN_E4_MASK (0x00000010U)
9070 #define CSL_EVETPCC_EESR_RN_E4_SHIFT (4U)
9071 #define CSL_EVETPCC_EESR_RN_E4_RESETVAL (0x00000000U)
9072 #define CSL_EVETPCC_EESR_RN_E4_MAX (0x00000001U)
9074 #define CSL_EVETPCC_EESR_RN_E5_MASK (0x00000020U)
9075 #define CSL_EVETPCC_EESR_RN_E5_SHIFT (5U)
9076 #define CSL_EVETPCC_EESR_RN_E5_RESETVAL (0x00000000U)
9077 #define CSL_EVETPCC_EESR_RN_E5_MAX (0x00000001U)
9079 #define CSL_EVETPCC_EESR_RN_E29_MASK (0x20000000U)
9080 #define CSL_EVETPCC_EESR_RN_E29_SHIFT (29U)
9081 #define CSL_EVETPCC_EESR_RN_E29_RESETVAL (0x00000000U)
9082 #define CSL_EVETPCC_EESR_RN_E29_MAX (0x00000001U)
9084 #define CSL_EVETPCC_EESR_RN_E0_MASK (0x00000001U)
9085 #define CSL_EVETPCC_EESR_RN_E0_SHIFT (0U)
9086 #define CSL_EVETPCC_EESR_RN_E0_RESETVAL (0x00000000U)
9087 #define CSL_EVETPCC_EESR_RN_E0_MAX (0x00000001U)
9089 #define CSL_EVETPCC_EESR_RN_E10_MASK (0x00000400U)
9090 #define CSL_EVETPCC_EESR_RN_E10_SHIFT (10U)
9091 #define CSL_EVETPCC_EESR_RN_E10_RESETVAL (0x00000000U)
9092 #define CSL_EVETPCC_EESR_RN_E10_MAX (0x00000001U)
9094 #define CSL_EVETPCC_EESR_RN_E28_MASK (0x10000000U)
9095 #define CSL_EVETPCC_EESR_RN_E28_SHIFT (28U)
9096 #define CSL_EVETPCC_EESR_RN_E28_RESETVAL (0x00000000U)
9097 #define CSL_EVETPCC_EESR_RN_E28_MAX (0x00000001U)
9099 #define CSL_EVETPCC_EESR_RN_E27_MASK (0x08000000U)
9100 #define CSL_EVETPCC_EESR_RN_E27_SHIFT (27U)
9101 #define CSL_EVETPCC_EESR_RN_E27_RESETVAL (0x00000000U)
9102 #define CSL_EVETPCC_EESR_RN_E27_MAX (0x00000001U)
9104 #define CSL_EVETPCC_EESR_RN_E26_MASK (0x04000000U)
9105 #define CSL_EVETPCC_EESR_RN_E26_SHIFT (26U)
9106 #define CSL_EVETPCC_EESR_RN_E26_RESETVAL (0x00000000U)
9107 #define CSL_EVETPCC_EESR_RN_E26_MAX (0x00000001U)
9109 #define CSL_EVETPCC_EESR_RN_E8_MASK (0x00000100U)
9110 #define CSL_EVETPCC_EESR_RN_E8_SHIFT (8U)
9111 #define CSL_EVETPCC_EESR_RN_E8_RESETVAL (0x00000000U)
9112 #define CSL_EVETPCC_EESR_RN_E8_MAX (0x00000001U)
9114 #define CSL_EVETPCC_EESR_RN_E9_MASK (0x00000200U)
9115 #define CSL_EVETPCC_EESR_RN_E9_SHIFT (9U)
9116 #define CSL_EVETPCC_EESR_RN_E9_RESETVAL (0x00000000U)
9117 #define CSL_EVETPCC_EESR_RN_E9_MAX (0x00000001U)
9119 #define CSL_EVETPCC_EESR_RN_E25_MASK (0x02000000U)
9120 #define CSL_EVETPCC_EESR_RN_E25_SHIFT (25U)
9121 #define CSL_EVETPCC_EESR_RN_E25_RESETVAL (0x00000000U)
9122 #define CSL_EVETPCC_EESR_RN_E25_MAX (0x00000001U)
9124 #define CSL_EVETPCC_EESR_RN_E24_MASK (0x01000000U)
9125 #define CSL_EVETPCC_EESR_RN_E24_SHIFT (24U)
9126 #define CSL_EVETPCC_EESR_RN_E24_RESETVAL (0x00000000U)
9127 #define CSL_EVETPCC_EESR_RN_E24_MAX (0x00000001U)
9129 #define CSL_EVETPCC_EESR_RN_E11_MASK (0x00000800U)
9130 #define CSL_EVETPCC_EESR_RN_E11_SHIFT (11U)
9131 #define CSL_EVETPCC_EESR_RN_E11_RESETVAL (0x00000000U)
9132 #define CSL_EVETPCC_EESR_RN_E11_MAX (0x00000001U)
9134 #define CSL_EVETPCC_EESR_RN_E23_MASK (0x00800000U)
9135 #define CSL_EVETPCC_EESR_RN_E23_SHIFT (23U)
9136 #define CSL_EVETPCC_EESR_RN_E23_RESETVAL (0x00000000U)
9137 #define CSL_EVETPCC_EESR_RN_E23_MAX (0x00000001U)
9139 #define CSL_EVETPCC_EESR_RN_E20_MASK (0x00100000U)
9140 #define CSL_EVETPCC_EESR_RN_E20_SHIFT (20U)
9141 #define CSL_EVETPCC_EESR_RN_E20_RESETVAL (0x00000000U)
9142 #define CSL_EVETPCC_EESR_RN_E20_MAX (0x00000001U)
9144 #define CSL_EVETPCC_EESR_RN_E22_MASK (0x00400000U)
9145 #define CSL_EVETPCC_EESR_RN_E22_SHIFT (22U)
9146 #define CSL_EVETPCC_EESR_RN_E22_RESETVAL (0x00000000U)
9147 #define CSL_EVETPCC_EESR_RN_E22_MAX (0x00000001U)
9149 #define CSL_EVETPCC_EESR_RN_E21_MASK (0x00200000U)
9150 #define CSL_EVETPCC_EESR_RN_E21_SHIFT (21U)
9151 #define CSL_EVETPCC_EESR_RN_E21_RESETVAL (0x00000000U)
9152 #define CSL_EVETPCC_EESR_RN_E21_MAX (0x00000001U)
9154 #define CSL_EVETPCC_EESR_RN_E2_MASK (0x00000004U)
9155 #define CSL_EVETPCC_EESR_RN_E2_SHIFT (2U)
9156 #define CSL_EVETPCC_EESR_RN_E2_RESETVAL (0x00000000U)
9157 #define CSL_EVETPCC_EESR_RN_E2_MAX (0x00000001U)
9159 #define CSL_EVETPCC_EESR_RN_E18_MASK (0x00040000U)
9160 #define CSL_EVETPCC_EESR_RN_E18_SHIFT (18U)
9161 #define CSL_EVETPCC_EESR_RN_E18_RESETVAL (0x00000000U)
9162 #define CSL_EVETPCC_EESR_RN_E18_MAX (0x00000001U)
9164 #define CSL_EVETPCC_EESR_RN_E3_MASK (0x00000008U)
9165 #define CSL_EVETPCC_EESR_RN_E3_SHIFT (3U)
9166 #define CSL_EVETPCC_EESR_RN_E3_RESETVAL (0x00000000U)
9167 #define CSL_EVETPCC_EESR_RN_E3_MAX (0x00000001U)
9169 #define CSL_EVETPCC_EESR_RN_E19_MASK (0x00080000U)
9170 #define CSL_EVETPCC_EESR_RN_E19_SHIFT (19U)
9171 #define CSL_EVETPCC_EESR_RN_E19_RESETVAL (0x00000000U)
9172 #define CSL_EVETPCC_EESR_RN_E19_MAX (0x00000001U)
9174 #define CSL_EVETPCC_EESR_RN_E31_MASK (0x80000000U)
9175 #define CSL_EVETPCC_EESR_RN_E31_SHIFT (31U)
9176 #define CSL_EVETPCC_EESR_RN_E31_RESETVAL (0x00000000U)
9177 #define CSL_EVETPCC_EESR_RN_E31_MAX (0x00000001U)
9179 #define CSL_EVETPCC_EESR_RN_E13_MASK (0x00002000U)
9180 #define CSL_EVETPCC_EESR_RN_E13_SHIFT (13U)
9181 #define CSL_EVETPCC_EESR_RN_E13_RESETVAL (0x00000000U)
9182 #define CSL_EVETPCC_EESR_RN_E13_MAX (0x00000001U)
9184 #define CSL_EVETPCC_EESR_RN_E12_MASK (0x00001000U)
9185 #define CSL_EVETPCC_EESR_RN_E12_SHIFT (12U)
9186 #define CSL_EVETPCC_EESR_RN_E12_RESETVAL (0x00000000U)
9187 #define CSL_EVETPCC_EESR_RN_E12_MAX (0x00000001U)
9189 #define CSL_EVETPCC_EESR_RN_E14_MASK (0x00004000U)
9190 #define CSL_EVETPCC_EESR_RN_E14_SHIFT (14U)
9191 #define CSL_EVETPCC_EESR_RN_E14_RESETVAL (0x00000000U)
9192 #define CSL_EVETPCC_EESR_RN_E14_MAX (0x00000001U)
9194 #define CSL_EVETPCC_EESR_RN_E1_MASK (0x00000002U)
9195 #define CSL_EVETPCC_EESR_RN_E1_SHIFT (1U)
9196 #define CSL_EVETPCC_EESR_RN_E1_RESETVAL (0x00000000U)
9197 #define CSL_EVETPCC_EESR_RN_E1_MAX (0x00000001U)
9199 #define CSL_EVETPCC_EESR_RN_E17_MASK (0x00020000U)
9200 #define CSL_EVETPCC_EESR_RN_E17_SHIFT (17U)
9201 #define CSL_EVETPCC_EESR_RN_E17_RESETVAL (0x00000000U)
9202 #define CSL_EVETPCC_EESR_RN_E17_MAX (0x00000001U)
9204 #define CSL_EVETPCC_EESR_RN_RESETVAL (0x00000000U)
9206 /* QER_RN */
9208 #define CSL_EVETPCC_QER_RN_E7_MASK (0x00000080U)
9209 #define CSL_EVETPCC_QER_RN_E7_SHIFT (7U)
9210 #define CSL_EVETPCC_QER_RN_E7_RESETVAL (0x00000000U)
9211 #define CSL_EVETPCC_QER_RN_E7_MAX (0x00000001U)
9213 #define CSL_EVETPCC_QER_RN_E6_MASK (0x00000040U)
9214 #define CSL_EVETPCC_QER_RN_E6_SHIFT (6U)
9215 #define CSL_EVETPCC_QER_RN_E6_RESETVAL (0x00000000U)
9216 #define CSL_EVETPCC_QER_RN_E6_MAX (0x00000001U)
9218 #define CSL_EVETPCC_QER_RN_E5_MASK (0x00000020U)
9219 #define CSL_EVETPCC_QER_RN_E5_SHIFT (5U)
9220 #define CSL_EVETPCC_QER_RN_E5_RESETVAL (0x00000000U)
9221 #define CSL_EVETPCC_QER_RN_E5_MAX (0x00000001U)
9223 #define CSL_EVETPCC_QER_RN_E3_MASK (0x00000008U)
9224 #define CSL_EVETPCC_QER_RN_E3_SHIFT (3U)
9225 #define CSL_EVETPCC_QER_RN_E3_RESETVAL (0x00000000U)
9226 #define CSL_EVETPCC_QER_RN_E3_MAX (0x00000001U)
9228 #define CSL_EVETPCC_QER_RN_E4_MASK (0x00000010U)
9229 #define CSL_EVETPCC_QER_RN_E4_SHIFT (4U)
9230 #define CSL_EVETPCC_QER_RN_E4_RESETVAL (0x00000000U)
9231 #define CSL_EVETPCC_QER_RN_E4_MAX (0x00000001U)
9233 #define CSL_EVETPCC_QER_RN_E1_MASK (0x00000002U)
9234 #define CSL_EVETPCC_QER_RN_E1_SHIFT (1U)
9235 #define CSL_EVETPCC_QER_RN_E1_RESETVAL (0x00000000U)
9236 #define CSL_EVETPCC_QER_RN_E1_MAX (0x00000001U)
9238 #define CSL_EVETPCC_QER_RN_E2_MASK (0x00000004U)
9239 #define CSL_EVETPCC_QER_RN_E2_SHIFT (2U)
9240 #define CSL_EVETPCC_QER_RN_E2_RESETVAL (0x00000000U)
9241 #define CSL_EVETPCC_QER_RN_E2_MAX (0x00000001U)
9243 #define CSL_EVETPCC_QER_RN_E0_MASK (0x00000001U)
9244 #define CSL_EVETPCC_QER_RN_E0_SHIFT (0U)
9245 #define CSL_EVETPCC_QER_RN_E0_RESETVAL (0x00000000U)
9246 #define CSL_EVETPCC_QER_RN_E0_MAX (0x00000001U)
9248 #define CSL_EVETPCC_QER_RN_RESETVAL (0x00000000U)
9250 /* SECRH_RN */
9252 #define CSL_EVETPCC_SECRH_RN_E34_MASK (0x00000004U)
9253 #define CSL_EVETPCC_SECRH_RN_E34_SHIFT (2U)
9254 #define CSL_EVETPCC_SECRH_RN_E34_RESETVAL (0x00000000U)
9255 #define CSL_EVETPCC_SECRH_RN_E34_MAX (0x00000001U)
9257 #define CSL_EVETPCC_SECRH_RN_E44_MASK (0x00001000U)
9258 #define CSL_EVETPCC_SECRH_RN_E44_SHIFT (12U)
9259 #define CSL_EVETPCC_SECRH_RN_E44_RESETVAL (0x00000000U)
9260 #define CSL_EVETPCC_SECRH_RN_E44_MAX (0x00000001U)
9262 #define CSL_EVETPCC_SECRH_RN_E54_MASK (0x00400000U)
9263 #define CSL_EVETPCC_SECRH_RN_E54_SHIFT (22U)
9264 #define CSL_EVETPCC_SECRH_RN_E54_RESETVAL (0x00000000U)
9265 #define CSL_EVETPCC_SECRH_RN_E54_MAX (0x00000001U)
9267 #define CSL_EVETPCC_SECRH_RN_E33_MASK (0x00000002U)
9268 #define CSL_EVETPCC_SECRH_RN_E33_SHIFT (1U)
9269 #define CSL_EVETPCC_SECRH_RN_E33_RESETVAL (0x00000000U)
9270 #define CSL_EVETPCC_SECRH_RN_E33_MAX (0x00000001U)
9272 #define CSL_EVETPCC_SECRH_RN_E43_MASK (0x00000800U)
9273 #define CSL_EVETPCC_SECRH_RN_E43_SHIFT (11U)
9274 #define CSL_EVETPCC_SECRH_RN_E43_RESETVAL (0x00000000U)
9275 #define CSL_EVETPCC_SECRH_RN_E43_MAX (0x00000001U)
9277 #define CSL_EVETPCC_SECRH_RN_E53_MASK (0x00200000U)
9278 #define CSL_EVETPCC_SECRH_RN_E53_SHIFT (21U)
9279 #define CSL_EVETPCC_SECRH_RN_E53_RESETVAL (0x00000000U)
9280 #define CSL_EVETPCC_SECRH_RN_E53_MAX (0x00000001U)
9282 #define CSL_EVETPCC_SECRH_RN_E58_MASK (0x04000000U)
9283 #define CSL_EVETPCC_SECRH_RN_E58_SHIFT (26U)
9284 #define CSL_EVETPCC_SECRH_RN_E58_RESETVAL (0x00000000U)
9285 #define CSL_EVETPCC_SECRH_RN_E58_MAX (0x00000001U)
9287 #define CSL_EVETPCC_SECRH_RN_E32_MASK (0x00000001U)
9288 #define CSL_EVETPCC_SECRH_RN_E32_SHIFT (0U)
9289 #define CSL_EVETPCC_SECRH_RN_E32_RESETVAL (0x00000000U)
9290 #define CSL_EVETPCC_SECRH_RN_E32_MAX (0x00000001U)
9292 #define CSL_EVETPCC_SECRH_RN_E63_MASK (0x80000000U)
9293 #define CSL_EVETPCC_SECRH_RN_E63_SHIFT (31U)
9294 #define CSL_EVETPCC_SECRH_RN_E63_RESETVAL (0x00000000U)
9295 #define CSL_EVETPCC_SECRH_RN_E63_MAX (0x00000001U)
9297 #define CSL_EVETPCC_SECRH_RN_E57_MASK (0x02000000U)
9298 #define CSL_EVETPCC_SECRH_RN_E57_SHIFT (25U)
9299 #define CSL_EVETPCC_SECRH_RN_E57_RESETVAL (0x00000000U)
9300 #define CSL_EVETPCC_SECRH_RN_E57_MAX (0x00000001U)
9302 #define CSL_EVETPCC_SECRH_RN_E56_MASK (0x01000000U)
9303 #define CSL_EVETPCC_SECRH_RN_E56_SHIFT (24U)
9304 #define CSL_EVETPCC_SECRH_RN_E56_RESETVAL (0x00000000U)
9305 #define CSL_EVETPCC_SECRH_RN_E56_MAX (0x00000001U)
9307 #define CSL_EVETPCC_SECRH_RN_E55_MASK (0x00800000U)
9308 #define CSL_EVETPCC_SECRH_RN_E55_SHIFT (23U)
9309 #define CSL_EVETPCC_SECRH_RN_E55_RESETVAL (0x00000000U)
9310 #define CSL_EVETPCC_SECRH_RN_E55_MAX (0x00000001U)
9312 #define CSL_EVETPCC_SECRH_RN_E52_MASK (0x00100000U)
9313 #define CSL_EVETPCC_SECRH_RN_E52_SHIFT (20U)
9314 #define CSL_EVETPCC_SECRH_RN_E52_RESETVAL (0x00000000U)
9315 #define CSL_EVETPCC_SECRH_RN_E52_MAX (0x00000001U)
9317 #define CSL_EVETPCC_SECRH_RN_E42_MASK (0x00000400U)
9318 #define CSL_EVETPCC_SECRH_RN_E42_SHIFT (10U)
9319 #define CSL_EVETPCC_SECRH_RN_E42_RESETVAL (0x00000000U)
9320 #define CSL_EVETPCC_SECRH_RN_E42_MAX (0x00000001U)
9322 #define CSL_EVETPCC_SECRH_RN_E51_MASK (0x00080000U)
9323 #define CSL_EVETPCC_SECRH_RN_E51_SHIFT (19U)
9324 #define CSL_EVETPCC_SECRH_RN_E51_RESETVAL (0x00000000U)
9325 #define CSL_EVETPCC_SECRH_RN_E51_MAX (0x00000001U)
9327 #define CSL_EVETPCC_SECRH_RN_E41_MASK (0x00000200U)
9328 #define CSL_EVETPCC_SECRH_RN_E41_SHIFT (9U)
9329 #define CSL_EVETPCC_SECRH_RN_E41_RESETVAL (0x00000000U)
9330 #define CSL_EVETPCC_SECRH_RN_E41_MAX (0x00000001U)
9332 #define CSL_EVETPCC_SECRH_RN_E50_MASK (0x00040000U)
9333 #define CSL_EVETPCC_SECRH_RN_E50_SHIFT (18U)
9334 #define CSL_EVETPCC_SECRH_RN_E50_RESETVAL (0x00000000U)
9335 #define CSL_EVETPCC_SECRH_RN_E50_MAX (0x00000001U)
9337 #define CSL_EVETPCC_SECRH_RN_E40_MASK (0x00000100U)
9338 #define CSL_EVETPCC_SECRH_RN_E40_SHIFT (8U)
9339 #define CSL_EVETPCC_SECRH_RN_E40_RESETVAL (0x00000000U)
9340 #define CSL_EVETPCC_SECRH_RN_E40_MAX (0x00000001U)
9342 #define CSL_EVETPCC_SECRH_RN_E49_MASK (0x00020000U)
9343 #define CSL_EVETPCC_SECRH_RN_E49_SHIFT (17U)
9344 #define CSL_EVETPCC_SECRH_RN_E49_RESETVAL (0x00000000U)
9345 #define CSL_EVETPCC_SECRH_RN_E49_MAX (0x00000001U)
9347 #define CSL_EVETPCC_SECRH_RN_E39_MASK (0x00000080U)
9348 #define CSL_EVETPCC_SECRH_RN_E39_SHIFT (7U)
9349 #define CSL_EVETPCC_SECRH_RN_E39_RESETVAL (0x00000000U)
9350 #define CSL_EVETPCC_SECRH_RN_E39_MAX (0x00000001U)
9352 #define CSL_EVETPCC_SECRH_RN_E48_MASK (0x00010000U)
9353 #define CSL_EVETPCC_SECRH_RN_E48_SHIFT (16U)
9354 #define CSL_EVETPCC_SECRH_RN_E48_RESETVAL (0x00000000U)
9355 #define CSL_EVETPCC_SECRH_RN_E48_MAX (0x00000001U)
9357 #define CSL_EVETPCC_SECRH_RN_E38_MASK (0x00000040U)
9358 #define CSL_EVETPCC_SECRH_RN_E38_SHIFT (6U)
9359 #define CSL_EVETPCC_SECRH_RN_E38_RESETVAL (0x00000000U)
9360 #define CSL_EVETPCC_SECRH_RN_E38_MAX (0x00000001U)
9362 #define CSL_EVETPCC_SECRH_RN_E59_MASK (0x08000000U)
9363 #define CSL_EVETPCC_SECRH_RN_E59_SHIFT (27U)
9364 #define CSL_EVETPCC_SECRH_RN_E59_RESETVAL (0x00000000U)
9365 #define CSL_EVETPCC_SECRH_RN_E59_MAX (0x00000001U)
9367 #define CSL_EVETPCC_SECRH_RN_E47_MASK (0x00008000U)
9368 #define CSL_EVETPCC_SECRH_RN_E47_SHIFT (15U)
9369 #define CSL_EVETPCC_SECRH_RN_E47_RESETVAL (0x00000000U)
9370 #define CSL_EVETPCC_SECRH_RN_E47_MAX (0x00000001U)
9372 #define CSL_EVETPCC_SECRH_RN_E37_MASK (0x00000020U)
9373 #define CSL_EVETPCC_SECRH_RN_E37_SHIFT (5U)
9374 #define CSL_EVETPCC_SECRH_RN_E37_RESETVAL (0x00000000U)
9375 #define CSL_EVETPCC_SECRH_RN_E37_MAX (0x00000001U)
9377 #define CSL_EVETPCC_SECRH_RN_E60_MASK (0x10000000U)
9378 #define CSL_EVETPCC_SECRH_RN_E60_SHIFT (28U)
9379 #define CSL_EVETPCC_SECRH_RN_E60_RESETVAL (0x00000000U)
9380 #define CSL_EVETPCC_SECRH_RN_E60_MAX (0x00000001U)
9382 #define CSL_EVETPCC_SECRH_RN_E36_MASK (0x00000010U)
9383 #define CSL_EVETPCC_SECRH_RN_E36_SHIFT (4U)
9384 #define CSL_EVETPCC_SECRH_RN_E36_RESETVAL (0x00000000U)
9385 #define CSL_EVETPCC_SECRH_RN_E36_MAX (0x00000001U)
9387 #define CSL_EVETPCC_SECRH_RN_E46_MASK (0x00004000U)
9388 #define CSL_EVETPCC_SECRH_RN_E46_SHIFT (14U)
9389 #define CSL_EVETPCC_SECRH_RN_E46_RESETVAL (0x00000000U)
9390 #define CSL_EVETPCC_SECRH_RN_E46_MAX (0x00000001U)
9392 #define CSL_EVETPCC_SECRH_RN_E61_MASK (0x20000000U)
9393 #define CSL_EVETPCC_SECRH_RN_E61_SHIFT (29U)
9394 #define CSL_EVETPCC_SECRH_RN_E61_RESETVAL (0x00000000U)
9395 #define CSL_EVETPCC_SECRH_RN_E61_MAX (0x00000001U)
9397 #define CSL_EVETPCC_SECRH_RN_E35_MASK (0x00000008U)
9398 #define CSL_EVETPCC_SECRH_RN_E35_SHIFT (3U)
9399 #define CSL_EVETPCC_SECRH_RN_E35_RESETVAL (0x00000000U)
9400 #define CSL_EVETPCC_SECRH_RN_E35_MAX (0x00000001U)
9402 #define CSL_EVETPCC_SECRH_RN_E62_MASK (0x40000000U)
9403 #define CSL_EVETPCC_SECRH_RN_E62_SHIFT (30U)
9404 #define CSL_EVETPCC_SECRH_RN_E62_RESETVAL (0x00000000U)
9405 #define CSL_EVETPCC_SECRH_RN_E62_MAX (0x00000001U)
9407 #define CSL_EVETPCC_SECRH_RN_E45_MASK (0x00002000U)
9408 #define CSL_EVETPCC_SECRH_RN_E45_SHIFT (13U)
9409 #define CSL_EVETPCC_SECRH_RN_E45_RESETVAL (0x00000000U)
9410 #define CSL_EVETPCC_SECRH_RN_E45_MAX (0x00000001U)
9412 #define CSL_EVETPCC_SECRH_RN_RESETVAL (0x00000000U)
9414 /* EESRH_RN */
9416 #define CSL_EVETPCC_EESRH_RN_E33_MASK (0x00000002U)
9417 #define CSL_EVETPCC_EESRH_RN_E33_SHIFT (1U)
9418 #define CSL_EVETPCC_EESRH_RN_E33_RESETVAL (0x00000000U)
9419 #define CSL_EVETPCC_EESRH_RN_E33_MAX (0x00000001U)
9421 #define CSL_EVETPCC_EESRH_RN_E35_MASK (0x00000008U)
9422 #define CSL_EVETPCC_EESRH_RN_E35_SHIFT (3U)
9423 #define CSL_EVETPCC_EESRH_RN_E35_RESETVAL (0x00000000U)
9424 #define CSL_EVETPCC_EESRH_RN_E35_MAX (0x00000001U)
9426 #define CSL_EVETPCC_EESRH_RN_E44_MASK (0x00001000U)
9427 #define CSL_EVETPCC_EESRH_RN_E44_SHIFT (12U)
9428 #define CSL_EVETPCC_EESRH_RN_E44_RESETVAL (0x00000000U)
9429 #define CSL_EVETPCC_EESRH_RN_E44_MAX (0x00000001U)
9431 #define CSL_EVETPCC_EESRH_RN_E32_MASK (0x00000001U)
9432 #define CSL_EVETPCC_EESRH_RN_E32_SHIFT (0U)
9433 #define CSL_EVETPCC_EESRH_RN_E32_RESETVAL (0x00000000U)
9434 #define CSL_EVETPCC_EESRH_RN_E32_MAX (0x00000001U)
9436 #define CSL_EVETPCC_EESRH_RN_E43_MASK (0x00000800U)
9437 #define CSL_EVETPCC_EESRH_RN_E43_SHIFT (11U)
9438 #define CSL_EVETPCC_EESRH_RN_E43_RESETVAL (0x00000000U)
9439 #define CSL_EVETPCC_EESRH_RN_E43_MAX (0x00000001U)
9441 #define CSL_EVETPCC_EESRH_RN_E55_MASK (0x00800000U)
9442 #define CSL_EVETPCC_EESRH_RN_E55_SHIFT (23U)
9443 #define CSL_EVETPCC_EESRH_RN_E55_RESETVAL (0x00000000U)
9444 #define CSL_EVETPCC_EESRH_RN_E55_MAX (0x00000001U)
9446 #define CSL_EVETPCC_EESRH_RN_E42_MASK (0x00000400U)
9447 #define CSL_EVETPCC_EESRH_RN_E42_SHIFT (10U)
9448 #define CSL_EVETPCC_EESRH_RN_E42_RESETVAL (0x00000000U)
9449 #define CSL_EVETPCC_EESRH_RN_E42_MAX (0x00000001U)
9451 #define CSL_EVETPCC_EESRH_RN_E54_MASK (0x00400000U)
9452 #define CSL_EVETPCC_EESRH_RN_E54_SHIFT (22U)
9453 #define CSL_EVETPCC_EESRH_RN_E54_RESETVAL (0x00000000U)
9454 #define CSL_EVETPCC_EESRH_RN_E54_MAX (0x00000001U)
9456 #define CSL_EVETPCC_EESRH_RN_E53_MASK (0x00200000U)
9457 #define CSL_EVETPCC_EESRH_RN_E53_SHIFT (21U)
9458 #define CSL_EVETPCC_EESRH_RN_E53_RESETVAL (0x00000000U)
9459 #define CSL_EVETPCC_EESRH_RN_E53_MAX (0x00000001U)
9461 #define CSL_EVETPCC_EESRH_RN_E56_MASK (0x01000000U)
9462 #define CSL_EVETPCC_EESRH_RN_E56_SHIFT (24U)
9463 #define CSL_EVETPCC_EESRH_RN_E56_RESETVAL (0x00000000U)
9464 #define CSL_EVETPCC_EESRH_RN_E56_MAX (0x00000001U)
9466 #define CSL_EVETPCC_EESRH_RN_E41_MASK (0x00000200U)
9467 #define CSL_EVETPCC_EESRH_RN_E41_SHIFT (9U)
9468 #define CSL_EVETPCC_EESRH_RN_E41_RESETVAL (0x00000000U)
9469 #define CSL_EVETPCC_EESRH_RN_E41_MAX (0x00000001U)
9471 #define CSL_EVETPCC_EESRH_RN_E40_MASK (0x00000100U)
9472 #define CSL_EVETPCC_EESRH_RN_E40_SHIFT (8U)
9473 #define CSL_EVETPCC_EESRH_RN_E40_RESETVAL (0x00000000U)
9474 #define CSL_EVETPCC_EESRH_RN_E40_MAX (0x00000001U)
9476 #define CSL_EVETPCC_EESRH_RN_E57_MASK (0x02000000U)
9477 #define CSL_EVETPCC_EESRH_RN_E57_SHIFT (25U)
9478 #define CSL_EVETPCC_EESRH_RN_E57_RESETVAL (0x00000000U)
9479 #define CSL_EVETPCC_EESRH_RN_E57_MAX (0x00000001U)
9481 #define CSL_EVETPCC_EESRH_RN_E52_MASK (0x00100000U)
9482 #define CSL_EVETPCC_EESRH_RN_E52_SHIFT (20U)
9483 #define CSL_EVETPCC_EESRH_RN_E52_RESETVAL (0x00000000U)
9484 #define CSL_EVETPCC_EESRH_RN_E52_MAX (0x00000001U)
9486 #define CSL_EVETPCC_EESRH_RN_E34_MASK (0x00000004U)
9487 #define CSL_EVETPCC_EESRH_RN_E34_SHIFT (2U)
9488 #define CSL_EVETPCC_EESRH_RN_E34_RESETVAL (0x00000000U)
9489 #define CSL_EVETPCC_EESRH_RN_E34_MAX (0x00000001U)
9491 #define CSL_EVETPCC_EESRH_RN_E39_MASK (0x00000080U)
9492 #define CSL_EVETPCC_EESRH_RN_E39_SHIFT (7U)
9493 #define CSL_EVETPCC_EESRH_RN_E39_RESETVAL (0x00000000U)
9494 #define CSL_EVETPCC_EESRH_RN_E39_MAX (0x00000001U)
9496 #define CSL_EVETPCC_EESRH_RN_E58_MASK (0x04000000U)
9497 #define CSL_EVETPCC_EESRH_RN_E58_SHIFT (26U)
9498 #define CSL_EVETPCC_EESRH_RN_E58_RESETVAL (0x00000000U)
9499 #define CSL_EVETPCC_EESRH_RN_E58_MAX (0x00000001U)
9501 #define CSL_EVETPCC_EESRH_RN_E51_MASK (0x00080000U)
9502 #define CSL_EVETPCC_EESRH_RN_E51_SHIFT (19U)
9503 #define CSL_EVETPCC_EESRH_RN_E51_RESETVAL (0x00000000U)
9504 #define CSL_EVETPCC_EESRH_RN_E51_MAX (0x00000001U)
9506 #define CSL_EVETPCC_EESRH_RN_E36_MASK (0x00000010U)
9507 #define CSL_EVETPCC_EESRH_RN_E36_SHIFT (4U)
9508 #define CSL_EVETPCC_EESRH_RN_E36_RESETVAL (0x00000000U)
9509 #define CSL_EVETPCC_EESRH_RN_E36_MAX (0x00000001U)
9511 #define CSL_EVETPCC_EESRH_RN_E38_MASK (0x00000040U)
9512 #define CSL_EVETPCC_EESRH_RN_E38_SHIFT (6U)
9513 #define CSL_EVETPCC_EESRH_RN_E38_RESETVAL (0x00000000U)
9514 #define CSL_EVETPCC_EESRH_RN_E38_MAX (0x00000001U)
9516 #define CSL_EVETPCC_EESRH_RN_E59_MASK (0x08000000U)
9517 #define CSL_EVETPCC_EESRH_RN_E59_SHIFT (27U)
9518 #define CSL_EVETPCC_EESRH_RN_E59_RESETVAL (0x00000000U)
9519 #define CSL_EVETPCC_EESRH_RN_E59_MAX (0x00000001U)
9521 #define CSL_EVETPCC_EESRH_RN_E50_MASK (0x00040000U)
9522 #define CSL_EVETPCC_EESRH_RN_E50_SHIFT (18U)
9523 #define CSL_EVETPCC_EESRH_RN_E50_RESETVAL (0x00000000U)
9524 #define CSL_EVETPCC_EESRH_RN_E50_MAX (0x00000001U)
9526 #define CSL_EVETPCC_EESRH_RN_E37_MASK (0x00000020U)
9527 #define CSL_EVETPCC_EESRH_RN_E37_SHIFT (5U)
9528 #define CSL_EVETPCC_EESRH_RN_E37_RESETVAL (0x00000000U)
9529 #define CSL_EVETPCC_EESRH_RN_E37_MAX (0x00000001U)
9531 #define CSL_EVETPCC_EESRH_RN_E60_MASK (0x10000000U)
9532 #define CSL_EVETPCC_EESRH_RN_E60_SHIFT (28U)
9533 #define CSL_EVETPCC_EESRH_RN_E60_RESETVAL (0x00000000U)
9534 #define CSL_EVETPCC_EESRH_RN_E60_MAX (0x00000001U)
9536 #define CSL_EVETPCC_EESRH_RN_E49_MASK (0x00020000U)
9537 #define CSL_EVETPCC_EESRH_RN_E49_SHIFT (17U)
9538 #define CSL_EVETPCC_EESRH_RN_E49_RESETVAL (0x00000000U)
9539 #define CSL_EVETPCC_EESRH_RN_E49_MAX (0x00000001U)
9541 #define CSL_EVETPCC_EESRH_RN_E61_MASK (0x20000000U)
9542 #define CSL_EVETPCC_EESRH_RN_E61_SHIFT (29U)
9543 #define CSL_EVETPCC_EESRH_RN_E61_RESETVAL (0x00000000U)
9544 #define CSL_EVETPCC_EESRH_RN_E61_MAX (0x00000001U)
9546 #define CSL_EVETPCC_EESRH_RN_E48_MASK (0x00010000U)
9547 #define CSL_EVETPCC_EESRH_RN_E48_SHIFT (16U)
9548 #define CSL_EVETPCC_EESRH_RN_E48_RESETVAL (0x00000000U)
9549 #define CSL_EVETPCC_EESRH_RN_E48_MAX (0x00000001U)
9551 #define CSL_EVETPCC_EESRH_RN_E62_MASK (0x40000000U)
9552 #define CSL_EVETPCC_EESRH_RN_E62_SHIFT (30U)
9553 #define CSL_EVETPCC_EESRH_RN_E62_RESETVAL (0x00000000U)
9554 #define CSL_EVETPCC_EESRH_RN_E62_MAX (0x00000001U)
9556 #define CSL_EVETPCC_EESRH_RN_E47_MASK (0x00008000U)
9557 #define CSL_EVETPCC_EESRH_RN_E47_SHIFT (15U)
9558 #define CSL_EVETPCC_EESRH_RN_E47_RESETVAL (0x00000000U)
9559 #define CSL_EVETPCC_EESRH_RN_E47_MAX (0x00000001U)
9561 #define CSL_EVETPCC_EESRH_RN_E63_MASK (0x80000000U)
9562 #define CSL_EVETPCC_EESRH_RN_E63_SHIFT (31U)
9563 #define CSL_EVETPCC_EESRH_RN_E63_RESETVAL (0x00000000U)
9564 #define CSL_EVETPCC_EESRH_RN_E63_MAX (0x00000001U)
9566 #define CSL_EVETPCC_EESRH_RN_E46_MASK (0x00004000U)
9567 #define CSL_EVETPCC_EESRH_RN_E46_SHIFT (14U)
9568 #define CSL_EVETPCC_EESRH_RN_E46_RESETVAL (0x00000000U)
9569 #define CSL_EVETPCC_EESRH_RN_E46_MAX (0x00000001U)
9571 #define CSL_EVETPCC_EESRH_RN_E45_MASK (0x00002000U)
9572 #define CSL_EVETPCC_EESRH_RN_E45_SHIFT (13U)
9573 #define CSL_EVETPCC_EESRH_RN_E45_RESETVAL (0x00000000U)
9574 #define CSL_EVETPCC_EESRH_RN_E45_MAX (0x00000001U)
9576 #define CSL_EVETPCC_EESRH_RN_RESETVAL (0x00000000U)
9578 /* IER_RN */
9580 #define CSL_EVETPCC_IER_RN_I15_MASK (0x00008000U)
9581 #define CSL_EVETPCC_IER_RN_I15_SHIFT (15U)
9582 #define CSL_EVETPCC_IER_RN_I15_RESETVAL (0x00000000U)
9583 #define CSL_EVETPCC_IER_RN_I15_MAX (0x00000001U)
9585 #define CSL_EVETPCC_IER_RN_I30_MASK (0x40000000U)
9586 #define CSL_EVETPCC_IER_RN_I30_SHIFT (30U)
9587 #define CSL_EVETPCC_IER_RN_I30_RESETVAL (0x00000000U)
9588 #define CSL_EVETPCC_IER_RN_I30_MAX (0x00000001U)
9590 #define CSL_EVETPCC_IER_RN_I14_MASK (0x00004000U)
9591 #define CSL_EVETPCC_IER_RN_I14_SHIFT (14U)
9592 #define CSL_EVETPCC_IER_RN_I14_RESETVAL (0x00000000U)
9593 #define CSL_EVETPCC_IER_RN_I14_MAX (0x00000001U)
9595 #define CSL_EVETPCC_IER_RN_I29_MASK (0x20000000U)
9596 #define CSL_EVETPCC_IER_RN_I29_SHIFT (29U)
9597 #define CSL_EVETPCC_IER_RN_I29_RESETVAL (0x00000000U)
9598 #define CSL_EVETPCC_IER_RN_I29_MAX (0x00000001U)
9600 #define CSL_EVETPCC_IER_RN_I7_MASK (0x00000080U)
9601 #define CSL_EVETPCC_IER_RN_I7_SHIFT (7U)
9602 #define CSL_EVETPCC_IER_RN_I7_RESETVAL (0x00000000U)
9603 #define CSL_EVETPCC_IER_RN_I7_MAX (0x00000001U)
9605 #define CSL_EVETPCC_IER_RN_I28_MASK (0x10000000U)
9606 #define CSL_EVETPCC_IER_RN_I28_SHIFT (28U)
9607 #define CSL_EVETPCC_IER_RN_I28_RESETVAL (0x00000000U)
9608 #define CSL_EVETPCC_IER_RN_I28_MAX (0x00000001U)
9610 #define CSL_EVETPCC_IER_RN_I17_MASK (0x00020000U)
9611 #define CSL_EVETPCC_IER_RN_I17_SHIFT (17U)
9612 #define CSL_EVETPCC_IER_RN_I17_RESETVAL (0x00000000U)
9613 #define CSL_EVETPCC_IER_RN_I17_MAX (0x00000001U)
9615 #define CSL_EVETPCC_IER_RN_I16_MASK (0x00010000U)
9616 #define CSL_EVETPCC_IER_RN_I16_SHIFT (16U)
9617 #define CSL_EVETPCC_IER_RN_I16_RESETVAL (0x00000000U)
9618 #define CSL_EVETPCC_IER_RN_I16_MAX (0x00000001U)
9620 #define CSL_EVETPCC_IER_RN_I27_MASK (0x08000000U)
9621 #define CSL_EVETPCC_IER_RN_I27_SHIFT (27U)
9622 #define CSL_EVETPCC_IER_RN_I27_RESETVAL (0x00000000U)
9623 #define CSL_EVETPCC_IER_RN_I27_MAX (0x00000001U)
9625 #define CSL_EVETPCC_IER_RN_I0_MASK (0x00000001U)
9626 #define CSL_EVETPCC_IER_RN_I0_SHIFT (0U)
9627 #define CSL_EVETPCC_IER_RN_I0_RESETVAL (0x00000000U)
9628 #define CSL_EVETPCC_IER_RN_I0_MAX (0x00000001U)
9630 #define CSL_EVETPCC_IER_RN_I1_MASK (0x00000002U)
9631 #define CSL_EVETPCC_IER_RN_I1_SHIFT (1U)
9632 #define CSL_EVETPCC_IER_RN_I1_RESETVAL (0x00000000U)
9633 #define CSL_EVETPCC_IER_RN_I1_MAX (0x00000001U)
9635 #define CSL_EVETPCC_IER_RN_I13_MASK (0x00002000U)
9636 #define CSL_EVETPCC_IER_RN_I13_SHIFT (13U)
9637 #define CSL_EVETPCC_IER_RN_I13_RESETVAL (0x00000000U)
9638 #define CSL_EVETPCC_IER_RN_I13_MAX (0x00000001U)
9640 #define CSL_EVETPCC_IER_RN_I2_MASK (0x00000004U)
9641 #define CSL_EVETPCC_IER_RN_I2_SHIFT (2U)
9642 #define CSL_EVETPCC_IER_RN_I2_RESETVAL (0x00000000U)
9643 #define CSL_EVETPCC_IER_RN_I2_MAX (0x00000001U)
9645 #define CSL_EVETPCC_IER_RN_I31_MASK (0x80000000U)
9646 #define CSL_EVETPCC_IER_RN_I31_SHIFT (31U)
9647 #define CSL_EVETPCC_IER_RN_I31_RESETVAL (0x00000000U)
9648 #define CSL_EVETPCC_IER_RN_I31_MAX (0x00000001U)
9650 #define CSL_EVETPCC_IER_RN_I22_MASK (0x00400000U)
9651 #define CSL_EVETPCC_IER_RN_I22_SHIFT (22U)
9652 #define CSL_EVETPCC_IER_RN_I22_RESETVAL (0x00000000U)
9653 #define CSL_EVETPCC_IER_RN_I22_MAX (0x00000001U)
9655 #define CSL_EVETPCC_IER_RN_I3_MASK (0x00000008U)
9656 #define CSL_EVETPCC_IER_RN_I3_SHIFT (3U)
9657 #define CSL_EVETPCC_IER_RN_I3_RESETVAL (0x00000000U)
9658 #define CSL_EVETPCC_IER_RN_I3_MAX (0x00000001U)
9660 #define CSL_EVETPCC_IER_RN_I26_MASK (0x04000000U)
9661 #define CSL_EVETPCC_IER_RN_I26_SHIFT (26U)
9662 #define CSL_EVETPCC_IER_RN_I26_RESETVAL (0x00000000U)
9663 #define CSL_EVETPCC_IER_RN_I26_MAX (0x00000001U)
9665 #define CSL_EVETPCC_IER_RN_I5_MASK (0x00000020U)
9666 #define CSL_EVETPCC_IER_RN_I5_SHIFT (5U)
9667 #define CSL_EVETPCC_IER_RN_I5_RESETVAL (0x00000000U)
9668 #define CSL_EVETPCC_IER_RN_I5_MAX (0x00000001U)
9670 #define CSL_EVETPCC_IER_RN_I19_MASK (0x00080000U)
9671 #define CSL_EVETPCC_IER_RN_I19_SHIFT (19U)
9672 #define CSL_EVETPCC_IER_RN_I19_RESETVAL (0x00000000U)
9673 #define CSL_EVETPCC_IER_RN_I19_MAX (0x00000001U)
9675 #define CSL_EVETPCC_IER_RN_I8_MASK (0x00000100U)
9676 #define CSL_EVETPCC_IER_RN_I8_SHIFT (8U)
9677 #define CSL_EVETPCC_IER_RN_I8_RESETVAL (0x00000000U)
9678 #define CSL_EVETPCC_IER_RN_I8_MAX (0x00000001U)
9680 #define CSL_EVETPCC_IER_RN_I25_MASK (0x02000000U)
9681 #define CSL_EVETPCC_IER_RN_I25_SHIFT (25U)
9682 #define CSL_EVETPCC_IER_RN_I25_RESETVAL (0x00000000U)
9683 #define CSL_EVETPCC_IER_RN_I25_MAX (0x00000001U)
9685 #define CSL_EVETPCC_IER_RN_I4_MASK (0x00000010U)
9686 #define CSL_EVETPCC_IER_RN_I4_SHIFT (4U)
9687 #define CSL_EVETPCC_IER_RN_I4_RESETVAL (0x00000000U)
9688 #define CSL_EVETPCC_IER_RN_I4_MAX (0x00000001U)
9690 #define CSL_EVETPCC_IER_RN_I18_MASK (0x00040000U)
9691 #define CSL_EVETPCC_IER_RN_I18_SHIFT (18U)
9692 #define CSL_EVETPCC_IER_RN_I18_RESETVAL (0x00000000U)
9693 #define CSL_EVETPCC_IER_RN_I18_MAX (0x00000001U)
9695 #define CSL_EVETPCC_IER_RN_I9_MASK (0x00000200U)
9696 #define CSL_EVETPCC_IER_RN_I9_SHIFT (9U)
9697 #define CSL_EVETPCC_IER_RN_I9_RESETVAL (0x00000000U)
9698 #define CSL_EVETPCC_IER_RN_I9_MAX (0x00000001U)
9700 #define CSL_EVETPCC_IER_RN_I21_MASK (0x00200000U)
9701 #define CSL_EVETPCC_IER_RN_I21_SHIFT (21U)
9702 #define CSL_EVETPCC_IER_RN_I21_RESETVAL (0x00000000U)
9703 #define CSL_EVETPCC_IER_RN_I21_MAX (0x00000001U)
9705 #define CSL_EVETPCC_IER_RN_I24_MASK (0x01000000U)
9706 #define CSL_EVETPCC_IER_RN_I24_SHIFT (24U)
9707 #define CSL_EVETPCC_IER_RN_I24_RESETVAL (0x00000000U)
9708 #define CSL_EVETPCC_IER_RN_I24_MAX (0x00000001U)
9710 #define CSL_EVETPCC_IER_RN_I10_MASK (0x00000400U)
9711 #define CSL_EVETPCC_IER_RN_I10_SHIFT (10U)
9712 #define CSL_EVETPCC_IER_RN_I10_RESETVAL (0x00000000U)
9713 #define CSL_EVETPCC_IER_RN_I10_MAX (0x00000001U)
9715 #define CSL_EVETPCC_IER_RN_I12_MASK (0x00001000U)
9716 #define CSL_EVETPCC_IER_RN_I12_SHIFT (12U)
9717 #define CSL_EVETPCC_IER_RN_I12_RESETVAL (0x00000000U)
9718 #define CSL_EVETPCC_IER_RN_I12_MAX (0x00000001U)
9720 #define CSL_EVETPCC_IER_RN_I23_MASK (0x00800000U)
9721 #define CSL_EVETPCC_IER_RN_I23_SHIFT (23U)
9722 #define CSL_EVETPCC_IER_RN_I23_RESETVAL (0x00000000U)
9723 #define CSL_EVETPCC_IER_RN_I23_MAX (0x00000001U)
9725 #define CSL_EVETPCC_IER_RN_I20_MASK (0x00100000U)
9726 #define CSL_EVETPCC_IER_RN_I20_SHIFT (20U)
9727 #define CSL_EVETPCC_IER_RN_I20_RESETVAL (0x00000000U)
9728 #define CSL_EVETPCC_IER_RN_I20_MAX (0x00000001U)
9730 #define CSL_EVETPCC_IER_RN_I6_MASK (0x00000040U)
9731 #define CSL_EVETPCC_IER_RN_I6_SHIFT (6U)
9732 #define CSL_EVETPCC_IER_RN_I6_RESETVAL (0x00000000U)
9733 #define CSL_EVETPCC_IER_RN_I6_MAX (0x00000001U)
9735 #define CSL_EVETPCC_IER_RN_I11_MASK (0x00000800U)
9736 #define CSL_EVETPCC_IER_RN_I11_SHIFT (11U)
9737 #define CSL_EVETPCC_IER_RN_I11_RESETVAL (0x00000000U)
9738 #define CSL_EVETPCC_IER_RN_I11_MAX (0x00000001U)
9740 #define CSL_EVETPCC_IER_RN_RESETVAL (0x00000000U)
9742 /* QEECR_RN */
9744 #define CSL_EVETPCC_QEECR_RN_E3_MASK (0x00000008U)
9745 #define CSL_EVETPCC_QEECR_RN_E3_SHIFT (3U)
9746 #define CSL_EVETPCC_QEECR_RN_E3_RESETVAL (0x00000000U)
9747 #define CSL_EVETPCC_QEECR_RN_E3_MAX (0x00000001U)
9749 #define CSL_EVETPCC_QEECR_RN_E2_MASK (0x00000004U)
9750 #define CSL_EVETPCC_QEECR_RN_E2_SHIFT (2U)
9751 #define CSL_EVETPCC_QEECR_RN_E2_RESETVAL (0x00000000U)
9752 #define CSL_EVETPCC_QEECR_RN_E2_MAX (0x00000001U)
9754 #define CSL_EVETPCC_QEECR_RN_E1_MASK (0x00000002U)
9755 #define CSL_EVETPCC_QEECR_RN_E1_SHIFT (1U)
9756 #define CSL_EVETPCC_QEECR_RN_E1_RESETVAL (0x00000000U)
9757 #define CSL_EVETPCC_QEECR_RN_E1_MAX (0x00000001U)
9759 #define CSL_EVETPCC_QEECR_RN_E4_MASK (0x00000010U)
9760 #define CSL_EVETPCC_QEECR_RN_E4_SHIFT (4U)
9761 #define CSL_EVETPCC_QEECR_RN_E4_RESETVAL (0x00000000U)
9762 #define CSL_EVETPCC_QEECR_RN_E4_MAX (0x00000001U)
9764 #define CSL_EVETPCC_QEECR_RN_E0_MASK (0x00000001U)
9765 #define CSL_EVETPCC_QEECR_RN_E0_SHIFT (0U)
9766 #define CSL_EVETPCC_QEECR_RN_E0_RESETVAL (0x00000000U)
9767 #define CSL_EVETPCC_QEECR_RN_E0_MAX (0x00000001U)
9769 #define CSL_EVETPCC_QEECR_RN_E6_MASK (0x00000040U)
9770 #define CSL_EVETPCC_QEECR_RN_E6_SHIFT (6U)
9771 #define CSL_EVETPCC_QEECR_RN_E6_RESETVAL (0x00000000U)
9772 #define CSL_EVETPCC_QEECR_RN_E6_MAX (0x00000001U)
9774 #define CSL_EVETPCC_QEECR_RN_E5_MASK (0x00000020U)
9775 #define CSL_EVETPCC_QEECR_RN_E5_SHIFT (5U)
9776 #define CSL_EVETPCC_QEECR_RN_E5_RESETVAL (0x00000000U)
9777 #define CSL_EVETPCC_QEECR_RN_E5_MAX (0x00000001U)
9779 #define CSL_EVETPCC_QEECR_RN_E7_MASK (0x00000080U)
9780 #define CSL_EVETPCC_QEECR_RN_E7_SHIFT (7U)
9781 #define CSL_EVETPCC_QEECR_RN_E7_RESETVAL (0x00000000U)
9782 #define CSL_EVETPCC_QEECR_RN_E7_MAX (0x00000001U)
9784 #define CSL_EVETPCC_QEECR_RN_RESETVAL (0x00000000U)
9786 /* EER_RN */
9788 #define CSL_EVETPCC_EER_RN_E11_MASK (0x00000800U)
9789 #define CSL_EVETPCC_EER_RN_E11_SHIFT (11U)
9790 #define CSL_EVETPCC_EER_RN_E11_RESETVAL (0x00000000U)
9791 #define CSL_EVETPCC_EER_RN_E11_MAX (0x00000001U)
9793 #define CSL_EVETPCC_EER_RN_E24_MASK (0x01000000U)
9794 #define CSL_EVETPCC_EER_RN_E24_SHIFT (24U)
9795 #define CSL_EVETPCC_EER_RN_E24_RESETVAL (0x00000000U)
9796 #define CSL_EVETPCC_EER_RN_E24_MAX (0x00000001U)
9798 #define CSL_EVETPCC_EER_RN_E10_MASK (0x00000400U)
9799 #define CSL_EVETPCC_EER_RN_E10_SHIFT (10U)
9800 #define CSL_EVETPCC_EER_RN_E10_RESETVAL (0x00000000U)
9801 #define CSL_EVETPCC_EER_RN_E10_MAX (0x00000001U)
9803 #define CSL_EVETPCC_EER_RN_E12_MASK (0x00001000U)
9804 #define CSL_EVETPCC_EER_RN_E12_SHIFT (12U)
9805 #define CSL_EVETPCC_EER_RN_E12_RESETVAL (0x00000000U)
9806 #define CSL_EVETPCC_EER_RN_E12_MAX (0x00000001U)
9808 #define CSL_EVETPCC_EER_RN_E25_MASK (0x02000000U)
9809 #define CSL_EVETPCC_EER_RN_E25_SHIFT (25U)
9810 #define CSL_EVETPCC_EER_RN_E25_RESETVAL (0x00000000U)
9811 #define CSL_EVETPCC_EER_RN_E25_MAX (0x00000001U)
9813 #define CSL_EVETPCC_EER_RN_E9_MASK (0x00000200U)
9814 #define CSL_EVETPCC_EER_RN_E9_SHIFT (9U)
9815 #define CSL_EVETPCC_EER_RN_E9_RESETVAL (0x00000000U)
9816 #define CSL_EVETPCC_EER_RN_E9_MAX (0x00000001U)
9818 #define CSL_EVETPCC_EER_RN_E21_MASK (0x00200000U)
9819 #define CSL_EVETPCC_EER_RN_E21_SHIFT (21U)
9820 #define CSL_EVETPCC_EER_RN_E21_RESETVAL (0x00000000U)
9821 #define CSL_EVETPCC_EER_RN_E21_MAX (0x00000001U)
9823 #define CSL_EVETPCC_EER_RN_E22_MASK (0x00400000U)
9824 #define CSL_EVETPCC_EER_RN_E22_SHIFT (22U)
9825 #define CSL_EVETPCC_EER_RN_E22_RESETVAL (0x00000000U)
9826 #define CSL_EVETPCC_EER_RN_E22_MAX (0x00000001U)
9828 #define CSL_EVETPCC_EER_RN_E0_MASK (0x00000001U)
9829 #define CSL_EVETPCC_EER_RN_E0_SHIFT (0U)
9830 #define CSL_EVETPCC_EER_RN_E0_RESETVAL (0x00000000U)
9831 #define CSL_EVETPCC_EER_RN_E0_MAX (0x00000001U)
9833 #define CSL_EVETPCC_EER_RN_E23_MASK (0x00800000U)
9834 #define CSL_EVETPCC_EER_RN_E23_SHIFT (23U)
9835 #define CSL_EVETPCC_EER_RN_E23_RESETVAL (0x00000000U)
9836 #define CSL_EVETPCC_EER_RN_E23_MAX (0x00000001U)
9838 #define CSL_EVETPCC_EER_RN_E19_MASK (0x00080000U)
9839 #define CSL_EVETPCC_EER_RN_E19_SHIFT (19U)
9840 #define CSL_EVETPCC_EER_RN_E19_RESETVAL (0x00000000U)
9841 #define CSL_EVETPCC_EER_RN_E19_MAX (0x00000001U)
9843 #define CSL_EVETPCC_EER_RN_E20_MASK (0x00100000U)
9844 #define CSL_EVETPCC_EER_RN_E20_SHIFT (20U)
9845 #define CSL_EVETPCC_EER_RN_E20_RESETVAL (0x00000000U)
9846 #define CSL_EVETPCC_EER_RN_E20_MAX (0x00000001U)
9848 #define CSL_EVETPCC_EER_RN_E29_MASK (0x20000000U)
9849 #define CSL_EVETPCC_EER_RN_E29_SHIFT (29U)
9850 #define CSL_EVETPCC_EER_RN_E29_RESETVAL (0x00000000U)
9851 #define CSL_EVETPCC_EER_RN_E29_MAX (0x00000001U)
9853 #define CSL_EVETPCC_EER_RN_E30_MASK (0x40000000U)
9854 #define CSL_EVETPCC_EER_RN_E30_SHIFT (30U)
9855 #define CSL_EVETPCC_EER_RN_E30_RESETVAL (0x00000000U)
9856 #define CSL_EVETPCC_EER_RN_E30_MAX (0x00000001U)
9858 #define CSL_EVETPCC_EER_RN_E18_MASK (0x00040000U)
9859 #define CSL_EVETPCC_EER_RN_E18_SHIFT (18U)
9860 #define CSL_EVETPCC_EER_RN_E18_RESETVAL (0x00000000U)
9861 #define CSL_EVETPCC_EER_RN_E18_MAX (0x00000001U)
9863 #define CSL_EVETPCC_EER_RN_E31_MASK (0x80000000U)
9864 #define CSL_EVETPCC_EER_RN_E31_SHIFT (31U)
9865 #define CSL_EVETPCC_EER_RN_E31_RESETVAL (0x00000000U)
9866 #define CSL_EVETPCC_EER_RN_E31_MAX (0x00000001U)
9868 #define CSL_EVETPCC_EER_RN_E5_MASK (0x00000020U)
9869 #define CSL_EVETPCC_EER_RN_E5_SHIFT (5U)
9870 #define CSL_EVETPCC_EER_RN_E5_RESETVAL (0x00000000U)
9871 #define CSL_EVETPCC_EER_RN_E5_MAX (0x00000001U)
9873 #define CSL_EVETPCC_EER_RN_E6_MASK (0x00000040U)
9874 #define CSL_EVETPCC_EER_RN_E6_SHIFT (6U)
9875 #define CSL_EVETPCC_EER_RN_E6_RESETVAL (0x00000000U)
9876 #define CSL_EVETPCC_EER_RN_E6_MAX (0x00000001U)
9878 #define CSL_EVETPCC_EER_RN_E8_MASK (0x00000100U)
9879 #define CSL_EVETPCC_EER_RN_E8_SHIFT (8U)
9880 #define CSL_EVETPCC_EER_RN_E8_RESETVAL (0x00000000U)
9881 #define CSL_EVETPCC_EER_RN_E8_MAX (0x00000001U)
9883 #define CSL_EVETPCC_EER_RN_E7_MASK (0x00000080U)
9884 #define CSL_EVETPCC_EER_RN_E7_SHIFT (7U)
9885 #define CSL_EVETPCC_EER_RN_E7_RESETVAL (0x00000000U)
9886 #define CSL_EVETPCC_EER_RN_E7_MAX (0x00000001U)
9888 #define CSL_EVETPCC_EER_RN_E28_MASK (0x10000000U)
9889 #define CSL_EVETPCC_EER_RN_E28_SHIFT (28U)
9890 #define CSL_EVETPCC_EER_RN_E28_RESETVAL (0x00000000U)
9891 #define CSL_EVETPCC_EER_RN_E28_MAX (0x00000001U)
9893 #define CSL_EVETPCC_EER_RN_E3_MASK (0x00000008U)
9894 #define CSL_EVETPCC_EER_RN_E3_SHIFT (3U)
9895 #define CSL_EVETPCC_EER_RN_E3_RESETVAL (0x00000000U)
9896 #define CSL_EVETPCC_EER_RN_E3_MAX (0x00000001U)
9898 #define CSL_EVETPCC_EER_RN_E2_MASK (0x00000004U)
9899 #define CSL_EVETPCC_EER_RN_E2_SHIFT (2U)
9900 #define CSL_EVETPCC_EER_RN_E2_RESETVAL (0x00000000U)
9901 #define CSL_EVETPCC_EER_RN_E2_MAX (0x00000001U)
9903 #define CSL_EVETPCC_EER_RN_E1_MASK (0x00000002U)
9904 #define CSL_EVETPCC_EER_RN_E1_SHIFT (1U)
9905 #define CSL_EVETPCC_EER_RN_E1_RESETVAL (0x00000000U)
9906 #define CSL_EVETPCC_EER_RN_E1_MAX (0x00000001U)
9908 #define CSL_EVETPCC_EER_RN_E13_MASK (0x00002000U)
9909 #define CSL_EVETPCC_EER_RN_E13_SHIFT (13U)
9910 #define CSL_EVETPCC_EER_RN_E13_RESETVAL (0x00000000U)
9911 #define CSL_EVETPCC_EER_RN_E13_MAX (0x00000001U)
9913 #define CSL_EVETPCC_EER_RN_E17_MASK (0x00020000U)
9914 #define CSL_EVETPCC_EER_RN_E17_SHIFT (17U)
9915 #define CSL_EVETPCC_EER_RN_E17_RESETVAL (0x00000000U)
9916 #define CSL_EVETPCC_EER_RN_E17_MAX (0x00000001U)
9918 #define CSL_EVETPCC_EER_RN_E26_MASK (0x04000000U)
9919 #define CSL_EVETPCC_EER_RN_E26_SHIFT (26U)
9920 #define CSL_EVETPCC_EER_RN_E26_RESETVAL (0x00000000U)
9921 #define CSL_EVETPCC_EER_RN_E26_MAX (0x00000001U)
9923 #define CSL_EVETPCC_EER_RN_E14_MASK (0x00004000U)
9924 #define CSL_EVETPCC_EER_RN_E14_SHIFT (14U)
9925 #define CSL_EVETPCC_EER_RN_E14_RESETVAL (0x00000000U)
9926 #define CSL_EVETPCC_EER_RN_E14_MAX (0x00000001U)
9928 #define CSL_EVETPCC_EER_RN_E16_MASK (0x00010000U)
9929 #define CSL_EVETPCC_EER_RN_E16_SHIFT (16U)
9930 #define CSL_EVETPCC_EER_RN_E16_RESETVAL (0x00000000U)
9931 #define CSL_EVETPCC_EER_RN_E16_MAX (0x00000001U)
9933 #define CSL_EVETPCC_EER_RN_E27_MASK (0x08000000U)
9934 #define CSL_EVETPCC_EER_RN_E27_SHIFT (27U)
9935 #define CSL_EVETPCC_EER_RN_E27_RESETVAL (0x00000000U)
9936 #define CSL_EVETPCC_EER_RN_E27_MAX (0x00000001U)
9938 #define CSL_EVETPCC_EER_RN_E4_MASK (0x00000010U)
9939 #define CSL_EVETPCC_EER_RN_E4_SHIFT (4U)
9940 #define CSL_EVETPCC_EER_RN_E4_RESETVAL (0x00000000U)
9941 #define CSL_EVETPCC_EER_RN_E4_MAX (0x00000001U)
9943 #define CSL_EVETPCC_EER_RN_E15_MASK (0x00008000U)
9944 #define CSL_EVETPCC_EER_RN_E15_SHIFT (15U)
9945 #define CSL_EVETPCC_EER_RN_E15_RESETVAL (0x00000000U)
9946 #define CSL_EVETPCC_EER_RN_E15_MAX (0x00000001U)
9948 #define CSL_EVETPCC_EER_RN_RESETVAL (0x00000000U)
9950 /* CERH_RN */
9952 #define CSL_EVETPCC_CERH_RN_E49_MASK (0x00020000U)
9953 #define CSL_EVETPCC_CERH_RN_E49_SHIFT (17U)
9954 #define CSL_EVETPCC_CERH_RN_E49_RESETVAL (0x00000000U)
9955 #define CSL_EVETPCC_CERH_RN_E49_MAX (0x00000001U)
9957 #define CSL_EVETPCC_CERH_RN_E38_MASK (0x00000040U)
9958 #define CSL_EVETPCC_CERH_RN_E38_SHIFT (6U)
9959 #define CSL_EVETPCC_CERH_RN_E38_RESETVAL (0x00000000U)
9960 #define CSL_EVETPCC_CERH_RN_E38_MAX (0x00000001U)
9962 #define CSL_EVETPCC_CERH_RN_E39_MASK (0x00000080U)
9963 #define CSL_EVETPCC_CERH_RN_E39_SHIFT (7U)
9964 #define CSL_EVETPCC_CERH_RN_E39_RESETVAL (0x00000000U)
9965 #define CSL_EVETPCC_CERH_RN_E39_MAX (0x00000001U)
9967 #define CSL_EVETPCC_CERH_RN_E40_MASK (0x00000100U)
9968 #define CSL_EVETPCC_CERH_RN_E40_SHIFT (8U)
9969 #define CSL_EVETPCC_CERH_RN_E40_RESETVAL (0x00000000U)
9970 #define CSL_EVETPCC_CERH_RN_E40_MAX (0x00000001U)
9972 #define CSL_EVETPCC_CERH_RN_E63_MASK (0x80000000U)
9973 #define CSL_EVETPCC_CERH_RN_E63_SHIFT (31U)
9974 #define CSL_EVETPCC_CERH_RN_E63_RESETVAL (0x00000000U)
9975 #define CSL_EVETPCC_CERH_RN_E63_MAX (0x00000001U)
9977 #define CSL_EVETPCC_CERH_RN_E41_MASK (0x00000200U)
9978 #define CSL_EVETPCC_CERH_RN_E41_SHIFT (9U)
9979 #define CSL_EVETPCC_CERH_RN_E41_RESETVAL (0x00000000U)
9980 #define CSL_EVETPCC_CERH_RN_E41_MAX (0x00000001U)
9982 #define CSL_EVETPCC_CERH_RN_E62_MASK (0x40000000U)
9983 #define CSL_EVETPCC_CERH_RN_E62_SHIFT (30U)
9984 #define CSL_EVETPCC_CERH_RN_E62_RESETVAL (0x00000000U)
9985 #define CSL_EVETPCC_CERH_RN_E62_MAX (0x00000001U)
9987 #define CSL_EVETPCC_CERH_RN_E61_MASK (0x20000000U)
9988 #define CSL_EVETPCC_CERH_RN_E61_SHIFT (29U)
9989 #define CSL_EVETPCC_CERH_RN_E61_RESETVAL (0x00000000U)
9990 #define CSL_EVETPCC_CERH_RN_E61_MAX (0x00000001U)
9992 #define CSL_EVETPCC_CERH_RN_E42_MASK (0x00000400U)
9993 #define CSL_EVETPCC_CERH_RN_E42_SHIFT (10U)
9994 #define CSL_EVETPCC_CERH_RN_E42_RESETVAL (0x00000000U)
9995 #define CSL_EVETPCC_CERH_RN_E42_MAX (0x00000001U)
9997 #define CSL_EVETPCC_CERH_RN_E32_MASK (0x00000001U)
9998 #define CSL_EVETPCC_CERH_RN_E32_SHIFT (0U)
9999 #define CSL_EVETPCC_CERH_RN_E32_RESETVAL (0x00000000U)
10000 #define CSL_EVETPCC_CERH_RN_E32_MAX (0x00000001U)
10002 #define CSL_EVETPCC_CERH_RN_E57_MASK (0x02000000U)
10003 #define CSL_EVETPCC_CERH_RN_E57_SHIFT (25U)
10004 #define CSL_EVETPCC_CERH_RN_E57_RESETVAL (0x00000000U)
10005 #define CSL_EVETPCC_CERH_RN_E57_MAX (0x00000001U)
10007 #define CSL_EVETPCC_CERH_RN_E43_MASK (0x00000800U)
10008 #define CSL_EVETPCC_CERH_RN_E43_SHIFT (11U)
10009 #define CSL_EVETPCC_CERH_RN_E43_RESETVAL (0x00000000U)
10010 #define CSL_EVETPCC_CERH_RN_E43_MAX (0x00000001U)
10012 #define CSL_EVETPCC_CERH_RN_E58_MASK (0x04000000U)
10013 #define CSL_EVETPCC_CERH_RN_E58_SHIFT (26U)
10014 #define CSL_EVETPCC_CERH_RN_E58_RESETVAL (0x00000000U)
10015 #define CSL_EVETPCC_CERH_RN_E58_MAX (0x00000001U)
10017 #define CSL_EVETPCC_CERH_RN_E44_MASK (0x00001000U)
10018 #define CSL_EVETPCC_CERH_RN_E44_SHIFT (12U)
10019 #define CSL_EVETPCC_CERH_RN_E44_RESETVAL (0x00000000U)
10020 #define CSL_EVETPCC_CERH_RN_E44_MAX (0x00000001U)
10022 #define CSL_EVETPCC_CERH_RN_E59_MASK (0x08000000U)
10023 #define CSL_EVETPCC_CERH_RN_E59_SHIFT (27U)
10024 #define CSL_EVETPCC_CERH_RN_E59_RESETVAL (0x00000000U)
10025 #define CSL_EVETPCC_CERH_RN_E59_MAX (0x00000001U)
10027 #define CSL_EVETPCC_CERH_RN_E60_MASK (0x10000000U)
10028 #define CSL_EVETPCC_CERH_RN_E60_SHIFT (28U)
10029 #define CSL_EVETPCC_CERH_RN_E60_RESETVAL (0x00000000U)
10030 #define CSL_EVETPCC_CERH_RN_E60_MAX (0x00000001U)
10032 #define CSL_EVETPCC_CERH_RN_E45_MASK (0x00002000U)
10033 #define CSL_EVETPCC_CERH_RN_E45_SHIFT (13U)
10034 #define CSL_EVETPCC_CERH_RN_E45_RESETVAL (0x00000000U)
10035 #define CSL_EVETPCC_CERH_RN_E45_MAX (0x00000001U)
10037 #define CSL_EVETPCC_CERH_RN_E33_MASK (0x00000002U)
10038 #define CSL_EVETPCC_CERH_RN_E33_SHIFT (1U)
10039 #define CSL_EVETPCC_CERH_RN_E33_RESETVAL (0x00000000U)
10040 #define CSL_EVETPCC_CERH_RN_E33_MAX (0x00000001U)
10042 #define CSL_EVETPCC_CERH_RN_E46_MASK (0x00004000U)
10043 #define CSL_EVETPCC_CERH_RN_E46_SHIFT (14U)
10044 #define CSL_EVETPCC_CERH_RN_E46_RESETVAL (0x00000000U)
10045 #define CSL_EVETPCC_CERH_RN_E46_MAX (0x00000001U)
10047 #define CSL_EVETPCC_CERH_RN_E34_MASK (0x00000004U)
10048 #define CSL_EVETPCC_CERH_RN_E34_SHIFT (2U)
10049 #define CSL_EVETPCC_CERH_RN_E34_RESETVAL (0x00000000U)
10050 #define CSL_EVETPCC_CERH_RN_E34_MAX (0x00000001U)
10052 #define CSL_EVETPCC_CERH_RN_E47_MASK (0x00008000U)
10053 #define CSL_EVETPCC_CERH_RN_E47_SHIFT (15U)
10054 #define CSL_EVETPCC_CERH_RN_E47_RESETVAL (0x00000000U)
10055 #define CSL_EVETPCC_CERH_RN_E47_MAX (0x00000001U)
10057 #define CSL_EVETPCC_CERH_RN_E53_MASK (0x00200000U)
10058 #define CSL_EVETPCC_CERH_RN_E53_SHIFT (21U)
10059 #define CSL_EVETPCC_CERH_RN_E53_RESETVAL (0x00000000U)
10060 #define CSL_EVETPCC_CERH_RN_E53_MAX (0x00000001U)
10062 #define CSL_EVETPCC_CERH_RN_E54_MASK (0x00400000U)
10063 #define CSL_EVETPCC_CERH_RN_E54_SHIFT (22U)
10064 #define CSL_EVETPCC_CERH_RN_E54_RESETVAL (0x00000000U)
10065 #define CSL_EVETPCC_CERH_RN_E54_MAX (0x00000001U)
10067 #define CSL_EVETPCC_CERH_RN_E50_MASK (0x00040000U)
10068 #define CSL_EVETPCC_CERH_RN_E50_SHIFT (18U)
10069 #define CSL_EVETPCC_CERH_RN_E50_RESETVAL (0x00000000U)
10070 #define CSL_EVETPCC_CERH_RN_E50_MAX (0x00000001U)
10072 #define CSL_EVETPCC_CERH_RN_E35_MASK (0x00000008U)
10073 #define CSL_EVETPCC_CERH_RN_E35_SHIFT (3U)
10074 #define CSL_EVETPCC_CERH_RN_E35_RESETVAL (0x00000000U)
10075 #define CSL_EVETPCC_CERH_RN_E35_MAX (0x00000001U)
10077 #define CSL_EVETPCC_CERH_RN_E48_MASK (0x00010000U)
10078 #define CSL_EVETPCC_CERH_RN_E48_SHIFT (16U)
10079 #define CSL_EVETPCC_CERH_RN_E48_RESETVAL (0x00000000U)
10080 #define CSL_EVETPCC_CERH_RN_E48_MAX (0x00000001U)
10082 #define CSL_EVETPCC_CERH_RN_E56_MASK (0x01000000U)
10083 #define CSL_EVETPCC_CERH_RN_E56_SHIFT (24U)
10084 #define CSL_EVETPCC_CERH_RN_E56_RESETVAL (0x00000000U)
10085 #define CSL_EVETPCC_CERH_RN_E56_MAX (0x00000001U)
10087 #define CSL_EVETPCC_CERH_RN_E51_MASK (0x00080000U)
10088 #define CSL_EVETPCC_CERH_RN_E51_SHIFT (19U)
10089 #define CSL_EVETPCC_CERH_RN_E51_RESETVAL (0x00000000U)
10090 #define CSL_EVETPCC_CERH_RN_E51_MAX (0x00000001U)
10092 #define CSL_EVETPCC_CERH_RN_E36_MASK (0x00000010U)
10093 #define CSL_EVETPCC_CERH_RN_E36_SHIFT (4U)
10094 #define CSL_EVETPCC_CERH_RN_E36_RESETVAL (0x00000000U)
10095 #define CSL_EVETPCC_CERH_RN_E36_MAX (0x00000001U)
10097 #define CSL_EVETPCC_CERH_RN_E55_MASK (0x00800000U)
10098 #define CSL_EVETPCC_CERH_RN_E55_SHIFT (23U)
10099 #define CSL_EVETPCC_CERH_RN_E55_RESETVAL (0x00000000U)
10100 #define CSL_EVETPCC_CERH_RN_E55_MAX (0x00000001U)
10102 #define CSL_EVETPCC_CERH_RN_E52_MASK (0x00100000U)
10103 #define CSL_EVETPCC_CERH_RN_E52_SHIFT (20U)
10104 #define CSL_EVETPCC_CERH_RN_E52_RESETVAL (0x00000000U)
10105 #define CSL_EVETPCC_CERH_RN_E52_MAX (0x00000001U)
10107 #define CSL_EVETPCC_CERH_RN_E37_MASK (0x00000020U)
10108 #define CSL_EVETPCC_CERH_RN_E37_SHIFT (5U)
10109 #define CSL_EVETPCC_CERH_RN_E37_RESETVAL (0x00000000U)
10110 #define CSL_EVETPCC_CERH_RN_E37_MAX (0x00000001U)
10112 #define CSL_EVETPCC_CERH_RN_RESETVAL (0x00000000U)
10114 /* QEER_RN */
10116 #define CSL_EVETPCC_QEER_RN_E6_MASK (0x00000040U)
10117 #define CSL_EVETPCC_QEER_RN_E6_SHIFT (6U)
10118 #define CSL_EVETPCC_QEER_RN_E6_RESETVAL (0x00000000U)
10119 #define CSL_EVETPCC_QEER_RN_E6_MAX (0x00000001U)
10121 #define CSL_EVETPCC_QEER_RN_E5_MASK (0x00000020U)
10122 #define CSL_EVETPCC_QEER_RN_E5_SHIFT (5U)
10123 #define CSL_EVETPCC_QEER_RN_E5_RESETVAL (0x00000000U)
10124 #define CSL_EVETPCC_QEER_RN_E5_MAX (0x00000001U)
10126 #define CSL_EVETPCC_QEER_RN_E7_MASK (0x00000080U)
10127 #define CSL_EVETPCC_QEER_RN_E7_SHIFT (7U)
10128 #define CSL_EVETPCC_QEER_RN_E7_RESETVAL (0x00000000U)
10129 #define CSL_EVETPCC_QEER_RN_E7_MAX (0x00000001U)
10131 #define CSL_EVETPCC_QEER_RN_E0_MASK (0x00000001U)
10132 #define CSL_EVETPCC_QEER_RN_E0_SHIFT (0U)
10133 #define CSL_EVETPCC_QEER_RN_E0_RESETVAL (0x00000000U)
10134 #define CSL_EVETPCC_QEER_RN_E0_MAX (0x00000001U)
10136 #define CSL_EVETPCC_QEER_RN_E2_MASK (0x00000004U)
10137 #define CSL_EVETPCC_QEER_RN_E2_SHIFT (2U)
10138 #define CSL_EVETPCC_QEER_RN_E2_RESETVAL (0x00000000U)
10139 #define CSL_EVETPCC_QEER_RN_E2_MAX (0x00000001U)
10141 #define CSL_EVETPCC_QEER_RN_E1_MASK (0x00000002U)
10142 #define CSL_EVETPCC_QEER_RN_E1_SHIFT (1U)
10143 #define CSL_EVETPCC_QEER_RN_E1_RESETVAL (0x00000000U)
10144 #define CSL_EVETPCC_QEER_RN_E1_MAX (0x00000001U)
10146 #define CSL_EVETPCC_QEER_RN_E4_MASK (0x00000010U)
10147 #define CSL_EVETPCC_QEER_RN_E4_SHIFT (4U)
10148 #define CSL_EVETPCC_QEER_RN_E4_RESETVAL (0x00000000U)
10149 #define CSL_EVETPCC_QEER_RN_E4_MAX (0x00000001U)
10151 #define CSL_EVETPCC_QEER_RN_E3_MASK (0x00000008U)
10152 #define CSL_EVETPCC_QEER_RN_E3_SHIFT (3U)
10153 #define CSL_EVETPCC_QEER_RN_E3_RESETVAL (0x00000000U)
10154 #define CSL_EVETPCC_QEER_RN_E3_MAX (0x00000001U)
10156 #define CSL_EVETPCC_QEER_RN_RESETVAL (0x00000000U)
10158 /* QSECR_RN */
10160 #define CSL_EVETPCC_QSECR_RN_E5_MASK (0x00000020U)
10161 #define CSL_EVETPCC_QSECR_RN_E5_SHIFT (5U)
10162 #define CSL_EVETPCC_QSECR_RN_E5_RESETVAL (0x00000000U)
10163 #define CSL_EVETPCC_QSECR_RN_E5_MAX (0x00000001U)
10165 #define CSL_EVETPCC_QSECR_RN_E6_MASK (0x00000040U)
10166 #define CSL_EVETPCC_QSECR_RN_E6_SHIFT (6U)
10167 #define CSL_EVETPCC_QSECR_RN_E6_RESETVAL (0x00000000U)
10168 #define CSL_EVETPCC_QSECR_RN_E6_MAX (0x00000001U)
10170 #define CSL_EVETPCC_QSECR_RN_E7_MASK (0x00000080U)
10171 #define CSL_EVETPCC_QSECR_RN_E7_SHIFT (7U)
10172 #define CSL_EVETPCC_QSECR_RN_E7_RESETVAL (0x00000000U)
10173 #define CSL_EVETPCC_QSECR_RN_E7_MAX (0x00000001U)
10175 #define CSL_EVETPCC_QSECR_RN_E0_MASK (0x00000001U)
10176 #define CSL_EVETPCC_QSECR_RN_E0_SHIFT (0U)
10177 #define CSL_EVETPCC_QSECR_RN_E0_RESETVAL (0x00000000U)
10178 #define CSL_EVETPCC_QSECR_RN_E0_MAX (0x00000001U)
10180 #define CSL_EVETPCC_QSECR_RN_E2_MASK (0x00000004U)
10181 #define CSL_EVETPCC_QSECR_RN_E2_SHIFT (2U)
10182 #define CSL_EVETPCC_QSECR_RN_E2_RESETVAL (0x00000000U)
10183 #define CSL_EVETPCC_QSECR_RN_E2_MAX (0x00000001U)
10185 #define CSL_EVETPCC_QSECR_RN_E1_MASK (0x00000002U)
10186 #define CSL_EVETPCC_QSECR_RN_E1_SHIFT (1U)
10187 #define CSL_EVETPCC_QSECR_RN_E1_RESETVAL (0x00000000U)
10188 #define CSL_EVETPCC_QSECR_RN_E1_MAX (0x00000001U)
10190 #define CSL_EVETPCC_QSECR_RN_E4_MASK (0x00000010U)
10191 #define CSL_EVETPCC_QSECR_RN_E4_SHIFT (4U)
10192 #define CSL_EVETPCC_QSECR_RN_E4_RESETVAL (0x00000000U)
10193 #define CSL_EVETPCC_QSECR_RN_E4_MAX (0x00000001U)
10195 #define CSL_EVETPCC_QSECR_RN_E3_MASK (0x00000008U)
10196 #define CSL_EVETPCC_QSECR_RN_E3_SHIFT (3U)
10197 #define CSL_EVETPCC_QSECR_RN_E3_RESETVAL (0x00000000U)
10198 #define CSL_EVETPCC_QSECR_RN_E3_MAX (0x00000001U)
10200 #define CSL_EVETPCC_QSECR_RN_RESETVAL (0x00000000U)
10202 /* ECRH_RN */
10204 #define CSL_EVETPCC_ECRH_RN_E50_MASK (0x00040000U)
10205 #define CSL_EVETPCC_ECRH_RN_E50_SHIFT (18U)
10206 #define CSL_EVETPCC_ECRH_RN_E50_RESETVAL (0x00000000U)
10207 #define CSL_EVETPCC_ECRH_RN_E50_MAX (0x00000001U)
10209 #define CSL_EVETPCC_ECRH_RN_E36_MASK (0x00000010U)
10210 #define CSL_EVETPCC_ECRH_RN_E36_SHIFT (4U)
10211 #define CSL_EVETPCC_ECRH_RN_E36_RESETVAL (0x00000000U)
10212 #define CSL_EVETPCC_ECRH_RN_E36_MAX (0x00000001U)
10214 #define CSL_EVETPCC_ECRH_RN_E60_MASK (0x10000000U)
10215 #define CSL_EVETPCC_ECRH_RN_E60_SHIFT (28U)
10216 #define CSL_EVETPCC_ECRH_RN_E60_RESETVAL (0x00000000U)
10217 #define CSL_EVETPCC_ECRH_RN_E60_MAX (0x00000001U)
10219 #define CSL_EVETPCC_ECRH_RN_E49_MASK (0x00020000U)
10220 #define CSL_EVETPCC_ECRH_RN_E49_SHIFT (17U)
10221 #define CSL_EVETPCC_ECRH_RN_E49_RESETVAL (0x00000000U)
10222 #define CSL_EVETPCC_ECRH_RN_E49_MAX (0x00000001U)
10224 #define CSL_EVETPCC_ECRH_RN_E37_MASK (0x00000020U)
10225 #define CSL_EVETPCC_ECRH_RN_E37_SHIFT (5U)
10226 #define CSL_EVETPCC_ECRH_RN_E37_RESETVAL (0x00000000U)
10227 #define CSL_EVETPCC_ECRH_RN_E37_MAX (0x00000001U)
10229 #define CSL_EVETPCC_ECRH_RN_E48_MASK (0x00010000U)
10230 #define CSL_EVETPCC_ECRH_RN_E48_SHIFT (16U)
10231 #define CSL_EVETPCC_ECRH_RN_E48_RESETVAL (0x00000000U)
10232 #define CSL_EVETPCC_ECRH_RN_E48_MAX (0x00000001U)
10234 #define CSL_EVETPCC_ECRH_RN_E58_MASK (0x04000000U)
10235 #define CSL_EVETPCC_ECRH_RN_E58_SHIFT (26U)
10236 #define CSL_EVETPCC_ECRH_RN_E58_RESETVAL (0x00000000U)
10237 #define CSL_EVETPCC_ECRH_RN_E58_MAX (0x00000001U)
10239 #define CSL_EVETPCC_ECRH_RN_E38_MASK (0x00000040U)
10240 #define CSL_EVETPCC_ECRH_RN_E38_SHIFT (6U)
10241 #define CSL_EVETPCC_ECRH_RN_E38_RESETVAL (0x00000000U)
10242 #define CSL_EVETPCC_ECRH_RN_E38_MAX (0x00000001U)
10244 #define CSL_EVETPCC_ECRH_RN_E63_MASK (0x80000000U)
10245 #define CSL_EVETPCC_ECRH_RN_E63_SHIFT (31U)
10246 #define CSL_EVETPCC_ECRH_RN_E63_RESETVAL (0x00000000U)
10247 #define CSL_EVETPCC_ECRH_RN_E63_MAX (0x00000001U)
10249 #define CSL_EVETPCC_ECRH_RN_E47_MASK (0x00008000U)
10250 #define CSL_EVETPCC_ECRH_RN_E47_SHIFT (15U)
10251 #define CSL_EVETPCC_ECRH_RN_E47_RESETVAL (0x00000000U)
10252 #define CSL_EVETPCC_ECRH_RN_E47_MAX (0x00000001U)
10254 #define CSL_EVETPCC_ECRH_RN_E39_MASK (0x00000080U)
10255 #define CSL_EVETPCC_ECRH_RN_E39_SHIFT (7U)
10256 #define CSL_EVETPCC_ECRH_RN_E39_RESETVAL (0x00000000U)
10257 #define CSL_EVETPCC_ECRH_RN_E39_MAX (0x00000001U)
10259 #define CSL_EVETPCC_ECRH_RN_E32_MASK (0x00000001U)
10260 #define CSL_EVETPCC_ECRH_RN_E32_SHIFT (0U)
10261 #define CSL_EVETPCC_ECRH_RN_E32_RESETVAL (0x00000000U)
10262 #define CSL_EVETPCC_ECRH_RN_E32_MAX (0x00000001U)
10264 #define CSL_EVETPCC_ECRH_RN_E51_MASK (0x00080000U)
10265 #define CSL_EVETPCC_ECRH_RN_E51_SHIFT (19U)
10266 #define CSL_EVETPCC_ECRH_RN_E51_RESETVAL (0x00000000U)
10267 #define CSL_EVETPCC_ECRH_RN_E51_MAX (0x00000001U)
10269 #define CSL_EVETPCC_ECRH_RN_E33_MASK (0x00000002U)
10270 #define CSL_EVETPCC_ECRH_RN_E33_SHIFT (1U)
10271 #define CSL_EVETPCC_ECRH_RN_E33_RESETVAL (0x00000000U)
10272 #define CSL_EVETPCC_ECRH_RN_E33_MAX (0x00000001U)
10274 #define CSL_EVETPCC_ECRH_RN_E34_MASK (0x00000004U)
10275 #define CSL_EVETPCC_ECRH_RN_E34_SHIFT (2U)
10276 #define CSL_EVETPCC_ECRH_RN_E34_RESETVAL (0x00000000U)
10277 #define CSL_EVETPCC_ECRH_RN_E34_MAX (0x00000001U)
10279 #define CSL_EVETPCC_ECRH_RN_E35_MASK (0x00000008U)
10280 #define CSL_EVETPCC_ECRH_RN_E35_SHIFT (3U)
10281 #define CSL_EVETPCC_ECRH_RN_E35_RESETVAL (0x00000000U)
10282 #define CSL_EVETPCC_ECRH_RN_E35_MAX (0x00000001U)
10284 #define CSL_EVETPCC_ECRH_RN_E42_MASK (0x00000400U)
10285 #define CSL_EVETPCC_ECRH_RN_E42_SHIFT (10U)
10286 #define CSL_EVETPCC_ECRH_RN_E42_RESETVAL (0x00000000U)
10287 #define CSL_EVETPCC_ECRH_RN_E42_MAX (0x00000001U)
10289 #define CSL_EVETPCC_ECRH_RN_E52_MASK (0x00100000U)
10290 #define CSL_EVETPCC_ECRH_RN_E52_SHIFT (20U)
10291 #define CSL_EVETPCC_ECRH_RN_E52_RESETVAL (0x00000000U)
10292 #define CSL_EVETPCC_ECRH_RN_E52_MAX (0x00000001U)
10294 #define CSL_EVETPCC_ECRH_RN_E41_MASK (0x00000200U)
10295 #define CSL_EVETPCC_ECRH_RN_E41_SHIFT (9U)
10296 #define CSL_EVETPCC_ECRH_RN_E41_RESETVAL (0x00000000U)
10297 #define CSL_EVETPCC_ECRH_RN_E41_MAX (0x00000001U)
10299 #define CSL_EVETPCC_ECRH_RN_E55_MASK (0x00800000U)
10300 #define CSL_EVETPCC_ECRH_RN_E55_SHIFT (23U)
10301 #define CSL_EVETPCC_ECRH_RN_E55_RESETVAL (0x00000000U)
10302 #define CSL_EVETPCC_ECRH_RN_E55_MAX (0x00000001U)
10304 #define CSL_EVETPCC_ECRH_RN_E53_MASK (0x00200000U)
10305 #define CSL_EVETPCC_ECRH_RN_E53_SHIFT (21U)
10306 #define CSL_EVETPCC_ECRH_RN_E53_RESETVAL (0x00000000U)
10307 #define CSL_EVETPCC_ECRH_RN_E53_MAX (0x00000001U)
10309 #define CSL_EVETPCC_ECRH_RN_E46_MASK (0x00004000U)
10310 #define CSL_EVETPCC_ECRH_RN_E46_SHIFT (14U)
10311 #define CSL_EVETPCC_ECRH_RN_E46_RESETVAL (0x00000000U)
10312 #define CSL_EVETPCC_ECRH_RN_E46_MAX (0x00000001U)
10314 #define CSL_EVETPCC_ECRH_RN_E62_MASK (0x40000000U)
10315 #define CSL_EVETPCC_ECRH_RN_E62_SHIFT (30U)
10316 #define CSL_EVETPCC_ECRH_RN_E62_RESETVAL (0x00000000U)
10317 #define CSL_EVETPCC_ECRH_RN_E62_MAX (0x00000001U)
10319 #define CSL_EVETPCC_ECRH_RN_E40_MASK (0x00000100U)
10320 #define CSL_EVETPCC_ECRH_RN_E40_SHIFT (8U)
10321 #define CSL_EVETPCC_ECRH_RN_E40_RESETVAL (0x00000000U)
10322 #define CSL_EVETPCC_ECRH_RN_E40_MAX (0x00000001U)
10324 #define CSL_EVETPCC_ECRH_RN_E56_MASK (0x01000000U)
10325 #define CSL_EVETPCC_ECRH_RN_E56_SHIFT (24U)
10326 #define CSL_EVETPCC_ECRH_RN_E56_RESETVAL (0x00000000U)
10327 #define CSL_EVETPCC_ECRH_RN_E56_MAX (0x00000001U)
10329 #define CSL_EVETPCC_ECRH_RN_E61_MASK (0x20000000U)
10330 #define CSL_EVETPCC_ECRH_RN_E61_SHIFT (29U)
10331 #define CSL_EVETPCC_ECRH_RN_E61_RESETVAL (0x00000000U)
10332 #define CSL_EVETPCC_ECRH_RN_E61_MAX (0x00000001U)
10334 #define CSL_EVETPCC_ECRH_RN_E45_MASK (0x00002000U)
10335 #define CSL_EVETPCC_ECRH_RN_E45_SHIFT (13U)
10336 #define CSL_EVETPCC_ECRH_RN_E45_RESETVAL (0x00000000U)
10337 #define CSL_EVETPCC_ECRH_RN_E45_MAX (0x00000001U)
10339 #define CSL_EVETPCC_ECRH_RN_E59_MASK (0x08000000U)
10340 #define CSL_EVETPCC_ECRH_RN_E59_SHIFT (27U)
10341 #define CSL_EVETPCC_ECRH_RN_E59_RESETVAL (0x00000000U)
10342 #define CSL_EVETPCC_ECRH_RN_E59_MAX (0x00000001U)
10344 #define CSL_EVETPCC_ECRH_RN_E44_MASK (0x00001000U)
10345 #define CSL_EVETPCC_ECRH_RN_E44_SHIFT (12U)
10346 #define CSL_EVETPCC_ECRH_RN_E44_RESETVAL (0x00000000U)
10347 #define CSL_EVETPCC_ECRH_RN_E44_MAX (0x00000001U)
10349 #define CSL_EVETPCC_ECRH_RN_E54_MASK (0x00400000U)
10350 #define CSL_EVETPCC_ECRH_RN_E54_SHIFT (22U)
10351 #define CSL_EVETPCC_ECRH_RN_E54_RESETVAL (0x00000000U)
10352 #define CSL_EVETPCC_ECRH_RN_E54_MAX (0x00000001U)
10354 #define CSL_EVETPCC_ECRH_RN_E43_MASK (0x00000800U)
10355 #define CSL_EVETPCC_ECRH_RN_E43_SHIFT (11U)
10356 #define CSL_EVETPCC_ECRH_RN_E43_RESETVAL (0x00000000U)
10357 #define CSL_EVETPCC_ECRH_RN_E43_MAX (0x00000001U)
10359 #define CSL_EVETPCC_ECRH_RN_E57_MASK (0x02000000U)
10360 #define CSL_EVETPCC_ECRH_RN_E57_SHIFT (25U)
10361 #define CSL_EVETPCC_ECRH_RN_E57_RESETVAL (0x00000000U)
10362 #define CSL_EVETPCC_ECRH_RN_E57_MAX (0x00000001U)
10364 #define CSL_EVETPCC_ECRH_RN_RESETVAL (0x00000000U)
10366 /* ICR_RN */
10368 #define CSL_EVETPCC_ICR_RN_I17_MASK (0x00020000U)
10369 #define CSL_EVETPCC_ICR_RN_I17_SHIFT (17U)
10370 #define CSL_EVETPCC_ICR_RN_I17_RESETVAL (0x00000000U)
10371 #define CSL_EVETPCC_ICR_RN_I17_MAX (0x00000001U)
10373 #define CSL_EVETPCC_ICR_RN_I30_MASK (0x40000000U)
10374 #define CSL_EVETPCC_ICR_RN_I30_SHIFT (30U)
10375 #define CSL_EVETPCC_ICR_RN_I30_RESETVAL (0x00000000U)
10376 #define CSL_EVETPCC_ICR_RN_I30_MAX (0x00000001U)
10378 #define CSL_EVETPCC_ICR_RN_I7_MASK (0x00000080U)
10379 #define CSL_EVETPCC_ICR_RN_I7_SHIFT (7U)
10380 #define CSL_EVETPCC_ICR_RN_I7_RESETVAL (0x00000000U)
10381 #define CSL_EVETPCC_ICR_RN_I7_MAX (0x00000001U)
10383 #define CSL_EVETPCC_ICR_RN_I19_MASK (0x00080000U)
10384 #define CSL_EVETPCC_ICR_RN_I19_SHIFT (19U)
10385 #define CSL_EVETPCC_ICR_RN_I19_RESETVAL (0x00000000U)
10386 #define CSL_EVETPCC_ICR_RN_I19_MAX (0x00000001U)
10388 #define CSL_EVETPCC_ICR_RN_I16_MASK (0x00010000U)
10389 #define CSL_EVETPCC_ICR_RN_I16_SHIFT (16U)
10390 #define CSL_EVETPCC_ICR_RN_I16_RESETVAL (0x00000000U)
10391 #define CSL_EVETPCC_ICR_RN_I16_MAX (0x00000001U)
10393 #define CSL_EVETPCC_ICR_RN_I6_MASK (0x00000040U)
10394 #define CSL_EVETPCC_ICR_RN_I6_SHIFT (6U)
10395 #define CSL_EVETPCC_ICR_RN_I6_RESETVAL (0x00000000U)
10396 #define CSL_EVETPCC_ICR_RN_I6_MAX (0x00000001U)
10398 #define CSL_EVETPCC_ICR_RN_I31_MASK (0x80000000U)
10399 #define CSL_EVETPCC_ICR_RN_I31_SHIFT (31U)
10400 #define CSL_EVETPCC_ICR_RN_I31_RESETVAL (0x00000000U)
10401 #define CSL_EVETPCC_ICR_RN_I31_MAX (0x00000001U)
10403 #define CSL_EVETPCC_ICR_RN_I20_MASK (0x00100000U)
10404 #define CSL_EVETPCC_ICR_RN_I20_SHIFT (20U)
10405 #define CSL_EVETPCC_ICR_RN_I20_RESETVAL (0x00000000U)
10406 #define CSL_EVETPCC_ICR_RN_I20_MAX (0x00000001U)
10408 #define CSL_EVETPCC_ICR_RN_I18_MASK (0x00040000U)
10409 #define CSL_EVETPCC_ICR_RN_I18_SHIFT (18U)
10410 #define CSL_EVETPCC_ICR_RN_I18_RESETVAL (0x00000000U)
10411 #define CSL_EVETPCC_ICR_RN_I18_MAX (0x00000001U)
10413 #define CSL_EVETPCC_ICR_RN_I21_MASK (0x00200000U)
10414 #define CSL_EVETPCC_ICR_RN_I21_SHIFT (21U)
10415 #define CSL_EVETPCC_ICR_RN_I21_RESETVAL (0x00000000U)
10416 #define CSL_EVETPCC_ICR_RN_I21_MAX (0x00000001U)
10418 #define CSL_EVETPCC_ICR_RN_I8_MASK (0x00000100U)
10419 #define CSL_EVETPCC_ICR_RN_I8_SHIFT (8U)
10420 #define CSL_EVETPCC_ICR_RN_I8_RESETVAL (0x00000000U)
10421 #define CSL_EVETPCC_ICR_RN_I8_MAX (0x00000001U)
10423 #define CSL_EVETPCC_ICR_RN_I22_MASK (0x00400000U)
10424 #define CSL_EVETPCC_ICR_RN_I22_SHIFT (22U)
10425 #define CSL_EVETPCC_ICR_RN_I22_RESETVAL (0x00000000U)
10426 #define CSL_EVETPCC_ICR_RN_I22_MAX (0x00000001U)
10428 #define CSL_EVETPCC_ICR_RN_I13_MASK (0x00002000U)
10429 #define CSL_EVETPCC_ICR_RN_I13_SHIFT (13U)
10430 #define CSL_EVETPCC_ICR_RN_I13_RESETVAL (0x00000000U)
10431 #define CSL_EVETPCC_ICR_RN_I13_MAX (0x00000001U)
10433 #define CSL_EVETPCC_ICR_RN_I3_MASK (0x00000008U)
10434 #define CSL_EVETPCC_ICR_RN_I3_SHIFT (3U)
10435 #define CSL_EVETPCC_ICR_RN_I3_RESETVAL (0x00000000U)
10436 #define CSL_EVETPCC_ICR_RN_I3_MAX (0x00000001U)
10438 #define CSL_EVETPCC_ICR_RN_I23_MASK (0x00800000U)
10439 #define CSL_EVETPCC_ICR_RN_I23_SHIFT (23U)
10440 #define CSL_EVETPCC_ICR_RN_I23_RESETVAL (0x00000000U)
10441 #define CSL_EVETPCC_ICR_RN_I23_MAX (0x00000001U)
10443 #define CSL_EVETPCC_ICR_RN_I12_MASK (0x00001000U)
10444 #define CSL_EVETPCC_ICR_RN_I12_SHIFT (12U)
10445 #define CSL_EVETPCC_ICR_RN_I12_RESETVAL (0x00000000U)
10446 #define CSL_EVETPCC_ICR_RN_I12_MAX (0x00000001U)
10448 #define CSL_EVETPCC_ICR_RN_I2_MASK (0x00000004U)
10449 #define CSL_EVETPCC_ICR_RN_I2_SHIFT (2U)
10450 #define CSL_EVETPCC_ICR_RN_I2_RESETVAL (0x00000000U)
10451 #define CSL_EVETPCC_ICR_RN_I2_MAX (0x00000001U)
10453 #define CSL_EVETPCC_ICR_RN_I24_MASK (0x01000000U)
10454 #define CSL_EVETPCC_ICR_RN_I24_SHIFT (24U)
10455 #define CSL_EVETPCC_ICR_RN_I24_RESETVAL (0x00000000U)
10456 #define CSL_EVETPCC_ICR_RN_I24_MAX (0x00000001U)
10458 #define CSL_EVETPCC_ICR_RN_I15_MASK (0x00008000U)
10459 #define CSL_EVETPCC_ICR_RN_I15_SHIFT (15U)
10460 #define CSL_EVETPCC_ICR_RN_I15_RESETVAL (0x00000000U)
10461 #define CSL_EVETPCC_ICR_RN_I15_MAX (0x00000001U)
10463 #define CSL_EVETPCC_ICR_RN_I25_MASK (0x02000000U)
10464 #define CSL_EVETPCC_ICR_RN_I25_SHIFT (25U)
10465 #define CSL_EVETPCC_ICR_RN_I25_RESETVAL (0x00000000U)
10466 #define CSL_EVETPCC_ICR_RN_I25_MAX (0x00000001U)
10468 #define CSL_EVETPCC_ICR_RN_I5_MASK (0x00000020U)
10469 #define CSL_EVETPCC_ICR_RN_I5_SHIFT (5U)
10470 #define CSL_EVETPCC_ICR_RN_I5_RESETVAL (0x00000000U)
10471 #define CSL_EVETPCC_ICR_RN_I5_MAX (0x00000001U)
10473 #define CSL_EVETPCC_ICR_RN_I14_MASK (0x00004000U)
10474 #define CSL_EVETPCC_ICR_RN_I14_SHIFT (14U)
10475 #define CSL_EVETPCC_ICR_RN_I14_RESETVAL (0x00000000U)
10476 #define CSL_EVETPCC_ICR_RN_I14_MAX (0x00000001U)
10478 #define CSL_EVETPCC_ICR_RN_I4_MASK (0x00000010U)
10479 #define CSL_EVETPCC_ICR_RN_I4_SHIFT (4U)
10480 #define CSL_EVETPCC_ICR_RN_I4_RESETVAL (0x00000000U)
10481 #define CSL_EVETPCC_ICR_RN_I4_MAX (0x00000001U)
10483 #define CSL_EVETPCC_ICR_RN_I9_MASK (0x00000200U)
10484 #define CSL_EVETPCC_ICR_RN_I9_SHIFT (9U)
10485 #define CSL_EVETPCC_ICR_RN_I9_RESETVAL (0x00000000U)
10486 #define CSL_EVETPCC_ICR_RN_I9_MAX (0x00000001U)
10488 #define CSL_EVETPCC_ICR_RN_I27_MASK (0x08000000U)
10489 #define CSL_EVETPCC_ICR_RN_I27_SHIFT (27U)
10490 #define CSL_EVETPCC_ICR_RN_I27_RESETVAL (0x00000000U)
10491 #define CSL_EVETPCC_ICR_RN_I27_MAX (0x00000001U)
10493 #define CSL_EVETPCC_ICR_RN_I26_MASK (0x04000000U)
10494 #define CSL_EVETPCC_ICR_RN_I26_SHIFT (26U)
10495 #define CSL_EVETPCC_ICR_RN_I26_RESETVAL (0x00000000U)
10496 #define CSL_EVETPCC_ICR_RN_I26_MAX (0x00000001U)
10498 #define CSL_EVETPCC_ICR_RN_I11_MASK (0x00000800U)
10499 #define CSL_EVETPCC_ICR_RN_I11_SHIFT (11U)
10500 #define CSL_EVETPCC_ICR_RN_I11_RESETVAL (0x00000000U)
10501 #define CSL_EVETPCC_ICR_RN_I11_MAX (0x00000001U)
10503 #define CSL_EVETPCC_ICR_RN_I1_MASK (0x00000002U)
10504 #define CSL_EVETPCC_ICR_RN_I1_SHIFT (1U)
10505 #define CSL_EVETPCC_ICR_RN_I1_RESETVAL (0x00000000U)
10506 #define CSL_EVETPCC_ICR_RN_I1_MAX (0x00000001U)
10508 #define CSL_EVETPCC_ICR_RN_I10_MASK (0x00000400U)
10509 #define CSL_EVETPCC_ICR_RN_I10_SHIFT (10U)
10510 #define CSL_EVETPCC_ICR_RN_I10_RESETVAL (0x00000000U)
10511 #define CSL_EVETPCC_ICR_RN_I10_MAX (0x00000001U)
10513 #define CSL_EVETPCC_ICR_RN_I28_MASK (0x10000000U)
10514 #define CSL_EVETPCC_ICR_RN_I28_SHIFT (28U)
10515 #define CSL_EVETPCC_ICR_RN_I28_RESETVAL (0x00000000U)
10516 #define CSL_EVETPCC_ICR_RN_I28_MAX (0x00000001U)
10518 #define CSL_EVETPCC_ICR_RN_I0_MASK (0x00000001U)
10519 #define CSL_EVETPCC_ICR_RN_I0_SHIFT (0U)
10520 #define CSL_EVETPCC_ICR_RN_I0_RESETVAL (0x00000000U)
10521 #define CSL_EVETPCC_ICR_RN_I0_MAX (0x00000001U)
10523 #define CSL_EVETPCC_ICR_RN_I29_MASK (0x20000000U)
10524 #define CSL_EVETPCC_ICR_RN_I29_SHIFT (29U)
10525 #define CSL_EVETPCC_ICR_RN_I29_RESETVAL (0x00000000U)
10526 #define CSL_EVETPCC_ICR_RN_I29_MAX (0x00000001U)
10528 #define CSL_EVETPCC_ICR_RN_RESETVAL (0x00000000U)
10530 /* IPRH_RN */
10532 #define CSL_EVETPCC_IPRH_RN_I53_MASK (0x00200000U)
10533 #define CSL_EVETPCC_IPRH_RN_I53_SHIFT (21U)
10534 #define CSL_EVETPCC_IPRH_RN_I53_RESETVAL (0x00000000U)
10535 #define CSL_EVETPCC_IPRH_RN_I53_MAX (0x00000001U)
10537 #define CSL_EVETPCC_IPRH_RN_I41_MASK (0x00000200U)
10538 #define CSL_EVETPCC_IPRH_RN_I41_SHIFT (9U)
10539 #define CSL_EVETPCC_IPRH_RN_I41_RESETVAL (0x00000000U)
10540 #define CSL_EVETPCC_IPRH_RN_I41_MAX (0x00000001U)
10542 #define CSL_EVETPCC_IPRH_RN_I52_MASK (0x00100000U)
10543 #define CSL_EVETPCC_IPRH_RN_I52_SHIFT (20U)
10544 #define CSL_EVETPCC_IPRH_RN_I52_RESETVAL (0x00000000U)
10545 #define CSL_EVETPCC_IPRH_RN_I52_MAX (0x00000001U)
10547 #define CSL_EVETPCC_IPRH_RN_I40_MASK (0x00000100U)
10548 #define CSL_EVETPCC_IPRH_RN_I40_SHIFT (8U)
10549 #define CSL_EVETPCC_IPRH_RN_I40_RESETVAL (0x00000000U)
10550 #define CSL_EVETPCC_IPRH_RN_I40_MAX (0x00000001U)
10552 #define CSL_EVETPCC_IPRH_RN_I51_MASK (0x00080000U)
10553 #define CSL_EVETPCC_IPRH_RN_I51_SHIFT (19U)
10554 #define CSL_EVETPCC_IPRH_RN_I51_RESETVAL (0x00000000U)
10555 #define CSL_EVETPCC_IPRH_RN_I51_MAX (0x00000001U)
10557 #define CSL_EVETPCC_IPRH_RN_I39_MASK (0x00000080U)
10558 #define CSL_EVETPCC_IPRH_RN_I39_SHIFT (7U)
10559 #define CSL_EVETPCC_IPRH_RN_I39_RESETVAL (0x00000000U)
10560 #define CSL_EVETPCC_IPRH_RN_I39_MAX (0x00000001U)
10562 #define CSL_EVETPCC_IPRH_RN_I32_MASK (0x00000001U)
10563 #define CSL_EVETPCC_IPRH_RN_I32_SHIFT (0U)
10564 #define CSL_EVETPCC_IPRH_RN_I32_RESETVAL (0x00000000U)
10565 #define CSL_EVETPCC_IPRH_RN_I32_MAX (0x00000001U)
10567 #define CSL_EVETPCC_IPRH_RN_I50_MASK (0x00040000U)
10568 #define CSL_EVETPCC_IPRH_RN_I50_SHIFT (18U)
10569 #define CSL_EVETPCC_IPRH_RN_I50_RESETVAL (0x00000000U)
10570 #define CSL_EVETPCC_IPRH_RN_I50_MAX (0x00000001U)
10572 #define CSL_EVETPCC_IPRH_RN_I33_MASK (0x00000002U)
10573 #define CSL_EVETPCC_IPRH_RN_I33_SHIFT (1U)
10574 #define CSL_EVETPCC_IPRH_RN_I33_RESETVAL (0x00000000U)
10575 #define CSL_EVETPCC_IPRH_RN_I33_MAX (0x00000001U)
10577 #define CSL_EVETPCC_IPRH_RN_I34_MASK (0x00000004U)
10578 #define CSL_EVETPCC_IPRH_RN_I34_SHIFT (2U)
10579 #define CSL_EVETPCC_IPRH_RN_I34_RESETVAL (0x00000000U)
10580 #define CSL_EVETPCC_IPRH_RN_I34_MAX (0x00000001U)
10582 #define CSL_EVETPCC_IPRH_RN_I49_MASK (0x00020000U)
10583 #define CSL_EVETPCC_IPRH_RN_I49_SHIFT (17U)
10584 #define CSL_EVETPCC_IPRH_RN_I49_RESETVAL (0x00000000U)
10585 #define CSL_EVETPCC_IPRH_RN_I49_MAX (0x00000001U)
10587 #define CSL_EVETPCC_IPRH_RN_I60_MASK (0x10000000U)
10588 #define CSL_EVETPCC_IPRH_RN_I60_SHIFT (28U)
10589 #define CSL_EVETPCC_IPRH_RN_I60_RESETVAL (0x00000000U)
10590 #define CSL_EVETPCC_IPRH_RN_I60_MAX (0x00000001U)
10592 #define CSL_EVETPCC_IPRH_RN_I47_MASK (0x00008000U)
10593 #define CSL_EVETPCC_IPRH_RN_I47_SHIFT (15U)
10594 #define CSL_EVETPCC_IPRH_RN_I47_RESETVAL (0x00000000U)
10595 #define CSL_EVETPCC_IPRH_RN_I47_MAX (0x00000001U)
10597 #define CSL_EVETPCC_IPRH_RN_I35_MASK (0x00000008U)
10598 #define CSL_EVETPCC_IPRH_RN_I35_SHIFT (3U)
10599 #define CSL_EVETPCC_IPRH_RN_I35_RESETVAL (0x00000000U)
10600 #define CSL_EVETPCC_IPRH_RN_I35_MAX (0x00000001U)
10602 #define CSL_EVETPCC_IPRH_RN_I36_MASK (0x00000010U)
10603 #define CSL_EVETPCC_IPRH_RN_I36_SHIFT (4U)
10604 #define CSL_EVETPCC_IPRH_RN_I36_RESETVAL (0x00000000U)
10605 #define CSL_EVETPCC_IPRH_RN_I36_MAX (0x00000001U)
10607 #define CSL_EVETPCC_IPRH_RN_I59_MASK (0x08000000U)
10608 #define CSL_EVETPCC_IPRH_RN_I59_SHIFT (27U)
10609 #define CSL_EVETPCC_IPRH_RN_I59_RESETVAL (0x00000000U)
10610 #define CSL_EVETPCC_IPRH_RN_I59_MAX (0x00000001U)
10612 #define CSL_EVETPCC_IPRH_RN_I48_MASK (0x00010000U)
10613 #define CSL_EVETPCC_IPRH_RN_I48_SHIFT (16U)
10614 #define CSL_EVETPCC_IPRH_RN_I48_RESETVAL (0x00000000U)
10615 #define CSL_EVETPCC_IPRH_RN_I48_MAX (0x00000001U)
10617 #define CSL_EVETPCC_IPRH_RN_I37_MASK (0x00000020U)
10618 #define CSL_EVETPCC_IPRH_RN_I37_SHIFT (5U)
10619 #define CSL_EVETPCC_IPRH_RN_I37_RESETVAL (0x00000000U)
10620 #define CSL_EVETPCC_IPRH_RN_I37_MAX (0x00000001U)
10622 #define CSL_EVETPCC_IPRH_RN_I61_MASK (0x20000000U)
10623 #define CSL_EVETPCC_IPRH_RN_I61_SHIFT (29U)
10624 #define CSL_EVETPCC_IPRH_RN_I61_RESETVAL (0x00000000U)
10625 #define CSL_EVETPCC_IPRH_RN_I61_MAX (0x00000001U)
10627 #define CSL_EVETPCC_IPRH_RN_I38_MASK (0x00000040U)
10628 #define CSL_EVETPCC_IPRH_RN_I38_SHIFT (6U)
10629 #define CSL_EVETPCC_IPRH_RN_I38_RESETVAL (0x00000000U)
10630 #define CSL_EVETPCC_IPRH_RN_I38_MAX (0x00000001U)
10632 #define CSL_EVETPCC_IPRH_RN_I58_MASK (0x04000000U)
10633 #define CSL_EVETPCC_IPRH_RN_I58_SHIFT (26U)
10634 #define CSL_EVETPCC_IPRH_RN_I58_RESETVAL (0x00000000U)
10635 #define CSL_EVETPCC_IPRH_RN_I58_MAX (0x00000001U)
10637 #define CSL_EVETPCC_IPRH_RN_I46_MASK (0x00004000U)
10638 #define CSL_EVETPCC_IPRH_RN_I46_SHIFT (14U)
10639 #define CSL_EVETPCC_IPRH_RN_I46_RESETVAL (0x00000000U)
10640 #define CSL_EVETPCC_IPRH_RN_I46_MAX (0x00000001U)
10642 #define CSL_EVETPCC_IPRH_RN_I45_MASK (0x00002000U)
10643 #define CSL_EVETPCC_IPRH_RN_I45_SHIFT (13U)
10644 #define CSL_EVETPCC_IPRH_RN_I45_RESETVAL (0x00000000U)
10645 #define CSL_EVETPCC_IPRH_RN_I45_MAX (0x00000001U)
10647 #define CSL_EVETPCC_IPRH_RN_I57_MASK (0x02000000U)
10648 #define CSL_EVETPCC_IPRH_RN_I57_SHIFT (25U)
10649 #define CSL_EVETPCC_IPRH_RN_I57_RESETVAL (0x00000000U)
10650 #define CSL_EVETPCC_IPRH_RN_I57_MAX (0x00000001U)
10652 #define CSL_EVETPCC_IPRH_RN_I44_MASK (0x00001000U)
10653 #define CSL_EVETPCC_IPRH_RN_I44_SHIFT (12U)
10654 #define CSL_EVETPCC_IPRH_RN_I44_RESETVAL (0x00000000U)
10655 #define CSL_EVETPCC_IPRH_RN_I44_MAX (0x00000001U)
10657 #define CSL_EVETPCC_IPRH_RN_I56_MASK (0x01000000U)
10658 #define CSL_EVETPCC_IPRH_RN_I56_SHIFT (24U)
10659 #define CSL_EVETPCC_IPRH_RN_I56_RESETVAL (0x00000000U)
10660 #define CSL_EVETPCC_IPRH_RN_I56_MAX (0x00000001U)
10662 #define CSL_EVETPCC_IPRH_RN_I63_MASK (0x80000000U)
10663 #define CSL_EVETPCC_IPRH_RN_I63_SHIFT (31U)
10664 #define CSL_EVETPCC_IPRH_RN_I63_RESETVAL (0x00000000U)
10665 #define CSL_EVETPCC_IPRH_RN_I63_MAX (0x00000001U)
10667 #define CSL_EVETPCC_IPRH_RN_I43_MASK (0x00000800U)
10668 #define CSL_EVETPCC_IPRH_RN_I43_SHIFT (11U)
10669 #define CSL_EVETPCC_IPRH_RN_I43_RESETVAL (0x00000000U)
10670 #define CSL_EVETPCC_IPRH_RN_I43_MAX (0x00000001U)
10672 #define CSL_EVETPCC_IPRH_RN_I55_MASK (0x00800000U)
10673 #define CSL_EVETPCC_IPRH_RN_I55_SHIFT (23U)
10674 #define CSL_EVETPCC_IPRH_RN_I55_RESETVAL (0x00000000U)
10675 #define CSL_EVETPCC_IPRH_RN_I55_MAX (0x00000001U)
10677 #define CSL_EVETPCC_IPRH_RN_I62_MASK (0x40000000U)
10678 #define CSL_EVETPCC_IPRH_RN_I62_SHIFT (30U)
10679 #define CSL_EVETPCC_IPRH_RN_I62_RESETVAL (0x00000000U)
10680 #define CSL_EVETPCC_IPRH_RN_I62_MAX (0x00000001U)
10682 #define CSL_EVETPCC_IPRH_RN_I42_MASK (0x00000400U)
10683 #define CSL_EVETPCC_IPRH_RN_I42_SHIFT (10U)
10684 #define CSL_EVETPCC_IPRH_RN_I42_RESETVAL (0x00000000U)
10685 #define CSL_EVETPCC_IPRH_RN_I42_MAX (0x00000001U)
10687 #define CSL_EVETPCC_IPRH_RN_I54_MASK (0x00400000U)
10688 #define CSL_EVETPCC_IPRH_RN_I54_SHIFT (22U)
10689 #define CSL_EVETPCC_IPRH_RN_I54_RESETVAL (0x00000000U)
10690 #define CSL_EVETPCC_IPRH_RN_I54_MAX (0x00000001U)
10692 #define CSL_EVETPCC_IPRH_RN_RESETVAL (0x00000000U)
10694 /* CER_RN */
10696 #define CSL_EVETPCC_CER_RN_E6_MASK (0x00000040U)
10697 #define CSL_EVETPCC_CER_RN_E6_SHIFT (6U)
10698 #define CSL_EVETPCC_CER_RN_E6_RESETVAL (0x00000000U)
10699 #define CSL_EVETPCC_CER_RN_E6_MAX (0x00000001U)
10701 #define CSL_EVETPCC_CER_RN_E25_MASK (0x02000000U)
10702 #define CSL_EVETPCC_CER_RN_E25_SHIFT (25U)
10703 #define CSL_EVETPCC_CER_RN_E25_RESETVAL (0x00000000U)
10704 #define CSL_EVETPCC_CER_RN_E25_MAX (0x00000001U)
10706 #define CSL_EVETPCC_CER_RN_E18_MASK (0x00040000U)
10707 #define CSL_EVETPCC_CER_RN_E18_SHIFT (18U)
10708 #define CSL_EVETPCC_CER_RN_E18_RESETVAL (0x00000000U)
10709 #define CSL_EVETPCC_CER_RN_E18_MAX (0x00000001U)
10711 #define CSL_EVETPCC_CER_RN_E7_MASK (0x00000080U)
10712 #define CSL_EVETPCC_CER_RN_E7_SHIFT (7U)
10713 #define CSL_EVETPCC_CER_RN_E7_RESETVAL (0x00000000U)
10714 #define CSL_EVETPCC_CER_RN_E7_MAX (0x00000001U)
10716 #define CSL_EVETPCC_CER_RN_E24_MASK (0x01000000U)
10717 #define CSL_EVETPCC_CER_RN_E24_SHIFT (24U)
10718 #define CSL_EVETPCC_CER_RN_E24_RESETVAL (0x00000000U)
10719 #define CSL_EVETPCC_CER_RN_E24_MAX (0x00000001U)
10721 #define CSL_EVETPCC_CER_RN_E31_MASK (0x80000000U)
10722 #define CSL_EVETPCC_CER_RN_E31_SHIFT (31U)
10723 #define CSL_EVETPCC_CER_RN_E31_RESETVAL (0x00000000U)
10724 #define CSL_EVETPCC_CER_RN_E31_MAX (0x00000001U)
10726 #define CSL_EVETPCC_CER_RN_E8_MASK (0x00000100U)
10727 #define CSL_EVETPCC_CER_RN_E8_SHIFT (8U)
10728 #define CSL_EVETPCC_CER_RN_E8_RESETVAL (0x00000000U)
10729 #define CSL_EVETPCC_CER_RN_E8_MAX (0x00000001U)
10731 #define CSL_EVETPCC_CER_RN_E26_MASK (0x04000000U)
10732 #define CSL_EVETPCC_CER_RN_E26_SHIFT (26U)
10733 #define CSL_EVETPCC_CER_RN_E26_RESETVAL (0x00000000U)
10734 #define CSL_EVETPCC_CER_RN_E26_MAX (0x00000001U)
10736 #define CSL_EVETPCC_CER_RN_E29_MASK (0x20000000U)
10737 #define CSL_EVETPCC_CER_RN_E29_SHIFT (29U)
10738 #define CSL_EVETPCC_CER_RN_E29_RESETVAL (0x00000000U)
10739 #define CSL_EVETPCC_CER_RN_E29_MAX (0x00000001U)
10741 #define CSL_EVETPCC_CER_RN_E9_MASK (0x00000200U)
10742 #define CSL_EVETPCC_CER_RN_E9_SHIFT (9U)
10743 #define CSL_EVETPCC_CER_RN_E9_RESETVAL (0x00000000U)
10744 #define CSL_EVETPCC_CER_RN_E9_MAX (0x00000001U)
10746 #define CSL_EVETPCC_CER_RN_E30_MASK (0x40000000U)
10747 #define CSL_EVETPCC_CER_RN_E30_SHIFT (30U)
10748 #define CSL_EVETPCC_CER_RN_E30_RESETVAL (0x00000000U)
10749 #define CSL_EVETPCC_CER_RN_E30_MAX (0x00000001U)
10751 #define CSL_EVETPCC_CER_RN_E10_MASK (0x00000400U)
10752 #define CSL_EVETPCC_CER_RN_E10_SHIFT (10U)
10753 #define CSL_EVETPCC_CER_RN_E10_RESETVAL (0x00000000U)
10754 #define CSL_EVETPCC_CER_RN_E10_MAX (0x00000001U)
10756 #define CSL_EVETPCC_CER_RN_E28_MASK (0x10000000U)
10757 #define CSL_EVETPCC_CER_RN_E28_SHIFT (28U)
10758 #define CSL_EVETPCC_CER_RN_E28_RESETVAL (0x00000000U)
10759 #define CSL_EVETPCC_CER_RN_E28_MAX (0x00000001U)
10761 #define CSL_EVETPCC_CER_RN_E11_MASK (0x00000800U)
10762 #define CSL_EVETPCC_CER_RN_E11_SHIFT (11U)
10763 #define CSL_EVETPCC_CER_RN_E11_RESETVAL (0x00000000U)
10764 #define CSL_EVETPCC_CER_RN_E11_MAX (0x00000001U)
10766 #define CSL_EVETPCC_CER_RN_E27_MASK (0x08000000U)
10767 #define CSL_EVETPCC_CER_RN_E27_SHIFT (27U)
10768 #define CSL_EVETPCC_CER_RN_E27_RESETVAL (0x00000000U)
10769 #define CSL_EVETPCC_CER_RN_E27_MAX (0x00000001U)
10771 #define CSL_EVETPCC_CER_RN_E0_MASK (0x00000001U)
10772 #define CSL_EVETPCC_CER_RN_E0_SHIFT (0U)
10773 #define CSL_EVETPCC_CER_RN_E0_RESETVAL (0x00000000U)
10774 #define CSL_EVETPCC_CER_RN_E0_MAX (0x00000001U)
10776 #define CSL_EVETPCC_CER_RN_E12_MASK (0x00001000U)
10777 #define CSL_EVETPCC_CER_RN_E12_SHIFT (12U)
10778 #define CSL_EVETPCC_CER_RN_E12_RESETVAL (0x00000000U)
10779 #define CSL_EVETPCC_CER_RN_E12_MAX (0x00000001U)
10781 #define CSL_EVETPCC_CER_RN_E1_MASK (0x00000002U)
10782 #define CSL_EVETPCC_CER_RN_E1_SHIFT (1U)
10783 #define CSL_EVETPCC_CER_RN_E1_RESETVAL (0x00000000U)
10784 #define CSL_EVETPCC_CER_RN_E1_MAX (0x00000001U)
10786 #define CSL_EVETPCC_CER_RN_E13_MASK (0x00002000U)
10787 #define CSL_EVETPCC_CER_RN_E13_SHIFT (13U)
10788 #define CSL_EVETPCC_CER_RN_E13_RESETVAL (0x00000000U)
10789 #define CSL_EVETPCC_CER_RN_E13_MAX (0x00000001U)
10791 #define CSL_EVETPCC_CER_RN_E19_MASK (0x00080000U)
10792 #define CSL_EVETPCC_CER_RN_E19_SHIFT (19U)
10793 #define CSL_EVETPCC_CER_RN_E19_RESETVAL (0x00000000U)
10794 #define CSL_EVETPCC_CER_RN_E19_MAX (0x00000001U)
10796 #define CSL_EVETPCC_CER_RN_E2_MASK (0x00000004U)
10797 #define CSL_EVETPCC_CER_RN_E2_SHIFT (2U)
10798 #define CSL_EVETPCC_CER_RN_E2_RESETVAL (0x00000000U)
10799 #define CSL_EVETPCC_CER_RN_E2_MAX (0x00000001U)
10801 #define CSL_EVETPCC_CER_RN_E14_MASK (0x00004000U)
10802 #define CSL_EVETPCC_CER_RN_E14_SHIFT (14U)
10803 #define CSL_EVETPCC_CER_RN_E14_RESETVAL (0x00000000U)
10804 #define CSL_EVETPCC_CER_RN_E14_MAX (0x00000001U)
10806 #define CSL_EVETPCC_CER_RN_E3_MASK (0x00000008U)
10807 #define CSL_EVETPCC_CER_RN_E3_SHIFT (3U)
10808 #define CSL_EVETPCC_CER_RN_E3_RESETVAL (0x00000000U)
10809 #define CSL_EVETPCC_CER_RN_E3_MAX (0x00000001U)
10811 #define CSL_EVETPCC_CER_RN_E15_MASK (0x00008000U)
10812 #define CSL_EVETPCC_CER_RN_E15_SHIFT (15U)
10813 #define CSL_EVETPCC_CER_RN_E15_RESETVAL (0x00000000U)
10814 #define CSL_EVETPCC_CER_RN_E15_MAX (0x00000001U)
10816 #define CSL_EVETPCC_CER_RN_E21_MASK (0x00200000U)
10817 #define CSL_EVETPCC_CER_RN_E21_SHIFT (21U)
10818 #define CSL_EVETPCC_CER_RN_E21_RESETVAL (0x00000000U)
10819 #define CSL_EVETPCC_CER_RN_E21_MAX (0x00000001U)
10821 #define CSL_EVETPCC_CER_RN_E20_MASK (0x00100000U)
10822 #define CSL_EVETPCC_CER_RN_E20_SHIFT (20U)
10823 #define CSL_EVETPCC_CER_RN_E20_RESETVAL (0x00000000U)
10824 #define CSL_EVETPCC_CER_RN_E20_MAX (0x00000001U)
10826 #define CSL_EVETPCC_CER_RN_E4_MASK (0x00000010U)
10827 #define CSL_EVETPCC_CER_RN_E4_SHIFT (4U)
10828 #define CSL_EVETPCC_CER_RN_E4_RESETVAL (0x00000000U)
10829 #define CSL_EVETPCC_CER_RN_E4_MAX (0x00000001U)
10831 #define CSL_EVETPCC_CER_RN_E23_MASK (0x00800000U)
10832 #define CSL_EVETPCC_CER_RN_E23_SHIFT (23U)
10833 #define CSL_EVETPCC_CER_RN_E23_RESETVAL (0x00000000U)
10834 #define CSL_EVETPCC_CER_RN_E23_MAX (0x00000001U)
10836 #define CSL_EVETPCC_CER_RN_E16_MASK (0x00010000U)
10837 #define CSL_EVETPCC_CER_RN_E16_SHIFT (16U)
10838 #define CSL_EVETPCC_CER_RN_E16_RESETVAL (0x00000000U)
10839 #define CSL_EVETPCC_CER_RN_E16_MAX (0x00000001U)
10841 #define CSL_EVETPCC_CER_RN_E5_MASK (0x00000020U)
10842 #define CSL_EVETPCC_CER_RN_E5_SHIFT (5U)
10843 #define CSL_EVETPCC_CER_RN_E5_RESETVAL (0x00000000U)
10844 #define CSL_EVETPCC_CER_RN_E5_MAX (0x00000001U)
10846 #define CSL_EVETPCC_CER_RN_E22_MASK (0x00400000U)
10847 #define CSL_EVETPCC_CER_RN_E22_SHIFT (22U)
10848 #define CSL_EVETPCC_CER_RN_E22_RESETVAL (0x00000000U)
10849 #define CSL_EVETPCC_CER_RN_E22_MAX (0x00000001U)
10851 #define CSL_EVETPCC_CER_RN_E17_MASK (0x00020000U)
10852 #define CSL_EVETPCC_CER_RN_E17_SHIFT (17U)
10853 #define CSL_EVETPCC_CER_RN_E17_RESETVAL (0x00000000U)
10854 #define CSL_EVETPCC_CER_RN_E17_MAX (0x00000001U)
10856 #define CSL_EVETPCC_CER_RN_RESETVAL (0x00000000U)
10858 /* IECRH_RN */
10860 #define CSL_EVETPCC_IECRH_RN_I35_MASK (0x00000008U)
10861 #define CSL_EVETPCC_IECRH_RN_I35_SHIFT (3U)
10862 #define CSL_EVETPCC_IECRH_RN_I35_RESETVAL (0x00000000U)
10863 #define CSL_EVETPCC_IECRH_RN_I35_MAX (0x00000001U)
10865 #define CSL_EVETPCC_IECRH_RN_I48_MASK (0x00010000U)
10866 #define CSL_EVETPCC_IECRH_RN_I48_SHIFT (16U)
10867 #define CSL_EVETPCC_IECRH_RN_I48_RESETVAL (0x00000000U)
10868 #define CSL_EVETPCC_IECRH_RN_I48_MAX (0x00000001U)
10870 #define CSL_EVETPCC_IECRH_RN_I56_MASK (0x01000000U)
10871 #define CSL_EVETPCC_IECRH_RN_I56_SHIFT (24U)
10872 #define CSL_EVETPCC_IECRH_RN_I56_RESETVAL (0x00000000U)
10873 #define CSL_EVETPCC_IECRH_RN_I56_MAX (0x00000001U)
10875 #define CSL_EVETPCC_IECRH_RN_I34_MASK (0x00000004U)
10876 #define CSL_EVETPCC_IECRH_RN_I34_SHIFT (2U)
10877 #define CSL_EVETPCC_IECRH_RN_I34_RESETVAL (0x00000000U)
10878 #define CSL_EVETPCC_IECRH_RN_I34_MAX (0x00000001U)
10880 #define CSL_EVETPCC_IECRH_RN_I47_MASK (0x00008000U)
10881 #define CSL_EVETPCC_IECRH_RN_I47_SHIFT (15U)
10882 #define CSL_EVETPCC_IECRH_RN_I47_RESETVAL (0x00000000U)
10883 #define CSL_EVETPCC_IECRH_RN_I47_MAX (0x00000001U)
10885 #define CSL_EVETPCC_IECRH_RN_I46_MASK (0x00004000U)
10886 #define CSL_EVETPCC_IECRH_RN_I46_SHIFT (14U)
10887 #define CSL_EVETPCC_IECRH_RN_I46_RESETVAL (0x00000000U)
10888 #define CSL_EVETPCC_IECRH_RN_I46_MAX (0x00000001U)
10890 #define CSL_EVETPCC_IECRH_RN_I55_MASK (0x00800000U)
10891 #define CSL_EVETPCC_IECRH_RN_I55_SHIFT (23U)
10892 #define CSL_EVETPCC_IECRH_RN_I55_RESETVAL (0x00000000U)
10893 #define CSL_EVETPCC_IECRH_RN_I55_MAX (0x00000001U)
10895 #define CSL_EVETPCC_IECRH_RN_I45_MASK (0x00002000U)
10896 #define CSL_EVETPCC_IECRH_RN_I45_SHIFT (13U)
10897 #define CSL_EVETPCC_IECRH_RN_I45_RESETVAL (0x00000000U)
10898 #define CSL_EVETPCC_IECRH_RN_I45_MAX (0x00000001U)
10900 #define CSL_EVETPCC_IECRH_RN_I58_MASK (0x04000000U)
10901 #define CSL_EVETPCC_IECRH_RN_I58_SHIFT (26U)
10902 #define CSL_EVETPCC_IECRH_RN_I58_RESETVAL (0x00000000U)
10903 #define CSL_EVETPCC_IECRH_RN_I58_MAX (0x00000001U)
10905 #define CSL_EVETPCC_IECRH_RN_I32_MASK (0x00000001U)
10906 #define CSL_EVETPCC_IECRH_RN_I32_SHIFT (0U)
10907 #define CSL_EVETPCC_IECRH_RN_I32_RESETVAL (0x00000000U)
10908 #define CSL_EVETPCC_IECRH_RN_I32_MAX (0x00000001U)
10910 #define CSL_EVETPCC_IECRH_RN_I44_MASK (0x00001000U)
10911 #define CSL_EVETPCC_IECRH_RN_I44_SHIFT (12U)
10912 #define CSL_EVETPCC_IECRH_RN_I44_RESETVAL (0x00000000U)
10913 #define CSL_EVETPCC_IECRH_RN_I44_MAX (0x00000001U)
10915 #define CSL_EVETPCC_IECRH_RN_I33_MASK (0x00000002U)
10916 #define CSL_EVETPCC_IECRH_RN_I33_SHIFT (1U)
10917 #define CSL_EVETPCC_IECRH_RN_I33_RESETVAL (0x00000000U)
10918 #define CSL_EVETPCC_IECRH_RN_I33_MAX (0x00000001U)
10920 #define CSL_EVETPCC_IECRH_RN_I57_MASK (0x02000000U)
10921 #define CSL_EVETPCC_IECRH_RN_I57_SHIFT (25U)
10922 #define CSL_EVETPCC_IECRH_RN_I57_RESETVAL (0x00000000U)
10923 #define CSL_EVETPCC_IECRH_RN_I57_MAX (0x00000001U)
10925 #define CSL_EVETPCC_IECRH_RN_I43_MASK (0x00000800U)
10926 #define CSL_EVETPCC_IECRH_RN_I43_SHIFT (11U)
10927 #define CSL_EVETPCC_IECRH_RN_I43_RESETVAL (0x00000000U)
10928 #define CSL_EVETPCC_IECRH_RN_I43_MAX (0x00000001U)
10930 #define CSL_EVETPCC_IECRH_RN_I60_MASK (0x10000000U)
10931 #define CSL_EVETPCC_IECRH_RN_I60_SHIFT (28U)
10932 #define CSL_EVETPCC_IECRH_RN_I60_RESETVAL (0x00000000U)
10933 #define CSL_EVETPCC_IECRH_RN_I60_MAX (0x00000001U)
10935 #define CSL_EVETPCC_IECRH_RN_I42_MASK (0x00000400U)
10936 #define CSL_EVETPCC_IECRH_RN_I42_SHIFT (10U)
10937 #define CSL_EVETPCC_IECRH_RN_I42_RESETVAL (0x00000000U)
10938 #define CSL_EVETPCC_IECRH_RN_I42_MAX (0x00000001U)
10940 #define CSL_EVETPCC_IECRH_RN_I59_MASK (0x08000000U)
10941 #define CSL_EVETPCC_IECRH_RN_I59_SHIFT (27U)
10942 #define CSL_EVETPCC_IECRH_RN_I59_RESETVAL (0x00000000U)
10943 #define CSL_EVETPCC_IECRH_RN_I59_MAX (0x00000001U)
10945 #define CSL_EVETPCC_IECRH_RN_I41_MASK (0x00000200U)
10946 #define CSL_EVETPCC_IECRH_RN_I41_SHIFT (9U)
10947 #define CSL_EVETPCC_IECRH_RN_I41_RESETVAL (0x00000000U)
10948 #define CSL_EVETPCC_IECRH_RN_I41_MAX (0x00000001U)
10950 #define CSL_EVETPCC_IECRH_RN_I62_MASK (0x40000000U)
10951 #define CSL_EVETPCC_IECRH_RN_I62_SHIFT (30U)
10952 #define CSL_EVETPCC_IECRH_RN_I62_RESETVAL (0x00000000U)
10953 #define CSL_EVETPCC_IECRH_RN_I62_MAX (0x00000001U)
10955 #define CSL_EVETPCC_IECRH_RN_I61_MASK (0x20000000U)
10956 #define CSL_EVETPCC_IECRH_RN_I61_SHIFT (29U)
10957 #define CSL_EVETPCC_IECRH_RN_I61_RESETVAL (0x00000000U)
10958 #define CSL_EVETPCC_IECRH_RN_I61_MAX (0x00000001U)
10960 #define CSL_EVETPCC_IECRH_RN_I52_MASK (0x00100000U)
10961 #define CSL_EVETPCC_IECRH_RN_I52_SHIFT (20U)
10962 #define CSL_EVETPCC_IECRH_RN_I52_RESETVAL (0x00000000U)
10963 #define CSL_EVETPCC_IECRH_RN_I52_MAX (0x00000001U)
10965 #define CSL_EVETPCC_IECRH_RN_I38_MASK (0x00000040U)
10966 #define CSL_EVETPCC_IECRH_RN_I38_SHIFT (6U)
10967 #define CSL_EVETPCC_IECRH_RN_I38_RESETVAL (0x00000000U)
10968 #define CSL_EVETPCC_IECRH_RN_I38_MAX (0x00000001U)
10970 #define CSL_EVETPCC_IECRH_RN_I40_MASK (0x00000100U)
10971 #define CSL_EVETPCC_IECRH_RN_I40_SHIFT (8U)
10972 #define CSL_EVETPCC_IECRH_RN_I40_RESETVAL (0x00000000U)
10973 #define CSL_EVETPCC_IECRH_RN_I40_MAX (0x00000001U)
10975 #define CSL_EVETPCC_IECRH_RN_I51_MASK (0x00080000U)
10976 #define CSL_EVETPCC_IECRH_RN_I51_SHIFT (19U)
10977 #define CSL_EVETPCC_IECRH_RN_I51_RESETVAL (0x00000000U)
10978 #define CSL_EVETPCC_IECRH_RN_I51_MAX (0x00000001U)
10980 #define CSL_EVETPCC_IECRH_RN_I50_MASK (0x00040000U)
10981 #define CSL_EVETPCC_IECRH_RN_I50_SHIFT (18U)
10982 #define CSL_EVETPCC_IECRH_RN_I50_RESETVAL (0x00000000U)
10983 #define CSL_EVETPCC_IECRH_RN_I50_MAX (0x00000001U)
10985 #define CSL_EVETPCC_IECRH_RN_I63_MASK (0x80000000U)
10986 #define CSL_EVETPCC_IECRH_RN_I63_SHIFT (31U)
10987 #define CSL_EVETPCC_IECRH_RN_I63_RESETVAL (0x00000000U)
10988 #define CSL_EVETPCC_IECRH_RN_I63_MAX (0x00000001U)
10990 #define CSL_EVETPCC_IECRH_RN_I39_MASK (0x00000080U)
10991 #define CSL_EVETPCC_IECRH_RN_I39_SHIFT (7U)
10992 #define CSL_EVETPCC_IECRH_RN_I39_RESETVAL (0x00000000U)
10993 #define CSL_EVETPCC_IECRH_RN_I39_MAX (0x00000001U)
10995 #define CSL_EVETPCC_IECRH_RN_I54_MASK (0x00400000U)
10996 #define CSL_EVETPCC_IECRH_RN_I54_SHIFT (22U)
10997 #define CSL_EVETPCC_IECRH_RN_I54_RESETVAL (0x00000000U)
10998 #define CSL_EVETPCC_IECRH_RN_I54_MAX (0x00000001U)
11000 #define CSL_EVETPCC_IECRH_RN_I36_MASK (0x00000010U)
11001 #define CSL_EVETPCC_IECRH_RN_I36_SHIFT (4U)
11002 #define CSL_EVETPCC_IECRH_RN_I36_RESETVAL (0x00000000U)
11003 #define CSL_EVETPCC_IECRH_RN_I36_MAX (0x00000001U)
11005 #define CSL_EVETPCC_IECRH_RN_I53_MASK (0x00200000U)
11006 #define CSL_EVETPCC_IECRH_RN_I53_SHIFT (21U)
11007 #define CSL_EVETPCC_IECRH_RN_I53_RESETVAL (0x00000000U)
11008 #define CSL_EVETPCC_IECRH_RN_I53_MAX (0x00000001U)
11010 #define CSL_EVETPCC_IECRH_RN_I49_MASK (0x00020000U)
11011 #define CSL_EVETPCC_IECRH_RN_I49_SHIFT (17U)
11012 #define CSL_EVETPCC_IECRH_RN_I49_RESETVAL (0x00000000U)
11013 #define CSL_EVETPCC_IECRH_RN_I49_MAX (0x00000001U)
11015 #define CSL_EVETPCC_IECRH_RN_I37_MASK (0x00000020U)
11016 #define CSL_EVETPCC_IECRH_RN_I37_SHIFT (5U)
11017 #define CSL_EVETPCC_IECRH_RN_I37_RESETVAL (0x00000000U)
11018 #define CSL_EVETPCC_IECRH_RN_I37_MAX (0x00000001U)
11020 #define CSL_EVETPCC_IECRH_RN_RESETVAL (0x00000000U)
11022 /* IECR_RN */
11024 #define CSL_EVETPCC_IECR_RN_I27_MASK (0x08000000U)
11025 #define CSL_EVETPCC_IECR_RN_I27_SHIFT (27U)
11026 #define CSL_EVETPCC_IECR_RN_I27_RESETVAL (0x00000000U)
11027 #define CSL_EVETPCC_IECR_RN_I27_MAX (0x00000001U)
11029 #define CSL_EVETPCC_IECR_RN_I28_MASK (0x10000000U)
11030 #define CSL_EVETPCC_IECR_RN_I28_SHIFT (28U)
11031 #define CSL_EVETPCC_IECR_RN_I28_RESETVAL (0x00000000U)
11032 #define CSL_EVETPCC_IECR_RN_I28_MAX (0x00000001U)
11034 #define CSL_EVETPCC_IECR_RN_I25_MASK (0x02000000U)
11035 #define CSL_EVETPCC_IECR_RN_I25_SHIFT (25U)
11036 #define CSL_EVETPCC_IECR_RN_I25_RESETVAL (0x00000000U)
11037 #define CSL_EVETPCC_IECR_RN_I25_MAX (0x00000001U)
11039 #define CSL_EVETPCC_IECR_RN_I16_MASK (0x00010000U)
11040 #define CSL_EVETPCC_IECR_RN_I16_SHIFT (16U)
11041 #define CSL_EVETPCC_IECR_RN_I16_RESETVAL (0x00000000U)
11042 #define CSL_EVETPCC_IECR_RN_I16_MAX (0x00000001U)
11044 #define CSL_EVETPCC_IECR_RN_I26_MASK (0x04000000U)
11045 #define CSL_EVETPCC_IECR_RN_I26_SHIFT (26U)
11046 #define CSL_EVETPCC_IECR_RN_I26_RESETVAL (0x00000000U)
11047 #define CSL_EVETPCC_IECR_RN_I26_MAX (0x00000001U)
11049 #define CSL_EVETPCC_IECR_RN_I15_MASK (0x00008000U)
11050 #define CSL_EVETPCC_IECR_RN_I15_SHIFT (15U)
11051 #define CSL_EVETPCC_IECR_RN_I15_RESETVAL (0x00000000U)
11052 #define CSL_EVETPCC_IECR_RN_I15_MAX (0x00000001U)
11054 #define CSL_EVETPCC_IECR_RN_I14_MASK (0x00004000U)
11055 #define CSL_EVETPCC_IECR_RN_I14_SHIFT (14U)
11056 #define CSL_EVETPCC_IECR_RN_I14_RESETVAL (0x00000000U)
11057 #define CSL_EVETPCC_IECR_RN_I14_MAX (0x00000001U)
11059 #define CSL_EVETPCC_IECR_RN_I13_MASK (0x00002000U)
11060 #define CSL_EVETPCC_IECR_RN_I13_SHIFT (13U)
11061 #define CSL_EVETPCC_IECR_RN_I13_RESETVAL (0x00000000U)
11062 #define CSL_EVETPCC_IECR_RN_I13_MAX (0x00000001U)
11064 #define CSL_EVETPCC_IECR_RN_I0_MASK (0x00000001U)
11065 #define CSL_EVETPCC_IECR_RN_I0_SHIFT (0U)
11066 #define CSL_EVETPCC_IECR_RN_I0_RESETVAL (0x00000000U)
11067 #define CSL_EVETPCC_IECR_RN_I0_MAX (0x00000001U)
11069 #define CSL_EVETPCC_IECR_RN_I22_MASK (0x00400000U)
11070 #define CSL_EVETPCC_IECR_RN_I22_SHIFT (22U)
11071 #define CSL_EVETPCC_IECR_RN_I22_RESETVAL (0x00000000U)
11072 #define CSL_EVETPCC_IECR_RN_I22_MAX (0x00000001U)
11074 #define CSL_EVETPCC_IECR_RN_I10_MASK (0x00000400U)
11075 #define CSL_EVETPCC_IECR_RN_I10_SHIFT (10U)
11076 #define CSL_EVETPCC_IECR_RN_I10_RESETVAL (0x00000000U)
11077 #define CSL_EVETPCC_IECR_RN_I10_MAX (0x00000001U)
11079 #define CSL_EVETPCC_IECR_RN_I21_MASK (0x00200000U)
11080 #define CSL_EVETPCC_IECR_RN_I21_SHIFT (21U)
11081 #define CSL_EVETPCC_IECR_RN_I21_RESETVAL (0x00000000U)
11082 #define CSL_EVETPCC_IECR_RN_I21_MAX (0x00000001U)
11084 #define CSL_EVETPCC_IECR_RN_I9_MASK (0x00000200U)
11085 #define CSL_EVETPCC_IECR_RN_I9_SHIFT (9U)
11086 #define CSL_EVETPCC_IECR_RN_I9_RESETVAL (0x00000000U)
11087 #define CSL_EVETPCC_IECR_RN_I9_MAX (0x00000001U)
11089 #define CSL_EVETPCC_IECR_RN_I1_MASK (0x00000002U)
11090 #define CSL_EVETPCC_IECR_RN_I1_SHIFT (1U)
11091 #define CSL_EVETPCC_IECR_RN_I1_RESETVAL (0x00000000U)
11092 #define CSL_EVETPCC_IECR_RN_I1_MAX (0x00000001U)
11094 #define CSL_EVETPCC_IECR_RN_I24_MASK (0x01000000U)
11095 #define CSL_EVETPCC_IECR_RN_I24_SHIFT (24U)
11096 #define CSL_EVETPCC_IECR_RN_I24_RESETVAL (0x00000000U)
11097 #define CSL_EVETPCC_IECR_RN_I24_MAX (0x00000001U)
11099 #define CSL_EVETPCC_IECR_RN_I3_MASK (0x00000008U)
11100 #define CSL_EVETPCC_IECR_RN_I3_SHIFT (3U)
11101 #define CSL_EVETPCC_IECR_RN_I3_RESETVAL (0x00000000U)
11102 #define CSL_EVETPCC_IECR_RN_I3_MAX (0x00000001U)
11104 #define CSL_EVETPCC_IECR_RN_I2_MASK (0x00000004U)
11105 #define CSL_EVETPCC_IECR_RN_I2_SHIFT (2U)
11106 #define CSL_EVETPCC_IECR_RN_I2_RESETVAL (0x00000000U)
11107 #define CSL_EVETPCC_IECR_RN_I2_MAX (0x00000001U)
11109 #define CSL_EVETPCC_IECR_RN_I12_MASK (0x00001000U)
11110 #define CSL_EVETPCC_IECR_RN_I12_SHIFT (12U)
11111 #define CSL_EVETPCC_IECR_RN_I12_RESETVAL (0x00000000U)
11112 #define CSL_EVETPCC_IECR_RN_I12_MAX (0x00000001U)
11114 #define CSL_EVETPCC_IECR_RN_I23_MASK (0x00800000U)
11115 #define CSL_EVETPCC_IECR_RN_I23_SHIFT (23U)
11116 #define CSL_EVETPCC_IECR_RN_I23_RESETVAL (0x00000000U)
11117 #define CSL_EVETPCC_IECR_RN_I23_MAX (0x00000001U)
11119 #define CSL_EVETPCC_IECR_RN_I4_MASK (0x00000010U)
11120 #define CSL_EVETPCC_IECR_RN_I4_SHIFT (4U)
11121 #define CSL_EVETPCC_IECR_RN_I4_RESETVAL (0x00000000U)
11122 #define CSL_EVETPCC_IECR_RN_I4_MAX (0x00000001U)
11124 #define CSL_EVETPCC_IECR_RN_I11_MASK (0x00000800U)
11125 #define CSL_EVETPCC_IECR_RN_I11_SHIFT (11U)
11126 #define CSL_EVETPCC_IECR_RN_I11_RESETVAL (0x00000000U)
11127 #define CSL_EVETPCC_IECR_RN_I11_MAX (0x00000001U)
11129 #define CSL_EVETPCC_IECR_RN_I6_MASK (0x00000040U)
11130 #define CSL_EVETPCC_IECR_RN_I6_SHIFT (6U)
11131 #define CSL_EVETPCC_IECR_RN_I6_RESETVAL (0x00000000U)
11132 #define CSL_EVETPCC_IECR_RN_I6_MAX (0x00000001U)
11134 #define CSL_EVETPCC_IECR_RN_I31_MASK (0x80000000U)
11135 #define CSL_EVETPCC_IECR_RN_I31_SHIFT (31U)
11136 #define CSL_EVETPCC_IECR_RN_I31_RESETVAL (0x00000000U)
11137 #define CSL_EVETPCC_IECR_RN_I31_MAX (0x00000001U)
11139 #define CSL_EVETPCC_IECR_RN_I18_MASK (0x00040000U)
11140 #define CSL_EVETPCC_IECR_RN_I18_SHIFT (18U)
11141 #define CSL_EVETPCC_IECR_RN_I18_RESETVAL (0x00000000U)
11142 #define CSL_EVETPCC_IECR_RN_I18_MAX (0x00000001U)
11144 #define CSL_EVETPCC_IECR_RN_I17_MASK (0x00020000U)
11145 #define CSL_EVETPCC_IECR_RN_I17_SHIFT (17U)
11146 #define CSL_EVETPCC_IECR_RN_I17_RESETVAL (0x00000000U)
11147 #define CSL_EVETPCC_IECR_RN_I17_MAX (0x00000001U)
11149 #define CSL_EVETPCC_IECR_RN_I5_MASK (0x00000020U)
11150 #define CSL_EVETPCC_IECR_RN_I5_SHIFT (5U)
11151 #define CSL_EVETPCC_IECR_RN_I5_RESETVAL (0x00000000U)
11152 #define CSL_EVETPCC_IECR_RN_I5_MAX (0x00000001U)
11154 #define CSL_EVETPCC_IECR_RN_I20_MASK (0x00100000U)
11155 #define CSL_EVETPCC_IECR_RN_I20_SHIFT (20U)
11156 #define CSL_EVETPCC_IECR_RN_I20_RESETVAL (0x00000000U)
11157 #define CSL_EVETPCC_IECR_RN_I20_MAX (0x00000001U)
11159 #define CSL_EVETPCC_IECR_RN_I29_MASK (0x20000000U)
11160 #define CSL_EVETPCC_IECR_RN_I29_SHIFT (29U)
11161 #define CSL_EVETPCC_IECR_RN_I29_RESETVAL (0x00000000U)
11162 #define CSL_EVETPCC_IECR_RN_I29_MAX (0x00000001U)
11164 #define CSL_EVETPCC_IECR_RN_I8_MASK (0x00000100U)
11165 #define CSL_EVETPCC_IECR_RN_I8_SHIFT (8U)
11166 #define CSL_EVETPCC_IECR_RN_I8_RESETVAL (0x00000000U)
11167 #define CSL_EVETPCC_IECR_RN_I8_MAX (0x00000001U)
11169 #define CSL_EVETPCC_IECR_RN_I19_MASK (0x00080000U)
11170 #define CSL_EVETPCC_IECR_RN_I19_SHIFT (19U)
11171 #define CSL_EVETPCC_IECR_RN_I19_RESETVAL (0x00000000U)
11172 #define CSL_EVETPCC_IECR_RN_I19_MAX (0x00000001U)
11174 #define CSL_EVETPCC_IECR_RN_I30_MASK (0x40000000U)
11175 #define CSL_EVETPCC_IECR_RN_I30_SHIFT (30U)
11176 #define CSL_EVETPCC_IECR_RN_I30_RESETVAL (0x00000000U)
11177 #define CSL_EVETPCC_IECR_RN_I30_MAX (0x00000001U)
11179 #define CSL_EVETPCC_IECR_RN_I7_MASK (0x00000080U)
11180 #define CSL_EVETPCC_IECR_RN_I7_SHIFT (7U)
11181 #define CSL_EVETPCC_IECR_RN_I7_RESETVAL (0x00000000U)
11182 #define CSL_EVETPCC_IECR_RN_I7_MAX (0x00000001U)
11184 #define CSL_EVETPCC_IECR_RN_RESETVAL (0x00000000U)
11186 /* QSER_RN */
11188 #define CSL_EVETPCC_QSER_RN_E4_MASK (0x00000010U)
11189 #define CSL_EVETPCC_QSER_RN_E4_SHIFT (4U)
11190 #define CSL_EVETPCC_QSER_RN_E4_RESETVAL (0x00000000U)
11191 #define CSL_EVETPCC_QSER_RN_E4_MAX (0x00000001U)
11193 #define CSL_EVETPCC_QSER_RN_E3_MASK (0x00000008U)
11194 #define CSL_EVETPCC_QSER_RN_E3_SHIFT (3U)
11195 #define CSL_EVETPCC_QSER_RN_E3_RESETVAL (0x00000000U)
11196 #define CSL_EVETPCC_QSER_RN_E3_MAX (0x00000001U)
11198 #define CSL_EVETPCC_QSER_RN_E2_MASK (0x00000004U)
11199 #define CSL_EVETPCC_QSER_RN_E2_SHIFT (2U)
11200 #define CSL_EVETPCC_QSER_RN_E2_RESETVAL (0x00000000U)
11201 #define CSL_EVETPCC_QSER_RN_E2_MAX (0x00000001U)
11203 #define CSL_EVETPCC_QSER_RN_E1_MASK (0x00000002U)
11204 #define CSL_EVETPCC_QSER_RN_E1_SHIFT (1U)
11205 #define CSL_EVETPCC_QSER_RN_E1_RESETVAL (0x00000000U)
11206 #define CSL_EVETPCC_QSER_RN_E1_MAX (0x00000001U)
11208 #define CSL_EVETPCC_QSER_RN_E0_MASK (0x00000001U)
11209 #define CSL_EVETPCC_QSER_RN_E0_SHIFT (0U)
11210 #define CSL_EVETPCC_QSER_RN_E0_RESETVAL (0x00000000U)
11211 #define CSL_EVETPCC_QSER_RN_E0_MAX (0x00000001U)
11213 #define CSL_EVETPCC_QSER_RN_E7_MASK (0x00000080U)
11214 #define CSL_EVETPCC_QSER_RN_E7_SHIFT (7U)
11215 #define CSL_EVETPCC_QSER_RN_E7_RESETVAL (0x00000000U)
11216 #define CSL_EVETPCC_QSER_RN_E7_MAX (0x00000001U)
11218 #define CSL_EVETPCC_QSER_RN_E5_MASK (0x00000020U)
11219 #define CSL_EVETPCC_QSER_RN_E5_SHIFT (5U)
11220 #define CSL_EVETPCC_QSER_RN_E5_RESETVAL (0x00000000U)
11221 #define CSL_EVETPCC_QSER_RN_E5_MAX (0x00000001U)
11223 #define CSL_EVETPCC_QSER_RN_E6_MASK (0x00000040U)
11224 #define CSL_EVETPCC_QSER_RN_E6_SHIFT (6U)
11225 #define CSL_EVETPCC_QSER_RN_E6_RESETVAL (0x00000000U)
11226 #define CSL_EVETPCC_QSER_RN_E6_MAX (0x00000001U)
11228 #define CSL_EVETPCC_QSER_RN_RESETVAL (0x00000000U)
11230 /* IERH_RN */
11232 #define CSL_EVETPCC_IERH_RN_I48_MASK (0x00010000U)
11233 #define CSL_EVETPCC_IERH_RN_I48_SHIFT (16U)
11234 #define CSL_EVETPCC_IERH_RN_I48_RESETVAL (0x00000000U)
11235 #define CSL_EVETPCC_IERH_RN_I48_MAX (0x00000001U)
11237 #define CSL_EVETPCC_IERH_RN_I35_MASK (0x00000008U)
11238 #define CSL_EVETPCC_IERH_RN_I35_SHIFT (3U)
11239 #define CSL_EVETPCC_IERH_RN_I35_RESETVAL (0x00000000U)
11240 #define CSL_EVETPCC_IERH_RN_I35_MAX (0x00000001U)
11242 #define CSL_EVETPCC_IERH_RN_I34_MASK (0x00000004U)
11243 #define CSL_EVETPCC_IERH_RN_I34_SHIFT (2U)
11244 #define CSL_EVETPCC_IERH_RN_I34_RESETVAL (0x00000000U)
11245 #define CSL_EVETPCC_IERH_RN_I34_MAX (0x00000001U)
11247 #define CSL_EVETPCC_IERH_RN_I46_MASK (0x00004000U)
11248 #define CSL_EVETPCC_IERH_RN_I46_SHIFT (14U)
11249 #define CSL_EVETPCC_IERH_RN_I46_RESETVAL (0x00000000U)
11250 #define CSL_EVETPCC_IERH_RN_I46_MAX (0x00000001U)
11252 #define CSL_EVETPCC_IERH_RN_I59_MASK (0x08000000U)
11253 #define CSL_EVETPCC_IERH_RN_I59_SHIFT (27U)
11254 #define CSL_EVETPCC_IERH_RN_I59_RESETVAL (0x00000000U)
11255 #define CSL_EVETPCC_IERH_RN_I59_MAX (0x00000001U)
11257 #define CSL_EVETPCC_IERH_RN_I33_MASK (0x00000002U)
11258 #define CSL_EVETPCC_IERH_RN_I33_SHIFT (1U)
11259 #define CSL_EVETPCC_IERH_RN_I33_RESETVAL (0x00000000U)
11260 #define CSL_EVETPCC_IERH_RN_I33_MAX (0x00000001U)
11262 #define CSL_EVETPCC_IERH_RN_I45_MASK (0x00002000U)
11263 #define CSL_EVETPCC_IERH_RN_I45_SHIFT (13U)
11264 #define CSL_EVETPCC_IERH_RN_I45_RESETVAL (0x00000000U)
11265 #define CSL_EVETPCC_IERH_RN_I45_MAX (0x00000001U)
11267 #define CSL_EVETPCC_IERH_RN_I60_MASK (0x10000000U)
11268 #define CSL_EVETPCC_IERH_RN_I60_SHIFT (28U)
11269 #define CSL_EVETPCC_IERH_RN_I60_RESETVAL (0x00000000U)
11270 #define CSL_EVETPCC_IERH_RN_I60_MAX (0x00000001U)
11272 #define CSL_EVETPCC_IERH_RN_I32_MASK (0x00000001U)
11273 #define CSL_EVETPCC_IERH_RN_I32_SHIFT (0U)
11274 #define CSL_EVETPCC_IERH_RN_I32_RESETVAL (0x00000000U)
11275 #define CSL_EVETPCC_IERH_RN_I32_MAX (0x00000001U)
11277 #define CSL_EVETPCC_IERH_RN_I44_MASK (0x00001000U)
11278 #define CSL_EVETPCC_IERH_RN_I44_SHIFT (12U)
11279 #define CSL_EVETPCC_IERH_RN_I44_RESETVAL (0x00000000U)
11280 #define CSL_EVETPCC_IERH_RN_I44_MAX (0x00000001U)
11282 #define CSL_EVETPCC_IERH_RN_I61_MASK (0x20000000U)
11283 #define CSL_EVETPCC_IERH_RN_I61_SHIFT (29U)
11284 #define CSL_EVETPCC_IERH_RN_I61_RESETVAL (0x00000000U)
11285 #define CSL_EVETPCC_IERH_RN_I61_MAX (0x00000001U)
11287 #define CSL_EVETPCC_IERH_RN_I43_MASK (0x00000800U)
11288 #define CSL_EVETPCC_IERH_RN_I43_SHIFT (11U)
11289 #define CSL_EVETPCC_IERH_RN_I43_RESETVAL (0x00000000U)
11290 #define CSL_EVETPCC_IERH_RN_I43_MAX (0x00000001U)
11292 #define CSL_EVETPCC_IERH_RN_I49_MASK (0x00020000U)
11293 #define CSL_EVETPCC_IERH_RN_I49_SHIFT (17U)
11294 #define CSL_EVETPCC_IERH_RN_I49_RESETVAL (0x00000000U)
11295 #define CSL_EVETPCC_IERH_RN_I49_MAX (0x00000001U)
11297 #define CSL_EVETPCC_IERH_RN_I62_MASK (0x40000000U)
11298 #define CSL_EVETPCC_IERH_RN_I62_SHIFT (30U)
11299 #define CSL_EVETPCC_IERH_RN_I62_RESETVAL (0x00000000U)
11300 #define CSL_EVETPCC_IERH_RN_I62_MAX (0x00000001U)
11302 #define CSL_EVETPCC_IERH_RN_I50_MASK (0x00040000U)
11303 #define CSL_EVETPCC_IERH_RN_I50_SHIFT (18U)
11304 #define CSL_EVETPCC_IERH_RN_I50_RESETVAL (0x00000000U)
11305 #define CSL_EVETPCC_IERH_RN_I50_MAX (0x00000001U)
11307 #define CSL_EVETPCC_IERH_RN_I42_MASK (0x00000400U)
11308 #define CSL_EVETPCC_IERH_RN_I42_SHIFT (10U)
11309 #define CSL_EVETPCC_IERH_RN_I42_RESETVAL (0x00000000U)
11310 #define CSL_EVETPCC_IERH_RN_I42_MAX (0x00000001U)
11312 #define CSL_EVETPCC_IERH_RN_I63_MASK (0x80000000U)
11313 #define CSL_EVETPCC_IERH_RN_I63_SHIFT (31U)
11314 #define CSL_EVETPCC_IERH_RN_I63_RESETVAL (0x00000000U)
11315 #define CSL_EVETPCC_IERH_RN_I63_MAX (0x00000001U)
11317 #define CSL_EVETPCC_IERH_RN_I51_MASK (0x00080000U)
11318 #define CSL_EVETPCC_IERH_RN_I51_SHIFT (19U)
11319 #define CSL_EVETPCC_IERH_RN_I51_RESETVAL (0x00000000U)
11320 #define CSL_EVETPCC_IERH_RN_I51_MAX (0x00000001U)
11322 #define CSL_EVETPCC_IERH_RN_I41_MASK (0x00000200U)
11323 #define CSL_EVETPCC_IERH_RN_I41_SHIFT (9U)
11324 #define CSL_EVETPCC_IERH_RN_I41_RESETVAL (0x00000000U)
11325 #define CSL_EVETPCC_IERH_RN_I41_MAX (0x00000001U)
11327 #define CSL_EVETPCC_IERH_RN_I52_MASK (0x00100000U)
11328 #define CSL_EVETPCC_IERH_RN_I52_SHIFT (20U)
11329 #define CSL_EVETPCC_IERH_RN_I52_RESETVAL (0x00000000U)
11330 #define CSL_EVETPCC_IERH_RN_I52_MAX (0x00000001U)
11332 #define CSL_EVETPCC_IERH_RN_I40_MASK (0x00000100U)
11333 #define CSL_EVETPCC_IERH_RN_I40_SHIFT (8U)
11334 #define CSL_EVETPCC_IERH_RN_I40_RESETVAL (0x00000000U)
11335 #define CSL_EVETPCC_IERH_RN_I40_MAX (0x00000001U)
11337 #define CSL_EVETPCC_IERH_RN_I53_MASK (0x00200000U)
11338 #define CSL_EVETPCC_IERH_RN_I53_SHIFT (21U)
11339 #define CSL_EVETPCC_IERH_RN_I53_RESETVAL (0x00000000U)
11340 #define CSL_EVETPCC_IERH_RN_I53_MAX (0x00000001U)
11342 #define CSL_EVETPCC_IERH_RN_I39_MASK (0x00000080U)
11343 #define CSL_EVETPCC_IERH_RN_I39_SHIFT (7U)
11344 #define CSL_EVETPCC_IERH_RN_I39_RESETVAL (0x00000000U)
11345 #define CSL_EVETPCC_IERH_RN_I39_MAX (0x00000001U)
11347 #define CSL_EVETPCC_IERH_RN_I54_MASK (0x00400000U)
11348 #define CSL_EVETPCC_IERH_RN_I54_SHIFT (22U)
11349 #define CSL_EVETPCC_IERH_RN_I54_RESETVAL (0x00000000U)
11350 #define CSL_EVETPCC_IERH_RN_I54_MAX (0x00000001U)
11352 #define CSL_EVETPCC_IERH_RN_I55_MASK (0x00800000U)
11353 #define CSL_EVETPCC_IERH_RN_I55_SHIFT (23U)
11354 #define CSL_EVETPCC_IERH_RN_I55_RESETVAL (0x00000000U)
11355 #define CSL_EVETPCC_IERH_RN_I55_MAX (0x00000001U)
11357 #define CSL_EVETPCC_IERH_RN_I56_MASK (0x01000000U)
11358 #define CSL_EVETPCC_IERH_RN_I56_SHIFT (24U)
11359 #define CSL_EVETPCC_IERH_RN_I56_RESETVAL (0x00000000U)
11360 #define CSL_EVETPCC_IERH_RN_I56_MAX (0x00000001U)
11362 #define CSL_EVETPCC_IERH_RN_I38_MASK (0x00000040U)
11363 #define CSL_EVETPCC_IERH_RN_I38_SHIFT (6U)
11364 #define CSL_EVETPCC_IERH_RN_I38_RESETVAL (0x00000000U)
11365 #define CSL_EVETPCC_IERH_RN_I38_MAX (0x00000001U)
11367 #define CSL_EVETPCC_IERH_RN_I57_MASK (0x02000000U)
11368 #define CSL_EVETPCC_IERH_RN_I57_SHIFT (25U)
11369 #define CSL_EVETPCC_IERH_RN_I57_RESETVAL (0x00000000U)
11370 #define CSL_EVETPCC_IERH_RN_I57_MAX (0x00000001U)
11372 #define CSL_EVETPCC_IERH_RN_I58_MASK (0x04000000U)
11373 #define CSL_EVETPCC_IERH_RN_I58_SHIFT (26U)
11374 #define CSL_EVETPCC_IERH_RN_I58_RESETVAL (0x00000000U)
11375 #define CSL_EVETPCC_IERH_RN_I58_MAX (0x00000001U)
11377 #define CSL_EVETPCC_IERH_RN_I37_MASK (0x00000020U)
11378 #define CSL_EVETPCC_IERH_RN_I37_SHIFT (5U)
11379 #define CSL_EVETPCC_IERH_RN_I37_RESETVAL (0x00000000U)
11380 #define CSL_EVETPCC_IERH_RN_I37_MAX (0x00000001U)
11382 #define CSL_EVETPCC_IERH_RN_I47_MASK (0x00008000U)
11383 #define CSL_EVETPCC_IERH_RN_I47_SHIFT (15U)
11384 #define CSL_EVETPCC_IERH_RN_I47_RESETVAL (0x00000000U)
11385 #define CSL_EVETPCC_IERH_RN_I47_MAX (0x00000001U)
11387 #define CSL_EVETPCC_IERH_RN_I36_MASK (0x00000010U)
11388 #define CSL_EVETPCC_IERH_RN_I36_SHIFT (4U)
11389 #define CSL_EVETPCC_IERH_RN_I36_RESETVAL (0x00000000U)
11390 #define CSL_EVETPCC_IERH_RN_I36_MAX (0x00000001U)
11392 #define CSL_EVETPCC_IERH_RN_RESETVAL (0x00000000U)
11394 /* ECR_RN */
11396 #define CSL_EVETPCC_ECR_RN_E16_MASK (0x00010000U)
11397 #define CSL_EVETPCC_ECR_RN_E16_SHIFT (16U)
11398 #define CSL_EVETPCC_ECR_RN_E16_RESETVAL (0x00000000U)
11399 #define CSL_EVETPCC_ECR_RN_E16_MAX (0x00000001U)
11401 #define CSL_EVETPCC_ECR_RN_E10_MASK (0x00000400U)
11402 #define CSL_EVETPCC_ECR_RN_E10_SHIFT (10U)
11403 #define CSL_EVETPCC_ECR_RN_E10_RESETVAL (0x00000000U)
11404 #define CSL_EVETPCC_ECR_RN_E10_MAX (0x00000001U)
11406 #define CSL_EVETPCC_ECR_RN_E30_MASK (0x40000000U)
11407 #define CSL_EVETPCC_ECR_RN_E30_SHIFT (30U)
11408 #define CSL_EVETPCC_ECR_RN_E30_RESETVAL (0x00000000U)
11409 #define CSL_EVETPCC_ECR_RN_E30_MAX (0x00000001U)
11411 #define CSL_EVETPCC_ECR_RN_E19_MASK (0x00080000U)
11412 #define CSL_EVETPCC_ECR_RN_E19_SHIFT (19U)
11413 #define CSL_EVETPCC_ECR_RN_E19_RESETVAL (0x00000000U)
11414 #define CSL_EVETPCC_ECR_RN_E19_MAX (0x00000001U)
11416 #define CSL_EVETPCC_ECR_RN_E29_MASK (0x20000000U)
11417 #define CSL_EVETPCC_ECR_RN_E29_SHIFT (29U)
11418 #define CSL_EVETPCC_ECR_RN_E29_RESETVAL (0x00000000U)
11419 #define CSL_EVETPCC_ECR_RN_E29_MAX (0x00000001U)
11421 #define CSL_EVETPCC_ECR_RN_E12_MASK (0x00001000U)
11422 #define CSL_EVETPCC_ECR_RN_E12_SHIFT (12U)
11423 #define CSL_EVETPCC_ECR_RN_E12_RESETVAL (0x00000000U)
11424 #define CSL_EVETPCC_ECR_RN_E12_MAX (0x00000001U)
11426 #define CSL_EVETPCC_ECR_RN_E18_MASK (0x00040000U)
11427 #define CSL_EVETPCC_ECR_RN_E18_SHIFT (18U)
11428 #define CSL_EVETPCC_ECR_RN_E18_RESETVAL (0x00000000U)
11429 #define CSL_EVETPCC_ECR_RN_E18_MAX (0x00000001U)
11431 #define CSL_EVETPCC_ECR_RN_E11_MASK (0x00000800U)
11432 #define CSL_EVETPCC_ECR_RN_E11_SHIFT (11U)
11433 #define CSL_EVETPCC_ECR_RN_E11_RESETVAL (0x00000000U)
11434 #define CSL_EVETPCC_ECR_RN_E11_MAX (0x00000001U)
11436 #define CSL_EVETPCC_ECR_RN_E21_MASK (0x00200000U)
11437 #define CSL_EVETPCC_ECR_RN_E21_SHIFT (21U)
11438 #define CSL_EVETPCC_ECR_RN_E21_RESETVAL (0x00000000U)
11439 #define CSL_EVETPCC_ECR_RN_E21_MAX (0x00000001U)
11441 #define CSL_EVETPCC_ECR_RN_E31_MASK (0x80000000U)
11442 #define CSL_EVETPCC_ECR_RN_E31_SHIFT (31U)
11443 #define CSL_EVETPCC_ECR_RN_E31_RESETVAL (0x00000000U)
11444 #define CSL_EVETPCC_ECR_RN_E31_MAX (0x00000001U)
11446 #define CSL_EVETPCC_ECR_RN_E14_MASK (0x00004000U)
11447 #define CSL_EVETPCC_ECR_RN_E14_SHIFT (14U)
11448 #define CSL_EVETPCC_ECR_RN_E14_RESETVAL (0x00000000U)
11449 #define CSL_EVETPCC_ECR_RN_E14_MAX (0x00000001U)
11451 #define CSL_EVETPCC_ECR_RN_E26_MASK (0x04000000U)
11452 #define CSL_EVETPCC_ECR_RN_E26_SHIFT (26U)
11453 #define CSL_EVETPCC_ECR_RN_E26_RESETVAL (0x00000000U)
11454 #define CSL_EVETPCC_ECR_RN_E26_MAX (0x00000001U)
11456 #define CSL_EVETPCC_ECR_RN_E13_MASK (0x00002000U)
11457 #define CSL_EVETPCC_ECR_RN_E13_SHIFT (13U)
11458 #define CSL_EVETPCC_ECR_RN_E13_RESETVAL (0x00000000U)
11459 #define CSL_EVETPCC_ECR_RN_E13_MAX (0x00000001U)
11461 #define CSL_EVETPCC_ECR_RN_E25_MASK (0x02000000U)
11462 #define CSL_EVETPCC_ECR_RN_E25_SHIFT (25U)
11463 #define CSL_EVETPCC_ECR_RN_E25_RESETVAL (0x00000000U)
11464 #define CSL_EVETPCC_ECR_RN_E25_MAX (0x00000001U)
11466 #define CSL_EVETPCC_ECR_RN_E15_MASK (0x00008000U)
11467 #define CSL_EVETPCC_ECR_RN_E15_SHIFT (15U)
11468 #define CSL_EVETPCC_ECR_RN_E15_RESETVAL (0x00000000U)
11469 #define CSL_EVETPCC_ECR_RN_E15_MAX (0x00000001U)
11471 #define CSL_EVETPCC_ECR_RN_E28_MASK (0x10000000U)
11472 #define CSL_EVETPCC_ECR_RN_E28_SHIFT (28U)
11473 #define CSL_EVETPCC_ECR_RN_E28_RESETVAL (0x00000000U)
11474 #define CSL_EVETPCC_ECR_RN_E28_MAX (0x00000001U)
11476 #define CSL_EVETPCC_ECR_RN_E17_MASK (0x00020000U)
11477 #define CSL_EVETPCC_ECR_RN_E17_SHIFT (17U)
11478 #define CSL_EVETPCC_ECR_RN_E17_RESETVAL (0x00000000U)
11479 #define CSL_EVETPCC_ECR_RN_E17_MAX (0x00000001U)
11481 #define CSL_EVETPCC_ECR_RN_E27_MASK (0x08000000U)
11482 #define CSL_EVETPCC_ECR_RN_E27_SHIFT (27U)
11483 #define CSL_EVETPCC_ECR_RN_E27_RESETVAL (0x00000000U)
11484 #define CSL_EVETPCC_ECR_RN_E27_MAX (0x00000001U)
11486 #define CSL_EVETPCC_ECR_RN_E4_MASK (0x00000010U)
11487 #define CSL_EVETPCC_ECR_RN_E4_SHIFT (4U)
11488 #define CSL_EVETPCC_ECR_RN_E4_RESETVAL (0x00000000U)
11489 #define CSL_EVETPCC_ECR_RN_E4_MAX (0x00000001U)
11491 #define CSL_EVETPCC_ECR_RN_E24_MASK (0x01000000U)
11492 #define CSL_EVETPCC_ECR_RN_E24_SHIFT (24U)
11493 #define CSL_EVETPCC_ECR_RN_E24_RESETVAL (0x00000000U)
11494 #define CSL_EVETPCC_ECR_RN_E24_MAX (0x00000001U)
11496 #define CSL_EVETPCC_ECR_RN_E2_MASK (0x00000004U)
11497 #define CSL_EVETPCC_ECR_RN_E2_SHIFT (2U)
11498 #define CSL_EVETPCC_ECR_RN_E2_RESETVAL (0x00000000U)
11499 #define CSL_EVETPCC_ECR_RN_E2_MAX (0x00000001U)
11501 #define CSL_EVETPCC_ECR_RN_E3_MASK (0x00000008U)
11502 #define CSL_EVETPCC_ECR_RN_E3_SHIFT (3U)
11503 #define CSL_EVETPCC_ECR_RN_E3_RESETVAL (0x00000000U)
11504 #define CSL_EVETPCC_ECR_RN_E3_MAX (0x00000001U)
11506 #define CSL_EVETPCC_ECR_RN_E0_MASK (0x00000001U)
11507 #define CSL_EVETPCC_ECR_RN_E0_SHIFT (0U)
11508 #define CSL_EVETPCC_ECR_RN_E0_RESETVAL (0x00000000U)
11509 #define CSL_EVETPCC_ECR_RN_E0_MAX (0x00000001U)
11511 #define CSL_EVETPCC_ECR_RN_E20_MASK (0x00100000U)
11512 #define CSL_EVETPCC_ECR_RN_E20_SHIFT (20U)
11513 #define CSL_EVETPCC_ECR_RN_E20_RESETVAL (0x00000000U)
11514 #define CSL_EVETPCC_ECR_RN_E20_MAX (0x00000001U)
11516 #define CSL_EVETPCC_ECR_RN_E6_MASK (0x00000040U)
11517 #define CSL_EVETPCC_ECR_RN_E6_SHIFT (6U)
11518 #define CSL_EVETPCC_ECR_RN_E6_RESETVAL (0x00000000U)
11519 #define CSL_EVETPCC_ECR_RN_E6_MAX (0x00000001U)
11521 #define CSL_EVETPCC_ECR_RN_E1_MASK (0x00000002U)
11522 #define CSL_EVETPCC_ECR_RN_E1_SHIFT (1U)
11523 #define CSL_EVETPCC_ECR_RN_E1_RESETVAL (0x00000000U)
11524 #define CSL_EVETPCC_ECR_RN_E1_MAX (0x00000001U)
11526 #define CSL_EVETPCC_ECR_RN_E5_MASK (0x00000020U)
11527 #define CSL_EVETPCC_ECR_RN_E5_SHIFT (5U)
11528 #define CSL_EVETPCC_ECR_RN_E5_RESETVAL (0x00000000U)
11529 #define CSL_EVETPCC_ECR_RN_E5_MAX (0x00000001U)
11531 #define CSL_EVETPCC_ECR_RN_E23_MASK (0x00800000U)
11532 #define CSL_EVETPCC_ECR_RN_E23_SHIFT (23U)
11533 #define CSL_EVETPCC_ECR_RN_E23_RESETVAL (0x00000000U)
11534 #define CSL_EVETPCC_ECR_RN_E23_MAX (0x00000001U)
11536 #define CSL_EVETPCC_ECR_RN_E8_MASK (0x00000100U)
11537 #define CSL_EVETPCC_ECR_RN_E8_SHIFT (8U)
11538 #define CSL_EVETPCC_ECR_RN_E8_RESETVAL (0x00000000U)
11539 #define CSL_EVETPCC_ECR_RN_E8_MAX (0x00000001U)
11541 #define CSL_EVETPCC_ECR_RN_E9_MASK (0x00000200U)
11542 #define CSL_EVETPCC_ECR_RN_E9_SHIFT (9U)
11543 #define CSL_EVETPCC_ECR_RN_E9_RESETVAL (0x00000000U)
11544 #define CSL_EVETPCC_ECR_RN_E9_MAX (0x00000001U)
11546 #define CSL_EVETPCC_ECR_RN_E22_MASK (0x00400000U)
11547 #define CSL_EVETPCC_ECR_RN_E22_SHIFT (22U)
11548 #define CSL_EVETPCC_ECR_RN_E22_RESETVAL (0x00000000U)
11549 #define CSL_EVETPCC_ECR_RN_E22_MAX (0x00000001U)
11551 #define CSL_EVETPCC_ECR_RN_E7_MASK (0x00000080U)
11552 #define CSL_EVETPCC_ECR_RN_E7_SHIFT (7U)
11553 #define CSL_EVETPCC_ECR_RN_E7_RESETVAL (0x00000000U)
11554 #define CSL_EVETPCC_ECR_RN_E7_MAX (0x00000001U)
11556 #define CSL_EVETPCC_ECR_RN_RESETVAL (0x00000000U)
11558 /* EERH_RN */
11560 #define CSL_EVETPCC_EERH_RN_E47_MASK (0x00008000U)
11561 #define CSL_EVETPCC_EERH_RN_E47_SHIFT (15U)
11562 #define CSL_EVETPCC_EERH_RN_E47_RESETVAL (0x00000000U)
11563 #define CSL_EVETPCC_EERH_RN_E47_MAX (0x00000001U)
11565 #define CSL_EVETPCC_EERH_RN_E45_MASK (0x00002000U)
11566 #define CSL_EVETPCC_EERH_RN_E45_SHIFT (13U)
11567 #define CSL_EVETPCC_EERH_RN_E45_RESETVAL (0x00000000U)
11568 #define CSL_EVETPCC_EERH_RN_E45_MAX (0x00000001U)
11570 #define CSL_EVETPCC_EERH_RN_E35_MASK (0x00000008U)
11571 #define CSL_EVETPCC_EERH_RN_E35_SHIFT (3U)
11572 #define CSL_EVETPCC_EERH_RN_E35_RESETVAL (0x00000000U)
11573 #define CSL_EVETPCC_EERH_RN_E35_MAX (0x00000001U)
11575 #define CSL_EVETPCC_EERH_RN_E56_MASK (0x01000000U)
11576 #define CSL_EVETPCC_EERH_RN_E56_SHIFT (24U)
11577 #define CSL_EVETPCC_EERH_RN_E56_RESETVAL (0x00000000U)
11578 #define CSL_EVETPCC_EERH_RN_E56_MAX (0x00000001U)
11580 #define CSL_EVETPCC_EERH_RN_E46_MASK (0x00004000U)
11581 #define CSL_EVETPCC_EERH_RN_E46_SHIFT (14U)
11582 #define CSL_EVETPCC_EERH_RN_E46_RESETVAL (0x00000000U)
11583 #define CSL_EVETPCC_EERH_RN_E46_MAX (0x00000001U)
11585 #define CSL_EVETPCC_EERH_RN_E36_MASK (0x00000010U)
11586 #define CSL_EVETPCC_EERH_RN_E36_SHIFT (4U)
11587 #define CSL_EVETPCC_EERH_RN_E36_RESETVAL (0x00000000U)
11588 #define CSL_EVETPCC_EERH_RN_E36_MAX (0x00000001U)
11590 #define CSL_EVETPCC_EERH_RN_E55_MASK (0x00800000U)
11591 #define CSL_EVETPCC_EERH_RN_E55_SHIFT (23U)
11592 #define CSL_EVETPCC_EERH_RN_E55_RESETVAL (0x00000000U)
11593 #define CSL_EVETPCC_EERH_RN_E55_MAX (0x00000001U)
11595 #define CSL_EVETPCC_EERH_RN_E33_MASK (0x00000002U)
11596 #define CSL_EVETPCC_EERH_RN_E33_SHIFT (1U)
11597 #define CSL_EVETPCC_EERH_RN_E33_RESETVAL (0x00000000U)
11598 #define CSL_EVETPCC_EERH_RN_E33_MAX (0x00000001U)
11600 #define CSL_EVETPCC_EERH_RN_E54_MASK (0x00400000U)
11601 #define CSL_EVETPCC_EERH_RN_E54_SHIFT (22U)
11602 #define CSL_EVETPCC_EERH_RN_E54_RESETVAL (0x00000000U)
11603 #define CSL_EVETPCC_EERH_RN_E54_MAX (0x00000001U)
11605 #define CSL_EVETPCC_EERH_RN_E43_MASK (0x00000800U)
11606 #define CSL_EVETPCC_EERH_RN_E43_SHIFT (11U)
11607 #define CSL_EVETPCC_EERH_RN_E43_RESETVAL (0x00000000U)
11608 #define CSL_EVETPCC_EERH_RN_E43_MAX (0x00000001U)
11610 #define CSL_EVETPCC_EERH_RN_E53_MASK (0x00200000U)
11611 #define CSL_EVETPCC_EERH_RN_E53_SHIFT (21U)
11612 #define CSL_EVETPCC_EERH_RN_E53_RESETVAL (0x00000000U)
11613 #define CSL_EVETPCC_EERH_RN_E53_MAX (0x00000001U)
11615 #define CSL_EVETPCC_EERH_RN_E63_MASK (0x80000000U)
11616 #define CSL_EVETPCC_EERH_RN_E63_SHIFT (31U)
11617 #define CSL_EVETPCC_EERH_RN_E63_RESETVAL (0x00000000U)
11618 #define CSL_EVETPCC_EERH_RN_E63_MAX (0x00000001U)
11620 #define CSL_EVETPCC_EERH_RN_E34_MASK (0x00000004U)
11621 #define CSL_EVETPCC_EERH_RN_E34_SHIFT (2U)
11622 #define CSL_EVETPCC_EERH_RN_E34_RESETVAL (0x00000000U)
11623 #define CSL_EVETPCC_EERH_RN_E34_MAX (0x00000001U)
11625 #define CSL_EVETPCC_EERH_RN_E44_MASK (0x00001000U)
11626 #define CSL_EVETPCC_EERH_RN_E44_SHIFT (12U)
11627 #define CSL_EVETPCC_EERH_RN_E44_RESETVAL (0x00000000U)
11628 #define CSL_EVETPCC_EERH_RN_E44_MAX (0x00000001U)
11630 #define CSL_EVETPCC_EERH_RN_E52_MASK (0x00100000U)
11631 #define CSL_EVETPCC_EERH_RN_E52_SHIFT (20U)
11632 #define CSL_EVETPCC_EERH_RN_E52_RESETVAL (0x00000000U)
11633 #define CSL_EVETPCC_EERH_RN_E52_MAX (0x00000001U)
11635 #define CSL_EVETPCC_EERH_RN_E41_MASK (0x00000200U)
11636 #define CSL_EVETPCC_EERH_RN_E41_SHIFT (9U)
11637 #define CSL_EVETPCC_EERH_RN_E41_RESETVAL (0x00000000U)
11638 #define CSL_EVETPCC_EERH_RN_E41_MAX (0x00000001U)
11640 #define CSL_EVETPCC_EERH_RN_E62_MASK (0x40000000U)
11641 #define CSL_EVETPCC_EERH_RN_E62_SHIFT (30U)
11642 #define CSL_EVETPCC_EERH_RN_E62_RESETVAL (0x00000000U)
11643 #define CSL_EVETPCC_EERH_RN_E62_MAX (0x00000001U)
11645 #define CSL_EVETPCC_EERH_RN_E32_MASK (0x00000001U)
11646 #define CSL_EVETPCC_EERH_RN_E32_SHIFT (0U)
11647 #define CSL_EVETPCC_EERH_RN_E32_RESETVAL (0x00000000U)
11648 #define CSL_EVETPCC_EERH_RN_E32_MAX (0x00000001U)
11650 #define CSL_EVETPCC_EERH_RN_E51_MASK (0x00080000U)
11651 #define CSL_EVETPCC_EERH_RN_E51_SHIFT (19U)
11652 #define CSL_EVETPCC_EERH_RN_E51_RESETVAL (0x00000000U)
11653 #define CSL_EVETPCC_EERH_RN_E51_MAX (0x00000001U)
11655 #define CSL_EVETPCC_EERH_RN_E42_MASK (0x00000400U)
11656 #define CSL_EVETPCC_EERH_RN_E42_SHIFT (10U)
11657 #define CSL_EVETPCC_EERH_RN_E42_RESETVAL (0x00000000U)
11658 #define CSL_EVETPCC_EERH_RN_E42_MAX (0x00000001U)
11660 #define CSL_EVETPCC_EERH_RN_E61_MASK (0x20000000U)
11661 #define CSL_EVETPCC_EERH_RN_E61_SHIFT (29U)
11662 #define CSL_EVETPCC_EERH_RN_E61_RESETVAL (0x00000000U)
11663 #define CSL_EVETPCC_EERH_RN_E61_MAX (0x00000001U)
11665 #define CSL_EVETPCC_EERH_RN_E50_MASK (0x00040000U)
11666 #define CSL_EVETPCC_EERH_RN_E50_SHIFT (18U)
11667 #define CSL_EVETPCC_EERH_RN_E50_RESETVAL (0x00000000U)
11668 #define CSL_EVETPCC_EERH_RN_E50_MAX (0x00000001U)
11670 #define CSL_EVETPCC_EERH_RN_E39_MASK (0x00000080U)
11671 #define CSL_EVETPCC_EERH_RN_E39_SHIFT (7U)
11672 #define CSL_EVETPCC_EERH_RN_E39_RESETVAL (0x00000000U)
11673 #define CSL_EVETPCC_EERH_RN_E39_MAX (0x00000001U)
11675 #define CSL_EVETPCC_EERH_RN_E60_MASK (0x10000000U)
11676 #define CSL_EVETPCC_EERH_RN_E60_SHIFT (28U)
11677 #define CSL_EVETPCC_EERH_RN_E60_RESETVAL (0x00000000U)
11678 #define CSL_EVETPCC_EERH_RN_E60_MAX (0x00000001U)
11680 #define CSL_EVETPCC_EERH_RN_E49_MASK (0x00020000U)
11681 #define CSL_EVETPCC_EERH_RN_E49_SHIFT (17U)
11682 #define CSL_EVETPCC_EERH_RN_E49_RESETVAL (0x00000000U)
11683 #define CSL_EVETPCC_EERH_RN_E49_MAX (0x00000001U)
11685 #define CSL_EVETPCC_EERH_RN_E40_MASK (0x00000100U)
11686 #define CSL_EVETPCC_EERH_RN_E40_SHIFT (8U)
11687 #define CSL_EVETPCC_EERH_RN_E40_RESETVAL (0x00000000U)
11688 #define CSL_EVETPCC_EERH_RN_E40_MAX (0x00000001U)
11690 #define CSL_EVETPCC_EERH_RN_E59_MASK (0x08000000U)
11691 #define CSL_EVETPCC_EERH_RN_E59_SHIFT (27U)
11692 #define CSL_EVETPCC_EERH_RN_E59_RESETVAL (0x00000000U)
11693 #define CSL_EVETPCC_EERH_RN_E59_MAX (0x00000001U)
11695 #define CSL_EVETPCC_EERH_RN_E48_MASK (0x00010000U)
11696 #define CSL_EVETPCC_EERH_RN_E48_SHIFT (16U)
11697 #define CSL_EVETPCC_EERH_RN_E48_RESETVAL (0x00000000U)
11698 #define CSL_EVETPCC_EERH_RN_E48_MAX (0x00000001U)
11700 #define CSL_EVETPCC_EERH_RN_E58_MASK (0x04000000U)
11701 #define CSL_EVETPCC_EERH_RN_E58_SHIFT (26U)
11702 #define CSL_EVETPCC_EERH_RN_E58_RESETVAL (0x00000000U)
11703 #define CSL_EVETPCC_EERH_RN_E58_MAX (0x00000001U)
11705 #define CSL_EVETPCC_EERH_RN_E37_MASK (0x00000020U)
11706 #define CSL_EVETPCC_EERH_RN_E37_SHIFT (5U)
11707 #define CSL_EVETPCC_EERH_RN_E37_RESETVAL (0x00000000U)
11708 #define CSL_EVETPCC_EERH_RN_E37_MAX (0x00000001U)
11710 #define CSL_EVETPCC_EERH_RN_E57_MASK (0x02000000U)
11711 #define CSL_EVETPCC_EERH_RN_E57_SHIFT (25U)
11712 #define CSL_EVETPCC_EERH_RN_E57_RESETVAL (0x00000000U)
11713 #define CSL_EVETPCC_EERH_RN_E57_MAX (0x00000001U)
11715 #define CSL_EVETPCC_EERH_RN_E38_MASK (0x00000040U)
11716 #define CSL_EVETPCC_EERH_RN_E38_SHIFT (6U)
11717 #define CSL_EVETPCC_EERH_RN_E38_RESETVAL (0x00000000U)
11718 #define CSL_EVETPCC_EERH_RN_E38_MAX (0x00000001U)
11720 #define CSL_EVETPCC_EERH_RN_RESETVAL (0x00000000U)
11722 /* IPR_RN */
11724 #define CSL_EVETPCC_IPR_RN_I15_MASK (0x00008000U)
11725 #define CSL_EVETPCC_IPR_RN_I15_SHIFT (15U)
11726 #define CSL_EVETPCC_IPR_RN_I15_RESETVAL (0x00000000U)
11727 #define CSL_EVETPCC_IPR_RN_I15_MAX (0x00000001U)
11729 #define CSL_EVETPCC_IPR_RN_I27_MASK (0x08000000U)
11730 #define CSL_EVETPCC_IPR_RN_I27_SHIFT (27U)
11731 #define CSL_EVETPCC_IPR_RN_I27_RESETVAL (0x00000000U)
11732 #define CSL_EVETPCC_IPR_RN_I27_MAX (0x00000001U)
11734 #define CSL_EVETPCC_IPR_RN_I3_MASK (0x00000008U)
11735 #define CSL_EVETPCC_IPR_RN_I3_SHIFT (3U)
11736 #define CSL_EVETPCC_IPR_RN_I3_RESETVAL (0x00000000U)
11737 #define CSL_EVETPCC_IPR_RN_I3_MAX (0x00000001U)
11739 #define CSL_EVETPCC_IPR_RN_I14_MASK (0x00004000U)
11740 #define CSL_EVETPCC_IPR_RN_I14_SHIFT (14U)
11741 #define CSL_EVETPCC_IPR_RN_I14_RESETVAL (0x00000000U)
11742 #define CSL_EVETPCC_IPR_RN_I14_MAX (0x00000001U)
11744 #define CSL_EVETPCC_IPR_RN_I2_MASK (0x00000004U)
11745 #define CSL_EVETPCC_IPR_RN_I2_SHIFT (2U)
11746 #define CSL_EVETPCC_IPR_RN_I2_RESETVAL (0x00000000U)
11747 #define CSL_EVETPCC_IPR_RN_I2_MAX (0x00000001U)
11749 #define CSL_EVETPCC_IPR_RN_I1_MASK (0x00000002U)
11750 #define CSL_EVETPCC_IPR_RN_I1_SHIFT (1U)
11751 #define CSL_EVETPCC_IPR_RN_I1_RESETVAL (0x00000000U)
11752 #define CSL_EVETPCC_IPR_RN_I1_MAX (0x00000001U)
11754 #define CSL_EVETPCC_IPR_RN_I13_MASK (0x00002000U)
11755 #define CSL_EVETPCC_IPR_RN_I13_SHIFT (13U)
11756 #define CSL_EVETPCC_IPR_RN_I13_RESETVAL (0x00000000U)
11757 #define CSL_EVETPCC_IPR_RN_I13_MAX (0x00000001U)
11759 #define CSL_EVETPCC_IPR_RN_I28_MASK (0x10000000U)
11760 #define CSL_EVETPCC_IPR_RN_I28_SHIFT (28U)
11761 #define CSL_EVETPCC_IPR_RN_I28_RESETVAL (0x00000000U)
11762 #define CSL_EVETPCC_IPR_RN_I28_MAX (0x00000001U)
11764 #define CSL_EVETPCC_IPR_RN_I17_MASK (0x00020000U)
11765 #define CSL_EVETPCC_IPR_RN_I17_SHIFT (17U)
11766 #define CSL_EVETPCC_IPR_RN_I17_RESETVAL (0x00000000U)
11767 #define CSL_EVETPCC_IPR_RN_I17_MAX (0x00000001U)
11769 #define CSL_EVETPCC_IPR_RN_I0_MASK (0x00000001U)
11770 #define CSL_EVETPCC_IPR_RN_I0_SHIFT (0U)
11771 #define CSL_EVETPCC_IPR_RN_I0_RESETVAL (0x00000000U)
11772 #define CSL_EVETPCC_IPR_RN_I0_MAX (0x00000001U)
11774 #define CSL_EVETPCC_IPR_RN_I12_MASK (0x00001000U)
11775 #define CSL_EVETPCC_IPR_RN_I12_SHIFT (12U)
11776 #define CSL_EVETPCC_IPR_RN_I12_RESETVAL (0x00000000U)
11777 #define CSL_EVETPCC_IPR_RN_I12_MAX (0x00000001U)
11779 #define CSL_EVETPCC_IPR_RN_I29_MASK (0x20000000U)
11780 #define CSL_EVETPCC_IPR_RN_I29_SHIFT (29U)
11781 #define CSL_EVETPCC_IPR_RN_I29_RESETVAL (0x00000000U)
11782 #define CSL_EVETPCC_IPR_RN_I29_MAX (0x00000001U)
11784 #define CSL_EVETPCC_IPR_RN_I6_MASK (0x00000040U)
11785 #define CSL_EVETPCC_IPR_RN_I6_SHIFT (6U)
11786 #define CSL_EVETPCC_IPR_RN_I6_RESETVAL (0x00000000U)
11787 #define CSL_EVETPCC_IPR_RN_I6_MAX (0x00000001U)
11789 #define CSL_EVETPCC_IPR_RN_I26_MASK (0x04000000U)
11790 #define CSL_EVETPCC_IPR_RN_I26_SHIFT (26U)
11791 #define CSL_EVETPCC_IPR_RN_I26_RESETVAL (0x00000000U)
11792 #define CSL_EVETPCC_IPR_RN_I26_MAX (0x00000001U)
11794 #define CSL_EVETPCC_IPR_RN_I5_MASK (0x00000020U)
11795 #define CSL_EVETPCC_IPR_RN_I5_SHIFT (5U)
11796 #define CSL_EVETPCC_IPR_RN_I5_RESETVAL (0x00000000U)
11797 #define CSL_EVETPCC_IPR_RN_I5_MAX (0x00000001U)
11799 #define CSL_EVETPCC_IPR_RN_I4_MASK (0x00000010U)
11800 #define CSL_EVETPCC_IPR_RN_I4_SHIFT (4U)
11801 #define CSL_EVETPCC_IPR_RN_I4_RESETVAL (0x00000000U)
11802 #define CSL_EVETPCC_IPR_RN_I4_MAX (0x00000001U)
11804 #define CSL_EVETPCC_IPR_RN_I16_MASK (0x00010000U)
11805 #define CSL_EVETPCC_IPR_RN_I16_SHIFT (16U)
11806 #define CSL_EVETPCC_IPR_RN_I16_RESETVAL (0x00000000U)
11807 #define CSL_EVETPCC_IPR_RN_I16_MAX (0x00000001U)
11809 #define CSL_EVETPCC_IPR_RN_I23_MASK (0x00800000U)
11810 #define CSL_EVETPCC_IPR_RN_I23_SHIFT (23U)
11811 #define CSL_EVETPCC_IPR_RN_I23_RESETVAL (0x00000000U)
11812 #define CSL_EVETPCC_IPR_RN_I23_MAX (0x00000001U)
11814 #define CSL_EVETPCC_IPR_RN_I7_MASK (0x00000080U)
11815 #define CSL_EVETPCC_IPR_RN_I7_SHIFT (7U)
11816 #define CSL_EVETPCC_IPR_RN_I7_RESETVAL (0x00000000U)
11817 #define CSL_EVETPCC_IPR_RN_I7_MAX (0x00000001U)
11819 #define CSL_EVETPCC_IPR_RN_I22_MASK (0x00400000U)
11820 #define CSL_EVETPCC_IPR_RN_I22_SHIFT (22U)
11821 #define CSL_EVETPCC_IPR_RN_I22_RESETVAL (0x00000000U)
11822 #define CSL_EVETPCC_IPR_RN_I22_MAX (0x00000001U)
11824 #define CSL_EVETPCC_IPR_RN_I25_MASK (0x02000000U)
11825 #define CSL_EVETPCC_IPR_RN_I25_SHIFT (25U)
11826 #define CSL_EVETPCC_IPR_RN_I25_RESETVAL (0x00000000U)
11827 #define CSL_EVETPCC_IPR_RN_I25_MAX (0x00000001U)
11829 #define CSL_EVETPCC_IPR_RN_I24_MASK (0x01000000U)
11830 #define CSL_EVETPCC_IPR_RN_I24_SHIFT (24U)
11831 #define CSL_EVETPCC_IPR_RN_I24_RESETVAL (0x00000000U)
11832 #define CSL_EVETPCC_IPR_RN_I24_MAX (0x00000001U)
11834 #define CSL_EVETPCC_IPR_RN_I19_MASK (0x00080000U)
11835 #define CSL_EVETPCC_IPR_RN_I19_SHIFT (19U)
11836 #define CSL_EVETPCC_IPR_RN_I19_RESETVAL (0x00000000U)
11837 #define CSL_EVETPCC_IPR_RN_I19_MAX (0x00000001U)
11839 #define CSL_EVETPCC_IPR_RN_I30_MASK (0x40000000U)
11840 #define CSL_EVETPCC_IPR_RN_I30_SHIFT (30U)
11841 #define CSL_EVETPCC_IPR_RN_I30_RESETVAL (0x00000000U)
11842 #define CSL_EVETPCC_IPR_RN_I30_MAX (0x00000001U)
11844 #define CSL_EVETPCC_IPR_RN_I11_MASK (0x00000800U)
11845 #define CSL_EVETPCC_IPR_RN_I11_SHIFT (11U)
11846 #define CSL_EVETPCC_IPR_RN_I11_RESETVAL (0x00000000U)
11847 #define CSL_EVETPCC_IPR_RN_I11_MAX (0x00000001U)
11849 #define CSL_EVETPCC_IPR_RN_I18_MASK (0x00040000U)
11850 #define CSL_EVETPCC_IPR_RN_I18_SHIFT (18U)
11851 #define CSL_EVETPCC_IPR_RN_I18_RESETVAL (0x00000000U)
11852 #define CSL_EVETPCC_IPR_RN_I18_MAX (0x00000001U)
11854 #define CSL_EVETPCC_IPR_RN_I31_MASK (0x80000000U)
11855 #define CSL_EVETPCC_IPR_RN_I31_SHIFT (31U)
11856 #define CSL_EVETPCC_IPR_RN_I31_RESETVAL (0x00000000U)
11857 #define CSL_EVETPCC_IPR_RN_I31_MAX (0x00000001U)
11859 #define CSL_EVETPCC_IPR_RN_I10_MASK (0x00000400U)
11860 #define CSL_EVETPCC_IPR_RN_I10_SHIFT (10U)
11861 #define CSL_EVETPCC_IPR_RN_I10_RESETVAL (0x00000000U)
11862 #define CSL_EVETPCC_IPR_RN_I10_MAX (0x00000001U)
11864 #define CSL_EVETPCC_IPR_RN_I9_MASK (0x00000200U)
11865 #define CSL_EVETPCC_IPR_RN_I9_SHIFT (9U)
11866 #define CSL_EVETPCC_IPR_RN_I9_RESETVAL (0x00000000U)
11867 #define CSL_EVETPCC_IPR_RN_I9_MAX (0x00000001U)
11869 #define CSL_EVETPCC_IPR_RN_I21_MASK (0x00200000U)
11870 #define CSL_EVETPCC_IPR_RN_I21_SHIFT (21U)
11871 #define CSL_EVETPCC_IPR_RN_I21_RESETVAL (0x00000000U)
11872 #define CSL_EVETPCC_IPR_RN_I21_MAX (0x00000001U)
11874 #define CSL_EVETPCC_IPR_RN_I8_MASK (0x00000100U)
11875 #define CSL_EVETPCC_IPR_RN_I8_SHIFT (8U)
11876 #define CSL_EVETPCC_IPR_RN_I8_RESETVAL (0x00000000U)
11877 #define CSL_EVETPCC_IPR_RN_I8_MAX (0x00000001U)
11879 #define CSL_EVETPCC_IPR_RN_I20_MASK (0x00100000U)
11880 #define CSL_EVETPCC_IPR_RN_I20_SHIFT (20U)
11881 #define CSL_EVETPCC_IPR_RN_I20_RESETVAL (0x00000000U)
11882 #define CSL_EVETPCC_IPR_RN_I20_MAX (0x00000001U)
11884 #define CSL_EVETPCC_IPR_RN_RESETVAL (0x00000000U)
11886 /* ESRH_RN */
11888 #define CSL_EVETPCC_ESRH_RN_E41_MASK (0x00000200U)
11889 #define CSL_EVETPCC_ESRH_RN_E41_SHIFT (9U)
11890 #define CSL_EVETPCC_ESRH_RN_E41_RESETVAL (0x00000000U)
11891 #define CSL_EVETPCC_ESRH_RN_E41_MAX (0x00000001U)
11893 #define CSL_EVETPCC_ESRH_RN_E57_MASK (0x02000000U)
11894 #define CSL_EVETPCC_ESRH_RN_E57_SHIFT (25U)
11895 #define CSL_EVETPCC_ESRH_RN_E57_RESETVAL (0x00000000U)
11896 #define CSL_EVETPCC_ESRH_RN_E57_MAX (0x00000001U)
11898 #define CSL_EVETPCC_ESRH_RN_E46_MASK (0x00004000U)
11899 #define CSL_EVETPCC_ESRH_RN_E46_SHIFT (14U)
11900 #define CSL_EVETPCC_ESRH_RN_E46_RESETVAL (0x00000000U)
11901 #define CSL_EVETPCC_ESRH_RN_E46_MAX (0x00000001U)
11903 #define CSL_EVETPCC_ESRH_RN_E42_MASK (0x00000400U)
11904 #define CSL_EVETPCC_ESRH_RN_E42_SHIFT (10U)
11905 #define CSL_EVETPCC_ESRH_RN_E42_RESETVAL (0x00000000U)
11906 #define CSL_EVETPCC_ESRH_RN_E42_MAX (0x00000001U)
11908 #define CSL_EVETPCC_ESRH_RN_E56_MASK (0x01000000U)
11909 #define CSL_EVETPCC_ESRH_RN_E56_SHIFT (24U)
11910 #define CSL_EVETPCC_ESRH_RN_E56_RESETVAL (0x00000000U)
11911 #define CSL_EVETPCC_ESRH_RN_E56_MAX (0x00000001U)
11913 #define CSL_EVETPCC_ESRH_RN_E33_MASK (0x00000002U)
11914 #define CSL_EVETPCC_ESRH_RN_E33_SHIFT (1U)
11915 #define CSL_EVETPCC_ESRH_RN_E33_RESETVAL (0x00000000U)
11916 #define CSL_EVETPCC_ESRH_RN_E33_MAX (0x00000001U)
11918 #define CSL_EVETPCC_ESRH_RN_E43_MASK (0x00000800U)
11919 #define CSL_EVETPCC_ESRH_RN_E43_SHIFT (11U)
11920 #define CSL_EVETPCC_ESRH_RN_E43_RESETVAL (0x00000000U)
11921 #define CSL_EVETPCC_ESRH_RN_E43_MAX (0x00000001U)
11923 #define CSL_EVETPCC_ESRH_RN_E55_MASK (0x00800000U)
11924 #define CSL_EVETPCC_ESRH_RN_E55_SHIFT (23U)
11925 #define CSL_EVETPCC_ESRH_RN_E55_RESETVAL (0x00000000U)
11926 #define CSL_EVETPCC_ESRH_RN_E55_MAX (0x00000001U)
11928 #define CSL_EVETPCC_ESRH_RN_E32_MASK (0x00000001U)
11929 #define CSL_EVETPCC_ESRH_RN_E32_SHIFT (0U)
11930 #define CSL_EVETPCC_ESRH_RN_E32_RESETVAL (0x00000000U)
11931 #define CSL_EVETPCC_ESRH_RN_E32_MAX (0x00000001U)
11933 #define CSL_EVETPCC_ESRH_RN_E48_MASK (0x00010000U)
11934 #define CSL_EVETPCC_ESRH_RN_E48_SHIFT (16U)
11935 #define CSL_EVETPCC_ESRH_RN_E48_RESETVAL (0x00000000U)
11936 #define CSL_EVETPCC_ESRH_RN_E48_MAX (0x00000001U)
11938 #define CSL_EVETPCC_ESRH_RN_E44_MASK (0x00001000U)
11939 #define CSL_EVETPCC_ESRH_RN_E44_SHIFT (12U)
11940 #define CSL_EVETPCC_ESRH_RN_E44_RESETVAL (0x00000000U)
11941 #define CSL_EVETPCC_ESRH_RN_E44_MAX (0x00000001U)
11943 #define CSL_EVETPCC_ESRH_RN_E45_MASK (0x00002000U)
11944 #define CSL_EVETPCC_ESRH_RN_E45_SHIFT (13U)
11945 #define CSL_EVETPCC_ESRH_RN_E45_RESETVAL (0x00000000U)
11946 #define CSL_EVETPCC_ESRH_RN_E45_MAX (0x00000001U)
11948 #define CSL_EVETPCC_ESRH_RN_E49_MASK (0x00020000U)
11949 #define CSL_EVETPCC_ESRH_RN_E49_SHIFT (17U)
11950 #define CSL_EVETPCC_ESRH_RN_E49_RESETVAL (0x00000000U)
11951 #define CSL_EVETPCC_ESRH_RN_E49_MAX (0x00000001U)
11953 #define CSL_EVETPCC_ESRH_RN_E61_MASK (0x20000000U)
11954 #define CSL_EVETPCC_ESRH_RN_E61_SHIFT (29U)
11955 #define CSL_EVETPCC_ESRH_RN_E61_RESETVAL (0x00000000U)
11956 #define CSL_EVETPCC_ESRH_RN_E61_MAX (0x00000001U)
11958 #define CSL_EVETPCC_ESRH_RN_E52_MASK (0x00100000U)
11959 #define CSL_EVETPCC_ESRH_RN_E52_SHIFT (20U)
11960 #define CSL_EVETPCC_ESRH_RN_E52_RESETVAL (0x00000000U)
11961 #define CSL_EVETPCC_ESRH_RN_E52_MAX (0x00000001U)
11963 #define CSL_EVETPCC_ESRH_RN_E63_MASK (0x80000000U)
11964 #define CSL_EVETPCC_ESRH_RN_E63_SHIFT (31U)
11965 #define CSL_EVETPCC_ESRH_RN_E63_RESETVAL (0x00000000U)
11966 #define CSL_EVETPCC_ESRH_RN_E63_MAX (0x00000001U)
11968 #define CSL_EVETPCC_ESRH_RN_E34_MASK (0x00000004U)
11969 #define CSL_EVETPCC_ESRH_RN_E34_SHIFT (2U)
11970 #define CSL_EVETPCC_ESRH_RN_E34_RESETVAL (0x00000000U)
11971 #define CSL_EVETPCC_ESRH_RN_E34_MAX (0x00000001U)
11973 #define CSL_EVETPCC_ESRH_RN_E47_MASK (0x00008000U)
11974 #define CSL_EVETPCC_ESRH_RN_E47_SHIFT (15U)
11975 #define CSL_EVETPCC_ESRH_RN_E47_RESETVAL (0x00000000U)
11976 #define CSL_EVETPCC_ESRH_RN_E47_MAX (0x00000001U)
11978 #define CSL_EVETPCC_ESRH_RN_E60_MASK (0x10000000U)
11979 #define CSL_EVETPCC_ESRH_RN_E60_SHIFT (28U)
11980 #define CSL_EVETPCC_ESRH_RN_E60_RESETVAL (0x00000000U)
11981 #define CSL_EVETPCC_ESRH_RN_E60_MAX (0x00000001U)
11983 #define CSL_EVETPCC_ESRH_RN_E59_MASK (0x08000000U)
11984 #define CSL_EVETPCC_ESRH_RN_E59_SHIFT (27U)
11985 #define CSL_EVETPCC_ESRH_RN_E59_RESETVAL (0x00000000U)
11986 #define CSL_EVETPCC_ESRH_RN_E59_MAX (0x00000001U)
11988 #define CSL_EVETPCC_ESRH_RN_E50_MASK (0x00040000U)
11989 #define CSL_EVETPCC_ESRH_RN_E50_SHIFT (18U)
11990 #define CSL_EVETPCC_ESRH_RN_E50_RESETVAL (0x00000000U)
11991 #define CSL_EVETPCC_ESRH_RN_E50_MAX (0x00000001U)
11993 #define CSL_EVETPCC_ESRH_RN_E58_MASK (0x04000000U)
11994 #define CSL_EVETPCC_ESRH_RN_E58_SHIFT (26U)
11995 #define CSL_EVETPCC_ESRH_RN_E58_RESETVAL (0x00000000U)
11996 #define CSL_EVETPCC_ESRH_RN_E58_MAX (0x00000001U)
11998 #define CSL_EVETPCC_ESRH_RN_E53_MASK (0x00200000U)
11999 #define CSL_EVETPCC_ESRH_RN_E53_SHIFT (21U)
12000 #define CSL_EVETPCC_ESRH_RN_E53_RESETVAL (0x00000000U)
12001 #define CSL_EVETPCC_ESRH_RN_E53_MAX (0x00000001U)
12003 #define CSL_EVETPCC_ESRH_RN_E35_MASK (0x00000008U)
12004 #define CSL_EVETPCC_ESRH_RN_E35_SHIFT (3U)
12005 #define CSL_EVETPCC_ESRH_RN_E35_RESETVAL (0x00000000U)
12006 #define CSL_EVETPCC_ESRH_RN_E35_MAX (0x00000001U)
12008 #define CSL_EVETPCC_ESRH_RN_E51_MASK (0x00080000U)
12009 #define CSL_EVETPCC_ESRH_RN_E51_SHIFT (19U)
12010 #define CSL_EVETPCC_ESRH_RN_E51_RESETVAL (0x00000000U)
12011 #define CSL_EVETPCC_ESRH_RN_E51_MAX (0x00000001U)
12013 #define CSL_EVETPCC_ESRH_RN_E54_MASK (0x00400000U)
12014 #define CSL_EVETPCC_ESRH_RN_E54_SHIFT (22U)
12015 #define CSL_EVETPCC_ESRH_RN_E54_RESETVAL (0x00000000U)
12016 #define CSL_EVETPCC_ESRH_RN_E54_MAX (0x00000001U)
12018 #define CSL_EVETPCC_ESRH_RN_E36_MASK (0x00000010U)
12019 #define CSL_EVETPCC_ESRH_RN_E36_SHIFT (4U)
12020 #define CSL_EVETPCC_ESRH_RN_E36_RESETVAL (0x00000000U)
12021 #define CSL_EVETPCC_ESRH_RN_E36_MAX (0x00000001U)
12023 #define CSL_EVETPCC_ESRH_RN_E62_MASK (0x40000000U)
12024 #define CSL_EVETPCC_ESRH_RN_E62_SHIFT (30U)
12025 #define CSL_EVETPCC_ESRH_RN_E62_RESETVAL (0x00000000U)
12026 #define CSL_EVETPCC_ESRH_RN_E62_MAX (0x00000001U)
12028 #define CSL_EVETPCC_ESRH_RN_E37_MASK (0x00000020U)
12029 #define CSL_EVETPCC_ESRH_RN_E37_SHIFT (5U)
12030 #define CSL_EVETPCC_ESRH_RN_E37_RESETVAL (0x00000000U)
12031 #define CSL_EVETPCC_ESRH_RN_E37_MAX (0x00000001U)
12033 #define CSL_EVETPCC_ESRH_RN_E38_MASK (0x00000040U)
12034 #define CSL_EVETPCC_ESRH_RN_E38_SHIFT (6U)
12035 #define CSL_EVETPCC_ESRH_RN_E38_RESETVAL (0x00000000U)
12036 #define CSL_EVETPCC_ESRH_RN_E38_MAX (0x00000001U)
12038 #define CSL_EVETPCC_ESRH_RN_E39_MASK (0x00000080U)
12039 #define CSL_EVETPCC_ESRH_RN_E39_SHIFT (7U)
12040 #define CSL_EVETPCC_ESRH_RN_E39_RESETVAL (0x00000000U)
12041 #define CSL_EVETPCC_ESRH_RN_E39_MAX (0x00000001U)
12043 #define CSL_EVETPCC_ESRH_RN_E40_MASK (0x00000100U)
12044 #define CSL_EVETPCC_ESRH_RN_E40_SHIFT (8U)
12045 #define CSL_EVETPCC_ESRH_RN_E40_RESETVAL (0x00000000U)
12046 #define CSL_EVETPCC_ESRH_RN_E40_MAX (0x00000001U)
12048 #define CSL_EVETPCC_ESRH_RN_RESETVAL (0x00000000U)
12050 /* QEESR_RN */
12052 #define CSL_EVETPCC_QEESR_RN_E5_MASK (0x00000020U)
12053 #define CSL_EVETPCC_QEESR_RN_E5_SHIFT (5U)
12054 #define CSL_EVETPCC_QEESR_RN_E5_RESETVAL (0x00000000U)
12055 #define CSL_EVETPCC_QEESR_RN_E5_MAX (0x00000001U)
12057 #define CSL_EVETPCC_QEESR_RN_E3_MASK (0x00000008U)
12058 #define CSL_EVETPCC_QEESR_RN_E3_SHIFT (3U)
12059 #define CSL_EVETPCC_QEESR_RN_E3_RESETVAL (0x00000000U)
12060 #define CSL_EVETPCC_QEESR_RN_E3_MAX (0x00000001U)
12062 #define CSL_EVETPCC_QEESR_RN_E6_MASK (0x00000040U)
12063 #define CSL_EVETPCC_QEESR_RN_E6_SHIFT (6U)
12064 #define CSL_EVETPCC_QEESR_RN_E6_RESETVAL (0x00000000U)
12065 #define CSL_EVETPCC_QEESR_RN_E6_MAX (0x00000001U)
12067 #define CSL_EVETPCC_QEESR_RN_E4_MASK (0x00000010U)
12068 #define CSL_EVETPCC_QEESR_RN_E4_SHIFT (4U)
12069 #define CSL_EVETPCC_QEESR_RN_E4_RESETVAL (0x00000000U)
12070 #define CSL_EVETPCC_QEESR_RN_E4_MAX (0x00000001U)
12072 #define CSL_EVETPCC_QEESR_RN_E1_MASK (0x00000002U)
12073 #define CSL_EVETPCC_QEESR_RN_E1_SHIFT (1U)
12074 #define CSL_EVETPCC_QEESR_RN_E1_RESETVAL (0x00000000U)
12075 #define CSL_EVETPCC_QEESR_RN_E1_MAX (0x00000001U)
12077 #define CSL_EVETPCC_QEESR_RN_E2_MASK (0x00000004U)
12078 #define CSL_EVETPCC_QEESR_RN_E2_SHIFT (2U)
12079 #define CSL_EVETPCC_QEESR_RN_E2_RESETVAL (0x00000000U)
12080 #define CSL_EVETPCC_QEESR_RN_E2_MAX (0x00000001U)
12082 #define CSL_EVETPCC_QEESR_RN_E0_MASK (0x00000001U)
12083 #define CSL_EVETPCC_QEESR_RN_E0_SHIFT (0U)
12084 #define CSL_EVETPCC_QEESR_RN_E0_RESETVAL (0x00000000U)
12085 #define CSL_EVETPCC_QEESR_RN_E0_MAX (0x00000001U)
12087 #define CSL_EVETPCC_QEESR_RN_E7_MASK (0x00000080U)
12088 #define CSL_EVETPCC_QEESR_RN_E7_SHIFT (7U)
12089 #define CSL_EVETPCC_QEESR_RN_E7_RESETVAL (0x00000000U)
12090 #define CSL_EVETPCC_QEESR_RN_E7_MAX (0x00000001U)
12092 #define CSL_EVETPCC_QEESR_RN_RESETVAL (0x00000000U)
12094 /* ERH_RN */
12096 #define CSL_EVETPCC_ERH_RN_E61_MASK (0x20000000U)
12097 #define CSL_EVETPCC_ERH_RN_E61_SHIFT (29U)
12098 #define CSL_EVETPCC_ERH_RN_E61_RESETVAL (0x00000000U)
12099 #define CSL_EVETPCC_ERH_RN_E61_MAX (0x00000001U)
12101 #define CSL_EVETPCC_ERH_RN_E54_MASK (0x00400000U)
12102 #define CSL_EVETPCC_ERH_RN_E54_SHIFT (22U)
12103 #define CSL_EVETPCC_ERH_RN_E54_RESETVAL (0x00000000U)
12104 #define CSL_EVETPCC_ERH_RN_E54_MAX (0x00000001U)
12106 #define CSL_EVETPCC_ERH_RN_E55_MASK (0x00800000U)
12107 #define CSL_EVETPCC_ERH_RN_E55_SHIFT (23U)
12108 #define CSL_EVETPCC_ERH_RN_E55_RESETVAL (0x00000000U)
12109 #define CSL_EVETPCC_ERH_RN_E55_MAX (0x00000001U)
12111 #define CSL_EVETPCC_ERH_RN_E59_MASK (0x08000000U)
12112 #define CSL_EVETPCC_ERH_RN_E59_SHIFT (27U)
12113 #define CSL_EVETPCC_ERH_RN_E59_RESETVAL (0x00000000U)
12114 #define CSL_EVETPCC_ERH_RN_E59_MAX (0x00000001U)
12116 #define CSL_EVETPCC_ERH_RN_E50_MASK (0x00040000U)
12117 #define CSL_EVETPCC_ERH_RN_E50_SHIFT (18U)
12118 #define CSL_EVETPCC_ERH_RN_E50_RESETVAL (0x00000000U)
12119 #define CSL_EVETPCC_ERH_RN_E50_MAX (0x00000001U)
12121 #define CSL_EVETPCC_ERH_RN_E52_MASK (0x00100000U)
12122 #define CSL_EVETPCC_ERH_RN_E52_SHIFT (20U)
12123 #define CSL_EVETPCC_ERH_RN_E52_RESETVAL (0x00000000U)
12124 #define CSL_EVETPCC_ERH_RN_E52_MAX (0x00000001U)
12126 #define CSL_EVETPCC_ERH_RN_E53_MASK (0x00200000U)
12127 #define CSL_EVETPCC_ERH_RN_E53_SHIFT (21U)
12128 #define CSL_EVETPCC_ERH_RN_E53_RESETVAL (0x00000000U)
12129 #define CSL_EVETPCC_ERH_RN_E53_MAX (0x00000001U)
12131 #define CSL_EVETPCC_ERH_RN_E51_MASK (0x00080000U)
12132 #define CSL_EVETPCC_ERH_RN_E51_SHIFT (19U)
12133 #define CSL_EVETPCC_ERH_RN_E51_RESETVAL (0x00000000U)
12134 #define CSL_EVETPCC_ERH_RN_E51_MAX (0x00000001U)
12136 #define CSL_EVETPCC_ERH_RN_E36_MASK (0x00000010U)
12137 #define CSL_EVETPCC_ERH_RN_E36_SHIFT (4U)
12138 #define CSL_EVETPCC_ERH_RN_E36_RESETVAL (0x00000000U)
12139 #define CSL_EVETPCC_ERH_RN_E36_MAX (0x00000001U)
12141 #define CSL_EVETPCC_ERH_RN_E40_MASK (0x00000100U)
12142 #define CSL_EVETPCC_ERH_RN_E40_SHIFT (8U)
12143 #define CSL_EVETPCC_ERH_RN_E40_RESETVAL (0x00000000U)
12144 #define CSL_EVETPCC_ERH_RN_E40_MAX (0x00000001U)
12146 #define CSL_EVETPCC_ERH_RN_E39_MASK (0x00000080U)
12147 #define CSL_EVETPCC_ERH_RN_E39_SHIFT (7U)
12148 #define CSL_EVETPCC_ERH_RN_E39_RESETVAL (0x00000000U)
12149 #define CSL_EVETPCC_ERH_RN_E39_MAX (0x00000001U)
12151 #define CSL_EVETPCC_ERH_RN_E38_MASK (0x00000040U)
12152 #define CSL_EVETPCC_ERH_RN_E38_SHIFT (6U)
12153 #define CSL_EVETPCC_ERH_RN_E38_RESETVAL (0x00000000U)
12154 #define CSL_EVETPCC_ERH_RN_E38_MAX (0x00000001U)
12156 #define CSL_EVETPCC_ERH_RN_E42_MASK (0x00000400U)
12157 #define CSL_EVETPCC_ERH_RN_E42_SHIFT (10U)
12158 #define CSL_EVETPCC_ERH_RN_E42_RESETVAL (0x00000000U)
12159 #define CSL_EVETPCC_ERH_RN_E42_MAX (0x00000001U)
12161 #define CSL_EVETPCC_ERH_RN_E49_MASK (0x00020000U)
12162 #define CSL_EVETPCC_ERH_RN_E49_SHIFT (17U)
12163 #define CSL_EVETPCC_ERH_RN_E49_RESETVAL (0x00000000U)
12164 #define CSL_EVETPCC_ERH_RN_E49_MAX (0x00000001U)
12166 #define CSL_EVETPCC_ERH_RN_E41_MASK (0x00000200U)
12167 #define CSL_EVETPCC_ERH_RN_E41_SHIFT (9U)
12168 #define CSL_EVETPCC_ERH_RN_E41_RESETVAL (0x00000000U)
12169 #define CSL_EVETPCC_ERH_RN_E41_MAX (0x00000001U)
12171 #define CSL_EVETPCC_ERH_RN_E32_MASK (0x00000001U)
12172 #define CSL_EVETPCC_ERH_RN_E32_SHIFT (0U)
12173 #define CSL_EVETPCC_ERH_RN_E32_RESETVAL (0x00000000U)
12174 #define CSL_EVETPCC_ERH_RN_E32_MAX (0x00000001U)
12176 #define CSL_EVETPCC_ERH_RN_E35_MASK (0x00000008U)
12177 #define CSL_EVETPCC_ERH_RN_E35_SHIFT (3U)
12178 #define CSL_EVETPCC_ERH_RN_E35_RESETVAL (0x00000000U)
12179 #define CSL_EVETPCC_ERH_RN_E35_MAX (0x00000001U)
12181 #define CSL_EVETPCC_ERH_RN_E43_MASK (0x00000800U)
12182 #define CSL_EVETPCC_ERH_RN_E43_SHIFT (11U)
12183 #define CSL_EVETPCC_ERH_RN_E43_RESETVAL (0x00000000U)
12184 #define CSL_EVETPCC_ERH_RN_E43_MAX (0x00000001U)
12186 #define CSL_EVETPCC_ERH_RN_E34_MASK (0x00000004U)
12187 #define CSL_EVETPCC_ERH_RN_E34_SHIFT (2U)
12188 #define CSL_EVETPCC_ERH_RN_E34_RESETVAL (0x00000000U)
12189 #define CSL_EVETPCC_ERH_RN_E34_MAX (0x00000001U)
12191 #define CSL_EVETPCC_ERH_RN_E44_MASK (0x00001000U)
12192 #define CSL_EVETPCC_ERH_RN_E44_SHIFT (12U)
12193 #define CSL_EVETPCC_ERH_RN_E44_RESETVAL (0x00000000U)
12194 #define CSL_EVETPCC_ERH_RN_E44_MAX (0x00000001U)
12196 #define CSL_EVETPCC_ERH_RN_E37_MASK (0x00000020U)
12197 #define CSL_EVETPCC_ERH_RN_E37_SHIFT (5U)
12198 #define CSL_EVETPCC_ERH_RN_E37_RESETVAL (0x00000000U)
12199 #define CSL_EVETPCC_ERH_RN_E37_MAX (0x00000001U)
12201 #define CSL_EVETPCC_ERH_RN_E45_MASK (0x00002000U)
12202 #define CSL_EVETPCC_ERH_RN_E45_SHIFT (13U)
12203 #define CSL_EVETPCC_ERH_RN_E45_RESETVAL (0x00000000U)
12204 #define CSL_EVETPCC_ERH_RN_E45_MAX (0x00000001U)
12206 #define CSL_EVETPCC_ERH_RN_E58_MASK (0x04000000U)
12207 #define CSL_EVETPCC_ERH_RN_E58_SHIFT (26U)
12208 #define CSL_EVETPCC_ERH_RN_E58_RESETVAL (0x00000000U)
12209 #define CSL_EVETPCC_ERH_RN_E58_MAX (0x00000001U)
12211 #define CSL_EVETPCC_ERH_RN_E62_MASK (0x40000000U)
12212 #define CSL_EVETPCC_ERH_RN_E62_SHIFT (30U)
12213 #define CSL_EVETPCC_ERH_RN_E62_RESETVAL (0x00000000U)
12214 #define CSL_EVETPCC_ERH_RN_E62_MAX (0x00000001U)
12216 #define CSL_EVETPCC_ERH_RN_E46_MASK (0x00004000U)
12217 #define CSL_EVETPCC_ERH_RN_E46_SHIFT (14U)
12218 #define CSL_EVETPCC_ERH_RN_E46_RESETVAL (0x00000000U)
12219 #define CSL_EVETPCC_ERH_RN_E46_MAX (0x00000001U)
12221 #define CSL_EVETPCC_ERH_RN_E57_MASK (0x02000000U)
12222 #define CSL_EVETPCC_ERH_RN_E57_SHIFT (25U)
12223 #define CSL_EVETPCC_ERH_RN_E57_RESETVAL (0x00000000U)
12224 #define CSL_EVETPCC_ERH_RN_E57_MAX (0x00000001U)
12226 #define CSL_EVETPCC_ERH_RN_E63_MASK (0x80000000U)
12227 #define CSL_EVETPCC_ERH_RN_E63_SHIFT (31U)
12228 #define CSL_EVETPCC_ERH_RN_E63_RESETVAL (0x00000000U)
12229 #define CSL_EVETPCC_ERH_RN_E63_MAX (0x00000001U)
12231 #define CSL_EVETPCC_ERH_RN_E47_MASK (0x00008000U)
12232 #define CSL_EVETPCC_ERH_RN_E47_SHIFT (15U)
12233 #define CSL_EVETPCC_ERH_RN_E47_RESETVAL (0x00000000U)
12234 #define CSL_EVETPCC_ERH_RN_E47_MAX (0x00000001U)
12236 #define CSL_EVETPCC_ERH_RN_E56_MASK (0x01000000U)
12237 #define CSL_EVETPCC_ERH_RN_E56_SHIFT (24U)
12238 #define CSL_EVETPCC_ERH_RN_E56_RESETVAL (0x00000000U)
12239 #define CSL_EVETPCC_ERH_RN_E56_MAX (0x00000001U)
12241 #define CSL_EVETPCC_ERH_RN_E48_MASK (0x00010000U)
12242 #define CSL_EVETPCC_ERH_RN_E48_SHIFT (16U)
12243 #define CSL_EVETPCC_ERH_RN_E48_RESETVAL (0x00000000U)
12244 #define CSL_EVETPCC_ERH_RN_E48_MAX (0x00000001U)
12246 #define CSL_EVETPCC_ERH_RN_E33_MASK (0x00000002U)
12247 #define CSL_EVETPCC_ERH_RN_E33_SHIFT (1U)
12248 #define CSL_EVETPCC_ERH_RN_E33_RESETVAL (0x00000000U)
12249 #define CSL_EVETPCC_ERH_RN_E33_MAX (0x00000001U)
12251 #define CSL_EVETPCC_ERH_RN_E60_MASK (0x10000000U)
12252 #define CSL_EVETPCC_ERH_RN_E60_SHIFT (28U)
12253 #define CSL_EVETPCC_ERH_RN_E60_RESETVAL (0x00000000U)
12254 #define CSL_EVETPCC_ERH_RN_E60_MAX (0x00000001U)
12256 #define CSL_EVETPCC_ERH_RN_RESETVAL (0x00000000U)
12258 /* OPT */
12260 #define CSL_EVETPCC_OPT_PRIV_MASK (0x80000000U)
12261 #define CSL_EVETPCC_OPT_PRIV_SHIFT (31U)
12262 #define CSL_EVETPCC_OPT_PRIV_RESETVAL (0x00000000U)
12263 #define CSL_EVETPCC_OPT_PRIV_MAX (0x00000001U)
12265 #define CSL_EVETPCC_OPT_SECURE_MASK (0x40000000U)
12266 #define CSL_EVETPCC_OPT_SECURE_SHIFT (30U)
12267 #define CSL_EVETPCC_OPT_SECURE_RESETVAL (0x00000000U)
12268 #define CSL_EVETPCC_OPT_SECURE_MAX (0x00000001U)
12270 #define CSL_EVETPCC_OPT_PRIVID_MASK (0x0F000000U)
12271 #define CSL_EVETPCC_OPT_PRIVID_SHIFT (24U)
12272 #define CSL_EVETPCC_OPT_PRIVID_RESETVAL (0x00000000U)
12273 #define CSL_EVETPCC_OPT_PRIVID_MAX (0x0000000fU)
12275 #define CSL_EVETPCC_OPT_ITCCHEN_MASK (0x00800000U)
12276 #define CSL_EVETPCC_OPT_ITCCHEN_SHIFT (23U)
12277 #define CSL_EVETPCC_OPT_ITCCHEN_RESETVAL (0x00000000U)
12278 #define CSL_EVETPCC_OPT_ITCCHEN_MAX (0x00000001U)
12280 #define CSL_EVETPCC_OPT_TCCHEN_MASK (0x00400000U)
12281 #define CSL_EVETPCC_OPT_TCCHEN_SHIFT (22U)
12282 #define CSL_EVETPCC_OPT_TCCHEN_RESETVAL (0x00000000U)
12283 #define CSL_EVETPCC_OPT_TCCHEN_MAX (0x00000001U)
12285 #define CSL_EVETPCC_OPT_ITCINTEN_MASK (0x00200000U)
12286 #define CSL_EVETPCC_OPT_ITCINTEN_SHIFT (21U)
12287 #define CSL_EVETPCC_OPT_ITCINTEN_RESETVAL (0x00000000U)
12288 #define CSL_EVETPCC_OPT_ITCINTEN_MAX (0x00000001U)
12290 #define CSL_EVETPCC_OPT_TCINTEN_MASK (0x00100000U)
12291 #define CSL_EVETPCC_OPT_TCINTEN_SHIFT (20U)
12292 #define CSL_EVETPCC_OPT_TCINTEN_RESETVAL (0x00000000U)
12293 #define CSL_EVETPCC_OPT_TCINTEN_MAX (0x00000001U)
12295 #define CSL_EVETPCC_OPT_WIMODE_MASK (0x00080000U)
12296 #define CSL_EVETPCC_OPT_WIMODE_SHIFT (19U)
12297 #define CSL_EVETPCC_OPT_WIMODE_RESETVAL (0x00000000U)
12298 #define CSL_EVETPCC_OPT_WIMODE_MAX (0x00000001U)
12300 #define CSL_EVETPCC_OPT_TCC_MASK (0x0003F000U)
12301 #define CSL_EVETPCC_OPT_TCC_SHIFT (12U)
12302 #define CSL_EVETPCC_OPT_TCC_RESETVAL (0x00000000U)
12303 #define CSL_EVETPCC_OPT_TCC_MAX (0x0000003fU)
12305 #define CSL_EVETPCC_OPT_TCCMODE_MASK (0x00000800U)
12306 #define CSL_EVETPCC_OPT_TCCMODE_SHIFT (11U)
12307 #define CSL_EVETPCC_OPT_TCCMODE_RESETVAL (0x00000000U)
12308 #define CSL_EVETPCC_OPT_TCCMODE_MAX (0x00000001U)
12310 #define CSL_EVETPCC_OPT_FWID_MASK (0x00000700U)
12311 #define CSL_EVETPCC_OPT_FWID_SHIFT (8U)
12312 #define CSL_EVETPCC_OPT_FWID_RESETVAL (0x00000000U)
12313 #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH256BIT (0x00000005U)
12314 #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH128BIT (0x00000004U)
12315 #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH64BIT (0x00000003U)
12316 #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH32BIT (0x00000002U)
12317 #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH16BIT (0x00000001U)
12318 #define CSL_EVETPCC_OPT_FWID_FIFOWIDTH8BIT (0x00000000U)
12320 #define CSL_EVETPCC_OPT_STATIC_MASK (0x00000008U)
12321 #define CSL_EVETPCC_OPT_STATIC_SHIFT (3U)
12322 #define CSL_EVETPCC_OPT_STATIC_RESETVAL (0x00000000U)
12323 #define CSL_EVETPCC_OPT_STATIC_MAX (0x00000001U)
12325 #define CSL_EVETPCC_OPT_SYNCDIM_MASK (0x00000004U)
12326 #define CSL_EVETPCC_OPT_SYNCDIM_SHIFT (2U)
12327 #define CSL_EVETPCC_OPT_SYNCDIM_RESETVAL (0x00000000U)
12328 #define CSL_EVETPCC_OPT_SYNCDIM_MAX (0x00000001U)
12330 #define CSL_EVETPCC_OPT_DAM_MASK (0x00000002U)
12331 #define CSL_EVETPCC_OPT_DAM_SHIFT (1U)
12332 #define CSL_EVETPCC_OPT_DAM_RESETVAL (0x00000000U)
12333 #define CSL_EVETPCC_OPT_DAM_MAX (0x00000001U)
12335 #define CSL_EVETPCC_OPT_SAM_MASK (0x00000001U)
12336 #define CSL_EVETPCC_OPT_SAM_SHIFT (0U)
12337 #define CSL_EVETPCC_OPT_SAM_RESETVAL (0x00000000U)
12338 #define CSL_EVETPCC_OPT_SAM_MAX (0x00000001U)
12340 #define CSL_EVETPCC_OPT_RESETVAL (0x00000000U)
12342 /* SRC */
12344 #define CSL_EVETPCC_SRC_SRC_MASK (0xFFFFFFFFU)
12345 #define CSL_EVETPCC_SRC_SRC_SHIFT (0U)
12346 #define CSL_EVETPCC_SRC_SRC_RESETVAL (0x00000000U)
12347 #define CSL_EVETPCC_SRC_SRC_MAX (0xffffffffU)
12349 #define CSL_EVETPCC_SRC_RESETVAL (0x00000000U)
12351 /* ABCNT */
12353 #define CSL_EVETPCC_ABCNT_ACNT_MASK (0x0000FFFFU)
12354 #define CSL_EVETPCC_ABCNT_ACNT_SHIFT (0U)
12355 #define CSL_EVETPCC_ABCNT_ACNT_RESETVAL (0x00000000U)
12356 #define CSL_EVETPCC_ABCNT_ACNT_MAX (0x0000ffffU)
12358 #define CSL_EVETPCC_ABCNT_BCNT_MASK (0xFFFF0000U)
12359 #define CSL_EVETPCC_ABCNT_BCNT_SHIFT (16U)
12360 #define CSL_EVETPCC_ABCNT_BCNT_RESETVAL (0x00000000U)
12361 #define CSL_EVETPCC_ABCNT_BCNT_MAX (0x0000ffffU)
12363 #define CSL_EVETPCC_ABCNT_RESETVAL (0x00000000U)
12365 /* BIDX */
12367 #define CSL_EVETPCC_BIDX_SBIDX_MASK (0x0000FFFFU)
12368 #define CSL_EVETPCC_BIDX_SBIDX_SHIFT (0U)
12369 #define CSL_EVETPCC_BIDX_SBIDX_RESETVAL (0x00000000U)
12370 #define CSL_EVETPCC_BIDX_SBIDX_MAX (0x0000ffffU)
12372 #define CSL_EVETPCC_BIDX_DBIDX_MASK (0xFFFF0000U)
12373 #define CSL_EVETPCC_BIDX_DBIDX_SHIFT (16U)
12374 #define CSL_EVETPCC_BIDX_DBIDX_RESETVAL (0x00000000U)
12375 #define CSL_EVETPCC_BIDX_DBIDX_MAX (0x0000ffffU)
12377 #define CSL_EVETPCC_BIDX_RESETVAL (0x00000000U)
12379 /* LNK */
12381 #define CSL_EVETPCC_LNK_BCNTRLD_MASK (0xFFFF0000U)
12382 #define CSL_EVETPCC_LNK_BCNTRLD_SHIFT (16U)
12383 #define CSL_EVETPCC_LNK_BCNTRLD_RESETVAL (0x00000000U)
12384 #define CSL_EVETPCC_LNK_BCNTRLD_MAX (0x0000ffffU)
12386 #define CSL_EVETPCC_LNK_LINK_MASK (0x0000FFFFU)
12387 #define CSL_EVETPCC_LNK_LINK_SHIFT (0U)
12388 #define CSL_EVETPCC_LNK_LINK_RESETVAL (0x00000000U)
12389 #define CSL_EVETPCC_LNK_LINK_MAX (0x0000ffffU)
12391 #define CSL_EVETPCC_LNK_RESETVAL (0x00000000U)
12393 /* CIDX */
12395 #define CSL_EVETPCC_CIDX_SCIDX_MASK (0x0000FFFFU)
12396 #define CSL_EVETPCC_CIDX_SCIDX_SHIFT (0U)
12397 #define CSL_EVETPCC_CIDX_SCIDX_RESETVAL (0x00000000U)
12398 #define CSL_EVETPCC_CIDX_SCIDX_MAX (0x0000ffffU)
12400 #define CSL_EVETPCC_CIDX_DCIDX_MASK (0xFFFF0000U)
12401 #define CSL_EVETPCC_CIDX_DCIDX_SHIFT (16U)
12402 #define CSL_EVETPCC_CIDX_DCIDX_RESETVAL (0x00000000U)
12403 #define CSL_EVETPCC_CIDX_DCIDX_MAX (0x0000ffffU)
12405 #define CSL_EVETPCC_CIDX_RESETVAL (0x00000000U)
12407 /* CCNT */
12409 #define CSL_EVETPCC_CCNT_CCNT_MASK (0x0000FFFFU)
12410 #define CSL_EVETPCC_CCNT_CCNT_SHIFT (0U)
12411 #define CSL_EVETPCC_CCNT_CCNT_RESETVAL (0x00000000U)
12412 #define CSL_EVETPCC_CCNT_CCNT_MAX (0x0000ffffU)
12414 #define CSL_EVETPCC_CCNT_RESETVAL (0x00000000U)
12416 /* DST */
12418 #define CSL_EVETPCC_DST_DST_MASK (0xFFFFFFFFU)
12419 #define CSL_EVETPCC_DST_DST_SHIFT (0U)
12420 #define CSL_EVETPCC_DST_DST_RESETVAL (0x00000000U)
12421 #define CSL_EVETPCC_DST_DST_MAX (0xffffffffU)
12423 #define CSL_EVETPCC_DST_RESETVAL (0x00000000U)
12425 #ifdef __cplusplus
12426 }
12427 #endif
12428 #endif