1 /********************************************************************
2 * Copyright (C) 2003-2011 Texas Instruments Incorporated.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33 /*********************************************************************
34 * file: cslr_srio.h
35 *
36 * Brief: This file contains the Register Description for srio
37 *
38 *********************************************************************/
39 #ifndef CSLR_SRIO_H
40 #define CSLR_SRIO_H
42 /* CSL Modification:
43 * The file has been modified from the AUTOGEN file for the following
44 * reasons:-
45 * a) RIO_TLM_SP_BRR_0_CTL,RIO_TLM_SP_BRR_0_PATTERN_MATCH to
46 * RIO_TLM_SP_BRR_3_CTL,RIO_TLM_SP_BRR_3_PATTERN_MATCH
47 * was made into an array of structures.
48 * b) Modified the header file includes to be RTSC compliant
49 * c) Renamed REG_80014B_NODEID to REG_8B_NODEID for backward compatibility
50 */
51 #include <ti/csl/cslr.h>
52 #include <ti/csl/tistdtypes.h>
55 /* Minimum unit = 1 byte */
57 /**************************************************************************\
58 * Register Overlay Structure for block_enable_status
59 \**************************************************************************/
60 typedef struct {
61 volatile Uint32 RIO_BLK_EN;
62 volatile Uint32 RIO_BLK_EN_STAT;
63 } CSL_SrioBlock_enable_statusRegs;
65 /**************************************************************************\
66 * Register Overlay Structure for pf_cntl
67 \**************************************************************************/
68 typedef struct {
69 volatile Uint32 RIO_PF_16B_CNTL;
70 volatile Uint32 RIO_PF_8B_CNTL;
71 } CSL_SrioPf_cntlRegs;
73 /**************************************************************************\
74 * Register Overlay Structure for doorbell_icsr_iccr
75 \**************************************************************************/
76 typedef struct {
77 volatile Uint32 RIO_DOORBELL_ICSR;
78 volatile Uint8 RSVD0[4];
79 volatile Uint32 RIO_DOORBELL_ICCR;
80 volatile Uint8 RSVD3[4];
81 } CSL_SrioDoorbell_icsr_iccrRegs;
83 /**************************************************************************\
84 * Register Overlay Structure for lsu_icsr_iccr
85 \**************************************************************************/
86 typedef struct {
87 volatile Uint32 RIO_LSU_ICSR;
88 volatile Uint8 RSVD0[4];
89 volatile Uint32 RIO_LSU_ICCR;
90 volatile Uint8 RSVD5[4];
91 } CSL_SrioLsu_icsr_iccrRegs;
93 /**************************************************************************\
94 * Register Overlay Structure for doorbell_icrr
95 \**************************************************************************/
96 typedef struct {
97 volatile Uint32 RIO_DOORBELL_ICRR1;
98 volatile Uint32 RIO_DOORBELL_ICRR2;
99 volatile Uint8 RSVD9[4];
100 } CSL_SrioDoorbell_icrrRegs;
102 /**************************************************************************\
103 * Register Overlay Structure for rxu_map
104 \**************************************************************************/
105 typedef struct {
106 volatile Uint32 RIO_RXU_MAP_L;
107 volatile Uint32 RIO_RXU_MAP_H;
108 volatile Uint32 RIO_RXU_MAP_QID;
109 } CSL_SrioRxu_mapRegs;
111 /**************************************************************************\
112 * Register Overlay Structure for rxu_type9_map
113 \**************************************************************************/
114 typedef struct {
115 volatile Uint32 RIO_RXU_TYPE9_MAP0;
116 volatile Uint32 RIO_RXU_TYPE9_MAP1;
117 volatile Uint32 RIO_RXU_TYPE9_MAP2;
118 } CSL_SrioRxu_type9_mapRegs;
120 /**************************************************************************\
121 * Register Overlay Structure for amu_window
122 \**************************************************************************/
123 typedef struct {
124 volatile Uint32 RIO_AMU_WINDOW_REG0;
125 volatile Uint32 RIO_AMU_WINDOW_REG1;
126 volatile Uint32 RIO_AMU_WINDOW_REG2;
127 } CSL_SrioAmu_windowRegs;
129 /**************************************************************************\
130 * Register Overlay Structure for lsu_cmd
131 \**************************************************************************/
132 typedef struct {
133 volatile Uint32 RIO_LSU_REG0;
134 volatile Uint32 RIO_LSU_REG1;
135 volatile Uint32 RIO_LSU_REG2;
136 volatile Uint32 RIO_LSU_REG3;
137 volatile Uint32 RIO_LSU_REG4;
138 volatile Uint32 RIO_LSU_REG5;
139 volatile Uint32 RIO_LSU_REG6;
140 } CSL_SrioLsu_cmdRegs;
142 /**************************************************************************\
143 * Register Overlay Structure for tx_channel_global_config
144 \**************************************************************************/
145 typedef struct {
146 volatile Uint32 TX_CHANNEL_GLOBAL_CONFIG_REG_A;
147 volatile Uint32 TX_CHANNEL_GLOBAL_CONFIG_REG_B;
148 volatile Uint8 RSVD19[24];
149 } CSL_SrioTx_channel_global_configRegs;
151 /**************************************************************************\
152 * Register Overlay Structure for rx_channel_global_config
153 \**************************************************************************/
154 typedef struct {
155 volatile Uint32 RX_CHANNEL_GLOBAL_CONFIG_REG;
156 volatile Uint8 RSVD21[28];
157 } CSL_SrioRx_channel_global_configRegs;
159 /**************************************************************************\
160 * Register Overlay Structure for rx_flow_config
161 \**************************************************************************/
162 typedef struct {
163 volatile Uint32 RX_FLOW_CONFIG_REG_A;
164 volatile Uint32 RX_FLOW_CONFIG_REG_B;
165 volatile Uint32 RX_FLOW_CONFIG_REG_C;
166 volatile Uint32 RX_FLOW_CONFIG_REG_D;
167 volatile Uint32 RX_FLOW_CONFIG_REG_E;
168 volatile Uint32 RX_FLOW_CONFIG_REG_F;
169 volatile Uint32 RX_FLOW_CONFIG_REG_G;
170 volatile Uint32 RX_FLOW_CONFIG_REG_H;
171 } CSL_SrioRx_flow_configRegs;
173 /**************************************************************************\
174 * Register Overlay Structure for rio_sp
175 \**************************************************************************/
176 typedef struct {
177 volatile Uint32 RIO_SP_LM_REQ;
178 volatile Uint32 RIO_SP_LM_RESP;
179 volatile Uint32 RIO_SP_ACKID_STAT;
180 volatile Uint8 RSVD0[8];
181 volatile Uint32 RIO_SP_CTL2;
182 volatile Uint32 RIO_SP_ERR_STAT;
183 volatile Uint32 RIO_SP_CTL;
184 } CSL_SrioRio_spRegs;
186 /**************************************************************************\
187 * Register Overlay Structure for rio_sp_err
188 \**************************************************************************/
189 typedef struct {
190 volatile Uint32 RIO_SP_ERR_DET;
191 volatile Uint32 RIO_SP_RATE_EN;
192 volatile Uint32 RIO_SP_ERR_ATTR_CAPT;
193 volatile Uint32 RIO_SP_ERR_CAPT_0;
194 volatile Uint32 RIO_SP_ERR_CAPT_1;
195 volatile Uint32 RIO_SP_ERR_CAPT_2;
196 volatile Uint32 RIO_SP_ERR_CAPT_3;
197 volatile Uint8 RSVD0[12];
198 volatile Uint32 RIO_SP_ERR_RATE;
199 volatile Uint32 RIO_SP_ERR_THRESH;
200 volatile Uint8 RSVD36[16];
201 } CSL_SrioRio_sp_errRegs;
203 /**************************************************************************\
204 * Register Overlay Structure for rio_lane
205 \**************************************************************************/
206 typedef struct {
207 volatile Uint32 RIO_LANE_STAT0;
208 volatile Uint32 RIO_LANE_STAT1;
209 volatile Uint8 RSVD39[24];
210 } CSL_SrioRio_laneRegs;
212 /**************************************************************************\
213 * Register Overlay Structure for rio_plm
214 \**************************************************************************/
215 typedef struct {
216 volatile Uint32 RIO_PLM_SP_IMP_SPEC_CTL;
217 volatile Uint32 RIO_PLM_SP_PWDN_CTL;
218 volatile Uint8 RSVD0[8];
219 volatile Uint32 RIO_PLM_SP_STATUS;
220 volatile Uint32 RIO_PLM_SP_INT_ENABLE;
221 volatile Uint32 RIO_PLM_SP_PW_ENABLE;
222 volatile Uint32 RIO_PLM_SP_EVENT_GEN;
223 volatile Uint32 RIO_PLM_SP_ALL_INT_EN;
224 volatile Uint32 RIO_PLM_SP_ALL_PW_EN;
225 volatile Uint8 RSVD1[8];
226 volatile Uint32 RIO_PLM_SP_PATH_CTL;
227 volatile Uint32 RIO_PLM_SP_DISCOVERY_TIMER;
228 volatile Uint32 RIO_PLM_SP_SILENCE_TIMER;
229 volatile Uint32 RIO_PLM_SP_VMIN_EXP;
230 volatile Uint32 RIO_PLM_SP_POL_CTL;
231 volatile Uint8 RSVD2[4];
232 volatile Uint32 RIO_PLM_SP_DENIAL_CTL;
233 volatile Uint8 RSVD3[4];
234 volatile Uint32 RIO_PLM_SP_RCVD_MECS;
235 volatile Uint8 RSVD4[4];
236 volatile Uint32 RIO_PLM_SP_MECS_FWD;
237 volatile Uint8 RSVD5[4];
238 volatile Uint32 RIO_PLM_SP_LONG_CS_TX1;
239 volatile Uint32 RIO_PLM_SP_LONG_CS_TX2;
240 volatile Uint8 RSVD42[24];
241 } CSL_SrioRio_plmRegs;
243 #ifndef CSL_MODIFICATION
245 typedef struct {
246 volatile Uint32 RIO_TLM_SP_BRR_CTL;
247 volatile Uint32 RIO_TLM_SP_BRR_PATTERN_MATCH;
248 volatile Uint8 RSVD1[8];
249 }CSL_SrioRio_BRRConfig;
251 #endif
252 /**************************************************************************\
253 * Register Overlay Structure for rio_tlm
254 \**************************************************************************/
255 typedef struct {
256 volatile Uint32 RIO_TLM_SP_CONTROL;
257 volatile Uint8 RSVD0[12];
258 volatile Uint32 RIO_TLM_SP_STATUS;
259 volatile Uint32 RIO_TLM_SP_INT_ENABLE;
260 volatile Uint32 RIO_TLM_SP_PW_ENABLE;
261 volatile Uint32 RIO_TLM_SP_EVENT_GEN;
262 #ifdef CSL_MODIFICATION
263 volatile Uint32 RIO_TLM_SP_BRR_0_CTL;
264 volatile Uint32 RIO_TLM_SP_BRR_0_PATTERN_MATCH;
265 volatile Uint8 RSVD1[8];
266 volatile Uint32 RIO_TLM_SP_BRR_1_CTL;
267 volatile Uint32 RIO_TLM_SP_BRR_1_PATTERN_MATCH;
268 volatile Uint8 RSVD2[8];
269 volatile Uint32 RIO_TLM_SP_BRR_2_CTL;
270 volatile Uint32 RIO_TLM_SP_BRR_2_PATTERN_MATCH;
271 volatile Uint8 RSVD3[8];
272 volatile Uint32 RIO_TLM_SP_BRR_3_CTL;
273 volatile Uint32 RIO_TLM_SP_BRR_3_PATTERN_MATCH;
274 volatile Uint8 RSVD45[40];
275 #else
276 CSL_SrioRio_BRRConfig brr[4];
277 volatile Uint8 RSVD45[32];
278 #endif
279 } CSL_SrioRio_tlmRegs;
281 /**************************************************************************\
282 * Register Overlay Structure for rio_pbm
283 \**************************************************************************/
284 typedef struct {
285 volatile Uint32 RIO_PBM_SP_CONTROL;
286 volatile Uint8 RSVD0[12];
287 volatile Uint32 RIO_PBM_SP_STATUS;
288 volatile Uint32 RIO_PBM_SP_INT_ENABLE;
289 volatile Uint32 RIO_PBM_SP_PW_ENABLE;
290 volatile Uint32 RIO_PBM_SP_EVENT_GEN;
291 volatile Uint32 RIO_PBM_SP_IG_RESOURCES;
292 volatile Uint32 RIO_PBM_SP_EG_RESOURCES;
293 volatile Uint8 RSVD1[8];
294 volatile Uint32 RIO_PBM_SP_IG_WATERMARK0;
295 volatile Uint32 RIO_PBM_SP_IG_WATERMARK1;
296 volatile Uint32 RIO_PBM_SP_IG_WATERMARK2;
297 volatile Uint32 RIO_PBM_SP_IG_WATERMARK3;
298 volatile Uint8 RSVD48[64];
299 } CSL_SrioRio_pbmRegs;
301 /**************************************************************************\
302 * Register Overlay Structure
303 \**************************************************************************/
304 typedef struct {
305 volatile Uint32 RIO_PID;
306 volatile Uint32 RIO_PCR;
307 volatile Uint8 RSVD0[12];
308 volatile Uint32 RIO_PER_SET_CNTL;
309 volatile Uint32 RIO_PER_SET_CNTL1;
310 volatile Uint8 RSVD1[8];
311 volatile Uint32 RIO_GBL_EN;
312 volatile Uint32 RIO_GBL_EN_STAT;
313 CSL_SrioBlock_enable_statusRegs BLOCK_ENABLE_STATUS[10];
314 volatile Uint8 RSVD2[68];
315 volatile Uint32 RIO_MULTIID_REG[8];
316 CSL_SrioPf_cntlRegs PF_CNTL[8];
317 volatile Uint8 RSVD4[96];
318 CSL_SrioDoorbell_icsr_iccrRegs DOORBELL_ICSR_ICCR[4];
319 CSL_SrioLsu_icsr_iccrRegs LSU_ICSR_ICCR[2];
320 volatile Uint32 RIO_ERR_RST_EVNT_ICSR;
321 volatile Uint8 RSVD6[4];
322 volatile Uint32 RIO_ERR_RST_EVNT_ICCR;
323 volatile Uint8 RSVD7[4];
324 volatile Uint32 RIO_AMU_ICSR;
325 volatile Uint8 RSVD8[4];
326 volatile Uint32 RIO_AMU_ICCR;
327 volatile Uint8 RSVD10[4];
328 CSL_SrioDoorbell_icrrRegs DOORBELL_ICRR[4];
329 volatile Uint32 RIO_LSU0_MODULE_ICRR[4];
330 volatile Uint32 RIO_LSU1_MODULE_ICRR;
331 volatile Uint8 RSVD11[12];
332 volatile Uint32 RIO_ERR_RST_EVNT_ICRR;
333 volatile Uint32 RIO_ERR_RST_EVNT_ICRR2;
334 volatile Uint32 RIO_ERR_RST_EVNT_ICRR3;
335 volatile Uint32 RIO_AMU_ICRR1;
336 volatile Uint32 RIO_AMU_ICRR2;
337 volatile Uint32 RIO_INTERRUPT_CTL;
338 volatile Uint8 RSVD12[8];
339 volatile Uint32 RIO_INTDST_DECODE[24];
340 volatile Uint32 RIO_INTDST_RATE_CNT[16];
341 volatile Uint32 RIO_INTDST_RATE_DIS;
342 volatile Uint8 RSVD13[236];
343 CSL_SrioRxu_mapRegs RXU_MAP[64];
344 CSL_SrioRxu_type9_mapRegs RXU_TYPE9_MAP[64];
345 volatile Uint32 RIO_AMU_SRCID_MAP[4];
346 volatile Uint8 RSVD14[4];
347 CSL_SrioAmu_windowRegs AMU_WINDOW[16];
348 volatile Uint32 RIO_AMU_PRIORITY_MAP;
349 volatile Uint32 RIO_AMU_CAPT0_MAP;
350 volatile Uint32 RIO_AMU_CAPT1_MAP;
351 volatile Uint32 RIO_AMU_WINDOW_PANE[128];
352 volatile Uint32 RIO_AMU_FLOW_MASKS0;
353 volatile Uint8 RSVD15[28];
354 CSL_SrioLsu_cmdRegs LSU_CMD[8];
355 volatile Uint32 RIO_LSU_SETUP_REG0;
356 volatile Uint32 RIO_LSU_SETUP_REG1;
357 volatile Uint32 LSU_STAT_REG[6];
358 volatile Uint32 RIO_LSU_FLOW_MASKS[4];
359 volatile Uint8 RSVD16[60];
360 volatile Uint32 RIO_SUPERVISOR_ID;
361 volatile Uint32 RIO_FLOW_CNTL[16];
362 volatile Uint8 RSVD17[32];
363 volatile Uint32 RIO_TX_CPPI_FLOW_MASKS[8];
364 volatile Uint32 RIO_TX_QUEUE_SCH_INFO[4];
365 volatile Uint32 RIO_GARBAGE_COLL_QID0;
366 volatile Uint32 RIO_GARBAGE_COLL_QID1;
367 volatile Uint32 RIO_GARBAGE_COLL_QID2;
368 volatile Uint8 RSVD18[276];
369 volatile Uint32 REVISION_REG;
370 volatile Uint32 PERF_CONTROL_REG;
371 volatile Uint32 EMULATION_CONTROL_REG;
372 volatile Uint32 PRIORITY_CONTROL_REG;
373 volatile Uint32 QM_BASE_ADDRESS_REG[4];
374 volatile Uint8 RSVD20[992];
375 CSL_SrioTx_channel_global_configRegs TX_CHANNEL_GLOBAL_CONFIG[16];
376 volatile Uint8 RSVD22[512];
377 CSL_SrioRx_channel_global_configRegs RX_CHANNEL_GLOBAL_CONFIG[16];
378 volatile Uint8 RSVD23[512];
379 volatile Uint32 TX_CHANNEL_SCHEDULER_CONFIG_REG[16];
380 volatile Uint8 RSVD24[960];
381 CSL_SrioRx_flow_configRegs RX_FLOW_CONFIG[20];
382 volatile Uint8 RSVD25[36224];
383 volatile Uint32 RIO_DEV_ID;
384 volatile Uint32 RIO_DEV_INFO;
385 volatile Uint32 RIO_ASBLY_ID;
386 volatile Uint32 RIO_ASBLY_INFO;
387 volatile Uint32 RIO_PE_FEAT;
388 volatile Uint32 RIO_SW_PORT;
389 volatile Uint32 RIO_SRC_OP;
390 volatile Uint32 RIO_DEST_OP;
391 volatile Uint8 RSVD26[28];
392 volatile Uint32 RIO_DS_INFO;
393 volatile Uint8 RSVD27[8];
394 volatile Uint32 RIO_DS_LL_CTL;
395 volatile Uint32 RIO_PE_LL_CTL;
396 volatile Uint8 RSVD28[8];
397 volatile Uint32 RIO_LCL_CFG_HBAR;
398 volatile Uint32 RIO_LCL_CFG_BAR;
399 volatile Uint32 RIO_BASE_ID;
400 volatile Uint8 RSVD29[4];
401 volatile Uint32 RIO_HOST_BASE_ID_LOCK;
402 volatile Uint32 RIO_COMP_TAG;
403 volatile Uint8 RSVD30[144];
404 volatile Uint32 RIO_SP_MB_HEAD;
405 volatile Uint8 RSVD31[28];
406 volatile Uint32 RIO_SP_LT_CTL;
407 volatile Uint32 RIO_SP_RT_CTL;
408 volatile Uint8 RSVD32[20];
409 volatile Uint32 RIO_SP_GEN_CTL;
410 CSL_SrioRio_spRegs RIO_SP[4];
411 volatile Uint8 RSVD33[3648];
412 volatile Uint32 RIO_ERR_RPT_BH;
413 volatile Uint8 RSVD34[4];
414 volatile Uint32 RIO_ERR_DET;
415 volatile Uint32 RIO_ERR_EN;
416 volatile Uint32 RIO_H_ADDR_CAPT;
417 volatile Uint32 RIO_ADDR_CAPT;
418 volatile Uint32 RIO_ID_CAPT;
419 volatile Uint32 RIO_CTRL_CAPT;
420 volatile Uint8 RSVD35[8];
421 volatile Uint32 RIO_PW_TGT_ID;
422 volatile Uint8 RSVD37[20];
423 CSL_SrioRio_sp_errRegs RIO_SP_ERR[4];
424 volatile Uint8 RSVD38[7872];
425 volatile Uint32 RIO_PER_LANE_BH;
426 volatile Uint8 RSVD40[12];
427 CSL_SrioRio_laneRegs RIO_LANE[4];
428 volatile Uint8 RSVD41[53104];
429 volatile Uint32 RIO_PLM_BH;
430 volatile Uint8 RSVD43[124];
431 CSL_SrioRio_plmRegs RIO_PLM[4];
432 volatile Uint8 RSVD44[128];
433 volatile Uint32 RIO_TLM_BH;
434 volatile Uint8 RSVD46[124];
435 CSL_SrioRio_tlmRegs RIO_TLM[4];
436 volatile Uint8 RSVD47[128];
437 volatile Uint32 RIO_PBM_BH;
438 volatile Uint8 RSVD49[124];
439 CSL_SrioRio_pbmRegs RIO_PBM[4];
440 volatile Uint8 RSVD50[128];
441 volatile Uint32 RIO_EM_BH;
442 volatile Uint8 RSVD51[12];
443 volatile Uint32 RIO_EM_INT_STAT;
444 volatile Uint32 RIO_EM_INT_ENABLE;
445 volatile Uint32 RIO_EM_INT_PORT_STAT;
446 volatile Uint8 RSVD52[4];
447 volatile Uint32 RIO_EM_PW_STAT;
448 volatile Uint32 RIO_EM_PW_EN;
449 volatile Uint32 RIO_EM_PW_PORT_STAT;
450 volatile Uint8 RSVD53[4];
451 volatile Uint32 RIO_EM_DEV_INT_EN;
452 volatile Uint32 RIO_EM_DEV_PW_EN;
453 volatile Uint8 RSVD54[4];
454 volatile Uint32 RIO_EM_MECS_STAT;
455 volatile Uint32 RIO_EM_MECS_INT_EN;
456 volatile Uint32 RIO_EM_MECS_CAP_EN;
457 volatile Uint32 RIO_EM_MECS_TRIG_EN;
458 volatile Uint32 RIO_EM_MECS_REQ;
459 volatile Uint32 RIO_EM_MECS_PORT_STAT;
460 volatile Uint8 RSVD55[8];
461 volatile Uint32 RIO_EM_MECS_EVENT_GEN;
462 volatile Uint32 RIO_EM_RST_PORT_STAT;
463 volatile Uint8 RSVD56[4];
464 volatile Uint32 RIO_EM_RST_INT_EN;
465 volatile Uint8 RSVD57[4];
466 volatile Uint32 RIO_EM_RST_PW_EN;
467 volatile Uint8 RSVD58[140];
468 volatile Uint32 RIO_PW_BH;
469 volatile Uint32 RIO_PW_CTL;
470 volatile Uint32 RIO_PW_ROUTE;
471 volatile Uint8 RSVD59[4];
472 volatile Uint32 RIO_PW_RX_STAT;
473 volatile Uint32 RIO_PW_RX_EVENT_GEN;
474 volatile Uint8 RSVD60[8];
475 volatile Uint32 RIO_PW_RX_CAPT[4];
476 volatile Uint8 RSVD61[720];
477 volatile Uint32 RIO_LLM_BH;
478 volatile Uint8 RSVD62[32];
479 volatile Uint32 RIO_WHITEBOARD;
480 volatile Uint32 RIO_PORT_NUMBER;
481 volatile Uint8 RSVD63[4];
482 volatile Uint32 RIO_PRESCALAR_SRV_CLK;
483 volatile Uint32 RIO_REG_RST_CTL;
484 volatile Uint8 RSVD64[16];
485 volatile Uint32 RIO_LOCAL_ERR_DET;
486 volatile Uint32 RIO_LOCAL_ERR_EN;
487 volatile Uint32 RIO_LOCAL_H_ADDR_CAPT;
488 volatile Uint32 RIO_LOCAL_ADDR_CAPT;
489 volatile Uint32 RIO_LOCAL_ID_CAPT;
490 volatile Uint32 RIO_LOCAL_CTRL_CAPT;
491 volatile Uint8 RSVD65[160];
492 volatile Uint32 RIO_FABRIC_BH;
493 volatile Uint8 RSVD66[12];
494 volatile Uint32 RIO_FABRIC_CSR;
495 volatile Uint8 RSVD67[44];
496 volatile Uint32 RIO_SP_FABRIC_STATUS[4];
497 } CSL_SrioRegs;
499 /**************************************************************************\
500 * Field Definition Macros
501 \**************************************************************************/
503 /* rio_blk_en */
505 #define CSL_SRIO_RIO_BLK_EN_EN_MASK (0x00000001u)
506 #define CSL_SRIO_RIO_BLK_EN_EN_SHIFT (0x00000000u)
507 #define CSL_SRIO_RIO_BLK_EN_EN_RESETVAL (0x00000001u)
509 #define CSL_SRIO_RIO_BLK_EN_RESETVAL (0x00000001u)
511 /* rio_blk_en_stat */
513 #define CSL_SRIO_RIO_BLK_EN_STAT_EN_STATUS_MASK (0x00000001u)
514 #define CSL_SRIO_RIO_BLK_EN_STAT_EN_STATUS_SHIFT (0x00000000u)
515 #define CSL_SRIO_RIO_BLK_EN_STAT_EN_STATUS_RESETVAL (0x00000001u)
517 #define CSL_SRIO_RIO_BLK_EN_STAT_RESETVAL (0x00000001u)
519 /* rio_pf_16b_cntl */
521 #define CSL_SRIO_RIO_PF_16B_CNTL_DEVID_16B_LO_MASK (0x0000FFFFu)
522 #define CSL_SRIO_RIO_PF_16B_CNTL_DEVID_16B_LO_SHIFT (0x00000000u)
523 #define CSL_SRIO_RIO_PF_16B_CNTL_DEVID_16B_LO_RESETVAL (0x0000FFFFu)
525 #define CSL_SRIO_RIO_PF_16B_CNTL_DEVID_16B_UP_MASK (0xFFFF0000u)
526 #define CSL_SRIO_RIO_PF_16B_CNTL_DEVID_16B_UP_SHIFT (0x00000010u)
527 #define CSL_SRIO_RIO_PF_16B_CNTL_DEVID_16B_UP_RESETVAL (0x0000FFFFu)
529 #define CSL_SRIO_RIO_PF_16B_CNTL_RESETVAL (0xFFFFFFFFu)
531 /* rio_pf_8b_cntl */
533 #define CSL_SRIO_RIO_PF_8B_CNTL_DEVID_8B_LO_MASK (0x000000FFu)
534 #define CSL_SRIO_RIO_PF_8B_CNTL_DEVID_8B_LO_SHIFT (0x00000000u)
535 #define CSL_SRIO_RIO_PF_8B_CNTL_DEVID_8B_LO_RESETVAL (0x000000FFu)
537 #define CSL_SRIO_RIO_PF_8B_CNTL_DEVID_8B_UP_MASK (0x0000FF00u)
538 #define CSL_SRIO_RIO_PF_8B_CNTL_DEVID_8B_UP_SHIFT (0x00000008u)
539 #define CSL_SRIO_RIO_PF_8B_CNTL_DEVID_8B_UP_RESETVAL (0x000000FFu)
541 #define CSL_SRIO_RIO_PF_8B_CNTL_OUT_PORT_MASK (0x00030000u)
542 #define CSL_SRIO_RIO_PF_8B_CNTL_OUT_PORT_SHIFT (0x00000010u)
543 #define CSL_SRIO_RIO_PF_8B_CNTL_OUT_PORT_RESETVAL (0x00000003u)
545 #define CSL_SRIO_RIO_PF_8B_CNTL_RESETVAL (0x0003FFFFu)
547 /* rio_doorbell_icsr */
549 #define CSL_SRIO_RIO_DOORBELL_ICSR_RIO_DOORBELL_MASK (0x0000FFFFu)
550 #define CSL_SRIO_RIO_DOORBELL_ICSR_RIO_DOORBELL_SHIFT (0x00000000u)
551 #define CSL_SRIO_RIO_DOORBELL_ICSR_RIO_DOORBELL_RESETVAL (0x00000000u)
553 #define CSL_SRIO_RIO_DOORBELL_ICSR_RESETVAL (0x00000000u)
555 /* rio_doorbell_iccr */
557 #define CSL_SRIO_RIO_DOORBELL_ICCR_RIO_DOORBELL_MASK (0x0000FFFFu)
558 #define CSL_SRIO_RIO_DOORBELL_ICCR_RIO_DOORBELL_SHIFT (0x00000000u)
559 #define CSL_SRIO_RIO_DOORBELL_ICCR_RIO_DOORBELL_RESETVAL (0x00000000u)
561 #define CSL_SRIO_RIO_DOORBELL_ICCR_RESETVAL (0x00000000u)
563 /* rio_lsu_icsr */
565 #define CSL_SRIO_RIO_LSU_ICSR_RIO_LSU_ICSR_MASK (0xFFFFFFFFu)
566 #define CSL_SRIO_RIO_LSU_ICSR_RIO_LSU_ICSR_SHIFT (0x00000000u)
567 #define CSL_SRIO_RIO_LSU_ICSR_RIO_LSU_ICSR_RESETVAL (0x00000000u)
569 #define CSL_SRIO_RIO_LSU_ICSR_RESETVAL (0x00000000u)
571 /* rio_lsu_iccr */
573 #define CSL_SRIO_RIO_LSU_ICCR_RIO_LSU_ICCR_MASK (0xFFFFFFFFu)
574 #define CSL_SRIO_RIO_LSU_ICCR_RIO_LSU_ICCR_SHIFT (0x00000000u)
575 #define CSL_SRIO_RIO_LSU_ICCR_RIO_LSU_ICCR_RESETVAL (0x00000000u)
577 #define CSL_SRIO_RIO_LSU_ICCR_RESETVAL (0x00000000u)
579 /* rio_doorbell_icrr1 */
581 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR0_MASK (0x0000000Fu)
582 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR0_SHIFT (0x00000000u)
583 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR0_RESETVAL (0x00000000u)
585 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR1_MASK (0x000000F0u)
586 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR1_SHIFT (0x00000004u)
587 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR1_RESETVAL (0x00000000u)
589 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR2_MASK (0x00000F00u)
590 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR2_SHIFT (0x00000008u)
591 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR2_RESETVAL (0x00000000u)
593 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR3_MASK (0x0000F000u)
594 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR3_SHIFT (0x0000000Cu)
595 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR3_RESETVAL (0x00000000u)
597 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR4_MASK (0x000F0000u)
598 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR4_SHIFT (0x00000010u)
599 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR4_RESETVAL (0x00000000u)
601 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR5_MASK (0x00F00000u)
602 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR5_SHIFT (0x00000014u)
603 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR5_RESETVAL (0x00000000u)
605 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR6_MASK (0x0F000000u)
606 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR6_SHIFT (0x00000018u)
607 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR6_RESETVAL (0x00000000u)
609 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR7_MASK (0xF0000000u)
610 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR7_SHIFT (0x0000001Cu)
611 #define CSL_SRIO_RIO_DOORBELL_ICRR1_ICR7_RESETVAL (0x00000000u)
613 #define CSL_SRIO_RIO_DOORBELL_ICRR1_RESETVAL (0x00000000u)
615 /* rio_doorbell_icrr2 */
617 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR8_MASK (0x0000000Fu)
618 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR8_SHIFT (0x00000000u)
619 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR8_RESETVAL (0x00000000u)
621 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR9_MASK (0x000000F0u)
622 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR9_SHIFT (0x00000004u)
623 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR9_RESETVAL (0x00000000u)
625 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR10_MASK (0x00000F00u)
626 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR10_SHIFT (0x00000008u)
627 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR10_RESETVAL (0x00000000u)
629 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR11_MASK (0x0000F000u)
630 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR11_SHIFT (0x0000000Cu)
631 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR11_RESETVAL (0x00000000u)
633 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR12_MASK (0x000F0000u)
634 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR12_SHIFT (0x00000010u)
635 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR12_RESETVAL (0x00000000u)
637 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR13_MASK (0x00F00000u)
638 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR13_SHIFT (0x00000014u)
639 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR13_RESETVAL (0x00000000u)
641 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR14_MASK (0x0F000000u)
642 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR14_SHIFT (0x00000018u)
643 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR14_RESETVAL (0x00000000u)
645 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR15_MASK (0xF0000000u)
646 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR15_SHIFT (0x0000001Cu)
647 #define CSL_SRIO_RIO_DOORBELL_ICRR2_ICR15_RESETVAL (0x00000000u)
649 #define CSL_SRIO_RIO_DOORBELL_ICRR2_RESETVAL (0x00000000u)
651 /* rio_rxu_map_l */
653 #define CSL_SRIO_RIO_RXU_MAP_L_SRCID_MASK (0x0000FFFFu)
654 #define CSL_SRIO_RIO_RXU_MAP_L_SRCID_SHIFT (0x00000000u)
655 #define CSL_SRIO_RIO_RXU_MAP_L_SRCID_RESETVAL (0x00000000u)
657 #define CSL_SRIO_RIO_RXU_MAP_L_MBX_MASK (0x003F0000u)
658 #define CSL_SRIO_RIO_RXU_MAP_L_MBX_SHIFT (0x00000010u)
659 #define CSL_SRIO_RIO_RXU_MAP_L_MBX_RESETVAL (0x00000000u)
661 #define CSL_SRIO_RIO_RXU_MAP_L_LTR_MASK (0x00C00000u)
662 #define CSL_SRIO_RIO_RXU_MAP_L_LTR_SHIFT (0x00000016u)
663 #define CSL_SRIO_RIO_RXU_MAP_L_LTR_RESETVAL (0x00000000u)
665 #define CSL_SRIO_RIO_RXU_MAP_L_MBX_MASK_MASK (0x3F000000u)
666 #define CSL_SRIO_RIO_RXU_MAP_L_MBX_MASK_SHIFT (0x00000018u)
667 #define CSL_SRIO_RIO_RXU_MAP_L_MBX_MASK_RESETVAL (0x0000003Fu)
669 #define CSL_SRIO_RIO_RXU_MAP_L_LTR_MASK_MASK (0xC0000000u)
670 #define CSL_SRIO_RIO_RXU_MAP_L_LTR_MASK_SHIFT (0x0000001Eu)
671 #define CSL_SRIO_RIO_RXU_MAP_L_LTR_MASK_RESETVAL (0x00000003u)
673 #define CSL_SRIO_RIO_RXU_MAP_L_RESETVAL (0xFF000000u)
675 /* rio_rxu_map_h */
677 #define CSL_SRIO_RIO_RXU_MAP_H_SEG_MAP_MASK (0x00000001u)
678 #define CSL_SRIO_RIO_RXU_MAP_H_SEG_MAP_SHIFT (0x00000000u)
679 #define CSL_SRIO_RIO_RXU_MAP_H_SEG_MAP_RESETVAL (0x00000000u)
681 #define CSL_SRIO_RIO_RXU_MAP_H_SRC_PROM_MASK (0x00000002u)
682 #define CSL_SRIO_RIO_RXU_MAP_H_SRC_PROM_SHIFT (0x00000001u)
683 #define CSL_SRIO_RIO_RXU_MAP_H_SRC_PROM_RESETVAL (0x00000000u)
685 #define CSL_SRIO_RIO_RXU_MAP_H_TT_MASK (0x00006000u)
686 #define CSL_SRIO_RIO_RXU_MAP_H_TT_SHIFT (0x0000000Du)
687 #define CSL_SRIO_RIO_RXU_MAP_H_TT_RESETVAL (0x00000001u)
689 #define CSL_SRIO_RIO_RXU_MAP_H_DEST_PROM_MASK (0x00008000u)
690 #define CSL_SRIO_RIO_RXU_MAP_H_DEST_PROM_SHIFT (0x0000000Fu)
691 #define CSL_SRIO_RIO_RXU_MAP_H_DEST_PROM_RESETVAL (0x00000000u)
693 #define CSL_SRIO_RIO_RXU_MAP_H_DEST_ID_MASK (0xFFFF0000u)
694 #define CSL_SRIO_RIO_RXU_MAP_H_DEST_ID_SHIFT (0x00000010u)
695 #define CSL_SRIO_RIO_RXU_MAP_H_DEST_ID_RESETVAL (0x00000000u)
697 #define CSL_SRIO_RIO_RXU_MAP_H_RESETVAL (0x00002000u)
699 /* rio_rxu_map_qid */
701 #define CSL_SRIO_RIO_RXU_MAP_QID_DEST_QID_MASK (0x00003FFFu)
702 #define CSL_SRIO_RIO_RXU_MAP_QID_DEST_QID_SHIFT (0x00000000u)
703 #define CSL_SRIO_RIO_RXU_MAP_QID_DEST_QID_RESETVAL (0x00000000u)
705 #define CSL_SRIO_RIO_RXU_MAP_QID_FLOWID_MASK (0x00FF0000u)
706 #define CSL_SRIO_RIO_RXU_MAP_QID_FLOWID_SHIFT (0x00000010u)
707 #define CSL_SRIO_RIO_RXU_MAP_QID_FLOWID_RESETVAL (0x00000000u)
709 #define CSL_SRIO_RIO_RXU_MAP_QID_RESETVAL (0x00000000u)
711 /* rio_rxu_type9_map0 */
713 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_SRCID_MASK (0x0000FFFFu)
714 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_SRCID_SHIFT (0x00000000u)
715 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_SRCID_RESETVAL (0x00000000u)
717 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_COS_MASK (0x00FF0000u)
718 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_COS_SHIFT (0x00000010u)
719 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_COS_RESETVAL (0x00000000u)
721 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_COS_MASK_MASK (0xFF000000u)
722 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_COS_MASK_SHIFT (0x00000018u)
723 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_COS_MASK_RESETVAL (0x00000000u)
725 #define CSL_SRIO_RIO_RXU_TYPE9_MAP0_RESETVAL (0x00000000u)
727 /* rio_rxu_type9_map1 */
729 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_SRC_PROM_MASK (0x00000002u)
730 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_SRC_PROM_SHIFT (0x00000001u)
731 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_SRC_PROM_RESETVAL (0x00000000u)
733 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_TT_MASK (0x00006000u)
734 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_TT_SHIFT (0x0000000Du)
735 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_TT_RESETVAL (0x00000001u)
737 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_DEST_PROM_MASK (0x00008000u)
738 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_DEST_PROM_SHIFT (0x0000000Fu)
739 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_DEST_PROM_RESETVAL (0x00000000u)
741 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_DEST_ID_MASK (0xFFFF0000u)
742 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_DEST_ID_SHIFT (0x00000010u)
743 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_DEST_ID_RESETVAL (0x00000000u)
745 #define CSL_SRIO_RIO_RXU_TYPE9_MAP1_RESETVAL (0x00002000u)
747 /* rio_rxu_type9_map2 */
749 #define CSL_SRIO_RIO_RXU_TYPE9_MAP2_STRM_ID_MASK (0x0000FFFFu)
750 #define CSL_SRIO_RIO_RXU_TYPE9_MAP2_STRM_ID_SHIFT (0x00000000u)
751 #define CSL_SRIO_RIO_RXU_TYPE9_MAP2_STRM_ID_RESETVAL (0x00000000u)
753 #define CSL_SRIO_RIO_RXU_TYPE9_MAP2_STRM_MASK_MASK (0xFFFF0000u)
754 #define CSL_SRIO_RIO_RXU_TYPE9_MAP2_STRM_MASK_SHIFT (0x00000010u)
755 #define CSL_SRIO_RIO_RXU_TYPE9_MAP2_STRM_MASK_RESETVAL (0x0000FFFFu)
757 #define CSL_SRIO_RIO_RXU_TYPE9_MAP2_RESETVAL (0xFFFF0000u)
759 /* rio_amu_window_reg0 */
761 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_XAMBS_MASK (0x00000003u)
762 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_XAMBS_SHIFT (0x00000000u)
763 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_XAMBS_RESETVAL (0x00000000u)
765 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_PANE_COUNT_MASK (0x00000C00u)
766 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_PANE_COUNT_SHIFT (0x0000000Au)
767 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_PANE_COUNT_RESETVAL (0x00000000u)
769 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_PANE_SIZE_MASK (0x00FFF000u)
770 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_PANE_SIZE_SHIFT (0x0000000Cu)
771 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_PANE_SIZE_RESETVAL (0x00000800u)
773 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_WINDOW_SIZE_MASK (0xFF000000u)
774 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_WINDOW_SIZE_SHIFT (0x00000018u)
775 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_WINDOW_SIZE_RESETVAL (0x00000010u)
777 #define CSL_SRIO_RIO_AMU_WINDOW_REG0_RESETVAL (0x10800000u)
779 /* rio_amu_window_reg1 */
781 #define CSL_SRIO_RIO_AMU_WINDOW_REG1_RIO_ADDRESS_MSB_MASK (0xFFFFFFFFu)
782 #define CSL_SRIO_RIO_AMU_WINDOW_REG1_RIO_ADDRESS_MSB_SHIFT (0x00000000u)
783 #define CSL_SRIO_RIO_AMU_WINDOW_REG1_RIO_ADDRESS_MSB_RESETVAL (0x00000000u)
785 #define CSL_SRIO_RIO_AMU_WINDOW_REG1_RESETVAL (0x00000000u)
787 /* rio_amu_window_reg2 */
789 #define CSL_SRIO_RIO_AMU_WINDOW_REG2_RIO_ADDRESS_LSB_MASK (0xFFFFFFFFu)
790 #define CSL_SRIO_RIO_AMU_WINDOW_REG2_RIO_ADDRESS_LSB_SHIFT (0x00000000u)
791 #define CSL_SRIO_RIO_AMU_WINDOW_REG2_RIO_ADDRESS_LSB_RESETVAL (0x00000000u)
793 #define CSL_SRIO_RIO_AMU_WINDOW_REG2_RESETVAL (0x00000000u)
795 /* rio_lsu_reg0 */
797 #define CSL_SRIO_RIO_LSU_REG0_RIO_ADDRESS_MSB_MASK (0xFFFFFFFFu)
798 #define CSL_SRIO_RIO_LSU_REG0_RIO_ADDRESS_MSB_SHIFT (0x00000000u)
799 #define CSL_SRIO_RIO_LSU_REG0_RIO_ADDRESS_MSB_RESETVAL (0x00000000u)
801 #define CSL_SRIO_RIO_LSU_REG0_RESETVAL (0x00000000u)
803 /* rio_lsu_reg1 */
805 #define CSL_SRIO_RIO_LSU_REG1_RIO_ADDRESS_LSB_MASK (0xFFFFFFFFu)
806 #define CSL_SRIO_RIO_LSU_REG1_RIO_ADDRESS_LSB_SHIFT (0x00000000u)
807 #define CSL_SRIO_RIO_LSU_REG1_RIO_ADDRESS_LSB_RESETVAL (0x00000000u)
809 #define CSL_SRIO_RIO_LSU_REG1_RESETVAL (0x00000000u)
811 /* rio_lsu_reg2 */
813 #define CSL_SRIO_RIO_LSU_REG2_DSP_ADDRESS_MASK (0xFFFFFFFFu)
814 #define CSL_SRIO_RIO_LSU_REG2_DSP_ADDRESS_SHIFT (0x00000000u)
815 #define CSL_SRIO_RIO_LSU_REG2_DSP_ADDRESS_RESETVAL (0x00000000u)
817 #define CSL_SRIO_RIO_LSU_REG2_RESETVAL (0x00000000u)
819 /* rio_lsu_reg3 */
821 #define CSL_SRIO_RIO_LSU_REG3_BYTE_COUNT_MASK (0x000FFFFFu)
822 #define CSL_SRIO_RIO_LSU_REG3_BYTE_COUNT_SHIFT (0x00000000u)
823 #define CSL_SRIO_RIO_LSU_REG3_BYTE_COUNT_RESETVAL (0x00000000u)
825 #define CSL_SRIO_RIO_LSU_REG3_DRBLL_VALUE_MASK (0x80000000u)
826 #define CSL_SRIO_RIO_LSU_REG3_DRBLL_VALUE_SHIFT (0x0000001Fu)
827 #define CSL_SRIO_RIO_LSU_REG3_DRBLL_VALUE_RESETVAL (0x00000000u)
829 #define CSL_SRIO_RIO_LSU_REG3_RESETVAL (0x00000000u)
831 /* rio_lsu_reg4 */
833 #define CSL_SRIO_RIO_LSU_REG4_INT_REQ_MASK (0x00000001u)
834 #define CSL_SRIO_RIO_LSU_REG4_INT_REQ_SHIFT (0x00000000u)
835 #define CSL_SRIO_RIO_LSU_REG4_INT_REQ_RESETVAL (0x00000000u)
837 #define CSL_SRIO_RIO_LSU_REG4_SUP_GINT_MASK (0x00000002u)
838 #define CSL_SRIO_RIO_LSU_REG4_SUP_GINT_SHIFT (0x00000001u)
839 #define CSL_SRIO_RIO_LSU_REG4_SUP_GINT_RESETVAL (0x00000000u)
841 #define CSL_SRIO_RIO_LSU_REG4_XAMBS_MASK (0x0000000Cu)
842 #define CSL_SRIO_RIO_LSU_REG4_XAMBS_SHIFT (0x00000002u)
843 #define CSL_SRIO_RIO_LSU_REG4_XAMBS_RESETVAL (0x00000000u)
845 #define CSL_SRIO_RIO_LSU_REG4_PRIORITY_MASK (0x000000F0u)
846 #define CSL_SRIO_RIO_LSU_REG4_PRIORITY_SHIFT (0x00000004u)
847 #define CSL_SRIO_RIO_LSU_REG4_PRIORITY_RESETVAL (0x00000000u)
849 #define CSL_SRIO_RIO_LSU_REG4_OUTPORTID_MASK (0x00000300u)
850 #define CSL_SRIO_RIO_LSU_REG4_OUTPORTID_SHIFT (0x00000008u)
851 #define CSL_SRIO_RIO_LSU_REG4_OUTPORTID_RESETVAL (0x00000000u)
853 #define CSL_SRIO_RIO_LSU_REG4_ID_SIZE_MASK (0x00000C00u)
854 #define CSL_SRIO_RIO_LSU_REG4_ID_SIZE_SHIFT (0x0000000Au)
855 #define CSL_SRIO_RIO_LSU_REG4_ID_SIZE_RESETVAL (0x00000000u)
857 #define CSL_SRIO_RIO_LSU_REG4_SRCID_MAP_MASK (0x0000F000u)
858 #define CSL_SRIO_RIO_LSU_REG4_SRCID_MAP_SHIFT (0x0000000Cu)
859 #define CSL_SRIO_RIO_LSU_REG4_SRCID_MAP_RESETVAL (0x00000000u)
861 #define CSL_SRIO_RIO_LSU_REG4_DESTID_MASK (0xFFFF0000u)
862 #define CSL_SRIO_RIO_LSU_REG4_DESTID_SHIFT (0x00000010u)
863 #define CSL_SRIO_RIO_LSU_REG4_DESTID_RESETVAL (0x00000000u)
865 #define CSL_SRIO_RIO_LSU_REG4_RESETVAL (0x00000000u)
867 /* rio_lsu_reg5 */
869 #define CSL_SRIO_RIO_LSU_REG5_TTYPE_MASK (0x0000000Fu)
870 #define CSL_SRIO_RIO_LSU_REG5_TTYPE_SHIFT (0x00000000u)
871 #define CSL_SRIO_RIO_LSU_REG5_TTYPE_RESETVAL (0x00000000u)
873 #define CSL_SRIO_RIO_LSU_REG5_FTYPE_MASK (0x000000F0u)
874 #define CSL_SRIO_RIO_LSU_REG5_FTYPE_SHIFT (0x00000004u)
875 #define CSL_SRIO_RIO_LSU_REG5_FTYPE_RESETVAL (0x00000000u)
877 #define CSL_SRIO_RIO_LSU_REG5_HOP_COUNT_MASK (0x0000FF00u)
878 #define CSL_SRIO_RIO_LSU_REG5_HOP_COUNT_SHIFT (0x00000008u)
879 #define CSL_SRIO_RIO_LSU_REG5_HOP_COUNT_RESETVAL (0x000000FFu)
881 #define CSL_SRIO_RIO_LSU_REG5_DRBLL_INFO_MASK (0xFFFF0000u)
882 #define CSL_SRIO_RIO_LSU_REG5_DRBLL_INFO_SHIFT (0x00000010u)
883 #define CSL_SRIO_RIO_LSU_REG5_DRBLL_INFO_RESETVAL (0x00000000u)
885 #define CSL_SRIO_RIO_LSU_REG5_RESETVAL (0x0000FF00u)
887 /* rio_lsu_reg6 */
889 #define CSL_SRIO_RIO_LSU_REG6_LTID_MASK (0x0000000Fu)
890 #define CSL_SRIO_RIO_LSU_REG6_LTID_SHIFT (0x00000000u)
891 #define CSL_SRIO_RIO_LSU_REG6_LTID_RESETVAL (0x00000000u)
893 #define CSL_SRIO_RIO_LSU_REG6_LCB_MASK (0x00000010u)
894 #define CSL_SRIO_RIO_LSU_REG6_LCB_SHIFT (0x00000004u)
895 #define CSL_SRIO_RIO_LSU_REG6_LCB_RESETVAL (0x00000001u)
897 #define CSL_SRIO_RIO_LSU_REG6_FULL_MASK (0x40000000u)
898 #define CSL_SRIO_RIO_LSU_REG6_FULL_SHIFT (0x0000001Eu)
899 #define CSL_SRIO_RIO_LSU_REG6_FULL_RESETVAL (0x00000000u)
901 #define CSL_SRIO_RIO_LSU_REG6_BUSY_MASK (0x80000000u)
902 #define CSL_SRIO_RIO_LSU_REG6_BUSY_SHIFT (0x0000001Fu)
903 #define CSL_SRIO_RIO_LSU_REG6_BUSY_RESETVAL (0x00000000u)
905 #define CSL_SRIO_RIO_LSU_REG6_FLUSH_MASK (0x00000001u)
906 #define CSL_SRIO_RIO_LSU_REG6_FLUSH_SHIFT (0x00000000u)
907 #define CSL_SRIO_RIO_LSU_REG6_FLUSH_RESETVAL (0x00000000u)
909 #define CSL_SRIO_RIO_LSU_REG6_RESTART_MASK (0x00000002u)
910 #define CSL_SRIO_RIO_LSU_REG6_RESTART_SHIFT (0x00000001u)
911 #define CSL_SRIO_RIO_LSU_REG6_RESTART_RESETVAL (0x00000000u)
913 #define CSL_SRIO_RIO_LSU_REG6_SCRID_MAP_MASK (0x0000003Cu)
914 #define CSL_SRIO_RIO_LSU_REG6_SCRID_MAP_SHIFT (0x00000002u)
915 #define CSL_SRIO_RIO_LSU_REG6_SCRID_MAP_RESETVAL (0x00000000u)
917 #define CSL_SRIO_RIO_LSU_REG6_CBUSY_MASK (0x08000000u)
918 #define CSL_SRIO_RIO_LSU_REG6_CBUSY_SHIFT (0x0000001Bu)
919 #define CSL_SRIO_RIO_LSU_REG6_CBUSY_RESETVAL (0x00000000u)
921 #define CSL_SRIO_RIO_LSU_REG6_PRIVID_MASK (0xF0000000u)
922 #define CSL_SRIO_RIO_LSU_REG6_PRIVID_SHIFT (0x0000001Cu)
923 #define CSL_SRIO_RIO_LSU_REG6_PRIVID_RESETVAL (0x00000000u)
925 #define CSL_SRIO_RIO_LSU_REG6_RESETVAL (0x00000010u)
927 /* tx_channel_global_config_reg_a */
929 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_PAUSE_MASK (0x20000000u)
930 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_PAUSE_SHIFT (0x0000001Du)
931 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_PAUSE_RESETVAL (0x00000000u)
933 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_TEARDOWN_MASK (0x40000000u)
934 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_TEARDOWN_SHIFT (0x0000001Eu)
935 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_TEARDOWN_RESETVAL (0x00000000u)
937 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_ENABLE_MASK (0x80000000u)
938 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_ENABLE_SHIFT (0x0000001Fu)
939 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_ENABLE_RESETVAL (0x00000000u)
941 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_A_RESETVAL (0x00000000u)
943 /* tx_channel_global_config_reg_b */
945 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_DEFAULT_QNUM_MASK (0x00000FFFu)
946 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_DEFAULT_QNUM_SHIFT (0x00000000u)
947 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_DEFAULT_QNUM_RESETVAL (0x00000000u)
949 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_DEFAULT_QMGR_MASK (0x00003000u)
950 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_DEFAULT_QMGR_SHIFT (0x0000000Cu)
951 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_DEFAULT_QMGR_RESETVAL (0x00000000u)
953 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_AIF_MONO_MODE_MASK (0x01000000u)
954 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_AIF_MONO_MODE_SHIFT (0x00000018u)
955 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_AIF_MONO_MODE_RESETVAL (0x00000000u)
957 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_PSWORDS_MASK (0x20000000u)
958 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_PSWORDS_SHIFT (0x0000001Du)
959 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_PSWORDS_RESETVAL (0x00000000u)
961 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_EINFO_MASK (0x40000000u)
962 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_EINFO_SHIFT (0x0000001Eu)
963 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_EINFO_RESETVAL (0x00000000u)
965 #define CSL_SRIO_TX_CHANNEL_GLOBAL_CONFIG_REG_B_RESETVAL (0x00000000u)
967 /* rx_channel_global_config_reg */
969 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_MASK (0x20000000u)
970 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_SHIFT (0x0000001Du)
971 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_RESETVAL (0x00000000u)
973 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_MASK (0x40000000u)
974 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_SHIFT (0x0000001Eu)
975 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_RESETVAL (0x00000000u)
977 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_MASK (0x80000000u)
978 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_SHIFT (0x0000001Fu)
979 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_RESETVAL (0x00000000u)
981 #define CSL_SRIO_RX_CHANNEL_GLOBAL_CONFIG_REG_RESETVAL (0x00000000u)
983 /* rx_flow_config_reg_a */
985 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_MASK (0x00000FFFu)
986 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_SHIFT (0x00000000u)
987 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_RESETVAL (0x00000000u)
989 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_MASK (0x00003000u)
990 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_SHIFT (0x0000000Cu)
991 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_RESETVAL (0x00000000u)
993 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_MASK (0x01FF0000u)
994 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_SHIFT (0x00000010u)
995 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_RESETVAL (0x00000000u)
997 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_MASK (0x02000000u)
998 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_SHIFT (0x00000019u)
999 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_RESETVAL (0x00000000u)
1001 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_MASK (0x0C000000u)
1002 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_SHIFT (0x0000001Au)
1003 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_RESETVAL (0x00000000u)
1005 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_MASK (0x10000000u)
1006 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_SHIFT (0x0000001Cu)
1007 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_RESETVAL (0x00000000u)
1009 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_MASK (0x20000000u)
1010 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_SHIFT (0x0000001Du)
1011 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_RESETVAL (0x00000000u)
1013 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_MASK (0x40000000u)
1014 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_SHIFT (0x0000001Eu)
1015 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_RESETVAL (0x00000000u)
1017 #define CSL_SRIO_RX_FLOW_CONFIG_REG_A_RESETVAL (0x00000000u)
1019 /* rx_flow_config_reg_b */
1021 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_MASK (0x000000FFu)
1022 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_SHIFT (0x00000000u)
1023 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_RESETVAL (0x00000000u)
1025 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_MASK (0x0000FF00u)
1026 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_SHIFT (0x00000008u)
1027 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_RESETVAL (0x00000000u)
1029 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_MASK (0x00FF0000u)
1030 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_SHIFT (0x00000010u)
1031 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_RESETVAL (0x00000000u)
1033 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_MASK (0xFF000000u)
1034 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_SHIFT (0x00000018u)
1035 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_RESETVAL (0x00000000u)
1037 #define CSL_SRIO_RX_FLOW_CONFIG_REG_B_RESETVAL (0x00000000u)
1039 /* rx_flow_config_reg_c */
1041 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_MASK (0x0000000Fu)
1042 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_SHIFT (0x00000000u)
1043 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_RESETVAL (0x00000000u)
1045 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_MASK (0x00070000u)
1046 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_SHIFT (0x00000010u)
1047 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_RESETVAL (0x00000000u)
1049 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_MASK (0x00700000u)
1050 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_SHIFT (0x00000014u)
1051 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_RESETVAL (0x00000000u)
1053 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_MASK (0x07000000u)
1054 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_SHIFT (0x00000018u)
1055 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_RESETVAL (0x00000000u)
1057 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_MASK (0x70000000u)
1058 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_SHIFT (0x0000001Cu)
1059 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_RESETVAL (0x00000000u)
1061 #define CSL_SRIO_RX_FLOW_CONFIG_REG_C_RESETVAL (0x00000000u)
1063 /* rx_flow_config_reg_d */
1065 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_MASK (0x00000FFFu)
1066 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_SHIFT (0x00000000u)
1067 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_RESETVAL (0x00000000u)
1069 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_MASK (0x00003000u)
1070 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_SHIFT (0x0000000Cu)
1071 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_RESETVAL (0x00000000u)
1073 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_MASK (0x0FFF0000u)
1074 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_SHIFT (0x00000010u)
1075 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_RESETVAL (0x00000000u)
1077 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_MASK (0x30000000u)
1078 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_SHIFT (0x0000001Cu)
1079 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_RESETVAL (0x00000000u)
1081 #define CSL_SRIO_RX_FLOW_CONFIG_REG_D_RESETVAL (0x00000000u)
1083 /* rx_flow_config_reg_e */
1085 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_MASK (0x00000FFFu)
1086 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_SHIFT (0x00000000u)
1087 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_RESETVAL (0x00000000u)
1089 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_MASK (0x00003000u)
1090 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_SHIFT (0x0000000Cu)
1091 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_RESETVAL (0x00000000u)
1093 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_MASK (0x0FFF0000u)
1094 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_SHIFT (0x00000010u)
1095 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_RESETVAL (0x00000000u)
1097 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_MASK (0x30000000u)
1098 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_SHIFT (0x0000001Cu)
1099 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_RESETVAL (0x00000000u)
1101 #define CSL_SRIO_RX_FLOW_CONFIG_REG_E_RESETVAL (0x00000000u)
1103 /* rx_flow_config_reg_f */
1105 #define CSL_SRIO_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_MASK (0x0000FFFFu)
1106 #define CSL_SRIO_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_SHIFT (0x00000000u)
1107 #define CSL_SRIO_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_RESETVAL (0x00000000u)
1109 #define CSL_SRIO_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_MASK (0xFFFF0000u)
1110 #define CSL_SRIO_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_SHIFT (0x00000010u)
1111 #define CSL_SRIO_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_RESETVAL (0x00000000u)
1113 #define CSL_SRIO_RX_FLOW_CONFIG_REG_F_RESETVAL (0x00000000u)
1115 /* rx_flow_config_reg_g */
1117 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_MASK (0x00000FFFu)
1118 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_SHIFT (0x00000000u)
1119 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_RESETVAL (0x00000000u)
1121 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_MASK (0x00003000u)
1122 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_SHIFT (0x0000000Cu)
1123 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_RESETVAL (0x00000000u)
1125 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_MASK (0xFFFF0000u)
1126 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_SHIFT (0x00000010u)
1127 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_RESETVAL (0x00000000u)
1129 #define CSL_SRIO_RX_FLOW_CONFIG_REG_G_RESETVAL (0x00000000u)
1131 /* rx_flow_config_reg_h */
1133 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_MASK (0x00000FFFu)
1134 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_SHIFT (0x00000000u)
1135 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_RESETVAL (0x00000000u)
1137 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_MASK (0x00003000u)
1138 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_SHIFT (0x0000000Cu)
1139 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_RESETVAL (0x00000000u)
1141 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_MASK (0x0FFF0000u)
1142 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_SHIFT (0x00000010u)
1143 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_RESETVAL (0x00000000u)
1145 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_MASK (0x30000000u)
1146 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_SHIFT (0x0000001Cu)
1147 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_RESETVAL (0x00000000u)
1149 #define CSL_SRIO_RX_FLOW_CONFIG_REG_H_RESETVAL (0x00000000u)
1151 /* rio_sp_lm_req */
1153 #define CSL_SRIO_RIO_SP_LM_REQ_CMD_MASK (0x00000007u)
1154 #define CSL_SRIO_RIO_SP_LM_REQ_CMD_SHIFT (0x00000000u)
1155 #define CSL_SRIO_RIO_SP_LM_REQ_CMD_RESETVAL (0x00000000u)
1157 #define CSL_SRIO_RIO_SP_LM_REQ_RESETVAL (0x00000000u)
1159 /* rio_sp_lm_resp */
1161 #define CSL_SRIO_RIO_SP_LM_RESP_RESP_VALID_MASK (0x80000000u)
1162 #define CSL_SRIO_RIO_SP_LM_RESP_RESP_VALID_SHIFT (0x0000001Fu)
1163 #define CSL_SRIO_RIO_SP_LM_RESP_RESP_VALID_RESETVAL (0x00000000u)
1165 #define CSL_SRIO_RIO_SP_LM_RESP_ACK_ID_STAT_MASK (0x000007E0u)
1166 #define CSL_SRIO_RIO_SP_LM_RESP_ACK_ID_STAT_SHIFT (0x00000005u)
1167 #define CSL_SRIO_RIO_SP_LM_RESP_ACK_ID_STAT_RESETVAL (0x00000000u)
1169 #define CSL_SRIO_RIO_SP_LM_RESP_LINK_STAT_MASK (0x0000001Fu)
1170 #define CSL_SRIO_RIO_SP_LM_RESP_LINK_STAT_SHIFT (0x00000000u)
1171 #define CSL_SRIO_RIO_SP_LM_RESP_LINK_STAT_RESETVAL (0x00000000u)
1173 #define CSL_SRIO_RIO_SP_LM_RESP_RESETVAL (0x00000000u)
1175 /* rio_sp_ackid_stat */
1177 #define CSL_SRIO_RIO_SP_ACKID_STAT_CLR_OUTSTD_ACKID_MASK (0x80000000u)
1178 #define CSL_SRIO_RIO_SP_ACKID_STAT_CLR_OUTSTD_ACKID_SHIFT (0x0000001Fu)
1179 #define CSL_SRIO_RIO_SP_ACKID_STAT_CLR_OUTSTD_ACKID_RESETVAL (0x00000000u)
1181 #define CSL_SRIO_RIO_SP_ACKID_STAT_INB_ACKID_MASK (0x3F000000u)
1182 #define CSL_SRIO_RIO_SP_ACKID_STAT_INB_ACKID_SHIFT (0x00000018u)
1183 #define CSL_SRIO_RIO_SP_ACKID_STAT_INB_ACKID_RESETVAL (0x00000000u)
1185 #define CSL_SRIO_RIO_SP_ACKID_STAT_OUTSTD_ACKID_MASK (0x00001F00u)
1186 #define CSL_SRIO_RIO_SP_ACKID_STAT_OUTSTD_ACKID_SHIFT (0x00000008u)
1187 #define CSL_SRIO_RIO_SP_ACKID_STAT_OUTSTD_ACKID_RESETVAL (0x00000000u)
1189 #define CSL_SRIO_RIO_SP_ACKID_STAT_OUTB_ACKID_MASK (0x0000003Fu)
1190 #define CSL_SRIO_RIO_SP_ACKID_STAT_OUTB_ACKID_SHIFT (0x00000000u)
1191 #define CSL_SRIO_RIO_SP_ACKID_STAT_OUTB_ACKID_RESETVAL (0x00000000u)
1193 #define CSL_SRIO_RIO_SP_ACKID_STAT_RESETVAL (0x00000000u)
1195 /* rio_sp_ctl2 */
1197 #define CSL_SRIO_RIO_SP_CTL2_BAUD_SEL_MASK (0xF0000000u)
1198 #define CSL_SRIO_RIO_SP_CTL2_BAUD_SEL_SHIFT (0x0000001Cu)
1199 #define CSL_SRIO_RIO_SP_CTL2_BAUD_SEL_RESETVAL (0x00000000u)
1201 #define CSL_SRIO_RIO_SP_CTL2_BAUD_DISC_MASK (0x08000000u)
1202 #define CSL_SRIO_RIO_SP_CTL2_BAUD_DISC_SHIFT (0x0000001Bu)
1203 #define CSL_SRIO_RIO_SP_CTL2_BAUD_DISC_RESETVAL (0x00000000u)
1205 #define CSL_SRIO_RIO_SP_CTL2_GB_1P25_MASK (0x02000000u)
1206 #define CSL_SRIO_RIO_SP_CTL2_GB_1P25_SHIFT (0x00000019u)
1207 #define CSL_SRIO_RIO_SP_CTL2_GB_1P25_RESETVAL (0x00000001u)
1209 #define CSL_SRIO_RIO_SP_CTL2_GB_1P25_EN_MASK (0x01000000u)
1210 #define CSL_SRIO_RIO_SP_CTL2_GB_1P25_EN_SHIFT (0x00000018u)
1211 #define CSL_SRIO_RIO_SP_CTL2_GB_1P25_EN_RESETVAL (0x00000000u)
1213 #define CSL_SRIO_RIO_SP_CTL2_GB_2P5_MASK (0x00800000u)
1214 #define CSL_SRIO_RIO_SP_CTL2_GB_2P5_SHIFT (0x00000017u)
1215 #define CSL_SRIO_RIO_SP_CTL2_GB_2P5_RESETVAL (0x00000001u)
1217 #define CSL_SRIO_RIO_SP_CTL2_GB_2P5_EN_MASK (0x00400000u)
1218 #define CSL_SRIO_RIO_SP_CTL2_GB_2P5_EN_SHIFT (0x00000016u)
1219 #define CSL_SRIO_RIO_SP_CTL2_GB_2P5_EN_RESETVAL (0x00000000u)
1221 #define CSL_SRIO_RIO_SP_CTL2_GB_3P125_MASK (0x00200000u)
1222 #define CSL_SRIO_RIO_SP_CTL2_GB_3P125_SHIFT (0x00000015u)
1223 #define CSL_SRIO_RIO_SP_CTL2_GB_3P125_RESETVAL (0x00000001u)
1225 #define CSL_SRIO_RIO_SP_CTL2_GB_3P125_EN_MASK (0x00100000u)
1226 #define CSL_SRIO_RIO_SP_CTL2_GB_3P125_EN_SHIFT (0x00000014u)
1227 #define CSL_SRIO_RIO_SP_CTL2_GB_3P125_EN_RESETVAL (0x00000000u)
1229 #define CSL_SRIO_RIO_SP_CTL2_GB_5P0_MASK (0x00080000u)
1230 #define CSL_SRIO_RIO_SP_CTL2_GB_5P0_SHIFT (0x00000013u)
1231 #define CSL_SRIO_RIO_SP_CTL2_GB_5P0_RESETVAL (0x00000001u)
1233 #define CSL_SRIO_RIO_SP_CTL2_GB_5P0_EN_MASK (0x00040000u)
1234 #define CSL_SRIO_RIO_SP_CTL2_GB_5P0_EN_SHIFT (0x00000012u)
1235 #define CSL_SRIO_RIO_SP_CTL2_GB_5P0_EN_RESETVAL (0x00000000u)
1237 #define CSL_SRIO_RIO_SP_CTL2_GB_6P25_MASK (0x00020000u)
1238 #define CSL_SRIO_RIO_SP_CTL2_GB_6P25_SHIFT (0x00000011u)
1239 #define CSL_SRIO_RIO_SP_CTL2_GB_6P25_RESETVAL (0x00000001u)
1241 #define CSL_SRIO_RIO_SP_CTL2_GB_6P25_EN_MASK (0x00010000u)
1242 #define CSL_SRIO_RIO_SP_CTL2_GB_6P25_EN_SHIFT (0x00000010u)
1243 #define CSL_SRIO_RIO_SP_CTL2_GB_6P25_EN_RESETVAL (0x00000000u)
1245 #define CSL_SRIO_RIO_SP_CTL2_INACT_EN_MASK (0x00000008u)
1246 #define CSL_SRIO_RIO_SP_CTL2_INACT_EN_SHIFT (0x00000003u)
1247 #define CSL_SRIO_RIO_SP_CTL2_INACT_EN_RESETVAL (0x00000000u)
1249 #define CSL_SRIO_RIO_SP_CTL2_D_SCRM_DIS_MASK (0x00000004u)
1250 #define CSL_SRIO_RIO_SP_CTL2_D_SCRM_DIS_SHIFT (0x00000002u)
1251 #define CSL_SRIO_RIO_SP_CTL2_D_SCRM_DIS_RESETVAL (0x00000000u)
1253 #define CSL_SRIO_RIO_SP_CTL2_RTEC_MASK (0x00000002u)
1254 #define CSL_SRIO_RIO_SP_CTL2_RTEC_SHIFT (0x00000001u)
1255 #define CSL_SRIO_RIO_SP_CTL2_RTEC_RESETVAL (0x00000000u)
1257 #define CSL_SRIO_RIO_SP_CTL2_RTEC_EN_MASK (0x00000001u)
1258 #define CSL_SRIO_RIO_SP_CTL2_RTEC_EN_SHIFT (0x00000000u)
1259 #define CSL_SRIO_RIO_SP_CTL2_RTEC_EN_RESETVAL (0x00000000u)
1261 #define CSL_SRIO_RIO_SP_CTL2_RESETVAL (0x02AA0000u)
1263 /* rio_sp_err_stat */
1265 #define CSL_SRIO_RIO_SP_ERR_STAT_IDLE2_MASK (0x80000000u)
1266 #define CSL_SRIO_RIO_SP_ERR_STAT_IDLE2_SHIFT (0x0000001Fu)
1267 #define CSL_SRIO_RIO_SP_ERR_STAT_IDLE2_RESETVAL (0x00000000u)
1269 #define CSL_SRIO_RIO_SP_ERR_STAT_IDLE2_EN_MASK (0x40000000u)
1270 #define CSL_SRIO_RIO_SP_ERR_STAT_IDLE2_EN_SHIFT (0x0000001Eu)
1271 #define CSL_SRIO_RIO_SP_ERR_STAT_IDLE2_EN_RESETVAL (0x00000000u)
1273 #define CSL_SRIO_RIO_SP_ERR_STAT_IDLE2_SEQ_MASK (0x20000000u)
1274 #define CSL_SRIO_RIO_SP_ERR_STAT_IDLE2_SEQ_SHIFT (0x0000001Du)
1275 #define CSL_SRIO_RIO_SP_ERR_STAT_IDLE2_SEQ_RESETVAL (0x00000000u)
1277 #define CSL_SRIO_RIO_SP_ERR_STAT_TXFC_MASK (0x08000000u)
1278 #define CSL_SRIO_RIO_SP_ERR_STAT_TXFC_SHIFT (0x0000001Bu)
1279 #define CSL_SRIO_RIO_SP_ERR_STAT_TXFC_RESETVAL (0x00000000u)
1281 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_DROP_MASK (0x04000000u)
1282 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_DROP_SHIFT (0x0000001Au)
1283 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_DROP_RESETVAL (0x00000000u)
1285 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_FAIL_MASK (0x02000000u)
1286 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_FAIL_SHIFT (0x00000019u)
1287 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_FAIL_RESETVAL (0x00000000u)
1289 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_DEGR_MASK (0x01000000u)
1290 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_DEGR_SHIFT (0x00000018u)
1291 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_DEGR_RESETVAL (0x00000000u)
1293 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_RETRY_MASK (0x00100000u)
1294 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_RETRY_SHIFT (0x00000014u)
1295 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_RETRY_RESETVAL (0x00000000u)
1297 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_RETRIED_MASK (0x00080000u)
1298 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_RETRIED_SHIFT (0x00000013u)
1299 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_RETRIED_RESETVAL (0x00000000u)
1301 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_RETRY_STOPPED_MASK (0x00040000u)
1302 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_RETRY_STOPPED_SHIFT (0x00000012u)
1303 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_RETRY_STOPPED_RESETVAL (0x00000000u)
1305 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_ERR_MASK (0x00020000u)
1306 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_ERR_SHIFT (0x00000011u)
1307 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_ERR_RESETVAL (0x00000000u)
1309 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_ERR_STOPPED_MASK (0x00010000u)
1310 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_ERR_STOPPED_SHIFT (0x00000010u)
1311 #define CSL_SRIO_RIO_SP_ERR_STAT_OUTPUT_ERR_STOPPED_RESETVAL (0x00000000u)
1313 #define CSL_SRIO_RIO_SP_ERR_STAT_INPUT_RETRY_STOPPED_MASK (0x00000400u)
1314 #define CSL_SRIO_RIO_SP_ERR_STAT_INPUT_RETRY_STOPPED_SHIFT (0x0000000Au)
1315 #define CSL_SRIO_RIO_SP_ERR_STAT_INPUT_RETRY_STOPPED_RESETVAL (0x00000000u)
1317 #define CSL_SRIO_RIO_SP_ERR_STAT_INPUT_ERR_ENCTR_MASK (0x00000200u)
1318 #define CSL_SRIO_RIO_SP_ERR_STAT_INPUT_ERR_ENCTR_SHIFT (0x00000009u)
1319 #define CSL_SRIO_RIO_SP_ERR_STAT_INPUT_ERR_ENCTR_RESETVAL (0x00000000u)
1321 #define CSL_SRIO_RIO_SP_ERR_STAT_INPUT_ERR_STOPPED_MASK (0x00000100u)
1322 #define CSL_SRIO_RIO_SP_ERR_STAT_INPUT_ERR_STOPPED_SHIFT (0x00000008u)
1323 #define CSL_SRIO_RIO_SP_ERR_STAT_INPUT_ERR_STOPPED_RESETVAL (0x00000000u)
1325 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_WRITE_PEND_MASK (0x00000010u)
1326 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_WRITE_PEND_SHIFT (0x00000004u)
1327 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_WRITE_PEND_RESETVAL (0x00000000u)
1329 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_UNAVL_MASK (0x00000008u)
1330 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_UNAVL_SHIFT (0x00000003u)
1331 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_UNAVL_RESETVAL (0x00000000u)
1333 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_ERR_MASK (0x00000004u)
1334 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_ERR_SHIFT (0x00000002u)
1335 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_ERR_RESETVAL (0x00000000u)
1337 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_OK_MASK (0x00000002u)
1338 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_OK_SHIFT (0x00000001u)
1339 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_OK_RESETVAL (0x00000000u)
1341 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_UNINIT_MASK (0x00000001u)
1342 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_UNINIT_SHIFT (0x00000000u)
1343 #define CSL_SRIO_RIO_SP_ERR_STAT_PORT_UNINIT_RESETVAL (0x00000001u)
1345 #define CSL_SRIO_RIO_SP_ERR_STAT_RESETVAL (0x00000001u)
1347 /* rio_sp_ctl */
1349 #define CSL_SRIO_RIO_SP_CTL_PORT_WIDTH_MASK (0xC0000000u)
1350 #define CSL_SRIO_RIO_SP_CTL_PORT_WIDTH_SHIFT (0x0000001Eu)
1351 #define CSL_SRIO_RIO_SP_CTL_PORT_WIDTH_RESETVAL (0x00000000u)
1353 #define CSL_SRIO_RIO_SP_CTL_INIT_PWIDTH_MASK (0x38000000u)
1354 #define CSL_SRIO_RIO_SP_CTL_INIT_PWIDTH_SHIFT (0x0000001Bu)
1355 #define CSL_SRIO_RIO_SP_CTL_INIT_PWIDTH_RESETVAL (0x00000000u)
1357 #define CSL_SRIO_RIO_SP_CTL_OVER_PWIDTH_MASK (0x07000000u)
1358 #define CSL_SRIO_RIO_SP_CTL_OVER_PWIDTH_SHIFT (0x00000018u)
1359 #define CSL_SRIO_RIO_SP_CTL_OVER_PWIDTH_RESETVAL (0x00000000u)
1361 #define CSL_SRIO_RIO_SP_CTL_PORT_DIS_MASK (0x00800000u)
1362 #define CSL_SRIO_RIO_SP_CTL_PORT_DIS_SHIFT (0x00000017u)
1363 #define CSL_SRIO_RIO_SP_CTL_PORT_DIS_RESETVAL (0x00000000u)
1365 #define CSL_SRIO_RIO_SP_CTL_OTP_EN_MASK (0x00400000u)
1366 #define CSL_SRIO_RIO_SP_CTL_OTP_EN_SHIFT (0x00000016u)
1367 #define CSL_SRIO_RIO_SP_CTL_OTP_EN_RESETVAL (0x00000000u)
1369 #define CSL_SRIO_RIO_SP_CTL_INP_EN_MASK (0x00200000u)
1370 #define CSL_SRIO_RIO_SP_CTL_INP_EN_SHIFT (0x00000015u)
1371 #define CSL_SRIO_RIO_SP_CTL_INP_EN_RESETVAL (0x00000000u)
1373 #define CSL_SRIO_RIO_SP_CTL_ERR_DIS_MASK (0x00100000u)
1374 #define CSL_SRIO_RIO_SP_CTL_ERR_DIS_SHIFT (0x00000014u)
1375 #define CSL_SRIO_RIO_SP_CTL_ERR_DIS_RESETVAL (0x00000000u)
1377 #define CSL_SRIO_RIO_SP_CTL_MULT_CS_MASK (0x00080000u)
1378 #define CSL_SRIO_RIO_SP_CTL_MULT_CS_SHIFT (0x00000013u)
1379 #define CSL_SRIO_RIO_SP_CTL_MULT_CS_RESETVAL (0x00000000u)
1381 #define CSL_SRIO_RIO_SP_CTL_FLOW_CTRL_MASK (0x00040000u)
1382 #define CSL_SRIO_RIO_SP_CTL_FLOW_CTRL_SHIFT (0x00000012u)
1383 #define CSL_SRIO_RIO_SP_CTL_FLOW_CTRL_RESETVAL (0x00000000u)
1385 #define CSL_SRIO_RIO_SP_CTL_ENUM_B_MASK (0x00020000u)
1386 #define CSL_SRIO_RIO_SP_CTL_ENUM_B_SHIFT (0x00000011u)
1387 #define CSL_SRIO_RIO_SP_CTL_ENUM_B_RESETVAL (0x00000000u)
1389 #define CSL_SRIO_RIO_SP_CTL_FLOW_ARB_MASK (0x00010000u)
1390 #define CSL_SRIO_RIO_SP_CTL_FLOW_ARB_SHIFT (0x00000010u)
1391 #define CSL_SRIO_RIO_SP_CTL_FLOW_ARB_RESETVAL (0x00000000u)
1393 #define CSL_SRIO_RIO_SP_CTL_OVER_PWIDTH2_MASK (0x0000C000u)
1394 #define CSL_SRIO_RIO_SP_CTL_OVER_PWIDTH2_SHIFT (0x0000000Eu)
1395 #define CSL_SRIO_RIO_SP_CTL_OVER_PWIDTH2_RESETVAL (0x00000000u)
1397 #define CSL_SRIO_RIO_SP_CTL_PORT_WIDTH2_MASK (0x00003000u)
1398 #define CSL_SRIO_RIO_SP_CTL_PORT_WIDTH2_SHIFT (0x0000000Cu)
1399 #define CSL_SRIO_RIO_SP_CTL_PORT_WIDTH2_RESETVAL (0x00000000u)
1401 #define CSL_SRIO_RIO_SP_CTL_STOP_FAIL_EN_MASK (0x00000008u)
1402 #define CSL_SRIO_RIO_SP_CTL_STOP_FAIL_EN_SHIFT (0x00000003u)
1403 #define CSL_SRIO_RIO_SP_CTL_STOP_FAIL_EN_RESETVAL (0x00000000u)
1405 #define CSL_SRIO_RIO_SP_CTL_DROP_EN_MASK (0x00000004u)
1406 #define CSL_SRIO_RIO_SP_CTL_DROP_EN_SHIFT (0x00000002u)
1407 #define CSL_SRIO_RIO_SP_CTL_DROP_EN_RESETVAL (0x00000000u)
1409 #define CSL_SRIO_RIO_SP_CTL_PORT_LOCKOUT_MASK (0x00000002u)
1410 #define CSL_SRIO_RIO_SP_CTL_PORT_LOCKOUT_SHIFT (0x00000001u)
1411 #define CSL_SRIO_RIO_SP_CTL_PORT_LOCKOUT_RESETVAL (0x00000000u)
1413 #define CSL_SRIO_RIO_SP_CTL_PTYP_MASK (0x00000001u)
1414 #define CSL_SRIO_RIO_SP_CTL_PTYP_SHIFT (0x00000000u)
1415 #define CSL_SRIO_RIO_SP_CTL_PTYP_RESETVAL (0x00000001u)
1417 #define CSL_SRIO_RIO_SP_CTL_RESETVAL (0x00000001u)
1419 /* rio_sp_err_det */
1421 #define CSL_SRIO_RIO_SP_ERR_DET_IMP_SPEC_MASK (0x80000000u)
1422 #define CSL_SRIO_RIO_SP_ERR_DET_IMP_SPEC_SHIFT (0x0000001Fu)
1423 #define CSL_SRIO_RIO_SP_ERR_DET_IMP_SPEC_RESETVAL (0x00000000u)
1425 #define CSL_SRIO_RIO_SP_ERR_DET_CS_CRC_ERR_MASK (0x00400000u)
1426 #define CSL_SRIO_RIO_SP_ERR_DET_CS_CRC_ERR_SHIFT (0x00000016u)
1427 #define CSL_SRIO_RIO_SP_ERR_DET_CS_CRC_ERR_RESETVAL (0x00000000u)
1429 #define CSL_SRIO_RIO_SP_ERR_DET_CS_ILL_ID_MASK (0x00200000u)
1430 #define CSL_SRIO_RIO_SP_ERR_DET_CS_ILL_ID_SHIFT (0x00000015u)
1431 #define CSL_SRIO_RIO_SP_ERR_DET_CS_ILL_ID_RESETVAL (0x00000000u)
1433 #define CSL_SRIO_RIO_SP_ERR_DET_CS_NOT_ACC_MASK (0x00100000u)
1434 #define CSL_SRIO_RIO_SP_ERR_DET_CS_NOT_ACC_SHIFT (0x00000014u)
1435 #define CSL_SRIO_RIO_SP_ERR_DET_CS_NOT_ACC_RESETVAL (0x00000000u)
1437 #define CSL_SRIO_RIO_SP_ERR_DET_PKT_ILL_ACKID_MASK (0x00080000u)
1438 #define CSL_SRIO_RIO_SP_ERR_DET_PKT_ILL_ACKID_SHIFT (0x00000013u)
1439 #define CSL_SRIO_RIO_SP_ERR_DET_PKT_ILL_ACKID_RESETVAL (0x00000000u)
1441 #define CSL_SRIO_RIO_SP_ERR_DET_PKT_CRC_ERR_MASK (0x00040000u)
1442 #define CSL_SRIO_RIO_SP_ERR_DET_PKT_CRC_ERR_SHIFT (0x00000012u)
1443 #define CSL_SRIO_RIO_SP_ERR_DET_PKT_CRC_ERR_RESETVAL (0x00000000u)
1445 #define CSL_SRIO_RIO_SP_ERR_DET_PKT_ILL_SIZE_MASK (0x00020000u)
1446 #define CSL_SRIO_RIO_SP_ERR_DET_PKT_ILL_SIZE_SHIFT (0x00000011u)
1447 #define CSL_SRIO_RIO_SP_ERR_DET_PKT_ILL_SIZE_RESETVAL (0x00000000u)
1449 #define CSL_SRIO_RIO_SP_ERR_DET_DSCRAM_LOS_MASK (0x00004000u)
1450 #define CSL_SRIO_RIO_SP_ERR_DET_DSCRAM_LOS_SHIFT (0x0000000Eu)
1451 #define CSL_SRIO_RIO_SP_ERR_DET_DSCRAM_LOS_RESETVAL (0x00000000u)
1453 #define CSL_SRIO_RIO_SP_ERR_DET_LR_ACKID_ILL_MASK (0x00000020u)
1454 #define CSL_SRIO_RIO_SP_ERR_DET_LR_ACKID_ILL_SHIFT (0x00000005u)
1455 #define CSL_SRIO_RIO_SP_ERR_DET_LR_ACKID_ILL_RESETVAL (0x00000000u)
1457 #define CSL_SRIO_RIO_SP_ERR_DET_PROT_ERR_MASK (0x00000010u)
1458 #define CSL_SRIO_RIO_SP_ERR_DET_PROT_ERR_SHIFT (0x00000004u)
1459 #define CSL_SRIO_RIO_SP_ERR_DET_PROT_ERR_RESETVAL (0x00000000u)
1461 #define CSL_SRIO_RIO_SP_ERR_DET_DELIN_ERR_MASK (0x00000004u)
1462 #define CSL_SRIO_RIO_SP_ERR_DET_DELIN_ERR_SHIFT (0x00000002u)
1463 #define CSL_SRIO_RIO_SP_ERR_DET_DELIN_ERR_RESETVAL (0x00000000u)
1465 #define CSL_SRIO_RIO_SP_ERR_DET_CS_ACK_ILL_MASK (0x00000002u)
1466 #define CSL_SRIO_RIO_SP_ERR_DET_CS_ACK_ILL_SHIFT (0x00000001u)
1467 #define CSL_SRIO_RIO_SP_ERR_DET_CS_ACK_ILL_RESETVAL (0x00000000u)
1469 #define CSL_SRIO_RIO_SP_ERR_DET_LINK_TO_MASK (0x00000001u)
1470 #define CSL_SRIO_RIO_SP_ERR_DET_LINK_TO_SHIFT (0x00000000u)
1471 #define CSL_SRIO_RIO_SP_ERR_DET_LINK_TO_RESETVAL (0x00000000u)
1473 #define CSL_SRIO_RIO_SP_ERR_DET_RESETVAL (0x00000000u)
1475 /* rio_sp_rate_en */
1477 #define CSL_SRIO_RIO_SP_RATE_EN_IMP_SPEC_EN_MASK (0x80000000u)
1478 #define CSL_SRIO_RIO_SP_RATE_EN_IMP_SPEC_EN_SHIFT (0x0000001Fu)
1479 #define CSL_SRIO_RIO_SP_RATE_EN_IMP_SPEC_EN_RESETVAL (0x00000000u)
1481 #define CSL_SRIO_RIO_SP_RATE_EN_CS_CRC_EN_MASK (0x00400000u)
1482 #define CSL_SRIO_RIO_SP_RATE_EN_CS_CRC_EN_SHIFT (0x00000016u)
1483 #define CSL_SRIO_RIO_SP_RATE_EN_CS_CRC_EN_RESETVAL (0x00000000u)
1485 #define CSL_SRIO_RIO_SP_RATE_EN_CS_ILL_ID_EN_MASK (0x00200000u)
1486 #define CSL_SRIO_RIO_SP_RATE_EN_CS_ILL_ID_EN_SHIFT (0x00000015u)
1487 #define CSL_SRIO_RIO_SP_RATE_EN_CS_ILL_ID_EN_RESETVAL (0x00000000u)
1489 #define CSL_SRIO_RIO_SP_RATE_EN_CS_NOT_ACC_EN_MASK (0x00100000u)
1490 #define CSL_SRIO_RIO_SP_RATE_EN_CS_NOT_ACC_EN_SHIFT (0x00000014u)
1491 #define CSL_SRIO_RIO_SP_RATE_EN_CS_NOT_ACC_EN_RESETVAL (0x00000000u)
1493 #define CSL_SRIO_RIO_SP_RATE_EN_PKT_ILL_ACKID_EN_MASK (0x00080000u)
1494 #define CSL_SRIO_RIO_SP_RATE_EN_PKT_ILL_ACKID_EN_SHIFT (0x00000013u)
1495 #define CSL_SRIO_RIO_SP_RATE_EN_PKT_ILL_ACKID_EN_RESETVAL (0x00000000u)
1497 #define CSL_SRIO_RIO_SP_RATE_EN_PKT_CRC_ERR_EN_MASK (0x00040000u)
1498 #define CSL_SRIO_RIO_SP_RATE_EN_PKT_CRC_ERR_EN_SHIFT (0x00000012u)
1499 #define CSL_SRIO_RIO_SP_RATE_EN_PKT_CRC_ERR_EN_RESETVAL (0x00000000u)
1501 #define CSL_SRIO_RIO_SP_RATE_EN_PKT_ILL_SIZE_EN_MASK (0x00020000u)
1502 #define CSL_SRIO_RIO_SP_RATE_EN_PKT_ILL_SIZE_EN_SHIFT (0x00000011u)
1503 #define CSL_SRIO_RIO_SP_RATE_EN_PKT_ILL_SIZE_EN_RESETVAL (0x00000000u)
1505 #define CSL_SRIO_RIO_SP_RATE_EN_DSCRAM_LOS_EN_MASK (0x00004000u)
1506 #define CSL_SRIO_RIO_SP_RATE_EN_DSCRAM_LOS_EN_SHIFT (0x0000000Eu)
1507 #define CSL_SRIO_RIO_SP_RATE_EN_DSCRAM_LOS_EN_RESETVAL (0x00000000u)
1509 #define CSL_SRIO_RIO_SP_RATE_EN_LR_ACKID_ILL_EN_MASK (0x00000020u)
1510 #define CSL_SRIO_RIO_SP_RATE_EN_LR_ACKID_ILL_EN_SHIFT (0x00000005u)
1511 #define CSL_SRIO_RIO_SP_RATE_EN_LR_ACKID_ILL_EN_RESETVAL (0x00000000u)
1513 #define CSL_SRIO_RIO_SP_RATE_EN_PROT_ERR_EN_MASK (0x00000010u)
1514 #define CSL_SRIO_RIO_SP_RATE_EN_PROT_ERR_EN_SHIFT (0x00000004u)
1515 #define CSL_SRIO_RIO_SP_RATE_EN_PROT_ERR_EN_RESETVAL (0x00000000u)
1517 #define CSL_SRIO_RIO_SP_RATE_EN_DELIN_ERR_EN_MASK (0x00000004u)
1518 #define CSL_SRIO_RIO_SP_RATE_EN_DELIN_ERR_EN_SHIFT (0x00000002u)
1519 #define CSL_SRIO_RIO_SP_RATE_EN_DELIN_ERR_EN_RESETVAL (0x00000000u)
1521 #define CSL_SRIO_RIO_SP_RATE_EN_CS_ACK_ILL_EN_MASK (0x00000002u)
1522 #define CSL_SRIO_RIO_SP_RATE_EN_CS_ACK_ILL_EN_SHIFT (0x00000001u)
1523 #define CSL_SRIO_RIO_SP_RATE_EN_CS_ACK_ILL_EN_RESETVAL (0x00000000u)
1525 #define CSL_SRIO_RIO_SP_RATE_EN_LINK_TO_EN_MASK (0x00000001u)
1526 #define CSL_SRIO_RIO_SP_RATE_EN_LINK_TO_EN_SHIFT (0x00000000u)
1527 #define CSL_SRIO_RIO_SP_RATE_EN_LINK_TO_EN_RESETVAL (0x00000000u)
1529 #define CSL_SRIO_RIO_SP_RATE_EN_RESETVAL (0x00000000u)
1531 /* rio_sp_err_attr_capt */
1533 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_INFO_TYPE_MASK (0xE0000000u)
1534 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_INFO_TYPE_SHIFT (0x0000001Du)
1535 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_INFO_TYPE_RESETVAL (0x00000000u)
1537 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_ERR_TYPE_MASK (0x1F000000u)
1538 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_ERR_TYPE_SHIFT (0x00000018u)
1539 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_ERR_TYPE_RESETVAL (0x00000000u)
1541 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_IMPL_DEP_MASK (0x00FFFFF0u)
1542 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_IMPL_DEP_SHIFT (0x00000004u)
1543 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_IMPL_DEP_RESETVAL (0x00000000u)
1545 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_VAL_CAPT_MASK (0x00000001u)
1546 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_VAL_CAPT_SHIFT (0x00000000u)
1547 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_VAL_CAPT_RESETVAL (0x00000000u)
1549 #define CSL_SRIO_RIO_SP_ERR_ATTR_CAPT_RESETVAL (0x00000000u)
1551 /* rio_sp_err_capt_0 */
1553 #define CSL_SRIO_RIO_SP_ERR_CAPT_0_CAPT_0_MASK (0xFFFFFFFFu)
1554 #define CSL_SRIO_RIO_SP_ERR_CAPT_0_CAPT_0_SHIFT (0x00000000u)
1555 #define CSL_SRIO_RIO_SP_ERR_CAPT_0_CAPT_0_RESETVAL (0x00000000u)
1557 #define CSL_SRIO_RIO_SP_ERR_CAPT_0_RESETVAL (0x00000000u)
1559 /* rio_sp_err_capt_1 */
1561 #define CSL_SRIO_RIO_SP_ERR_CAPT_1_CAPT_1_MASK (0xFFFFFFFFu)
1562 #define CSL_SRIO_RIO_SP_ERR_CAPT_1_CAPT_1_SHIFT (0x00000000u)
1563 #define CSL_SRIO_RIO_SP_ERR_CAPT_1_CAPT_1_RESETVAL (0x00000000u)
1565 #define CSL_SRIO_RIO_SP_ERR_CAPT_1_RESETVAL (0x00000000u)
1567 /* rio_sp_err_capt_2 */
1569 #define CSL_SRIO_RIO_SP_ERR_CAPT_2_CAPT_2_MASK (0xFFFFFFFFu)
1570 #define CSL_SRIO_RIO_SP_ERR_CAPT_2_CAPT_2_SHIFT (0x00000000u)
1571 #define CSL_SRIO_RIO_SP_ERR_CAPT_2_CAPT_2_RESETVAL (0x00000000u)
1573 #define CSL_SRIO_RIO_SP_ERR_CAPT_2_RESETVAL (0x00000000u)
1575 /* rio_sp_err_capt_3 */
1577 #define CSL_SRIO_RIO_SP_ERR_CAPT_3_CAPT_3_MASK (0xFFFFFFFFu)
1578 #define CSL_SRIO_RIO_SP_ERR_CAPT_3_CAPT_3_SHIFT (0x00000000u)
1579 #define CSL_SRIO_RIO_SP_ERR_CAPT_3_CAPT_3_RESETVAL (0x00000000u)
1581 #define CSL_SRIO_RIO_SP_ERR_CAPT_3_RESETVAL (0x00000000u)
1583 /* rio_sp_err_rate */
1585 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_RB_MASK (0xFF000000u)
1586 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_RB_SHIFT (0x00000018u)
1587 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_RB_RESETVAL (0x00000080u)
1589 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_RR_MASK (0x00030000u)
1590 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_RR_SHIFT (0x00000010u)
1591 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_RR_RESETVAL (0x00000000u)
1593 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_PEAK_MASK (0x0000FF00u)
1594 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_PEAK_SHIFT (0x00000008u)
1595 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_PEAK_RESETVAL (0x00000000u)
1597 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_RATE_CNT_MASK (0x000000FFu)
1598 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_RATE_CNT_SHIFT (0x00000000u)
1599 #define CSL_SRIO_RIO_SP_ERR_RATE_ERR_RATE_CNT_RESETVAL (0x00000000u)
1601 #define CSL_SRIO_RIO_SP_ERR_RATE_RESETVAL (0x80000000u)
1603 /* rio_sp_err_thresh */
1605 #define CSL_SRIO_RIO_SP_ERR_THRESH_ERR_RFT_MASK (0xFF000000u)
1606 #define CSL_SRIO_RIO_SP_ERR_THRESH_ERR_RFT_SHIFT (0x00000018u)
1607 #define CSL_SRIO_RIO_SP_ERR_THRESH_ERR_RFT_RESETVAL (0x000000FFu)
1609 #define CSL_SRIO_RIO_SP_ERR_THRESH_ERR_RDT_MASK (0x00FF0000u)
1610 #define CSL_SRIO_RIO_SP_ERR_THRESH_ERR_RDT_SHIFT (0x00000010u)
1611 #define CSL_SRIO_RIO_SP_ERR_THRESH_ERR_RDT_RESETVAL (0x000000FFu)
1613 #define CSL_SRIO_RIO_SP_ERR_THRESH_RESETVAL (0xFFFF0000u)
1615 /* rio_lane_stat0 */
1617 #define CSL_SRIO_RIO_LANE_STAT0_PORT_NUM_MASK (0xFF000000u)
1618 #define CSL_SRIO_RIO_LANE_STAT0_PORT_NUM_SHIFT (0x00000018u)
1619 #define CSL_SRIO_RIO_LANE_STAT0_PORT_NUM_RESETVAL (0x00000000u)
1621 #define CSL_SRIO_RIO_LANE_STAT0_LANE_NUM_MASK (0x00F00000u)
1622 #define CSL_SRIO_RIO_LANE_STAT0_LANE_NUM_SHIFT (0x00000014u)
1623 #define CSL_SRIO_RIO_LANE_STAT0_LANE_NUM_RESETVAL (0x00000000u)
1625 #define CSL_SRIO_RIO_LANE_STAT0_TX_TYPE_MASK (0x00080000u)
1626 #define CSL_SRIO_RIO_LANE_STAT0_TX_TYPE_SHIFT (0x00000013u)
1627 #define CSL_SRIO_RIO_LANE_STAT0_TX_TYPE_RESETVAL (0x00000000u)
1629 #define CSL_SRIO_RIO_LANE_STAT0_TX_MODE_MASK (0x00040000u)
1630 #define CSL_SRIO_RIO_LANE_STAT0_TX_MODE_SHIFT (0x00000012u)
1631 #define CSL_SRIO_RIO_LANE_STAT0_TX_MODE_RESETVAL (0x00000000u)
1633 #define CSL_SRIO_RIO_LANE_STAT0_RX_TYPE_MASK (0x00030000u)
1634 #define CSL_SRIO_RIO_LANE_STAT0_RX_TYPE_SHIFT (0x00000010u)
1635 #define CSL_SRIO_RIO_LANE_STAT0_RX_TYPE_RESETVAL (0x00000000u)
1637 #define CSL_SRIO_RIO_LANE_STAT0_RX_INV_MASK (0x00008000u)
1638 #define CSL_SRIO_RIO_LANE_STAT0_RX_INV_SHIFT (0x0000000Fu)
1639 #define CSL_SRIO_RIO_LANE_STAT0_RX_INV_RESETVAL (0x00000000u)
1641 #define CSL_SRIO_RIO_LANE_STAT0_RX_TRN_MASK (0x00004000u)
1642 #define CSL_SRIO_RIO_LANE_STAT0_RX_TRN_SHIFT (0x0000000Eu)
1643 #define CSL_SRIO_RIO_LANE_STAT0_RX_TRN_RESETVAL (0x00000001u)
1645 #define CSL_SRIO_RIO_LANE_STAT0_RX_SYNC_MASK (0x00002000u)
1646 #define CSL_SRIO_RIO_LANE_STAT0_RX_SYNC_SHIFT (0x0000000Du)
1647 #define CSL_SRIO_RIO_LANE_STAT0_RX_SYNC_RESETVAL (0x00000000u)
1649 #define CSL_SRIO_RIO_LANE_STAT0_RX_RDY_MASK (0x00001000u)
1650 #define CSL_SRIO_RIO_LANE_STAT0_RX_RDY_SHIFT (0x0000000Cu)
1651 #define CSL_SRIO_RIO_LANE_STAT0_RX_RDY_RESETVAL (0x00000000u)
1653 #define CSL_SRIO_RIO_LANE_STAT0_ERR_CNT_MASK (0x00000F00u)
1654 #define CSL_SRIO_RIO_LANE_STAT0_ERR_CNT_SHIFT (0x00000008u)
1655 #define CSL_SRIO_RIO_LANE_STAT0_ERR_CNT_RESETVAL (0x00000000u)
1657 #define CSL_SRIO_RIO_LANE_STAT0_CHG_SYNC_MASK (0x00000080u)
1658 #define CSL_SRIO_RIO_LANE_STAT0_CHG_SYNC_SHIFT (0x00000007u)
1659 #define CSL_SRIO_RIO_LANE_STAT0_CHG_SYNC_RESETVAL (0x00000000u)
1661 #define CSL_SRIO_RIO_LANE_STAT0_CHG_TRN_MASK (0x00000040u)
1662 #define CSL_SRIO_RIO_LANE_STAT0_CHG_TRN_SHIFT (0x00000006u)
1663 #define CSL_SRIO_RIO_LANE_STAT0_CHG_TRN_RESETVAL (0x00000000u)
1665 #define CSL_SRIO_RIO_LANE_STAT0_STAT1_MASK (0x00000008u)
1666 #define CSL_SRIO_RIO_LANE_STAT0_STAT1_SHIFT (0x00000003u)
1667 #define CSL_SRIO_RIO_LANE_STAT0_STAT1_RESETVAL (0x00000001u)
1669 #define CSL_SRIO_RIO_LANE_STAT0_STAT2_7_MASK (0x00000007u)
1670 #define CSL_SRIO_RIO_LANE_STAT0_STAT2_7_SHIFT (0x00000000u)
1671 #define CSL_SRIO_RIO_LANE_STAT0_STAT2_7_RESETVAL (0x00000000u)
1673 #define CSL_SRIO_RIO_LANE_STAT0_RESETVAL (0x00004008u)
1675 /* rio_lane_stat1 */
1677 #define CSL_SRIO_RIO_LANE_STAT1_IDLE2_MASK (0x80000000u)
1678 #define CSL_SRIO_RIO_LANE_STAT1_IDLE2_SHIFT (0x0000001Fu)
1679 #define CSL_SRIO_RIO_LANE_STAT1_IDLE2_RESETVAL (0x00000000u)
1681 #define CSL_SRIO_RIO_LANE_STAT1_INFO_OK_MASK (0x40000000u)
1682 #define CSL_SRIO_RIO_LANE_STAT1_INFO_OK_SHIFT (0x0000001Eu)
1683 #define CSL_SRIO_RIO_LANE_STAT1_INFO_OK_RESETVAL (0x00000000u)
1685 #define CSL_SRIO_RIO_LANE_STAT1_CHG_MASK (0x20000000u)
1686 #define CSL_SRIO_RIO_LANE_STAT1_CHG_SHIFT (0x0000001Du)
1687 #define CSL_SRIO_RIO_LANE_STAT1_CHG_RESETVAL (0x00000000u)
1689 #define CSL_SRIO_RIO_LANE_STAT1_IMPL_SPEC_MASK (0x10000000u)
1690 #define CSL_SRIO_RIO_LANE_STAT1_IMPL_SPEC_SHIFT (0x0000001Cu)
1691 #define CSL_SRIO_RIO_LANE_STAT1_IMPL_SPEC_RESETVAL (0x00000000u)
1693 #define CSL_SRIO_RIO_LANE_STAT1_LP_RX_TRN_MASK (0x08000000u)
1694 #define CSL_SRIO_RIO_LANE_STAT1_LP_RX_TRN_SHIFT (0x0000001Bu)
1695 #define CSL_SRIO_RIO_LANE_STAT1_LP_RX_TRN_RESETVAL (0x00000000u)
1697 #define CSL_SRIO_RIO_LANE_STAT1_LP_WIDTH_MASK (0x07000000u)
1698 #define CSL_SRIO_RIO_LANE_STAT1_LP_WIDTH_SHIFT (0x00000018u)
1699 #define CSL_SRIO_RIO_LANE_STAT1_LP_WIDTH_RESETVAL (0x00000000u)
1701 #define CSL_SRIO_RIO_LANE_STAT1_LP_LANE_NUM_MASK (0x00F00000u)
1702 #define CSL_SRIO_RIO_LANE_STAT1_LP_LANE_NUM_SHIFT (0x00000014u)
1703 #define CSL_SRIO_RIO_LANE_STAT1_LP_LANE_NUM_RESETVAL (0x00000000u)
1705 #define CSL_SRIO_RIO_LANE_STAT1_LP_TAP_M1_MASK (0x000C0000u)
1706 #define CSL_SRIO_RIO_LANE_STAT1_LP_TAP_M1_SHIFT (0x00000012u)
1707 #define CSL_SRIO_RIO_LANE_STAT1_LP_TAP_M1_RESETVAL (0x00000000u)
1709 #define CSL_SRIO_RIO_LANE_STAT1_LP_TAP_P1_MASK (0x00030000u)
1710 #define CSL_SRIO_RIO_LANE_STAT1_LP_TAP_P1_SHIFT (0x00000010u)
1711 #define CSL_SRIO_RIO_LANE_STAT1_LP_TAP_P1_RESETVAL (0x00000000u)
1713 #define CSL_SRIO_RIO_LANE_STAT1_LP_SCRM_MASK (0x00008000u)
1714 #define CSL_SRIO_RIO_LANE_STAT1_LP_SCRM_SHIFT (0x0000000Fu)
1715 #define CSL_SRIO_RIO_LANE_STAT1_LP_SCRM_RESETVAL (0x00000000u)
1717 #define CSL_SRIO_RIO_LANE_STAT1_RESETVAL (0x00000000u)
1719 /* rio_plm_sp_imp_spec_ctl */
1721 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_PAYL_CAP_MASK (0x80000000u)
1722 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_PAYL_CAP_SHIFT (0x0000001Fu)
1723 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_PAYL_CAP_RESETVAL (0x00000000u)
1725 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_USE_IDLE2_MASK (0x40000000u)
1726 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_USE_IDLE2_SHIFT (0x0000001Eu)
1727 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_USE_IDLE2_RESETVAL (0x00000000u)
1729 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_USE_IDLE1_MASK (0x20000000u)
1730 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_USE_IDLE1_SHIFT (0x0000001Du)
1731 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_USE_IDLE1_RESETVAL (0x00000000u)
1733 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_DLB_EN_MASK (0x10000000u)
1734 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_DLB_EN_SHIFT (0x0000001Cu)
1735 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_DLB_EN_RESETVAL (0x00000000u)
1737 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_FORCE_REINIT_MASK (0x04000000u)
1738 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_FORCE_REINIT_SHIFT (0x0000001Au)
1739 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_FORCE_REINIT_RESETVAL (0x00000000u)
1741 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SOFT_RST_PORT_MASK (0x02000000u)
1742 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SOFT_RST_PORT_SHIFT (0x00000019u)
1743 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SOFT_RST_PORT_RESETVAL (0x00000000u)
1745 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_TX_BYPASS_MASK (0x01000000u)
1746 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_TX_BYPASS_SHIFT (0x00000018u)
1747 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_TX_BYPASS_RESETVAL (0x00000000u)
1749 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_LLB_EN_MASK (0x00800000u)
1750 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_LLB_EN_SHIFT (0x00000017u)
1751 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_LLB_EN_RESETVAL (0x00000000u)
1753 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_PORT_SELF_RST_MASK (0x00200000u)
1754 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_PORT_SELF_RST_SHIFT (0x00000015u)
1755 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_PORT_SELF_RST_RESETVAL (0x00000000u)
1757 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SELF_RST_MASK (0x00100000u)
1758 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SELF_RST_SHIFT (0x00000014u)
1759 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SELF_RST_RESETVAL (0x00000000u)
1761 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SWAP_TX_MASK (0x000C0000u)
1762 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SWAP_TX_SHIFT (0x00000012u)
1763 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SWAP_TX_RESETVAL (0x00000000u)
1765 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SWAP_RX_MASK (0x00030000u)
1766 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SWAP_RX_SHIFT (0x00000010u)
1767 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_SWAP_RX_RESETVAL (0x00000000u)
1769 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_DLT_THRESH_MASK (0x0000FFFFu)
1770 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_DLT_THRESH_SHIFT (0x00000000u)
1771 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_DLT_THRESH_RESETVAL (0x00000000u)
1773 #define CSL_SRIO_RIO_PLM_SP_IMP_SPEC_CTL_RESETVAL (0x00000000u)
1775 /* rio_plm_sp_pwdn_ctl */
1777 #define CSL_SRIO_RIO_PLM_SP_PWDN_CTL_PWDN_PORT_MASK (0x00000001u)
1778 #define CSL_SRIO_RIO_PLM_SP_PWDN_CTL_PWDN_PORT_SHIFT (0x00000000u)
1779 #define CSL_SRIO_RIO_PLM_SP_PWDN_CTL_PWDN_PORT_RESETVAL (0x00000000u)
1781 #define CSL_SRIO_RIO_PLM_SP_PWDN_CTL_RESETVAL (0x00000000u)
1783 /* rio_plm_sp_status */
1785 #define CSL_SRIO_RIO_PLM_SP_STATUS_MAX_DENIAL_MASK (0x80000000u)
1786 #define CSL_SRIO_RIO_PLM_SP_STATUS_MAX_DENIAL_SHIFT (0x0000001Fu)
1787 #define CSL_SRIO_RIO_PLM_SP_STATUS_MAX_DENIAL_RESETVAL (0x00000000u)
1789 #define CSL_SRIO_RIO_PLM_SP_STATUS_LINK_INIT_MASK (0x10000000u)
1790 #define CSL_SRIO_RIO_PLM_SP_STATUS_LINK_INIT_SHIFT (0x0000001Cu)
1791 #define CSL_SRIO_RIO_PLM_SP_STATUS_LINK_INIT_RESETVAL (0x00000000u)
1793 #define CSL_SRIO_RIO_PLM_SP_STATUS_DLT_MASK (0x08000000u)
1794 #define CSL_SRIO_RIO_PLM_SP_STATUS_DLT_SHIFT (0x0000001Bu)
1795 #define CSL_SRIO_RIO_PLM_SP_STATUS_DLT_RESETVAL (0x00000000u)
1797 #define CSL_SRIO_RIO_PLM_SP_STATUS_PORT_ERR_MASK (0x04000000u)
1798 #define CSL_SRIO_RIO_PLM_SP_STATUS_PORT_ERR_SHIFT (0x0000001Au)
1799 #define CSL_SRIO_RIO_PLM_SP_STATUS_PORT_ERR_RESETVAL (0x00000000u)
1801 #define CSL_SRIO_RIO_PLM_SP_STATUS_OUTPUT_FAIL_MASK (0x02000000u)
1802 #define CSL_SRIO_RIO_PLM_SP_STATUS_OUTPUT_FAIL_SHIFT (0x00000019u)
1803 #define CSL_SRIO_RIO_PLM_SP_STATUS_OUTPUT_FAIL_RESETVAL (0x00000000u)
1805 #define CSL_SRIO_RIO_PLM_SP_STATUS_OUTPUT_DEGR_MASK (0x01000000u)
1806 #define CSL_SRIO_RIO_PLM_SP_STATUS_OUTPUT_DEGR_SHIFT (0x00000018u)
1807 #define CSL_SRIO_RIO_PLM_SP_STATUS_OUTPUT_DEGR_RESETVAL (0x00000000u)
1809 #define CSL_SRIO_RIO_PLM_SP_STATUS_RST_REQ_MASK (0x00010000u)
1810 #define CSL_SRIO_RIO_PLM_SP_STATUS_RST_REQ_SHIFT (0x00000010u)
1811 #define CSL_SRIO_RIO_PLM_SP_STATUS_RST_REQ_RESETVAL (0x00000000u)
1813 #define CSL_SRIO_RIO_PLM_SP_STATUS_PBM_PW_MASK (0x00008000u)
1814 #define CSL_SRIO_RIO_PLM_SP_STATUS_PBM_PW_SHIFT (0x0000000Fu)
1815 #define CSL_SRIO_RIO_PLM_SP_STATUS_PBM_PW_RESETVAL (0x00000000u)
1817 #define CSL_SRIO_RIO_PLM_SP_STATUS_TLM_PW_MASK (0x00004000u)
1818 #define CSL_SRIO_RIO_PLM_SP_STATUS_TLM_PW_SHIFT (0x0000000Eu)
1819 #define CSL_SRIO_RIO_PLM_SP_STATUS_TLM_PW_RESETVAL (0x00000000u)
1821 #define CSL_SRIO_RIO_PLM_SP_STATUS_MECS_MASK (0x00001000u)
1822 #define CSL_SRIO_RIO_PLM_SP_STATUS_MECS_SHIFT (0x0000000Cu)
1823 #define CSL_SRIO_RIO_PLM_SP_STATUS_MECS_RESETVAL (0x00000000u)
1825 #define CSL_SRIO_RIO_PLM_SP_STATUS_PBM_INT_MASK (0x00000800u)
1826 #define CSL_SRIO_RIO_PLM_SP_STATUS_PBM_INT_SHIFT (0x0000000Bu)
1827 #define CSL_SRIO_RIO_PLM_SP_STATUS_PBM_INT_RESETVAL (0x00000000u)
1829 #define CSL_SRIO_RIO_PLM_SP_STATUS_TLM_INT_MASK (0x00000400u)
1830 #define CSL_SRIO_RIO_PLM_SP_STATUS_TLM_INT_SHIFT (0x0000000Au)
1831 #define CSL_SRIO_RIO_PLM_SP_STATUS_TLM_INT_RESETVAL (0x00000000u)
1833 #define CSL_SRIO_RIO_PLM_SP_STATUS_RESETVAL (0x00000000u)
1835 /* rio_plm_sp_int_enable */
1837 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_MAX_DENIAL_MASK (0x80000000u)
1838 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_MAX_DENIAL_SHIFT (0x0000001Fu)
1839 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_MAX_DENIAL_RESETVAL (0x00000000u)
1841 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_LINK_INIT_MASK (0x10000000u)
1842 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_LINK_INIT_SHIFT (0x0000001Cu)
1843 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_LINK_INIT_RESETVAL (0x00000000u)
1845 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_DLT_MASK (0x08000000u)
1846 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_DLT_SHIFT (0x0000001Bu)
1847 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_DLT_RESETVAL (0x00000000u)
1849 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_PORT_ERR_MASK (0x04000000u)
1850 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_PORT_ERR_SHIFT (0x0000001Au)
1851 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_PORT_ERR_RESETVAL (0x00000000u)
1853 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_OUTPUT_FAIL_MASK (0x02000000u)
1854 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_OUTPUT_FAIL_SHIFT (0x00000019u)
1855 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_OUTPUT_FAIL_RESETVAL (0x00000000u)
1857 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_OUTPUT_DEGR_MASK (0x01000000u)
1858 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_OUTPUT_DEGR_SHIFT (0x00000018u)
1859 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_OUTPUT_DEGR_RESETVAL (0x00000000u)
1861 #define CSL_SRIO_RIO_PLM_SP_INT_ENABLE_RESETVAL (0x00000000u)
1863 /* rio_plm_sp_pw_enable */
1865 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_MAX_DENIAL_MASK (0x80000000u)
1866 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_MAX_DENIAL_SHIFT (0x0000001Fu)
1867 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_MAX_DENIAL_RESETVAL (0x00000000u)
1869 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_LINK_INIT_MASK (0x10000000u)
1870 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_LINK_INIT_SHIFT (0x0000001Cu)
1871 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_LINK_INIT_RESETVAL (0x00000000u)
1873 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_DLT_MASK (0x08000000u)
1874 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_DLT_SHIFT (0x0000001Bu)
1875 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_DLT_RESETVAL (0x00000000u)
1877 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_PORT_ERR_MASK (0x04000000u)
1878 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_PORT_ERR_SHIFT (0x0000001Au)
1879 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_PORT_ERR_RESETVAL (0x00000000u)
1881 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_OUTPUT_FAIL_MASK (0x02000000u)
1882 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_OUTPUT_FAIL_SHIFT (0x00000019u)
1883 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_OUTPUT_FAIL_RESETVAL (0x00000000u)
1885 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_OUTPUT_DEGR_MASK (0x01000000u)
1886 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_OUTPUT_DEGR_SHIFT (0x00000018u)
1887 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_OUTPUT_DEGR_RESETVAL (0x00000000u)
1889 #define CSL_SRIO_RIO_PLM_SP_PW_ENABLE_RESETVAL (0x00000000u)
1891 /* rio_plm_sp_event_gen */
1893 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_MAX_DENIAL_MASK (0x80000000u)
1894 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_MAX_DENIAL_SHIFT (0x0000001Fu)
1895 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_MAX_DENIAL_RESETVAL (0x00000000u)
1897 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_LINK_INIT_MASK (0x10000000u)
1898 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_LINK_INIT_SHIFT (0x0000001Cu)
1899 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_LINK_INIT_RESETVAL (0x00000000u)
1901 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_DLT_MASK (0x08000000u)
1902 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_DLT_SHIFT (0x0000001Bu)
1903 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_DLT_RESETVAL (0x00000000u)
1905 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_PORT_ERR_MASK (0x04000000u)
1906 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_PORT_ERR_SHIFT (0x0000001Au)
1907 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_PORT_ERR_RESETVAL (0x00000000u)
1909 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_OUTPUT_FAIL_MASK (0x02000000u)
1910 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_OUTPUT_FAIL_SHIFT (0x00000019u)
1911 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_OUTPUT_FAIL_RESETVAL (0x00000000u)
1913 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_OUTPUT_DEGR_MASK (0x01000000u)
1914 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_OUTPUT_DEGR_SHIFT (0x00000018u)
1915 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_OUTPUT_DEGR_RESETVAL (0x00000000u)
1917 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_RST_REQ_MASK (0x00010000u)
1918 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_RST_REQ_SHIFT (0x00000010u)
1919 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_RST_REQ_RESETVAL (0x00000000u)
1921 #define CSL_SRIO_RIO_PLM_SP_EVENT_GEN_RESETVAL (0x00000000u)
1923 /* rio_plm_sp_all_int_en */
1925 #define CSL_SRIO_RIO_PLM_SP_ALL_INT_EN_IRQ_EN_MASK (0x00000001u)
1926 #define CSL_SRIO_RIO_PLM_SP_ALL_INT_EN_IRQ_EN_SHIFT (0x00000000u)
1927 #define CSL_SRIO_RIO_PLM_SP_ALL_INT_EN_IRQ_EN_RESETVAL (0x00000000u)
1929 #define CSL_SRIO_RIO_PLM_SP_ALL_INT_EN_RESETVAL (0x00000000u)
1931 /* rio_plm_sp_all_pw_en */
1933 #define CSL_SRIO_RIO_PLM_SP_ALL_PW_EN_PW_EN_MASK (0x00000001u)
1934 #define CSL_SRIO_RIO_PLM_SP_ALL_PW_EN_PW_EN_SHIFT (0x00000000u)
1935 #define CSL_SRIO_RIO_PLM_SP_ALL_PW_EN_PW_EN_RESETVAL (0x00000001u)
1937 #define CSL_SRIO_RIO_PLM_SP_ALL_PW_EN_RESETVAL (0x00000001u)
1939 /* rio_plm_sp_path_ctl */
1941 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_PATH_ID_MASK (0x001F0000u)
1942 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_PATH_ID_SHIFT (0x00000010u)
1943 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_PATH_ID_RESETVAL (0x00000000u)
1945 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_PATH_CONFIGURATION_MASK (0x00000700u)
1946 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_PATH_CONFIGURATION_SHIFT (0x00000008u)
1947 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_PATH_CONFIGURATION_RESETVAL (0x00000000u)
1949 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_PATH_MODE_MASK (0x00000007u)
1950 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_PATH_MODE_SHIFT (0x00000000u)
1951 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_PATH_MODE_RESETVAL (0x00000000u)
1953 #define CSL_SRIO_RIO_PLM_SP_PATH_CTL_RESETVAL (0x00000000u)
1955 /* rio_plm_sp_discovery_timer */
1957 #define CSL_SRIO_RIO_PLM_SP_DISCOVERY_TIMER_DISCOVERY_TIMER_MASK (0xF0000000u)
1958 #define CSL_SRIO_RIO_PLM_SP_DISCOVERY_TIMER_DISCOVERY_TIMER_SHIFT (0x0000001Cu)
1959 #define CSL_SRIO_RIO_PLM_SP_DISCOVERY_TIMER_DISCOVERY_TIMER_RESETVAL (0x00000007u)
1961 #define CSL_SRIO_RIO_PLM_SP_DISCOVERY_TIMER_RESETVAL (0x70000000u)
1963 /* rio_plm_sp_silence_timer */
1965 #define CSL_SRIO_RIO_PLM_SP_SILENCE_TIMER_SILENCE_TIMER_MASK (0xF0000000u)
1966 #define CSL_SRIO_RIO_PLM_SP_SILENCE_TIMER_SILENCE_TIMER_SHIFT (0x0000001Cu)
1967 #define CSL_SRIO_RIO_PLM_SP_SILENCE_TIMER_SILENCE_TIMER_RESETVAL (0x00000009u)
1969 #define CSL_SRIO_RIO_PLM_SP_SILENCE_TIMER_RESETVAL (0x90000000u)
1971 /* rio_plm_sp_vmin_exp */
1973 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_VMIN_EXP_MASK (0x1F000000u)
1974 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_VMIN_EXP_SHIFT (0x00000018u)
1975 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_VMIN_EXP_RESETVAL (0x00000000u)
1977 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_IMAX_MASK (0x000F0000u)
1978 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_IMAX_SHIFT (0x00000010u)
1979 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_IMAX_RESETVAL (0x00000003u)
1981 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_MMAX_MASK (0x00000F00u)
1982 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_MMAX_SHIFT (0x00000008u)
1983 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_MMAX_RESETVAL (0x00000003u)
1985 #define CSL_SRIO_RIO_PLM_SP_VMIN_EXP_RESETVAL (0x00030300u)
1987 /* rio_plm_sp_pol_ctl */
1989 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX3_POL_MASK (0x00080000u)
1990 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX3_POL_SHIFT (0x00000013u)
1991 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX3_POL_RESETVAL (0x00000000u)
1993 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX2_POL_MASK (0x00040000u)
1994 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX2_POL_SHIFT (0x00000012u)
1995 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX2_POL_RESETVAL (0x00000000u)
1997 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX1_POL_MASK (0x00020000u)
1998 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX1_POL_SHIFT (0x00000011u)
1999 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX1_POL_RESETVAL (0x00000000u)
2001 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX0_POL_MASK (0x00010000u)
2002 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX0_POL_SHIFT (0x00000010u)
2003 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_TX0_POL_RESETVAL (0x00000000u)
2005 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX3_POL_MASK (0x00000008u)
2006 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX3_POL_SHIFT (0x00000003u)
2007 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX3_POL_RESETVAL (0x00000000u)
2009 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX2_POL_MASK (0x00000004u)
2010 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX2_POL_SHIFT (0x00000002u)
2011 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX2_POL_RESETVAL (0x00000000u)
2013 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX1_POL_MASK (0x00000002u)
2014 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX1_POL_SHIFT (0x00000001u)
2015 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX1_POL_RESETVAL (0x00000000u)
2017 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX0_POL_MASK (0x00000001u)
2018 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX0_POL_SHIFT (0x00000000u)
2019 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RX0_POL_RESETVAL (0x00000000u)
2021 #define CSL_SRIO_RIO_PLM_SP_POL_CTL_RESETVAL (0x00000000u)
2023 /* rio_plm_sp_denial_ctl */
2025 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_CNT_PNA_MASK (0x20000000u)
2026 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_CNT_PNA_SHIFT (0x0000001Du)
2027 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_CNT_PNA_RESETVAL (0x00000001u)
2029 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_CNT_RTY_MASK (0x10000000u)
2030 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_CNT_RTY_SHIFT (0x0000001Cu)
2031 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_CNT_RTY_RESETVAL (0x00000001u)
2033 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_DENIAL_THRESH_MASK (0x000000FFu)
2034 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_DENIAL_THRESH_SHIFT (0x00000000u)
2035 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_DENIAL_THRESH_RESETVAL (0x00000000u)
2037 #define CSL_SRIO_RIO_PLM_SP_DENIAL_CTL_RESETVAL (0x30000000u)
2039 /* rio_plm_sp_rcvd_mecs */
2041 #define CSL_SRIO_RIO_PLM_SP_RCVD_MECS_CMD_STAT_MASK (0x000000FFu)
2042 #define CSL_SRIO_RIO_PLM_SP_RCVD_MECS_CMD_STAT_SHIFT (0x00000000u)
2043 #define CSL_SRIO_RIO_PLM_SP_RCVD_MECS_CMD_STAT_RESETVAL (0x00000000u)
2045 #define CSL_SRIO_RIO_PLM_SP_RCVD_MECS_RESETVAL (0x00000000u)
2047 /* rio_plm_sp_mecs_fwd */
2049 #define CSL_SRIO_RIO_PLM_SP_MECS_FWD_SUBSCRIPTION_MASK (0x000000FEu)
2050 #define CSL_SRIO_RIO_PLM_SP_MECS_FWD_SUBSCRIPTION_SHIFT (0x00000001u)
2051 #define CSL_SRIO_RIO_PLM_SP_MECS_FWD_SUBSCRIPTION_RESETVAL (0x00000000u)
2053 #define CSL_SRIO_RIO_PLM_SP_MECS_FWD_MULT_CS_MASK (0x00000001u)
2054 #define CSL_SRIO_RIO_PLM_SP_MECS_FWD_MULT_CS_SHIFT (0x00000000u)
2055 #define CSL_SRIO_RIO_PLM_SP_MECS_FWD_MULT_CS_RESETVAL (0x00000000u)
2057 #define CSL_SRIO_RIO_PLM_SP_MECS_FWD_RESETVAL (0x00000000u)
2059 /* rio_plm_sp_long_cs_tx1 */
2061 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_STYPE_0_MASK (0x70000000u)
2062 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_STYPE_0_SHIFT (0x0000001Cu)
2063 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_STYPE_0_RESETVAL (0x00000000u)
2065 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_PAR_0_MASK (0x03F00000u)
2066 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_PAR_0_SHIFT (0x00000014u)
2067 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_PAR_0_RESETVAL (0x00000000u)
2069 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_PAR_1_MASK (0x0003F000u)
2070 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_PAR_1_SHIFT (0x0000000Cu)
2071 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_PAR_1_RESETVAL (0x00000000u)
2073 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_CS_EMB_MASK (0x00000100u)
2074 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_CS_EMB_SHIFT (0x00000008u)
2075 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_CS_EMB_RESETVAL (0x00000000u)
2077 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_STYPE_1_MASK (0x00000070u)
2078 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_STYPE_1_SHIFT (0x00000004u)
2079 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_STYPE_1_RESETVAL (0x00000000u)
2081 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_CMD_MASK (0x00000007u)
2082 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_CMD_SHIFT (0x00000000u)
2083 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_CMD_RESETVAL (0x00000000u)
2085 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX1_RESETVAL (0x00000000u)
2087 /* rio_plm_sp_long_cs_tx2 */
2089 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX2_STYPE_2_MASK (0x70000000u)
2090 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX2_STYPE_2_SHIFT (0x0000001Cu)
2091 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX2_STYPE_2_RESETVAL (0x00000000u)
2093 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX2_PARM_MASK (0x07FF0000u)
2094 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX2_PARM_SHIFT (0x00000010u)
2095 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX2_PARM_RESETVAL (0x00000000u)
2097 #define CSL_SRIO_RIO_PLM_SP_LONG_CS_TX2_RESETVAL (0x00000000u)
2099 /* rio_tlm_sp_control */
2101 #define CSL_SRIO_RIO_TLM_SP_CONTROL_PORTGROUP_SELECT_MASK (0x40000000u)
2102 #define CSL_SRIO_RIO_TLM_SP_CONTROL_PORTGROUP_SELECT_SHIFT (0x0000001Eu)
2103 #define CSL_SRIO_RIO_TLM_SP_CONTROL_PORTGROUP_SELECT_RESETVAL (0x00000000u)
2105 #define CSL_SRIO_RIO_TLM_SP_CONTROL_VOQ_SELECT_MASK (0x30000000u)
2106 #define CSL_SRIO_RIO_TLM_SP_CONTROL_VOQ_SELECT_SHIFT (0x0000001Cu)
2107 #define CSL_SRIO_RIO_TLM_SP_CONTROL_VOQ_SELECT_RESETVAL (0x00000000u)
2109 #define CSL_SRIO_RIO_TLM_SP_CONTROL_TGT_ID_DIS_MASK (0x00200000u)
2110 #define CSL_SRIO_RIO_TLM_SP_CONTROL_TGT_ID_DIS_SHIFT (0x00000015u)
2111 #define CSL_SRIO_RIO_TLM_SP_CONTROL_TGT_ID_DIS_RESETVAL (0x00000000u)
2113 #define CSL_SRIO_RIO_TLM_SP_CONTROL_MTC_TGT_ID_DIS_MASK (0x00100000u)
2114 #define CSL_SRIO_RIO_TLM_SP_CONTROL_MTC_TGT_ID_DIS_SHIFT (0x00000014u)
2115 #define CSL_SRIO_RIO_TLM_SP_CONTROL_MTC_TGT_ID_DIS_RESETVAL (0x00000000u)
2117 #define CSL_SRIO_RIO_TLM_SP_CONTROL_LENGTH_MASK (0x0000F000u)
2118 #define CSL_SRIO_RIO_TLM_SP_CONTROL_LENGTH_SHIFT (0x0000000Cu)
2119 #define CSL_SRIO_RIO_TLM_SP_CONTROL_LENGTH_RESETVAL (0x00000009u)
2121 #define CSL_SRIO_RIO_TLM_SP_CONTROL_RESETVAL (0x00009000u)
2123 /* rio_tlm_sp_status */
2125 #define CSL_SRIO_RIO_TLM_SP_STATUS_IG_BAD_VC_MASK (0x80000000u)
2126 #define CSL_SRIO_RIO_TLM_SP_STATUS_IG_BAD_VC_SHIFT (0x0000001Fu)
2127 #define CSL_SRIO_RIO_TLM_SP_STATUS_IG_BAD_VC_RESETVAL (0x00000000u)
2129 #define CSL_SRIO_RIO_TLM_SP_STATUS_IG_BRR_FILTER_MASK (0x00100000u)
2130 #define CSL_SRIO_RIO_TLM_SP_STATUS_IG_BRR_FILTER_SHIFT (0x00000014u)
2131 #define CSL_SRIO_RIO_TLM_SP_STATUS_IG_BRR_FILTER_RESETVAL (0x00000000u)
2133 #define CSL_SRIO_RIO_TLM_SP_STATUS_RESETVAL (0x00000000u)
2135 /* rio_tlm_sp_int_enable */
2137 #define CSL_SRIO_RIO_TLM_SP_INT_ENABLE_IG_BAD_VC_MASK (0x80000000u)
2138 #define CSL_SRIO_RIO_TLM_SP_INT_ENABLE_IG_BAD_VC_SHIFT (0x0000001Fu)
2139 #define CSL_SRIO_RIO_TLM_SP_INT_ENABLE_IG_BAD_VC_RESETVAL (0x00000000u)
2141 #define CSL_SRIO_RIO_TLM_SP_INT_ENABLE_IG_BRR_FILTER_MASK (0x00100000u)
2142 #define CSL_SRIO_RIO_TLM_SP_INT_ENABLE_IG_BRR_FILTER_SHIFT (0x00000014u)
2143 #define CSL_SRIO_RIO_TLM_SP_INT_ENABLE_IG_BRR_FILTER_RESETVAL (0x00000000u)
2145 #define CSL_SRIO_RIO_TLM_SP_INT_ENABLE_RESETVAL (0x00000000u)
2147 /* rio_tlm_sp_pw_enable */
2149 #define CSL_SRIO_RIO_TLM_SP_PW_ENABLE_IG_BAD_VC_MASK (0x80000000u)
2150 #define CSL_SRIO_RIO_TLM_SP_PW_ENABLE_IG_BAD_VC_SHIFT (0x0000001Fu)
2151 #define CSL_SRIO_RIO_TLM_SP_PW_ENABLE_IG_BAD_VC_RESETVAL (0x00000000u)
2153 #define CSL_SRIO_RIO_TLM_SP_PW_ENABLE_IG_BRR_FILTER_MASK (0x00100000u)
2154 #define CSL_SRIO_RIO_TLM_SP_PW_ENABLE_IG_BRR_FILTER_SHIFT (0x00000014u)
2155 #define CSL_SRIO_RIO_TLM_SP_PW_ENABLE_IG_BRR_FILTER_RESETVAL (0x00000000u)
2157 #define CSL_SRIO_RIO_TLM_SP_PW_ENABLE_RESETVAL (0x00000000u)
2159 /* rio_tlm_sp_event_gen */
2161 #define CSL_SRIO_RIO_TLM_SP_EVENT_GEN_IG_BAD_VC_MASK (0x80000000u)
2162 #define CSL_SRIO_RIO_TLM_SP_EVENT_GEN_IG_BAD_VC_SHIFT (0x0000001Fu)
2163 #define CSL_SRIO_RIO_TLM_SP_EVENT_GEN_IG_BAD_VC_RESETVAL (0x00000000u)
2165 #define CSL_SRIO_RIO_TLM_SP_EVENT_GEN_IG_BRR_FILTER_MASK (0x00100000u)
2166 #define CSL_SRIO_RIO_TLM_SP_EVENT_GEN_IG_BRR_FILTER_SHIFT (0x00000014u)
2167 #define CSL_SRIO_RIO_TLM_SP_EVENT_GEN_IG_BRR_FILTER_RESETVAL (0x00000000u)
2169 #define CSL_SRIO_RIO_TLM_SP_EVENT_GEN_RESETVAL (0x00000000u)
2171 /* rio_tlm_sp_brr_0_ctl */
2173 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_ENABLE_MASK (0x80000000u)
2174 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_ENABLE_SHIFT (0x0000001Fu)
2175 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_ENABLE_RESETVAL (0x00000000u)
2177 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_ROUTE_MR_TO_LLM_MASK (0x04000000u)
2178 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_ROUTE_MR_TO_LLM_SHIFT (0x0000001Au)
2179 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_ROUTE_MR_TO_LLM_RESETVAL (0x00000001u)
2181 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_PRIVATE_MASK (0x01000000u)
2182 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_PRIVATE_SHIFT (0x00000018u)
2183 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_PRIVATE_RESETVAL (0x00000001u)
2185 #define CSL_SRIO_RIO_TLM_SP_BRR_0_CTL_RESETVAL (0x05000000u)
2187 /* rio_tlm_sp_brr_0_pattern_match */
2189 #define CSL_SRIO_RIO_TLM_SP_BRR_0_PATTERN_MATCH_PATTERN_MASK (0xFFFF0000u)
2190 #define CSL_SRIO_RIO_TLM_SP_BRR_0_PATTERN_MATCH_PATTERN_SHIFT (0x00000010u)
2191 #define CSL_SRIO_RIO_TLM_SP_BRR_0_PATTERN_MATCH_PATTERN_RESETVAL (0x00000000u)
2193 #define CSL_SRIO_RIO_TLM_SP_BRR_0_PATTERN_MATCH_MATCH_MASK (0x0000FFFFu)
2194 #define CSL_SRIO_RIO_TLM_SP_BRR_0_PATTERN_MATCH_MATCH_SHIFT (0x00000000u)
2195 #define CSL_SRIO_RIO_TLM_SP_BRR_0_PATTERN_MATCH_MATCH_RESETVAL (0x00000000u)
2197 #define CSL_SRIO_RIO_TLM_SP_BRR_0_PATTERN_MATCH_RESETVAL (0x00000000u)
2199 /* rio_tlm_sp_brr_1_ctl */
2201 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_ENABLE_MASK (0x80000000u)
2202 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_ENABLE_SHIFT (0x0000001Fu)
2203 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_ENABLE_RESETVAL (0x00000000u)
2205 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_ROUTE_MR_TO_LLM_MASK (0x04000000u)
2206 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_ROUTE_MR_TO_LLM_SHIFT (0x0000001Au)
2207 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_ROUTE_MR_TO_LLM_RESETVAL (0x00000001u)
2209 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_PRIVATE_MASK (0x01000000u)
2210 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_PRIVATE_SHIFT (0x00000018u)
2211 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_PRIVATE_RESETVAL (0x00000001u)
2213 #define CSL_SRIO_RIO_TLM_SP_BRR_1_CTL_RESETVAL (0x05000000u)
2215 /* rio_tlm_sp_brr_1_pattern_match */
2217 #define CSL_SRIO_RIO_TLM_SP_BRR_1_PATTERN_MATCH_PATTERN_MASK (0xFFFF0000u)
2218 #define CSL_SRIO_RIO_TLM_SP_BRR_1_PATTERN_MATCH_PATTERN_SHIFT (0x00000010u)
2219 #define CSL_SRIO_RIO_TLM_SP_BRR_1_PATTERN_MATCH_PATTERN_RESETVAL (0x00000000u)
2221 #define CSL_SRIO_RIO_TLM_SP_BRR_1_PATTERN_MATCH_MATCH_MASK (0x0000FFFFu)
2222 #define CSL_SRIO_RIO_TLM_SP_BRR_1_PATTERN_MATCH_MATCH_SHIFT (0x00000000u)
2223 #define CSL_SRIO_RIO_TLM_SP_BRR_1_PATTERN_MATCH_MATCH_RESETVAL (0x0000FFFFu)
2225 #define CSL_SRIO_RIO_TLM_SP_BRR_1_PATTERN_MATCH_RESETVAL (0x0000FFFFu)
2227 /* rio_tlm_sp_brr_2_ctl */
2229 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_ENABLE_MASK (0x80000000u)
2230 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_ENABLE_SHIFT (0x0000001Fu)
2231 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_ENABLE_RESETVAL (0x00000000u)
2233 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_ROUTE_MR_TO_LLM_MASK (0x04000000u)
2234 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_ROUTE_MR_TO_LLM_SHIFT (0x0000001Au)
2235 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_ROUTE_MR_TO_LLM_RESETVAL (0x00000001u)
2237 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_PRIVATE_MASK (0x01000000u)
2238 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_PRIVATE_SHIFT (0x00000018u)
2239 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_PRIVATE_RESETVAL (0x00000001u)
2241 #define CSL_SRIO_RIO_TLM_SP_BRR_2_CTL_RESETVAL (0x05000000u)
2243 /* rio_tlm_sp_brr_2_pattern_match */
2245 #define CSL_SRIO_RIO_TLM_SP_BRR_2_PATTERN_MATCH_PATTERN_MASK (0xFFFF0000u)
2246 #define CSL_SRIO_RIO_TLM_SP_BRR_2_PATTERN_MATCH_PATTERN_SHIFT (0x00000010u)
2247 #define CSL_SRIO_RIO_TLM_SP_BRR_2_PATTERN_MATCH_PATTERN_RESETVAL (0x00000000u)
2249 #define CSL_SRIO_RIO_TLM_SP_BRR_2_PATTERN_MATCH_MATCH_MASK (0x0000FFFFu)
2250 #define CSL_SRIO_RIO_TLM_SP_BRR_2_PATTERN_MATCH_MATCH_SHIFT (0x00000000u)
2251 #define CSL_SRIO_RIO_TLM_SP_BRR_2_PATTERN_MATCH_MATCH_RESETVAL (0x0000FFFFu)
2253 #define CSL_SRIO_RIO_TLM_SP_BRR_2_PATTERN_MATCH_RESETVAL (0x0000FFFFu)
2255 /* rio_tlm_sp_brr_3_ctl */
2257 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_ENABLE_MASK (0x80000000u)
2258 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_ENABLE_SHIFT (0x0000001Fu)
2259 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_ENABLE_RESETVAL (0x00000000u)
2261 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_ROUTE_MR_TO_LLM_MASK (0x04000000u)
2262 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_ROUTE_MR_TO_LLM_SHIFT (0x0000001Au)
2263 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_ROUTE_MR_TO_LLM_RESETVAL (0x00000001u)
2265 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_PRIVATE_MASK (0x01000000u)
2266 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_PRIVATE_SHIFT (0x00000018u)
2267 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_PRIVATE_RESETVAL (0x00000001u)
2269 #define CSL_SRIO_RIO_TLM_SP_BRR_3_CTL_RESETVAL (0x05000000u)
2271 /* rio_tlm_sp_brr_3_pattern_match */
2273 #define CSL_SRIO_RIO_TLM_SP_BRR_3_PATTERN_MATCH_PATTERN_MASK (0xFFFF0000u)
2274 #define CSL_SRIO_RIO_TLM_SP_BRR_3_PATTERN_MATCH_PATTERN_SHIFT (0x00000010u)
2275 #define CSL_SRIO_RIO_TLM_SP_BRR_3_PATTERN_MATCH_PATTERN_RESETVAL (0x00000000u)
2277 #define CSL_SRIO_RIO_TLM_SP_BRR_3_PATTERN_MATCH_MATCH_MASK (0x0000FFFFu)
2278 #define CSL_SRIO_RIO_TLM_SP_BRR_3_PATTERN_MATCH_MATCH_SHIFT (0x00000000u)
2279 #define CSL_SRIO_RIO_TLM_SP_BRR_3_PATTERN_MATCH_MATCH_RESETVAL (0x0000FFFFu)
2281 #define CSL_SRIO_RIO_TLM_SP_BRR_3_PATTERN_MATCH_RESETVAL (0x0000FFFFu)
2283 /* rio_pbm_sp_control */
2285 #define CSL_SRIO_RIO_PBM_SP_CONTROL_EG_REORDER_MODE_MASK (0x00000030u)
2286 #define CSL_SRIO_RIO_PBM_SP_CONTROL_EG_REORDER_MODE_SHIFT (0x00000004u)
2287 #define CSL_SRIO_RIO_PBM_SP_CONTROL_EG_REORDER_MODE_RESETVAL (0x00000000u)
2289 #define CSL_SRIO_RIO_PBM_SP_CONTROL_EG_REORDER_STICK_MASK (0x00000007u)
2290 #define CSL_SRIO_RIO_PBM_SP_CONTROL_EG_REORDER_STICK_SHIFT (0x00000000u)
2291 #define CSL_SRIO_RIO_PBM_SP_CONTROL_EG_REORDER_STICK_RESETVAL (0x00000000u)
2293 #define CSL_SRIO_RIO_PBM_SP_CONTROL_RESETVAL (0x00000000u)
2295 /* rio_pbm_sp_status */
2297 #define CSL_SRIO_RIO_PBM_SP_STATUS_IG_EMPTY_MASK (0x00010000u)
2298 #define CSL_SRIO_RIO_PBM_SP_STATUS_IG_EMPTY_SHIFT (0x00000010u)
2299 #define CSL_SRIO_RIO_PBM_SP_STATUS_IG_EMPTY_RESETVAL (0x00000001u)
2301 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_EMPTY_MASK (0x00008000u)
2302 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_EMPTY_SHIFT (0x0000000Fu)
2303 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_EMPTY_RESETVAL (0x00000001u)
2305 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_DATA_OVERFLOW_MASK (0x00000010u)
2306 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_DATA_OVERFLOW_SHIFT (0x00000004u)
2307 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_DATA_OVERFLOW_RESETVAL (0x00000000u)
2309 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_CRQ_OVERFLOW_MASK (0x00000008u)
2310 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_CRQ_OVERFLOW_SHIFT (0x00000003u)
2311 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_CRQ_OVERFLOW_RESETVAL (0x00000000u)
2313 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_BAD_CHANNEL_MASK (0x00000002u)
2314 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_BAD_CHANNEL_SHIFT (0x00000001u)
2315 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_BAD_CHANNEL_RESETVAL (0x00000000u)
2317 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_BABBLE_PACKET_MASK (0x00000001u)
2318 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_BABBLE_PACKET_SHIFT (0x00000000u)
2319 #define CSL_SRIO_RIO_PBM_SP_STATUS_EG_BABBLE_PACKET_RESETVAL (0x00000000u)
2321 #define CSL_SRIO_RIO_PBM_SP_STATUS_RESETVAL (0x00018000u)
2323 /* rio_pbm_sp_int_enable */
2325 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_DATA_OVERFLOW_MASK (0x00000010u)
2326 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_DATA_OVERFLOW_SHIFT (0x00000004u)
2327 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_DATA_OVERFLOW_RESETVAL (0x00000000u)
2329 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_CRQ_OVERFLOW_MASK (0x00000008u)
2330 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_CRQ_OVERFLOW_SHIFT (0x00000003u)
2331 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_CRQ_OVERFLOW_RESETVAL (0x00000000u)
2333 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_BAD_CHANNEL_MASK (0x00000002u)
2334 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_BAD_CHANNEL_SHIFT (0x00000001u)
2335 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_BAD_CHANNEL_RESETVAL (0x00000000u)
2337 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_BABBLE_PACKET_MASK (0x00000001u)
2338 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_BABBLE_PACKET_SHIFT (0x00000000u)
2339 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_EG_BABBLE_PACKET_RESETVAL (0x00000000u)
2341 #define CSL_SRIO_RIO_PBM_SP_INT_ENABLE_RESETVAL (0x00000000u)
2343 /* rio_pbm_sp_pw_enable */
2345 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_DATA_OVERFLOW_MASK (0x00000010u)
2346 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_DATA_OVERFLOW_SHIFT (0x00000004u)
2347 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_DATA_OVERFLOW_RESETVAL (0x00000000u)
2349 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_CRQ_OVERFLOW_MASK (0x00000008u)
2350 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_CRQ_OVERFLOW_SHIFT (0x00000003u)
2351 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_CRQ_OVERFLOW_RESETVAL (0x00000000u)
2353 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_BAD_CHANNEL_MASK (0x00000002u)
2354 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_BAD_CHANNEL_SHIFT (0x00000001u)
2355 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_BAD_CHANNEL_RESETVAL (0x00000000u)
2357 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_BABBLE_PACKET_MASK (0x00000001u)
2358 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_BABBLE_PACKET_SHIFT (0x00000000u)
2359 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_EG_BABBLE_PACKET_RESETVAL (0x00000000u)
2361 #define CSL_SRIO_RIO_PBM_SP_PW_ENABLE_RESETVAL (0x00000000u)
2363 /* rio_pbm_sp_event_gen */
2365 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_DATA_OVERFLOW_MASK (0x00000010u)
2366 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_DATA_OVERFLOW_SHIFT (0x00000004u)
2367 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_DATA_OVERFLOW_RESETVAL (0x00000000u)
2369 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_CRQ_OVERFLOW_MASK (0x00000008u)
2370 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_CRQ_OVERFLOW_SHIFT (0x00000003u)
2371 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_CRQ_OVERFLOW_RESETVAL (0x00000000u)
2373 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_BAD_CHANNEL_MASK (0x00000002u)
2374 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_BAD_CHANNEL_SHIFT (0x00000001u)
2375 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_BAD_CHANNEL_RESETVAL (0x00000000u)
2377 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_BABBLE_PACKET_MASK (0x00000001u)
2378 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_BABBLE_PACKET_SHIFT (0x00000000u)
2379 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_EG_BABBLE_PACKET_RESETVAL (0x00000000u)
2381 #define CSL_SRIO_RIO_PBM_SP_EVENT_GEN_RESETVAL (0x00000000u)
2383 /* rio_pbm_sp_ig_resources */
2385 #define CSL_SRIO_RIO_PBM_SP_IG_RESOURCES_DATANODES_MASK (0x03FF0000u)
2386 #define CSL_SRIO_RIO_PBM_SP_IG_RESOURCES_DATANODES_SHIFT (0x00000010u)
2387 #define CSL_SRIO_RIO_PBM_SP_IG_RESOURCES_DATANODES_RESETVAL (0x00000000u)
2389 #define CSL_SRIO_RIO_PBM_SP_IG_RESOURCES_TAGS_MASK (0x000003FFu)
2390 #define CSL_SRIO_RIO_PBM_SP_IG_RESOURCES_TAGS_SHIFT (0x00000000u)
2391 #define CSL_SRIO_RIO_PBM_SP_IG_RESOURCES_TAGS_RESETVAL (0x00000000u)
2393 #define CSL_SRIO_RIO_PBM_SP_IG_RESOURCES_RESETVAL (0x00000000u)
2395 /* rio_pbm_sp_eg_resources */
2397 #define CSL_SRIO_RIO_PBM_SP_EG_RESOURCES_DATANODES_MASK (0x03FF0000u)
2398 #define CSL_SRIO_RIO_PBM_SP_EG_RESOURCES_DATANODES_SHIFT (0x00000010u)
2399 #define CSL_SRIO_RIO_PBM_SP_EG_RESOURCES_DATANODES_RESETVAL (0x00000049u)
2401 #define CSL_SRIO_RIO_PBM_SP_EG_RESOURCES_CRQ_ENTRIES_MASK (0x0000007Fu)
2402 #define CSL_SRIO_RIO_PBM_SP_EG_RESOURCES_CRQ_ENTRIES_SHIFT (0x00000000u)
2403 #define CSL_SRIO_RIO_PBM_SP_EG_RESOURCES_CRQ_ENTRIES_RESETVAL (0x00000021u)
2405 #define CSL_SRIO_RIO_PBM_SP_EG_RESOURCES_RESETVAL (0x00490021u)
2407 /* rio_pbm_sp_ig_watermark0 */
2409 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK0_PRIO0CRF_WM_MASK (0x03FF0000u)
2410 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK0_PRIO0CRF_WM_SHIFT (0x00000010u)
2411 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK0_PRIO0CRF_WM_RESETVAL (0x0000003Fu)
2413 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK0_PRIO0_WM_MASK (0x000003FFu)
2414 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK0_PRIO0_WM_SHIFT (0x00000000u)
2415 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK0_PRIO0_WM_RESETVAL (0x00000048u)
2417 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK0_RESETVAL (0x003F0048u)
2419 /* rio_pbm_sp_ig_watermark1 */
2421 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK1_PRIO1CRF_WM_MASK (0x03FF0000u)
2422 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK1_PRIO1CRF_WM_SHIFT (0x00000010u)
2423 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK1_PRIO1CRF_WM_RESETVAL (0x0000002Du)
2425 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK1_PRIO1_WM_MASK (0x000003FFu)
2426 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK1_PRIO1_WM_SHIFT (0x00000000u)
2427 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK1_PRIO1_WM_RESETVAL (0x00000036u)
2429 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK1_RESETVAL (0x002D0036u)
2431 /* rio_pbm_sp_ig_watermark2 */
2433 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK2_PRIO2CRF_WM_MASK (0x03FF0000u)
2434 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK2_PRIO2CRF_WM_SHIFT (0x00000010u)
2435 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK2_PRIO2CRF_WM_RESETVAL (0x0000001Bu)
2437 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK2_PRIO2_WM_MASK (0x000003FFu)
2438 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK2_PRIO2_WM_SHIFT (0x00000000u)
2439 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK2_PRIO2_WM_RESETVAL (0x00000024u)
2441 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK2_RESETVAL (0x001B0024u)
2443 /* rio_pbm_sp_ig_watermark3 */
2445 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK3_PRIO3CRF_WM_MASK (0x03FF0000u)
2446 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK3_PRIO3CRF_WM_SHIFT (0x00000010u)
2447 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK3_PRIO3CRF_WM_RESETVAL (0x00000009u)
2449 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK3_PRIO3_WM_MASK (0x000003FFu)
2450 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK3_PRIO3_WM_SHIFT (0x00000000u)
2451 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK3_PRIO3_WM_RESETVAL (0x00000012u)
2453 #define CSL_SRIO_RIO_PBM_SP_IG_WATERMARK3_RESETVAL (0x00090012u)
2455 /* rio_pid */
2457 #define CSL_SRIO_RIO_PID_MINOR_MASK (0x0000003Fu)
2458 #define CSL_SRIO_RIO_PID_MINOR_SHIFT (0x00000000u)
2459 #define CSL_SRIO_RIO_PID_MINOR_RESETVAL (0x00000001u)
2461 #define CSL_SRIO_RIO_PID_CUSTOM_MASK (0x000000C0u)
2462 #define CSL_SRIO_RIO_PID_CUSTOM_SHIFT (0x00000006u)
2463 #define CSL_SRIO_RIO_PID_CUSTOM_RESETVAL (0x00000000u)
2465 #define CSL_SRIO_RIO_PID_MAJOR_MASK (0x00000700u)
2466 #define CSL_SRIO_RIO_PID_MAJOR_SHIFT (0x00000008u)
2467 #define CSL_SRIO_RIO_PID_MAJOR_RESETVAL (0x00000001u)
2469 #define CSL_SRIO_RIO_PID_RTL_MASK (0x0000F800u)
2470 #define CSL_SRIO_RIO_PID_RTL_SHIFT (0x0000000Bu)
2471 #define CSL_SRIO_RIO_PID_RTL_RESETVAL (0x00000004u)
2473 #define CSL_SRIO_RIO_PID_FUNC_MASK (0x0FFF0000u)
2474 #define CSL_SRIO_RIO_PID_FUNC_SHIFT (0x00000010u)
2475 #define CSL_SRIO_RIO_PID_FUNC_RESETVAL (0x000004ABu)
2477 #define CSL_SRIO_RIO_PID_BU_MASK (0x30000000u)
2478 #define CSL_SRIO_RIO_PID_BU_SHIFT (0x0000001Cu)
2479 #define CSL_SRIO_RIO_PID_BU_RESETVAL (0x00000000u)
2481 #define CSL_SRIO_RIO_PID_SCHEME_MASK (0xC0000000u)
2482 #define CSL_SRIO_RIO_PID_SCHEME_SHIFT (0x0000001Eu)
2483 #define CSL_SRIO_RIO_PID_SCHEME_RESETVAL (0x00000001u)
2485 #define CSL_SRIO_RIO_PID_RESETVAL (0x44AB2101u)
2487 /* rio_pcr */
2489 #define CSL_SRIO_RIO_PCR_FREE_MASK (0x00000001u)
2490 #define CSL_SRIO_RIO_PCR_FREE_SHIFT (0x00000000u)
2491 #define CSL_SRIO_RIO_PCR_FREE_RESETVAL (0x00000001u)
2493 #define CSL_SRIO_RIO_PCR_SOFT_MASK (0x00000002u)
2494 #define CSL_SRIO_RIO_PCR_SOFT_SHIFT (0x00000001u)
2495 #define CSL_SRIO_RIO_PCR_SOFT_RESETVAL (0x00000000u)
2497 #define CSL_SRIO_RIO_PCR_PEREN_MASK (0x00000004u)
2498 #define CSL_SRIO_RIO_PCR_PEREN_SHIFT (0x00000002u)
2499 #define CSL_SRIO_RIO_PCR_PEREN_RESETVAL (0x00000000u)
2501 #define CSL_SRIO_RIO_PCR_LOCAL_DIS_MASK (0x00000008u)
2502 #define CSL_SRIO_RIO_PCR_LOCAL_DIS_SHIFT (0x00000003u)
2503 #define CSL_SRIO_RIO_PCR_LOCAL_DIS_RESETVAL (0x00000000u)
2505 #define CSL_SRIO_RIO_PCR_RESTORE_MASK (0x00000010u)
2506 #define CSL_SRIO_RIO_PCR_RESTORE_SHIFT (0x00000004u)
2507 #define CSL_SRIO_RIO_PCR_RESTORE_RESETVAL (0x00000000u)
2509 #define CSL_SRIO_RIO_PCR_REORDER_BUF_DIS_MASK (0x00000020u)
2510 #define CSL_SRIO_RIO_PCR_REORDER_BUF_DIS_SHIFT (0x00000005u)
2511 #define CSL_SRIO_RIO_PCR_REORDER_BUF_DIS_RESETVAL (0x00000000u)
2513 #define CSL_SRIO_RIO_PCR_SRIO_IN_RESET_MASK (0x00000040u)
2514 #define CSL_SRIO_RIO_PCR_SRIO_IN_RESET_SHIFT (0x00000006u)
2515 #define CSL_SRIO_RIO_PCR_SRIO_IN_RESET_RESETVAL (0x00000000u)
2517 #define CSL_SRIO_RIO_PCR_RESETVAL (0x00000001u)
2519 /* rio_per_set_cntl */
2521 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES0_PRBS_OVR_MASK (0x00000001u)
2522 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES0_PRBS_OVR_SHIFT (0x00000000u)
2523 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES0_PRBS_OVR_RESETVAL (0x00000000u)
2525 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES1_PRBS_OVR_MASK (0x00000002u)
2526 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES1_PRBS_OVR_SHIFT (0x00000001u)
2527 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES1_PRBS_OVR_RESETVAL (0x00000000u)
2529 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES2_PRBS_OVR_MASK (0x00000004u)
2530 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES2_PRBS_OVR_SHIFT (0x00000002u)
2531 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES2_PRBS_OVR_RESETVAL (0x00000000u)
2533 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES3_PRBS_OVR_MASK (0x00000008u)
2534 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES3_PRBS_OVR_SHIFT (0x00000003u)
2535 #define CSL_SRIO_RIO_PER_SET_CNTL_SERDES3_PRBS_OVR_RESETVAL (0x00000000u)
2537 #define CSL_SRIO_RIO_PER_SET_CNTL_PRESCALER_SELECT_MASK (0x000000F0u)
2538 #define CSL_SRIO_RIO_PER_SET_CNTL_PRESCALER_SELECT_SHIFT (0x00000004u)
2539 #define CSL_SRIO_RIO_PER_SET_CNTL_PRESCALER_SELECT_RESETVAL (0x00000000u)
2541 #define CSL_SRIO_RIO_PER_SET_CNTL_CRF_CREDIT_MASK (0x00000100u)
2542 #define CSL_SRIO_RIO_PER_SET_CNTL_CRF_CREDIT_SHIFT (0x00000008u)
2543 #define CSL_SRIO_RIO_PER_SET_CNTL_CRF_CREDIT_RESETVAL (0x00000000u)
2545 #define CSL_SRIO_RIO_PER_SET_CNTL_CBA_TRANS_PRI_MASK (0x00000E00u)
2546 #define CSL_SRIO_RIO_PER_SET_CNTL_CBA_TRANS_PRI_SHIFT (0x00000009u)
2547 #define CSL_SRIO_RIO_PER_SET_CNTL_CBA_TRANS_PRI_RESETVAL (0x00000004u)
2549 #define CSL_SRIO_RIO_PER_SET_CNTL_TX_PRI0_WM_MASK (0x00007000u)
2550 #define CSL_SRIO_RIO_PER_SET_CNTL_TX_PRI0_WM_SHIFT (0x0000000Cu)
2551 #define CSL_SRIO_RIO_PER_SET_CNTL_TX_PRI0_WM_RESETVAL (0x00000003u)
2553 #define CSL_SRIO_RIO_PER_SET_CNTL_TX_PRI1_WM_MASK (0x00038000u)
2554 #define CSL_SRIO_RIO_PER_SET_CNTL_TX_PRI1_WM_SHIFT (0x0000000Fu)
2555 #define CSL_SRIO_RIO_PER_SET_CNTL_TX_PRI1_WM_RESETVAL (0x00000002u)
2557 #define CSL_SRIO_RIO_PER_SET_CNTL_TX_PRI2_WM_MASK (0x001C0000u)
2558 #define CSL_SRIO_RIO_PER_SET_CNTL_TX_PRI2_WM_SHIFT (0x00000012u)
2559 #define CSL_SRIO_RIO_PER_SET_CNTL_TX_PRI2_WM_RESETVAL (0x00000001u)
2561 #define CSL_SRIO_RIO_PER_SET_CNTL_PROMOTE_DIS_MASK (0x00200000u)
2562 #define CSL_SRIO_RIO_PER_SET_CNTL_PROMOTE_DIS_SHIFT (0x00000015u)
2563 #define CSL_SRIO_RIO_PER_SET_CNTL_PROMOTE_DIS_RESETVAL (0x00000000u)
2565 #define CSL_SRIO_RIO_PER_SET_CNTL_TXU_RXU_LEND_SWAP_MODE_MASK (0x00C00000u)
2566 #define CSL_SRIO_RIO_PER_SET_CNTL_TXU_RXU_LEND_SWAP_MODE_SHIFT (0x00000016u)
2567 #define CSL_SRIO_RIO_PER_SET_CNTL_TXU_RXU_LEND_SWAP_MODE_RESETVAL (0x00000000u)
2569 #define CSL_SRIO_RIO_PER_SET_CNTL_BOOT_COMPLETE_MASK (0x01000000u)
2570 #define CSL_SRIO_RIO_PER_SET_CNTL_BOOT_COMPLETE_SHIFT (0x00000018u)
2571 #define CSL_SRIO_RIO_PER_SET_CNTL_BOOT_COMPLETE_RESETVAL (0x00000000u)
2573 #define CSL_SRIO_RIO_PER_SET_CNTL_AMU_LEND_SWAP_MODE_MASK (0x06000000u)
2574 #define CSL_SRIO_RIO_PER_SET_CNTL_AMU_LEND_SWAP_MODE_SHIFT (0x00000019u)
2575 #define CSL_SRIO_RIO_PER_SET_CNTL_AMU_LEND_SWAP_MODE_RESETVAL (0x00000000u)
2577 #define CSL_SRIO_RIO_PER_SET_CNTL_LOG_TGT_ID_DIS_MASK (0x08000000u)
2578 #define CSL_SRIO_RIO_PER_SET_CNTL_LOG_TGT_ID_DIS_SHIFT (0x0000001Bu)
2579 #define CSL_SRIO_RIO_PER_SET_CNTL_LOG_TGT_ID_DIS_RESETVAL (0x00000000u)
2581 #define CSL_SRIO_RIO_PER_SET_CNTL_LSU_LEND_SWAP_MODE_MASK (0x30000000u)
2582 #define CSL_SRIO_RIO_PER_SET_CNTL_LSU_LEND_SWAP_MODE_SHIFT (0x0000001Cu)
2583 #define CSL_SRIO_RIO_PER_SET_CNTL_LSU_LEND_SWAP_MODE_RESETVAL (0x00000000u)
2585 #define CSL_SRIO_RIO_PER_SET_CNTL_MAU_LEND_SWAP_MODE_MASK (0xC0000000u)
2586 #define CSL_SRIO_RIO_PER_SET_CNTL_MAU_LEND_SWAP_MODE_SHIFT (0x0000001Eu)
2587 #define CSL_SRIO_RIO_PER_SET_CNTL_MAU_LEND_SWAP_MODE_RESETVAL (0x00000000u)
2589 #define CSL_SRIO_RIO_PER_SET_CNTL_RESETVAL (0x00053800u)
2591 /* rio_per_set_cntl1 */
2593 #define CSL_SRIO_RIO_PER_SET_CNTL1_CRF_MASK (0x00000001u)
2594 #define CSL_SRIO_RIO_PER_SET_CNTL1_CRF_SHIFT (0x00000000u)
2595 #define CSL_SRIO_RIO_PER_SET_CNTL1_CRF_RESETVAL (0x00000000u)
2597 #define CSL_SRIO_RIO_PER_SET_CNTL1_RXU_WATERMARK_MASK (0x00000002u)
2598 #define CSL_SRIO_RIO_PER_SET_CNTL1_RXU_WATERMARK_SHIFT (0x00000001u)
2599 #define CSL_SRIO_RIO_PER_SET_CNTL1_RXU_WATERMARK_RESETVAL (0x00000000u)
2601 #define CSL_SRIO_RIO_PER_SET_CNTL1_SYS_CLK_SEL_MASK (0x0000000Cu)
2602 #define CSL_SRIO_RIO_PER_SET_CNTL1_SYS_CLK_SEL_SHIFT (0x00000002u)
2603 #define CSL_SRIO_RIO_PER_SET_CNTL1_SYS_CLK_SEL_RESETVAL (0x00000000u)
2605 #define CSL_SRIO_RIO_PER_SET_CNTL1_LOOPBACK_MASK (0x000000F0u)
2606 #define CSL_SRIO_RIO_PER_SET_CNTL1_LOOPBACK_SHIFT (0x00000004u)
2607 #define CSL_SRIO_RIO_PER_SET_CNTL1_LOOPBACK_RESETVAL (0x00000000u)
2609 #define CSL_SRIO_RIO_PER_SET_CNTL1_COS_EN_MASK (0x00000100u)
2610 #define CSL_SRIO_RIO_PER_SET_CNTL1_COS_EN_SHIFT (0x00000008u)
2611 #define CSL_SRIO_RIO_PER_SET_CNTL1_COS_EN_RESETVAL (0x00000000u)
2613 #define CSL_SRIO_RIO_PER_SET_CNTL1_SYS_CLK_VBUSP_MASK (0x00000200u)
2614 #define CSL_SRIO_RIO_PER_SET_CNTL1_SYS_CLK_VBUSP_SHIFT (0x00000009u)
2615 #define CSL_SRIO_RIO_PER_SET_CNTL1_SYS_CLK_VBUSP_RESETVAL (0x00000000u)
2617 #define CSL_SRIO_RIO_PER_SET_CNTL1_TXU_RETRY_TIMER_MODE_MASK (0x0000F000u)
2618 #define CSL_SRIO_RIO_PER_SET_CNTL1_TXU_RETRY_TIMER_MODE_SHIFT (0x0000000Cu)
2619 #define CSL_SRIO_RIO_PER_SET_CNTL1_TXU_RETRY_TIMER_MODE_RESETVAL (0x00000000u)
2621 #define CSL_SRIO_RIO_PER_SET_CNTL1_RESETVAL (0x00000000u)
2623 /* rio_gbl_en */
2625 #define CSL_SRIO_RIO_GBL_EN_EN_MASK (0x00000001u)
2626 #define CSL_SRIO_RIO_GBL_EN_EN_SHIFT (0x00000000u)
2627 #define CSL_SRIO_RIO_GBL_EN_EN_RESETVAL (0x00000001u)
2629 #define CSL_SRIO_RIO_GBL_EN_RESETVAL (0x00000001u)
2631 /* rio_gbl_en_stat */
2633 #define CSL_SRIO_RIO_GBL_EN_STAT_GBL_EN_STAT_MASK (0x00000001u)
2634 #define CSL_SRIO_RIO_GBL_EN_STAT_GBL_EN_STAT_SHIFT (0x00000000u)
2635 #define CSL_SRIO_RIO_GBL_EN_STAT_GBL_EN_STAT_RESETVAL (0x00000001u)
2637 #define CSL_SRIO_RIO_GBL_EN_STAT_BLKX_EN_STAT_MASK (0x000007FEu)
2638 #define CSL_SRIO_RIO_GBL_EN_STAT_BLKX_EN_STAT_SHIFT (0x00000001u)
2639 #define CSL_SRIO_RIO_GBL_EN_STAT_BLKX_EN_STAT_RESETVAL (0x000003FFu)
2641 #define CSL_SRIO_RIO_GBL_EN_STAT_RESETVAL (0x000007FFu)
2643 /* rio_multiid_reg */
2645 #define CSL_SRIO_RIO_MULTIID_REG_16B_NODEID_MASK (0x0000FFFFu)
2646 #define CSL_SRIO_RIO_MULTIID_REG_16B_NODEID_SHIFT (0x00000000u)
2647 #define CSL_SRIO_RIO_MULTIID_REG_16B_NODEID_RESETVAL (0x0000FFFFu)
2649 #define CSL_SRIO_RIO_MULTIID_REG_8B_NODEID_MASK (0x00FF0000u)
2650 #define CSL_SRIO_RIO_MULTIID_REG_8B_NODEID_SHIFT (0x00000010u)
2651 #define CSL_SRIO_RIO_MULTIID_REG_8B_NODEID_RESETVAL (0x000000FFu)
2653 #define CSL_SRIO_RIO_MULTIID_REG_RESETVAL (0x00FFFFFFu)
2655 /* rio_err_rst_evnt_icsr */
2657 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_MCAST_INT_RECEIVED_MASK (0x00000001u)
2658 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_MCAST_INT_RECEIVED_SHIFT (0x00000000u)
2659 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_MCAST_INT_RECEIVED_RESETVAL (0x00000000u)
2661 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT_WRITE_IN_RECEIVED_MASK (0x00000002u)
2662 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT_WRITE_IN_RECEIVED_SHIFT (0x00000001u)
2663 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT_WRITE_IN_RECEIVED_RESETVAL (0x00000000u)
2665 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_LLERR_CAPTURE_MASK (0x00000004u)
2666 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_LLERR_CAPTURE_SHIFT (0x00000002u)
2667 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_LLERR_CAPTURE_RESETVAL (0x00000000u)
2669 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT0_ERR_MASK (0x00000100u)
2670 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT0_ERR_SHIFT (0x00000008u)
2671 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT0_ERR_RESETVAL (0x00000000u)
2673 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT1_ERR_MASK (0x00000200u)
2674 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT1_ERR_SHIFT (0x00000009u)
2675 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT1_ERR_RESETVAL (0x00000000u)
2677 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT2_ERR_MASK (0x00000400u)
2678 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT2_ERR_SHIFT (0x0000000Au)
2679 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT2_ERR_RESETVAL (0x00000000u)
2681 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT3_ERR_MASK (0x00000800u)
2682 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT3_ERR_SHIFT (0x0000000Bu)
2683 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_PORT3_ERR_RESETVAL (0x00000000u)
2685 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_DEVICE_RST_INT_MASK (0x00010000u)
2686 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_DEVICE_RST_INT_SHIFT (0x00000010u)
2687 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_DEVICE_RST_INT_RESETVAL (0x00000000u)
2689 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICSR_RESETVAL (0x00000000u)
2691 /* rio_err_rst_evnt_iccr */
2693 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_MCAST_INT_RECEIVED_MASK (0x00000001u)
2694 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_MCAST_INT_RECEIVED_SHIFT (0x00000000u)
2695 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_MCAST_INT_RECEIVED_RESETVAL (0x00000000u)
2697 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT_WRITE_IN_RECEIVED_MASK (0x00000002u)
2698 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT_WRITE_IN_RECEIVED_SHIFT (0x00000001u)
2699 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT_WRITE_IN_RECEIVED_RESETVAL (0x00000000u)
2701 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_LLERR_CAPTURE_MASK (0x00000004u)
2702 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_LLERR_CAPTURE_SHIFT (0x00000002u)
2703 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_LLERR_CAPTURE_RESETVAL (0x00000000u)
2705 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT0_ERR_MASK (0x00000100u)
2706 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT0_ERR_SHIFT (0x00000008u)
2707 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT0_ERR_RESETVAL (0x00000000u)
2709 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT1_ERR_MASK (0x00000200u)
2710 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT1_ERR_SHIFT (0x00000009u)
2711 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT1_ERR_RESETVAL (0x00000000u)
2713 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT2_ERR_MASK (0x00000400u)
2714 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT2_ERR_SHIFT (0x0000000Au)
2715 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT2_ERR_RESETVAL (0x00000000u)
2717 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT3_ERR_MASK (0x00000800u)
2718 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT3_ERR_SHIFT (0x0000000Bu)
2719 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_PORT3_ERR_RESETVAL (0x00000000u)
2721 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_DEVICE_RST_INT_MASK (0x00010000u)
2722 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_DEVICE_RST_INT_SHIFT (0x00000010u)
2723 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_DEVICE_RST_INT_RESETVAL (0x00000000u)
2725 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICCR_RESETVAL (0x00000000u)
2727 /* rio_amu_icsr */
2729 #define CSL_SRIO_RIO_AMU_ICSR_CPRIVID_MASK (0x0000FFFFu)
2730 #define CSL_SRIO_RIO_AMU_ICSR_CPRIVID_SHIFT (0x00000000u)
2731 #define CSL_SRIO_RIO_AMU_ICSR_CPRIVID_RESETVAL (0x00000000u)
2733 #define CSL_SRIO_RIO_AMU_ICSR_RESETVAL (0x00000000u)
2735 /* rio_amu_iccr */
2737 #define CSL_SRIO_RIO_AMU_ICCR_CPRIVID_MASK (0x0000FFFFu)
2738 #define CSL_SRIO_RIO_AMU_ICCR_CPRIVID_SHIFT (0x00000000u)
2739 #define CSL_SRIO_RIO_AMU_ICCR_CPRIVID_RESETVAL (0x00000000u)
2741 #define CSL_SRIO_RIO_AMU_ICCR_RESETVAL (0x00000000u)
2743 /* rio_lsu0_module_icrr */
2745 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR0_MASK (0x0000000Fu)
2746 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR0_SHIFT (0x00000000u)
2747 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR0_RESETVAL (0x00000000u)
2749 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR1_MASK (0x000000F0u)
2750 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR1_SHIFT (0x00000004u)
2751 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR1_RESETVAL (0x00000000u)
2753 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR2_MASK (0x00000F00u)
2754 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR2_SHIFT (0x00000008u)
2755 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR2_RESETVAL (0x00000000u)
2757 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR3_MASK (0x0000F000u)
2758 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR3_SHIFT (0x0000000Cu)
2759 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR3_RESETVAL (0x00000000u)
2761 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR4_MASK (0x000F0000u)
2762 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR4_SHIFT (0x00000010u)
2763 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR4_RESETVAL (0x00000000u)
2765 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR5_MASK (0x00F00000u)
2766 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR5_SHIFT (0x00000014u)
2767 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR5_RESETVAL (0x00000000u)
2769 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR6_MASK (0x0F000000u)
2770 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR6_SHIFT (0x00000018u)
2771 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR6_RESETVAL (0x00000000u)
2773 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR7_MASK (0xF0000000u)
2774 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR7_SHIFT (0x0000001Cu)
2775 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_ICR7_RESETVAL (0x00000000u)
2777 #define CSL_SRIO_RIO_LSU0_MODULE_ICRR_RESETVAL (0x00000000u)
2779 /* rio_lsu1_module_icrr */
2781 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR0_MASK (0x0000000Fu)
2782 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR0_SHIFT (0x00000000u)
2783 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR0_RESETVAL (0x00000000u)
2785 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR1_MASK (0x000000F0u)
2786 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR1_SHIFT (0x00000004u)
2787 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR1_RESETVAL (0x00000000u)
2789 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR2_MASK (0x00000F00u)
2790 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR2_SHIFT (0x00000008u)
2791 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR2_RESETVAL (0x00000000u)
2793 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR3_MASK (0x0000F000u)
2794 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR3_SHIFT (0x0000000Cu)
2795 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR3_RESETVAL (0x00000000u)
2797 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR4_MASK (0x000F0000u)
2798 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR4_SHIFT (0x00000010u)
2799 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR4_RESETVAL (0x00000000u)
2801 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR5_MASK (0x00F00000u)
2802 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR5_SHIFT (0x00000014u)
2803 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR5_RESETVAL (0x00000000u)
2805 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR6_MASK (0x0F000000u)
2806 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR6_SHIFT (0x00000018u)
2807 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR6_RESETVAL (0x00000000u)
2809 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR7_MASK (0xF0000000u)
2810 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR7_SHIFT (0x0000001Cu)
2811 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_ICR7_RESETVAL (0x00000000u)
2813 #define CSL_SRIO_RIO_LSU1_MODULE_ICRR_RESETVAL (0x00000000u)
2815 /* rio_err_rst_evnt_icrr */
2817 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_ICR0_MASK (0x0000000Fu)
2818 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_ICR0_SHIFT (0x00000000u)
2819 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_ICR0_RESETVAL (0x00000000u)
2821 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_ICR1_MASK (0x000000F0u)
2822 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_ICR1_SHIFT (0x00000004u)
2823 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_ICR1_RESETVAL (0x00000000u)
2825 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_ICR2_MASK (0x00000F00u)
2826 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_ICR2_SHIFT (0x00000008u)
2827 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_ICR2_RESETVAL (0x00000000u)
2829 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR_RESETVAL (0x00000000u)
2831 /* rio_err_rst_evnt_icrr2 */
2833 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR8_MASK (0x0000000Fu)
2834 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR8_SHIFT (0x00000000u)
2835 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR8_RESETVAL (0x00000000u)
2837 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR9_MASK (0x000000F0u)
2838 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR9_SHIFT (0x00000004u)
2839 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR9_RESETVAL (0x00000000u)
2841 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR10_MASK (0x00000F00u)
2842 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR10_SHIFT (0x00000008u)
2843 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR10_RESETVAL (0x00000000u)
2845 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR11_MASK (0x0000F000u)
2846 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR11_SHIFT (0x0000000Cu)
2847 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_ICR11_RESETVAL (0x00000000u)
2849 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR2_RESETVAL (0x00000000u)
2851 /* rio_err_rst_evnt_icrr3 */
2853 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR3_ICR16_MASK (0x0000000Fu)
2854 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR3_ICR16_SHIFT (0x00000000u)
2855 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR3_ICR16_RESETVAL (0x00000000u)
2857 #define CSL_SRIO_RIO_ERR_RST_EVNT_ICRR3_RESETVAL (0x00000000u)
2859 /* rio_amu_icrr1 */
2861 #define CSL_SRIO_RIO_AMU_ICRR1_ICR0_MASK (0x0000000Fu)
2862 #define CSL_SRIO_RIO_AMU_ICRR1_ICR0_SHIFT (0x00000000u)
2863 #define CSL_SRIO_RIO_AMU_ICRR1_ICR0_RESETVAL (0x00000000u)
2865 #define CSL_SRIO_RIO_AMU_ICRR1_ICR1_MASK (0x000000F0u)
2866 #define CSL_SRIO_RIO_AMU_ICRR1_ICR1_SHIFT (0x00000004u)
2867 #define CSL_SRIO_RIO_AMU_ICRR1_ICR1_RESETVAL (0x00000000u)
2869 #define CSL_SRIO_RIO_AMU_ICRR1_ICR2_MASK (0x00000F00u)
2870 #define CSL_SRIO_RIO_AMU_ICRR1_ICR2_SHIFT (0x00000008u)
2871 #define CSL_SRIO_RIO_AMU_ICRR1_ICR2_RESETVAL (0x00000000u)
2873 #define CSL_SRIO_RIO_AMU_ICRR1_ICR3_MASK (0x0000F000u)
2874 #define CSL_SRIO_RIO_AMU_ICRR1_ICR3_SHIFT (0x0000000Cu)
2875 #define CSL_SRIO_RIO_AMU_ICRR1_ICR3_RESETVAL (0x00000000u)
2877 #define CSL_SRIO_RIO_AMU_ICRR1_ICR4_MASK (0x000F0000u)
2878 #define CSL_SRIO_RIO_AMU_ICRR1_ICR4_SHIFT (0x00000010u)
2879 #define CSL_SRIO_RIO_AMU_ICRR1_ICR4_RESETVAL (0x00000000u)
2881 #define CSL_SRIO_RIO_AMU_ICRR1_ICR5_MASK (0x00F00000u)
2882 #define CSL_SRIO_RIO_AMU_ICRR1_ICR5_SHIFT (0x00000014u)
2883 #define CSL_SRIO_RIO_AMU_ICRR1_ICR5_RESETVAL (0x00000000u)
2885 #define CSL_SRIO_RIO_AMU_ICRR1_ICR6_MASK (0x0F000000u)
2886 #define CSL_SRIO_RIO_AMU_ICRR1_ICR6_SHIFT (0x00000018u)
2887 #define CSL_SRIO_RIO_AMU_ICRR1_ICR6_RESETVAL (0x00000000u)
2889 #define CSL_SRIO_RIO_AMU_ICRR1_ICR7_MASK (0xF0000000u)
2890 #define CSL_SRIO_RIO_AMU_ICRR1_ICR7_SHIFT (0x0000001Cu)
2891 #define CSL_SRIO_RIO_AMU_ICRR1_ICR7_RESETVAL (0x00000000u)
2893 #define CSL_SRIO_RIO_AMU_ICRR1_RESETVAL (0x00000000u)
2895 /* rio_amu_icrr2 */
2897 #define CSL_SRIO_RIO_AMU_ICRR2_ICR8_MASK (0x0000000Fu)
2898 #define CSL_SRIO_RIO_AMU_ICRR2_ICR8_SHIFT (0x00000000u)
2899 #define CSL_SRIO_RIO_AMU_ICRR2_ICR8_RESETVAL (0x00000000u)
2901 #define CSL_SRIO_RIO_AMU_ICRR2_ICR9_MASK (0x000000F0u)
2902 #define CSL_SRIO_RIO_AMU_ICRR2_ICR9_SHIFT (0x00000004u)
2903 #define CSL_SRIO_RIO_AMU_ICRR2_ICR9_RESETVAL (0x00000000u)
2905 #define CSL_SRIO_RIO_AMU_ICRR2_ICR10_MASK (0x00000F00u)
2906 #define CSL_SRIO_RIO_AMU_ICRR2_ICR10_SHIFT (0x00000008u)
2907 #define CSL_SRIO_RIO_AMU_ICRR2_ICR10_RESETVAL (0x00000000u)
2909 #define CSL_SRIO_RIO_AMU_ICRR2_ICR11_MASK (0x0000F000u)
2910 #define CSL_SRIO_RIO_AMU_ICRR2_ICR11_SHIFT (0x0000000Cu)
2911 #define CSL_SRIO_RIO_AMU_ICRR2_ICR11_RESETVAL (0x00000000u)
2913 #define CSL_SRIO_RIO_AMU_ICRR2_ICR12_MASK (0x000F0000u)
2914 #define CSL_SRIO_RIO_AMU_ICRR2_ICR12_SHIFT (0x00000010u)
2915 #define CSL_SRIO_RIO_AMU_ICRR2_ICR12_RESETVAL (0x00000000u)
2917 #define CSL_SRIO_RIO_AMU_ICRR2_ICR13_MASK (0x00F00000u)
2918 #define CSL_SRIO_RIO_AMU_ICRR2_ICR13_SHIFT (0x00000014u)
2919 #define CSL_SRIO_RIO_AMU_ICRR2_ICR13_RESETVAL (0x00000000u)
2921 #define CSL_SRIO_RIO_AMU_ICRR2_ICR14_MASK (0x0F000000u)
2922 #define CSL_SRIO_RIO_AMU_ICRR2_ICR14_SHIFT (0x00000018u)
2923 #define CSL_SRIO_RIO_AMU_ICRR2_ICR14_RESETVAL (0x00000000u)
2925 #define CSL_SRIO_RIO_AMU_ICRR2_ICR15_MASK (0xF0000000u)
2926 #define CSL_SRIO_RIO_AMU_ICRR2_ICR15_SHIFT (0x0000001Cu)
2927 #define CSL_SRIO_RIO_AMU_ICRR2_ICR15_RESETVAL (0x00000000u)
2929 #define CSL_SRIO_RIO_AMU_ICRR2_RESETVAL (0x00000000u)
2931 /* rio_interrupt_ctl */
2933 #define CSL_SRIO_RIO_INTERRUPT_CTL_DBLL_ROUTE_MASK (0x00000001u)
2934 #define CSL_SRIO_RIO_INTERRUPT_CTL_DBLL_ROUTE_SHIFT (0x00000000u)
2935 #define CSL_SRIO_RIO_INTERRUPT_CTL_DBLL_ROUTE_RESETVAL (0x00000000u)
2937 #define CSL_SRIO_RIO_INTERRUPT_CTL_RESETVAL (0x00000000u)
2939 /* rio_intdst_decode */
2941 #define CSL_SRIO_RIO_INTDST_DECODE_ISDR_MASK (0xFFFFFFFFu)
2942 #define CSL_SRIO_RIO_INTDST_DECODE_ISDR_SHIFT (0x00000000u)
2943 #define CSL_SRIO_RIO_INTDST_DECODE_ISDR_RESETVAL (0x00000000u)
2945 #define CSL_SRIO_RIO_INTDST_DECODE_RESETVAL (0x00000000u)
2947 /* rio_intdst_rate_cnt */
2949 #define CSL_SRIO_RIO_INTDST_RATE_CNT_COUNT_DOWN_VALUE_MASK (0xFFFFFFFFu)
2950 #define CSL_SRIO_RIO_INTDST_RATE_CNT_COUNT_DOWN_VALUE_SHIFT (0x00000000u)
2951 #define CSL_SRIO_RIO_INTDST_RATE_CNT_COUNT_DOWN_VALUE_RESETVAL (0x00000000u)
2953 #define CSL_SRIO_RIO_INTDST_RATE_CNT_RESETVAL (0x00000000u)
2955 /* rio_intdst_rate_dis */
2957 #define CSL_SRIO_RIO_INTDST_RATE_DIS_RATEN_DIS_MASK (0x0000FFFFu)
2958 #define CSL_SRIO_RIO_INTDST_RATE_DIS_RATEN_DIS_SHIFT (0x00000000u)
2959 #define CSL_SRIO_RIO_INTDST_RATE_DIS_RATEN_DIS_RESETVAL (0x00000000u)
2961 #define CSL_SRIO_RIO_INTDST_RATE_DIS_RESETVAL (0x00000000u)
2963 /* rio_amu_srcid_map */
2965 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID0_8_MASK (0x0000000Fu)
2966 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID0_8_SHIFT (0x00000000u)
2967 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID0_8_RESETVAL (0x00000000u)
2969 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID1_9_MASK (0x000000F0u)
2970 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID1_9_SHIFT (0x00000004u)
2971 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID1_9_RESETVAL (0x00000000u)
2973 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID2_10_MASK (0x00000F00u)
2974 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID2_10_SHIFT (0x00000008u)
2975 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID2_10_RESETVAL (0x00000000u)
2977 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID3_11_MASK (0x0000F000u)
2978 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID3_11_SHIFT (0x0000000Cu)
2979 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID3_11_RESETVAL (0x00000000u)
2981 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID4_12_MASK (0x000F0000u)
2982 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID4_12_SHIFT (0x00000010u)
2983 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID4_12_RESETVAL (0x00000000u)
2985 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID5_13_MASK (0x00F00000u)
2986 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID5_13_SHIFT (0x00000014u)
2987 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID5_13_RESETVAL (0x00000000u)
2989 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID6_14_MASK (0x0F000000u)
2990 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID6_14_SHIFT (0x00000018u)
2991 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID6_14_RESETVAL (0x00000000u)
2993 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID7_15_MASK (0xF0000000u)
2994 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID7_15_SHIFT (0x0000001Cu)
2995 #define CSL_SRIO_RIO_AMU_SRCID_MAP_CPRIVID7_15_RESETVAL (0x00000000u)
2997 #define CSL_SRIO_RIO_AMU_SRCID_MAP_RESETVAL (0x00000000u)
2999 /* rio_amu_priority_map */
3001 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI0_MASK (0x0000000Fu)
3002 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI0_SHIFT (0x00000000u)
3003 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI0_RESETVAL (0x00000000u)
3005 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI1_MASK (0x000000F0u)
3006 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI1_SHIFT (0x00000004u)
3007 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI1_RESETVAL (0x00000000u)
3009 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI2_MASK (0x00000F00u)
3010 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI2_SHIFT (0x00000008u)
3011 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI2_RESETVAL (0x00000000u)
3013 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI3_MASK (0x0000F000u)
3014 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI3_SHIFT (0x0000000Cu)
3015 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI3_RESETVAL (0x00000000u)
3017 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI4_MASK (0x000F0000u)
3018 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI4_SHIFT (0x00000010u)
3019 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI4_RESETVAL (0x00000000u)
3021 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI5_MASK (0x00F00000u)
3022 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI5_SHIFT (0x00000014u)
3023 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI5_RESETVAL (0x00000000u)
3025 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI6_MASK (0x0F000000u)
3026 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI6_SHIFT (0x00000018u)
3027 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI6_RESETVAL (0x00000000u)
3029 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI7_MASK (0xF0000000u)
3030 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI7_SHIFT (0x0000001Cu)
3031 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_DMA_PRI7_RESETVAL (0x00000000u)
3033 #define CSL_SRIO_RIO_AMU_PRIORITY_MAP_RESETVAL (0x00000000u)
3035 /* rio_amu_capt0_map */
3037 #define CSL_SRIO_RIO_AMU_CAPT0_MAP_TRANS_ADDRESS_MASK (0xFFFFFFFFu)
3038 #define CSL_SRIO_RIO_AMU_CAPT0_MAP_TRANS_ADDRESS_SHIFT (0x00000000u)
3039 #define CSL_SRIO_RIO_AMU_CAPT0_MAP_TRANS_ADDRESS_RESETVAL (0x00000000u)
3041 #define CSL_SRIO_RIO_AMU_CAPT0_MAP_RESETVAL (0x00000000u)
3043 /* rio_amu_capt1_map */
3045 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_CMSTID_MASK (0x000000FFu)
3046 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_CMSTID_SHIFT (0x00000000u)
3047 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_CMSTID_RESETVAL (0x00000000u)
3049 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_CPRIVID_MASK (0x00000F00u)
3050 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_CPRIVID_SHIFT (0x00000008u)
3051 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_CPRIVID_RESETVAL (0x00000000u)
3053 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_DOORBELL_INFO_MASK (0xFFFF0000u)
3054 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_DOORBELL_INFO_SHIFT (0x00000010u)
3055 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_DOORBELL_INFO_RESETVAL (0x00000000u)
3057 #define CSL_SRIO_RIO_AMU_CAPT1_MAP_RESETVAL (0x00000000u)
3059 /* rio_amu_window_pane */
3061 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_CMD_ENC_MASK (0x00000003u)
3062 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_CMD_ENC_SHIFT (0x00000000u)
3063 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_CMD_ENC_RESETVAL (0x00000000u)
3065 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_PORT_ID_MASK (0x0000000Cu)
3066 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_PORT_ID_SHIFT (0x00000002u)
3067 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_PORT_ID_RESETVAL (0x00000000u)
3069 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_ID_SIZE_MASK (0x0000C000u)
3070 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_ID_SIZE_SHIFT (0x0000000Eu)
3071 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_ID_SIZE_RESETVAL (0x00000000u)
3073 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_DESTID_MASK (0xFFFF0000u)
3074 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_DESTID_SHIFT (0x00000010u)
3075 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_DESTID_RESETVAL (0x00000000u)
3077 #define CSL_SRIO_RIO_AMU_WINDOW_PANE_RESETVAL (0x00000000u)
3079 /* rio_amu_flow_masks0 */
3081 #define CSL_SRIO_RIO_AMU_FLOW_MASKS0_AMU_FLOW_MASK_MASK (0x0000FFFFu)
3082 #define CSL_SRIO_RIO_AMU_FLOW_MASKS0_AMU_FLOW_MASK_SHIFT (0x00000000u)
3083 #define CSL_SRIO_RIO_AMU_FLOW_MASKS0_AMU_FLOW_MASK_RESETVAL (0x0000FFFFu)
3085 #define CSL_SRIO_RIO_AMU_FLOW_MASKS0_RESERVED_MASK (0xFFFF0000u)
3086 #define CSL_SRIO_RIO_AMU_FLOW_MASKS0_RESERVED_SHIFT (0x00000010u)
3087 #define CSL_SRIO_RIO_AMU_FLOW_MASKS0_RESERVED_RESETVAL (0x0000FFFFu)
3089 #define CSL_SRIO_RIO_AMU_FLOW_MASKS0_RESETVAL (0xFFFFFFFFu)
3091 /* rio_lsu_setup_reg0 */
3093 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU0_CNT_MASK (0x0000000Fu)
3094 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU0_CNT_SHIFT (0x00000000u)
3095 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU0_CNT_RESETVAL (0x00000004u)
3097 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU1_CNT_MASK (0x000000F0u)
3098 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU1_CNT_SHIFT (0x00000004u)
3099 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU1_CNT_RESETVAL (0x00000004u)
3101 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU2_CNT_MASK (0x00000F00u)
3102 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU2_CNT_SHIFT (0x00000008u)
3103 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU2_CNT_RESETVAL (0x00000004u)
3105 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU3_CNT_MASK (0x0000F000u)
3106 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU3_CNT_SHIFT (0x0000000Cu)
3107 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU3_CNT_RESETVAL (0x00000004u)
3109 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU4_CNT_MASK (0x000F0000u)
3110 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU4_CNT_SHIFT (0x00000010u)
3111 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU4_CNT_RESETVAL (0x00000004u)
3113 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU5_CNT_MASK (0x00F00000u)
3114 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU5_CNT_SHIFT (0x00000014u)
3115 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU5_CNT_RESETVAL (0x00000004u)
3117 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU6_CNT_MASK (0x0F000000u)
3118 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU6_CNT_SHIFT (0x00000018u)
3119 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU6_CNT_RESETVAL (0x00000004u)
3121 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU7_CNT_MASK (0xF0000000u)
3122 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU7_CNT_SHIFT (0x0000001Cu)
3123 #define CSL_SRIO_RIO_LSU_SETUP_REG0_LSU7_CNT_RESETVAL (0x00000004u)
3125 #define CSL_SRIO_RIO_LSU_SETUP_REG0_SHADOW_GRP0_MASK (0x0000001Fu)
3126 #define CSL_SRIO_RIO_LSU_SETUP_REG0_SHADOW_GRP0_SHIFT (0x00000000u)
3127 #define CSL_SRIO_RIO_LSU_SETUP_REG0_SHADOW_GRP0_RESETVAL (0x00000000u)
3129 #define CSL_SRIO_RIO_LSU_SETUP_REG0_SHADOW_GRP1_MASK (0x001F0000u)
3130 #define CSL_SRIO_RIO_LSU_SETUP_REG0_SHADOW_GRP1_SHIFT (0x00000010u)
3131 #define CSL_SRIO_RIO_LSU_SETUP_REG0_SHADOW_GRP1_RESETVAL (0x00000000u)
3133 #define CSL_SRIO_RIO_LSU_SETUP_REG0_RESETVAL (0x44444444u)
3135 /* rio_lsu_setup_reg1 */
3137 #define CSL_SRIO_RIO_LSU_SETUP_REG1_LSU_EDMA_MASK (0x000000FFu)
3138 #define CSL_SRIO_RIO_LSU_SETUP_REG1_LSU_EDMA_SHIFT (0x00000000u)
3139 #define CSL_SRIO_RIO_LSU_SETUP_REG1_LSU_EDMA_RESETVAL (0x00000000u)
3141 #define CSL_SRIO_RIO_LSU_SETUP_REG1_TIMEOUT_CNT_MASK (0x00000300u)
3142 #define CSL_SRIO_RIO_LSU_SETUP_REG1_TIMEOUT_CNT_SHIFT (0x00000008u)
3143 #define CSL_SRIO_RIO_LSU_SETUP_REG1_TIMEOUT_CNT_RESETVAL (0x00000000u)
3145 #define CSL_SRIO_RIO_LSU_SETUP_REG1_RESETVAL (0x00000000u)
3147 /* lsu_stat_reg */
3149 #define CSL_SRIO_LSU_STAT_REG_LSUX_STAT_MASK (0xFFFFFFFFu)
3150 #define CSL_SRIO_LSU_STAT_REG_LSUX_STAT_SHIFT (0x00000000u)
3151 #define CSL_SRIO_LSU_STAT_REG_LSUX_STAT_RESETVAL (0x00000000u)
3153 #define CSL_SRIO_LSU_STAT_REG_RESETVAL (0x00000000u)
3155 /* rio_lsu_flow_masks */
3157 #define CSL_SRIO_RIO_LSU_FLOW_MASKS_LSU_FLOW_MASK_MASK (0xFFFFFFFFu)
3158 #define CSL_SRIO_RIO_LSU_FLOW_MASKS_LSU_FLOW_MASK_SHIFT (0x00000000u)
3159 #define CSL_SRIO_RIO_LSU_FLOW_MASKS_LSU_FLOW_MASK_RESETVAL (u)
3161 #define CSL_SRIO_RIO_LSU_FLOW_MASKS_RESETVAL (0x00000000u)
3163 /* rio_supervisor_id */
3165 #define CSL_SRIO_RIO_SUPERVISOR_ID_16B_SUPRVSR_ID_MASK (0x0000FFFFu)
3166 #define CSL_SRIO_RIO_SUPERVISOR_ID_16B_SUPRVSR_ID_SHIFT (0x00000000u)
3167 #define CSL_SRIO_RIO_SUPERVISOR_ID_16B_SUPRVSR_ID_RESETVAL (0x00000000u)
3169 #define CSL_SRIO_RIO_SUPERVISOR_ID_8B_SUPRVSR_ID_MASK (0x00FF0000u)
3170 #define CSL_SRIO_RIO_SUPERVISOR_ID_8B_SUPRVSR_ID_SHIFT (0x00000010u)
3171 #define CSL_SRIO_RIO_SUPERVISOR_ID_8B_SUPRVSR_ID_RESETVAL (0x00000000u)
3173 #define CSL_SRIO_RIO_SUPERVISOR_ID_RESETVAL (0x00000000u)
3175 /* rio_flow_cntl */
3177 #define CSL_SRIO_RIO_FLOW_CNTL_FLOW_CNTL_ID_MASK (0x0000FFFFu)
3178 #define CSL_SRIO_RIO_FLOW_CNTL_FLOW_CNTL_ID_SHIFT (0x00000000u)
3179 #define CSL_SRIO_RIO_FLOW_CNTL_FLOW_CNTL_ID_RESETVAL (0x00000000u)
3181 #define CSL_SRIO_RIO_FLOW_CNTL_TT_MASK (0x00030000u)
3182 #define CSL_SRIO_RIO_FLOW_CNTL_TT_SHIFT (0x00000010u)
3183 #define CSL_SRIO_RIO_FLOW_CNTL_TT_RESETVAL (0x00000001u)
3185 #define CSL_SRIO_RIO_FLOW_CNTL_RESETVAL (0x00010000u)
3187 /* rio_tx_cppi_flow_masks */
3189 #define CSL_SRIO_RIO_TX_CPPI_FLOW_MASKS_TX_QUEUE_FLOW_MASK_MASK (0xFFFFFFFFu)
3190 #define CSL_SRIO_RIO_TX_CPPI_FLOW_MASKS_TX_QUEUE_FLOW_MASK_SHIFT (0x00000000u)
3191 #define CSL_SRIO_RIO_TX_CPPI_FLOW_MASKS_TX_QUEUE_FLOW_MASK_RESETVAL (u)
3193 #define CSL_SRIO_RIO_TX_CPPI_FLOW_MASKS_RESETVAL (0x00000000u)
3195 /* rio_tx_queue_sch_info */
3197 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE0_INFO_MASK (0x000000FFu)
3198 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE0_INFO_SHIFT (0x00000000u)
3199 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE0_INFO_RESETVAL (0x00000000u)
3201 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE1_INFO_MASK (0x0000FF00u)
3202 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE1_INFO_SHIFT (0x00000008u)
3203 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE1_INFO_RESETVAL (0x00000000u)
3205 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE2_INFO_MASK (0x00FF0000u)
3206 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE2_INFO_SHIFT (0x00000010u)
3207 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE2_INFO_RESETVAL (0x00000000u)
3209 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE3_INFO_MASK (0xFF000000u)
3210 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE3_INFO_SHIFT (0x00000018u)
3211 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_QUEUE3_INFO_RESETVAL (0x00000000u)
3213 #define CSL_SRIO_RIO_TX_QUEUE_SCH_INFO_RESETVAL (0x00000000u)
3215 /* rio_garbage_coll_qid0 */
3217 #define CSL_SRIO_RIO_GARBAGE_COLL_QID0_GARBAGE_QID_TOUT_MASK (0x00003FFFu)
3218 #define CSL_SRIO_RIO_GARBAGE_COLL_QID0_GARBAGE_QID_TOUT_SHIFT (0x00000000u)
3219 #define CSL_SRIO_RIO_GARBAGE_COLL_QID0_GARBAGE_QID_TOUT_RESETVAL (0x00000000u)
3221 #define CSL_SRIO_RIO_GARBAGE_COLL_QID0_GARBAGE_QID_LEN_MASK (0x3FFF0000u)
3222 #define CSL_SRIO_RIO_GARBAGE_COLL_QID0_GARBAGE_QID_LEN_SHIFT (0x00000010u)
3223 #define CSL_SRIO_RIO_GARBAGE_COLL_QID0_GARBAGE_QID_LEN_RESETVAL (0x00000000u)
3225 #define CSL_SRIO_RIO_GARBAGE_COLL_QID0_RESETVAL (0x00000000u)
3227 /* rio_garbage_coll_qid1 */
3229 #define CSL_SRIO_RIO_GARBAGE_COLL_QID1_GARBAGE_QID_TRANS_ERR_MASK (0x00003FFFu)
3230 #define CSL_SRIO_RIO_GARBAGE_COLL_QID1_GARBAGE_QID_TRANS_ERR_SHIFT (0x00000000u)
3231 #define CSL_SRIO_RIO_GARBAGE_COLL_QID1_GARBAGE_QID_TRANS_ERR_RESETVAL (0x00000000u)
3233 #define CSL_SRIO_RIO_GARBAGE_COLL_QID1_GARBAGE_QID_RETRY_MASK (0x3FFF0000u)
3234 #define CSL_SRIO_RIO_GARBAGE_COLL_QID1_GARBAGE_QID_RETRY_SHIFT (0x00000010u)
3235 #define CSL_SRIO_RIO_GARBAGE_COLL_QID1_GARBAGE_QID_RETRY_RESETVAL (0x00000000u)
3237 #define CSL_SRIO_RIO_GARBAGE_COLL_QID1_RESETVAL (0x00000000u)
3239 /* rio_garbage_coll_qid2 */
3241 #define CSL_SRIO_RIO_GARBAGE_COLL_QID2_GARBAGE_QID_SSIZE_MASK (0x00003FFFu)
3242 #define CSL_SRIO_RIO_GARBAGE_COLL_QID2_GARBAGE_QID_SSIZE_SHIFT (0x00000000u)
3243 #define CSL_SRIO_RIO_GARBAGE_COLL_QID2_GARBAGE_QID_SSIZE_RESETVAL (0x00000000u)
3245 #define CSL_SRIO_RIO_GARBAGE_COLL_QID2_GARBAGE_QID_PROG_MASK (0x3FFF0000u)
3246 #define CSL_SRIO_RIO_GARBAGE_COLL_QID2_GARBAGE_QID_PROG_SHIFT (0x00000010u)
3247 #define CSL_SRIO_RIO_GARBAGE_COLL_QID2_GARBAGE_QID_PROG_RESETVAL (0x00000000u)
3249 #define CSL_SRIO_RIO_GARBAGE_COLL_QID2_RESETVAL (0x00000000u)
3251 /* revision_reg */
3253 #define CSL_SRIO_REVISION_REG_REVMIN_MASK (0x0000003Fu)
3254 #define CSL_SRIO_REVISION_REG_REVMIN_SHIFT (0x00000000u)
3255 #define CSL_SRIO_REVISION_REG_REVMIN_RESETVAL (0x00000000u)
3257 #define CSL_SRIO_REVISION_REG_CUSTOM_MASK (0x000000C0u)
3258 #define CSL_SRIO_REVISION_REG_CUSTOM_SHIFT (0x00000006u)
3259 #define CSL_SRIO_REVISION_REG_CUSTOM_RESETVAL (0x00000000u)
3261 #define CSL_SRIO_REVISION_REG_REVMAJ_MASK (0x00000700u)
3262 #define CSL_SRIO_REVISION_REG_REVMAJ_SHIFT (0x00000008u)
3263 #define CSL_SRIO_REVISION_REG_REVMAJ_RESETVAL (0x00000001u)
3265 #define CSL_SRIO_REVISION_REG_REVRTL_MASK (0x0000F800u)
3266 #define CSL_SRIO_REVISION_REG_REVRTL_SHIFT (0x0000000Bu)
3267 #define CSL_SRIO_REVISION_REG_REVRTL_RESETVAL (0x00000019u)
3269 #define CSL_SRIO_REVISION_REG_FUNCTION_ID_MASK (0x0FFF0000u)
3270 #define CSL_SRIO_REVISION_REG_FUNCTION_ID_SHIFT (0x00000010u)
3271 #define CSL_SRIO_REVISION_REG_FUNCTION_ID_RESETVAL (0x00000E5Au)
3273 #define CSL_SRIO_REVISION_REG_BU_MASK (0x30000000u)
3274 #define CSL_SRIO_REVISION_REG_BU_SHIFT (0x0000001Cu)
3275 #define CSL_SRIO_REVISION_REG_BU_RESETVAL (0x00000000u)
3277 #define CSL_SRIO_REVISION_REG_RESERVED_MASK (0xC0000000u)
3278 #define CSL_SRIO_REVISION_REG_RESERVED_SHIFT (0x0000001Eu)
3279 #define CSL_SRIO_REVISION_REG_RESERVED_RESETVAL (0x00000001u)
3281 #define CSL_SRIO_REVISION_REG_RESETVAL (0x4E5AC900u)
3283 /* perf_control_reg */
3285 #define CSL_SRIO_PERF_CONTROL_REG_TIMEOUT_CNT_MASK (0x0000FFFFu)
3286 #define CSL_SRIO_PERF_CONTROL_REG_TIMEOUT_CNT_SHIFT (0x00000000u)
3287 #define CSL_SRIO_PERF_CONTROL_REG_TIMEOUT_CNT_RESETVAL (0x00000000u)
3289 #define CSL_SRIO_PERF_CONTROL_REG_WARB_FIFO_DEPTH_MASK (0x003F0000u)
3290 #define CSL_SRIO_PERF_CONTROL_REG_WARB_FIFO_DEPTH_SHIFT (0x00000010u)
3291 #define CSL_SRIO_PERF_CONTROL_REG_WARB_FIFO_DEPTH_RESETVAL (0x00000020u)
3293 #define CSL_SRIO_PERF_CONTROL_REG_RESETVAL (0x00200000u)
3295 /* emulation_control_reg */
3297 #define CSL_SRIO_EMULATION_CONTROL_REG_FREE_MASK (0x00000001u)
3298 #define CSL_SRIO_EMULATION_CONTROL_REG_FREE_SHIFT (0x00000000u)
3299 #define CSL_SRIO_EMULATION_CONTROL_REG_FREE_RESETVAL (0x00000000u)
3301 #define CSL_SRIO_EMULATION_CONTROL_REG_SOFT_MASK (0x00000002u)
3302 #define CSL_SRIO_EMULATION_CONTROL_REG_SOFT_SHIFT (0x00000001u)
3303 #define CSL_SRIO_EMULATION_CONTROL_REG_SOFT_RESETVAL (0x00000000u)
3305 #define CSL_SRIO_EMULATION_CONTROL_REG_LOOPBACK_EN_MASK (0x80000000u)
3306 #define CSL_SRIO_EMULATION_CONTROL_REG_LOOPBACK_EN_SHIFT (0x0000001Fu)
3307 #define CSL_SRIO_EMULATION_CONTROL_REG_LOOPBACK_EN_RESETVAL (0x00000001u)
3309 #define CSL_SRIO_EMULATION_CONTROL_REG_RESETVAL (0x80000000u)
3311 /* priority_control_reg */
3313 #define CSL_SRIO_PRIORITY_CONTROL_REG_TX_PRIORITY_MASK (0x00000007u)
3314 #define CSL_SRIO_PRIORITY_CONTROL_REG_TX_PRIORITY_SHIFT (0x00000000u)
3315 #define CSL_SRIO_PRIORITY_CONTROL_REG_TX_PRIORITY_RESETVAL (0x00000000u)
3317 #define CSL_SRIO_PRIORITY_CONTROL_REG_RX_PRIORITY_MASK (0x00070000u)
3318 #define CSL_SRIO_PRIORITY_CONTROL_REG_RX_PRIORITY_SHIFT (0x00000010u)
3319 #define CSL_SRIO_PRIORITY_CONTROL_REG_RX_PRIORITY_RESETVAL (0x00000000u)
3321 #define CSL_SRIO_PRIORITY_CONTROL_REG_RESETVAL (0x00000000u)
3323 /* qm_base_address_reg */
3325 #define CSL_SRIO_QM_BASE_ADDRESS_REG_QM_BASE_MASK (0xFFFFFFFFu)
3326 #define CSL_SRIO_QM_BASE_ADDRESS_REG_QM_BASE_SHIFT (0x00000000u)
3327 #define CSL_SRIO_QM_BASE_ADDRESS_REG_QM_BASE_RESETVAL (0x00000000u)
3329 #define CSL_SRIO_QM_BASE_ADDRESS_REG_RESETVAL (0x00000000u)
3331 /* tx_channel_scheduler_config_reg */
3333 #define CSL_SRIO_TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY_MASK (0x00000003u)
3334 #define CSL_SRIO_TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY_SHIFT (0x00000000u)
3335 #define CSL_SRIO_TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY_RESETVAL (0x00000000u)
3337 #define CSL_SRIO_TX_CHANNEL_SCHEDULER_CONFIG_REG_RESETVAL (0x00000000u)
3339 /* rio_dev_id */
3341 #define CSL_SRIO_RIO_DEV_ID_DEV_ID_MASK (0xFFFF0000u)
3342 #define CSL_SRIO_RIO_DEV_ID_DEV_ID_SHIFT (0x00000010u)
3343 #define CSL_SRIO_RIO_DEV_ID_DEV_ID_RESETVAL (0x00000000u)
3345 #define CSL_SRIO_RIO_DEV_ID_DEV_VEN_ID_MASK (0x0000FFFFu)
3346 #define CSL_SRIO_RIO_DEV_ID_DEV_VEN_ID_SHIFT (0x00000000u)
3347 #define CSL_SRIO_RIO_DEV_ID_DEV_VEN_ID_RESETVAL (0x00000030u)
3349 #define CSL_SRIO_RIO_DEV_ID_RESETVAL (0x00000030u)
3351 /* rio_dev_info */
3353 #define CSL_SRIO_RIO_DEV_INFO_DEVICE_REV_MASK (0xFFFFFFFFu)
3354 #define CSL_SRIO_RIO_DEV_INFO_DEVICE_REV_SHIFT (0x00000000u)
3355 #define CSL_SRIO_RIO_DEV_INFO_DEVICE_REV_RESETVAL (0x00000000u)
3357 #define CSL_SRIO_RIO_DEV_INFO_RESETVAL (0x00000000u)
3359 /* rio_asbly_id */
3361 #define CSL_SRIO_RIO_ASBLY_ID_ASBLY_ID_MASK (0xFFFF0000u)
3362 #define CSL_SRIO_RIO_ASBLY_ID_ASBLY_ID_SHIFT (0x00000010u)
3363 #define CSL_SRIO_RIO_ASBLY_ID_ASBLY_ID_RESETVAL (0x00000000u)
3365 #define CSL_SRIO_RIO_ASBLY_ID_ASBLY_VEN_ID_MASK (0x0000FFFFu)
3366 #define CSL_SRIO_RIO_ASBLY_ID_ASBLY_VEN_ID_SHIFT (0x00000000u)
3367 #define CSL_SRIO_RIO_ASBLY_ID_ASBLY_VEN_ID_RESETVAL (0x00000030u)
3369 #define CSL_SRIO_RIO_ASBLY_ID_RESETVAL (0x00000030u)
3371 /* rio_asbly_info */
3373 #define CSL_SRIO_RIO_ASBLY_INFO_ASBLY_REV_MASK (0xFFFF0000u)
3374 #define CSL_SRIO_RIO_ASBLY_INFO_ASBLY_REV_SHIFT (0x00000010u)
3375 #define CSL_SRIO_RIO_ASBLY_INFO_ASBLY_REV_RESETVAL (0x00000000u)
3377 #define CSL_SRIO_RIO_ASBLY_INFO_EXT_FEAT_PTR_MASK (0x0000FFFFu)
3378 #define CSL_SRIO_RIO_ASBLY_INFO_EXT_FEAT_PTR_SHIFT (0x00000000u)
3379 #define CSL_SRIO_RIO_ASBLY_INFO_EXT_FEAT_PTR_RESETVAL (0x00000100u)
3381 #define CSL_SRIO_RIO_ASBLY_INFO_RESETVAL (0x00000100u)
3383 /* rio_pe_feat */
3385 #define CSL_SRIO_RIO_PE_FEAT_BRDG_MASK (0x80000000u)
3386 #define CSL_SRIO_RIO_PE_FEAT_BRDG_SHIFT (0x0000001Fu)
3387 #define CSL_SRIO_RIO_PE_FEAT_BRDG_RESETVAL (0x00000000u)
3389 #define CSL_SRIO_RIO_PE_FEAT_MEM_MASK (0x40000000u)
3390 #define CSL_SRIO_RIO_PE_FEAT_MEM_SHIFT (0x0000001Eu)
3391 #define CSL_SRIO_RIO_PE_FEAT_MEM_RESETVAL (0x00000001u)
3393 #define CSL_SRIO_RIO_PE_FEAT_PROC_MASK (0x20000000u)
3394 #define CSL_SRIO_RIO_PE_FEAT_PROC_SHIFT (0x0000001Du)
3395 #define CSL_SRIO_RIO_PE_FEAT_PROC_RESETVAL (0x00000001u)
3397 #define CSL_SRIO_RIO_PE_FEAT_SW_MASK (0x10000000u)
3398 #define CSL_SRIO_RIO_PE_FEAT_SW_SHIFT (0x0000001Cu)
3399 #define CSL_SRIO_RIO_PE_FEAT_SW_RESETVAL (0x00000000u)
3401 #define CSL_SRIO_RIO_PE_FEAT_MULT_P_MASK (0x08000000u)
3402 #define CSL_SRIO_RIO_PE_FEAT_MULT_P_SHIFT (0x0000001Bu)
3403 #define CSL_SRIO_RIO_PE_FEAT_MULT_P_RESETVAL (0x00000000u)
3405 #define CSL_SRIO_RIO_PE_FEAT_FLOW_ARB_MASK (0x00000800u)
3406 #define CSL_SRIO_RIO_PE_FEAT_FLOW_ARB_SHIFT (0x0000000Bu)
3407 #define CSL_SRIO_RIO_PE_FEAT_FLOW_ARB_RESETVAL (0x00000000u)
3409 #define CSL_SRIO_RIO_PE_FEAT_MC_MASK (0x00000400u)
3410 #define CSL_SRIO_RIO_PE_FEAT_MC_SHIFT (0x0000000Au)
3411 #define CSL_SRIO_RIO_PE_FEAT_MC_RESETVAL (0x00000000u)
3413 #define CSL_SRIO_RIO_PE_FEAT_ERTC_MASK (0x00000200u)
3414 #define CSL_SRIO_RIO_PE_FEAT_ERTC_SHIFT (0x00000009u)
3415 #define CSL_SRIO_RIO_PE_FEAT_ERTC_RESETVAL (0x00000000u)
3417 #define CSL_SRIO_RIO_PE_FEAT_SRTC_MASK (0x00000100u)
3418 #define CSL_SRIO_RIO_PE_FEAT_SRTC_SHIFT (0x00000008u)
3419 #define CSL_SRIO_RIO_PE_FEAT_SRTC_RESETVAL (0x00000000u)
3421 #define CSL_SRIO_RIO_PE_FEAT_FLOW_CTRL_MASK (0x00000080u)
3422 #define CSL_SRIO_RIO_PE_FEAT_FLOW_CTRL_SHIFT (0x00000007u)
3423 #define CSL_SRIO_RIO_PE_FEAT_FLOW_CTRL_RESETVAL (0x00000000u)
3425 #define CSL_SRIO_RIO_PE_FEAT_CRF_MASK (0x00000020u)
3426 #define CSL_SRIO_RIO_PE_FEAT_CRF_SHIFT (0x00000005u)
3427 #define CSL_SRIO_RIO_PE_FEAT_CRF_RESETVAL (0x00000000u)
3429 #define CSL_SRIO_RIO_PE_FEAT_CTLS_MASK (0x00000010u)
3430 #define CSL_SRIO_RIO_PE_FEAT_CTLS_SHIFT (0x00000004u)
3431 #define CSL_SRIO_RIO_PE_FEAT_CTLS_RESETVAL (0x00000000u)
3433 #define CSL_SRIO_RIO_PE_FEAT_EXT_FEA_MASK (0x00000008u)
3434 #define CSL_SRIO_RIO_PE_FEAT_EXT_FEA_SHIFT (0x00000003u)
3435 #define CSL_SRIO_RIO_PE_FEAT_EXT_FEA_RESETVAL (0x00000000u)
3437 #define CSL_SRIO_RIO_PE_FEAT_EXT_AS_MASK (0x00000007u)
3438 #define CSL_SRIO_RIO_PE_FEAT_EXT_AS_SHIFT (0x00000000u)
3439 #define CSL_SRIO_RIO_PE_FEAT_EXT_AS_RESETVAL (0x00000000u)
3441 #define CSL_SRIO_RIO_PE_FEAT_RESETVAL (0x60000000u)
3443 /* rio_sw_port */
3445 #define CSL_SRIO_RIO_SW_PORT_PORT_TOTAL_MASK (0x0000FF00u)
3446 #define CSL_SRIO_RIO_SW_PORT_PORT_TOTAL_SHIFT (0x00000008u)
3447 #define CSL_SRIO_RIO_SW_PORT_PORT_TOTAL_RESETVAL (0x00000004u)
3449 #define CSL_SRIO_RIO_SW_PORT_PORT_NUM_MASK (0x000000FFu)
3450 #define CSL_SRIO_RIO_SW_PORT_PORT_NUM_SHIFT (0x00000000u)
3451 #define CSL_SRIO_RIO_SW_PORT_PORT_NUM_RESETVAL (0x00000000u)
3453 #define CSL_SRIO_RIO_SW_PORT_RESETVAL (0x00000400u)
3455 /* rio_src_op */
3457 #define CSL_SRIO_RIO_SRC_OP_G_READ_MASK (0x80000000u)
3458 #define CSL_SRIO_RIO_SRC_OP_G_READ_SHIFT (0x0000001Fu)
3459 #define CSL_SRIO_RIO_SRC_OP_G_READ_RESETVAL (0x00000000u)
3461 #define CSL_SRIO_RIO_SRC_OP_G_IREAD_MASK (0x40000000u)
3462 #define CSL_SRIO_RIO_SRC_OP_G_IREAD_SHIFT (0x0000001Eu)
3463 #define CSL_SRIO_RIO_SRC_OP_G_IREAD_RESETVAL (0x00000000u)
3465 #define CSL_SRIO_RIO_SRC_OP_G_READ_OWN_MASK (0x20000000u)
3466 #define CSL_SRIO_RIO_SRC_OP_G_READ_OWN_SHIFT (0x0000001Du)
3467 #define CSL_SRIO_RIO_SRC_OP_G_READ_OWN_RESETVAL (0x00000000u)
3469 #define CSL_SRIO_RIO_SRC_OP_G_DC_INVALIDATE_MASK (0x10000000u)
3470 #define CSL_SRIO_RIO_SRC_OP_G_DC_INVALIDATE_SHIFT (0x0000001Cu)
3471 #define CSL_SRIO_RIO_SRC_OP_G_DC_INVALIDATE_RESETVAL (0x00000000u)
3473 #define CSL_SRIO_RIO_SRC_OP_G_CASTOUT_MASK (0x08000000u)
3474 #define CSL_SRIO_RIO_SRC_OP_G_CASTOUT_SHIFT (0x0000001Bu)
3475 #define CSL_SRIO_RIO_SRC_OP_G_CASTOUT_RESETVAL (0x00000000u)
3477 #define CSL_SRIO_RIO_SRC_OP_G_DC_FLUSH_MASK (0x04000000u)
3478 #define CSL_SRIO_RIO_SRC_OP_G_DC_FLUSH_SHIFT (0x0000001Au)
3479 #define CSL_SRIO_RIO_SRC_OP_G_DC_FLUSH_RESETVAL (0x00000000u)
3481 #define CSL_SRIO_RIO_SRC_OP_G_IO_READ_MASK (0x02000000u)
3482 #define CSL_SRIO_RIO_SRC_OP_G_IO_READ_SHIFT (0x00000019u)
3483 #define CSL_SRIO_RIO_SRC_OP_G_IO_READ_RESETVAL (0x00000000u)
3485 #define CSL_SRIO_RIO_SRC_OP_G_IC_INVALIDATE_MASK (0x01000000u)
3486 #define CSL_SRIO_RIO_SRC_OP_G_IC_INVALIDATE_SHIFT (0x00000018u)
3487 #define CSL_SRIO_RIO_SRC_OP_G_IC_INVALIDATE_RESETVAL (0x00000000u)
3489 #define CSL_SRIO_RIO_SRC_OP_G_TLB_INVALIDATE_MASK (0x00800000u)
3490 #define CSL_SRIO_RIO_SRC_OP_G_TLB_INVALIDATE_SHIFT (0x00000017u)
3491 #define CSL_SRIO_RIO_SRC_OP_G_TLB_INVALIDATE_RESETVAL (0x00000000u)
3493 #define CSL_SRIO_RIO_SRC_OP_G_TLB_SYNC_MASK (0x00400000u)
3494 #define CSL_SRIO_RIO_SRC_OP_G_TLB_SYNC_SHIFT (0x00000016u)
3495 #define CSL_SRIO_RIO_SRC_OP_G_TLB_SYNC_RESETVAL (0x00000000u)
3497 #define CSL_SRIO_RIO_SRC_OP_G_RIO_RSVD_10_MASK (0x00200000u)
3498 #define CSL_SRIO_RIO_SRC_OP_G_RIO_RSVD_10_SHIFT (0x00000015u)
3499 #define CSL_SRIO_RIO_SRC_OP_G_RIO_RSVD_10_RESETVAL (0x00000000u)
3501 #define CSL_SRIO_RIO_SRC_OP_G_RIO_RSVD_11_MASK (0x00100000u)
3502 #define CSL_SRIO_RIO_SRC_OP_G_RIO_RSVD_11_SHIFT (0x00000014u)
3503 #define CSL_SRIO_RIO_SRC_OP_G_RIO_RSVD_11_RESETVAL (0x00000000u)
3505 #define CSL_SRIO_RIO_SRC_OP_DS_TM_MASK (0x00080000u)
3506 #define CSL_SRIO_RIO_SRC_OP_DS_TM_SHIFT (0x00000013u)
3507 #define CSL_SRIO_RIO_SRC_OP_DS_TM_RESETVAL (0x00000000u)
3509 #define CSL_SRIO_RIO_SRC_OP_DS_MASK (0x00040000u)
3510 #define CSL_SRIO_RIO_SRC_OP_DS_SHIFT (0x00000012u)
3511 #define CSL_SRIO_RIO_SRC_OP_DS_RESETVAL (0x00000000u)
3513 #define CSL_SRIO_RIO_SRC_OP_IMPLEMENT_DEF_MASK (0x00030000u)
3514 #define CSL_SRIO_RIO_SRC_OP_IMPLEMENT_DEF_SHIFT (0x00000010u)
3515 #define CSL_SRIO_RIO_SRC_OP_IMPLEMENT_DEF_RESETVAL (0x00000000u)
3517 #define CSL_SRIO_RIO_SRC_OP_READ_MASK (0x00008000u)
3518 #define CSL_SRIO_RIO_SRC_OP_READ_SHIFT (0x0000000Fu)
3519 #define CSL_SRIO_RIO_SRC_OP_READ_RESETVAL (0x00000000u)
3521 #define CSL_SRIO_RIO_SRC_OP_WRITE_MASK (0x00004000u)
3522 #define CSL_SRIO_RIO_SRC_OP_WRITE_SHIFT (0x0000000Eu)
3523 #define CSL_SRIO_RIO_SRC_OP_WRITE_RESETVAL (0x00000000u)
3525 #define CSL_SRIO_RIO_SRC_OP_STRM_WR_MASK (0x00002000u)
3526 #define CSL_SRIO_RIO_SRC_OP_STRM_WR_SHIFT (0x0000000Du)
3527 #define CSL_SRIO_RIO_SRC_OP_STRM_WR_RESETVAL (0x00000000u)
3529 #define CSL_SRIO_RIO_SRC_OP_WR_RES_MASK (0x00001000u)
3530 #define CSL_SRIO_RIO_SRC_OP_WR_RES_SHIFT (0x0000000Cu)
3531 #define CSL_SRIO_RIO_SRC_OP_WR_RES_RESETVAL (0x00000000u)
3533 #define CSL_SRIO_RIO_SRC_OP_D_MSG_MASK (0x00000800u)
3534 #define CSL_SRIO_RIO_SRC_OP_D_MSG_SHIFT (0x0000000Bu)
3535 #define CSL_SRIO_RIO_SRC_OP_D_MSG_RESETVAL (0x00000000u)
3537 #define CSL_SRIO_RIO_SRC_OP_DBELL_MASK (0x00000400u)
3538 #define CSL_SRIO_RIO_SRC_OP_DBELL_SHIFT (0x0000000Au)
3539 #define CSL_SRIO_RIO_SRC_OP_DBELL_RESETVAL (0x00000000u)
3541 #define CSL_SRIO_RIO_SRC_OP_ACSWAP_MASK (0x00000200u)
3542 #define CSL_SRIO_RIO_SRC_OP_ACSWAP_SHIFT (0x00000009u)
3543 #define CSL_SRIO_RIO_SRC_OP_ACSWAP_RESETVAL (0x00000000u)
3545 #define CSL_SRIO_RIO_SRC_OP_ATSWAP_MASK (0x00000100u)
3546 #define CSL_SRIO_RIO_SRC_OP_ATSWAP_SHIFT (0x00000008u)
3547 #define CSL_SRIO_RIO_SRC_OP_ATSWAP_RESETVAL (0x00000000u)
3549 #define CSL_SRIO_RIO_SRC_OP_A_INC_MASK (0x00000080u)
3550 #define CSL_SRIO_RIO_SRC_OP_A_INC_SHIFT (0x00000007u)
3551 #define CSL_SRIO_RIO_SRC_OP_A_INC_RESETVAL (0x00000000u)
3553 #define CSL_SRIO_RIO_SRC_OP_A_DEC_MASK (0x00000040u)
3554 #define CSL_SRIO_RIO_SRC_OP_A_DEC_SHIFT (0x00000006u)
3555 #define CSL_SRIO_RIO_SRC_OP_A_DEC_RESETVAL (0x00000000u)
3557 #define CSL_SRIO_RIO_SRC_OP_A_SET_MASK (0x00000020u)
3558 #define CSL_SRIO_RIO_SRC_OP_A_SET_SHIFT (0x00000005u)
3559 #define CSL_SRIO_RIO_SRC_OP_A_SET_RESETVAL (0x00000000u)
3561 #define CSL_SRIO_RIO_SRC_OP_A_CLEAR_MASK (0x00000010u)
3562 #define CSL_SRIO_RIO_SRC_OP_A_CLEAR_SHIFT (0x00000004u)
3563 #define CSL_SRIO_RIO_SRC_OP_A_CLEAR_RESETVAL (0x00000000u)
3565 #define CSL_SRIO_RIO_SRC_OP_A_SWAP_MASK (0xFFFFFFF8u)
3566 #define CSL_SRIO_RIO_SRC_OP_A_SWAP_SHIFT (0x00000003u)
3567 #define CSL_SRIO_RIO_SRC_OP_A_SWAP_RESETVAL (0x00000000u)
3569 #define CSL_SRIO_RIO_SRC_OP_PORT_WR_MASK (0x00000004u)
3570 #define CSL_SRIO_RIO_SRC_OP_PORT_WR_SHIFT (0x00000002u)
3571 #define CSL_SRIO_RIO_SRC_OP_PORT_WR_RESETVAL (0x00000000u)
3573 #define CSL_SRIO_RIO_SRC_OP_IMPLEMENT_DEF2_MASK (0x00000003u)
3574 #define CSL_SRIO_RIO_SRC_OP_IMPLEMENT_DEF2_SHIFT (0x00000000u)
3575 #define CSL_SRIO_RIO_SRC_OP_IMPLEMENT_DEF2_RESETVAL (0x00000000u)
3577 #define CSL_SRIO_RIO_SRC_OP_RESETVAL (0x00000000u)
3579 /* rio_dest_op */
3581 #define CSL_SRIO_RIO_DEST_OP_G_READ_MASK (0x80000000u)
3582 #define CSL_SRIO_RIO_DEST_OP_G_READ_SHIFT (0x0000001Fu)
3583 #define CSL_SRIO_RIO_DEST_OP_G_READ_RESETVAL (0x00000000u)
3585 #define CSL_SRIO_RIO_DEST_OP_G_IREAD_MASK (0x40000000u)
3586 #define CSL_SRIO_RIO_DEST_OP_G_IREAD_SHIFT (0x0000001Eu)
3587 #define CSL_SRIO_RIO_DEST_OP_G_IREAD_RESETVAL (0x00000000u)
3589 #define CSL_SRIO_RIO_DEST_OP_G_READ_OWN_MASK (0x20000000u)
3590 #define CSL_SRIO_RIO_DEST_OP_G_READ_OWN_SHIFT (0x0000001Du)
3591 #define CSL_SRIO_RIO_DEST_OP_G_READ_OWN_RESETVAL (0x00000000u)
3593 #define CSL_SRIO_RIO_DEST_OP_G_DC_INVALIDATE_MASK (0x10000000u)
3594 #define CSL_SRIO_RIO_DEST_OP_G_DC_INVALIDATE_SHIFT (0x0000001Cu)
3595 #define CSL_SRIO_RIO_DEST_OP_G_DC_INVALIDATE_RESETVAL (0x00000000u)
3597 #define CSL_SRIO_RIO_DEST_OP_G_CASTOUT_MASK (0x08000000u)
3598 #define CSL_SRIO_RIO_DEST_OP_G_CASTOUT_SHIFT (0x0000001Bu)
3599 #define CSL_SRIO_RIO_DEST_OP_G_CASTOUT_RESETVAL (0x00000000u)
3601 #define CSL_SRIO_RIO_DEST_OP_G_DC_FLUSH_MASK (0x04000000u)
3602 #define CSL_SRIO_RIO_DEST_OP_G_DC_FLUSH_SHIFT (0x0000001Au)
3603 #define CSL_SRIO_RIO_DEST_OP_G_DC_FLUSH_RESETVAL (0x00000000u)
3605 #define CSL_SRIO_RIO_DEST_OP_G_IO_READ_MASK (0x02000000u)
3606 #define CSL_SRIO_RIO_DEST_OP_G_IO_READ_SHIFT (0x00000019u)
3607 #define CSL_SRIO_RIO_DEST_OP_G_IO_READ_RESETVAL (0x00000000u)
3609 #define CSL_SRIO_RIO_DEST_OP_G_IC_INVALIDATE_MASK (0x01000000u)
3610 #define CSL_SRIO_RIO_DEST_OP_G_IC_INVALIDATE_SHIFT (0x00000018u)
3611 #define CSL_SRIO_RIO_DEST_OP_G_IC_INVALIDATE_RESETVAL (0x00000000u)
3613 #define CSL_SRIO_RIO_DEST_OP_G_TLB_INVALIDATE_MASK (0x00800000u)
3614 #define CSL_SRIO_RIO_DEST_OP_G_TLB_INVALIDATE_SHIFT (0x00000017u)
3615 #define CSL_SRIO_RIO_DEST_OP_G_TLB_INVALIDATE_RESETVAL (0x00000000u)
3617 #define CSL_SRIO_RIO_DEST_OP_G_TLB_SYNC_MASK (0x00400000u)
3618 #define CSL_SRIO_RIO_DEST_OP_G_TLB_SYNC_SHIFT (0x00000016u)
3619 #define CSL_SRIO_RIO_DEST_OP_G_TLB_SYNC_RESETVAL (0x00000000u)
3621 #define CSL_SRIO_RIO_DEST_OP_G_RIO_RSVD_10_MASK (0x00200000u)
3622 #define CSL_SRIO_RIO_DEST_OP_G_RIO_RSVD_10_SHIFT (0x00000015u)
3623 #define CSL_SRIO_RIO_DEST_OP_G_RIO_RSVD_10_RESETVAL (0x00000000u)
3625 #define CSL_SRIO_RIO_DEST_OP_G_RIO_RSVD_11_MASK (0x00100000u)
3626 #define CSL_SRIO_RIO_DEST_OP_G_RIO_RSVD_11_SHIFT (0x00000014u)
3627 #define CSL_SRIO_RIO_DEST_OP_G_RIO_RSVD_11_RESETVAL (0x00000000u)
3629 #define CSL_SRIO_RIO_DEST_OP_DS_TM_MASK (0x00080000u)
3630 #define CSL_SRIO_RIO_DEST_OP_DS_TM_SHIFT (0x00000013u)
3631 #define CSL_SRIO_RIO_DEST_OP_DS_TM_RESETVAL (0x00000000u)
3633 #define CSL_SRIO_RIO_DEST_OP_DS_MASK (0x00040000u)
3634 #define CSL_SRIO_RIO_DEST_OP_DS_SHIFT (0x00000012u)
3635 #define CSL_SRIO_RIO_DEST_OP_DS_RESETVAL (0x00000000u)
3637 #define CSL_SRIO_RIO_DEST_OP_IMPLEMENT_DEF_MASK (0x00030000u)
3638 #define CSL_SRIO_RIO_DEST_OP_IMPLEMENT_DEF_SHIFT (0x00000010u)
3639 #define CSL_SRIO_RIO_DEST_OP_IMPLEMENT_DEF_RESETVAL (0x00000000u)
3641 #define CSL_SRIO_RIO_DEST_OP_READ_MASK (0x00008000u)
3642 #define CSL_SRIO_RIO_DEST_OP_READ_SHIFT (0x0000000Fu)
3643 #define CSL_SRIO_RIO_DEST_OP_READ_RESETVAL (0x00000000u)
3645 #define CSL_SRIO_RIO_DEST_OP_WRITE_MASK (0x00004000u)
3646 #define CSL_SRIO_RIO_DEST_OP_WRITE_SHIFT (0x0000000Eu)
3647 #define CSL_SRIO_RIO_DEST_OP_WRITE_RESETVAL (0x00000000u)
3649 #define CSL_SRIO_RIO_DEST_OP_STRM_WR_MASK (0x00002000u)
3650 #define CSL_SRIO_RIO_DEST_OP_STRM_WR_SHIFT (0x0000000Du)
3651 #define CSL_SRIO_RIO_DEST_OP_STRM_WR_RESETVAL (0x00000000u)
3653 #define CSL_SRIO_RIO_DEST_OP_WR_RES_MASK (0x00001000u)
3654 #define CSL_SRIO_RIO_DEST_OP_WR_RES_SHIFT (0x0000000Cu)
3655 #define CSL_SRIO_RIO_DEST_OP_WR_RES_RESETVAL (0x00000000u)
3657 #define CSL_SRIO_RIO_DEST_OP_D_MSG_MASK (0x00000800u)
3658 #define CSL_SRIO_RIO_DEST_OP_D_MSG_SHIFT (0x0000000Bu)
3659 #define CSL_SRIO_RIO_DEST_OP_D_MSG_RESETVAL (0x00000000u)
3661 #define CSL_SRIO_RIO_DEST_OP_DBELL_MASK (0x00000400u)
3662 #define CSL_SRIO_RIO_DEST_OP_DBELL_SHIFT (0x0000000Au)
3663 #define CSL_SRIO_RIO_DEST_OP_DBELL_RESETVAL (0x00000000u)
3665 #define CSL_SRIO_RIO_DEST_OP_ACSWAP_MASK (0x00000200u)
3666 #define CSL_SRIO_RIO_DEST_OP_ACSWAP_SHIFT (0x00000009u)
3667 #define CSL_SRIO_RIO_DEST_OP_ACSWAP_RESETVAL (0x00000000u)
3669 #define CSL_SRIO_RIO_DEST_OP_ATSWAP_MASK (0x00000100u)
3670 #define CSL_SRIO_RIO_DEST_OP_ATSWAP_SHIFT (0x00000008u)
3671 #define CSL_SRIO_RIO_DEST_OP_ATSWAP_RESETVAL (0x00000000u)
3673 #define CSL_SRIO_RIO_DEST_OP_A_INC_MASK (0x00000080u)
3674 #define CSL_SRIO_RIO_DEST_OP_A_INC_SHIFT (0x00000007u)
3675 #define CSL_SRIO_RIO_DEST_OP_A_INC_RESETVAL (0x00000000u)
3677 #define CSL_SRIO_RIO_DEST_OP_A_DEC_MASK (0x00000040u)
3678 #define CSL_SRIO_RIO_DEST_OP_A_DEC_SHIFT (0x00000006u)
3679 #define CSL_SRIO_RIO_DEST_OP_A_DEC_RESETVAL (0x00000000u)
3681 #define CSL_SRIO_RIO_DEST_OP_A_SET_MASK (0x00000020u)
3682 #define CSL_SRIO_RIO_DEST_OP_A_SET_SHIFT (0x00000005u)
3683 #define CSL_SRIO_RIO_DEST_OP_A_SET_RESETVAL (0x00000000u)
3685 #define CSL_SRIO_RIO_DEST_OP_A_CLEAR_MASK (0x00000010u)
3686 #define CSL_SRIO_RIO_DEST_OP_A_CLEAR_SHIFT (0x00000004u)
3687 #define CSL_SRIO_RIO_DEST_OP_A_CLEAR_RESETVAL (0x00000000u)
3689 #define CSL_SRIO_RIO_DEST_OP_A_SWAP_MASK (0x00000008u)
3690 #define CSL_SRIO_RIO_DEST_OP_A_SWAP_SHIFT (0x00000003u)
3691 #define CSL_SRIO_RIO_DEST_OP_A_SWAP_RESETVAL (0x00000000u)
3693 #define CSL_SRIO_RIO_DEST_OP_PORT_WR_MASK (0x00000004u)
3694 #define CSL_SRIO_RIO_DEST_OP_PORT_WR_SHIFT (0x00000002u)
3695 #define CSL_SRIO_RIO_DEST_OP_PORT_WR_RESETVAL (0x00000000u)
3697 #define CSL_SRIO_RIO_DEST_OP_IMPLEMENT_DEF2_MASK (0x00000003u)
3698 #define CSL_SRIO_RIO_DEST_OP_IMPLEMENT_DEF2_SHIFT (0x00000000u)
3699 #define CSL_SRIO_RIO_DEST_OP_IMPLEMENT_DEF2_RESETVAL (0x00000000u)
3701 #define CSL_SRIO_RIO_DEST_OP_RESETVAL (0x00000000u)
3703 /* rio_ds_info */
3705 #define CSL_SRIO_RIO_DS_INFO_MAX_PDU_MASK (0xFFFF0000u)
3706 #define CSL_SRIO_RIO_DS_INFO_MAX_PDU_SHIFT (0x00000010u)
3707 #define CSL_SRIO_RIO_DS_INFO_MAX_PDU_RESETVAL (0x00000000u)
3709 #define CSL_SRIO_RIO_DS_INFO_SEG_SUPPORT_MASK (0x0000FFFFu)
3710 #define CSL_SRIO_RIO_DS_INFO_SEG_SUPPORT_SHIFT (0x00000000u)
3711 #define CSL_SRIO_RIO_DS_INFO_SEG_SUPPORT_RESETVAL (0x00000010u)
3713 #define CSL_SRIO_RIO_DS_INFO_RESETVAL (0x00000010u)
3715 /* rio_ds_ll_ctl */
3717 #define CSL_SRIO_RIO_DS_LL_CTL_TM_TYPES_MASK (0xF0000000u)
3718 #define CSL_SRIO_RIO_DS_LL_CTL_TM_TYPES_SHIFT (0x0000001Cu)
3719 #define CSL_SRIO_RIO_DS_LL_CTL_TM_TYPES_RESETVAL (0x00000000u)
3721 #define CSL_SRIO_RIO_DS_LL_CTL_TM_MODE_MASK (0x0F000000u)
3722 #define CSL_SRIO_RIO_DS_LL_CTL_TM_MODE_SHIFT (0x00000018u)
3723 #define CSL_SRIO_RIO_DS_LL_CTL_TM_MODE_RESETVAL (0x00000000u)
3725 #define CSL_SRIO_RIO_DS_LL_CTL_MTU_MASK (0x000000FFu)
3726 #define CSL_SRIO_RIO_DS_LL_CTL_MTU_SHIFT (0x00000000u)
3727 #define CSL_SRIO_RIO_DS_LL_CTL_MTU_RESETVAL (0x00000040u)
3729 #define CSL_SRIO_RIO_DS_LL_CTL_RESETVAL (0x00000040u)
3731 /* rio_pe_ll_ctl */
3733 #define CSL_SRIO_RIO_PE_LL_CTL_EXT_ADDR_CTL_MASK (0x00000007u)
3734 #define CSL_SRIO_RIO_PE_LL_CTL_EXT_ADDR_CTL_SHIFT (0x00000000u)
3735 #define CSL_SRIO_RIO_PE_LL_CTL_EXT_ADDR_CTL_RESETVAL (0x00000001u)
3737 #define CSL_SRIO_RIO_PE_LL_CTL_RESETVAL (0x00000001u)
3739 /* rio_lcl_cfg_hbar */
3741 #define CSL_SRIO_RIO_LCL_CFG_HBAR_LCSBA1_MASK (0x7FFF8000u)
3742 #define CSL_SRIO_RIO_LCL_CFG_HBAR_LCSBA1_SHIFT (0x0000000Fu)
3743 #define CSL_SRIO_RIO_LCL_CFG_HBAR_LCSBA1_RESETVAL (0x00000000u)
3745 #define CSL_SRIO_RIO_LCL_CFG_HBAR_LCSBA0_MASK (0x00007FFFu)
3746 #define CSL_SRIO_RIO_LCL_CFG_HBAR_LCSBA0_SHIFT (0x00000000u)
3747 #define CSL_SRIO_RIO_LCL_CFG_HBAR_LCSBA0_RESETVAL (0x00000000u)
3749 #define CSL_SRIO_RIO_LCL_CFG_HBAR_RESETVAL (0x00000000u)
3751 /* rio_lcl_cfg_bar */
3753 #define CSL_SRIO_RIO_LCL_CFG_BAR_LCSBA1_MASK (0x80000000u)
3754 #define CSL_SRIO_RIO_LCL_CFG_BAR_LCSBA1_SHIFT (0x0000001Fu)
3755 #define CSL_SRIO_RIO_LCL_CFG_BAR_LCSBA1_RESETVAL (0x00000000u)
3757 #define CSL_SRIO_RIO_LCL_CFG_BAR_LCSBA0_MASK (0x7FFFFFFFu)
3758 #define CSL_SRIO_RIO_LCL_CFG_BAR_LCSBA0_SHIFT (0x00000000u)
3759 #define CSL_SRIO_RIO_LCL_CFG_BAR_LCSBA0_RESETVAL (0x00000000u)
3761 #define CSL_SRIO_RIO_LCL_CFG_BAR_RESETVAL (0x00000000u)
3763 /* rio_base_id */
3765 #define CSL_SRIO_RIO_BASE_ID_BASE_ID_MASK (0x00FF0000u)
3766 #define CSL_SRIO_RIO_BASE_ID_BASE_ID_SHIFT (0x00000010u)
3767 #define CSL_SRIO_RIO_BASE_ID_BASE_ID_RESETVAL (0x000000FFu)
3769 #define CSL_SRIO_RIO_BASE_ID_LARGE_BASE_ID_MASK (0x0000FFFFu)
3770 #define CSL_SRIO_RIO_BASE_ID_LARGE_BASE_ID_SHIFT (0x00000000u)
3771 #define CSL_SRIO_RIO_BASE_ID_LARGE_BASE_ID_RESETVAL (0x0000FFFFu)
3773 #define CSL_SRIO_RIO_BASE_ID_RESETVAL (0x00FFFFFFu)
3775 /* rio_host_base_id_lock */
3777 #define CSL_SRIO_RIO_HOST_BASE_ID_LOCK_HOST_BASE_ID_MASK (0x0000FFFFu)
3778 #define CSL_SRIO_RIO_HOST_BASE_ID_LOCK_HOST_BASE_ID_SHIFT (0x00000000u)
3779 #define CSL_SRIO_RIO_HOST_BASE_ID_LOCK_HOST_BASE_ID_RESETVAL (0x0000FFFFu)
3781 #define CSL_SRIO_RIO_HOST_BASE_ID_LOCK_RESETVAL (0x0000FFFFu)
3783 /* rio_comp_tag */
3785 #define CSL_SRIO_RIO_COMP_TAG_CTAG_MASK (0xFFFFFFFFu)
3786 #define CSL_SRIO_RIO_COMP_TAG_CTAG_SHIFT (0x00000000u)
3787 #define CSL_SRIO_RIO_COMP_TAG_CTAG_RESETVAL (0x00000000u)
3789 #define CSL_SRIO_RIO_COMP_TAG_RESETVAL (0x00000000u)
3791 /* rio_sp_mb_head */
3793 #define CSL_SRIO_RIO_SP_MB_HEAD_EF_PTR_MASK (0xFFFF0000u)
3794 #define CSL_SRIO_RIO_SP_MB_HEAD_EF_PTR_SHIFT (0x00000010u)
3795 #define CSL_SRIO_RIO_SP_MB_HEAD_EF_PTR_RESETVAL (0x00001000u)
3797 #define CSL_SRIO_RIO_SP_MB_HEAD_EF_ID_MASK (0x0000FFFFu)
3798 #define CSL_SRIO_RIO_SP_MB_HEAD_EF_ID_SHIFT (0x00000000u)
3799 #define CSL_SRIO_RIO_SP_MB_HEAD_EF_ID_RESETVAL (0x00000002u)
3801 #define CSL_SRIO_RIO_SP_MB_HEAD_RESETVAL (0x10000002u)
3803 /* rio_sp_lt_ctl */
3805 #define CSL_SRIO_RIO_SP_LT_CTL_TVAL_MASK (0xFFFFFF00u)
3806 #define CSL_SRIO_RIO_SP_LT_CTL_TVAL_SHIFT (0x00000008u)
3807 #define CSL_SRIO_RIO_SP_LT_CTL_TVAL_RESETVAL (0x00FFFFFFu)
3809 #define CSL_SRIO_RIO_SP_LT_CTL_RESETVAL (0xFFFFFF00u)
3811 /* rio_sp_rt_ctl */
3813 #define CSL_SRIO_RIO_SP_RT_CTL_TVAL_MASK (0xFFFFFF00u)
3814 #define CSL_SRIO_RIO_SP_RT_CTL_TVAL_SHIFT (0x00000008u)
3815 #define CSL_SRIO_RIO_SP_RT_CTL_TVAL_RESETVAL (0x00FFFFFFu)
3817 #define CSL_SRIO_RIO_SP_RT_CTL_RESETVAL (0xFFFFFF00u)
3819 /* rio_sp_gen_ctl */
3821 #define CSL_SRIO_RIO_SP_GEN_CTL_HOST_MASK (0x80000000u)
3822 #define CSL_SRIO_RIO_SP_GEN_CTL_HOST_SHIFT (0x0000001Fu)
3823 #define CSL_SRIO_RIO_SP_GEN_CTL_HOST_RESETVAL (0x00000000u)
3825 #define CSL_SRIO_RIO_SP_GEN_CTL_MAST_EN_MASK (0x40000000u)
3826 #define CSL_SRIO_RIO_SP_GEN_CTL_MAST_EN_SHIFT (0x0000001Eu)
3827 #define CSL_SRIO_RIO_SP_GEN_CTL_MAST_EN_RESETVAL (0x00000000u)
3829 #define CSL_SRIO_RIO_SP_GEN_CTL_DISC_MASK (0x20000000u)
3830 #define CSL_SRIO_RIO_SP_GEN_CTL_DISC_SHIFT (0x0000001Du)
3831 #define CSL_SRIO_RIO_SP_GEN_CTL_DISC_RESETVAL (0x00000000u)
3833 #define CSL_SRIO_RIO_SP_GEN_CTL_RESETVAL (0x00000000u)
3835 /* rio_err_rpt_bh */
3837 #define CSL_SRIO_RIO_ERR_RPT_BH_EF_PTR_MASK (0xFFFF0000u)
3838 #define CSL_SRIO_RIO_ERR_RPT_BH_EF_PTR_SHIFT (0x00000010u)
3839 #define CSL_SRIO_RIO_ERR_RPT_BH_EF_PTR_RESETVAL (0x00003000u)
3841 #define CSL_SRIO_RIO_ERR_RPT_BH_EF_ID_MASK (0x0000FFFFu)
3842 #define CSL_SRIO_RIO_ERR_RPT_BH_EF_ID_SHIFT (0x00000000u)
3843 #define CSL_SRIO_RIO_ERR_RPT_BH_EF_ID_RESETVAL (0x00000007u)
3845 #define CSL_SRIO_RIO_ERR_RPT_BH_RESETVAL (0x30000007u)
3847 /* rio_err_det */
3849 #define CSL_SRIO_RIO_ERR_DET_IO_ERR_RESP_MASK (0x80000000u)
3850 #define CSL_SRIO_RIO_ERR_DET_IO_ERR_RESP_SHIFT (0x0000001Fu)
3851 #define CSL_SRIO_RIO_ERR_DET_IO_ERR_RESP_RESETVAL (0x00000000u)
3853 #define CSL_SRIO_RIO_ERR_DET_MSG_ERR_RESP_MASK (0x40000000u)
3854 #define CSL_SRIO_RIO_ERR_DET_MSG_ERR_RESP_SHIFT (0x0000001Eu)
3855 #define CSL_SRIO_RIO_ERR_DET_MSG_ERR_RESP_RESETVAL (0x00000000u)
3857 #define CSL_SRIO_RIO_ERR_DET_GSM_ERR_RESP_MASK (0x20000000u)
3858 #define CSL_SRIO_RIO_ERR_DET_GSM_ERR_RESP_SHIFT (0x0000001Du)
3859 #define CSL_SRIO_RIO_ERR_DET_GSM_ERR_RESP_RESETVAL (0x00000000u)
3861 #define CSL_SRIO_RIO_ERR_DET_MSG_FMT_ERR_MASK (0x10000000u)
3862 #define CSL_SRIO_RIO_ERR_DET_MSG_FMT_ERR_SHIFT (0x0000001Cu)
3863 #define CSL_SRIO_RIO_ERR_DET_MSG_FMT_ERR_RESETVAL (0x00000000u)
3865 #define CSL_SRIO_RIO_ERR_DET_ILL_TRANS_DECODE_MASK (0x08000000u)
3866 #define CSL_SRIO_RIO_ERR_DET_ILL_TRANS_DECODE_SHIFT (0x0000001Bu)
3867 #define CSL_SRIO_RIO_ERR_DET_ILL_TRANS_DECODE_RESETVAL (0x00000000u)
3869 #define CSL_SRIO_RIO_ERR_DET_ILL_TRANS_TGT_ERR_MASK (0x04000000u)
3870 #define CSL_SRIO_RIO_ERR_DET_ILL_TRANS_TGT_ERR_SHIFT (0x0000001Au)
3871 #define CSL_SRIO_RIO_ERR_DET_ILL_TRANS_TGT_ERR_RESETVAL (0x00000000u)
3873 #define CSL_SRIO_RIO_ERR_DET_MSG_REQ_TIMEOUT_MASK (0x02000000u)
3874 #define CSL_SRIO_RIO_ERR_DET_MSG_REQ_TIMEOUT_SHIFT (0x00000019u)
3875 #define CSL_SRIO_RIO_ERR_DET_MSG_REQ_TIMEOUT_RESETVAL (0x00000000u)
3877 #define CSL_SRIO_RIO_ERR_DET_PKT_RESP_TIMEOUT_MASK (0x01000000u)
3878 #define CSL_SRIO_RIO_ERR_DET_PKT_RESP_TIMEOUT_SHIFT (0x00000018u)
3879 #define CSL_SRIO_RIO_ERR_DET_PKT_RESP_TIMEOUT_RESETVAL (0x00000000u)
3881 #define CSL_SRIO_RIO_ERR_DET_UNSOLICITED_RESP_MASK (0x00800000u)
3882 #define CSL_SRIO_RIO_ERR_DET_UNSOLICITED_RESP_SHIFT (0x00000017u)
3883 #define CSL_SRIO_RIO_ERR_DET_UNSOLICITED_RESP_RESETVAL (0x00000000u)
3885 #define CSL_SRIO_RIO_ERR_DET_UNSUPPORTED_TRANS_MASK (0x00400000u)
3886 #define CSL_SRIO_RIO_ERR_DET_UNSUPPORTED_TRANS_SHIFT (0x00000016u)
3887 #define CSL_SRIO_RIO_ERR_DET_UNSUPPORTED_TRANS_RESETVAL (0x00000000u)
3889 #define CSL_SRIO_RIO_ERR_DET_PDU_LEN_ERR_MASK (0x00004000u)
3890 #define CSL_SRIO_RIO_ERR_DET_PDU_LEN_ERR_SHIFT (0x0000000Eu)
3891 #define CSL_SRIO_RIO_ERR_DET_PDU_LEN_ERR_RESETVAL (0x00000000u)
3893 #define CSL_SRIO_RIO_ERR_DET_SHORT_STREAM_SEG_MASK (0x00002000u)
3894 #define CSL_SRIO_RIO_ERR_DET_SHORT_STREAM_SEG_SHIFT (0x0000000Du)
3895 #define CSL_SRIO_RIO_ERR_DET_SHORT_STREAM_SEG_RESETVAL (0x00000000u)
3897 #define CSL_SRIO_RIO_ERR_DET_LONG_STREAM_SEG_MASK (0x00001000u)
3898 #define CSL_SRIO_RIO_ERR_DET_LONG_STREAM_SEG_SHIFT (0x0000000Cu)
3899 #define CSL_SRIO_RIO_ERR_DET_LONG_STREAM_SEG_RESETVAL (0x00000000u)
3901 #define CSL_SRIO_RIO_ERR_DET_OPEN_STREAM_CONTEXT_MASK (0x00000800u)
3902 #define CSL_SRIO_RIO_ERR_DET_OPEN_STREAM_CONTEXT_SHIFT (0x0000000Bu)
3903 #define CSL_SRIO_RIO_ERR_DET_OPEN_STREAM_CONTEXT_RESETVAL (0x00000000u)
3905 #define CSL_SRIO_RIO_ERR_DET_MISSING_STREAM_CONTEXT_MASK (0x00000400u)
3906 #define CSL_SRIO_RIO_ERR_DET_MISSING_STREAM_CONTEXT_SHIFT (0x0000000Au)
3907 #define CSL_SRIO_RIO_ERR_DET_MISSING_STREAM_CONTEXT_RESETVAL (0x00000000u)
3909 #define CSL_SRIO_RIO_ERR_DET_NO_CONTEXT_AVAILABLE_MASK (0x00000200u)
3910 #define CSL_SRIO_RIO_ERR_DET_NO_CONTEXT_AVAILABLE_SHIFT (0x00000009u)
3911 #define CSL_SRIO_RIO_ERR_DET_NO_CONTEXT_AVAILABLE_RESETVAL (0x00000000u)
3913 #define CSL_SRIO_RIO_ERR_DET_CPPI_SECURITY_VIOLATION_MASK (0x00000080u)
3914 #define CSL_SRIO_RIO_ERR_DET_CPPI_SECURITY_VIOLATION_SHIFT (0x00000007u)
3915 #define CSL_SRIO_RIO_ERR_DET_CPPI_SECURITY_VIOLATION_RESETVAL (0x00000000u)
3917 #define CSL_SRIO_RIO_ERR_DET_RX_DMA_ERR_MASK (0x00000040u)
3918 #define CSL_SRIO_RIO_ERR_DET_RX_DMA_ERR_SHIFT (0x00000006u)
3919 #define CSL_SRIO_RIO_ERR_DET_RX_DMA_ERR_RESETVAL (0x00000000u)
3921 #define CSL_SRIO_RIO_ERR_DET_TX_RETRY_CREDIT_TIMEOUT_MASK (0x00000020u)
3922 #define CSL_SRIO_RIO_ERR_DET_TX_RETRY_CREDIT_TIMEOUT_SHIFT (0x00000005u)
3923 #define CSL_SRIO_RIO_ERR_DET_TX_RETRY_CREDIT_TIMEOUT_RESETVAL (0x00000000u)
3925 #define CSL_SRIO_RIO_ERR_DET_RESETVAL (0x00000000u)
3927 /* rio_err_en */
3929 #define CSL_SRIO_RIO_ERR_EN_IO_ERR_RESP_EN_MASK (0x80000000u)
3930 #define CSL_SRIO_RIO_ERR_EN_IO_ERR_RESP_EN_SHIFT (0x0000001Fu)
3931 #define CSL_SRIO_RIO_ERR_EN_IO_ERR_RESP_EN_RESETVAL (0x00000000u)
3933 #define CSL_SRIO_RIO_ERR_EN_MSG_ERR_RESP_EN_MASK (0x40000000u)
3934 #define CSL_SRIO_RIO_ERR_EN_MSG_ERR_RESP_EN_SHIFT (0x0000001Eu)
3935 #define CSL_SRIO_RIO_ERR_EN_MSG_ERR_RESP_EN_RESETVAL (0x00000000u)
3937 #define CSL_SRIO_RIO_ERR_EN_GSM_ERR_RESP_EN_MASK (0x20000000u)
3938 #define CSL_SRIO_RIO_ERR_EN_GSM_ERR_RESP_EN_SHIFT (0x0000001Du)
3939 #define CSL_SRIO_RIO_ERR_EN_GSM_ERR_RESP_EN_RESETVAL (0x00000000u)
3941 #define CSL_SRIO_RIO_ERR_EN_MSG_FMT_ERR_EN_MASK (0x10000000u)
3942 #define CSL_SRIO_RIO_ERR_EN_MSG_FMT_ERR_EN_SHIFT (0x0000001Cu)
3943 #define CSL_SRIO_RIO_ERR_EN_MSG_FMT_ERR_EN_RESETVAL (0x00000000u)
3945 #define CSL_SRIO_RIO_ERR_EN_ILL_TRANS_DECODE_EN_MASK (0x08000000u)
3946 #define CSL_SRIO_RIO_ERR_EN_ILL_TRANS_DECODE_EN_SHIFT (0x0000001Bu)
3947 #define CSL_SRIO_RIO_ERR_EN_ILL_TRANS_DECODE_EN_RESETVAL (0x00000000u)
3949 #define CSL_SRIO_RIO_ERR_EN_ILL_TRANS_TGT_ERR_EN_MASK (0x04000000u)
3950 #define CSL_SRIO_RIO_ERR_EN_ILL_TRANS_TGT_ERR_EN_SHIFT (0x0000001Au)
3951 #define CSL_SRIO_RIO_ERR_EN_ILL_TRANS_TGT_ERR_EN_RESETVAL (0x00000000u)
3953 #define CSL_SRIO_RIO_ERR_EN_MSG_REQ_TIMEOUT_EN_MASK (0x02000000u)
3954 #define CSL_SRIO_RIO_ERR_EN_MSG_REQ_TIMEOUT_EN_SHIFT (0x00000019u)
3955 #define CSL_SRIO_RIO_ERR_EN_MSG_REQ_TIMEOUT_EN_RESETVAL (0x00000000u)
3957 #define CSL_SRIO_RIO_ERR_EN_PKT_RESP_TIMEOUT_EN_MASK (0x01000000u)
3958 #define CSL_SRIO_RIO_ERR_EN_PKT_RESP_TIMEOUT_EN_SHIFT (0x00000018u)
3959 #define CSL_SRIO_RIO_ERR_EN_PKT_RESP_TIMEOUT_EN_RESETVAL (0x00000000u)
3961 #define CSL_SRIO_RIO_ERR_EN_UNSOLICITED_RESP_EN_MASK (0x00800000u)
3962 #define CSL_SRIO_RIO_ERR_EN_UNSOLICITED_RESP_EN_SHIFT (0x00000017u)
3963 #define CSL_SRIO_RIO_ERR_EN_UNSOLICITED_RESP_EN_RESETVAL (0x00000000u)
3965 #define CSL_SRIO_RIO_ERR_EN_UNSUPPORTED_TRANS_EN_MASK (0x00400000u)
3966 #define CSL_SRIO_RIO_ERR_EN_UNSUPPORTED_TRANS_EN_SHIFT (0x00000016u)
3967 #define CSL_SRIO_RIO_ERR_EN_UNSUPPORTED_TRANS_EN_RESETVAL (0x00000000u)
3969 #define CSL_SRIO_RIO_ERR_EN_PDU_LEN_ERR_EN_MASK (0x00004000u)
3970 #define CSL_SRIO_RIO_ERR_EN_PDU_LEN_ERR_EN_SHIFT (0x0000000Eu)
3971 #define CSL_SRIO_RIO_ERR_EN_PDU_LEN_ERR_EN_RESETVAL (0x00000000u)
3973 #define CSL_SRIO_RIO_ERR_EN_SHORT_STREAM_SEG_EN_MASK (0x00002000u)
3974 #define CSL_SRIO_RIO_ERR_EN_SHORT_STREAM_SEG_EN_SHIFT (0x0000000Du)
3975 #define CSL_SRIO_RIO_ERR_EN_SHORT_STREAM_SEG_EN_RESETVAL (0x00000000u)
3977 #define CSL_SRIO_RIO_ERR_EN_LONG_STREAM_SEG_EN_MASK (0x00001000u)
3978 #define CSL_SRIO_RIO_ERR_EN_LONG_STREAM_SEG_EN_SHIFT (0x0000000Cu)
3979 #define CSL_SRIO_RIO_ERR_EN_LONG_STREAM_SEG_EN_RESETVAL (0x00000000u)
3981 #define CSL_SRIO_RIO_ERR_EN_OPEN_STREAM_CONTEXT_EN_MASK (0x00000800u)
3982 #define CSL_SRIO_RIO_ERR_EN_OPEN_STREAM_CONTEXT_EN_SHIFT (0x0000000Bu)
3983 #define CSL_SRIO_RIO_ERR_EN_OPEN_STREAM_CONTEXT_EN_RESETVAL (0x00000000u)
3985 #define CSL_SRIO_RIO_ERR_EN_MISSING_STREAM_CONTEXT_EN_MASK (0x00000400u)
3986 #define CSL_SRIO_RIO_ERR_EN_MISSING_STREAM_CONTEXT_EN_SHIFT (0x0000000Au)
3987 #define CSL_SRIO_RIO_ERR_EN_MISSING_STREAM_CONTEXT_EN_RESETVAL (0x00000000u)
3989 #define CSL_SRIO_RIO_ERR_EN_NO_CONTEXT_AVAILABLE_EN_MASK (0x00000200u)
3990 #define CSL_SRIO_RIO_ERR_EN_NO_CONTEXT_AVAILABLE_EN_SHIFT (0x00000009u)
3991 #define CSL_SRIO_RIO_ERR_EN_NO_CONTEXT_AVAILABLE_EN_RESETVAL (0x00000000u)
3993 #define CSL_SRIO_RIO_ERR_EN_CPPI_SECURITY_VIOLATION_EN_MASK (0x00000080u)
3994 #define CSL_SRIO_RIO_ERR_EN_CPPI_SECURITY_VIOLATION_EN_SHIFT (0x00000007u)
3995 #define CSL_SRIO_RIO_ERR_EN_CPPI_SECURITY_VIOLATION_EN_RESETVAL (0x00000000u)
3997 #define CSL_SRIO_RIO_ERR_EN_RX_DMA_ERR_EN_MASK (0x00000040u)
3998 #define CSL_SRIO_RIO_ERR_EN_RX_DMA_ERR_EN_SHIFT (0x00000006u)
3999 #define CSL_SRIO_RIO_ERR_EN_RX_DMA_ERR_EN_RESETVAL (0x00000000u)
4001 #define CSL_SRIO_RIO_ERR_EN_TX_RETRY_CREDIT_TIMEOUT_EN_MASK (0x00000020u)
4002 #define CSL_SRIO_RIO_ERR_EN_TX_RETRY_CREDIT_TIMEOUT_EN_SHIFT (0x00000005u)
4003 #define CSL_SRIO_RIO_ERR_EN_TX_RETRY_CREDIT_TIMEOUT_EN_RESETVAL (0x00000000u)
4005 #define CSL_SRIO_RIO_ERR_EN_RESETVAL (0x00000000u)
4007 /* rio_h_addr_capt */
4009 #define CSL_SRIO_RIO_H_ADDR_CAPT_ADDR_HIGH_MASK (0xFFFFFFFFu)
4010 #define CSL_SRIO_RIO_H_ADDR_CAPT_ADDR_HIGH_SHIFT (0x00000000u)
4011 #define CSL_SRIO_RIO_H_ADDR_CAPT_ADDR_HIGH_RESETVAL (0x00000000u)
4013 #define CSL_SRIO_RIO_H_ADDR_CAPT_RESETVAL (0x00000000u)
4015 /* rio_addr_capt */
4017 #define CSL_SRIO_RIO_ADDR_CAPT_ADDR_LOW_MASK (0xFFFFFFF8u)
4018 #define CSL_SRIO_RIO_ADDR_CAPT_ADDR_LOW_SHIFT (0x00000003u)
4019 #define CSL_SRIO_RIO_ADDR_CAPT_ADDR_LOW_RESETVAL (0x00000000u)
4021 #define CSL_SRIO_RIO_ADDR_CAPT_XAMSBS_MASK (0x00000003u)
4022 #define CSL_SRIO_RIO_ADDR_CAPT_XAMSBS_SHIFT (0x00000000u)
4023 #define CSL_SRIO_RIO_ADDR_CAPT_XAMSBS_RESETVAL (0x00000000u)
4025 #define CSL_SRIO_RIO_ADDR_CAPT_RESETVAL (0x00000000u)
4027 /* rio_id_capt */
4029 #define CSL_SRIO_RIO_ID_CAPT_MSB_DSTID_MASK (0xFF000000u)
4030 #define CSL_SRIO_RIO_ID_CAPT_MSB_DSTID_SHIFT (0x00000018u)
4031 #define CSL_SRIO_RIO_ID_CAPT_MSB_DSTID_RESETVAL (0x00000000u)
4033 #define CSL_SRIO_RIO_ID_CAPT_DSTID_MASK (0x00FF0000u)
4034 #define CSL_SRIO_RIO_ID_CAPT_DSTID_SHIFT (0x00000010u)
4035 #define CSL_SRIO_RIO_ID_CAPT_DSTID_RESETVAL (0x00000000u)
4037 #define CSL_SRIO_RIO_ID_CAPT_MSB_SRCTID_MASK (0x0000FF00u)
4038 #define CSL_SRIO_RIO_ID_CAPT_MSB_SRCTID_SHIFT (0x00000008u)
4039 #define CSL_SRIO_RIO_ID_CAPT_MSB_SRCTID_RESETVAL (0x00000000u)
4041 #define CSL_SRIO_RIO_ID_CAPT_SRCID_MASK (0x000000FFu)
4042 #define CSL_SRIO_RIO_ID_CAPT_SRCID_SHIFT (0x00000000u)
4043 #define CSL_SRIO_RIO_ID_CAPT_SRCID_RESETVAL (0x00000000u)
4045 #define CSL_SRIO_RIO_ID_CAPT_RESETVAL (0x00000000u)
4047 /* rio_ctrl_capt */
4049 #define CSL_SRIO_RIO_CTRL_CAPT_FTYPE_MASK (0xF0000000u)
4050 #define CSL_SRIO_RIO_CTRL_CAPT_FTYPE_SHIFT (0x0000001Cu)
4051 #define CSL_SRIO_RIO_CTRL_CAPT_FTYPE_RESETVAL (0x00000000u)
4053 #define CSL_SRIO_RIO_CTRL_CAPT_TTYPE_MASK (0x0F000000u)
4054 #define CSL_SRIO_RIO_CTRL_CAPT_TTYPE_SHIFT (0x00000018u)
4055 #define CSL_SRIO_RIO_CTRL_CAPT_TTYPE_RESETVAL (0x00000000u)
4057 #define CSL_SRIO_RIO_CTRL_CAPT_MSG_INFO_MASK (0x00FF0000u)
4058 #define CSL_SRIO_RIO_CTRL_CAPT_MSG_INFO_SHIFT (0x00000010u)
4059 #define CSL_SRIO_RIO_CTRL_CAPT_MSG_INFO_RESETVAL (0x00000000u)
4061 #define CSL_SRIO_RIO_CTRL_CAPT_IMP_SPECIFIC_MASK (0x0000FFFFu)
4062 #define CSL_SRIO_RIO_CTRL_CAPT_IMP_SPECIFIC_SHIFT (0x00000000u)
4063 #define CSL_SRIO_RIO_CTRL_CAPT_IMP_SPECIFIC_RESETVAL (0x00000000u)
4065 #define CSL_SRIO_RIO_CTRL_CAPT_RESETVAL (0x00000000u)
4067 /* rio_pw_tgt_id */
4069 #define CSL_SRIO_RIO_PW_TGT_ID_DEVICEID_MSB_MASK (0xFF000000u)
4070 #define CSL_SRIO_RIO_PW_TGT_ID_DEVICEID_MSB_SHIFT (0x00000018u)
4071 #define CSL_SRIO_RIO_PW_TGT_ID_DEVICEID_MSB_RESETVAL (0x00000000u)
4073 #define CSL_SRIO_RIO_PW_TGT_ID_DEVICEID_MASK (0x00FF0000u)
4074 #define CSL_SRIO_RIO_PW_TGT_ID_DEVICEID_SHIFT (0x00000010u)
4075 #define CSL_SRIO_RIO_PW_TGT_ID_DEVICEID_RESETVAL (0x00000000u)
4077 #define CSL_SRIO_RIO_PW_TGT_ID_ID_LARGE_MASK (0x00008000u)
4078 #define CSL_SRIO_RIO_PW_TGT_ID_ID_LARGE_SHIFT (0x0000000Fu)
4079 #define CSL_SRIO_RIO_PW_TGT_ID_ID_LARGE_RESETVAL (0x00000000u)
4081 #define CSL_SRIO_RIO_PW_TGT_ID_RESETVAL (0x00000000u)
4083 /* rio_per_lane_bh */
4085 #define CSL_SRIO_RIO_PER_LANE_BH_EF_PTR_MASK (0xFFFF0000u)
4086 #define CSL_SRIO_RIO_PER_LANE_BH_EF_PTR_SHIFT (0x00000010u)
4087 #define CSL_SRIO_RIO_PER_LANE_BH_EF_PTR_RESETVAL (0x00000000u)
4089 #define CSL_SRIO_RIO_PER_LANE_BH_EF_ID_MASK (0x0000FFFFu)
4090 #define CSL_SRIO_RIO_PER_LANE_BH_EF_ID_SHIFT (0x00000000u)
4091 #define CSL_SRIO_RIO_PER_LANE_BH_EF_ID_RESETVAL (0x0000000Du)
4093 #define CSL_SRIO_RIO_PER_LANE_BH_RESETVAL (0x0000000Du)
4095 /* rio_plm_bh */
4097 #define CSL_SRIO_RIO_PLM_BH_NEXT_BLK_PTR_MASK (0xFFFF0000u)
4098 #define CSL_SRIO_RIO_PLM_BH_NEXT_BLK_PTR_SHIFT (0x00000010u)
4099 #define CSL_SRIO_RIO_PLM_BH_NEXT_BLK_PTR_RESETVAL (0x00000103u)
4101 #define CSL_SRIO_RIO_PLM_BH_BLK_REV_MASK (0x0000F000u)
4102 #define CSL_SRIO_RIO_PLM_BH_BLK_REV_SHIFT (0x0000000Cu)
4103 #define CSL_SRIO_RIO_PLM_BH_BLK_REV_RESETVAL (0x00000000u)
4105 #define CSL_SRIO_RIO_PLM_BH_BLK_TYPE_MASK (0x00000FFFu)
4106 #define CSL_SRIO_RIO_PLM_BH_BLK_TYPE_SHIFT (0x00000000u)
4107 #define CSL_SRIO_RIO_PLM_BH_BLK_TYPE_RESETVAL (0x00000000u)
4109 #define CSL_SRIO_RIO_PLM_BH_RESETVAL (0x01030000u)
4111 /* rio_tlm_bh */
4113 #define CSL_SRIO_RIO_TLM_BH_NXT_BLK_PTR_MASK (0xFFFF0000u)
4114 #define CSL_SRIO_RIO_TLM_BH_NXT_BLK_PTR_SHIFT (0x00000010u)
4115 #define CSL_SRIO_RIO_TLM_BH_NXT_BLK_PTR_RESETVAL (0x00000106u)
4117 #define CSL_SRIO_RIO_TLM_BH_BLK_REV_MASK (0x0000F000u)
4118 #define CSL_SRIO_RIO_TLM_BH_BLK_REV_SHIFT (0x0000000Cu)
4119 #define CSL_SRIO_RIO_TLM_BH_BLK_REV_RESETVAL (0x00000000u)
4121 #define CSL_SRIO_RIO_TLM_BH_BLK_TYPE_MASK (0x00000FFFu)
4122 #define CSL_SRIO_RIO_TLM_BH_BLK_TYPE_SHIFT (0x00000000u)
4123 #define CSL_SRIO_RIO_TLM_BH_BLK_TYPE_RESETVAL (0x00000000u)
4125 #define CSL_SRIO_RIO_TLM_BH_RESETVAL (0x01060000u)
4127 /* rio_pbm_bh */
4129 #define CSL_SRIO_RIO_PBM_BH_NEXT_BLK_PTR_MASK (0xFFFF0000u)
4130 #define CSL_SRIO_RIO_PBM_BH_NEXT_BLK_PTR_SHIFT (0x00000010u)
4131 #define CSL_SRIO_RIO_PBM_BH_NEXT_BLK_PTR_RESETVAL (0x00000109u)
4133 #define CSL_SRIO_RIO_PBM_BH_BLK_REV_MASK (0x0000F000u)
4134 #define CSL_SRIO_RIO_PBM_BH_BLK_REV_SHIFT (0x0000000Cu)
4135 #define CSL_SRIO_RIO_PBM_BH_BLK_REV_RESETVAL (0x00000000u)
4137 #define CSL_SRIO_RIO_PBM_BH_BLK_TYPE_MASK (0x00000FFFu)
4138 #define CSL_SRIO_RIO_PBM_BH_BLK_TYPE_SHIFT (0x00000000u)
4139 #define CSL_SRIO_RIO_PBM_BH_BLK_TYPE_RESETVAL (0x00000000u)
4141 #define CSL_SRIO_RIO_PBM_BH_RESETVAL (0x01090000u)
4143 /* rio_em_bh */
4145 #define CSL_SRIO_RIO_EM_BH_NEXT_BLK_PTR_MASK (0xFFFF0000u)
4146 #define CSL_SRIO_RIO_EM_BH_NEXT_BLK_PTR_SHIFT (0x00000010u)
4147 #define CSL_SRIO_RIO_EM_BH_NEXT_BLK_PTR_RESETVAL (0x0000010Au)
4149 #define CSL_SRIO_RIO_EM_BH_BLK_REV_MASK (0x0000F000u)
4150 #define CSL_SRIO_RIO_EM_BH_BLK_REV_SHIFT (0x0000000Cu)
4151 #define CSL_SRIO_RIO_EM_BH_BLK_REV_RESETVAL (0x00000000u)
4153 #define CSL_SRIO_RIO_EM_BH_BLK_TYPE_MASK (0x00000FFFu)
4154 #define CSL_SRIO_RIO_EM_BH_BLK_TYPE_SHIFT (0x00000000u)
4155 #define CSL_SRIO_RIO_EM_BH_BLK_TYPE_RESETVAL (0x00000000u)
4157 #define CSL_SRIO_RIO_EM_BH_RESETVAL (0x010A0000u)
4159 /* rio_em_int_stat */
4161 #define CSL_SRIO_RIO_EM_INT_STAT_PORT_MASK (0x20000000u)
4162 #define CSL_SRIO_RIO_EM_INT_STAT_PORT_SHIFT (0x0000001Du)
4163 #define CSL_SRIO_RIO_EM_INT_STAT_PORT_RESETVAL (0x00000000u)
4165 #define CSL_SRIO_RIO_EM_INT_STAT_LOG_MASK (0x10000000u)
4166 #define CSL_SRIO_RIO_EM_INT_STAT_LOG_SHIFT (0x0000001Cu)
4167 #define CSL_SRIO_RIO_EM_INT_STAT_LOG_RESETVAL (0x00000000u)
4169 #define CSL_SRIO_RIO_EM_INT_STAT_RCS_MASK (0x08000000u)
4170 #define CSL_SRIO_RIO_EM_INT_STAT_RCS_SHIFT (0x0000001Bu)
4171 #define CSL_SRIO_RIO_EM_INT_STAT_RCS_RESETVAL (0x00000000u)
4173 #define CSL_SRIO_RIO_EM_INT_STAT_MECS_MASK (0x04000000u)
4174 #define CSL_SRIO_RIO_EM_INT_STAT_MECS_SHIFT (0x0000001Au)
4175 #define CSL_SRIO_RIO_EM_INT_STAT_MECS_RESETVAL (0x00000000u)
4177 #define CSL_SRIO_RIO_EM_INT_STAT_PW_RX_MASK (0x00010000u)
4178 #define CSL_SRIO_RIO_EM_INT_STAT_PW_RX_SHIFT (0x00000010u)
4179 #define CSL_SRIO_RIO_EM_INT_STAT_PW_RX_RESETVAL (0x00000000u)
4181 #define CSL_SRIO_RIO_EM_INT_STAT_LOCALOG_MASK (0x00000100u)
4182 #define CSL_SRIO_RIO_EM_INT_STAT_LOCALOG_SHIFT (0x00000008u)
4183 #define CSL_SRIO_RIO_EM_INT_STAT_LOCALOG_RESETVAL (0x00000000u)
4185 #define CSL_SRIO_RIO_EM_INT_STAT_RESETVAL (0x00000000u)
4187 /* rio_em_int_enable */
4189 #define CSL_SRIO_RIO_EM_INT_ENABLE_LOG_MASK (0x10000000u)
4190 #define CSL_SRIO_RIO_EM_INT_ENABLE_LOG_SHIFT (0x0000001Cu)
4191 #define CSL_SRIO_RIO_EM_INT_ENABLE_LOG_RESETVAL (0x00000000u)
4193 #define CSL_SRIO_RIO_EM_INT_ENABLE_MECS_MASK (0x04000000u)
4194 #define CSL_SRIO_RIO_EM_INT_ENABLE_MECS_SHIFT (0x0000001Au)
4195 #define CSL_SRIO_RIO_EM_INT_ENABLE_MECS_RESETVAL (0x00000000u)
4197 #define CSL_SRIO_RIO_EM_INT_ENABLE_PW_RX_MASK (0x00010000u)
4198 #define CSL_SRIO_RIO_EM_INT_ENABLE_PW_RX_SHIFT (0x00000010u)
4199 #define CSL_SRIO_RIO_EM_INT_ENABLE_PW_RX_RESETVAL (0x00000000u)
4201 #define CSL_SRIO_RIO_EM_INT_ENABLE_LOCALOG_MASK (0x00000100u)
4202 #define CSL_SRIO_RIO_EM_INT_ENABLE_LOCALOG_SHIFT (0x00000008u)
4203 #define CSL_SRIO_RIO_EM_INT_ENABLE_LOCALOG_RESETVAL (0x00000000u)
4205 #define CSL_SRIO_RIO_EM_INT_ENABLE_RESETVAL (0x00000000u)
4207 /* rio_em_int_port_stat */
4209 #define CSL_SRIO_RIO_EM_INT_PORT_STAT_IRQ_PENDING_MASK (0x0000000Fu)
4210 #define CSL_SRIO_RIO_EM_INT_PORT_STAT_IRQ_PENDING_SHIFT (0x00000000u)
4211 #define CSL_SRIO_RIO_EM_INT_PORT_STAT_IRQ_PENDING_RESETVAL (0x00000000u)
4213 #define CSL_SRIO_RIO_EM_INT_PORT_STAT_RESETVAL (0x00000000u)
4215 /* rio_em_pw_stat */
4217 #define CSL_SRIO_RIO_EM_PW_STAT_PORT_MASK (0x20000000u)
4218 #define CSL_SRIO_RIO_EM_PW_STAT_PORT_SHIFT (0x0000001Du)
4219 #define CSL_SRIO_RIO_EM_PW_STAT_PORT_RESETVAL (0x00000000u)
4221 #define CSL_SRIO_RIO_EM_PW_STAT_LOG_MASK (0x10000000u)
4222 #define CSL_SRIO_RIO_EM_PW_STAT_LOG_SHIFT (0x0000001Cu)
4223 #define CSL_SRIO_RIO_EM_PW_STAT_LOG_RESETVAL (0x00000000u)
4225 #define CSL_SRIO_RIO_EM_PW_STAT_RCS_MASK (0x08000000u)
4226 #define CSL_SRIO_RIO_EM_PW_STAT_RCS_SHIFT (0x0000001Bu)
4227 #define CSL_SRIO_RIO_EM_PW_STAT_RCS_RESETVAL (0x00000000u)
4229 #define CSL_SRIO_RIO_EM_PW_STAT_MULTIPORT_ERR_MASK (0x00000200u)
4230 #define CSL_SRIO_RIO_EM_PW_STAT_MULTIPORT_ERR_SHIFT (0x00000009u)
4231 #define CSL_SRIO_RIO_EM_PW_STAT_MULTIPORT_ERR_RESETVAL (0x00000000u)
4233 #define CSL_SRIO_RIO_EM_PW_STAT_LOCALOG_MASK (0x00000100u)
4234 #define CSL_SRIO_RIO_EM_PW_STAT_LOCALOG_SHIFT (0x00000008u)
4235 #define CSL_SRIO_RIO_EM_PW_STAT_LOCALOG_RESETVAL (0x00000000u)
4237 #define CSL_SRIO_RIO_EM_PW_STAT_RESETVAL (0x00000000u)
4239 /* rio_em_pw_en */
4241 #define CSL_SRIO_RIO_EM_PW_EN_LOG_MASK (0x10000000u)
4242 #define CSL_SRIO_RIO_EM_PW_EN_LOG_SHIFT (0x0000001Cu)
4243 #define CSL_SRIO_RIO_EM_PW_EN_LOG_RESETVAL (0x00000001u)
4245 #define CSL_SRIO_RIO_EM_PW_EN_LOCALOG_MASK (0x00000100u)
4246 #define CSL_SRIO_RIO_EM_PW_EN_LOCALOG_SHIFT (0x00000008u)
4247 #define CSL_SRIO_RIO_EM_PW_EN_LOCALOG_RESETVAL (0x00000000u)
4249 #define CSL_SRIO_RIO_EM_PW_EN_RESETVAL (0x10000000u)
4251 /* rio_em_pw_port_stat */
4253 #define CSL_SRIO_RIO_EM_PW_PORT_STAT_PW_PENDING_MASK (0x0000000Fu)
4254 #define CSL_SRIO_RIO_EM_PW_PORT_STAT_PW_PENDING_SHIFT (0x00000000u)
4255 #define CSL_SRIO_RIO_EM_PW_PORT_STAT_PW_PENDING_RESETVAL (0x00000000u)
4257 #define CSL_SRIO_RIO_EM_PW_PORT_STAT_RESETVAL (0x00000000u)
4259 /* rio_em_dev_int_en */
4261 #define CSL_SRIO_RIO_EM_DEV_INT_EN_INT_EN_MASK (0x00000001u)
4262 #define CSL_SRIO_RIO_EM_DEV_INT_EN_INT_EN_SHIFT (0x00000000u)
4263 #define CSL_SRIO_RIO_EM_DEV_INT_EN_INT_EN_RESETVAL (0x00000000u)
4265 #define CSL_SRIO_RIO_EM_DEV_INT_EN_RESETVAL (0x00000000u)
4267 /* rio_em_dev_pw_en */
4269 #define CSL_SRIO_RIO_EM_DEV_PW_EN_PW_EN_MASK (0x00000001u)
4270 #define CSL_SRIO_RIO_EM_DEV_PW_EN_PW_EN_SHIFT (0x00000000u)
4271 #define CSL_SRIO_RIO_EM_DEV_PW_EN_PW_EN_RESETVAL (0x00000001u)
4273 #define CSL_SRIO_RIO_EM_DEV_PW_EN_RESETVAL (0x00000001u)
4275 /* rio_em_mecs_stat */
4277 #define CSL_SRIO_RIO_EM_MECS_STAT_CMD_STAT_MASK (0x000000FFu)
4278 #define CSL_SRIO_RIO_EM_MECS_STAT_CMD_STAT_SHIFT (0x00000000u)
4279 #define CSL_SRIO_RIO_EM_MECS_STAT_CMD_STAT_RESETVAL (0x00000000u)
4281 #define CSL_SRIO_RIO_EM_MECS_STAT_RESETVAL (0x00000000u)
4283 /* rio_em_mecs_int_en */
4285 #define CSL_SRIO_RIO_EM_MECS_INT_EN_CMD_EN_MASK (0x000000FFu)
4286 #define CSL_SRIO_RIO_EM_MECS_INT_EN_CMD_EN_SHIFT (0x00000000u)
4287 #define CSL_SRIO_RIO_EM_MECS_INT_EN_CMD_EN_RESETVAL (0x00000001u)
4289 #define CSL_SRIO_RIO_EM_MECS_INT_EN_RESETVAL (0x00000001u)
4291 /* rio_em_mecs_cap_en */
4293 #define CSL_SRIO_RIO_EM_MECS_CAP_EN_CMD_EN_MASK (0x000000FFu)
4294 #define CSL_SRIO_RIO_EM_MECS_CAP_EN_CMD_EN_SHIFT (0x00000000u)
4295 #define CSL_SRIO_RIO_EM_MECS_CAP_EN_CMD_EN_RESETVAL (0x00000000u)
4297 #define CSL_SRIO_RIO_EM_MECS_CAP_EN_RESETVAL (0x00000000u)
4299 /* rio_em_mecs_trig_en */
4301 #define CSL_SRIO_RIO_EM_MECS_TRIG_EN_CMD_STAT_MASK (0x0000FF00u)
4302 #define CSL_SRIO_RIO_EM_MECS_TRIG_EN_CMD_STAT_SHIFT (0x00000008u)
4303 #define CSL_SRIO_RIO_EM_MECS_TRIG_EN_CMD_STAT_RESETVAL (0x00000000u)
4305 #define CSL_SRIO_RIO_EM_MECS_TRIG_EN_CMD_EN_MASK (0x000000FFu)
4306 #define CSL_SRIO_RIO_EM_MECS_TRIG_EN_CMD_EN_SHIFT (0x00000000u)
4307 #define CSL_SRIO_RIO_EM_MECS_TRIG_EN_CMD_EN_RESETVAL (0x00000000u)
4309 #define CSL_SRIO_RIO_EM_MECS_TRIG_EN_RESETVAL (0x00000000u)
4311 /* rio_em_mecs_req */
4313 #define CSL_SRIO_RIO_EM_MECS_REQ_SEND_MASK (0x00000100u)
4314 #define CSL_SRIO_RIO_EM_MECS_REQ_SEND_SHIFT (0x00000008u)
4315 #define CSL_SRIO_RIO_EM_MECS_REQ_SEND_RESETVAL (0x00000000u)
4317 #define CSL_SRIO_RIO_EM_MECS_REQ_CMD_MASK (0x000000FFu)
4318 #define CSL_SRIO_RIO_EM_MECS_REQ_CMD_SHIFT (0x00000000u)
4319 #define CSL_SRIO_RIO_EM_MECS_REQ_CMD_RESETVAL (0x00000000u)
4321 #define CSL_SRIO_RIO_EM_MECS_REQ_RESETVAL (0x00000000u)
4323 /* rio_em_mecs_port_stat */
4325 #define CSL_SRIO_RIO_EM_MECS_PORT_STAT_PORT_MASK (0x0000000Fu)
4326 #define CSL_SRIO_RIO_EM_MECS_PORT_STAT_PORT_SHIFT (0x00000000u)
4327 #define CSL_SRIO_RIO_EM_MECS_PORT_STAT_PORT_RESETVAL (0x00000000u)
4329 #define CSL_SRIO_RIO_EM_MECS_PORT_STAT_RESETVAL (0x00000000u)
4331 /* rio_em_mecs_event_gen */
4333 #define CSL_SRIO_RIO_EM_MECS_EVENT_GEN_CMD_STAT_MASK (0x000000FFu)
4334 #define CSL_SRIO_RIO_EM_MECS_EVENT_GEN_CMD_STAT_SHIFT (0x00000000u)
4335 #define CSL_SRIO_RIO_EM_MECS_EVENT_GEN_CMD_STAT_RESETVAL (0x00000000u)
4337 #define CSL_SRIO_RIO_EM_MECS_EVENT_GEN_RESETVAL (0x00000000u)
4339 /* rio_em_rst_port_stat */
4341 #define CSL_SRIO_RIO_EM_RST_PORT_STAT_RST_REQ_MASK (0x000000FFu)
4342 #define CSL_SRIO_RIO_EM_RST_PORT_STAT_RST_REQ_SHIFT (0x00000000u)
4343 #define CSL_SRIO_RIO_EM_RST_PORT_STAT_RST_REQ_RESETVAL (0x00000000u)
4345 #define CSL_SRIO_RIO_EM_RST_PORT_STAT_RESETVAL (0x00000000u)
4347 /* rio_em_rst_int_en */
4349 #define CSL_SRIO_RIO_EM_RST_INT_EN_RST_INT_EN_MASK (0x0000000Fu)
4350 #define CSL_SRIO_RIO_EM_RST_INT_EN_RST_INT_EN_SHIFT (0x00000000u)
4351 #define CSL_SRIO_RIO_EM_RST_INT_EN_RST_INT_EN_RESETVAL (0x00000000u)
4353 #define CSL_SRIO_RIO_EM_RST_INT_EN_RESETVAL (0x00000000u)
4355 /* rio_em_rst_pw_en */
4357 #define CSL_SRIO_RIO_EM_RST_PW_EN_RST_PW_EN_MASK (0x0000000Fu)
4358 #define CSL_SRIO_RIO_EM_RST_PW_EN_RST_PW_EN_SHIFT (0x00000000u)
4359 #define CSL_SRIO_RIO_EM_RST_PW_EN_RST_PW_EN_RESETVAL (0x00000000u)
4361 #define CSL_SRIO_RIO_EM_RST_PW_EN_RESETVAL (0x00000000u)
4363 /* rio_pw_bh */
4365 #define CSL_SRIO_RIO_PW_BH_NEXT_BLK_PTR_MASK (0xFFFF0000u)
4366 #define CSL_SRIO_RIO_PW_BH_NEXT_BLK_PTR_SHIFT (0x00000010u)
4367 #define CSL_SRIO_RIO_PW_BH_NEXT_BLK_PTR_RESETVAL (0x0000010Du)
4369 #define CSL_SRIO_RIO_PW_BH_BLK_REV_MASK (0x0000F000u)
4370 #define CSL_SRIO_RIO_PW_BH_BLK_REV_SHIFT (0x0000000Cu)
4371 #define CSL_SRIO_RIO_PW_BH_BLK_REV_RESETVAL (0x00000000u)
4373 #define CSL_SRIO_RIO_PW_BH_BLK_TYPE_MASK (0x00000FFFu)
4374 #define CSL_SRIO_RIO_PW_BH_BLK_TYPE_SHIFT (0x00000000u)
4375 #define CSL_SRIO_RIO_PW_BH_BLK_TYPE_RESETVAL (0x00000000u)
4377 #define CSL_SRIO_RIO_PW_BH_RESETVAL (0x010D0000u)
4379 /* rio_pw_ctl */
4381 #define CSL_SRIO_RIO_PW_CTL_PW_TIMER_MASK (0xF0000000u)
4382 #define CSL_SRIO_RIO_PW_CTL_PW_TIMER_SHIFT (0x0000001Cu)
4383 #define CSL_SRIO_RIO_PW_CTL_PW_TIMER_RESETVAL (0x00000000u)
4385 #define CSL_SRIO_RIO_PW_CTL_PWC_MODE_MASK (0x01000000u)
4386 #define CSL_SRIO_RIO_PW_CTL_PWC_MODE_SHIFT (0x00000018u)
4387 #define CSL_SRIO_RIO_PW_CTL_PWC_MODE_RESETVAL (0x00000000u)
4389 #define CSL_SRIO_RIO_PW_CTL_RESETVAL (0x00000000u)
4391 /* rio_pw_route */
4393 #define CSL_SRIO_RIO_PW_ROUTE_PORT_MASK (0x0000000Fu)
4394 #define CSL_SRIO_RIO_PW_ROUTE_PORT_SHIFT (0x00000000u)
4395 #define CSL_SRIO_RIO_PW_ROUTE_PORT_RESETVAL (0x00000001u)
4397 #define CSL_SRIO_RIO_PW_ROUTE_RESETVAL (0x00000001u)
4399 /* rio_pw_rx_stat */
4401 #define CSL_SRIO_RIO_PW_RX_STAT_WR_SIZE_MASK (0x0000F000u)
4402 #define CSL_SRIO_RIO_PW_RX_STAT_WR_SIZE_SHIFT (0x0000000Cu)
4403 #define CSL_SRIO_RIO_PW_RX_STAT_WR_SIZE_RESETVAL (0x00000000u)
4405 #define CSL_SRIO_RIO_PW_RX_STAT_WDPTR_MASK (0x00000100u)
4406 #define CSL_SRIO_RIO_PW_RX_STAT_WDPTR_SHIFT (0x00000008u)
4407 #define CSL_SRIO_RIO_PW_RX_STAT_WDPTR_RESETVAL (0x00000000u)
4409 #define CSL_SRIO_RIO_PW_RX_STAT_PW_SHORT_MASK (0x00000008u)
4410 #define CSL_SRIO_RIO_PW_RX_STAT_PW_SHORT_SHIFT (0x00000003u)
4411 #define CSL_SRIO_RIO_PW_RX_STAT_PW_SHORT_RESETVAL (0x00000000u)
4413 #define CSL_SRIO_RIO_PW_RX_STAT_PW_TRUNC_MASK (0x00000004u)
4414 #define CSL_SRIO_RIO_PW_RX_STAT_PW_TRUNC_SHIFT (0x00000002u)
4415 #define CSL_SRIO_RIO_PW_RX_STAT_PW_TRUNC_RESETVAL (0x00000000u)
4417 #define CSL_SRIO_RIO_PW_RX_STAT_PW_DISC_MASK (0x00000002u)
4418 #define CSL_SRIO_RIO_PW_RX_STAT_PW_DISC_SHIFT (0x00000001u)
4419 #define CSL_SRIO_RIO_PW_RX_STAT_PW_DISC_RESETVAL (0x00000000u)
4421 #define CSL_SRIO_RIO_PW_RX_STAT_PW_VAL_MASK (0x00000001u)
4422 #define CSL_SRIO_RIO_PW_RX_STAT_PW_VAL_SHIFT (0x00000000u)
4423 #define CSL_SRIO_RIO_PW_RX_STAT_PW_VAL_RESETVAL (0x00000000u)
4425 #define CSL_SRIO_RIO_PW_RX_STAT_RESETVAL (0x00000000u)
4427 /* rio_pw_rx_event_gen */
4429 #define CSL_SRIO_RIO_PW_RX_EVENT_GEN_PW_DISC_MASK (0x00000002u)
4430 #define CSL_SRIO_RIO_PW_RX_EVENT_GEN_PW_DISC_SHIFT (0x00000001u)
4431 #define CSL_SRIO_RIO_PW_RX_EVENT_GEN_PW_DISC_RESETVAL (0x00000000u)
4433 #define CSL_SRIO_RIO_PW_RX_EVENT_GEN_PW_VAL_MASK (0x00000001u)
4434 #define CSL_SRIO_RIO_PW_RX_EVENT_GEN_PW_VAL_SHIFT (0x00000000u)
4435 #define CSL_SRIO_RIO_PW_RX_EVENT_GEN_PW_VAL_RESETVAL (0x00000000u)
4437 #define CSL_SRIO_RIO_PW_RX_EVENT_GEN_RESETVAL (0x00000000u)
4439 /* rio_pw_rx_capt */
4441 #define CSL_SRIO_RIO_PW_RX_CAPT_PW_CAPT_MASK (0xFFFFFFFFu)
4442 #define CSL_SRIO_RIO_PW_RX_CAPT_PW_CAPT_SHIFT (0x00000000u)
4443 #define CSL_SRIO_RIO_PW_RX_CAPT_PW_CAPT_RESETVAL (0x00000000u)
4445 #define CSL_SRIO_RIO_PW_RX_CAPT_RESETVAL (0x00000000u)
4447 /* rio_llm_bh */
4449 #define CSL_SRIO_RIO_LLM_BH_NEXT_BLK_PTR_MASK (0xFFFF0000u)
4450 #define CSL_SRIO_RIO_LLM_BH_NEXT_BLK_PTR_SHIFT (0x00000010u)
4451 #define CSL_SRIO_RIO_LLM_BH_NEXT_BLK_PTR_RESETVAL (0x0000010Eu)
4453 #define CSL_SRIO_RIO_LLM_BH_BLK_REV_MASK (0x0000F000u)
4454 #define CSL_SRIO_RIO_LLM_BH_BLK_REV_SHIFT (0x0000000Cu)
4455 #define CSL_SRIO_RIO_LLM_BH_BLK_REV_RESETVAL (0x00000000u)
4457 #define CSL_SRIO_RIO_LLM_BH_BLK_TYPE_MASK (0x00000FFFu)
4458 #define CSL_SRIO_RIO_LLM_BH_BLK_TYPE_SHIFT (0x00000000u)
4459 #define CSL_SRIO_RIO_LLM_BH_BLK_TYPE_RESETVAL (0x00000000u)
4461 #define CSL_SRIO_RIO_LLM_BH_RESETVAL (0x010E0000u)
4463 /* rio_whiteboard */
4465 #define CSL_SRIO_RIO_WHITEBOARD_SCRATCH_MASK (0xFFFFFFFFu)
4466 #define CSL_SRIO_RIO_WHITEBOARD_SCRATCH_SHIFT (0x00000000u)
4467 #define CSL_SRIO_RIO_WHITEBOARD_SCRATCH_RESETVAL (0x00000000u)
4469 #define CSL_SRIO_RIO_WHITEBOARD_RESETVAL (0x00000000u)
4471 /* rio_port_number */
4473 #define CSL_SRIO_RIO_PORT_NUMBER_PORT_TOTAL_MASK (0x0000FF00u)
4474 #define CSL_SRIO_RIO_PORT_NUMBER_PORT_TOTAL_SHIFT (0x00000008u)
4475 #define CSL_SRIO_RIO_PORT_NUMBER_PORT_TOTAL_RESETVAL (0x00000004u)
4477 #define CSL_SRIO_RIO_PORT_NUMBER_PORT_NUM_MASK (0x000000FFu)
4478 #define CSL_SRIO_RIO_PORT_NUMBER_PORT_NUM_SHIFT (0x00000000u)
4479 #define CSL_SRIO_RIO_PORT_NUMBER_PORT_NUM_RESETVAL (0x00000000u)
4481 #define CSL_SRIO_RIO_PORT_NUMBER_RESETVAL (0x00000400u)
4483 /* rio_prescalar_srv_clk */
4485 #define CSL_SRIO_RIO_PRESCALAR_SRV_CLK_PRESCALAR_SRV_CLK_MASK (0x000000FFu)
4486 #define CSL_SRIO_RIO_PRESCALAR_SRV_CLK_PRESCALAR_SRV_CLK_SHIFT (0x00000000u)
4487 #define CSL_SRIO_RIO_PRESCALAR_SRV_CLK_PRESCALAR_SRV_CLK_RESETVAL (0x0000001Fu)
4489 #define CSL_SRIO_RIO_PRESCALAR_SRV_CLK_RESETVAL (0x0000001Fu)
4491 /* rio_reg_rst_ctl */
4493 #define CSL_SRIO_RIO_REG_RST_CTL_CLEAR_STICKY_MASK (0x00000001u)
4494 #define CSL_SRIO_RIO_REG_RST_CTL_CLEAR_STICKY_SHIFT (0x00000000u)
4495 #define CSL_SRIO_RIO_REG_RST_CTL_CLEAR_STICKY_RESETVAL (0x00000000u)
4497 #define CSL_SRIO_RIO_REG_RST_CTL_RESETVAL (0x00000000u)
4499 /* rio_local_err_det */
4501 #define CSL_SRIO_RIO_LOCAL_ERR_DET_ILL_ID_MASK (0x04000000u)
4502 #define CSL_SRIO_RIO_LOCAL_ERR_DET_ILL_ID_SHIFT (0x0000001Au)
4503 #define CSL_SRIO_RIO_LOCAL_ERR_DET_ILL_ID_RESETVAL (0x00000000u)
4505 #define CSL_SRIO_RIO_LOCAL_ERR_DET_ILL_TYPE_MASK (0x00400000u)
4506 #define CSL_SRIO_RIO_LOCAL_ERR_DET_ILL_TYPE_SHIFT (0x00000016u)
4507 #define CSL_SRIO_RIO_LOCAL_ERR_DET_ILL_TYPE_RESETVAL (0x00000000u)
4509 #define CSL_SRIO_RIO_LOCAL_ERR_DET_RESETVAL (0x00000000u)
4511 /* rio_local_err_en */
4513 #define CSL_SRIO_RIO_LOCAL_ERR_EN_ILL_ID_EN_MASK (0x04000000u)
4514 #define CSL_SRIO_RIO_LOCAL_ERR_EN_ILL_ID_EN_SHIFT (0x0000001Au)
4515 #define CSL_SRIO_RIO_LOCAL_ERR_EN_ILL_ID_EN_RESETVAL (0x00000000u)
4517 #define CSL_SRIO_RIO_LOCAL_ERR_EN_ILL_TYPE_EN_MASK (0x00400000u)
4518 #define CSL_SRIO_RIO_LOCAL_ERR_EN_ILL_TYPE_EN_SHIFT (0x00000016u)
4519 #define CSL_SRIO_RIO_LOCAL_ERR_EN_ILL_TYPE_EN_RESETVAL (0x00000000u)
4521 #define CSL_SRIO_RIO_LOCAL_ERR_EN_RESETVAL (0x00000000u)
4523 /* rio_local_h_addr_capt */
4525 #define CSL_SRIO_RIO_LOCAL_H_ADDR_CAPT_ADDR_MASK (0xFFFFFFFFu)
4526 #define CSL_SRIO_RIO_LOCAL_H_ADDR_CAPT_ADDR_SHIFT (0x00000000u)
4527 #define CSL_SRIO_RIO_LOCAL_H_ADDR_CAPT_ADDR_RESETVAL (0x00000000u)
4529 #define CSL_SRIO_RIO_LOCAL_H_ADDR_CAPT_RESETVAL (0x00000000u)
4531 /* rio_local_addr_capt */
4533 #define CSL_SRIO_RIO_LOCAL_ADDR_CAPT_ADDR_MASK (0xFFFFFFF8u)
4534 #define CSL_SRIO_RIO_LOCAL_ADDR_CAPT_ADDR_SHIFT (0x00000003u)
4535 #define CSL_SRIO_RIO_LOCAL_ADDR_CAPT_ADDR_RESETVAL (0x00000000u)
4537 #define CSL_SRIO_RIO_LOCAL_ADDR_CAPT_XAMSBS_MASK (0x00000003u)
4538 #define CSL_SRIO_RIO_LOCAL_ADDR_CAPT_XAMSBS_SHIFT (0x00000000u)
4539 #define CSL_SRIO_RIO_LOCAL_ADDR_CAPT_XAMSBS_RESETVAL (0x00000000u)
4541 #define CSL_SRIO_RIO_LOCAL_ADDR_CAPT_RESETVAL (0x00000000u)
4543 /* rio_local_id_capt */
4545 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_MSB_DEST_ID_MASK (0xFF000000u)
4546 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_MSB_DEST_ID_SHIFT (0x00000018u)
4547 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_MSB_DEST_ID_RESETVAL (0x00000000u)
4549 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_DEST_ID_MASK (0x00FF0000u)
4550 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_DEST_ID_SHIFT (0x00000010u)
4551 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_DEST_ID_RESETVAL (0x00000000u)
4553 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_MSB_SRC_ID_MASK (0x0000FF00u)
4554 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_MSB_SRC_ID_SHIFT (0x00000008u)
4555 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_MSB_SRC_ID_RESETVAL (0x00000000u)
4557 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_SRC_ID_MASK (0x000000FFu)
4558 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_SRC_ID_SHIFT (0x00000000u)
4559 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_SRC_ID_RESETVAL (0x00000000u)
4561 #define CSL_SRIO_RIO_LOCAL_ID_CAPT_RESETVAL (0x00000000u)
4563 /* rio_local_ctrl_capt */
4565 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_FTYPE_MASK (0xF0000000u)
4566 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_FTYPE_SHIFT (0x0000001Cu)
4567 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_FTYPE_RESETVAL (0x00000000u)
4569 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_TTYPE_MASK (0x0F000000u)
4570 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_TTYPE_SHIFT (0x00000018u)
4571 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_TTYPE_RESETVAL (0x00000000u)
4573 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_MESSAGE_INFO_MASK (0x00FF0000u)
4574 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_MESSAGE_INFO_SHIFT (0x00000010u)
4575 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_MESSAGE_INFO_RESETVAL (0x00000000u)
4577 #define CSL_SRIO_RIO_LOCAL_CTRL_CAPT_RESETVAL (0x00000000u)
4579 /* rio_fabric_bh */
4581 #define CSL_SRIO_RIO_FABRIC_BH_NEXT_BLK_PTR_MASK (0xFFFF0000u)
4582 #define CSL_SRIO_RIO_FABRIC_BH_NEXT_BLK_PTR_SHIFT (0x00000010u)
4583 #define CSL_SRIO_RIO_FABRIC_BH_NEXT_BLK_PTR_RESETVAL (0x00000000u)
4585 #define CSL_SRIO_RIO_FABRIC_BH_BLK_REV_MASK (0x0000F000u)
4586 #define CSL_SRIO_RIO_FABRIC_BH_BLK_REV_SHIFT (0x0000000Cu)
4587 #define CSL_SRIO_RIO_FABRIC_BH_BLK_REV_RESETVAL (0x00000000u)
4589 #define CSL_SRIO_RIO_FABRIC_BH_BLK_TYPE_MASK (0x00000FFFu)
4590 #define CSL_SRIO_RIO_FABRIC_BH_BLK_TYPE_SHIFT (0x00000000u)
4591 #define CSL_SRIO_RIO_FABRIC_BH_BLK_TYPE_RESETVAL (0x00000000u)
4593 #define CSL_SRIO_RIO_FABRIC_BH_RESETVAL (0x00000000u)
4595 /* rio_fabric_csr */
4597 #define CSL_SRIO_RIO_FABRIC_CSR_IG_LLM_BACKPRESSURE_MASK (0x08000000u)
4598 #define CSL_SRIO_RIO_FABRIC_CSR_IG_LLM_BACKPRESSURE_SHIFT (0x0000001Bu)
4599 #define CSL_SRIO_RIO_FABRIC_CSR_IG_LLM_BACKPRESSURE_RESETVAL (0x00000000u)
4601 #define CSL_SRIO_RIO_FABRIC_CSR_IG_UC_BACKPRESSURE_MASK (0x04000000u)
4602 #define CSL_SRIO_RIO_FABRIC_CSR_IG_UC_BACKPRESSURE_SHIFT (0x0000001Au)
4603 #define CSL_SRIO_RIO_FABRIC_CSR_IG_UC_BACKPRESSURE_RESETVAL (0x00000000u)
4605 #define CSL_SRIO_RIO_FABRIC_CSR_RESETVAL (0x00000000u)
4607 /* rio_sp_fabric_status */
4609 #define CSL_SRIO_RIO_SP_FABRIC_STATUS_IG_PKT_ENABLE_STATUS_MASK (0x00F00000u)
4610 #define CSL_SRIO_RIO_SP_FABRIC_STATUS_IG_PKT_ENABLE_STATUS_SHIFT (0x00000014u)
4611 #define CSL_SRIO_RIO_SP_FABRIC_STATUS_IG_PKT_ENABLE_STATUS_RESETVAL (0x00000000u)
4613 #define CSL_SRIO_RIO_SP_FABRIC_STATUS_EG_PKT_ENABLE_STATUS_MASK (0x000F0000u)
4614 #define CSL_SRIO_RIO_SP_FABRIC_STATUS_EG_PKT_ENABLE_STATUS_SHIFT (0x00000010u)
4615 #define CSL_SRIO_RIO_SP_FABRIC_STATUS_EG_PKT_ENABLE_STATUS_RESETVAL (0x00000000u)
4617 #define CSL_SRIO_RIO_SP_FABRIC_STATUS_RESETVAL (0x00000000u)
4619 #endif