pdk_k2g_1_0_1/packages/ti/csl/docs/doxygen/html/functions_vars_d.html

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  31       <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
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  35     <ul class="tablist">
  36       <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
  37       <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
  38       <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
  39       <li class="current"><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
  40       <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
  41       <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
  42       <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
  43       <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
  44       <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
  45       <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
  46       <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
  47       <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
  48       <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
  49       <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
  50       <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
  51       <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
  52       <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
  53       <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
  54       <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
  55       <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
  56       <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
  57       <li><a href="functions_vars_x.html#index_x"><span>x</span></a></li>
  58       <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
  59       <li><a href="functions_vars_z.html#index_z"><span>z</span></a></li>
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  63 <div class="contents">
  64 &#160;
  65
  66 <h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
  67 <li>data
  68 : <a class="el" href="group___c_s_l___m_d_i_o___d_a_t_a_s_t_r_u_c_t.html#ga0bd3c39c4f31eef489c8ccfb3226fb07">CSL_MDIO_USERACCESS</a>
  69 , <a class="el" href="structpcie_msi_mailbox_params.html#a16512b5264123a9d4fcec97900ba82d8">pcieMsiMailboxParams</a>
  70 </li>
  71 <li>DataFormat
  72 : <a class="el" href="struct_c_s_l___aif2_pd_ch_config1.html#ae435ac02c36111febc891d6eaec65e9c">CSL_Aif2PdChConfig1</a>
  73 , <a class="el" href="struct_c_s_l___aif2_pd_ch_config.html#a0c103250422e813776dff644bcbcb3e1">CSL_Aif2PdChConfig</a>
  74 </li>
  75 <li>dataLength
  76 : <a class="el" href="structdcan_msg_params.html#a6b402aeddc6afbcdaa242db23d1b23f5">dcanMsgParams</a>
  77 </li>
  78 <li>DataOffset
  79 : <a class="el" href="struct___e_m_a_c___pkt.html#a6a5c353cd38fb5667d2a2ab3b70093eb">_EMAC_Pkt</a>
  80 </li>
  81 <li>dataRegs
  82 : <a class="el" href="struct_c_s_l___r_a_c___base_address.html#a42f0088bf70dd40cbc234aa8d003b10b">CSL_RAC_BaseAddress</a>
  83 , <a class="el" href="struct_c_s_l___r_a_c___obj__s.html#a9854048dd4ffa0bb6062b45183cffdf7">CSL_RAC_Obj_s</a>
  84 </li>
  85 <li>DataSwap
  86 : <a class="el" href="struct_c_s_l___aif2_db_channel.html#ad25195f5665a67fccbef49aa93000aad">CSL_Aif2DbChannel</a>
  87 </li>
  88 <li>day
  89 : <a class="el" href="struct_c_s_l__rtc_date_obj.html#acf3aaf0ce126a2fca9224015f27589b5">CSL_rtcDateObj</a>
  90 </li>
  91 <li>db_ee_e_cd_data_err
  92 : <a class="el" href="struct_c_s_l___aif2_ee_db_int.html#a587c4c14e4ac6cd361d4587797c8c48c">CSL_Aif2EeDbInt</a>
  93 </li>
  94 <li>db_ee_e_cd_data_type_err
  95 : <a class="el" href="struct_c_s_l___aif2_ee_db_int.html#a3c2820cc395d33ef2ebe6c54328049eb">CSL_Aif2EeDbInt</a>
  96 </li>
  97 <li>db_ee_e_ps_axc_err
  98 : <a class="el" href="struct_c_s_l___aif2_ee_db_int.html#ac76bc98fd9a2f735a39dc757e40e6973">CSL_Aif2EeDbInt</a>
  99 </li>
 100 <li>db_ee_i_fifo_ovfl_err
 101 : <a class="el" href="struct_c_s_l___aif2_ee_db_int.html#a14379e03466751c821d24559086d58f8">CSL_Aif2EeDbInt</a>
 102 </li>
 103 <li>db_ee_i_pd2db_full_err
 104 : <a class="el" href="struct_c_s_l___aif2_ee_db_int.html#aa99d5ec66b46cdbecbc8d68a1217a8c4">CSL_Aif2EeDbInt</a>
 105 </li>
 106 <li>db_ee_i_token_ovfl_err
 107 : <a class="el" href="struct_c_s_l___aif2_ee_db_int.html#a0b7668e8bbd0efaf3b0f120befe7abd2">CSL_Aif2EeDbInt</a>
 108 </li>
 109 <li>db_ee_i_trc_ram_ovfl_err
 110 : <a class="el" href="struct_c_s_l___aif2_ee_db_int.html#a49aa967fb18b2e269fbc6790ddd43fb8">CSL_Aif2EeDbInt</a>
 111 </li>
 112 <li>db_en_sts
 113 : <a class="el" href="struct_c_s_l___aif2_ee_origin.html#a55152a27e6cc4b960aa34a9b97bcf68d">CSL_Aif2EeOrigin</a>
 114 </li>
 115 <li>DBCN
 116 : <a class="el" href="struct_c_s_l___aif2_ad_dio_engine.html#a22165b8ca43a7256353abae6141ea6b0">CSL_Aif2AdDioEngine</a>
 117 </li>
 118 <li>Dbm1Map
 119 : <a class="el" href="struct_c_s_l___aif2_dual_bit_map.html#aac2ac2a98669245f5ae09858346b9c91">CSL_Aif2DualBitMap</a>
 120 </li>
 121 <li>Dbm1Mult
 122 : <a class="el" href="struct_c_s_l___aif2_dual_bit_map.html#a4ed4e67902efc5b97c8625888c54431a">CSL_Aif2DualBitMap</a>
 123 </li>
 124 <li>Dbm1Size
 125 : <a class="el" href="struct_c_s_l___aif2_dual_bit_map.html#a1f95dd7a8577776bcf87cc01ebe8723e">CSL_Aif2DualBitMap</a>
 126 </li>
 127 <li>Dbm2Map
 128 : <a class="el" href="struct_c_s_l___aif2_dual_bit_map.html#a019c47093095ebfd16885b01d06fe7ad">CSL_Aif2DualBitMap</a>
 129 </li>
 130 <li>Dbm2Size
 131 : <a class="el" href="struct_c_s_l___aif2_dual_bit_map.html#ad6300b82bfa21c9c413f5111ea1b2c6f">CSL_Aif2DualBitMap</a>
 132 </li>
 133 <li>DbmX
 134 : <a class="el" href="struct_c_s_l___aif2_dual_bit_map.html#a9683891c99359b70ab790f2a6db229f0">CSL_Aif2DualBitMap</a>
 135 </li>
 136 <li>DbmXBubble
 137 : <a class="el" href="struct_c_s_l___aif2_dual_bit_map.html#a23b7713566fed268aa8bc92c3e883bcf">CSL_Aif2DualBitMap</a>
 138 </li>
 139 <li>dccEnable
 140 : <a class="el" href="struct_c_s_l___pllc_mpu_param.html#af6f46e3728eac4546735b8717c413a85">CSL_PllcMpuParam</a>
 141 , <a class="el" href="struct_c_s_l___pllc_param.html#aeb9e06f1cf0790dc3bcad19648253f83">CSL_PllcParam</a>
 142 </li>
 143 <li>ddrPhyCtrl
 144 : <a class="el" href="struct_c_s_l__emif_ddr_param.html#a0deadd1d7cc332db1cf10cb45be08062">CSL_emifDdrParam</a>
 145 </li>
 146 <li>decBuffLen
 147 : <a class="el" href="struct_v_c_p2___params.html#af429fbd0a712178c6bc285503393d97c">VCP2_Params</a>
 148 </li>
 149 <li>decision
 150 : <a class="el" href="struct_v_c_p2___base_params.html#a006f5b62cf3ca01ce46a7d89a3555911">VCP2_BaseParams</a>
 151 , <a class="el" href="struct_v_c_p2___params.html#a82fbfb6390a1615c87ccb20906c5257a">VCP2_Params</a>
 152 </li>
 153 <li>defThread
 154 : <a class="el" href="struct_c_s_l___c_p_s_w___a_l_e___p_o_l_i_c_e_r___g_l_o_b___c_o_n_f_i_g.html#a667e79112030c26bc33985d16ef3e2c5">CSL_CPSW_ALE_POLICER_GLOB_CONFIG</a>
 155 </li>
 156 <li>defThreadEnable
 157 : <a class="el" href="struct_c_s_l___c_p_s_w___a_l_e___p_o_l_i_c_e_r___g_l_o_b___c_o_n_f_i_g.html#ab6a1fe30f625b67e646763a13825513d">CSL_CPSW_ALE_POLICER_GLOB_CONFIG</a>
 158 </li>
 159 <li>DeltaOffset
 160 : <a class="el" href="struct_c_s_l___aif2_at_link_setup.html#a30fb2d29897558fc23b57628587effb3">CSL_Aif2AtLinkSetup</a>
 161 </li>
 162 <li>DescBase
 163 : <a class="el" href="struct___e_m_a_c___core___config.html#aa4856e054407dc135164cac355622335">_EMAC_Core_Config</a>
 164 </li>
 165 <li>DescCount
 166 : <a class="el" href="struct___e_m_a_c___desc_ch.html#ae18c68da9ed6ff73c4f69ce73906fd19">_EMAC_DescCh</a>
 167 </li>
 168 <li>DescMax
 169 : <a class="el" href="struct___e_m_a_c___desc_ch.html#af264d6a870801d57da5b1b78a20e902e">_EMAC_DescCh</a>
 170 </li>
 171 <li>DescQueue
 172 : <a class="el" href="struct___e_m_a_c___desc_ch.html#ad20fd8af7b217ce005be656fd2acb24a">_EMAC_DescCh</a>
 173 </li>
 174 <li>destAddr
 175 : <a class="el" href="struct_e_d_m_a3_c_c_pa_r_a_m_entry.html#a3a7072ac7fda10eb842aa66310144ad7">EDMA3CCPaRAMEntry</a>
 176 </li>
 177 <li>destBIdx
 178 : <a class="el" href="struct_e_d_m_a3_c_c_pa_r_a_m_entry.html#a99df86c1cb021e909586b5566743ee2b">EDMA3CCPaRAMEntry</a>
 179 </li>
 180 <li>destCIdx
 181 : <a class="el" href="struct_e_d_m_a3_c_c_pa_r_a_m_entry.html#aaa817fd65833add639157c6cba97f6ed">EDMA3CCPaRAMEntry</a>
 182 </li>
 183 <li>destn
 184 : <a class="el" href="struct_c_s_l___i_d_m_a___i_d_m_a0_c_o_n_f_i_g.html#af8079a2fb0e006eabb665c7aedcfcac2">CSL_IDMA_IDMA0CONFIG</a>
 185 , <a class="el" href="struct_c_s_l___i_d_m_a___i_d_m_a1_c_o_n_f_i_g.html#a548960628f4eb581051d0275eec8880a">CSL_IDMA_IDMA1CONFIG</a>
 186 </li>
 187 <li>DevMagic
 188 : <a class="el" href="struct___e_m_a_c___device.html#afc6d81a58f6642aee8e9575c04a7607e">_EMAC_Device</a>
 189 </li>
 190 <li>diagSliceCfg
 191 : <a class="el" href="structtesoc_diagnostic_slice_cfg.html#a6cb12dbcb8594e94adba5a1aab379236">tesocDiagnosticSliceCfg</a>
 192 </li>
 193 <li>diagSliceNumber
 194 : <a class="el" href="structtesoc_diagnostic_slice_cfg.html#a8461fd9606e24dabb37a791f00afc2aa">tesocDiagnosticSliceCfg</a>
 195 </li>
 196 <li>DioAddress
 197 : <a class="el" href="struct_c_s_l___aif2_db_side_data.html#a813ee0a9e8942c3c1b7e5e89c1bc9cf2">CSL_Aif2DbSideData</a>
 198 </li>
 199 <li>DioBufferLen
 200 : <a class="el" href="struct_c_s_l___aif2_egr_db_setup.html#ac3f41a96e9dafb29b89d51040a0af0ac">CSL_Aif2EgrDbSetup</a>
 201 , <a class="el" href="struct_c_s_l___aif2_ingr_db_setup.html#ad336f9dbcbf939cb1230ab3cb7e37cb2">CSL_Aif2IngrDbSetup</a>
 202 </li>
 203 <li>DioFrameEventOffset
 204 : <a class="el" href="struct_c_s_l___aif2_at_event.html#a5ee3b44a5419fb65ee8f2bf798f178d9">CSL_Aif2AtEvent</a>
 205 </li>
 206 <li>DioFrameStrobeSel
 207 : <a class="el" href="struct_c_s_l___aif2_at_event.html#ac5efd2756dbbdbd14ddc5b9f280b60a2">CSL_Aif2AtEvent</a>
 208 </li>
 209 <li>DioOffset
 210 : <a class="el" href="struct_c_s_l___aif2_pd_ch_config1.html#aeed708a8c29a76a2e4a87aaa7e36f819">CSL_Aif2PdChConfig1</a>
 211 </li>
 212 <li>dir
 213 : <a class="el" href="struct_c_s_l___x_m_c___x_p_f_a_d_d_r.html#a7efb56c305e0aba894f66afb6a78fb08">CSL_XMC_XPFADDR</a>
 214 </li>
 215 <li>direction
 216 : <a class="el" href="structdcan_msg_obj_cfg_params.html#a8eaf9f744feb595a04d957d3f05abc2f">dcanMsgObjCfgParams</a>
 217 </li>
 218 <li>dirMask
 219 : <a class="el" href="structdcan_msg_obj_cfg_params.html#a8d9872da26b15797eb7b4f2cd7a693be">dcanMsgObjCfgParams</a>
 220 </li>
 221 <li>DisableLinkClock
 222 : <a class="el" href="struct_c_s_l___aif2_sd_common_setup.html#a0ad498a35a440d462c838a650b6ba32c">CSL_Aif2SdCommonSetup</a>
 223 </li>
 224 <li>distBasePtr
 225 : <a class="el" href="struct_c_s_l___arm_gic_dist_intrf.html#ab4e3749c691aae398508944f11b64b6c">CSL_ArmGicDistIntrf</a>
 226 </li>
 227 <li>div
 228 : <a class="el" href="struct_c_s_l___pllc_abe_param.html#afbe0eccb569448f296dc4238fabd7378">CSL_PllcAbeParam</a>
 229 , <a class="el" href="struct_c_s_l___pllc_core_param.html#ac9a727cbc5b41bd03861f921aa1f346d">CSL_PllcCoreParam</a>
 230 , <a class="el" href="struct_c_s_l___pllc_ddr_param.html#a5a23bbf291b18c55981219e00319bc54">CSL_PllcDdrParam</a>
 231 , <a class="el" href="struct_c_s_l___pllc_dsp_param.html#aa3a769b5238955c3de80d9541f57c71f">CSL_PllcDspParam</a>
 232 , <a class="el" href="struct_c_s_l___pllc_gmac_param.html#a710ae4878899eb9957ead3880bfedf16">CSL_PllcGmacParam</a>
 233 , <a class="el" href="struct_c_s_l___pllc_gpu_param.html#addb37add2002f820562474235f65648f">CSL_PllcGpuParam</a>
 234 , <a class="el" href="struct_c_s_l___pllc_iva_param.html#a82f61c0928f5937dfa39a465d6c45b8a">CSL_PllcIvaParam</a>
 235 , <a class="el" href="struct_c_s_l___pllc_mpu_param.html#ae4ce139775bb19b14ad100feee316924">CSL_PllcMpuParam</a>
 236 , <a class="el" href="struct_c_s_l___pllc_param.html#a27015e5c6005a41ed1faad5bb2720ef8">CSL_PllcParam</a>
 237 , <a class="el" href="struct_c_s_l___pllc_pcie_param.html#a43483a22c572985acbee1c45843ee195">CSL_PllcPcieParam</a>
 238 , <a class="el" href="struct_c_s_l___pllc_per_param.html#a84649f3415b63e906228ef722f433a20">CSL_PllcPerParam</a>
 239 </li>
 240 <li>divH11
 241 : <a class="el" href="struct_c_s_l___pllc_ddr_param.html#af4099d7ffa2860c6f42bd87f32043a5e">CSL_PllcDdrParam</a>
 242 , <a class="el" href="struct_c_s_l___pllc_gmac_param.html#a48c10e82a0c8b413242268cae5fb204c">CSL_PllcGmacParam</a>
 243 , <a class="el" href="struct_c_s_l___pllc_param.html#ae673137360409340ab8bab492ba4d3ec">CSL_PllcParam</a>
 244 , <a class="el" href="struct_c_s_l___pllc_per_param.html#a769bf1efbc6773ba3630dd53b2163ff3">CSL_PllcPerParam</a>
 245 </li>
 246 <li>divH12
 247 : <a class="el" href="struct_c_s_l___pllc_core_param.html#a22abd7e9ee7d4cf93e1a1c9bd7fb930b">CSL_PllcCoreParam</a>
 248 , <a class="el" href="struct_c_s_l___pllc_gmac_param.html#abf09950a1be11a665adbd1e17ba5bcf8">CSL_PllcGmacParam</a>
 249 , <a class="el" href="struct_c_s_l___pllc_param.html#a4a92e1b5060035e67b5897511680037e">CSL_PllcParam</a>
 250 , <a class="el" href="struct_c_s_l___pllc_per_param.html#a04ac7e99d5e84bc8aaab63de256097cf">CSL_PllcPerParam</a>
 251 </li>
 252 <li>divH13
 253 : <a class="el" href="struct_c_s_l___pllc_core_param.html#a8ce1053b113879b35f8cd0bd59d06fe5">CSL_PllcCoreParam</a>
 254 , <a class="el" href="struct_c_s_l___pllc_gmac_param.html#a31b43026b99f659ca85326843c479fd6">CSL_PllcGmacParam</a>
 255 , <a class="el" href="struct_c_s_l___pllc_param.html#a93d5da7cacb2a4162d805bf6b53cf30c">CSL_PllcParam</a>
 256 , <a class="el" href="struct_c_s_l___pllc_per_param.html#a0ad9db9db606ea226a129c7ea16a13df">CSL_PllcPerParam</a>
 257 </li>
 258 <li>divH14
 259 : <a class="el" href="struct_c_s_l___pllc_core_param.html#a72eb758b2c68f9995413b75bc0dba0e3">CSL_PllcCoreParam</a>
 260 , <a class="el" href="struct_c_s_l___pllc_param.html#a4584d6dd97944c9c48d2280344341676">CSL_PllcParam</a>
 261 , <a class="el" href="struct_c_s_l___pllc_per_param.html#a6240f9b8cc45a96cb058485616280343">CSL_PllcPerParam</a>
 262 </li>
 263 <li>divH21
 264 : <a class="el" href="struct_c_s_l___pllc_param.html#a89e62914ffbaf3151dfdeb2ffdeb70ba">CSL_PllcParam</a>
 265 </li>
 266 <li>divH22
 267 : <a class="el" href="struct_c_s_l___pllc_core_param.html#a32c948bf42a9c14c974ca6e9b67398b4">CSL_PllcCoreParam</a>
 268 , <a class="el" href="struct_c_s_l___pllc_param.html#a9fb4548b509816d197723034d94bc8a4">CSL_PllcParam</a>
 269 </li>
 270 <li>divH23
 271 : <a class="el" href="struct_c_s_l___pllc_core_param.html#af76e8a532bd9ec506d3d143216543d93">CSL_PllcCoreParam</a>
 272 , <a class="el" href="struct_c_s_l___pllc_param.html#ad07b546306e135a878aa6b8ec5b62420">CSL_PllcParam</a>
 273 </li>
 274 <li>divH24
 275 : <a class="el" href="struct_c_s_l___pllc_core_param.html#ad60eb0935b35eb65cb4467a157342a87">CSL_PllcCoreParam</a>
 276 , <a class="el" href="struct_c_s_l___pllc_param.html#a72409405304506588d1883c65f42eea1">CSL_PllcParam</a>
 277 </li>
 278 <li>divM2
 279 : <a class="el" href="struct_c_s_l___pllc_abe_param.html#a5b8a6a223a47a3efc5f4595d232107ca">CSL_PllcAbeParam</a>
 280 , <a class="el" href="struct_c_s_l___pllc_core_param.html#a8d8602183d0b228b3c4ef871bb855bed">CSL_PllcCoreParam</a>
 281 , <a class="el" href="struct_c_s_l___pllc_ddr_param.html#a6fa45ed597d563830980e5ae43a690a8">CSL_PllcDdrParam</a>
 282 , <a class="el" href="struct_c_s_l___pllc_dsp_param.html#aca2286981fe2869855ccef5b2dca0cd1">CSL_PllcDspParam</a>
 283 , <a class="el" href="struct_c_s_l___pllc_gmac_param.html#a057eea6f17d546ff2f1630cc97bc8586">CSL_PllcGmacParam</a>
 284 , <a class="el" href="struct_c_s_l___pllc_gpu_param.html#a6225139443bef48e160b76929568078c">CSL_PllcGpuParam</a>
 285 , <a class="el" href="struct_c_s_l___pllc_iva_param.html#ae7d219efc31b1af7cc6ec068008e5542">CSL_PllcIvaParam</a>
 286 , <a class="el" href="struct_c_s_l___pllc_mpu_param.html#a5cdb78c5cd8461f990405d887e45c6e1">CSL_PllcMpuParam</a>
 287 , <a class="el" href="struct_c_s_l___pllc_param.html#afce347bff62ce7c7185728e9af7ea6a5">CSL_PllcParam</a>
 288 , <a class="el" href="struct_c_s_l___pllc_pcie_param.html#a15574226f7ac65bf5aad009e5ea994d2">CSL_PllcPcieParam</a>
 289 , <a class="el" href="struct_c_s_l___pllc_per_param.html#aaa66dc728323aee80de7ea20784ff548">CSL_PllcPerParam</a>
 290 </li>
 291 <li>divM3
 292 : <a class="el" href="struct_c_s_l___pllc_abe_param.html#aeb4a400e9d908b0f9ae3f5c3e2c8a1d5">CSL_PllcAbeParam</a>
 293 , <a class="el" href="struct_c_s_l___pllc_core_param.html#a1ad05d870c123090be376be8d93d858a">CSL_PllcCoreParam</a>
 294 , <a class="el" href="struct_c_s_l___pllc_ddr_param.html#a9225cf1ab47bd536aa9f2ffe8585a79e">CSL_PllcDdrParam</a>
 295 , <a class="el" href="struct_c_s_l___pllc_dsp_param.html#a09df3207496ececea83f3427d922301d">CSL_PllcDspParam</a>
 296 , <a class="el" href="struct_c_s_l___pllc_gmac_param.html#a5c5687e3b9876d05687dfff14254d7e3">CSL_PllcGmacParam</a>
 297 , <a class="el" href="struct_c_s_l___pllc_param.html#ac50765036d2f957cc05f2fb70249604d">CSL_PllcParam</a>
 298 , <a class="el" href="struct_c_s_l___pllc_per_param.html#aeb560e285c5e4467eed06bf25b4e2303">CSL_PllcPerParam</a>
 299 </li>
 300 <li>DmaBaseAddr
 301 : <a class="el" href="struct_c_s_l___aif2_ad_dio_engine.html#a83799ef9e8a94156e379bd094be4280c">CSL_Aif2AdDioEngine</a>
 302 </li>
 303 <li>DmaBlockAddrStride
 304 : <a class="el" href="struct_c_s_l___aif2_ad_dio_engine.html#ab8ac2c972751ddcbfb61139047860971">CSL_Aif2AdDioEngine</a>
 305 </li>
 306 <li>DmaBurstAddrStride
 307 : <a class="el" href="struct_c_s_l___aif2_ad_dio_engine.html#a11ddac4c5a892d18a4d1970193f2838c">CSL_Aif2AdDioEngine</a>
 308 </li>
 309 <li>DmaBurstLen
 310 : <a class="el" href="struct_c_s_l___aif2_ad_dio_engine.html#a3e5dcaade5571eafd4fa6b3700b74639">CSL_Aif2AdDioEngine</a>
 311 </li>
 312 <li>DmaChannel
 313 : <a class="el" href="struct_c_s_l___aif2_rt_header_status.html#a6f6018a7cfa3251991c3b1d57bbee6b4">CSL_Aif2RtHeaderStatus</a>
 314 </li>
 315 <li>dmaChaSetup
 316 : <a class="el" href="struct_c_s_l___edma3_hw_setup.html#aec4491606fe03da9f4988c4f38286dd1">CSL_Edma3HwSetup</a>
 317 </li>
 318 <li>DmaNumBlock
 319 : <a class="el" href="struct_c_s_l___aif2_ad_dio_engine.html#a9ab18b7c84123d472bdf5b3258a0c2f7">CSL_Aif2AdDioEngine</a>
 320 </li>
 321 <li>domain
 322 : <a class="el" href="struct_c_s_l___a15_mmu_short_desc_attr.html#a6294e9ef9350db1802cd159160cbc6d8">CSL_A15MmuShortDescAttr</a>
 323 , <a class="el" href="struct_c_s_l___c_p_t_s___e_v_e_n_t_i_n_f_o.html#af292194d6d7bd8decb8ebddc82263446">CSL_CPTS_EVENTINFO</a>
 324 </li>
 325 <li>domainLabel
 326 : <a class="el" href="structtesoc_advance_result.html#a1164a0b8c61f5c2f6b618a6eb11106a2">tesocAdvanceResult</a>
 327 , <a class="el" href="structtesoc_diagnostic_slice_cfg.html#a168151a5af7ef27731569e7a94adcc51">tesocDiagnosticSliceCfg</a>
 328 , <a class="el" href="structtesoc_test_cfg.html#abd8c0903d2a78f4a09c48da5ffca7070">tesocTestCfg</a>
 329 </li>
 330 <li>doubleBitErr
 331 : <a class="el" href="structdcan_ecc_err_status.html#a3dcdf6eb5cee8fa0755b0b437faa10a7">dcanEccErrStatus</a>
 332 </li>
 333 <li>dph
 334 : <a class="el" href="struct_c_s_l___x_m_c___x_p_f_a_d_d_r.html#a5c908b21e142a76c3dd4f630327ac1c7">CSL_XMC_XPFADDR</a>
 335 </li>
 336 <li>dpl
 337 : <a class="el" href="struct_c_s_l___x_m_c___x_p_f_a_d_d_r.html#af66fb649f208d544635cf57ce94bf51a">CSL_XMC_XPFADDR</a>
 338 </li>
 339 <li>dqOffset
 340 : <a class="el" href="struct_c_s_l__emif_ddr_phy_param.html#aa64fd99273a7d4d38fdba3373db4521a">CSL_emifDdrPhyParam</a>
 341 </li>
 342 <li>drae
 343 : <a class="el" href="struct_c_s_l___edma3_cmd_drae__s.html#a01096be346457eaea5f609a5e33c480f">CSL_Edma3CmdDrae_s</a>
 344 </li>
 345 <li>draeh
 346 : <a class="el" href="struct_c_s_l___edma3_cmd_drae__s.html#a86ffafe650dfbd60d1bf76af03cc98cc">CSL_Edma3CmdDrae_s</a>
 347 </li>
 348 <li>drop
 349 : <a class="el" href="struct_c_s_l___intc_drop_status.html#a9ea2fa6b4cd91acea35cc52ca2e7c9ca">CSL_IntcDropStatus</a>
 350 </li>
 351 <li>dropUntaggedEnable
 352 : <a class="el" href="struct_c_s_l___c_p_s_w__3_g_f___a_l_e___p_o_r_t_c_o_n_t_r_o_l.html#ae862065c7f786859c539efc9caa08d28">CSL_CPSW_3GF_ALE_PORTCONTROL</a>
 353 , <a class="el" href="struct_c_s_l___c_p_s_w__5_g_f___a_l_e___p_o_r_t_c_o_n_t_r_o_l.html#ae8d0741c47aa925128bdae65880358ac">CSL_CPSW_5GF_ALE_PORTCONTROL</a>
 354 , <a class="el" href="struct_c_s_l___c_p_s_w___a_l_e___p_o_r_t_c_o_n_t_r_o_l.html#a7a8522c1f0b0563fbfdad07add0bb313">CSL_CPSW_ALE_PORTCONTROL</a>
 355 </li>
 356 <li>dscpIpv4Enable
 357 : <a class="el" href="struct_c_s_l___c_p_s_w___p_o_r_t___c_o_n_t_r_o_l.html#a86d49223f4661d33f3f1106ef65c19ef">CSL_CPSW_PORT_CONTROL</a>
 358 </li>
 359 <li>dscpIpv6Enable
 360 : <a class="el" href="struct_c_s_l___c_p_s_w___p_o_r_t___c_o_n_t_r_o_l.html#aca2bd9c357b644a4fb1c76aba3f330af">CSL_CPSW_PORT_CONTROL</a>
 361 </li>
 362 <li>dstAddr
 363 : <a class="el" href="struct_c_s_l___edma3_param_setup__s.html#a12b02b005ffecc5fea6cfba843060b63">CSL_Edma3ParamSetup_s</a>
 364 </li>
 365 <li>dstIpIdx
 366 : <a class="el" href="struct_c_s_l___c_p_s_w___a_l_e___p_o_l_i_c_e_r___e_n_t_r_y.html#ac95dab360767be5baebbda8a3ff87689">CSL_CPSW_ALE_POLICER_ENTRY</a>
 367 </li>
 368 <li>dstMacIdx
 369 : <a class="el" href="struct_c_s_l___c_p_s_w___a_l_e___p_o_l_i_c_e_r___e_n_t_r_y.html#a29071024a4fd80da7781f68cc359776c">CSL_CPSW_ALE_POLICER_ENTRY</a>
 370 </li>
 371 <li>DualBitMap
 372 : <a class="el" href="struct_c_s_l___aif2_pe_dbmr.html#a4a1d8adb2865a3597215b42dd7c6eeee">CSL_Aif2PeDbmr</a>
 373 </li>
 374 <li>duplex
 375 : <a class="el" href="struct_c_s_l___c_p_s_w___w_r___r_g_m_i_i___s_t_a_t_u_s.html#ab8cc920c692caf9b84873669aadd3026">CSL_CPSW_WR_RGMII_STATUS</a>
 376 </li>
 377 <li>duplexMode
 378 : <a class="el" href="struct_c_s_l___s_g_m_i_i___a_d_v_a_b_i_l_i_t_y.html#a7af1b15903df148a52cab7f3e776c031">CSL_SGMII_ADVABILITY</a>
 379 </li>
 380 <li>dvh
 381 : <a class="el" href="struct_c_s_l___x_m_c___x_p_f_a_d_d_r.html#a0e533cf5d246192069b78258d4d6b07f">CSL_XMC_XPFADDR</a>
 382 </li>
 383 <li>dvl
 384 : <a class="el" href="struct_c_s_l___x_m_c___x_p_f_a_d_d_r.html#a94fac2dfa7a20a2357b409fb6cf56df2">CSL_XMC_XPFADDR</a>
 385 </li>
 386 </ul>
 387 </div><!-- contents -->
 388 <hr size="1"><small>
 389 Copyright  2016, Texas Instruments Incorporated</small>
 390 </body>
 391 </html>