[processor-sdk/performance-audio-sr.git] / pdk_k2g_1_0_1 / packages / ti / csl / src / ip / uart / V0 / uart.h
1 /**
2 * @file uart.h
3 *
4 * @brief This file contains the prototypes of the functions defined in
5 * <uart.c>. This also contains some related macro
6 * definitions and some files to be included.
7 *
8 */
10 /*
11 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
12 */
13 /*
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 *
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the
24 * distribution.
25 *
26 * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 */
44 #ifndef UART_K2_LLD_H
45 #define UART_K2_LLD_H
48 #include <ti/csl/src/ip/uart/V0/cslr_uart.h>
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
54 /****************************************************************************
55 ** MACRO DEFINITIONS
56 ****************************************************************************/
57 #ifndef CSL_UART_FCR
58 #define CSL_UART_FCR (CSL_UART_IIR) /* IIR & FCR have same offset */
59 #endif
61 #ifndef CSL_UART_THR
62 #define CSL_UART_THR (CSL_UART_RBR) /* RBR & THR have same offset */
63 #endif
65 #define MEM_BARRIER_DISABLE
66 /* The size of the Transmitter FIFO. */
67 #define TX_FIFO_SIZE (16U)
68 /* The size of the Receiver FIFO. */
69 #define RX_FIFO_SIZE (16U)
71 /*
72 ** Values to configure the Operating modes of UART.
73 */
74 #define UART16x_OPER_MODE (CSL_UART_MDR_OSM_SEL__16XOVERSAMPLING)
75 #define UART13x_OPER_MODE (CSL_UART_MDR_OSM_SEL__13XOVERSAMPLING)
76 #define UART_DISABLED_MODE (CSL_UART_MDR_OSM_SEL_RESETVAL)
78 /****************************************************************************/
79 /*
80 ** Values to control the Line characteristics.
81 */
83 /* Break condition generation controls. */
84 #define UART_BREAK_COND_DISABLE (CSL_UART_LCR_BC_DISABLE << \
85 CSL_UART_LCR_BC_SHIFT)
86 #define UART_BREAK_COND_ENABLE (CSL_UART_LCR_BC_ENABLE << \
87 CSL_UART_LCR_BC_SHIFT)
89 /* Values to control parity feature. */
91 #define UART_PARITY_REPR_1 (CSL_UART_LCR_PARITY_TYPE2_MASK | \
92 (0 << \
93 CSL_UART_LCR_PARITY_TYPE1_SHIFT) | \
94 CSL_UART_LCR_PARITY_EN_PARITY_EN_VALUE_1)
96 #define UART_PARITY_REPR_0 (CSL_UART_LCR_PARITY_TYPE2_MASK | \
97 (1 << \
98 CSL_UART_LCR_PARITY_TYPE1_SHIFT) | \
99 CSL_UART_LCR_PARITY_EN_PARITY_EN_VALUE_1)
101 #define UART_ODD_PARITY ((0 << \
102 CSL_UART_LCR_PARITY_TYPE1_SHIFT) | \
103 CSL_UART_LCR_PARITY_EN_PARITY_EN_VALUE_1)
105 #define UART_EVEN_PARITY ((1 << \
106 CSL_UART_LCR_PARITY_TYPE1_SHIFT) | \
107 CSL_UART_LCR_PARITY_EN_PARITY_EN_VALUE_1)
109 #define UART_PARITY_NONE (0x0 << \
110 0x00000003u)
113 #define UART_INT_MODEM_STAT (0x00000008u)
114 #define UART_INT_LINE_STAT (0x00000004u)
115 #define UART_INT_THR (0x00000002u)
116 #define UART_INT_RHR_CTI (0x00000001u)
118 /****************************************************************************/
119 /*
120 ** Miscellaneous macros.
121 */
122 /*
123 ** Values used to choose the trigger level granularity.
124 */
125 #define UART_TRIG_LVL_GRANULARITY_4 (0x0000)
126 #define UART_TRIG_LVL_GRANULARITY_1 (0x0001)
128 /* Values to be used while switching between register configuration modes. */
130 #define UART_REG_CONFIG_MODE_A (0x0080U)
131 #define UART_REG_CONFIG_MODE_B (0x00BFU)
132 #define UART_REG_OPERATIONAL_MODE (0x007FU)
134 /* Parameterized macro to configure the FIFO settings. */
135 #define UART_FIFO_CONFIG(rxTrig, txClr, rxClr, dmaMode1) \
136 ((uint32_t) \
137 ((((rxTrig) & 0xFFU) << 6U) | \
138 (((txClr) & 0x1U) << 5U) | \
139 (((rxClr) & 0x1U) << 4U) | \
140 ((dmaMode1) & 0x1U)))
142 /****************************************************************************/
143 /*
144 ** Values to configure the FIFO control.
145 */
146 #define UART_FIFO_ENABLE (0x1u) /* TX/RX FIFOs mode enable */
147 #define UART_FIFO_DISABLE (0x0u) /* TX/RX FIFOs mode disable */
148 #define UART_FIFO_TXCLR (0x1u) /* Clears TX FIFO */
149 #define UART_FIFO_RXCLR (0x1u) /* Clears RX FIFO */
150 #define UART_FIFO_DMAMODE1_ENABLE (0x1u) /* DMA mode 1 enable */
151 #define UART_FIFO_DMAMODE1_DISABLE (0x0u) /* DMA mode 1 disable */
152 #define UART_FIFO_RXTL0 (0x0u) /* RX FIFO trigger level 0: 1 byte */
153 #define UART_FIFO_RXTL1 (0x1u) /* RX FIFO trigger level 1: 4 byte */
154 #define UART_FIFO_RXTL2 (0x2u) /* RX FIFO trigger level 2: 8 byte */
155 #define UART_FIFO_RXTL3 (0x3u) /* RX FIFO trigger level 3: 14 byte */
157 #define UART_FIFO_RXTRIG_SHIFT (CSL_UART_FCR_RXFIFTL_SHIFT)
159 #define UART_FIFO_CONFIG_RXTRIG ((0xFFU) << 6U)
160 #define UART_FIFO_CONFIG_TXCLR (UART_FIFO_TXCLR << 5)
161 #define UART_FIFO_CONFIG_RXCLR (UART_FIFO_RXCLR << 4)
162 #define UART_FIFO_CONFIG_DMAMODE1 (UART_FIFO_DMAMODE1_ENABLE << 0)
164 /* Parameterized macro used to determine a value to be written to FCR. */
165 #define UART_FCR_PROGRAM(rxFIFOTrig, dmaMode1, txClr, rxClr, fifoEn) \
166 ((uint32_t) \
167 ((((rxFIFOTrig) << CSL_UART_FCR_RXFIFTL_SHIFT) & CSL_UART_FCR_RXFIFTL_MASK) | \
168 (((dmaMode1) << CSL_UART_FCR_DMAMODE1_SHIFT) & CSL_UART_FCR_DMAMODE1_MASK)| \
169 (((txClr) << CSL_UART_FCR_TXCLR_SHIFT) & CSL_UART_FCR_TXCLR_MASK) | \
170 (((rxClr) << CSL_UART_FCR_RXCLR_SHIFT) & CSL_UART_FCR_RXCLR_MASK)| \
171 ((fifoEn) & CSL_UART_FCR_FIFOEN_MASK)))
173 /*
174 ** Values used to configure the power and emulation management register.
175 */
176 #define UART_PWREMU_MGMT_ENABLE (CSL_UART_PWREMU_MGMT_UTRST_MASK | \
177 CSL_UART_PWREMU_MGMT_URRST_MASK | \
178 CSL_UART_PWREMU_MGMT_FREE_MASK)
180 /******************************************************************************
181 ** FUNCTION PROTOTYPES
182 ******************************************************************************/
184 /* APIs pertaining to UART. */
186 extern uint32_t UART_operatingModeSelect_v0(uint32_t baseAdd,
187 uint32_t modeFlag);
188 extern uint32_t UART_divisorValCompute_v0(uint32_t moduleClk,
189 uint32_t baudRate,
190 uint32_t modeFlag);
191 extern uint32_t UART_divisorLatchWrite_v0(uint32_t baseAdd,
192 uint32_t divisorValue);
193 extern void UART_divisorLatchEnable_v0(uint32_t baseAdd);
194 extern void UART_divisorLatchDisable_v0(uint32_t baseAdd);
195 extern uint32_t UART_regConfigModeEnable_v0(uint32_t baseAdd,
196 uint32_t modeFlag);
197 extern void UART_breakCtl_v0(uint32_t baseAdd, uint32_t breakState);
198 extern void UART_lineCharacConfig_v0(uint32_t baseAdd,
199 uint32_t wLenStbFlag,
200 uint32_t parityFlag);
201 extern void UART_parityModeSet_v0(uint32_t baseAdd, uint32_t parityFlag);
202 extern uint32_t UART_parityModeGet_v0(uint32_t baseAdd);
204 extern uint32_t UART_fIFOConfig_v0(uint32_t baseAdd,
205 uint32_t fifoConfig);
207 extern void UART_intEnable_v0(uint32_t baseAdd, uint32_t intFlag);
208 extern void UART_intDisable_v0(uint32_t baseAdd, uint32_t intFlag);
209 extern int8_t UART_charGetNonBlocking_v0(uint32_t baseAdd);
210 extern int8_t UART_charGet_v0(uint32_t baseAdd);
211 extern int32_t UART_charGetTimeout_v0(uint32_t baseAdd,
212 uint32_t timeOutVal);
214 extern void UART_charPut_v0(uint32_t baseAdd, uint8_t byteTx);
215 extern void UART_fIFOCharPut_v0(uint32_t baseAdd, uint8_t byteTx);
216 extern int8_t UART_fIFOCharGet_v0(uint32_t baseAdd);
217 extern uint32_t UART_fIFOWrite_v0(uint32_t baseAdd, const uint8_t *pBuffer,
218 uint32_t numTxBytes);
219 extern void UART_fIFORegisterWrite_v0(uint32_t baseAdd, uint32_t fcrValue);
220 extern void UART_fifoWait_v0(uint32_t baseAdd);
221 extern uint32_t UART_fifoEmpty_v0(uint32_t baseAdd);
223 extern uint32_t UART_intIdentityGet_v0(uint32_t baseAdd);
224 extern uint32_t UART_pwremuConfig_v0(uint32_t baseAdd, uint32_t pwremuConfig);
225 #ifdef __cplusplus
226 }
227 #endif
229 #endif
231 /********************************* End of File********************************/