[processor-sdk/performance-audio-sr.git] / pdk_k2g_1_0_1_0_eng / packages / ti / board / diag / icss_emac / src / icss_emac_main.c
1 /*
2 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
15 * distribution.
16 *
17 * Neither the name of Texas Instruments Incorporated nor the names of
18 * its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34 #include "stdio.h"
35 #include "string.h"
36 #include <stdlib.h>
37 #include <stdint.h>
39 #include <ti/csl/src/ip/mdio/V2/cslr_mdio.h>
40 #include <ti/csl/src/ip/mdio/V2/csl_mdio.h>
41 #include <ti/csl/src/ip/mdio/V2/csl_mdioAux.h>
42 #include <ti/csl/src/ip/icss/V0/cslr_icss_intc.h>
43 #include <ti/csl/hw_types.h>
45 #include "ti/drv/icss_emac/icss_emacDrv.h"
47 #ifdef SOC_AM572x
48 #include "ti/drv/icss_emac/soc/am572x/icss_emacSoc.c"
49 #include <ti/drv/icss_emac/firmware/am57x/v1_0/icss_emac_pru0_bin.h>
50 #include <ti/drv/icss_emac/firmware/am57x/v1_0/icss_emac_pru1_bin.h>
51 #include <ti/drv/pruss/soc/am572x/pruicss_device.c>
52 #include <ti/csl/soc/am572x/src/csl_device_xbar.h>
53 #define PRU0_FIRMWARE_V1_0_NAME PRU0_FIRMWARE_V1_0 // name of the C struct in PRU header file for PG version 1.x
54 #define PRU1_FIRMWARE_V1_1_NAME PRU1_FIRMWARE_V1_0 // name of the C struct in PRU header file for PG versin 1.x
56 #include <ti/drv/icss_emac/firmware/am57x/v2_1/icss_emac_pru0_bin.h>
57 #include <ti/drv/icss_emac/firmware/am57x/v2_1/icss_emac_pru1_bin.h>
58 #define PRU0_FIRMWARE_NAME PRU0_FIRMWARE // name of the C struct in PRU header file
59 #define PRU1_FIRMWARE_NAME PRU1_FIRMWARE // name of the C struct in PRU header file
60 #endif
62 #ifdef SOC_AM571x
63 #include "ti/drv/icss_emac/soc/am571x/icss_emacSoc.c"
64 #include <ti/drv/icss_emac/firmware/am57x/v2_1/icss_emac_pru0_bin.h>
65 #include <ti/drv/icss_emac/firmware/am57x/v2_1/icss_emac_pru1_bin.h>
66 #include <ti/drv/pruss/soc/am571x/pruicss_device.c>
67 #include <ti/csl/soc/am571x/src/csl_device_xbar.h>
68 #define PRU0_FIRMWARE_NAME PRU0_FIRMWARE // name of the C struct in PRU header file
69 #define PRU1_FIRMWARE_NAME PRU1_FIRMWARE // name of the C struct in PRU header file
70 #endif
72 #include "hw_ctrl_core_pad_io.h"
73 #include "icss_emac_startup.h"
74 #include "tiemac_pruss_intc_mapping.h"
76 #include <ti/csl/cslr.h>
77 #include <ti/csl/tistdtypes.h>
78 #include <ti/csl/cslr_device.h>
79 #include <ti/csl/csl_rtc.h>
80 #include <ti/csl/csl_rtcAux.h>
81 #include <ti/csl/csl_a15.h>
82 #include <ti/csl/csl_a15Aux.h>
83 #include <ti/csl/csl_armGic.h>
84 #include <ti/csl/csl_armGicAux.h>
85 #include <ti/csl/src/ip/arm_gic/V1/cslr_arm_gic_distr.h>
87 #include <ti/drv/gpio/src/v1/GPIO_v1_lld.h>
89 #include <ti/drv/uart/UART.h>
90 #include <ti/drv/uart/UART_stdio.h>
92 #include "board.h"
93 #include "board_cfg.h"
95 #define PKT_TX_COUNT 5
97 #define SWITCH_DEFAULT_MDIOBUSFREQ (2200000u)
98 #define SWITCH_DEFAULT_MDIOCLOCKFREQ (200000000)
100 #define MDIO_LINKSEL_ENABLE 1
101 #define MDIO_LINKSEL_DISABLE 0
102 static int phyCount = 0;
104 PRUICSS_Handle pruIcssHandle;
105 ICSS_EmacHandle emachandle;
106 uint32_t packetRcvd_port0 = 0;
107 uint32_t totalPktRcvd = 0;
110 CSL_ArmGicDistIntrf distrIntrf;
111 CSL_ArmGicCpuIntrf gCpuIntrf;
112 CSL_ArmGicIntrParams_t gIcssEmacIntrParams;
113 CSL_ArmGicIntrParams_t gIcssEmacIntrParamsLink;
115 uint32_t pktReceived = 0;
116 uint32_t totalPktsRcvd = 0;
118 PRUICSS_IntcInitData pruss_intc_initdata = PRUSS_INTC_INITDATA;
120 uint8_t lclMac[6];
122 /* DO NOT CHANGE test_pkt UNLESS TEST_PKT_SIZE IS UPDATED */
123 #define TEST_PKT_SIZE 42
124 static const uint8_t test_pkt[] = {
125 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* broadcast mac */
126 0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
127 0x08, 0x06, 0x00, 0x01,
128 0x08, 0x00, 0x06, 0x04, 0x00,0x01,
129 0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
130 0xc0, 0xa8, 0x01, 0x16,
131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
132 0xc0, 0xa8,0x01, 0x02
133 };
135 uint8_t packet_array[256] = {0};
139 #define PULLUDENABLE_ENABLE (0U)
140 #define PULLUDENABLE_DISABLE (1U)
141 #define PULLTYPESELECT_PULL_UP (1U)
142 #define PULLTYPESELECT_PULL_DOWN (0U)
143 #define INPUTENABLE_ENABLE (1U)
144 #define INPUTENABLE_DISABLE (0U)
145 #define SLEWCONTROL_FAST_SLEW (0U)
146 #define SLEWCONTROL_SLOW_SLEW (1U)
147 #define WAKEUPENABLE_ENABLE (1U)
148 #define WAKEUPENABLE_DISABLE (0U)
150 typedef struct {
151 uint32_t pin_num;
152 uint8_t muxmode;
153 uint8_t pullud_enable;
154 uint8_t pull_typeselect;
155 uint8_t input_enable;
156 uint8_t slewcontrol;
157 uint8_t wakeup_enable;
158 }pad_config_t;
164 #define PRUSS_INSTANCE_IN_USE 2
168 void pruss_iep_PinMux(uint8_t prussn);
169 void pruss_iep_Initialization(uint8_t prussn);
170 void pruss_iep_MemFill(uint32_t StartAddress, uint32_t Length , uint16_t Pattern);
171 void pruss_iep_MDIOInitialization(uint8_t prussn);
173 typedef struct GPIO_INFO {
174 uint32_t instance;
175 uint32_t pin;
176 uint32_t pinMux;
177 uint32_t baseAddr;
179 }GPIO_INFO;
180 GPIO_INFO PhyResetInfo[4], PhyIntInfo[4];
183 static unsigned char prussIcssInstance = PRUSS_INSTANCE_IN_USE;
185 void SOCCtrlGetPortMacAddr(uint32_t portNum, uint8_t *pMacAddr)
186 {
189 if(portNum == 0) {
190 pMacAddr[5U] = (HW_RD_REG32(0x4A002514)
191 >> 8U) & 0xFFU;
192 pMacAddr[4U] = (HW_RD_REG32(0x4A002514))
193 & 0xFF;
194 pMacAddr[3U] = (HW_RD_REG32(0x4A002518)
195 >> 24U) & 0xFFU;
196 pMacAddr[2U] = (HW_RD_REG32(0x4A002518)
197 >> 16U) & 0xFFU;
198 pMacAddr[1U] = (HW_RD_REG32(0x4A002518)
199 >> 8U) & 0xFFU;
200 pMacAddr[0U] = (HW_RD_REG32(0x4A002518))
201 & 0xFFU;
202 }
203 else {
204 pMacAddr[5U] = (HW_RD_REG32(0x4A00251c)
205 >> 8U) & 0xFFU;
206 pMacAddr[4U] = (HW_RD_REG32(0x4A00251c))
207 & 0xFF;
208 pMacAddr[3U] = (HW_RD_REG32(0x4A002520)
209 >> 24U) & 0xFFU;
210 pMacAddr[2U] = (HW_RD_REG32(0x4A002520)
211 >> 16U) & 0xFFU;
212 pMacAddr[1U] = (HW_RD_REG32(0x4A002520)
213 >> 8U) & 0xFFU;
214 pMacAddr[0U] = (HW_RD_REG32(0x4A002520))
215 & 0xFFU;
216 }
217 }
220 void Delay(uint32_t delay)
221 {
222 volatile uint32_t delay1 = delay*10;
223 while (delay1--) ;
224 }
227 /***********************************************************************/
228 /* local functions declaration */
229 /***********************************************************************/
230 //void PowerGPIO();
231 /***********************************************************************/
232 /* function definitions */
233 /***********************************************************************/
235 void cntrl_core_pad_configuration(uint32_t baseAdd, pad_config_t *pad_config)
236 {
237 uint32_t reg_val;
239 //PlatformUnlockMMR();
240 reg_val = HWREG(baseAdd + (pad_config->pin_num));
242 reg_val &= ~CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_MUXMODE_MASK;
244 reg_val |= (uint32_t) pad_config->muxmode <<
245 CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_MUXMODE_SHIFT;
247 if (pad_config->pullud_enable != 0xFF)
248 {
249 reg_val &= ~CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_PULLUDENABLE_MASK;
250 reg_val |= (uint32_t) pad_config->pullud_enable <<
251 CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_PULLUDENABLE_SHIFT;
252 }
253 if (pad_config->pull_typeselect != 0xFF)
254 {
255 reg_val &= ~CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_PULLTYPESELECT_MASK;
256 reg_val |= (uint32_t) pad_config->pull_typeselect <<
257 CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_PULLTYPESELECT_SHIFT;
258 }
259 if (pad_config->input_enable != 0xFF)
260 {
261 reg_val &= ~CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_INPUTENABLE_MASK;
262 reg_val |= (uint32_t) pad_config->input_enable <<
263 CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_INPUTENABLE_SHIFT;
264 }
265 if (pad_config->slewcontrol != 0xFF)
266 {
267 reg_val &= ~CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_SLEWCONTROL_MASK;
268 reg_val |= (uint32_t) pad_config->slewcontrol <<
269 CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_SLEWCONTROL_SHIFT;
270 }
271 if (pad_config->wakeup_enable != 0xFF)
272 {
273 reg_val &= ~CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_WAKEUPENABLE_MASK;
274 reg_val |= (uint32_t) pad_config->wakeup_enable <<
275 CTRL_CORE_PAD_GPMC_AD0_GPMC_AD0_WAKEUPENABLE_SHIFT;
276 }
278 HWREG(baseAdd + (pad_config->pin_num)) = reg_val;
279 //PlatformLockMMR();
280 }
283 void configure_pad(pad_config_t *pad_array, uint32_t elements)
284 {
285 uint32_t i;
287 for (i = 0; i < elements; ++i)
288 {
289 cntrl_core_pad_configuration(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS,
290 &pad_array[i]);
291 }
292 }
295 void pruss_iep_PinMux(uint8_t prussn)
296 {
298 if(prussn==1)
299 {
300 /*
301 Port 0 - PRUSS1 IEP0
303 RGMII0_RXC - PR1_MII_MT0_CLK
304 RGMII0_RXD2 - PR1_MII0_TXEN
305 RGMII0_RXD0 - PR1_MII0_TXD0
306 RGMII0_RXD1 - PR1_MII0_TXD1
307 RGMII0_RXD3 - PR1_MII0_TXD2
308 RGMII0_RXCTL - PR1_MII0_TXD3
310 UART3_TXD - PR1_MII_MR0_CLK
311 UART3_RXD - PR1_MII0_RXDV
312 RGMII0_TXD2 - PR1_MII0_RXER
314 RGMII0_TXD0 - PR1_MII0_RXD0
315 RGMII0_TXD1 - PR1_MII0_RXD1
316 RGMII0_TXCTL - PR1_MII0_RXD2
317 RGMII0_TXC - PR1_MII0_RXD3
319 RGMII0_TXD3 - PR1_MII0_CRS
320 MDIO_CLK - PR1_MII0_COL
321 MDIO_DATA - PR1_MII0_RXLINK
323 VIN2A_D10 - PR1_MDIO_MDCLK
324 VIN2A_D11 - PR1_MDIO_DATA
325 */
326 pad_config_t pruss1_iep0_pad_config[] = {
328 /* MDIO (2 pads) */
329 {CTRL_CORE_PAD_VIN2A_D10,
330 CTRL_CORE_PAD_VIN2A_D10_VIN2A_D10_MUXMODE_PR1_MDIO_MDCLK_11,
331 PULLUDENABLE_ENABLE,
332 PULLTYPESELECT_PULL_UP, INPUTENABLE_ENABLE, 0xff,
333 WAKEUPENABLE_DISABLE},
335 {CTRL_CORE_PAD_VIN2A_D11,
336 CTRL_CORE_PAD_VIN2A_D11_VIN2A_D11_MUXMODE_PR1_MDIO_DATA_11,
337 PULLUDENABLE_ENABLE,
338 PULLTYPESELECT_PULL_UP, INPUTENABLE_ENABLE, 0xff, WAKEUPENABLE_DISABLE},
340 /*Pin_num,Muxmode,pullud_enable,pull_typeselect,io,slewrate,wakeupmode*/
341 {CTRL_CORE_PAD_RGMII0_RXC,
342 CTRL_CORE_PAD_RGMII0_RXC_RGMII0_RXC_MUXMODE_PR1_MII_MT0_CLK_11,
343 PULLUDENABLE_ENABLE,
344 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
345 WAKEUPENABLE_DISABLE},
347 {CTRL_CORE_PAD_RGMII0_RXD2,
348 CTRL_CORE_PAD_RGMII0_RXD2_RGMII0_RXD2_MUXMODE_PR1_MII0_TXEN_11,
349 PULLUDENABLE_ENABLE,
350 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
351 WAKEUPENABLE_DISABLE},
353 {CTRL_CORE_PAD_RGMII0_RXD0,
354 CTRL_CORE_PAD_RGMII0_RXD0_RGMII0_RXD0_MUXMODE_PR1_MII0_TXD0_11,
355 PULLUDENABLE_ENABLE,
356 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
357 WAKEUPENABLE_DISABLE},
359 {CTRL_CORE_PAD_RGMII0_RXD1,
360 CTRL_CORE_PAD_RGMII0_RXD1_RGMII0_RXD1_MUXMODE_PR1_MII0_TXD1_11,
361 PULLUDENABLE_ENABLE,
362 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
363 WAKEUPENABLE_DISABLE},
365 {CTRL_CORE_PAD_RGMII0_RXD3,
366 CTRL_CORE_PAD_RGMII0_RXD3_RGMII0_RXD3_MUXMODE_PR1_MII0_TXD2_11,
367 PULLUDENABLE_ENABLE,
368 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
369 WAKEUPENABLE_DISABLE},
371 {CTRL_CORE_PAD_RGMII0_RXCTL,
372 CTRL_CORE_PAD_RGMII0_RXCTL_RGMII0_RXCTL_MUXMODE_PR1_MII0_TXD3_11,
373 PULLUDENABLE_ENABLE,
374 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
375 WAKEUPENABLE_DISABLE},
377 {CTRL_CORE_PAD_UART3_TXD,
378 CTRL_CORE_PAD_UART3_TXD_UART3_TXD_MUXMODE_PR1_MII_MR0_CLK_11,
379 PULLUDENABLE_ENABLE,
380 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
381 WAKEUPENABLE_DISABLE},
383 {CTRL_CORE_PAD_UART3_RXD,
384 CTRL_CORE_PAD_UART3_RXD_UART3_RXD_MUXMODE_PR1_MII0_RXDV_11,
385 PULLUDENABLE_ENABLE,
386 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
387 WAKEUPENABLE_DISABLE},
389 {CTRL_CORE_PAD_RGMII0_TXD2,
390 CTRL_CORE_PAD_RGMII0_TXD2_RGMII0_TXD2_MUXMODE_PR1_MII0_RXER_11,
391 PULLUDENABLE_ENABLE,
392 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
393 WAKEUPENABLE_DISABLE},
395 {CTRL_CORE_PAD_RGMII0_TXD0,
396 CTRL_CORE_PAD_RGMII0_TXD0_RGMII0_TXD0_MUXMODE_PR1_MII0_RXD0_11,
397 PULLUDENABLE_ENABLE,
398 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
399 WAKEUPENABLE_DISABLE},
401 {CTRL_CORE_PAD_RGMII0_TXD1,
402 CTRL_CORE_PAD_RGMII0_TXD1_RGMII0_TXD1_MUXMODE_PR1_MII0_RXD1_11,
403 PULLUDENABLE_ENABLE,
404 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
405 WAKEUPENABLE_DISABLE},
407 {CTRL_CORE_PAD_RGMII0_TXCTL,
408 CTRL_CORE_PAD_RGMII0_TXCTL_RGMII0_TXCTL_MUXMODE_PR1_MII0_RXD2_11,
409 PULLUDENABLE_ENABLE,
410 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
411 WAKEUPENABLE_DISABLE},
413 {CTRL_CORE_PAD_RGMII0_TXC,
414 CTRL_CORE_PAD_RGMII0_TXC_RGMII0_TXC_MUXMODE_PR1_MII0_RXD3_11,
415 PULLUDENABLE_ENABLE,
416 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
417 WAKEUPENABLE_DISABLE},
419 {CTRL_CORE_PAD_RGMII0_TXD3,
420 CTRL_CORE_PAD_RGMII0_TXD3_RGMII0_TXD3_MUXMODE_PR1_MII0_CRS_11,
421 PULLUDENABLE_ENABLE,
422 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
423 WAKEUPENABLE_DISABLE},
424 #if 0
425 {CTRL_CORE_PAD_MDIO_MCLK,
426 CTRL_CORE_PAD_MDIO_MCLK_MDIO_MCLK_MUXMODE_PR1_MII0_COL_11,
427 PULLUDENABLE_ENABLE,
428 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
429 WAKEUPENABLE_DISABLE},
430 #else
431 {CTRL_CORE_PAD_MDIO_MCLK,
432 0xff,
433 0xff,
434 0xff, 0xff, 0xff,
435 0xff},
436 #endif
437 {CTRL_CORE_PAD_MDIO_D,
438 CTRL_CORE_PAD_MDIO_D_MDIO_D_MUXMODE_PR1_MII0_RXLINK_11,
439 PULLUDENABLE_ENABLE,
440 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
441 WAKEUPENABLE_DISABLE}
442 };
444 /*configure the rgmii pad*/
445 configure_pad(pruss1_iep0_pad_config, sizeof (pruss1_iep0_pad_config) /
446 sizeof (pruss1_iep0_pad_config[0]));
449 /*
450 Port 1 - PRUSS1 IEP1
452 VIN2A_D6 - PR1_MII_MT1_CLK
453 VIN2A_D7 - PR1_MII1_TXEN
454 VIN2A_D13 - PR1_MII1_TXD0
455 VIN2A_D12 - PR1_MII1_TXD1
456 VIN2A_D9 - PR1_MII1_TXD2
457 VIN2A_D8 - PR1_MII1_TXD3
459 VIN2A_D14 - PR1_MII_MR1_CLK
460 VIN2A_D15 - PR1_MII1_RXDV
461 VIN2A_D20 - PR1_MII1_RXER
463 VIN2A_D19 - PR1_MII1_RXD0
464 VIN2A_D18 - PR1_MII1_RXD1
465 VIN2A_D17 - PR1_MII1_RXD2
466 VIN2A_D16 - PR1_MII1_RXD3
468 VIN2A_D23 - PR1_MII1_CRS
469 VIN2A_D22 - PR1_MII1_COL
470 VIN2A_D21 - PR1_MII1_RXLINK
472 */
474 pad_config_t pruss1_iep1_pad_config[] = {
476 /*Pin_num,Muxmode,pullud_enable,pull_typeselect,io,slewrate,wakeupmode*/
477 {CTRL_CORE_PAD_VIN2A_D6,
478 CTRL_CORE_PAD_VIN2A_D6_VIN2A_D6_MUXMODE_PR1_MII_MT1_CLK_11,
479 PULLUDENABLE_ENABLE,
480 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
481 WAKEUPENABLE_DISABLE},
483 {CTRL_CORE_PAD_VIN2A_D7,
484 CTRL_CORE_PAD_VIN2A_D7_VIN2A_D7_MUXMODE_PR1_MII1_TXEN_11,
485 PULLUDENABLE_ENABLE,
486 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
487 WAKEUPENABLE_DISABLE},
489 {CTRL_CORE_PAD_VIN2A_D13,
490 CTRL_CORE_PAD_VIN2A_D13_VIN2A_D13_MUXMODE_PR1_MII1_TXD0_11,
491 PULLUDENABLE_ENABLE,
492 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
493 WAKEUPENABLE_DISABLE},
495 {CTRL_CORE_PAD_VIN2A_D12,
496 CTRL_CORE_PAD_VIN2A_D12_VIN2A_D12_MUXMODE_PR1_MII1_TXD1_11,
497 PULLUDENABLE_ENABLE,
498 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
499 WAKEUPENABLE_DISABLE},
501 {CTRL_CORE_PAD_VIN2A_D9,
502 CTRL_CORE_PAD_VIN2A_D9_VIN2A_D9_MUXMODE_PR1_MII1_TXD2_11,
503 PULLUDENABLE_ENABLE,
504 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
505 WAKEUPENABLE_DISABLE},
507 {CTRL_CORE_PAD_VIN2A_D8,
508 CTRL_CORE_PAD_VIN2A_D8_VIN2A_D8_MUXMODE_PR1_MII1_TXD3_11,
509 PULLUDENABLE_ENABLE,
510 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
511 WAKEUPENABLE_DISABLE},
513 {CTRL_CORE_PAD_VIN2A_D14,
514 CTRL_CORE_PAD_VIN2A_D14_VIN2A_D14_MUXMODE_PR1_MII_MR1_CLK_11,
515 PULLUDENABLE_ENABLE,
516 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
517 WAKEUPENABLE_DISABLE},
519 {CTRL_CORE_PAD_VIN2A_D15,
520 CTRL_CORE_PAD_VIN2A_D15_VIN2A_D15_MUXMODE_PR1_MII1_RXDV_11,
521 PULLUDENABLE_ENABLE,
522 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
523 WAKEUPENABLE_DISABLE},
525 {CTRL_CORE_PAD_VIN2A_D20,
526 CTRL_CORE_PAD_VIN2A_D20_VIN2A_D20_MUXMODE_PR1_MII1_RXER_11,
527 PULLUDENABLE_ENABLE,
528 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
529 WAKEUPENABLE_DISABLE},
531 {CTRL_CORE_PAD_VIN2A_D19,
532 CTRL_CORE_PAD_VIN2A_D19_VIN2A_D19_MUXMODE_PR1_MII1_RXD0_11,
533 PULLUDENABLE_ENABLE,
534 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
535 WAKEUPENABLE_DISABLE},
537 {CTRL_CORE_PAD_VIN2A_D18,
538 CTRL_CORE_PAD_VIN2A_D18_VIN2A_D18_MUXMODE_PR1_MII1_RXD1_11,
539 PULLUDENABLE_ENABLE,
540 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
541 WAKEUPENABLE_DISABLE},
543 {CTRL_CORE_PAD_VIN2A_D17,
544 CTRL_CORE_PAD_VIN2A_D17_VIN2A_D17_MUXMODE_PR1_MII1_RXD2_11,
545 PULLUDENABLE_ENABLE,
546 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
547 WAKEUPENABLE_DISABLE},
549 {CTRL_CORE_PAD_VIN2A_D16,
550 CTRL_CORE_PAD_VIN2A_D16_VIN2A_D16_MUXMODE_PR1_MII1_RXD3_11,
551 PULLUDENABLE_ENABLE,
552 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
553 WAKEUPENABLE_DISABLE},
555 {CTRL_CORE_PAD_VIN2A_D23,
556 CTRL_CORE_PAD_VIN2A_D23_VIN2A_D23_MUXMODE_PR1_MII1_CRS_11,
557 PULLUDENABLE_ENABLE,
558 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
559 WAKEUPENABLE_DISABLE},
560 #if 0
561 {CTRL_CORE_PAD_VIN2A_D22,
562 CTRL_CORE_PAD_VIN2A_D22_VIN2A_D22_MUXMODE_PR1_MII1_COL_11,
563 PULLUDENABLE_ENABLE,
564 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
565 WAKEUPENABLE_DISABLE},
566 #else
567 {CTRL_CORE_PAD_VIN2A_D22,
568 0xff,
569 0xff,
570 0xff, 0xff, 0xff,
571 0xff},
572 #endif
573 {CTRL_CORE_PAD_VIN2A_D21,
574 CTRL_CORE_PAD_VIN2A_D21_VIN2A_D21_MUXMODE_PR1_MII1_RXLINK_11,
575 PULLUDENABLE_ENABLE,
576 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
577 WAKEUPENABLE_DISABLE},
578 };
580 /*configure the rgmii pad*/
581 configure_pad(pruss1_iep1_pad_config, sizeof (pruss1_iep1_pad_config) /
582 sizeof (pruss1_iep1_pad_config[0]));
586 }
587 else
588 {
589 /*
590 Port2 - PRUSS2 IEP 0
592 MCASP1_AXR1 - PR2_MII_MT0_CLK
593 MCASP1_AXR8 - PR2_MII0_TXEN
594 MCASP1_AXR12 - PR2_MII0_TXD0
595 MCASP1_AXR11 - PR2_MII0_TXD1
596 MCASP1_AXR10 - PR2_MII0_TXD2
597 MCASP1_AXR9 - PR2_MII0_TXD3
599 MCASP1_AXR13 - PR2_MII_MR0_CLK
600 MCASP1_AXR14 - PR2_MII0_RXDV
601 MCASP1_AXR0 -PR2_MII0_RXER
603 MCASP2_AXR2 -PR2_MII0_RXD0
604 MCASP2_FSX - PR2_MII0_RXD1
605 MCASP2_ACLKX - PR2_MII0_RXD2
606 MCASP1_AXR15 - PR2_MII0_RXD3
608 MCASP3_ACLKX - PR2_MII0_CRS
609 MCASP3_FSX - PR2_MII0_COL
610 MCASP2_AXR3 - PR2_MII0_RXLINK
612 MCASP1_ACLKX - PR2_MDIO_MDCLK
613 MCASP1_FSX - PR2_MDIO_DATA
615 */
617 pad_config_t pruss2_iep0_pad_config[] = {
619 /* MDIO (2 pads) */
620 {CTRL_CORE_PAD_MCASP1_ACLKX,
621 CTRL_CORE_PAD_MCASP1_ACLKX_MCASP1_ACLKX_MUXMODE_PR2_MDIO_MDCLK_11,
622 PULLUDENABLE_ENABLE,
623 PULLTYPESELECT_PULL_UP, INPUTENABLE_ENABLE, 0xff,
624 WAKEUPENABLE_DISABLE},
626 {CTRL_CORE_PAD_MCASP1_FSX,
627 CTRL_CORE_PAD_MCASP1_FSX_MCASP1_FSX_MUXMODE_PR2_MDIO_DATA_11,
628 PULLUDENABLE_ENABLE,
629 PULLTYPESELECT_PULL_UP, INPUTENABLE_ENABLE, 0xff, WAKEUPENABLE_DISABLE},
631 /*Pin_num,Muxmode,pullud_enable,pull_typeselect,io,slewrate,wakeupmode*/
632 {CTRL_CORE_PAD_MCASP1_AXR1,
633 CTRL_CORE_PAD_MCASP1_AXR1_MCASP1_AXR1_MUXMODE_PR2_MII_MT0_CLK_11,
634 PULLUDENABLE_ENABLE,
635 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
636 WAKEUPENABLE_DISABLE},
638 {CTRL_CORE_PAD_MCASP1_AXR8,
639 CTRL_CORE_PAD_MCASP1_AXR8_MCASP1_AXR8_MUXMODE_PR2_MII0_TXEN_11,
640 PULLUDENABLE_ENABLE,
641 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
642 WAKEUPENABLE_DISABLE},
644 {CTRL_CORE_PAD_MCASP1_AXR12,
645 CTRL_CORE_PAD_MCASP1_AXR12_MCASP1_AXR12_MUXMODE_PR2_MII0_TXD0_11,
646 PULLUDENABLE_ENABLE,
647 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
648 WAKEUPENABLE_DISABLE},
650 {CTRL_CORE_PAD_MCASP1_AXR11,
651 CTRL_CORE_PAD_MCASP1_AXR11_MCASP1_AXR11_MUXMODE_PR2_MII0_TXD1_11,
652 PULLUDENABLE_ENABLE,
653 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
654 WAKEUPENABLE_DISABLE},
656 {CTRL_CORE_PAD_MCASP1_AXR10,
657 CTRL_CORE_PAD_MCASP1_AXR10_MCASP1_AXR10_MUXMODE_PR2_MII0_TXD2_11,
658 PULLUDENABLE_ENABLE,
659 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
660 WAKEUPENABLE_DISABLE},
662 {CTRL_CORE_PAD_MCASP1_AXR9,
663 CTRL_CORE_PAD_MCASP1_AXR9_MCASP1_AXR9_MUXMODE_PR2_MII0_TXD3_11,
664 PULLUDENABLE_ENABLE,
665 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
666 WAKEUPENABLE_DISABLE},
668 {CTRL_CORE_PAD_MCASP1_AXR13,
669 CTRL_CORE_PAD_MCASP1_AXR13_MCASP1_AXR13_MUXMODE_PR2_MII_MR0_CLK_11,
670 PULLUDENABLE_ENABLE,
671 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
672 WAKEUPENABLE_DISABLE},
674 {CTRL_CORE_PAD_MCASP1_AXR14,
675 CTRL_CORE_PAD_MCASP1_AXR14_MCASP1_AXR14_MUXMODE_PR2_MII0_RXDV_11,
676 PULLUDENABLE_ENABLE,
677 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
678 WAKEUPENABLE_DISABLE},
680 {CTRL_CORE_PAD_MCASP1_AXR0,
681 CTRL_CORE_PAD_MCASP1_AXR0_MCASP1_AXR0_MUXMODE_PR2_MII0_RXER_11,
682 PULLUDENABLE_ENABLE,
683 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
684 WAKEUPENABLE_DISABLE},
686 {CTRL_CORE_PAD_MCASP2_AXR2,
687 CTRL_CORE_PAD_MCASP2_AXR2_MCASP2_AXR2_MUXMODE_PR2_MII0_RXD0_11,
688 PULLUDENABLE_ENABLE,
689 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
690 WAKEUPENABLE_DISABLE},
692 {CTRL_CORE_PAD_MCASP2_FSX,
693 CTRL_CORE_PAD_MCASP2_FSX_MCASP2_FSX_MUXMODE_PR2_MII0_RXD1_11,
694 PULLUDENABLE_ENABLE,
695 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
696 WAKEUPENABLE_DISABLE},
698 {CTRL_CORE_PAD_MCASP2_ACLKX,
699 CTRL_CORE_PAD_MCASP2_ACLKX_MCASP2_ACLKX_MUXMODE_PR2_MII0_RXD2_11,
700 PULLUDENABLE_ENABLE,
701 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
702 WAKEUPENABLE_DISABLE},
704 {CTRL_CORE_PAD_MCASP1_AXR15,
705 CTRL_CORE_PAD_MCASP1_AXR15_MCASP1_AXR15_MUXMODE_PR2_MII0_RXD3_11,
706 PULLUDENABLE_ENABLE,
707 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
708 WAKEUPENABLE_DISABLE},
710 {CTRL_CORE_PAD_MCASP3_ACLKX,
711 CTRL_CORE_PAD_MCASP3_ACLKX_MCASP3_ACLKX_MUXMODE_PR2_MII0_CRS_11,
712 PULLUDENABLE_ENABLE,
713 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
714 WAKEUPENABLE_DISABLE},
715 #if 0
716 {CTRL_CORE_PAD_MCASP3_FSX,
717 CTRL_CORE_PAD_MCASP3_FSX_MCASP3_FSX_MUXMODE_PR2_MII0_COL_11,
718 PULLUDENABLE_ENABLE,
719 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
720 WAKEUPENABLE_DISABLE},
721 #else
722 {CTRL_CORE_PAD_MCASP3_FSX,
723 0xff,
724 0xff,
725 0xff, 0xff, 0xff,
726 0xff},
727 #endif
729 #if 0
730 {CTRL_CORE_PAD_MCASP1_AXR3,
731 CTRL_CORE_PAD_MCASP2_AXR3_MCASP2_AXR3_MUXMODE_PR2_MII0_RXLINK_11,
732 PULLUDENABLE_ENABLE,
733 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
734 WAKEUPENABLE_DISABLE}
735 #else
736 {CTRL_CORE_PAD_MCASP1_AXR3,
737 0xff,
738 0xff,
739 0xff, 0xff, 0xff,
740 0xff},
741 #endif
742 };
744 /*configure the pruss2_iep0 pad*/
745 configure_pad(pruss2_iep0_pad_config, sizeof (pruss2_iep0_pad_config) /
746 sizeof (pruss2_iep0_pad_config[0]));
748 /*
749 Port3 - PRUSS2 IEP 1
751 GPIO6_10 - PR2_MII_MT1_CLK
752 GPIO6_11 - PR2_MII1_TXEN
753 MMC3_DAT1 - PR2_MII1_TXD0
754 MMC3_DAT0 - PR2_MII1_TXD1
755 MMC3_CMD - PR2_MII1_TXD2
756 MMC3_CLK - PR2_MII1_TXD3
758 MMC3_DAT2 - PR2_MII_MR1_CLK
759 MMC3_DAT3 - PR2_MII1_RXDV
760 MCASP3_AXR0 -PR2_MII1_RXER
762 MMC3_DAT7 -PR2_MII1_RXD0
763 MMC3_DAT6 - PR2_MII1_RXD1
764 MMC3_DAT5 - PR2_MII1_RXD2
765 MMC3_DAT4 - PR2_MII1_RXD3
767 XREF_CLK1 - PR2_MII1_CRS
768 XREF_CLK0 - PR2_MII1_COL
769 MCASP3_AXR1 - PR2_MII1_RXLINK
771 */
772 pad_config_t pruss2_iep1_pad_config[] = {
774 /*Pin_num,Muxmode,pullud_enable,pull_typeselect,io,slewrate,wakeupmode*/
775 {CTRL_CORE_PAD_GPIO6_10,
776 CTRL_CORE_PAD_GPIO6_10_GPIO6_10_MUXMODE_PR2_MII_MT1_CLK_11,
777 PULLUDENABLE_ENABLE,
778 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
779 WAKEUPENABLE_DISABLE},
781 {CTRL_CORE_PAD_GPIO6_11,
782 CTRL_CORE_PAD_GPIO6_11_GPIO6_11_MUXMODE_PR2_MII1_TXEN_11,
783 PULLUDENABLE_ENABLE,
784 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
785 WAKEUPENABLE_DISABLE},
787 {CTRL_CORE_PAD_MMC3_DAT1,
788 CTRL_CORE_PAD_MMC3_DAT1_MMC3_DAT1_MUXMODE_PR2_MII1_TXD0_11,
789 PULLUDENABLE_ENABLE,
790 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
791 WAKEUPENABLE_DISABLE},
793 {CTRL_CORE_PAD_MMC3_DAT0,
794 CTRL_CORE_PAD_MMC3_DAT0_MMC3_DAT0_MUXMODE_PR2_MII1_TXD1_11,
795 PULLUDENABLE_ENABLE,
796 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
797 WAKEUPENABLE_DISABLE},
799 {CTRL_CORE_PAD_MMC3_CMD,
800 CTRL_CORE_PAD_MMC3_CMD_MMC3_CMD_MUXMODE_PR2_MII1_TXD2_11,
801 PULLUDENABLE_ENABLE,
802 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
803 WAKEUPENABLE_DISABLE},
805 {CTRL_CORE_PAD_MMC3_CLK,
806 CTRL_CORE_PAD_MMC3_CLK_MMC3_CLK_MUXMODE_PR2_MII1_TXD3_11,
807 PULLUDENABLE_ENABLE,
808 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_DISABLE, 0xff,
809 WAKEUPENABLE_DISABLE},
811 {CTRL_CORE_PAD_MMC3_DAT2,
812 CTRL_CORE_PAD_MMC3_DAT2_MMC3_DAT2_MUXMODE_PR2_MII_MR1_CLK_11,
813 PULLUDENABLE_ENABLE,
814 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
815 WAKEUPENABLE_DISABLE},
817 {CTRL_CORE_PAD_MMC3_DAT3,
818 CTRL_CORE_PAD_MMC3_DAT3_MMC3_DAT3_MUXMODE_PR2_MII1_RXDV_11,
819 PULLUDENABLE_ENABLE,
820 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
821 WAKEUPENABLE_DISABLE},
823 {CTRL_CORE_PAD_MCASP3_AXR0,
824 CTRL_CORE_PAD_MCASP3_AXR0_MCASP3_AXR0_MUXMODE_PR2_MII1_RXER_11,
825 PULLUDENABLE_ENABLE,
826 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
827 WAKEUPENABLE_DISABLE},
829 {CTRL_CORE_PAD_MMC3_DAT7,
830 CTRL_CORE_PAD_MMC3_DAT7_MMC3_DAT7_MUXMODE_PR2_MII1_RXD0_11,
831 PULLUDENABLE_ENABLE,
832 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
833 WAKEUPENABLE_DISABLE},
835 {CTRL_CORE_PAD_MMC3_DAT6,
836 CTRL_CORE_PAD_MMC3_DAT6_MMC3_DAT6_MUXMODE_PR2_MII1_RXD1_11,
837 PULLUDENABLE_ENABLE,
838 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
839 WAKEUPENABLE_DISABLE},
841 {CTRL_CORE_PAD_MMC3_DAT5,
842 CTRL_CORE_PAD_MMC3_DAT5_MMC3_DAT5_MUXMODE_PR2_MII1_RXD2_11,
843 PULLUDENABLE_ENABLE,
844 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
845 WAKEUPENABLE_DISABLE},
847 {CTRL_CORE_PAD_MMC3_DAT4,
848 CTRL_CORE_PAD_MMC3_DAT4_MMC3_DAT4_MUXMODE_PR2_MII1_RXD3_11,
849 PULLUDENABLE_ENABLE,
850 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
851 WAKEUPENABLE_DISABLE},
853 {CTRL_CORE_PAD_XREF_CLK1,
854 CTRL_CORE_PAD_XREF_CLK1_XREF_CLK1_MUXMODE_PR2_MII1_CRS_11,
855 PULLUDENABLE_ENABLE,
856 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
857 WAKEUPENABLE_DISABLE},
858 #if 0
859 {CTRL_CORE_PAD_XREF_CLK0,
860 CTRL_CORE_PAD_XREF_CLK0_XREF_CLK0_MUXMODE_PR2_MII1_COL_11,
861 PULLUDENABLE_ENABLE,
862 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
863 WAKEUPENABLE_DISABLE},
864 #else
865 {CTRL_CORE_PAD_XREF_CLK0,
866 0xff,
867 0xff,
868 0xff, 0xff, 0xff,
869 0xff},
870 #endif
872 #if 0
873 {CTRL_CORE_PAD_MCASP3_AXR1,
874 CTRL_CORE_PAD_MCASP3_AXR1_MCASP3_AXR1_MUXMODE_PR2_MII1_RXLINK_11,
875 PULLUDENABLE_ENABLE,
876 PULLTYPESELECT_PULL_DOWN, INPUTENABLE_ENABLE, 0xff,
877 WAKEUPENABLE_DISABLE}
878 #else
879 {CTRL_CORE_PAD_MCASP3_AXR1,
880 0xff,
881 0xff,
882 0xff, 0xff, 0xff,
883 0xff},
884 #endif
886 };
888 /*configure the pruss2_iep0 pad*/
889 configure_pad(pruss2_iep1_pad_config, sizeof (pruss2_iep1_pad_config) /
890 sizeof (pruss2_iep1_pad_config[0]));
892 }
894 }
896 void pruss_iep_Initialization(uint8_t prussn)
897 {
898 uint32_t pruss_base=0;
900 if(prussn==1)
901 pruss_base = CSL_MPU_PRUSS1_U_CFG_REGS;
902 else
903 pruss_base = CSL_MPU_PRUSS2_U_CFG_REGS;
905 //perform all the pin muxing
906 pruss_iep_PinMux(prussn);
908 //Enable the PRUSS clock
909 if(prussn==1)
910 {
911 HWREG(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER2_PRUSS1_CLKCTRL) = 0;
912 }
913 else
914 {
915 HWREG(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER2_PRUSS2_CLKCTRL) = 0;
916 }
918 Delay(50);
920 if(prussn==1)
921 {
922 HWREG(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER2_PRUSS1_CLKCTRL) = 2;
923 while(0 != (HWREG(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER2_PRUSS1_CLKCTRL) & 0x00030000));
924 }
925 else
926 {
927 HWREG(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER2_PRUSS2_CLKCTRL) = 2;
928 while(0 != (HWREG(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER2_PRUSS2_CLKCTRL) & 0x00030000));
929 }
931 while(0x6100 != ((HWREG(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER2_CLKSTCTRL))&0x6100)); //ICSS_CLK, ICSS_IEP_CLK
935 HWREG(pruss_base + 0x04)=0x06; //NO_STANDBY
936 Delay(50);
938 }
940 void pruss_iep_MemFill(uint32_t StartAddress, uint32_t Length , uint16_t Pattern)
941 {
942 uint32_t tempCount = 0;
943 for(tempCount = 0; tempCount < (Length / 4 ) ; tempCount++ )
944 {
945 /*loading the pattern into the memory*/
946 HWREG(StartAddress + (tempCount*4)) = Pattern;
947 }
948 }
950 /*
951 * this can be changed to use the MDIO API
952 */
953 void pruss_iep_MDIOInitialization(uint8_t prussn)
954 {
955 uint32_t pruss_base = 0;
957 if(prussn==1)
958 {
959 pruss_base = icss_EmacBaseAddrCfgParams[prussn-1].prussMiiMdioRegs + 0x04;
960 }
961 else
962 {
963 pruss_base = icss_EmacBaseAddrCfgParams[prussn-1].prussMiiMdioRegs + 0x04;
964 }
966 /* Initialize the MDIO pin */
967 HWREG(pruss_base) = 0x4000009F;//increase speed
968 /*200/(0x9F+1) = 1.25 MHz*/
969 Delay(50);
970 }
972 void PhyIntConfig(int numPorts)
973 {
974 int i =0;
975 int startPort=0;
977 if(numPorts==2)
978 {
979 startPort = 2;
980 numPorts+=2;
981 }
983 for(i=startPort;i<numPorts;i++)
984 {
985 /* Do GPIO pin mux */
986 HWREG(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + PhyIntInfo[i].pinMux) = (0x20000 | 0x0E);
988 GPIOModuleEnable(PhyIntInfo[i].baseAddr,1);
989 GPIOSetDirMode(PhyIntInfo[i].baseAddr, PhyIntInfo[i].pin, GPIO_DIRECTION_INPUT);
990 }
992 }
994 void ManualPhyReset(int numPorts)
995 {
996 int i =0;
997 int startPort=0;
999 if(numPorts==2)
1000 {
1001 startPort = 2;
1002 numPorts+=2;
1003 }
1005 for(i=startPort;i<numPorts;i++)
1006 {
1007 /* Do GPIO pin mux */
1008 HWREG(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS + PhyResetInfo[i].pinMux) = (0x20000 | 0x0E);
1010 //GPIOModuleReset(info.baseAddr);
1011 GPIOModuleEnable(PhyResetInfo[i].baseAddr,1);
1012 GPIOSetDirMode(PhyResetInfo[i].baseAddr, PhyResetInfo[i].pin, GPIO_DIRECTION_OUTPUT);
1015 GPIOPinWrite(PhyResetInfo[i].baseAddr, PhyResetInfo[i].pin, GPIO_PIN_LOW);
1016 //Delay(100000);
1017 Delay(1000);
1018 GPIOPinWrite(PhyResetInfo[i].baseAddr, PhyResetInfo[i].pin, GPIO_PIN_HIGH);
1019 //Delay(100000);
1020 Delay(1000);
1021 }
1023 }
1025 void ICSS_EmacRxPktCallback(ICSS_EmacHandle ICSS_EmacSubSysHandle)
1026 {
1027 int8_t port_number;
1028 int8_t queue_number;
1029 int32_t morePkts;
1030 short pLength;
1031 ICSS_EmacRxArgument rxArg;
1032 memset(&rxArg, 0, sizeof(ICSS_EmacRxArgument));
1033 packetRcvd_port0 = 1;
1034 pLength = ICSS_EmacRxPktInfo(ICSS_EmacSubSysHandle,&port_number, &queue_number);
1036 rxArg.icssEmacHandle = ICSS_EmacSubSysHandle;
1037 rxArg.destAddress = (uint32_t)(&packet_array[0]);
1038 rxArg.queueNumber = queue_number;
1039 rxArg.port = port_number;
1040 rxArg.more = morePkts;
1042 if(pLength > 0)
1043 {
1044 pktReceived++;
1045 ICSS_EmacRxPktGet(&rxArg, NULL);
1046 }
1047 //ICSS_EmacClearRxIrq(ICSS_EmacSubSysHandle);
1048 if((((ICSS_EmacObject*)ICSS_EmacSubSysHandle->object)->emacInitcfg)->portMask == ICSS_EMAC_MODE_MAC2)
1049 HW_WR_FIELD32(((((ICSS_EmacHwAttrs*)ICSS_EmacSubSysHandle->hwAttrs)->emacBaseAddrCfg)->prussIntcRegs + CSL_ICSSINTC_SECR0),
1050 CSL_ICSSINTC_SECR0_ENA_STATUS_31_0, 1 << 21);
1051 else
1052 HW_WR_FIELD32(((((ICSS_EmacHwAttrs*)ICSS_EmacSubSysHandle->hwAttrs)->emacBaseAddrCfg)->prussIntcRegs + CSL_ICSSINTC_SECR0),
1053 CSL_ICSSINTC_SECR0_ENA_STATUS_31_0, 1 << 20);
1054 }
1057 uint8_t ICSSEmacDRVInit(ICSS_EmacHandle handle, uint8_t instance)
1058 {
1059 uint8_t retVal = -1;
1061 /* LLD attributes callocs */
1062 handle->object = (ICSS_EmacObject*)calloc(1, sizeof(ICSS_EmacObject));
1063 handle->hwAttrs= (ICSS_EmacHwAttrs*)calloc(1, sizeof(ICSS_EmacHwAttrs));
1065 /* Callback callocs */
1066 ICSS_EmacCallBackObject* callBackObj = (ICSS_EmacCallBackObject*)calloc(1, sizeof(ICSS_EmacCallBackObject));
1068 callBackObj->learningExCallBack=(ICSS_EmacCallBackConfig*)calloc(1, sizeof(ICSS_EmacCallBackConfig));
1069 callBackObj->rxRTCallBack=(ICSS_EmacCallBackConfig*)calloc(1, sizeof(ICSS_EmacCallBackConfig));
1070 callBackObj->rxCallBack=(ICSS_EmacCallBackConfig*)malloc(sizeof(ICSS_EmacCallBackConfig));
1071 callBackObj->txCallBack=(ICSS_EmacCallBackConfig*)malloc(sizeof(ICSS_EmacCallBackConfig));
1072 ((ICSS_EmacObject*)handle->object)->callBackHandle = callBackObj;
1074 /*Allocate memory for learning*/
1075 ((ICSS_EmacObject*)handle->object)->macTablePtr = (HashTable_t*)calloc(1, NUM_PORTS * sizeof(HashTable_t));
1077 /*Allocate memory for PRU Statistics*/
1078 ((ICSS_EmacObject*)handle->object)->pruStat = (ICSS_EmacPruStatistics_t*)calloc(1, NUM_PORTS * sizeof(ICSS_EmacPruStatistics_t));
1080 /*Allocate memory for Host Statistics*/
1081 ((ICSS_EmacObject*)handle->object)->hostStat = (ICSS_EmacHostStatistics_t*)calloc(1, NUM_PORTS * sizeof(ICSS_EmacHostStatistics_t));
1083 /*Allocate memory for Storm Prevention*/
1084 ((ICSS_EmacObject*)handle->object)->stormPrevPtr = (stormPrevention_t*)calloc(1, NUM_PORTS * sizeof(stormPrevention_t));
1086 /* Base address initialization */
1087 ((ICSS_EmacHwAttrs*)handle->hwAttrs)->emacBaseAddrCfg =
1088 (ICSS_EmacBaseAddressHandle_T)calloc(1, sizeof(ICSS_EmacBaseAddrCfgParams));
1090 ICSS_EmacBaseAddressHandle_T emacBaseAddr = ((ICSS_EmacHwAttrs*)handle->hwAttrs)->emacBaseAddrCfg;
1093 if(instance == 2)
1094 {
1095 emacBaseAddr->dataRam0BaseAddr = CSL_MPU_PRUSS2_U_DATA_RAM0_8KB_REGS;
1096 emacBaseAddr->dataRam1BaseAddr = CSL_MPU_PRUSS2_U_DATA_RAM1_8KB_REGS;
1097 emacBaseAddr->l3OcmcBaseAddr = CSL_MPU_OCMC_RAM1_REGS;
1098 emacBaseAddr->prussCfgRegs = CSL_MPU_PRUSS2_U_CFG_REGS;
1099 emacBaseAddr->prussIepRegs = CSL_MPU_PRUSS2_U_IEP_REGS;
1100 emacBaseAddr->prussIntcRegs = CSL_MPU_PRUSS2_U_INTC_REGS;
1101 emacBaseAddr->prussMiiMdioRegs = CSL_MPU_PRUSS2_U_MII_MDIO_REGS;
1102 emacBaseAddr->prussMiiRtCfgRegsBaseAddr = CSL_MPU_PRUSS2_U_MII_RT_CFG_REGS;
1103 emacBaseAddr->prussPru0CtrlRegs = CSL_MPU_PRUSS2_U_PRU0_CTRL_REGS;
1104 emacBaseAddr->prussPru1CtrlRegs = CSL_MPU_PRUSS2_U_PRU1_CTRL_REGS;
1105 emacBaseAddr->sharedDataRamBaseAddr = CSL_MPU_PRUSS2_U_DATA_RAM_32KB_REGS;
1106 retVal = 0;
1107 }
1108 return retVal;
1109 }
1111 void MDIO_enableLinkInterrupt(uint32_t mdioBaseAddress,uint32_t phyInst,uint32_t phyNum,uint8_t linkSel)
1112 {
1113 uint32_t PhySel;
1115 PhySel=phyNum;
1116 PhySel |= 0x40;
1117 if(MDIO_LINKSEL_ENABLE == linkSel)
1118 PhySel |= 0x80;
1120 HWREG(mdioBaseAddress + CSL_MDIO_USER_PHY_SEL_REG(0) + (phyInst*8)) = PhySel;
1121 }
1123 uint32_t EMACOpen(ICSS_EmacHandle icssEmacHandle)
1124 {
1125 int32_t i;
1126 uint32_t numPorts=0;
1127 uint32_t phyNum;
1128 uint32_t phyinst;
1129 if(ICSS_EMAC_MODE_SWITCH == (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->portMask)
1130 numPorts = 2;
1131 else
1132 numPorts = 1;
1133 /*No need of MDIO init for the second instance*/
1134 if(ICSS_EMAC_MODE_MAC2 != (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->portMask)
1135 CSL_MDIO_init((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs,
1136 SWITCH_DEFAULT_MDIOCLOCKFREQ, SWITCH_DEFAULT_MDIOBUSFREQ);
1137 /* Open all ports */
1138 for(i=0;i<numPorts; i++)
1139 {
1140 //ICSSMacOpen(i,icssEmacHandle);
1141 phyNum = (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->phyAddr[i];
1142 phyinst = (i + phyCount);
1143 phyCount++;
1144 MDIO_enableLinkInterrupt((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs,phyinst,phyNum,
1145 MDIO_LINKSEL_DISABLE);
1147 }/* end of for loop over PORTS */
1149 return 0;
1150 }
1152 void AM57x_setup(void)
1153 {
1154 int numPorts= 4, fixTemp=0;
1156 if(numPorts==4)
1157 {
1158 //GPIO_PRU1_ETH0_RESETn
1159 PhyResetInfo[0].instance=5; //MCASP1_AXR4 - GPIO5_6
1160 PhyResetInfo[0].pin=6;
1161 PhyResetInfo[0].pinMux=CSL_CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR4;
1162 PhyResetInfo[0].baseAddr=CSL_MPU_GPIO5_REGS;
1164 //GPIO_PRU1_ETH1_RESETn
1165 PhyResetInfo[1].instance=5; //MCASP1_AXR5 - GPIO5_7
1166 PhyResetInfo[1].pin=7;
1167 PhyResetInfo[1].pinMux=CSL_CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR5;
1168 PhyResetInfo[1].baseAddr=CSL_MPU_GPIO5_REGS;
1170 //PRU1_ETH0_INTn
1171 PhyIntInfo[0].instance=3; //VIN2A_CLK0 - GPIO3_28 - Input
1172 PhyIntInfo[0].pin=28;
1173 PhyIntInfo[0].pinMux=CSL_CONTROL_CORE_PAD_IO_PAD_VIN2A_CLK0;
1174 PhyIntInfo[0].baseAddr=CSL_MPU_GPIO3_REGS;
1176 //PRU1_ETH1_INTn
1177 PhyIntInfo[1].instance=3; //VIN2A_DE0- GPIO3_29 - Input
1178 PhyIntInfo[1].pin=29;
1179 PhyIntInfo[1].pinMux=CSL_CONTROL_CORE_PAD_IO_PAD_VIN2A_DE0;
1180 PhyIntInfo[1].baseAddr=CSL_MPU_GPIO3_REGS;
1181 }
1183 //GPIO_PRU2_ETH0_RESETn
1184 PhyResetInfo[2].instance=5; //MCASP1_AXR6 - GPIO5_8
1185 PhyResetInfo[2].pin=8;
1186 PhyResetInfo[2].pinMux=CSL_CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR6;
1187 PhyResetInfo[2].baseAddr=CSL_MPU_GPIO5_REGS;
1189 //GPIO_PRU2_ETH1_RESETn
1190 PhyResetInfo[3].instance=5; //MCASP1_AXR7 - GPIO5_9
1191 PhyResetInfo[3].pin=9;
1192 PhyResetInfo[3].pinMux=CSL_CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR7;
1193 PhyResetInfo[3].baseAddr=CSL_MPU_GPIO5_REGS;
1195 //PRU2_ETH0_INTn
1196 PhyIntInfo[2].instance=3; //VIN2A_FLD0- GPIO3_30 - Input
1197 PhyIntInfo[2].pin=30;
1198 PhyIntInfo[2].pinMux=CSL_CONTROL_CORE_PAD_IO_PAD_VIN2A_FLD0;
1199 PhyIntInfo[2].baseAddr=CSL_MPU_GPIO3_REGS;
1201 //PRU2_ETH1_INTn
1202 PhyIntInfo[3].instance=3; //VIN2A_HSYNC0- GPIO3_31 - Input
1203 PhyIntInfo[3].pin=31;
1204 PhyIntInfo[3].pinMux=CSL_CONTROL_CORE_PAD_IO_PAD_VIN2A_HSYNC0;
1205 PhyIntInfo[3].baseAddr=CSL_MPU_GPIO3_REGS;
1207 for(fixTemp=0;fixTemp<2;fixTemp++) //Temporary fix to run the initialisation twice to fix the second port failure
1208 {
1209 //reset the phys
1210 ManualPhyReset(numPorts);
1212 /*PHY Interrupt lines are configured as GPIO Input in order to avoid any
1213 spurious power down signal to TLK105L*/
1214 PhyIntConfig(numPorts);
1216 //call the ICSS PRU init function
1217 if(numPorts==4)
1218 pruss_iep_Initialization(1);
1220 pruss_iep_Initialization(2);
1222 *(unsigned int*)(0x4A003710) =(unsigned int)(0x000c000B);
1224 *(unsigned int*)(0x4A003730) =(unsigned int)(0x000c000B);
1226 //Init the MDIO
1227 if(numPorts==4)
1228 pruss_iep_MDIOInitialization(1);
1230 pruss_iep_MDIOInitialization(2);
1232 Delay(2000);
1233 }
1234 }
1237 void IcssEmacIntrInit(ICSS_EmacHandle icssEmacHandle)
1238 {
1239 /* Rx Packet Interrupt , HOST2 is always Rx Packet Interrupt*/
1240 CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_150, CSL_XBAR_PRUSS2_IRQ_HOST2);
1242 /* Do the interrupt related configurations */
1243 gIcssEmacIntrParams.triggerType = CSL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL;
1244 gIcssEmacIntrParams.priority = 0x20U;
1246 /*
1247 * Assign the ISR to the function pointer to invoke when the
1248 * interrupt is raised.
1249 */
1250 gIcssEmacIntrParams.pFnIntrHandler = (void*)&ICSS_EmacRxPktCallback;
1251 gIcssEmacIntrParams.pUserParam = icssEmacHandle;
1254 /* Configure the interrupt Controller 182 is CSL_XBAR_INST_MPU_IRQ_150 + 32*/
1255 CSL_armGicConfigIntr(&gCpuIntrf, 182U, &gIcssEmacIntrParams);
1258 /* Link Interrupt , HOST 8 is always link interrupt*/
1259 CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_120, CSL_XBAR_PRUSS2_IRQ_HOST8);
1260 /* Do the interrupt related configurations */
1261 gIcssEmacIntrParamsLink.triggerType = CSL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL;
1262 gIcssEmacIntrParamsLink.priority = 0x20U;
1264 /*
1265 * Assign the ISR to the function pointer to invoke when the
1266 * interrupt is raised.
1267 */
1268 gIcssEmacIntrParamsLink.pFnIntrHandler = (void*)&ICSS_EmacLinkISR;
1269 gIcssEmacIntrParamsLink.pUserParam = icssEmacHandle;
1271 /* Configure the interrupt Controller 152 is CSL_XBAR_INST_MPU_IRQ_120 + 32*/
1272 CSL_armGicConfigIntr(&gCpuIntrf,152, &gIcssEmacIntrParamsLink);
1273 }
1275 int icss_emacMain(void)
1276 {
1277 uint8_t firmwareLoad_done = FALSE;
1278 uint8_t count=0;
1279 int ret;
1280 uint32_t pgVersion;
1281 ICSS_EmacTxArgument txArg;
1282 memset(&txArg, 0, sizeof(ICSS_EmacTxArgument));
1284 pgVersion = (HW_RD_REG32(CSL_MPU_CTRL_MODULE_WKUP_CORE_REGISTERS_REGS + CTRL_WKUP_ID_CODE) & 0xf0000000) >> 28;
1286 pruIcssHandle = PRUICSS_create(pruss_config,(int) prussIcssInstance);
1287 AM57x_setup();
1289 /*Port I initializations*/
1290 emachandle = (ICSS_EmacHandle)calloc(1, sizeof(ICSS_EmacConfig));
1292 ICSS_EmacInitConfig* switchEmacCfg;
1293 switchEmacCfg = (ICSS_EmacInitConfig*)calloc(1,sizeof(ICSS_EmacInitConfig));
1294 switchEmacCfg->phyAddr[0]=0;
1295 switchEmacCfg->portMask = ICSS_EMAC_MODE_MAC1;
1296 switchEmacCfg->ethPrioQueue = ICSS_EMAC_QUEUE1;
1300 switchEmacCfg->halfDuplexEnable = 1;
1301 switchEmacCfg->enableIntrPacing = ICSS_EMAC_ENABLE_PACING;
1302 switchEmacCfg->ICSS_EmacIntrPacingMode = ICSS_EMAC_INTR_PACING_MODE1;
1303 switchEmacCfg->pacingThreshold = 100;
1304 switchEmacCfg->learningEn = 0;
1305 SOCCtrlGetPortMacAddr(0,lclMac);
1306 switchEmacCfg->macId = lclMac;
1308 ICSSEmacDRVInit(emachandle, 2); // ICSS_M instance 0
1310 ((ICSS_EmacObject*)emachandle->object)->pruIcssHandle = pruIcssHandle;
1311 ((ICSS_EmacObject*)emachandle->object)->emacInitcfg = switchEmacCfg;
1314 PRUICSS_IntcInitData pruss_intc_initdata = PRUSS_INTC_INITDATA;
1315 ICSS_EmacInit(emachandle,&pruss_intc_initdata,ICSS_EMAC_MODE_MAC1);
1319 PRUICSS_pinMuxConfig(pruIcssHandle, 0x0); // PRUSS pinmuxing
1320 IcssEmacIntrInit(emachandle);
1321 EMACOpen(emachandle);
1323 /* Same flow as taskPruss */
1324 PRUICSS_pruDisable(pruIcssHandle, ICSS_EMAC_PORT_1-1);
1325 PRUICSS_pruDisable(pruIcssHandle, ICSS_EMAC_PORT_2-1);
1328 #ifdef SOC_AM572x
1329 if (pgVersion >= 2)
1330 {
1331 if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(0) ,0,
1332 (uint32_t *) PRU0_FIRMWARE_NAME,
1333 sizeof(PRU0_FIRMWARE_NAME)))
1334 {
1335 if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(1) ,0,
1336 (uint32_t *) PRU1_FIRMWARE_NAME,
1337 sizeof(PRU1_FIRMWARE_NAME)))
1338 {
1339 firmwareLoad_done = TRUE;
1340 }
1341 }
1342 }
1343 else
1344 {
1345 if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(0) ,0,
1346 (uint32_t *) PRU0_FIRMWARE_V1_0_NAME,
1347 sizeof(PRU0_FIRMWARE_V1_0_NAME)))
1348 {
1349 if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(1) ,0,
1350 (uint32_t *) PRU1_FIRMWARE_V1_1_NAME,
1351 sizeof(PRU1_FIRMWARE_V1_1_NAME)))
1352 {
1353 firmwareLoad_done = TRUE;
1354 }
1355 }
1356 }
1357 #else
1358 if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(0) ,0,
1359 (uint32_t *) PRU0_FIRMWARE_NAME,
1360 sizeof(PRU0_FIRMWARE_NAME)))
1361 {
1362 if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(1) ,0,
1363 (uint32_t *) PRU1_FIRMWARE_NAME,
1364 sizeof(PRU1_FIRMWARE_NAME)))
1365 {
1366 firmwareLoad_done = TRUE;
1367 }
1368 }
1369 #endif
1371 if( firmwareLoad_done)
1372 {
1373 PRUICSS_pruEnable(pruIcssHandle, ICSS_EMAC_PORT_1-1);
1374 PRUICSS_pruEnable(pruIcssHandle, ICSS_EMAC_PORT_2-1);
1375 }
1377 /* wait for link to come up */
1378 while (!((ICSS_EmacObject*)emachandle->object)->linkStatus[0])
1379 {
1380 UART_printf("icss_emacMain: LINK IS DOWN, pluggin loopback cable\n");
1381 Delay(1000);
1382 }
1384 UART_printf("icss_emacMain: LINK IS UP\n");
1386 packetRcvd_port0 = 1;
1387 /* send the packet */
1388 for (count=0;count < PKT_TX_COUNT;count++)
1389 {
1390 {
1391 if(packetRcvd_port0 )
1392 {
1393 txArg.icssEmacHandle = emachandle;
1394 txArg.srcAddress = &test_pkt[0];
1395 txArg.portNumber = 1;
1396 txArg.queuePriority = 3;
1397 txArg.lengthOfPacket = TEST_PKT_SIZE;
1398 packetRcvd_port0 = 0;
1399 ret = ICSS_EmacTxPacket(&txArg, NULL);
1400 if (ret != 0) {
1401 UART_printf("Error sending packet\n");
1402 return (1);
1403 }
1405 while(!packetRcvd_port0)
1406 {
1407 Delay(100);
1408 }
1409 if (!(memcmp(&packet_array[0], &test_pkt[0],TEST_PKT_SIZE)))
1410 {
1411 memset(&packet_array[0], 0, TEST_PKT_SIZE);
1412 UART_printf("received pkt: %d\n", totalPktRcvd);
1413 totalPktRcvd++;
1414 }
1415 else
1416 {
1417 UART_printf("Unit Test Failure, packet mismatch occured\n");
1418 return (1);
1419 }
1420 }
1421 }
1422 }
1424 if (totalPktRcvd == PKT_TX_COUNT)
1425 {
1426 UART_printf("All tests have passed\n");
1427 }
1429 return(0);
1430 }
1432 /**
1433 * \brief This function does two operations:\n
1434 * 1> Copies an array which contains vector table values to the
1435 * processor's vector table space.\n
1436 * 2> Then it calls the main() function.\n
1437 *
1438 * \param None.
1439 *
1440 * \retval None.
1441 *
1442 * \note This function is the first function that needs to be called in a
1443 * system. This should be set as the entry point in the linker script
1444 * file if the ELF executable is to loaded via a debugger on the
1445 * target. This function never returns, but gives control to the
1446 * application entry point.
1447 **/
1448 int main(void)
1449 {
1450 Board_initCfg boardCfg;
1451 #ifdef PDK_RAW_BOOT
1452 boardCfg = BOARD_INIT_MODULE_CLOCK |
1453 BOARD_INIT_PINMUX_CONFIG |
1454 BOARD_INIT_UART_STDIO;
1455 #else
1456 boardCfg = BOARD_INIT_MODULE_CLOCK |
1457 BOARD_INIT_PINMUX_CONFIG |
1458 BOARD_INIT_UART_STDIO;
1459 #endif
1460 Board_init(boardCfg);
1462 /* Copy the vector table to desired location. */
1463 CopyVectorTable();
1465 /* Configure system */
1466 systemInit();
1468 /* Calling the main */
1469 return icss_emacMain();
1470 }