[processor-sdk/performance-audio-sr.git] / pdk_k2g_1_0_1_0_eng / packages / ti / board / src / evmK2H / evmK2H_ddr.c
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32 *****************************************************************************/
34 #include <ti/csl/csl_bootcfgAux.h>
35 #include <ti/csl/cslr_device.h>
36 #include <ti/csl/csl_xmcAux.h>
37 #include <ti/csl/csl_emif4f.h>
38 #include <ti/csl/hw_types.h>
40 #include "board_internal.h"
42 /** \brief DDR configuration dealy in usec */
43 #define DDR_CFG_DELAY 200
45 /** \brief DDR PHY register offset */
46 #define DDRPHY_PIR_OFFSET 0x04
47 #define DDRPHY_PGCR0_OFFSET 0x08
48 #define DDRPHY_PGCR1_OFFSET 0x0C
49 #define DDRPHY_PGSR0_OFFSET 0x10
50 #define DDRPHY_PGSR1_OFFSET 0x14
51 #define DDRPHY_PLLCR_OFFSET 0x18
52 #define DDRPHY_PTR0_OFFSET 0x1C
53 #define DDRPHY_PTR1_OFFSET 0x20
54 #define DDRPHY_PTR2_OFFSET 0x24
55 #define DDRPHY_PTR3_OFFSET 0x28
56 #define DDRPHY_PTR4_OFFSET 0x2C
57 #define DDRPHY_DCR_OFFSET 0x44
58 #define DDRPHY_DTPR0_OFFSET 0x48
59 #define DDRPHY_DTPR1_OFFSET 0x4C
60 #define DDRPHY_DTPR2_OFFSET 0x50
61 #define DDRPHY_MR0_OFFSET 0x54
62 #define DDRPHY_MR1_OFFSET 0x58
63 #define DDRPHY_MR2_OFFSET 0x5C
64 #define DDRPHY_DTCR_OFFSET 0x68
65 #define DDRPHY_PGCR2_OFFSET 0x8C
66 #define DDRPHY_ZQ0CR1_OFFSET 0x184
67 #define DDRPHY_ZQ1CR1_OFFSET 0x194
68 #define DDRPHY_ZQ2CR1_OFFSET 0x1A4
69 #define DDRPHY_ZQ3CR1_OFFSET 0x1B4
70 #define DDRPHY_DATX8_8_OFFSET 0x3C0
72 #define IODDRM_MASK 0x00000180
73 #define ZCKSEL_MASK 0x01800000
74 #define CL_MASK 0x00000072
75 #define WR_MASK 0x00000E00
76 #define BL_MASK 0x00000003
77 #define RRMODE_MASK 0x00040000
78 #define UDIMM_MASK 0x20000000
79 #define BYTEMASK_MASK 0x0000FC00
80 #define MPRDQ_MASK 0x00000080
81 #define PDQ_MASK 0x00000070
82 #define NOSRA_MASK 0x08000000
83 #define ECC_MASK 0x00000001
86 /**
87 * \brief This structure defines the various Configuration Parameters for
88 * DDR3 PHY.
89 */
90 typedef struct ddr3_phy_config {
91 uint32_t pllcr;
92 uint32_t pgcr1_mask;
93 uint32_t pgcr1_val;
94 uint32_t ptr0;
95 uint32_t ptr1;
96 uint32_t ptr2;
97 uint32_t ptr3;
98 uint32_t ptr4;
99 uint32_t dcr_mask;
100 uint32_t dcr_val;
101 uint32_t dtpr0;
102 uint32_t dtpr1;
103 uint32_t dtpr2;
104 uint32_t mr0;
105 uint32_t mr1;
106 uint32_t mr2;
107 uint32_t dtcr;
108 uint32_t pgcr2;
109 uint32_t zq0cr1;
110 uint32_t zq1cr1;
111 uint32_t zq2cr1;
112 uint32_t pir_v1;
113 uint32_t pir_v2;
114 } ddr3_phy_config;
116 /**
117 * \brief This structure defines the various Configuration Parameters for
118 * EMIF4 controller.
119 */
120 typedef struct ddr3_emif_config {
121 uint32_t sdcfg;
122 uint32_t sdtim1;
123 uint32_t sdtim2;
124 uint32_t sdtim3;
125 uint32_t sdtim4;
126 uint32_t zqcfg;
127 uint32_t sdrfc;
128 } ddr3_emif_config;
130 static const ddr3_emif_config ddr3_1333_32 = {
131 0x62009C62,
132 0x125C8044,
133 0x00001D29,
134 0x32CDFF43,
135 0x543F0ADF,
136 0x70073200,
137 0x00001457,
138 };
140 static const ddr3_phy_config ddr3phy_1333_32 = {
141 0x0005C000,
142 (IODDRM_MASK | ZCKSEL_MASK | ZCKSEL_MASK),
143 ((1 << 2) | (1 << 7) | (1 << 23)),
144 0x42C21590,
145 0xD05612C0,
146 0, /* not set in gel */
147 0x0B4515C2,
148 0x0A6E08B4,
149 (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK | UDIMM_MASK),
150 ((1 << 10) | (1 << 27) | (1 << 29)),
151 0x8558AA55,
152 0x12857280,
153 0x5002C200,
154 0x00001A60,
155 0x00000006,
156 0x00000010,
157 0x710035C7,
158 0x00F065B8,
159 0x0000005D,
160 0x0000005B,
161 0x0000005B,
162 0x00000033,
163 0x0000FF81,
164 };
166 static const ddr3_emif_config ddr3_1600_64 = {
167 0x6200CE62,
168 0x16709C55,
169 0x00001D4A,
170 0x435DFF54,
171 0x553F0CFF,
172 0xF0073200,
173 0x00001869,
174 };
176 static const ddr3_phy_config ddr3phy_1600_64 = {
177 0x1C000,
178 (IODDRM_MASK | ZCKSEL_MASK | ZCKSEL_MASK),
179 ((1 << 2) | (1 << 7) | (1 << 23)),
180 0x42C21590,
181 0xD05612C0,
182 0, /* not set in gel */
183 0x0D861A80,
184 0x0C827100,
185 (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
186 ((1 << 10) | (1 << 27)),
187 0xA19DBB66,
188 0x12868300,
189 0x50035200,
190 0x00001C70,
191 0x00000006,
192 0x00000018,
193 0x710035C7,
194 0x00F07A12,
195 0x0000005D,
196 0x0000005B,
197 0x0000005B,
198 0x00000033,
199 0x0000FF81,
200 };
202 extern void BOARD_delay(uint32_t usecs);
204 static void xmc_add_emif_cfg_region()
205 {
206 /* mapping for ddr emif registers XMPAX*2 */
207 CSL_XMC_XMPAXL mpaxl;
208 CSL_XMC_XMPAXH mpaxh;
210 mpaxh.bAddr = 0x21010; /* Segment Base Address */
211 mpaxh.segSize = 0xB; /* Segment size 4KB */
213 mpaxl.rAddr = 0x121010; /* Replacement Address */
214 mpaxl.sr = 1;
215 mpaxl.sw = 1;
216 mpaxl.sx = 1;
217 mpaxl.ur = 1;
218 mpaxl.uw = 1;
219 mpaxl.ux = 1;
221 /* set the xmpax for index2 */
222 CSL_XMC_setXMPAXH(2, &mpaxh);
223 CSL_XMC_setXMPAXL(2, &mpaxl);
224 }
226 static bool init_ddrphy(uint32_t base, const ddr3_phy_config *phy_cfg)
227 {
228 uint32_t tmp;
229 uint32_t timeoutCnt = 5;
231 while((HW_RD_REG32(base + DDRPHY_PGSR0_OFFSET)
232 & 0x00000001) != 0x00000001) {
233 BOARD_delay(DDR_CFG_DELAY);
234 timeoutCnt--;
235 if (timeoutCnt == 0)
236 return false;
237 }
239 HW_WR_REG32(base + DDRPHY_PLLCR_OFFSET, phy_cfg->pllcr);
240 BOARD_delay(DDR_CFG_DELAY);
242 tmp = HW_RD_REG32(base + DDRPHY_PGCR1_OFFSET);
243 tmp &= ~(phy_cfg->pgcr1_mask);
244 tmp |= phy_cfg->pgcr1_val;
245 HW_WR_REG32(base + DDRPHY_PGCR1_OFFSET, tmp);
246 BOARD_delay(DDR_CFG_DELAY);
248 HW_WR_REG32(base + DDRPHY_PTR0_OFFSET, phy_cfg->ptr0);
249 HW_WR_REG32(base + DDRPHY_PTR1_OFFSET, phy_cfg->ptr1);
250 HW_WR_REG32(base + DDRPHY_PTR3_OFFSET, phy_cfg->ptr3);
251 HW_WR_REG32(base + DDRPHY_PTR4_OFFSET, phy_cfg->ptr4);
253 tmp = HW_RD_REG32(base + DDRPHY_DCR_OFFSET);
254 tmp &= ~(phy_cfg->dcr_mask);
255 tmp |= phy_cfg->dcr_val;
256 HW_WR_REG32(base + DDRPHY_DCR_OFFSET, tmp);
257 BOARD_delay(DDR_CFG_DELAY);
259 HW_WR_REG32(base + DDRPHY_DTPR0_OFFSET, phy_cfg->dtpr0);
260 HW_WR_REG32(base + DDRPHY_DTPR1_OFFSET, phy_cfg->dtpr1);
261 HW_WR_REG32(base + DDRPHY_DTPR2_OFFSET, phy_cfg->dtpr2);
263 HW_WR_REG32(base + DDRPHY_MR0_OFFSET, phy_cfg->mr0);
264 HW_WR_REG32(base + DDRPHY_MR1_OFFSET, phy_cfg->mr1);
265 HW_WR_REG32(base + DDRPHY_MR2_OFFSET, phy_cfg->mr2);
267 HW_WR_REG32(base + DDRPHY_DTCR_OFFSET, phy_cfg->dtcr);
268 BOARD_delay(DDR_CFG_DELAY);
269 HW_WR_REG32(base + DDRPHY_PGCR2_OFFSET, phy_cfg->pgcr2);
270 BOARD_delay(DDR_CFG_DELAY);
272 HW_WR_REG32(base + DDRPHY_ZQ0CR1_OFFSET, phy_cfg->zq0cr1);
273 HW_WR_REG32(base + DDRPHY_ZQ1CR1_OFFSET, phy_cfg->zq1cr1);
274 HW_WR_REG32(base + DDRPHY_ZQ2CR1_OFFSET, phy_cfg->zq2cr1);
276 HW_WR_REG32(base + DDRPHY_PIR_OFFSET, phy_cfg->pir_v1);
277 BOARD_delay(DDR_CFG_DELAY);
279 timeoutCnt = 5;
280 while((HW_RD_REG32(base + DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) {
281 BOARD_delay(DDR_CFG_DELAY);
282 timeoutCnt--;
283 if (timeoutCnt == 0)
284 return false;
285 }
287 HW_WR_REG32(base + DDRPHY_PIR_OFFSET, phy_cfg->pir_v2);
288 BOARD_delay(DDR_CFG_DELAY);
289 timeoutCnt = 5;
290 while((HW_RD_REG32(base + DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) {
291 BOARD_delay(DDR_CFG_DELAY);
292 timeoutCnt--;
293 if (timeoutCnt == 0)
294 return false;
295 }
296 return true;
297 }
299 static void init_ddremif(CSL_Emif4fHandle hEmif4, const ddr3_emif_config *emif_cfg)
300 {
301 hEmif4->SDRAM_CONFIG = emif_cfg->sdcfg;
302 hEmif4->SDRAM_TIM_1 = emif_cfg->sdtim1;
303 hEmif4->SDRAM_TIM_2 = emif_cfg->sdtim2;
304 hEmif4->SDRAM_TIM_3 = emif_cfg->sdtim3;
305 hEmif4->SDRAM_TIM_4 = emif_cfg->sdtim4;
306 hEmif4->ZQ_CONFIG = emif_cfg->zqcfg;
307 hEmif4->SDRAM_REF_CTRL = emif_cfg->sdrfc;
308 }
310 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
311 Board_STATUS Board_DDR3Init()
312 {
313 xmc_add_emif_cfg_region();
315 CSL_BootCfgUnlockKicker();
316 if (init_ddrphy(CSL_DDR3_0_PHY_CFG_REGS, &ddr3phy_1333_32) == false)
317 return BOARD_INIT_DDR_FAIL;
318 init_ddremif((CSL_Emif4fHandle)CSL_DDR3_0_SLV_CFG_REGS, &ddr3_1333_32);
320 if (init_ddrphy(CSL_DDR3_1_PHY_CFG_REGS, &ddr3phy_1600_64) == false)
321 return BOARD_INIT_DDR_FAIL;
322 init_ddremif((CSL_Emif4fHandle)CSL_DDR3_1_SLV_CFG_REGS, &ddr3_1600_64);
324 return BOARD_SOK;
325 }