[processor-sdk/performance-audio-sr.git] / pdk_k2g_1_0_1_0_eng / packages / ti / board / src / evmKeystone / include / keystone_pll.h
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34 #ifndef EVM_KEYSTONE_PLL_H
35 #define EVM_KEYSTONE_PLL_H
37 #include <ti/csl/csl_pllc.h>
38 #include <ti/csl/cslr_bootcfg.h>
39 #include <ti/csl/hw_types.h>
41 #include "board_pll.h"
43 /** \brief PLL controller macros */
44 #define pllctl_reg(reg) (&(pllcReg->reg))
45 #define pllctl_reg_read(reg) HW_RD_REG32((uint32_t)pllctl_reg(reg))
46 #define pllctl_reg_write(reg, val) HW_WR_REG32((uint32_t)pllctl_reg(reg), val)
48 #define pllctl_reg_rmw(reg, mask, val) \
49 pllctl_reg_write(reg, \
50 (pllctl_reg_read(reg) & ~(mask)) | val)
52 #define pllctl_reg_setbits(reg, mask) \
53 pllctl_reg_rmw(reg, 0, mask)
55 #define pllctl_reg_clrbits(reg, mask) \
56 pllctl_reg_rmw(reg, mask, 0)
58 #define clrbits32(addr, clear) \
59 HW_WR_REG32((addr), HW_RD_REG32(addr) & ~(clear))
60 #define setbits32(addr, set) \
61 HW_WR_REG32((addr), HW_RD_REG32(addr) | (set))
62 #define clrsetbits32(addr, clear, set) \
63 HW_WR_REG32((addr), (HW_RD_REG32(addr) & ~(clear)) | (set))
65 /**
66 * \brief This structure defines the various Configuration Parameters for
67 * Keystone II PLL controller.
68 */
69 typedef struct
70 {
71 uint32_t reg0;
72 uint32_t reg1;
73 } keystonePllcReg;
75 /**
76 * \brief This structure defines the various Configuration Parameters for
77 * PLL controller.
78 */
79 typedef struct
80 {
81 CSL_PllcType pll;
82 /**< PLL controller type */
83 uint32_t pll_m;
84 /**< PLL multiplier */
85 uint32_t pll_d;
86 /**< PLL divider */
87 uint32_t pll_od;
88 /**< PLL output divider */
89 } pllcConfig;
91 extern const keystonePllcReg keystonePllcRegs[];
92 extern const pllcConfig pllcConfigs[];
94 extern uint32_t Board_getNumPllcConfigs();
95 #endif /* EVM_KEYSTONE_PLL_H */