pdk_k2g_1_0_1_0_eng/packages/ti/csl/arch/a15/hw_mpu_intc_dist.h

   1 /*
   2  *  Copyright (C) 2008-2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  *  Redistribution and use in source and binary forms, with or without
   5  *  modification, are permitted provided that the following conditions
   6  *  are met:
   7  *
   8  *    Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  *
  11  *    Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the
  14  *    distribution.
  15  *
  16  *    Neither the name of Texas Instruments Incorporated nor the names of
  17  *    its contributors may be used to endorse or promote products derived
  18  *    from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32 */
  33
  34 /**
  35  *  \file   hw_mpu_intc_dist.h
  36  *
  37  *  \brief  register-level header file for MPU
  38  *
  39 **/
  40
  41 #ifndef HW_MPU_INTC_DIST_H_
  42 #define HW_MPU_INTC_DIST_H_
  43
  44 #ifdef __cplusplus
  45 extern "C"
  46 {
  47 #endif
  48
  49 /****************************************************************************************************
  50 * Register Definitions
  51 ****************************************************************************************************/
  52 #define MPU_GICD_DCR                                                                                        (uint32_t)(0x0U)
  53 #define MPU_GICD_ICTR                                                                                       (uint32_t)(0x4U)
  54 #define MPU_GICD_IIDR                                                                                       (uint32_t)(0x8U)
  55 #define MPU_GICD_ISR0                                                                                       (uint32_t)(0x80U)
  56 #define MPU_GICD_ISR1                                                                                       (uint32_t)(0x84U)
  57 #define MPU_GICD_ISR2                                                                                       (uint32_t)(0x88U)
  58 #define MPU_GICD_ISR3                                                                                       (uint32_t)(0x8cU)
  59 #define MPU_GICD_ISR4                                                                                       (uint32_t)(0x90U)
  60 #define MPU_GICD_ISR5                                                                                       (uint32_t)(0x94U)
  61 #define MPU_GICD_ISER0                                                                                      (uint32_t)(0x100U)
  62 #define MPU_GICD_ISER1                                                                                      (uint32_t)(0x104U)
  63 #define MPU_GICD_ISER2                                                                                      (uint32_t)(0x108U)
  64 #define MPU_GICD_ISER3                                                                                      (uint32_t)(0x10cU)
  65 #define MPU_GICD_ISER4                                                                                      (uint32_t)(0x110U)
  66 #define MPU_GICD_ISER5                                                                                      (uint32_t)(0x114U)
  67 #define MPU_GICD_ICER0                                                                                      (uint32_t)(0x180U)
  68 #define MPU_GICD_ICER1                                                                                      (uint32_t)(0x184U)
  69 #define MPU_GICD_ICER2                                                                                      (uint32_t)(0x188U)
  70 #define MPU_GICD_ICER3                                                                                      (uint32_t)(0x18cU)
  71 #define MPU_GICD_ICER4                                                                                      (uint32_t)(0x190U)
  72 #define MPU_GICD_ICER5                                                                                      (uint32_t)(0x194U)
  73 #define MPU_GICD_ISPR0                                                                                      (uint32_t)(0x200U)
  74 #define MPU_GICD_ISPR1                                                                                      (uint32_t)(0x204U)
  75 #define MPU_GICD_ISPR2                                                                                      (uint32_t)(0x208U)
  76 #define MPU_GICD_ISPR3                                                                                      (uint32_t)(0x20cU)
  77 #define MPU_GICD_ISPR4                                                                                      (uint32_t)(0x210U)
  78 #define MPU_GICD_ISPR5                                                                                      (uint32_t)(0x214U)
  79 #define MPU_GICD_ICPR0                                                                                      (uint32_t)(0x280U)
  80 #define MPU_GICD_ICPR1                                                                                      (uint32_t)(0x284U)
  81 #define MPU_GICD_ICPR2                                                                                      (uint32_t)(0x288U)
  82 #define MPU_GICD_ICPR3                                                                                      (uint32_t)(0x28cU)
  83 #define MPU_GICD_ICPR4                                                                                      (uint32_t)(0x290U)
  84 #define MPU_GICD_ICPR5                                                                                      (uint32_t)(0x294U)
  85 #define MPU_GICD_ISACTIVER0                                                                                 (uint32_t)(0x300U)
  86 #define MPU_GICD_ISACTIVER1                                                                                 (uint32_t)(0x304U)
  87 #define MPU_GICD_ISACTIVER2                                                                                 (uint32_t)(0x308U)
  88 #define MPU_GICD_ISACTIVER3                                                                                 (uint32_t)(0x30cU)
  89 #define MPU_GICD_ISACTIVER4                                                                                 (uint32_t)(0x310U)
  90 #define MPU_GICD_ISACTIVER5                                                                                 (uint32_t)(0x314U)
  91 #define MPU_GICD_ICACTIVER0                                                                                 (uint32_t)(0x380U)
  92 #define MPU_GICD_ICACTIVER1                                                                                 (uint32_t)(0x384U)
  93 #define MPU_GICD_ICACTIVER2                                                                                 (uint32_t)(0x388U)
  94 #define MPU_GICD_ICACTIVER3                                                                                 (uint32_t)(0x38cU)
  95 #define MPU_GICD_ICACTIVER4                                                                                 (uint32_t)(0x390U)
  96 #define MPU_GICD_ICACTIVER5                                                                                 (uint32_t)(0x394U)
  97 #define MPU_GICD_IPR0                                                                                       (uint32_t)(0x400U)
  98 #define MPU_GICD_IPR1                                                                                       (uint32_t)(0x404U)
  99 #define MPU_GICD_IPR2                                                                                       (uint32_t)(0x408U)
 100 #define MPU_GICD_IPR3                                                                                       (uint32_t)(0x40cU)
 101 #define MPU_GICD_IPR4                                                                                       (uint32_t)(0x410U)
 102 #define MPU_GICD_IPR5                                                                                       (uint32_t)(0x414U)
 103 #define MPU_GICD_IPR6                                                                                       (uint32_t)(0x418U)
 104 #define MPU_GICD_IPR7                                                                                       (uint32_t)(0x41cU)
 105 #define MPU_GICD_IPR8                                                                                       (uint32_t)(0x420U)
 106 #define MPU_GICD_IPR9                                                                                       (uint32_t)(0x424U)
 107 #define MPU_GICD_IPR10                                                                                      (uint32_t)(0x428U)
 108 #define MPU_GICD_IPR11                                                                                      (uint32_t)(0x42cU)
 109 #define MPU_GICD_IPR12                                                                                      (uint32_t)(0x430U)
 110 #define MPU_GICD_IPR13                                                                                      (uint32_t)(0x434U)
 111 #define MPU_GICD_IPR14                                                                                      (uint32_t)(0x438U)
 112 #define MPU_GICD_IPR15                                                                                      (uint32_t)(0x43cU)
 113 #define MPU_GICD_IPR16                                                                                      (uint32_t)(0x440U)
 114 #define MPU_GICD_IPR17                                                                                      (uint32_t)(0x444U)
 115 #define MPU_GICD_IPR18                                                                                      (uint32_t)(0x448U)
 116 #define MPU_GICD_IPR19                                                                                      (uint32_t)(0x44cU)
 117 #define MPU_GICD_IPR20                                                                                      (uint32_t)(0x450U)
 118 #define MPU_GICD_IPR21                                                                                      (uint32_t)(0x454U)
 119 #define MPU_GICD_IPR22                                                                                      (uint32_t)(0x458U)
 120 #define MPU_GICD_IPR23                                                                                      (uint32_t)(0x45cU)
 121 #define MPU_GICD_IPR24                                                                                      (uint32_t)(0x460U)
 122 #define MPU_GICD_IPR25                                                                                      (uint32_t)(0x464U)
 123 #define MPU_GICD_IPR26                                                                                      (uint32_t)(0x468U)
 124 #define MPU_GICD_IPR27                                                                                      (uint32_t)(0x46cU)
 125 #define MPU_GICD_IPR28                                                                                      (uint32_t)(0x470U)
 126 #define MPU_GICD_IPR29                                                                                      (uint32_t)(0x474U)
 127 #define MPU_GICD_IPR30                                                                                      (uint32_t)(0x478U)
 128 #define MPU_GICD_IPR31                                                                                      (uint32_t)(0x47cU)
 129 #define MPU_GICD_IPR32                                                                                      (uint32_t)(0x480U)
 130 #define MPU_GICD_IPR33                                                                                      (uint32_t)(0x484U)
 131 #define MPU_GICD_IPR34                                                                                      (uint32_t)(0x488U)
 132 #define MPU_GICD_IPR35                                                                                      (uint32_t)(0x48cU)
 133 #define MPU_GICD_IPR36                                                                                      (uint32_t)(0x490U)
 134 #define MPU_GICD_IPR37                                                                                      (uint32_t)(0x494U)
 135 #define MPU_GICD_IPR38                                                                                      (uint32_t)(0x498U)
 136 #define MPU_GICD_IPR39                                                                                      (uint32_t)(0x49cU)
 137 #define MPU_GICD_IPR40                                                                                      (uint32_t)(0x4a0U)
 138 #define MPU_GICD_IPR41                                                                                      (uint32_t)(0x4a4U)
 139 #define MPU_GICD_IPR42                                                                                      (uint32_t)(0x4a8U)
 140 #define MPU_GICD_IPR43                                                                                      (uint32_t)(0x4acU)
 141 #define MPU_GICD_IPR44                                                                                      (uint32_t)(0x4b0U)
 142 #define MPU_GICD_IPR45                                                                                      (uint32_t)(0x4b4U)
 143 #define MPU_GICD_IPR46                                                                                      (uint32_t)(0x4b8U)
 144 #define MPU_GICD_IPR47                                                                                      (uint32_t)(0x4bcU)
 145 #define MPU_GICD_IPTR0                                                                                      (uint32_t)(0x800U)
 146 #define MPU_GICD_IPTR1                                                                                      (uint32_t)(0x804U)
 147 #define MPU_GICD_IPTR2                                                                                      (uint32_t)(0x808U)
 148 #define MPU_GICD_IPTR3                                                                                      (uint32_t)(0x80cU)
 149 #define MPU_GICD_IPTR4                                                                                      (uint32_t)(0x810U)
 150 #define MPU_GICD_IPTR5                                                                                      (uint32_t)(0x814U)
 151 #define MPU_GICD_IPTR6                                                                                      (uint32_t)(0x818U)
 152 #define MPU_GICD_IPTR7                                                                                      (uint32_t)(0x81cU)
 153 #define MPU_GICD_IPTR8                                                                                      (uint32_t)(0x820U)
 154 #define MPU_GICD_IPTR9                                                                                      (uint32_t)(0x824U)
 155 #define MPU_GICD_IPTR10                                                                                     (uint32_t)(0x828U)
 156 #define MPU_GICD_IPTR11                                                                                     (uint32_t)(0x82cU)
 157 #define MPU_GICD_IPTR12                                                                                     (uint32_t)(0x830U)
 158 #define MPU_GICD_IPTR13                                                                                     (uint32_t)(0x834U)
 159 #define MPU_GICD_IPTR14                                                                                     (uint32_t)(0x838U)
 160 #define MPU_GICD_IPTR15                                                                                     (uint32_t)(0x83cU)
 161 #define MPU_GICD_IPTR16                                                                                     (uint32_t)(0x840U)
 162 #define MPU_GICD_IPTR17                                                                                     (uint32_t)(0x844U)
 163 #define MPU_GICD_IPTR18                                                                                     (uint32_t)(0x848U)
 164 #define MPU_GICD_IPTR19                                                                                     (uint32_t)(0x84cU)
 165 #define MPU_GICD_IPTR20                                                                                     (uint32_t)(0x850U)
 166 #define MPU_GICD_IPTR21                                                                                     (uint32_t)(0x854U)
 167 #define MPU_GICD_IPTR22                                                                                     (uint32_t)(0x858U)
 168 #define MPU_GICD_IPTR23                                                                                     (uint32_t)(0x85cU)
 169 #define MPU_GICD_IPTR24                                                                                     (uint32_t)(0x860U)
 170 #define MPU_GICD_IPTR25                                                                                     (uint32_t)(0x864U)
 171 #define MPU_GICD_IPTR26                                                                                     (uint32_t)(0x868U)
 172 #define MPU_GICD_IPTR27                                                                                     (uint32_t)(0x86cU)
 173 #define MPU_GICD_IPTR28                                                                                     (uint32_t)(0x870U)
 174 #define MPU_GICD_IPTR29                                                                                     (uint32_t)(0x874U)
 175 #define MPU_GICD_IPTR30                                                                                     (uint32_t)(0x878U)
 176 #define MPU_GICD_IPTR31                                                                                     (uint32_t)(0x87cU)
 177 #define MPU_GICD_IPTR32                                                                                     (uint32_t)(0x880U)
 178 #define MPU_GICD_IPTR33                                                                                     (uint32_t)(0x884U)
 179 #define MPU_GICD_IPTR34                                                                                     (uint32_t)(0x888U)
 180 #define MPU_GICD_IPTR35                                                                                     (uint32_t)(0x88cU)
 181 #define MPU_GICD_IPTR36                                                                                     (uint32_t)(0x890U)
 182 #define MPU_GICD_IPTR37                                                                                     (uint32_t)(0x894U)
 183 #define MPU_GICD_IPTR38                                                                                     (uint32_t)(0x898U)
 184 #define MPU_GICD_IPTR39                                                                                     (uint32_t)(0x89cU)
 185 #define MPU_GICD_IPTR40                                                                                     (uint32_t)(0x8a0U)
 186 #define MPU_GICD_IPTR41                                                                                     (uint32_t)(0x8a4U)
 187 #define MPU_GICD_IPTR42                                                                                     (uint32_t)(0x8a8U)
 188 #define MPU_GICD_IPTR43                                                                                     (uint32_t)(0x8acU)
 189 #define MPU_GICD_IPTR44                                                                                     (uint32_t)(0x8b0U)
 190 #define MPU_GICD_IPTR45                                                                                     (uint32_t)(0x8b4U)
 191 #define MPU_GICD_IPTR46                                                                                     (uint32_t)(0x8b8U)
 192 #define MPU_GICD_IPTR47                                                                                     (uint32_t)(0x8bcU)
 193 #define MPU_GICD_ICFR0                                                                                      (uint32_t)(0xc00U)
 194 #define MPU_GICD_ICFR1                                                                                      (uint32_t)(0xc04U)
 195 #define MPU_GICD_ICFR2                                                                                      (uint32_t)(0xc08U)
 196 #define MPU_GICD_ICFR3                                                                                      (uint32_t)(0xc0cU)
 197 #define MPU_GICD_ICFR4                                                                                      (uint32_t)(0xc10U)
 198 #define MPU_GICD_ICFR5                                                                                      (uint32_t)(0xc14U)
 199 #define MPU_GICD_ICFR6                                                                                      (uint32_t)(0xc18U)
 200 #define MPU_GICD_ICFR7                                                                                      (uint32_t)(0xc1cU)
 201 #define MPU_GICD_ICFR8                                                                                      (uint32_t)(0xc20U)
 202 #define MPU_GICD_ICFR9                                                                                      (uint32_t)(0xc24U)
 203 #define MPU_GICD_ICFR10                                                                                     (uint32_t)(0xc28U)
 204 #define MPU_GICD_ICFR11                                                                                     (uint32_t)(0xc2cU)
 205 #define MPU_GICD_PPISR                                                                                      (uint32_t)(0xd00U)
 206 #define MPU_GICD_SPISR0                                                                                     (uint32_t)(0xd04U)
 207 #define MPU_GICD_SPISR1                                                                                     (uint32_t)(0xd08U)
 208 #define MPU_GICD_SPISR2                                                                                     (uint32_t)(0xd0cU)
 209 #define MPU_GICD_SPISR3                                                                                     (uint32_t)(0xd10U)
 210 #define MPU_GICD_SPISR4                                                                                     (uint32_t)(0xd14U)
 211 #define MPU_GICD_SGIR                                                                                       (uint32_t)(0xf00U)
 212 #define MPU_GICD_CPENDSGIR0                                                                                 (uint32_t)(0xf10U)
 213 #define MPU_GICD_CPENDSGIR1                                                                                 (uint32_t)(0xf14U)
 214 #define MPU_GICD_CPENDSGIR2                                                                                 (uint32_t)(0xf18U)
 215 #define MPU_GICD_CPENDSGIR3                                                                                 (uint32_t)(0xf1cU)
 216 #define MPU_GICD_SPENDSGIR0                                                                                 (uint32_t)(0xf20U)
 217 #define MPU_GICD_SPENDSGIR1                                                                                 (uint32_t)(0xf24U)
 218 #define MPU_GICD_SPENDSGIR2                                                                                 (uint32_t)(0xf28U)
 219 #define MPU_GICD_SPENDSGIR3                                                                                 (uint32_t)(0xf2cU)
 220 #define MPU_GICD_PIDR4                                                                                      (uint32_t)(0xfd0U)
 221 #define MPU_GICD_PIDR5                                                                                      (uint32_t)(0xfd4U)
 222 #define MPU_GICD_PIDR6                                                                                      (uint32_t)(0xfd8U)
 223 #define MPU_GICD_PIDR7                                                                                      (uint32_t)(0xfdcU)
 224 #define MPU_GICD_PIDR0                                                                                      (uint32_t)(0xfe0U)
 225 #define MPU_GICD_PIDR1                                                                                      (uint32_t)(0xfe4U)
 226 #define MPU_GICD_PIDR2                                                                                      (uint32_t)(0xfe8U)
 227 #define MPU_GICD_PIDR3                                                                                      (uint32_t)(0xfecU)
 228 #define MPU_GICD_CIDR0                                                                                      (uint32_t)(0xff0U)
 229 #define MPU_GICD_CIDR1                                                                                      (uint32_t)(0xff4U)
 230 #define MPU_GICD_CIDR2                                                                                      (uint32_t)(0xff8U)
 231 #define MPU_GICD_CIDR3                                                                                      (uint32_t)(0xffcU)
 232
 233 /****************************************************************************************************
 234 * Field Definition Macros
 235 ****************************************************************************************************/
 236
 237 #define MPU_GICD_DCR_ENABLES_SHIFT                                                                          (0U)
 238 #define MPU_GICD_DCR_ENABLES_MASK                                                                           (0x00000001U)
 239
 240 #define MPU_GICD_DCR_RESERVED_SHIFT                                                                         (2U)
 241 #define MPU_GICD_DCR_RESERVED_MASK                                                                          (0xfffffffcU)
 242
 243 #define MPU_GICD_DCR_ENABLENS_SHIFT                                                                         (1U)
 244 #define MPU_GICD_DCR_ENABLENS_MASK                                                                          (0x00000002U)
 245
 246 #define MPU_GICD_ICTR_ITLINESNUMBER_SHIFT                                                                   (0U)
 247 #define MPU_GICD_ICTR_ITLINESNUMBER_MASK                                                                    (0x0000001fU)
 248
 249 #define MPU_GICD_ICTR_CPUNUMBER_SHIFT                                                                       (5U)
 250 #define MPU_GICD_ICTR_CPUNUMBER_MASK                                                                        (0x000000e0U)
 251
 252 #define MPU_GICD_ICTR_SECURITYEXTN_SHIFT                                                                    (10U)
 253 #define MPU_GICD_ICTR_SECURITYEXTN_MASK                                                                     (0x00000400U)
 254
 255 #define MPU_GICD_ICTR_LSPI_SHIFT                                                                            (11U)
 256 #define MPU_GICD_ICTR_LSPI_MASK                                                                             (0x0000f800U)
 257
 258 #define MPU_GICD_ICTR_RESERVED_SHIFT                                                                        (8U)
 259 #define MPU_GICD_ICTR_RESERVED_MASK                                                                         (0x00000300U)
 260
 261 #define MPU_GICD_ICTR_RESERVED1_SHIFT                                                                       (16U)
 262 #define MPU_GICD_ICTR_RESERVED1_MASK                                                                        (0xffff0000U)
 263
 264 #define MPU_GICD_IIDR_IMPLEMENTER_SHIFT                                                                     (0U)
 265 #define MPU_GICD_IIDR_IMPLEMENTER_MASK                                                                      (0x00000fffU)
 266
 267 #define MPU_GICD_IIDR_REVISION_SHIFT                                                                        (12U)
 268 #define MPU_GICD_IIDR_REVISION_MASK                                                                         (0x0000f000U)
 269
 270 #define MPU_GICD_IIDR_VARIANT_SHIFT                                                                         (16U)
 271 #define MPU_GICD_IIDR_VARIANT_MASK                                                                          (0x000f0000U)
 272
 273 #define MPU_GICD_IIDR_PRODUCTID_SHIFT                                                                       (24U)
 274 #define MPU_GICD_IIDR_PRODUCTID_MASK                                                                        (0xff000000U)
 275
 276 #define MPU_GICD_IIDR_RESERVED_SHIFT                                                                        (20U)
 277 #define MPU_GICD_IIDR_RESERVED_MASK                                                                         (0x00f00000U)
 278
 279 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_0_SHIFT                                                           (0U)
 280 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_0_MASK                                                            (0x00000001U)
 281
 282 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_1_SHIFT                                                           (1U)
 283 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_1_MASK                                                            (0x00000002U)
 284
 285 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_2_SHIFT                                                           (2U)
 286 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_2_MASK                                                            (0x00000004U)
 287
 288 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_3_SHIFT                                                           (3U)
 289 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_3_MASK                                                            (0x00000008U)
 290
 291 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_4_SHIFT                                                           (4U)
 292 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_4_MASK                                                            (0x00000010U)
 293
 294 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_5_SHIFT                                                           (5U)
 295 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_5_MASK                                                            (0x00000020U)
 296
 297 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_6_SHIFT                                                           (6U)
 298 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_6_MASK                                                            (0x00000040U)
 299
 300 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_7_SHIFT                                                           (7U)
 301 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_7_MASK                                                            (0x00000080U)
 302
 303 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_8_SHIFT                                                           (8U)
 304 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_8_MASK                                                            (0x00000100U)
 305
 306 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_9_SHIFT                                                           (9U)
 307 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_9_MASK                                                            (0x00000200U)
 308
 309 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_10_SHIFT                                                          (10U)
 310 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_10_MASK                                                           (0x00000400U)
 311
 312 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_11_SHIFT                                                          (11U)
 313 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_11_MASK                                                           (0x00000800U)
 314
 315 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_12_SHIFT                                                          (12U)
 316 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_12_MASK                                                           (0x00001000U)
 317
 318 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_13_SHIFT                                                          (13U)
 319 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_13_MASK                                                           (0x00002000U)
 320
 321 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_14_SHIFT                                                          (14U)
 322 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_14_MASK                                                           (0x00004000U)
 323
 324 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_15_SHIFT                                                          (15U)
 325 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_15_MASK                                                           (0x00008000U)
 326
 327 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_27_SHIFT                                                          (27U)
 328 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_27_MASK                                                           (0x08000000U)
 329
 330 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_28_SHIFT                                                          (28U)
 331 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_28_MASK                                                           (0x10000000U)
 332
 333 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_29_SHIFT                                                          (29U)
 334 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_29_MASK                                                           (0x20000000U)
 335
 336 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_30_SHIFT                                                          (30U)
 337 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_30_MASK                                                           (0x40000000U)
 338
 339 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_31_SHIFT                                                          (31U)
 340 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_31_MASK                                                           (0x80000000U)
 341
 342 #define MPU_GICD_ISR0_RESERVED_SHIFT                                                                        (16U)
 343 #define MPU_GICD_ISR0_RESERVED_MASK                                                                         (0x01ff0000U)
 344
 345 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_25_SHIFT                                                          (25U)
 346 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_25_MASK                                                           (0x02000000U)
 347
 348 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_26_SHIFT                                                          (26U)
 349 #define MPU_GICD_ISR0_SECURITY_STATUS_FOR_26_MASK                                                           (0x04000000U)
 350
 351 #define MPU_GICD_ISR1_SECURITY_STATUS_FOR_32_63_SHIFT                                                       (0U)
 352 #define MPU_GICD_ISR1_SECURITY_STATUS_FOR_32_63_MASK                                                        (0xffffffffU)
 353
 354 #define MPU_GICD_ISR2_SECURITY_STATUS_FOR_64_95_SHIFT                                                       (0U)
 355 #define MPU_GICD_ISR2_SECURITY_STATUS_FOR_64_95_MASK                                                        (0xffffffffU)
 356
 357 #define MPU_GICD_ISR3_SECURITY_STATUS_FOR_96_127_SHIFT                                                      (0U)
 358 #define MPU_GICD_ISR3_SECURITY_STATUS_FOR_96_127_MASK                                                       (0xffffffffU)
 359
 360 #define MPU_GICD_ISR4_SECURITY_STATUS_FOR_127_159_SHIFT                                                     (0U)
 361 #define MPU_GICD_ISR4_SECURITY_STATUS_FOR_127_159_MASK                                                      (0xffffffffU)
 362
 363 #define MPU_GICD_ISR5_SECURITY_STATUS_FOR_160_191_SHIFT                                                     (0U)
 364 #define MPU_GICD_ISR5_SECURITY_STATUS_FOR_160_191_MASK                                                      (0xffffffffU)
 365
 366 #define MPU_GICD_ISER0_SET_ENABLE_FOR_0_SHIFT                                                               (0U)
 367 #define MPU_GICD_ISER0_SET_ENABLE_FOR_0_MASK                                                                (0x00000001U)
 368
 369 #define MPU_GICD_ISER0_SET_ENABLE_FOR_1_SHIFT                                                               (1U)
 370 #define MPU_GICD_ISER0_SET_ENABLE_FOR_1_MASK                                                                (0x00000002U)
 371
 372 #define MPU_GICD_ISER0_SET_ENABLE_FOR_2_SHIFT                                                               (2U)
 373 #define MPU_GICD_ISER0_SET_ENABLE_FOR_2_MASK                                                                (0x00000004U)
 374
 375 #define MPU_GICD_ISER0_SET_ENABLE_FOR_3_SHIFT                                                               (3U)
 376 #define MPU_GICD_ISER0_SET_ENABLE_FOR_3_MASK                                                                (0x00000008U)
 377
 378 #define MPU_GICD_ISER0_SET_ENABLE_FOR_4_SHIFT                                                               (4U)
 379 #define MPU_GICD_ISER0_SET_ENABLE_FOR_4_MASK                                                                (0x00000010U)
 380
 381 #define MPU_GICD_ISER0_SET_ENABLE_FOR_5_SHIFT                                                               (5U)
 382 #define MPU_GICD_ISER0_SET_ENABLE_FOR_5_MASK                                                                (0x00000020U)
 383
 384 #define MPU_GICD_ISER0_SET_ENABLE_FOR_6_SHIFT                                                               (6U)
 385 #define MPU_GICD_ISER0_SET_ENABLE_FOR_6_MASK                                                                (0x00000040U)
 386
 387 #define MPU_GICD_ISER0_SET_ENABLE_FOR_7_SHIFT                                                               (7U)
 388 #define MPU_GICD_ISER0_SET_ENABLE_FOR_7_MASK                                                                (0x00000080U)
 389
 390 #define MPU_GICD_ISER0_SET_ENABLE_FOR_8_SHIFT                                                               (8U)
 391 #define MPU_GICD_ISER0_SET_ENABLE_FOR_8_MASK                                                                (0x00000100U)
 392
 393 #define MPU_GICD_ISER0_SET_ENABLE_FOR_9_SHIFT                                                               (9U)
 394 #define MPU_GICD_ISER0_SET_ENABLE_FOR_9_MASK                                                                (0x00000200U)
 395
 396 #define MPU_GICD_ISER0_SET_ENABLE_FOR_10_SHIFT                                                              (10U)
 397 #define MPU_GICD_ISER0_SET_ENABLE_FOR_10_MASK                                                               (0x00000400U)
 398
 399 #define MPU_GICD_ISER0_SET_ENABLE_FOR_11_SHIFT                                                              (11U)
 400 #define MPU_GICD_ISER0_SET_ENABLE_FOR_11_MASK                                                               (0x00000800U)
 401
 402 #define MPU_GICD_ISER0_SET_ENABLE_FOR_12_SHIFT                                                              (12U)
 403 #define MPU_GICD_ISER0_SET_ENABLE_FOR_12_MASK                                                               (0x00001000U)
 404
 405 #define MPU_GICD_ISER0_SET_ENABLE_FOR_13_SHIFT                                                              (13U)
 406 #define MPU_GICD_ISER0_SET_ENABLE_FOR_13_MASK                                                               (0x00002000U)
 407
 408 #define MPU_GICD_ISER0_SET_ENABLE_FOR_14_SHIFT                                                              (14U)
 409 #define MPU_GICD_ISER0_SET_ENABLE_FOR_14_MASK                                                               (0x00004000U)
 410
 411 #define MPU_GICD_ISER0_SET_ENABLE_FOR_15_SHIFT                                                              (15U)
 412 #define MPU_GICD_ISER0_SET_ENABLE_FOR_15_MASK                                                               (0x00008000U)
 413
 414 #define MPU_GICD_ISER0_SET_ENABLE_FOR_27_SHIFT                                                              (27U)
 415 #define MPU_GICD_ISER0_SET_ENABLE_FOR_27_MASK                                                               (0x08000000U)
 416
 417 #define MPU_GICD_ISER0_SET_ENABLE_FOR_28_SHIFT                                                              (28U)
 418 #define MPU_GICD_ISER0_SET_ENABLE_FOR_28_MASK                                                               (0x10000000U)
 419
 420 #define MPU_GICD_ISER0_SET_ENABLE_FOR_29_SHIFT                                                              (29U)
 421 #define MPU_GICD_ISER0_SET_ENABLE_FOR_29_MASK                                                               (0x20000000U)
 422
 423 #define MPU_GICD_ISER0_SET_ENABLE_FOR_30_SHIFT                                                              (30U)
 424 #define MPU_GICD_ISER0_SET_ENABLE_FOR_30_MASK                                                               (0x40000000U)
 425
 426 #define MPU_GICD_ISER0_SET_ENABLE_FOR_31_SHIFT                                                              (31U)
 427 #define MPU_GICD_ISER0_SET_ENABLE_FOR_31_MASK                                                               (0x80000000U)
 428
 429 #define MPU_GICD_ISER0_RESERVED_SHIFT                                                                       (16U)
 430 #define MPU_GICD_ISER0_RESERVED_MASK                                                                        (0x01ff0000U)
 431
 432 #define MPU_GICD_ISER0_SET_ENABLE_FOR_25_SHIFT                                                              (25U)
 433 #define MPU_GICD_ISER0_SET_ENABLE_FOR_25_MASK                                                               (0x02000000U)
 434
 435 #define MPU_GICD_ISER0_SET_ENABLE_FOR_26_SHIFT                                                              (26U)
 436 #define MPU_GICD_ISER0_SET_ENABLE_FOR_26_MASK                                                               (0x04000000U)
 437
 438 #define MPU_GICD_ISER1_SET_ENABLE_FOR_63_32_SHIFT                                                           (0U)
 439 #define MPU_GICD_ISER1_SET_ENABLE_FOR_63_32_MASK                                                            (0xffffffffU)
 440
 441 #define MPU_GICD_ISER2_SET_ENABLE_FOR_95_64_SHIFT                                                           (0U)
 442 #define MPU_GICD_ISER2_SET_ENABLE_FOR_95_64_MASK                                                            (0xffffffffU)
 443
 444 #define MPU_GICD_ISER3_SET_ENABLE_FOR_127_96_SHIFT                                                          (0U)
 445 #define MPU_GICD_ISER3_SET_ENABLE_FOR_127_96_MASK                                                           (0xffffffffU)
 446
 447 #define MPU_GICD_ISER4_SET_ENABLE_FOR_159_128_SHIFT                                                         (0U)
 448 #define MPU_GICD_ISER4_SET_ENABLE_FOR_159_128_MASK                                                          (0xffffffffU)
 449
 450 #define MPU_GICD_ISER5_SET_ENABLE_FOR_191_160_SHIFT                                                         (0U)
 451 #define MPU_GICD_ISER5_SET_ENABLE_FOR_191_160_MASK                                                          (0xffffffffU)
 452
 453 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_0_SHIFT                                                             (0U)
 454 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_0_MASK                                                              (0x00000001U)
 455
 456 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_1_SHIFT                                                             (1U)
 457 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_1_MASK                                                              (0x00000002U)
 458
 459 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_2_SHIFT                                                             (2U)
 460 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_2_MASK                                                              (0x00000004U)
 461
 462 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_3_SHIFT                                                             (3U)
 463 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_3_MASK                                                              (0x00000008U)
 464
 465 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_4_SHIFT                                                             (4U)
 466 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_4_MASK                                                              (0x00000010U)
 467
 468 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_5_SHIFT                                                             (5U)
 469 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_5_MASK                                                              (0x00000020U)
 470
 471 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_6_SHIFT                                                             (6U)
 472 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_6_MASK                                                              (0x00000040U)
 473
 474 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_7_SHIFT                                                             (7U)
 475 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_7_MASK                                                              (0x00000080U)
 476
 477 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_8_SHIFT                                                             (8U)
 478 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_8_MASK                                                              (0x00000100U)
 479
 480 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_9_SHIFT                                                             (9U)
 481 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_9_MASK                                                              (0x00000200U)
 482
 483 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_10_SHIFT                                                            (10U)
 484 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_10_MASK                                                             (0x00000400U)
 485
 486 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_11_SHIFT                                                            (11U)
 487 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_11_MASK                                                             (0x00000800U)
 488
 489 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_12_SHIFT                                                            (12U)
 490 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_12_MASK                                                             (0x00001000U)
 491
 492 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_13_SHIFT                                                            (13U)
 493 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_13_MASK                                                             (0x00002000U)
 494
 495 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_14_SHIFT                                                            (14U)
 496 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_14_MASK                                                             (0x00004000U)
 497
 498 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_15_SHIFT                                                            (15U)
 499 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_15_MASK                                                             (0x00008000U)
 500
 501 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_27_SHIFT                                                            (27U)
 502 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_27_MASK                                                             (0x08000000U)
 503
 504 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_28_SHIFT                                                            (28U)
 505 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_28_MASK                                                             (0x10000000U)
 506
 507 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_29_SHIFT                                                            (29U)
 508 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_29_MASK                                                             (0x20000000U)
 509
 510 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_30_SHIFT                                                            (30U)
 511 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_30_MASK                                                             (0x40000000U)
 512
 513 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_31_SHIFT                                                            (31U)
 514 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_31_MASK                                                             (0x80000000U)
 515
 516 #define MPU_GICD_ICER0_RESERVED_SHIFT                                                                       (16U)
 517 #define MPU_GICD_ICER0_RESERVED_MASK                                                                        (0x01ff0000U)
 518
 519 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_25_SHIFT                                                            (25U)
 520 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_25_MASK                                                             (0x02000000U)
 521
 522 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_26_SHIFT                                                            (26U)
 523 #define MPU_GICD_ICER0_CLEAR_ENABLE_FOR_26_MASK                                                             (0x04000000U)
 524
 525 #define MPU_GICD_ICER1_CLEAR_ENABLE_FOR_63_32_SHIFT                                                         (0U)
 526 #define MPU_GICD_ICER1_CLEAR_ENABLE_FOR_63_32_MASK                                                          (0xffffffffU)
 527
 528 #define MPU_GICD_ICER2_CLEAR_ENABLE_FOR_95_64_SHIFT                                                         (0U)
 529 #define MPU_GICD_ICER2_CLEAR_ENABLE_FOR_95_64_MASK                                                          (0xffffffffU)
 530
 531 #define MPU_GICD_ICER3_CLEAR_ENABLE_FOR_127_96_SHIFT                                                        (0U)
 532 #define MPU_GICD_ICER3_CLEAR_ENABLE_FOR_127_96_MASK                                                         (0xffffffffU)
 533
 534 #define MPU_GICD_ICER4_CLEAR_ENABLE_FOR_159_128_SHIFT                                                       (0U)
 535 #define MPU_GICD_ICER4_CLEAR_ENABLE_FOR_159_128_MASK                                                        (0xffffffffU)
 536
 537 #define MPU_GICD_ICER5_CLEAR_ENABLE_FOR_191_160_SHIFT                                                       (0U)
 538 #define MPU_GICD_ICER5_CLEAR_ENABLE_FOR_191_160_MASK                                                        (0xffffffffU)
 539
 540 #define MPU_GICD_ISPR0_SET_PENDING_FOR_0_SHIFT                                                              (0U)
 541 #define MPU_GICD_ISPR0_SET_PENDING_FOR_0_MASK                                                               (0x00000001U)
 542
 543 #define MPU_GICD_ISPR0_SET_PENDING_FOR_1_SHIFT                                                              (1U)
 544 #define MPU_GICD_ISPR0_SET_PENDING_FOR_1_MASK                                                               (0x00000002U)
 545
 546 #define MPU_GICD_ISPR0_SET_PENDING_FOR_2_SHIFT                                                              (2U)
 547 #define MPU_GICD_ISPR0_SET_PENDING_FOR_2_MASK                                                               (0x00000004U)
 548
 549 #define MPU_GICD_ISPR0_SET_PENDING_FOR_3_SHIFT                                                              (3U)
 550 #define MPU_GICD_ISPR0_SET_PENDING_FOR_3_MASK                                                               (0x00000008U)
 551
 552 #define MPU_GICD_ISPR0_SET_PENDING_FOR_4_SHIFT                                                              (4U)
 553 #define MPU_GICD_ISPR0_SET_PENDING_FOR_4_MASK                                                               (0x00000010U)
 554
 555 #define MPU_GICD_ISPR0_SET_PENDING_FOR_5_SHIFT                                                              (5U)
 556 #define MPU_GICD_ISPR0_SET_PENDING_FOR_5_MASK                                                               (0x00000020U)
 557
 558 #define MPU_GICD_ISPR0_SET_PENDING_FOR_6_SHIFT                                                              (6U)
 559 #define MPU_GICD_ISPR0_SET_PENDING_FOR_6_MASK                                                               (0x00000040U)
 560
 561 #define MPU_GICD_ISPR0_SET_PENDING_FOR_7_SHIFT                                                              (7U)
 562 #define MPU_GICD_ISPR0_SET_PENDING_FOR_7_MASK                                                               (0x00000080U)
 563
 564 #define MPU_GICD_ISPR0_SET_PENDING_FOR_8_SHIFT                                                              (8U)
 565 #define MPU_GICD_ISPR0_SET_PENDING_FOR_8_MASK                                                               (0x00000100U)
 566
 567 #define MPU_GICD_ISPR0_SET_PENDING_FOR_9_SHIFT                                                              (9U)
 568 #define MPU_GICD_ISPR0_SET_PENDING_FOR_9_MASK                                                               (0x00000200U)
 569
 570 #define MPU_GICD_ISPR0_SET_PENDING_FOR_10_SHIFT                                                             (10U)
 571 #define MPU_GICD_ISPR0_SET_PENDING_FOR_10_MASK                                                              (0x00000400U)
 572
 573 #define MPU_GICD_ISPR0_SET_PENDING_FOR_11_SHIFT                                                             (11U)
 574 #define MPU_GICD_ISPR0_SET_PENDING_FOR_11_MASK                                                              (0x00000800U)
 575
 576 #define MPU_GICD_ISPR0_SET_PENDING_FOR_12_SHIFT                                                             (12U)
 577 #define MPU_GICD_ISPR0_SET_PENDING_FOR_12_MASK                                                              (0x00001000U)
 578
 579 #define MPU_GICD_ISPR0_SET_PENDING_FOR_13_SHIFT                                                             (13U)
 580 #define MPU_GICD_ISPR0_SET_PENDING_FOR_13_MASK                                                              (0x00002000U)
 581
 582 #define MPU_GICD_ISPR0_SET_PENDING_FOR_14_SHIFT                                                             (14U)
 583 #define MPU_GICD_ISPR0_SET_PENDING_FOR_14_MASK                                                              (0x00004000U)
 584
 585 #define MPU_GICD_ISPR0_SET_PENDING_FOR_15_SHIFT                                                             (15U)
 586 #define MPU_GICD_ISPR0_SET_PENDING_FOR_15_MASK                                                              (0x00008000U)
 587
 588 #define MPU_GICD_ISPR0_SET_PENDING_FOR_27_SHIFT                                                             (27U)
 589 #define MPU_GICD_ISPR0_SET_PENDING_FOR_27_MASK                                                              (0x08000000U)
 590
 591 #define MPU_GICD_ISPR0_SET_PENDING_FOR_28_SHIFT                                                             (28U)
 592 #define MPU_GICD_ISPR0_SET_PENDING_FOR_28_MASK                                                              (0x10000000U)
 593
 594 #define MPU_GICD_ISPR0_SET_PENDING_FOR_29_SHIFT                                                             (29U)
 595 #define MPU_GICD_ISPR0_SET_PENDING_FOR_29_MASK                                                              (0x20000000U)
 596
 597 #define MPU_GICD_ISPR0_SET_PENDING_FOR_30_SHIFT                                                             (30U)
 598 #define MPU_GICD_ISPR0_SET_PENDING_FOR_30_MASK                                                              (0x40000000U)
 599
 600 #define MPU_GICD_ISPR0_SET_PENDING_FOR_31_SHIFT                                                             (31U)
 601 #define MPU_GICD_ISPR0_SET_PENDING_FOR_31_MASK                                                              (0x80000000U)
 602
 603 #define MPU_GICD_ISPR0_RESERVED_SHIFT                                                                       (16U)
 604 #define MPU_GICD_ISPR0_RESERVED_MASK                                                                        (0x01ff0000U)
 605
 606 #define MPU_GICD_ISPR0_SET_PENDING_FOR_25_SHIFT                                                             (25U)
 607 #define MPU_GICD_ISPR0_SET_PENDING_FOR_25_MASK                                                              (0x02000000U)
 608
 609 #define MPU_GICD_ISPR0_SET_PENDING_FOR_26_SHIFT                                                             (26U)
 610 #define MPU_GICD_ISPR0_SET_PENDING_FOR_26_MASK                                                              (0x04000000U)
 611
 612 #define MPU_GICD_ISPR1_SET_PENDING_FOR_63_32_SHIFT                                                          (0U)
 613 #define MPU_GICD_ISPR1_SET_PENDING_FOR_63_32_MASK                                                           (0xffffffffU)
 614
 615 #define MPU_GICD_ISPR2_SET_PENDING_FOR_95_64_SHIFT                                                          (0U)
 616 #define MPU_GICD_ISPR2_SET_PENDING_FOR_95_64_MASK                                                           (0xffffffffU)
 617
 618 #define MPU_GICD_ISPR3_SET_PENDING_FOR_127_96_SHIFT                                                         (0U)
 619 #define MPU_GICD_ISPR3_SET_PENDING_FOR_127_96_MASK                                                          (0xffffffffU)
 620
 621 #define MPU_GICD_ISPR4_SET_PENDING_FOR_159_128_SHIFT                                                        (0U)
 622 #define MPU_GICD_ISPR4_SET_PENDING_FOR_159_128_MASK                                                         (0xffffffffU)
 623
 624 #define MPU_GICD_ISPR5_SET_PENDING_FOR_191_160_SHIFT                                                        (0U)
 625 #define MPU_GICD_ISPR5_SET_PENDING_FOR_191_160_MASK                                                         (0xffffffffU)
 626
 627 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_0_SHIFT                                                             (0U)
 628 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_0_MASK                                                              (0x00000001U)
 629
 630 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_1_SHIFT                                                             (1U)
 631 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_1_MASK                                                              (0x00000002U)
 632
 633 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_2_SHIFT                                                             (2U)
 634 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_2_MASK                                                              (0x00000004U)
 635
 636 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_3_SHIFT                                                             (3U)
 637 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_3_MASK                                                              (0x00000008U)
 638
 639 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_4_SHIFT                                                             (4U)
 640 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_4_MASK                                                              (0x00000010U)
 641
 642 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_5_SHIFT                                                             (5U)
 643 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_5_MASK                                                              (0x00000020U)
 644
 645 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_6_SHIFT                                                             (6U)
 646 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_6_MASK                                                              (0x00000040U)
 647
 648 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_7_SHIFT                                                             (7U)
 649 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_7_MASK                                                              (0x00000080U)
 650
 651 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_8_SHIFT                                                             (8U)
 652 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_8_MASK                                                              (0x00000100U)
 653
 654 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_9_SHIFT                                                             (9U)
 655 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_9_MASK                                                              (0x00000200U)
 656
 657 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_10_SHIFT                                                            (10U)
 658 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_10_MASK                                                             (0x00000400U)
 659
 660 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_11_SHIFT                                                            (11U)
 661 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_11_MASK                                                             (0x00000800U)
 662
 663 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_12_SHIFT                                                            (12U)
 664 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_12_MASK                                                             (0x00001000U)
 665
 666 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_13_SHIFT                                                            (13U)
 667 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_13_MASK                                                             (0x00002000U)
 668
 669 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_14_SHIFT                                                            (14U)
 670 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_14_MASK                                                             (0x00004000U)
 671
 672 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_15_SHIFT                                                            (15U)
 673 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_15_MASK                                                             (0x00008000U)
 674
 675 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_27_SHIFT                                                            (27U)
 676 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_27_MASK                                                             (0x08000000U)
 677
 678 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_28_SHIFT                                                            (28U)
 679 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_28_MASK                                                             (0x10000000U)
 680
 681 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_29_SHIFT                                                            (29U)
 682 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_29_MASK                                                             (0x20000000U)
 683
 684 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_30_SHIFT                                                            (30U)
 685 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_30_MASK                                                             (0x40000000U)
 686
 687 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_31_SHIFT                                                            (31U)
 688 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_31_MASK                                                             (0x80000000U)
 689
 690 #define MPU_GICD_ICPR0_RESERVED_SHIFT                                                                       (16U)
 691 #define MPU_GICD_ICPR0_RESERVED_MASK                                                                        (0x01ff0000U)
 692
 693 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_25_SHIFT                                                            (25U)
 694 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_25_MASK                                                             (0x02000000U)
 695
 696 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_26_SHIFT                                                            (26U)
 697 #define MPU_GICD_ICPR0_CLEARPENDING_FOR_26_MASK                                                             (0x04000000U)
 698
 699 #define MPU_GICD_ICPR1_CLEARPENDING_FOR_63_32_SHIFT                                                         (0U)
 700 #define MPU_GICD_ICPR1_CLEARPENDING_FOR_63_32_MASK                                                          (0xffffffffU)
 701
 702 #define MPU_GICD_ICPR2_CLEARPENDING_FOR_95_64_SHIFT                                                         (0U)
 703 #define MPU_GICD_ICPR2_CLEARPENDING_FOR_95_64_MASK                                                          (0xffffffffU)
 704
 705 #define MPU_GICD_ICPR3_CLEARPENDING_FOR_127_96_SHIFT                                                        (0U)
 706 #define MPU_GICD_ICPR3_CLEARPENDING_FOR_127_96_MASK                                                         (0xffffffffU)
 707
 708 #define MPU_GICD_ICPR4_CLEARPENDING_FOR_159_128_SHIFT                                                       (0U)
 709 #define MPU_GICD_ICPR4_CLEARPENDING_FOR_159_128_MASK                                                        (0xffffffffU)
 710
 711 #define MPU_GICD_ICPR5_CLEARPENDING_FOR_191_160_SHIFT                                                       (0U)
 712 #define MPU_GICD_ICPR5_CLEARPENDING_FOR_191_160_MASK                                                        (0xffffffffU)
 713
 714 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_0_SHIFT                                                         (0U)
 715 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_0_MASK                                                          (0x00000001U)
 716
 717 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_1_SHIFT                                                         (1U)
 718 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_1_MASK                                                          (0x00000002U)
 719
 720 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_2_SHIFT                                                         (2U)
 721 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_2_MASK                                                          (0x00000004U)
 722
 723 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_3_SHIFT                                                         (3U)
 724 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_3_MASK                                                          (0x00000008U)
 725
 726 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_4_SHIFT                                                         (4U)
 727 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_4_MASK                                                          (0x00000010U)
 728
 729 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_5_SHIFT                                                         (5U)
 730 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_5_MASK                                                          (0x00000020U)
 731
 732 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_6_SHIFT                                                         (6U)
 733 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_6_MASK                                                          (0x00000040U)
 734
 735 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_7_SHIFT                                                         (7U)
 736 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_7_MASK                                                          (0x00000080U)
 737
 738 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_8_SHIFT                                                         (8U)
 739 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_8_MASK                                                          (0x00000100U)
 740
 741 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_9_SHIFT                                                         (9U)
 742 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_9_MASK                                                          (0x00000200U)
 743
 744 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_10_SHIFT                                                        (10U)
 745 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_10_MASK                                                         (0x00000400U)
 746
 747 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_11_SHIFT                                                        (11U)
 748 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_11_MASK                                                         (0x00000800U)
 749
 750 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_12_SHIFT                                                        (12U)
 751 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_12_MASK                                                         (0x00001000U)
 752
 753 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_13_SHIFT                                                        (13U)
 754 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_13_MASK                                                         (0x00002000U)
 755
 756 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_14_SHIFT                                                        (14U)
 757 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_14_MASK                                                         (0x00004000U)
 758
 759 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_15_SHIFT                                                        (15U)
 760 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_15_MASK                                                         (0x00008000U)
 761
 762 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_27_SHIFT                                                        (27U)
 763 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_27_MASK                                                         (0x08000000U)
 764
 765 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_28_SHIFT                                                        (28U)
 766 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_28_MASK                                                         (0x10000000U)
 767
 768 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_29_SHIFT                                                        (29U)
 769 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_29_MASK                                                         (0x20000000U)
 770
 771 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_30_SHIFT                                                        (30U)
 772 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_30_MASK                                                         (0x40000000U)
 773
 774 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_31_SHIFT                                                        (31U)
 775 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_31_MASK                                                         (0x80000000U)
 776
 777 #define MPU_GICD_ISACTIVER0_RESERVED_SHIFT                                                                  (16U)
 778 #define MPU_GICD_ISACTIVER0_RESERVED_MASK                                                                   (0x01ff0000U)
 779
 780 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_25_SHIFT                                                        (25U)
 781 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_25_MASK                                                         (0x02000000U)
 782
 783 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_26_SHIFT                                                        (26U)
 784 #define MPU_GICD_ISACTIVER0_ACTIVE_BITS_FOR_26_MASK                                                         (0x04000000U)
 785
 786 #define MPU_GICD_ISACTIVER1_ACTIVE_BITS_FOR_63_32_SHIFT                                                     (0U)
 787 #define MPU_GICD_ISACTIVER1_ACTIVE_BITS_FOR_63_32_MASK                                                      (0xffffffffU)
 788
 789 #define MPU_GICD_ISACTIVER2_ACTIVE_BITS_FOR_95_64_SHIFT                                                     (0U)
 790 #define MPU_GICD_ISACTIVER2_ACTIVE_BITS_FOR_95_64_MASK                                                      (0xffffffffU)
 791
 792 #define MPU_GICD_ISACTIVER3_ACTIVE_BITS_FOR_127_96_SHIFT                                                    (0U)
 793 #define MPU_GICD_ISACTIVER3_ACTIVE_BITS_FOR_127_96_MASK                                                     (0xffffffffU)
 794
 795 #define MPU_GICD_ISACTIVER4_ACTIVE_BITS_FOR_159_128_SHIFT                                                   (0U)
 796 #define MPU_GICD_ISACTIVER4_ACTIVE_BITS_FOR_159_128_MASK                                                    (0xffffffffU)
 797
 798 #define MPU_GICD_ISACTIVER5_ACTIVE_BITS_FOR_191_160_SHIFT                                                   (0U)
 799 #define MPU_GICD_ISACTIVER5_ACTIVE_BITS_FOR_191_160_MASK                                                    (0xffffffffU)
 800
 801 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_0_SHIFT                                                         (0U)
 802 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_0_MASK                                                          (0x00000001U)
 803
 804 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_1_SHIFT                                                         (1U)
 805 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_1_MASK                                                          (0x00000002U)
 806
 807 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_2_SHIFT                                                         (2U)
 808 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_2_MASK                                                          (0x00000004U)
 809
 810 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_3_SHIFT                                                         (3U)
 811 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_3_MASK                                                          (0x00000008U)
 812
 813 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_4_SHIFT                                                         (4U)
 814 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_4_MASK                                                          (0x00000010U)
 815
 816 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_5_SHIFT                                                         (5U)
 817 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_5_MASK                                                          (0x00000020U)
 818
 819 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_6_SHIFT                                                         (6U)
 820 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_6_MASK                                                          (0x00000040U)
 821
 822 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_7_SHIFT                                                         (7U)
 823 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_7_MASK                                                          (0x00000080U)
 824
 825 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_8_SHIFT                                                         (8U)
 826 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_8_MASK                                                          (0x00000100U)
 827
 828 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_9_SHIFT                                                         (9U)
 829 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_9_MASK                                                          (0x00000200U)
 830
 831 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_10_SHIFT                                                        (10U)
 832 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_10_MASK                                                         (0x00000400U)
 833
 834 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_11_SHIFT                                                        (11U)
 835 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_11_MASK                                                         (0x00000800U)
 836
 837 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_12_SHIFT                                                        (12U)
 838 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_12_MASK                                                         (0x00001000U)
 839
 840 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_13_SHIFT                                                        (13U)
 841 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_13_MASK                                                         (0x00002000U)
 842
 843 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_14_SHIFT                                                        (14U)
 844 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_14_MASK                                                         (0x00004000U)
 845
 846 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_15_SHIFT                                                        (15U)
 847 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_15_MASK                                                         (0x00008000U)
 848
 849 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_27_SHIFT                                                        (27U)
 850 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_27_MASK                                                         (0x08000000U)
 851
 852 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_28_SHIFT                                                        (28U)
 853 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_28_MASK                                                         (0x10000000U)
 854
 855 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_29_SHIFT                                                        (29U)
 856 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_29_MASK                                                         (0x20000000U)
 857
 858 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_30_SHIFT                                                        (30U)
 859 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_30_MASK                                                         (0x40000000U)
 860
 861 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_31_SHIFT                                                        (31U)
 862 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_31_MASK                                                         (0x80000000U)
 863
 864 #define MPU_GICD_ICACTIVER0_RESERVED_SHIFT                                                                  (16U)
 865 #define MPU_GICD_ICACTIVER0_RESERVED_MASK                                                                   (0x01ff0000U)
 866
 867 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_25_SHIFT                                                        (25U)
 868 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_25_MASK                                                         (0x02000000U)
 869
 870 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_26_SHIFT                                                        (26U)
 871 #define MPU_GICD_ICACTIVER0_ACTIVE_BITS_FOR_26_MASK                                                         (0x04000000U)
 872
 873 #define MPU_GICD_ICACTIVER1_ACTIVE_BITS_FOR_63_32_SHIFT                                                     (0U)
 874 #define MPU_GICD_ICACTIVER1_ACTIVE_BITS_FOR_63_32_MASK                                                      (0xffffffffU)
 875
 876 #define MPU_GICD_ICACTIVER2_ACTIVE_BITS_FOR_95_64_SHIFT                                                     (0U)
 877 #define MPU_GICD_ICACTIVER2_ACTIVE_BITS_FOR_95_64_MASK                                                      (0xffffffffU)
 878
 879 #define MPU_GICD_ICACTIVER3_ACTIVE_BITS_FOR_127_96_SHIFT                                                    (0U)
 880 #define MPU_GICD_ICACTIVER3_ACTIVE_BITS_FOR_127_96_MASK                                                     (0xffffffffU)
 881
 882 #define MPU_GICD_ICACTIVER4_ACTIVE_BITS_FOR_159_128_SHIFT                                                   (0U)
 883 #define MPU_GICD_ICACTIVER4_ACTIVE_BITS_FOR_159_128_MASK                                                    (0xffffffffU)
 884
 885 #define MPU_GICD_ICACTIVER5_ACTIVE_BITS_FOR_191_160_SHIFT                                                   (0U)
 886 #define MPU_GICD_ICACTIVER5_ACTIVE_BITS_FOR_191_160_MASK                                                    (0xffffffffU)
 887
 888 #define MPU_GICD_IPR0_PRIORITY_BYTEOFFSET_2_SHIFT                                                           (16U)
 889 #define MPU_GICD_IPR0_PRIORITY_BYTEOFFSET_2_MASK                                                            (0x00ff0000U)
 890
 891 #define MPU_GICD_IPR0_PRIORITY_BYTEOFFSET_1_SHIFT                                                           (8U)
 892 #define MPU_GICD_IPR0_PRIORITY_BYTEOFFSET_1_MASK                                                            (0x0000ff00U)
 893
 894 #define MPU_GICD_IPR0_PRIORITY_BYTEOFFSET_3_SHIFT                                                           (24U)
 895 #define MPU_GICD_IPR0_PRIORITY_BYTEOFFSET_3_MASK                                                            (0xff000000U)
 896
 897 #define MPU_GICD_IPR0_PRIORITY_BYTEOFFSET_0_SHIFT                                                           (0U)
 898 #define MPU_GICD_IPR0_PRIORITY_BYTEOFFSET_0_MASK                                                            (0x000000ffU)
 899
 900 #define MPU_GICD_IPR1_PRIORITY_BYTEOFFSET_2_SHIFT                                                           (16U)
 901 #define MPU_GICD_IPR1_PRIORITY_BYTEOFFSET_2_MASK                                                            (0x00ff0000U)
 902
 903 #define MPU_GICD_IPR1_PRIORITY_BYTEOFFSET_1_SHIFT                                                           (8U)
 904 #define MPU_GICD_IPR1_PRIORITY_BYTEOFFSET_1_MASK                                                            (0x0000ff00U)
 905
 906 #define MPU_GICD_IPR1_PRIORITY_BYTEOFFSET_3_SHIFT                                                           (24U)
 907 #define MPU_GICD_IPR1_PRIORITY_BYTEOFFSET_3_MASK                                                            (0xff000000U)
 908
 909 #define MPU_GICD_IPR1_PRIORITY_BYTEOFFSET_0_SHIFT                                                           (0U)
 910 #define MPU_GICD_IPR1_PRIORITY_BYTEOFFSET_0_MASK                                                            (0x000000ffU)
 911
 912 #define MPU_GICD_IPR2_PRIORITY_BYTEOFFSET_2_SHIFT                                                           (16U)
 913 #define MPU_GICD_IPR2_PRIORITY_BYTEOFFSET_2_MASK                                                            (0x00ff0000U)
 914
 915 #define MPU_GICD_IPR2_PRIORITY_BYTEOFFSET_1_SHIFT                                                           (8U)
 916 #define MPU_GICD_IPR2_PRIORITY_BYTEOFFSET_1_MASK                                                            (0x0000ff00U)
 917
 918 #define MPU_GICD_IPR2_PRIORITY_BYTEOFFSET_3_SHIFT                                                           (24U)
 919 #define MPU_GICD_IPR2_PRIORITY_BYTEOFFSET_3_MASK                                                            (0xff000000U)
 920
 921 #define MPU_GICD_IPR2_PRIORITY_BYTEOFFSET_0_SHIFT                                                           (0U)
 922 #define MPU_GICD_IPR2_PRIORITY_BYTEOFFSET_0_MASK                                                            (0x000000ffU)
 923
 924 #define MPU_GICD_IPR3_PRIORITY_BYTEOFFSET_2_SHIFT                                                           (16U)
 925 #define MPU_GICD_IPR3_PRIORITY_BYTEOFFSET_2_MASK                                                            (0x00ff0000U)
 926
 927 #define MPU_GICD_IPR3_PRIORITY_BYTEOFFSET_1_SHIFT                                                           (8U)
 928 #define MPU_GICD_IPR3_PRIORITY_BYTEOFFSET_1_MASK                                                            (0x0000ff00U)
 929
 930 #define MPU_GICD_IPR3_PRIORITY_BYTEOFFSET_3_SHIFT                                                           (24U)
 931 #define MPU_GICD_IPR3_PRIORITY_BYTEOFFSET_3_MASK                                                            (0xff000000U)
 932
 933 #define MPU_GICD_IPR3_PRIORITY_BYTEOFFSET_0_SHIFT                                                           (0U)
 934 #define MPU_GICD_IPR3_PRIORITY_BYTEOFFSET_0_MASK                                                            (0x000000ffU)
 935
 936 #define MPU_GICD_IPR4_RESERVED_SHIFT                                                                        (0U)
 937 #define MPU_GICD_IPR4_RESERVED_MASK                                                                         (0x000000ffU)
 938
 939 #define MPU_GICD_IPR4_RESERVED1_SHIFT                                                                       (8U)
 940 #define MPU_GICD_IPR4_RESERVED1_MASK                                                                        (0x0000ff00U)
 941
 942 #define MPU_GICD_IPR4_RESERVED2_SHIFT                                                                       (16U)
 943 #define MPU_GICD_IPR4_RESERVED2_MASK                                                                        (0x00ff0000U)
 944
 945 #define MPU_GICD_IPR4_RESERVED3_SHIFT                                                                       (24U)
 946 #define MPU_GICD_IPR4_RESERVED3_MASK                                                                        (0xff000000U)
 947
 948 #define MPU_GICD_IPR5_RESERVED_SHIFT                                                                        (0U)
 949 #define MPU_GICD_IPR5_RESERVED_MASK                                                                         (0x000000ffU)
 950
 951 #define MPU_GICD_IPR5_RESERVED1_SHIFT                                                                       (8U)
 952 #define MPU_GICD_IPR5_RESERVED1_MASK                                                                        (0x0000ff00U)
 953
 954 #define MPU_GICD_IPR5_RESERVED2_SHIFT                                                                       (16U)
 955 #define MPU_GICD_IPR5_RESERVED2_MASK                                                                        (0x00ff0000U)
 956
 957 #define MPU_GICD_IPR5_RESERVED3_SHIFT                                                                       (24U)
 958 #define MPU_GICD_IPR5_RESERVED3_MASK                                                                        (0xff000000U)
 959
 960 #define MPU_GICD_IPR6_PRIORITY_BYTEOFFSET_3_SHIFT                                                           (24U)
 961 #define MPU_GICD_IPR6_PRIORITY_BYTEOFFSET_3_MASK                                                            (0xff000000U)
 962
 963 #define MPU_GICD_IPR6_PRIORITY_BYTEOFFSET_2_SHIFT                                                           (16U)
 964 #define MPU_GICD_IPR6_PRIORITY_BYTEOFFSET_2_MASK                                                            (0x00ff0000U)
 965
 966 #define MPU_GICD_IPR6_PRIORITY_BYTEOFFSET_1_SHIFT                                                           (8U)
 967 #define MPU_GICD_IPR6_PRIORITY_BYTEOFFSET_1_MASK                                                            (0x0000ff00U)
 968
 969 #define MPU_GICD_IPR6_RESERVED1_SHIFT                                                                       (0U)
 970 #define MPU_GICD_IPR6_RESERVED1_MASK                                                                        (0x000000ffU)
 971
 972 #define MPU_GICD_IPR7_PRIORITY_BYTEOFFSET_2_SHIFT                                                           (16U)
 973 #define MPU_GICD_IPR7_PRIORITY_BYTEOFFSET_2_MASK                                                            (0x00ff0000U)
 974
 975 #define MPU_GICD_IPR7_PRIORITY_BYTEOFFSET_1_SHIFT                                                           (8U)
 976 #define MPU_GICD_IPR7_PRIORITY_BYTEOFFSET_1_MASK                                                            (0x0000ff00U)
 977
 978 #define MPU_GICD_IPR7_PRIORITY_BYTEOFFSET_3_SHIFT                                                           (24U)
 979 #define MPU_GICD_IPR7_PRIORITY_BYTEOFFSET_3_MASK                                                            (0xff000000U)
 980
 981 #define MPU_GICD_IPR7_PRIORITY_BYTEOFFSET_0_SHIFT                                                           (0U)
 982 #define MPU_GICD_IPR7_PRIORITY_BYTEOFFSET_0_MASK                                                            (0x000000ffU)
 983
 984 #define MPU_GICD_IPR8_PRIORITY_BYTEOFFSET_2_SHIFT                                                           (16U)
 985 #define MPU_GICD_IPR8_PRIORITY_BYTEOFFSET_2_MASK                                                            (0x00ff0000U)
 986
 987 #define MPU_GICD_IPR8_PRIORITY_BYTEOFFSET_1_SHIFT                                                           (8U)
 988 #define MPU_GICD_IPR8_PRIORITY_BYTEOFFSET_1_MASK                                                            (0x0000ff00U)
 989
 990 #define MPU_GICD_IPR8_PRIORITY_BYTEOFFSET_3_SHIFT                                                           (24U)
 991 #define MPU_GICD_IPR8_PRIORITY_BYTEOFFSET_3_MASK                                                            (0xff000000U)
 992
 993 #define MPU_GICD_IPR8_PRIORITY_BYTEOFFSET_0_SHIFT                                                           (0U)
 994 #define MPU_GICD_IPR8_PRIORITY_BYTEOFFSET_0_MASK                                                            (0x000000ffU)
 995
 996 #define MPU_GICD_IPR9_PRIORITY_BYTEOFFSET_2_SHIFT                                                           (16U)
 997 #define MPU_GICD_IPR9_PRIORITY_BYTEOFFSET_2_MASK                                                            (0x00ff0000U)
 998
 999 #define MPU_GICD_IPR9_PRIORITY_BYTEOFFSET_1_SHIFT                                                           (8U)
1000 #define MPU_GICD_IPR9_PRIORITY_BYTEOFFSET_1_MASK                                                            (0x0000ff00U)
1001
1002 #define MPU_GICD_IPR9_PRIORITY_BYTEOFFSET_3_SHIFT                                                           (24U)
1003 #define MPU_GICD_IPR9_PRIORITY_BYTEOFFSET_3_MASK                                                            (0xff000000U)
1004
1005 #define MPU_GICD_IPR9_PRIORITY_BYTEOFFSET_0_SHIFT                                                           (0U)
1006 #define MPU_GICD_IPR9_PRIORITY_BYTEOFFSET_0_MASK                                                            (0x000000ffU)
1007
1008 #define MPU_GICD_IPR10_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1009 #define MPU_GICD_IPR10_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1010
1011 #define MPU_GICD_IPR10_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1012 #define MPU_GICD_IPR10_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1013
1014 #define MPU_GICD_IPR10_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1015 #define MPU_GICD_IPR10_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1016
1017 #define MPU_GICD_IPR10_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1018 #define MPU_GICD_IPR10_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1019
1020 #define MPU_GICD_IPR11_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1021 #define MPU_GICD_IPR11_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1022
1023 #define MPU_GICD_IPR11_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1024 #define MPU_GICD_IPR11_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1025
1026 #define MPU_GICD_IPR11_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1027 #define MPU_GICD_IPR11_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1028
1029 #define MPU_GICD_IPR11_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1030 #define MPU_GICD_IPR11_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1031
1032 #define MPU_GICD_IPR12_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1033 #define MPU_GICD_IPR12_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1034
1035 #define MPU_GICD_IPR12_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1036 #define MPU_GICD_IPR12_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1037
1038 #define MPU_GICD_IPR12_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1039 #define MPU_GICD_IPR12_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1040
1041 #define MPU_GICD_IPR12_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1042 #define MPU_GICD_IPR12_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1043
1044 #define MPU_GICD_IPR13_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1045 #define MPU_GICD_IPR13_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1046
1047 #define MPU_GICD_IPR13_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1048 #define MPU_GICD_IPR13_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1049
1050 #define MPU_GICD_IPR13_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1051 #define MPU_GICD_IPR13_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1052
1053 #define MPU_GICD_IPR13_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1054 #define MPU_GICD_IPR13_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1055
1056 #define MPU_GICD_IPR14_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1057 #define MPU_GICD_IPR14_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1058
1059 #define MPU_GICD_IPR14_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1060 #define MPU_GICD_IPR14_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1061
1062 #define MPU_GICD_IPR14_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1063 #define MPU_GICD_IPR14_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1064
1065 #define MPU_GICD_IPR14_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1066 #define MPU_GICD_IPR14_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1067
1068 #define MPU_GICD_IPR15_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1069 #define MPU_GICD_IPR15_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1070
1071 #define MPU_GICD_IPR15_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1072 #define MPU_GICD_IPR15_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1073
1074 #define MPU_GICD_IPR15_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1075 #define MPU_GICD_IPR15_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1076
1077 #define MPU_GICD_IPR15_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1078 #define MPU_GICD_IPR15_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1079
1080 #define MPU_GICD_IPR16_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1081 #define MPU_GICD_IPR16_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1082
1083 #define MPU_GICD_IPR16_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1084 #define MPU_GICD_IPR16_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1085
1086 #define MPU_GICD_IPR16_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1087 #define MPU_GICD_IPR16_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1088
1089 #define MPU_GICD_IPR16_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1090 #define MPU_GICD_IPR16_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1091
1092 #define MPU_GICD_IPR17_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1093 #define MPU_GICD_IPR17_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1094
1095 #define MPU_GICD_IPR17_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1096 #define MPU_GICD_IPR17_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1097
1098 #define MPU_GICD_IPR17_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1099 #define MPU_GICD_IPR17_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1100
1101 #define MPU_GICD_IPR17_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1102 #define MPU_GICD_IPR17_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1103
1104 #define MPU_GICD_IPR18_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1105 #define MPU_GICD_IPR18_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1106
1107 #define MPU_GICD_IPR18_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1108 #define MPU_GICD_IPR18_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1109
1110 #define MPU_GICD_IPR18_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1111 #define MPU_GICD_IPR18_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1112
1113 #define MPU_GICD_IPR18_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1114 #define MPU_GICD_IPR18_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1115
1116 #define MPU_GICD_IPR19_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1117 #define MPU_GICD_IPR19_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1118
1119 #define MPU_GICD_IPR19_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1120 #define MPU_GICD_IPR19_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1121
1122 #define MPU_GICD_IPR19_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1123 #define MPU_GICD_IPR19_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1124
1125 #define MPU_GICD_IPR19_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1126 #define MPU_GICD_IPR19_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1127
1128 #define MPU_GICD_IPR20_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1129 #define MPU_GICD_IPR20_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1130
1131 #define MPU_GICD_IPR20_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1132 #define MPU_GICD_IPR20_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1133
1134 #define MPU_GICD_IPR20_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1135 #define MPU_GICD_IPR20_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1136
1137 #define MPU_GICD_IPR20_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1138 #define MPU_GICD_IPR20_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1139
1140 #define MPU_GICD_IPR21_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1141 #define MPU_GICD_IPR21_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1142
1143 #define MPU_GICD_IPR21_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1144 #define MPU_GICD_IPR21_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1145
1146 #define MPU_GICD_IPR21_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1147 #define MPU_GICD_IPR21_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1148
1149 #define MPU_GICD_IPR21_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1150 #define MPU_GICD_IPR21_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1151
1152 #define MPU_GICD_IPR22_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1153 #define MPU_GICD_IPR22_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1154
1155 #define MPU_GICD_IPR22_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1156 #define MPU_GICD_IPR22_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1157
1158 #define MPU_GICD_IPR22_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1159 #define MPU_GICD_IPR22_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1160
1161 #define MPU_GICD_IPR22_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1162 #define MPU_GICD_IPR22_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1163
1164 #define MPU_GICD_IPR23_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1165 #define MPU_GICD_IPR23_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1166
1167 #define MPU_GICD_IPR23_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1168 #define MPU_GICD_IPR23_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1169
1170 #define MPU_GICD_IPR23_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1171 #define MPU_GICD_IPR23_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1172
1173 #define MPU_GICD_IPR23_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1174 #define MPU_GICD_IPR23_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1175
1176 #define MPU_GICD_IPR24_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1177 #define MPU_GICD_IPR24_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1178
1179 #define MPU_GICD_IPR24_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1180 #define MPU_GICD_IPR24_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1181
1182 #define MPU_GICD_IPR24_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1183 #define MPU_GICD_IPR24_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1184
1185 #define MPU_GICD_IPR24_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1186 #define MPU_GICD_IPR24_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1187
1188 #define MPU_GICD_IPR25_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1189 #define MPU_GICD_IPR25_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1190
1191 #define MPU_GICD_IPR25_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1192 #define MPU_GICD_IPR25_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1193
1194 #define MPU_GICD_IPR25_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1195 #define MPU_GICD_IPR25_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1196
1197 #define MPU_GICD_IPR25_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1198 #define MPU_GICD_IPR25_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1199
1200 #define MPU_GICD_IPR26_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1201 #define MPU_GICD_IPR26_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1202
1203 #define MPU_GICD_IPR26_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1204 #define MPU_GICD_IPR26_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1205
1206 #define MPU_GICD_IPR26_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1207 #define MPU_GICD_IPR26_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1208
1209 #define MPU_GICD_IPR26_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1210 #define MPU_GICD_IPR26_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1211
1212 #define MPU_GICD_IPR27_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1213 #define MPU_GICD_IPR27_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1214
1215 #define MPU_GICD_IPR27_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1216 #define MPU_GICD_IPR27_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1217
1218 #define MPU_GICD_IPR27_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1219 #define MPU_GICD_IPR27_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1220
1221 #define MPU_GICD_IPR27_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1222 #define MPU_GICD_IPR27_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1223
1224 #define MPU_GICD_IPR28_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1225 #define MPU_GICD_IPR28_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1226
1227 #define MPU_GICD_IPR28_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1228 #define MPU_GICD_IPR28_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1229
1230 #define MPU_GICD_IPR28_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1231 #define MPU_GICD_IPR28_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1232
1233 #define MPU_GICD_IPR28_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1234 #define MPU_GICD_IPR28_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1235
1236 #define MPU_GICD_IPR29_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1237 #define MPU_GICD_IPR29_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1238
1239 #define MPU_GICD_IPR29_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1240 #define MPU_GICD_IPR29_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1241
1242 #define MPU_GICD_IPR29_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1243 #define MPU_GICD_IPR29_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1244
1245 #define MPU_GICD_IPR29_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1246 #define MPU_GICD_IPR29_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1247
1248 #define MPU_GICD_IPR30_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1249 #define MPU_GICD_IPR30_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1250
1251 #define MPU_GICD_IPR30_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1252 #define MPU_GICD_IPR30_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1253
1254 #define MPU_GICD_IPR30_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1255 #define MPU_GICD_IPR30_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1256
1257 #define MPU_GICD_IPR30_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1258 #define MPU_GICD_IPR30_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1259
1260 #define MPU_GICD_IPR31_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1261 #define MPU_GICD_IPR31_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1262
1263 #define MPU_GICD_IPR31_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1264 #define MPU_GICD_IPR31_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1265
1266 #define MPU_GICD_IPR31_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1267 #define MPU_GICD_IPR31_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1268
1269 #define MPU_GICD_IPR31_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1270 #define MPU_GICD_IPR31_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1271
1272 #define MPU_GICD_IPR32_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1273 #define MPU_GICD_IPR32_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1274
1275 #define MPU_GICD_IPR32_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1276 #define MPU_GICD_IPR32_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1277
1278 #define MPU_GICD_IPR32_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1279 #define MPU_GICD_IPR32_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1280
1281 #define MPU_GICD_IPR32_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1282 #define MPU_GICD_IPR32_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1283
1284 #define MPU_GICD_IPR33_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1285 #define MPU_GICD_IPR33_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1286
1287 #define MPU_GICD_IPR33_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1288 #define MPU_GICD_IPR33_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1289
1290 #define MPU_GICD_IPR33_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1291 #define MPU_GICD_IPR33_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1292
1293 #define MPU_GICD_IPR33_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1294 #define MPU_GICD_IPR33_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1295
1296 #define MPU_GICD_IPR34_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1297 #define MPU_GICD_IPR34_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1298
1299 #define MPU_GICD_IPR34_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1300 #define MPU_GICD_IPR34_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1301
1302 #define MPU_GICD_IPR34_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1303 #define MPU_GICD_IPR34_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1304
1305 #define MPU_GICD_IPR34_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1306 #define MPU_GICD_IPR34_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1307
1308 #define MPU_GICD_IPR35_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1309 #define MPU_GICD_IPR35_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1310
1311 #define MPU_GICD_IPR35_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1312 #define MPU_GICD_IPR35_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1313
1314 #define MPU_GICD_IPR35_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1315 #define MPU_GICD_IPR35_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1316
1317 #define MPU_GICD_IPR35_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1318 #define MPU_GICD_IPR35_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1319
1320 #define MPU_GICD_IPR36_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1321 #define MPU_GICD_IPR36_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1322
1323 #define MPU_GICD_IPR36_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1324 #define MPU_GICD_IPR36_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1325
1326 #define MPU_GICD_IPR36_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1327 #define MPU_GICD_IPR36_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1328
1329 #define MPU_GICD_IPR36_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1330 #define MPU_GICD_IPR36_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1331
1332 #define MPU_GICD_IPR37_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1333 #define MPU_GICD_IPR37_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1334
1335 #define MPU_GICD_IPR37_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1336 #define MPU_GICD_IPR37_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1337
1338 #define MPU_GICD_IPR37_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1339 #define MPU_GICD_IPR37_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1340
1341 #define MPU_GICD_IPR37_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1342 #define MPU_GICD_IPR37_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1343
1344 #define MPU_GICD_IPR38_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1345 #define MPU_GICD_IPR38_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1346
1347 #define MPU_GICD_IPR38_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1348 #define MPU_GICD_IPR38_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1349
1350 #define MPU_GICD_IPR38_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1351 #define MPU_GICD_IPR38_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1352
1353 #define MPU_GICD_IPR38_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1354 #define MPU_GICD_IPR38_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1355
1356 #define MPU_GICD_IPR39_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1357 #define MPU_GICD_IPR39_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1358
1359 #define MPU_GICD_IPR39_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1360 #define MPU_GICD_IPR39_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1361
1362 #define MPU_GICD_IPR39_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1363 #define MPU_GICD_IPR39_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1364
1365 #define MPU_GICD_IPR39_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1366 #define MPU_GICD_IPR39_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1367
1368 #define MPU_GICD_IPR40_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1369 #define MPU_GICD_IPR40_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1370
1371 #define MPU_GICD_IPR40_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1372 #define MPU_GICD_IPR40_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1373
1374 #define MPU_GICD_IPR40_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1375 #define MPU_GICD_IPR40_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1376
1377 #define MPU_GICD_IPR40_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1378 #define MPU_GICD_IPR40_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1379
1380 #define MPU_GICD_IPR41_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1381 #define MPU_GICD_IPR41_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1382
1383 #define MPU_GICD_IPR41_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1384 #define MPU_GICD_IPR41_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1385
1386 #define MPU_GICD_IPR41_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1387 #define MPU_GICD_IPR41_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1388
1389 #define MPU_GICD_IPR41_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1390 #define MPU_GICD_IPR41_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1391
1392 #define MPU_GICD_IPR42_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1393 #define MPU_GICD_IPR42_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1394
1395 #define MPU_GICD_IPR42_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1396 #define MPU_GICD_IPR42_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1397
1398 #define MPU_GICD_IPR42_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1399 #define MPU_GICD_IPR42_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1400
1401 #define MPU_GICD_IPR42_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1402 #define MPU_GICD_IPR42_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1403
1404 #define MPU_GICD_IPR43_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1405 #define MPU_GICD_IPR43_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1406
1407 #define MPU_GICD_IPR43_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1408 #define MPU_GICD_IPR43_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1409
1410 #define MPU_GICD_IPR43_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1411 #define MPU_GICD_IPR43_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1412
1413 #define MPU_GICD_IPR43_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1414 #define MPU_GICD_IPR43_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1415
1416 #define MPU_GICD_IPR44_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1417 #define MPU_GICD_IPR44_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1418
1419 #define MPU_GICD_IPR44_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1420 #define MPU_GICD_IPR44_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1421
1422 #define MPU_GICD_IPR44_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1423 #define MPU_GICD_IPR44_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1424
1425 #define MPU_GICD_IPR44_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1426 #define MPU_GICD_IPR44_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1427
1428 #define MPU_GICD_IPR45_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1429 #define MPU_GICD_IPR45_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1430
1431 #define MPU_GICD_IPR45_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1432 #define MPU_GICD_IPR45_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1433
1434 #define MPU_GICD_IPR45_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1435 #define MPU_GICD_IPR45_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1436
1437 #define MPU_GICD_IPR45_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1438 #define MPU_GICD_IPR45_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1439
1440 #define MPU_GICD_IPR46_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1441 #define MPU_GICD_IPR46_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1442
1443 #define MPU_GICD_IPR46_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1444 #define MPU_GICD_IPR46_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1445
1446 #define MPU_GICD_IPR46_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1447 #define MPU_GICD_IPR46_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1448
1449 #define MPU_GICD_IPR46_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1450 #define MPU_GICD_IPR46_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1451
1452 #define MPU_GICD_IPR47_PRIORITY_BYTEOFFSET_2_SHIFT                                                          (16U)
1453 #define MPU_GICD_IPR47_PRIORITY_BYTEOFFSET_2_MASK                                                           (0x00ff0000U)
1454
1455 #define MPU_GICD_IPR47_PRIORITY_BYTEOFFSET_1_SHIFT                                                          (8U)
1456 #define MPU_GICD_IPR47_PRIORITY_BYTEOFFSET_1_MASK                                                           (0x0000ff00U)
1457
1458 #define MPU_GICD_IPR47_PRIORITY_BYTEOFFSET_3_SHIFT                                                          (24U)
1459 #define MPU_GICD_IPR47_PRIORITY_BYTEOFFSET_3_MASK                                                           (0xff000000U)
1460
1461 #define MPU_GICD_IPR47_PRIORITY_BYTEOFFSET_0_SHIFT                                                          (0U)
1462 #define MPU_GICD_IPR47_PRIORITY_BYTEOFFSET_0_MASK                                                           (0x000000ffU)
1463
1464 #define MPU_GICD_IPTR0_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                        (0U)
1465 #define MPU_GICD_IPTR0_CPUTARGETS_BYTEOFFSET_0_MASK                                                         (0x000000ffU)
1466
1467 #define MPU_GICD_IPTR0_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                        (8U)
1468 #define MPU_GICD_IPTR0_CPUTARGETS_BYTEOFFSET_1_MASK                                                         (0x0000ff00U)
1469
1470 #define MPU_GICD_IPTR0_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                        (16U)
1471 #define MPU_GICD_IPTR0_CPUTARGETS_BYTEOFFSET_2_MASK                                                         (0x00ff0000U)
1472
1473 #define MPU_GICD_IPTR0_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                        (24U)
1474 #define MPU_GICD_IPTR0_CPUTARGETS_BYTEOFFSET_3_MASK                                                         (0xff000000U)
1475
1476 #define MPU_GICD_IPTR1_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                        (0U)
1477 #define MPU_GICD_IPTR1_CPUTARGETS_BYTEOFFSET_0_MASK                                                         (0x000000ffU)
1478
1479 #define MPU_GICD_IPTR1_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                        (8U)
1480 #define MPU_GICD_IPTR1_CPUTARGETS_BYTEOFFSET_1_MASK                                                         (0x0000ff00U)
1481
1482 #define MPU_GICD_IPTR1_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                        (16U)
1483 #define MPU_GICD_IPTR1_CPUTARGETS_BYTEOFFSET_2_MASK                                                         (0x00ff0000U)
1484
1485 #define MPU_GICD_IPTR1_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                        (24U)
1486 #define MPU_GICD_IPTR1_CPUTARGETS_BYTEOFFSET_3_MASK                                                         (0xff000000U)
1487
1488 #define MPU_GICD_IPTR2_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                        (0U)
1489 #define MPU_GICD_IPTR2_CPUTARGETS_BYTEOFFSET_0_MASK                                                         (0x000000ffU)
1490
1491 #define MPU_GICD_IPTR2_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                        (8U)
1492 #define MPU_GICD_IPTR2_CPUTARGETS_BYTEOFFSET_1_MASK                                                         (0x0000ff00U)
1493
1494 #define MPU_GICD_IPTR2_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                        (16U)
1495 #define MPU_GICD_IPTR2_CPUTARGETS_BYTEOFFSET_2_MASK                                                         (0x00ff0000U)
1496
1497 #define MPU_GICD_IPTR2_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                        (24U)
1498 #define MPU_GICD_IPTR2_CPUTARGETS_BYTEOFFSET_3_MASK                                                         (0xff000000U)
1499
1500 #define MPU_GICD_IPTR3_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                        (0U)
1501 #define MPU_GICD_IPTR3_CPUTARGETS_BYTEOFFSET_0_MASK                                                         (0x000000ffU)
1502
1503 #define MPU_GICD_IPTR3_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                        (8U)
1504 #define MPU_GICD_IPTR3_CPUTARGETS_BYTEOFFSET_1_MASK                                                         (0x0000ff00U)
1505
1506 #define MPU_GICD_IPTR3_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                        (16U)
1507 #define MPU_GICD_IPTR3_CPUTARGETS_BYTEOFFSET_2_MASK                                                         (0x00ff0000U)
1508
1509 #define MPU_GICD_IPTR3_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                        (24U)
1510 #define MPU_GICD_IPTR3_CPUTARGETS_BYTEOFFSET_3_MASK                                                         (0xff000000U)
1511
1512 #define MPU_GICD_IPTR4_RESERVED_SHIFT                                                                       (0U)
1513 #define MPU_GICD_IPTR4_RESERVED_MASK                                                                        (0x000000ffU)
1514
1515 #define MPU_GICD_IPTR4_RESERVED1_SHIFT                                                                      (8U)
1516 #define MPU_GICD_IPTR4_RESERVED1_MASK                                                                       (0x0000ff00U)
1517
1518 #define MPU_GICD_IPTR4_RESERVED2_SHIFT                                                                      (16U)
1519 #define MPU_GICD_IPTR4_RESERVED2_MASK                                                                       (0x00ff0000U)
1520
1521 #define MPU_GICD_IPTR4_RESERVED3_SHIFT                                                                      (24U)
1522 #define MPU_GICD_IPTR4_RESERVED3_MASK                                                                       (0xff000000U)
1523
1524 #define MPU_GICD_IPTR5_RESERVED_SHIFT                                                                       (0U)
1525 #define MPU_GICD_IPTR5_RESERVED_MASK                                                                        (0x000000ffU)
1526
1527 #define MPU_GICD_IPTR5_RESERVED1_SHIFT                                                                      (8U)
1528 #define MPU_GICD_IPTR5_RESERVED1_MASK                                                                       (0x0000ff00U)
1529
1530 #define MPU_GICD_IPTR5_RESERVED2_SHIFT                                                                      (16U)
1531 #define MPU_GICD_IPTR5_RESERVED2_MASK                                                                       (0x00ff0000U)
1532
1533 #define MPU_GICD_IPTR5_RESERVED3_SHIFT                                                                      (24U)
1534 #define MPU_GICD_IPTR5_RESERVED3_MASK                                                                       (0xff000000U)
1535
1536 #define MPU_GICD_IPTR6_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                        (24U)
1537 #define MPU_GICD_IPTR6_CPUTARGETS_BYTEOFFSET_3_MASK                                                         (0xff000000U)
1538
1539 #define MPU_GICD_IPTR6_RESERVED_SHIFT                                                                       (0U)
1540 #define MPU_GICD_IPTR6_RESERVED_MASK                                                                        (0x000000ffU)
1541
1542 #define MPU_GICD_IPTR6_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                        (16U)
1543 #define MPU_GICD_IPTR6_CPUTARGETS_BYTEOFFSET_2_MASK                                                         (0x00ff0000U)
1544
1545 #define MPU_GICD_IPTR6_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                        (8U)
1546 #define MPU_GICD_IPTR6_CPUTARGETS_BYTEOFFSET_1_MASK                                                         (0x0000ff00U)
1547
1548 #define MPU_GICD_IPTR7_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                        (0U)
1549 #define MPU_GICD_IPTR7_CPUTARGETS_BYTEOFFSET_0_MASK                                                         (0x000000ffU)
1550
1551 #define MPU_GICD_IPTR7_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                        (8U)
1552 #define MPU_GICD_IPTR7_CPUTARGETS_BYTEOFFSET_1_MASK                                                         (0x0000ff00U)
1553
1554 #define MPU_GICD_IPTR7_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                        (16U)
1555 #define MPU_GICD_IPTR7_CPUTARGETS_BYTEOFFSET_2_MASK                                                         (0x00ff0000U)
1556
1557 #define MPU_GICD_IPTR7_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                        (24U)
1558 #define MPU_GICD_IPTR7_CPUTARGETS_BYTEOFFSET_3_MASK                                                         (0xff000000U)
1559
1560 #define MPU_GICD_IPTR8_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                        (0U)
1561 #define MPU_GICD_IPTR8_CPUTARGETS_BYTEOFFSET_0_MASK                                                         (0x000000ffU)
1562
1563 #define MPU_GICD_IPTR8_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                        (8U)
1564 #define MPU_GICD_IPTR8_CPUTARGETS_BYTEOFFSET_1_MASK                                                         (0x0000ff00U)
1565
1566 #define MPU_GICD_IPTR8_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                        (16U)
1567 #define MPU_GICD_IPTR8_CPUTARGETS_BYTEOFFSET_2_MASK                                                         (0x00ff0000U)
1568
1569 #define MPU_GICD_IPTR8_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                        (24U)
1570 #define MPU_GICD_IPTR8_CPUTARGETS_BYTEOFFSET_3_MASK                                                         (0xff000000U)
1571
1572 #define MPU_GICD_IPTR9_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                        (0U)
1573 #define MPU_GICD_IPTR9_CPUTARGETS_BYTEOFFSET_0_MASK                                                         (0x000000ffU)
1574
1575 #define MPU_GICD_IPTR9_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                        (8U)
1576 #define MPU_GICD_IPTR9_CPUTARGETS_BYTEOFFSET_1_MASK                                                         (0x0000ff00U)
1577
1578 #define MPU_GICD_IPTR9_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                        (16U)
1579 #define MPU_GICD_IPTR9_CPUTARGETS_BYTEOFFSET_2_MASK                                                         (0x00ff0000U)
1580
1581 #define MPU_GICD_IPTR9_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                        (24U)
1582 #define MPU_GICD_IPTR9_CPUTARGETS_BYTEOFFSET_3_MASK                                                         (0xff000000U)
1583
1584 #define MPU_GICD_IPTR10_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1585 #define MPU_GICD_IPTR10_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1586
1587 #define MPU_GICD_IPTR10_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1588 #define MPU_GICD_IPTR10_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1589
1590 #define MPU_GICD_IPTR10_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1591 #define MPU_GICD_IPTR10_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1592
1593 #define MPU_GICD_IPTR10_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1594 #define MPU_GICD_IPTR10_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1595
1596 #define MPU_GICD_IPTR11_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1597 #define MPU_GICD_IPTR11_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1598
1599 #define MPU_GICD_IPTR11_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1600 #define MPU_GICD_IPTR11_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1601
1602 #define MPU_GICD_IPTR11_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1603 #define MPU_GICD_IPTR11_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1604
1605 #define MPU_GICD_IPTR11_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1606 #define MPU_GICD_IPTR11_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1607
1608 #define MPU_GICD_IPTR12_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1609 #define MPU_GICD_IPTR12_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1610
1611 #define MPU_GICD_IPTR12_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1612 #define MPU_GICD_IPTR12_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1613
1614 #define MPU_GICD_IPTR12_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1615 #define MPU_GICD_IPTR12_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1616
1617 #define MPU_GICD_IPTR12_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1618 #define MPU_GICD_IPTR12_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1619
1620 #define MPU_GICD_IPTR13_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1621 #define MPU_GICD_IPTR13_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1622
1623 #define MPU_GICD_IPTR13_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1624 #define MPU_GICD_IPTR13_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1625
1626 #define MPU_GICD_IPTR13_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1627 #define MPU_GICD_IPTR13_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1628
1629 #define MPU_GICD_IPTR13_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1630 #define MPU_GICD_IPTR13_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1631
1632 #define MPU_GICD_IPTR14_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1633 #define MPU_GICD_IPTR14_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1634
1635 #define MPU_GICD_IPTR14_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1636 #define MPU_GICD_IPTR14_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1637
1638 #define MPU_GICD_IPTR14_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1639 #define MPU_GICD_IPTR14_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1640
1641 #define MPU_GICD_IPTR14_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1642 #define MPU_GICD_IPTR14_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1643
1644 #define MPU_GICD_IPTR15_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1645 #define MPU_GICD_IPTR15_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1646
1647 #define MPU_GICD_IPTR15_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1648 #define MPU_GICD_IPTR15_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1649
1650 #define MPU_GICD_IPTR15_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1651 #define MPU_GICD_IPTR15_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1652
1653 #define MPU_GICD_IPTR15_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1654 #define MPU_GICD_IPTR15_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1655
1656 #define MPU_GICD_IPTR16_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1657 #define MPU_GICD_IPTR16_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1658
1659 #define MPU_GICD_IPTR16_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1660 #define MPU_GICD_IPTR16_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1661
1662 #define MPU_GICD_IPTR16_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1663 #define MPU_GICD_IPTR16_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1664
1665 #define MPU_GICD_IPTR16_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1666 #define MPU_GICD_IPTR16_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1667
1668 #define MPU_GICD_IPTR17_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1669 #define MPU_GICD_IPTR17_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1670
1671 #define MPU_GICD_IPTR17_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1672 #define MPU_GICD_IPTR17_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1673
1674 #define MPU_GICD_IPTR17_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1675 #define MPU_GICD_IPTR17_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1676
1677 #define MPU_GICD_IPTR17_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1678 #define MPU_GICD_IPTR17_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1679
1680 #define MPU_GICD_IPTR18_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1681 #define MPU_GICD_IPTR18_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1682
1683 #define MPU_GICD_IPTR18_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1684 #define MPU_GICD_IPTR18_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1685
1686 #define MPU_GICD_IPTR18_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1687 #define MPU_GICD_IPTR18_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1688
1689 #define MPU_GICD_IPTR18_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1690 #define MPU_GICD_IPTR18_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1691
1692 #define MPU_GICD_IPTR19_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1693 #define MPU_GICD_IPTR19_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1694
1695 #define MPU_GICD_IPTR19_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1696 #define MPU_GICD_IPTR19_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1697
1698 #define MPU_GICD_IPTR19_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1699 #define MPU_GICD_IPTR19_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1700
1701 #define MPU_GICD_IPTR19_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1702 #define MPU_GICD_IPTR19_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1703
1704 #define MPU_GICD_IPTR20_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1705 #define MPU_GICD_IPTR20_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1706
1707 #define MPU_GICD_IPTR20_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1708 #define MPU_GICD_IPTR20_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1709
1710 #define MPU_GICD_IPTR20_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1711 #define MPU_GICD_IPTR20_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1712
1713 #define MPU_GICD_IPTR20_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1714 #define MPU_GICD_IPTR20_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1715
1716 #define MPU_GICD_IPTR21_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1717 #define MPU_GICD_IPTR21_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1718
1719 #define MPU_GICD_IPTR21_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1720 #define MPU_GICD_IPTR21_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1721
1722 #define MPU_GICD_IPTR21_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1723 #define MPU_GICD_IPTR21_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1724
1725 #define MPU_GICD_IPTR21_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1726 #define MPU_GICD_IPTR21_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1727
1728 #define MPU_GICD_IPTR22_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1729 #define MPU_GICD_IPTR22_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1730
1731 #define MPU_GICD_IPTR22_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1732 #define MPU_GICD_IPTR22_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1733
1734 #define MPU_GICD_IPTR22_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1735 #define MPU_GICD_IPTR22_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1736
1737 #define MPU_GICD_IPTR22_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1738 #define MPU_GICD_IPTR22_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1739
1740 #define MPU_GICD_IPTR23_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1741 #define MPU_GICD_IPTR23_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1742
1743 #define MPU_GICD_IPTR23_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1744 #define MPU_GICD_IPTR23_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1745
1746 #define MPU_GICD_IPTR23_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1747 #define MPU_GICD_IPTR23_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1748
1749 #define MPU_GICD_IPTR23_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1750 #define MPU_GICD_IPTR23_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1751
1752 #define MPU_GICD_IPTR24_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1753 #define MPU_GICD_IPTR24_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1754
1755 #define MPU_GICD_IPTR24_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1756 #define MPU_GICD_IPTR24_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1757
1758 #define MPU_GICD_IPTR24_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1759 #define MPU_GICD_IPTR24_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1760
1761 #define MPU_GICD_IPTR24_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1762 #define MPU_GICD_IPTR24_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1763
1764 #define MPU_GICD_IPTR25_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1765 #define MPU_GICD_IPTR25_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1766
1767 #define MPU_GICD_IPTR25_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1768 #define MPU_GICD_IPTR25_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1769
1770 #define MPU_GICD_IPTR25_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1771 #define MPU_GICD_IPTR25_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1772
1773 #define MPU_GICD_IPTR25_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1774 #define MPU_GICD_IPTR25_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1775
1776 #define MPU_GICD_IPTR26_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1777 #define MPU_GICD_IPTR26_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1778
1779 #define MPU_GICD_IPTR26_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1780 #define MPU_GICD_IPTR26_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1781
1782 #define MPU_GICD_IPTR26_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1783 #define MPU_GICD_IPTR26_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1784
1785 #define MPU_GICD_IPTR26_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1786 #define MPU_GICD_IPTR26_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1787
1788 #define MPU_GICD_IPTR27_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1789 #define MPU_GICD_IPTR27_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1790
1791 #define MPU_GICD_IPTR27_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1792 #define MPU_GICD_IPTR27_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1793
1794 #define MPU_GICD_IPTR27_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1795 #define MPU_GICD_IPTR27_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1796
1797 #define MPU_GICD_IPTR27_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1798 #define MPU_GICD_IPTR27_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1799
1800 #define MPU_GICD_IPTR28_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1801 #define MPU_GICD_IPTR28_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1802
1803 #define MPU_GICD_IPTR28_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1804 #define MPU_GICD_IPTR28_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1805
1806 #define MPU_GICD_IPTR28_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1807 #define MPU_GICD_IPTR28_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1808
1809 #define MPU_GICD_IPTR28_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1810 #define MPU_GICD_IPTR28_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1811
1812 #define MPU_GICD_IPTR29_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1813 #define MPU_GICD_IPTR29_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1814
1815 #define MPU_GICD_IPTR29_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1816 #define MPU_GICD_IPTR29_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1817
1818 #define MPU_GICD_IPTR29_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1819 #define MPU_GICD_IPTR29_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1820
1821 #define MPU_GICD_IPTR29_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1822 #define MPU_GICD_IPTR29_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1823
1824 #define MPU_GICD_IPTR30_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1825 #define MPU_GICD_IPTR30_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1826
1827 #define MPU_GICD_IPTR30_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1828 #define MPU_GICD_IPTR30_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1829
1830 #define MPU_GICD_IPTR30_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1831 #define MPU_GICD_IPTR30_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1832
1833 #define MPU_GICD_IPTR30_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1834 #define MPU_GICD_IPTR30_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1835
1836 #define MPU_GICD_IPTR31_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1837 #define MPU_GICD_IPTR31_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1838
1839 #define MPU_GICD_IPTR31_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1840 #define MPU_GICD_IPTR31_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1841
1842 #define MPU_GICD_IPTR31_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1843 #define MPU_GICD_IPTR31_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1844
1845 #define MPU_GICD_IPTR31_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1846 #define MPU_GICD_IPTR31_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1847
1848 #define MPU_GICD_IPTR32_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1849 #define MPU_GICD_IPTR32_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1850
1851 #define MPU_GICD_IPTR32_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1852 #define MPU_GICD_IPTR32_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1853
1854 #define MPU_GICD_IPTR32_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1855 #define MPU_GICD_IPTR32_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1856
1857 #define MPU_GICD_IPTR32_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1858 #define MPU_GICD_IPTR32_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1859
1860 #define MPU_GICD_IPTR33_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1861 #define MPU_GICD_IPTR33_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1862
1863 #define MPU_GICD_IPTR33_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1864 #define MPU_GICD_IPTR33_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1865
1866 #define MPU_GICD_IPTR33_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1867 #define MPU_GICD_IPTR33_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1868
1869 #define MPU_GICD_IPTR33_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1870 #define MPU_GICD_IPTR33_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1871
1872 #define MPU_GICD_IPTR34_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1873 #define MPU_GICD_IPTR34_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1874
1875 #define MPU_GICD_IPTR34_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1876 #define MPU_GICD_IPTR34_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1877
1878 #define MPU_GICD_IPTR34_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1879 #define MPU_GICD_IPTR34_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1880
1881 #define MPU_GICD_IPTR34_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1882 #define MPU_GICD_IPTR34_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1883
1884 #define MPU_GICD_IPTR35_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1885 #define MPU_GICD_IPTR35_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1886
1887 #define MPU_GICD_IPTR35_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1888 #define MPU_GICD_IPTR35_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1889
1890 #define MPU_GICD_IPTR35_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1891 #define MPU_GICD_IPTR35_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1892
1893 #define MPU_GICD_IPTR35_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1894 #define MPU_GICD_IPTR35_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1895
1896 #define MPU_GICD_IPTR36_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1897 #define MPU_GICD_IPTR36_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1898
1899 #define MPU_GICD_IPTR36_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1900 #define MPU_GICD_IPTR36_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1901
1902 #define MPU_GICD_IPTR36_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1903 #define MPU_GICD_IPTR36_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1904
1905 #define MPU_GICD_IPTR36_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1906 #define MPU_GICD_IPTR36_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1907
1908 #define MPU_GICD_IPTR37_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1909 #define MPU_GICD_IPTR37_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1910
1911 #define MPU_GICD_IPTR37_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1912 #define MPU_GICD_IPTR37_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1913
1914 #define MPU_GICD_IPTR37_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1915 #define MPU_GICD_IPTR37_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1916
1917 #define MPU_GICD_IPTR37_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1918 #define MPU_GICD_IPTR37_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1919
1920 #define MPU_GICD_IPTR38_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1921 #define MPU_GICD_IPTR38_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1922
1923 #define MPU_GICD_IPTR38_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1924 #define MPU_GICD_IPTR38_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1925
1926 #define MPU_GICD_IPTR38_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1927 #define MPU_GICD_IPTR38_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1928
1929 #define MPU_GICD_IPTR38_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1930 #define MPU_GICD_IPTR38_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1931
1932 #define MPU_GICD_IPTR39_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1933 #define MPU_GICD_IPTR39_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1934
1935 #define MPU_GICD_IPTR39_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1936 #define MPU_GICD_IPTR39_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1937
1938 #define MPU_GICD_IPTR39_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1939 #define MPU_GICD_IPTR39_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1940
1941 #define MPU_GICD_IPTR39_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1942 #define MPU_GICD_IPTR39_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1943
1944 #define MPU_GICD_IPTR40_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1945 #define MPU_GICD_IPTR40_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1946
1947 #define MPU_GICD_IPTR40_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1948 #define MPU_GICD_IPTR40_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1949
1950 #define MPU_GICD_IPTR40_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1951 #define MPU_GICD_IPTR40_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1952
1953 #define MPU_GICD_IPTR40_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1954 #define MPU_GICD_IPTR40_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1955
1956 #define MPU_GICD_IPTR41_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1957 #define MPU_GICD_IPTR41_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1958
1959 #define MPU_GICD_IPTR41_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1960 #define MPU_GICD_IPTR41_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1961
1962 #define MPU_GICD_IPTR41_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1963 #define MPU_GICD_IPTR41_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1964
1965 #define MPU_GICD_IPTR41_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1966 #define MPU_GICD_IPTR41_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1967
1968 #define MPU_GICD_IPTR42_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1969 #define MPU_GICD_IPTR42_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1970
1971 #define MPU_GICD_IPTR42_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1972 #define MPU_GICD_IPTR42_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1973
1974 #define MPU_GICD_IPTR42_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1975 #define MPU_GICD_IPTR42_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1976
1977 #define MPU_GICD_IPTR42_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1978 #define MPU_GICD_IPTR42_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1979
1980 #define MPU_GICD_IPTR43_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1981 #define MPU_GICD_IPTR43_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1982
1983 #define MPU_GICD_IPTR43_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1984 #define MPU_GICD_IPTR43_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1985
1986 #define MPU_GICD_IPTR43_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1987 #define MPU_GICD_IPTR43_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
1988
1989 #define MPU_GICD_IPTR43_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
1990 #define MPU_GICD_IPTR43_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
1991
1992 #define MPU_GICD_IPTR44_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
1993 #define MPU_GICD_IPTR44_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
1994
1995 #define MPU_GICD_IPTR44_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
1996 #define MPU_GICD_IPTR44_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
1997
1998 #define MPU_GICD_IPTR44_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
1999 #define MPU_GICD_IPTR44_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
2000
2001 #define MPU_GICD_IPTR44_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
2002 #define MPU_GICD_IPTR44_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
2003
2004 #define MPU_GICD_IPTR45_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
2005 #define MPU_GICD_IPTR45_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
2006
2007 #define MPU_GICD_IPTR45_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
2008 #define MPU_GICD_IPTR45_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
2009
2010 #define MPU_GICD_IPTR45_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
2011 #define MPU_GICD_IPTR45_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
2012
2013 #define MPU_GICD_IPTR45_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
2014 #define MPU_GICD_IPTR45_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
2015
2016 #define MPU_GICD_IPTR46_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
2017 #define MPU_GICD_IPTR46_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
2018
2019 #define MPU_GICD_IPTR46_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
2020 #define MPU_GICD_IPTR46_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
2021
2022 #define MPU_GICD_IPTR46_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
2023 #define MPU_GICD_IPTR46_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
2024
2025 #define MPU_GICD_IPTR46_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
2026 #define MPU_GICD_IPTR46_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
2027
2028 #define MPU_GICD_IPTR47_CPUTARGETS_BYTEOFFSET_0_SHIFT                                                       (0U)
2029 #define MPU_GICD_IPTR47_CPUTARGETS_BYTEOFFSET_0_MASK                                                        (0x000000ffU)
2030
2031 #define MPU_GICD_IPTR47_CPUTARGETS_BYTEOFFSET_1_SHIFT                                                       (8U)
2032 #define MPU_GICD_IPTR47_CPUTARGETS_BYTEOFFSET_1_MASK                                                        (0x0000ff00U)
2033
2034 #define MPU_GICD_IPTR47_CPUTARGETS_BYTEOFFSET_2_SHIFT                                                       (16U)
2035 #define MPU_GICD_IPTR47_CPUTARGETS_BYTEOFFSET_2_MASK                                                        (0x00ff0000U)
2036
2037 #define MPU_GICD_IPTR47_CPUTARGETS_BYTEOFFSET_3_SHIFT                                                       (24U)
2038 #define MPU_GICD_IPTR47_CPUTARGETS_BYTEOFFSET_3_MASK                                                        (0xff000000U)
2039
2040 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2041 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2042
2043 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2044 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2045
2046 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2047 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2048
2049 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2050 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2051
2052 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2053 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2054
2055 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2056 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2057
2058 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2059 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2060
2061 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2062 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2063
2064 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2065 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2066
2067 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2068 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2069
2070 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2071 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2072
2073 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2074 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2075
2076 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2077 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2078
2079 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2080 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2081
2082 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2083 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2084
2085 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2086 #define MPU_GICD_ICFR0_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2087
2088 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2089 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2090
2091 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2092 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2093
2094 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2095 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2096
2097 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2098 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2099
2100 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2101 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2102
2103 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2104 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2105
2106 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2107 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2108
2109 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2110 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2111
2112 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2113 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2114
2115 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2116 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2117
2118 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2119 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2120
2121 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2122 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2123
2124 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2125 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2126
2127 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2128 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2129
2130 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2131 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2132
2133 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2134 #define MPU_GICD_ICFR1_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2135
2136 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2137 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2138
2139 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2140 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2141
2142 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2143 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2144
2145 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2146 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2147
2148 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2149 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2150
2151 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2152 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2153
2154 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2155 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2156
2157 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2158 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2159
2160 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2161 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2162
2163 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2164 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2165
2166 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2167 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2168
2169 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2170 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2171
2172 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2173 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2174
2175 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2176 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2177
2178 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2179 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2180
2181 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2182 #define MPU_GICD_ICFR2_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2183
2184 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2185 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2186
2187 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2188 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2189
2190 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2191 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2192
2193 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2194 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2195
2196 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2197 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2198
2199 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2200 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2201
2202 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2203 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2204
2205 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2206 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2207
2208 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2209 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2210
2211 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2212 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2213
2214 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2215 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2216
2217 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2218 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2219
2220 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2221 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2222
2223 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2224 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2225
2226 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2227 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2228
2229 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2230 #define MPU_GICD_ICFR3_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2231
2232 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2233 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2234
2235 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2236 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2237
2238 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2239 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2240
2241 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2242 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2243
2244 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2245 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2246
2247 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2248 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2249
2250 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2251 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2252
2253 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2254 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2255
2256 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2257 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2258
2259 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2260 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2261
2262 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2263 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2264
2265 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2266 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2267
2268 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2269 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2270
2271 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2272 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2273
2274 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2275 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2276
2277 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2278 #define MPU_GICD_ICFR4_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2279
2280 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2281 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2282
2283 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2284 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2285
2286 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2287 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2288
2289 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2290 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2291
2292 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2293 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2294
2295 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2296 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2297
2298 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2299 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2300
2301 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2302 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2303
2304 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2305 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2306
2307 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2308 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2309
2310 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2311 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2312
2313 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2314 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2315
2316 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2317 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2318
2319 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2320 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2321
2322 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2323 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2324
2325 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2326 #define MPU_GICD_ICFR5_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2327
2328 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2329 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2330
2331 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2332 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2333
2334 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2335 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2336
2337 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2338 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2339
2340 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2341 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2342
2343 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2344 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2345
2346 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2347 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2348
2349 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2350 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2351
2352 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2353 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2354
2355 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2356 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2357
2358 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2359 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2360
2361 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2362 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2363
2364 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2365 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2366
2367 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2368 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2369
2370 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2371 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2372
2373 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2374 #define MPU_GICD_ICFR6_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2375
2376 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2377 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2378
2379 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2380 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2381
2382 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2383 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2384
2385 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2386 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2387
2388 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2389 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2390
2391 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2392 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2393
2394 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2395 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2396
2397 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2398 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2399
2400 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2401 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2402
2403 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2404 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2405
2406 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2407 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2408
2409 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2410 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2411
2412 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2413 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2414
2415 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2416 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2417
2418 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2419 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2420
2421 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2422 #define MPU_GICD_ICFR7_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2423
2424 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2425 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2426
2427 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2428 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2429
2430 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2431 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2432
2433 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2434 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2435
2436 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2437 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2438
2439 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2440 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2441
2442 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2443 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2444
2445 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2446 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2447
2448 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2449 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2450
2451 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2452 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2453
2454 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2455 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2456
2457 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2458 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2459
2460 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2461 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2462
2463 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2464 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2465
2466 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2467 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2468
2469 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2470 #define MPU_GICD_ICFR8_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2471
2472 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_0_SHIFT                                                             (0U)
2473 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_0_MASK                                                              (0x00000003U)
2474
2475 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_1_SHIFT                                                             (2U)
2476 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_1_MASK                                                              (0x0000000cU)
2477
2478 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_2_SHIFT                                                             (4U)
2479 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_2_MASK                                                              (0x00000030U)
2480
2481 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_3_SHIFT                                                             (6U)
2482 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_3_MASK                                                              (0x000000c0U)
2483
2484 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_4_SHIFT                                                             (8U)
2485 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_4_MASK                                                              (0x00000300U)
2486
2487 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_5_SHIFT                                                             (10U)
2488 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_5_MASK                                                              (0x00000c00U)
2489
2490 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_6_SHIFT                                                             (12U)
2491 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_6_MASK                                                              (0x00003000U)
2492
2493 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_7_SHIFT                                                             (14U)
2494 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_7_MASK                                                              (0x0000c000U)
2495
2496 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_8_SHIFT                                                             (16U)
2497 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_8_MASK                                                              (0x00030000U)
2498
2499 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_9_SHIFT                                                             (18U)
2500 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_9_MASK                                                              (0x000c0000U)
2501
2502 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_10_SHIFT                                                            (20U)
2503 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_10_MASK                                                             (0x00300000U)
2504
2505 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_11_SHIFT                                                            (22U)
2506 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_11_MASK                                                             (0x00c00000U)
2507
2508 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_12_SHIFT                                                            (24U)
2509 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_12_MASK                                                             (0x03000000U)
2510
2511 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_13_SHIFT                                                            (26U)
2512 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_13_MASK                                                             (0x0c000000U)
2513
2514 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_14_SHIFT                                                            (28U)
2515 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_14_MASK                                                             (0x30000000U)
2516
2517 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_15_SHIFT                                                            (30U)
2518 #define MPU_GICD_ICFR9_INT_CONFIG_FIELD_15_MASK                                                             (0xc0000000U)
2519
2520 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_0_SHIFT                                                            (0U)
2521 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_0_MASK                                                             (0x00000003U)
2522
2523 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_1_SHIFT                                                            (2U)
2524 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_1_MASK                                                             (0x0000000cU)
2525
2526 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_2_SHIFT                                                            (4U)
2527 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_2_MASK                                                             (0x00000030U)
2528
2529 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_3_SHIFT                                                            (6U)
2530 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_3_MASK                                                             (0x000000c0U)
2531
2532 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_4_SHIFT                                                            (8U)
2533 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_4_MASK                                                             (0x00000300U)
2534
2535 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_5_SHIFT                                                            (10U)
2536 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_5_MASK                                                             (0x00000c00U)
2537
2538 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_6_SHIFT                                                            (12U)
2539 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_6_MASK                                                             (0x00003000U)
2540
2541 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_7_SHIFT                                                            (14U)
2542 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_7_MASK                                                             (0x0000c000U)
2543
2544 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_8_SHIFT                                                            (16U)
2545 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_8_MASK                                                             (0x00030000U)
2546
2547 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_9_SHIFT                                                            (18U)
2548 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_9_MASK                                                             (0x000c0000U)
2549
2550 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_10_SHIFT                                                           (20U)
2551 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_10_MASK                                                            (0x00300000U)
2552
2553 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_11_SHIFT                                                           (22U)
2554 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_11_MASK                                                            (0x00c00000U)
2555
2556 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_12_SHIFT                                                           (24U)
2557 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_12_MASK                                                            (0x03000000U)
2558
2559 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_13_SHIFT                                                           (26U)
2560 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_13_MASK                                                            (0x0c000000U)
2561
2562 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_14_SHIFT                                                           (28U)
2563 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_14_MASK                                                            (0x30000000U)
2564
2565 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_15_SHIFT                                                           (30U)
2566 #define MPU_GICD_ICFR10_INT_CONFIG_FIELD_15_MASK                                                            (0xc0000000U)
2567
2568 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_0_SHIFT                                                            (0U)
2569 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_0_MASK                                                             (0x00000003U)
2570
2571 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_1_SHIFT                                                            (2U)
2572 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_1_MASK                                                             (0x0000000cU)
2573
2574 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_2_SHIFT                                                            (4U)
2575 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_2_MASK                                                             (0x00000030U)
2576
2577 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_3_SHIFT                                                            (6U)
2578 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_3_MASK                                                             (0x000000c0U)
2579
2580 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_4_SHIFT                                                            (8U)
2581 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_4_MASK                                                             (0x00000300U)
2582
2583 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_5_SHIFT                                                            (10U)
2584 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_5_MASK                                                             (0x00000c00U)
2585
2586 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_6_SHIFT                                                            (12U)
2587 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_6_MASK                                                             (0x00003000U)
2588
2589 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_7_SHIFT                                                            (14U)
2590 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_7_MASK                                                             (0x0000c000U)
2591
2592 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_8_SHIFT                                                            (16U)
2593 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_8_MASK                                                             (0x00030000U)
2594
2595 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_9_SHIFT                                                            (18U)
2596 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_9_MASK                                                             (0x000c0000U)
2597
2598 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_10_SHIFT                                                           (20U)
2599 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_10_MASK                                                            (0x00300000U)
2600
2601 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_11_SHIFT                                                           (22U)
2602 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_11_MASK                                                            (0x00c00000U)
2603
2604 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_12_SHIFT                                                           (24U)
2605 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_12_MASK                                                            (0x03000000U)
2606
2607 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_13_SHIFT                                                           (26U)
2608 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_13_MASK                                                            (0x0c000000U)
2609
2610 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_14_SHIFT                                                           (28U)
2611 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_14_MASK                                                            (0x30000000U)
2612
2613 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_15_SHIFT                                                           (30U)
2614 #define MPU_GICD_ICFR11_INT_CONFIG_FIELD_15_MASK                                                            (0xc0000000U)
2615
2616 #define MPU_GICD_PPISR_PPI_STATUS_0_SHIFT                                                                   (12U)
2617 #define MPU_GICD_PPISR_PPI_STATUS_0_MASK                                                                    (0x00001000U)
2618
2619 #define MPU_GICD_PPISR_PPI_STATUS_1_SHIFT                                                                   (13U)
2620 #define MPU_GICD_PPISR_PPI_STATUS_1_MASK                                                                    (0x00002000U)
2621
2622 #define MPU_GICD_PPISR_PPI_STATUS_2_SHIFT                                                                   (14U)
2623 #define MPU_GICD_PPISR_PPI_STATUS_2_MASK                                                                    (0x00004000U)
2624
2625 #define MPU_GICD_PPISR_PPI_STATUS_3_SHIFT                                                                   (15U)
2626 #define MPU_GICD_PPISR_PPI_STATUS_3_MASK                                                                    (0x00008000U)
2627
2628 #define MPU_GICD_PPISR_PPI_STATUS_4_SHIFT                                                                   (11U)
2629 #define MPU_GICD_PPISR_PPI_STATUS_4_MASK                                                                    (0x00000800U)
2630
2631 #define MPU_GICD_PPISR_PPI_STATUS_5_SHIFT                                                                   (10U)
2632 #define MPU_GICD_PPISR_PPI_STATUS_5_MASK                                                                    (0x00000400U)
2633
2634 #define MPU_GICD_PPISR_PPI_STATUS_6_SHIFT                                                                   (9U)
2635 #define MPU_GICD_PPISR_PPI_STATUS_6_MASK                                                                    (0x00000200U)
2636
2637 #define MPU_GICD_PPISR_RESERVED_SHIFT                                                                       (0U)
2638 #define MPU_GICD_PPISR_RESERVED_MASK                                                                        (0x000001ffU)
2639
2640 #define MPU_GICD_PPISR_RESERVED1_SHIFT                                                                      (16U)
2641 #define MPU_GICD_PPISR_RESERVED1_MASK                                                                       (0xffff0000U)
2642
2643 #define MPU_GICD_SPISR0_SPI_0_SHIFT                                                                         (0U)
2644 #define MPU_GICD_SPISR0_SPI_0_MASK                                                                          (0x00000001U)
2645
2646 #define MPU_GICD_SPISR0_SPI_1_SHIFT                                                                         (1U)
2647 #define MPU_GICD_SPISR0_SPI_1_MASK                                                                          (0x00000002U)
2648
2649 #define MPU_GICD_SPISR0_SPI_2_SHIFT                                                                         (2U)
2650 #define MPU_GICD_SPISR0_SPI_2_MASK                                                                          (0x00000004U)
2651
2652 #define MPU_GICD_SPISR0_SPI_3_SHIFT                                                                         (3U)
2653 #define MPU_GICD_SPISR0_SPI_3_MASK                                                                          (0x00000008U)
2654
2655 #define MPU_GICD_SPISR0_SPI_4_SHIFT                                                                         (4U)
2656 #define MPU_GICD_SPISR0_SPI_4_MASK                                                                          (0x00000010U)
2657
2658 #define MPU_GICD_SPISR0_SPI_5_SHIFT                                                                         (5U)
2659 #define MPU_GICD_SPISR0_SPI_5_MASK                                                                          (0x00000020U)
2660
2661 #define MPU_GICD_SPISR0_SPI_6_SHIFT                                                                         (6U)
2662 #define MPU_GICD_SPISR0_SPI_6_MASK                                                                          (0x00000040U)
2663
2664 #define MPU_GICD_SPISR0_SPI_7_SHIFT                                                                         (7U)
2665 #define MPU_GICD_SPISR0_SPI_7_MASK                                                                          (0x00000080U)
2666
2667 #define MPU_GICD_SPISR0_SPI_8_SHIFT                                                                         (8U)
2668 #define MPU_GICD_SPISR0_SPI_8_MASK                                                                          (0x00000100U)
2669
2670 #define MPU_GICD_SPISR0_SPI_9_SHIFT                                                                         (9U)
2671 #define MPU_GICD_SPISR0_SPI_9_MASK                                                                          (0x00000200U)
2672
2673 #define MPU_GICD_SPISR0_SPI_10_SHIFT                                                                        (10U)
2674 #define MPU_GICD_SPISR0_SPI_10_MASK                                                                         (0x00000400U)
2675
2676 #define MPU_GICD_SPISR0_SPI_11_SHIFT                                                                        (11U)
2677 #define MPU_GICD_SPISR0_SPI_11_MASK                                                                         (0x00000800U)
2678
2679 #define MPU_GICD_SPISR0_SPI_12_SHIFT                                                                        (12U)
2680 #define MPU_GICD_SPISR0_SPI_12_MASK                                                                         (0x00001000U)
2681
2682 #define MPU_GICD_SPISR0_SPI_13_SHIFT                                                                        (13U)
2683 #define MPU_GICD_SPISR0_SPI_13_MASK                                                                         (0x00002000U)
2684
2685 #define MPU_GICD_SPISR0_SPI_14_SHIFT                                                                        (14U)
2686 #define MPU_GICD_SPISR0_SPI_14_MASK                                                                         (0x00004000U)
2687
2688 #define MPU_GICD_SPISR0_SPI_15_SHIFT                                                                        (15U)
2689 #define MPU_GICD_SPISR0_SPI_15_MASK                                                                         (0x00008000U)
2690
2691 #define MPU_GICD_SPISR0_SPI_16_SHIFT                                                                        (16U)
2692 #define MPU_GICD_SPISR0_SPI_16_MASK                                                                         (0x00010000U)
2693
2694 #define MPU_GICD_SPISR0_SPI_17_SHIFT                                                                        (17U)
2695 #define MPU_GICD_SPISR0_SPI_17_MASK                                                                         (0x00020000U)
2696
2697 #define MPU_GICD_SPISR0_SPI_18_SHIFT                                                                        (18U)
2698 #define MPU_GICD_SPISR0_SPI_18_MASK                                                                         (0x00040000U)
2699
2700 #define MPU_GICD_SPISR0_SPI_19_SHIFT                                                                        (19U)
2701 #define MPU_GICD_SPISR0_SPI_19_MASK                                                                         (0x00080000U)
2702
2703 #define MPU_GICD_SPISR0_SPI_20_SHIFT                                                                        (20U)
2704 #define MPU_GICD_SPISR0_SPI_20_MASK                                                                         (0x00100000U)
2705
2706 #define MPU_GICD_SPISR0_SPI_21_SHIFT                                                                        (21U)
2707 #define MPU_GICD_SPISR0_SPI_21_MASK                                                                         (0x00200000U)
2708
2709 #define MPU_GICD_SPISR0_SPI_22_SHIFT                                                                        (22U)
2710 #define MPU_GICD_SPISR0_SPI_22_MASK                                                                         (0x00400000U)
2711
2712 #define MPU_GICD_SPISR0_SPI_23_SHIFT                                                                        (23U)
2713 #define MPU_GICD_SPISR0_SPI_23_MASK                                                                         (0x00800000U)
2714
2715 #define MPU_GICD_SPISR0_SPI_24_SHIFT                                                                        (24U)
2716 #define MPU_GICD_SPISR0_SPI_24_MASK                                                                         (0x01000000U)
2717
2718 #define MPU_GICD_SPISR0_SPI_25_SHIFT                                                                        (25U)
2719 #define MPU_GICD_SPISR0_SPI_25_MASK                                                                         (0x02000000U)
2720
2721 #define MPU_GICD_SPISR0_SPI_26_SHIFT                                                                        (26U)
2722 #define MPU_GICD_SPISR0_SPI_26_MASK                                                                         (0x04000000U)
2723
2724 #define MPU_GICD_SPISR0_SPI_27_SHIFT                                                                        (27U)
2725 #define MPU_GICD_SPISR0_SPI_27_MASK                                                                         (0x08000000U)
2726
2727 #define MPU_GICD_SPISR0_SPI_28_SHIFT                                                                        (28U)
2728 #define MPU_GICD_SPISR0_SPI_28_MASK                                                                         (0x10000000U)
2729
2730 #define MPU_GICD_SPISR0_SPI_29_SHIFT                                                                        (29U)
2731 #define MPU_GICD_SPISR0_SPI_29_MASK                                                                         (0x20000000U)
2732
2733 #define MPU_GICD_SPISR0_SPI_30_SHIFT                                                                        (30U)
2734 #define MPU_GICD_SPISR0_SPI_30_MASK                                                                         (0x40000000U)
2735
2736 #define MPU_GICD_SPISR0_SPI_31_SHIFT                                                                        (31U)
2737 #define MPU_GICD_SPISR0_SPI_31_MASK                                                                         (0x80000000U)
2738
2739 #define MPU_GICD_SPISR1_SPI_32_SHIFT                                                                        (0U)
2740 #define MPU_GICD_SPISR1_SPI_32_MASK                                                                         (0x00000001U)
2741
2742 #define MPU_GICD_SPISR1_SPI_33_SHIFT                                                                        (1U)
2743 #define MPU_GICD_SPISR1_SPI_33_MASK                                                                         (0x00000002U)
2744
2745 #define MPU_GICD_SPISR1_SPI_34_SHIFT                                                                        (2U)
2746 #define MPU_GICD_SPISR1_SPI_34_MASK                                                                         (0x00000004U)
2747
2748 #define MPU_GICD_SPISR1_SPI_35_SHIFT                                                                        (3U)
2749 #define MPU_GICD_SPISR1_SPI_35_MASK                                                                         (0x00000008U)
2750
2751 #define MPU_GICD_SPISR1_SPI_36_SHIFT                                                                        (4U)
2752 #define MPU_GICD_SPISR1_SPI_36_MASK                                                                         (0x00000010U)
2753
2754 #define MPU_GICD_SPISR1_SPI_37_SHIFT                                                                        (5U)
2755 #define MPU_GICD_SPISR1_SPI_37_MASK                                                                         (0x00000020U)
2756
2757 #define MPU_GICD_SPISR1_SPI_38_SHIFT                                                                        (6U)
2758 #define MPU_GICD_SPISR1_SPI_38_MASK                                                                         (0x00000040U)
2759
2760 #define MPU_GICD_SPISR1_SPI_39_SHIFT                                                                        (7U)
2761 #define MPU_GICD_SPISR1_SPI_39_MASK                                                                         (0x00000080U)
2762
2763 #define MPU_GICD_SPISR1_SPI_40_SHIFT                                                                        (8U)
2764 #define MPU_GICD_SPISR1_SPI_40_MASK                                                                         (0x00000100U)
2765
2766 #define MPU_GICD_SPISR1_SPI_41_SHIFT                                                                        (9U)
2767 #define MPU_GICD_SPISR1_SPI_41_MASK                                                                         (0x00000200U)
2768
2769 #define MPU_GICD_SPISR1_SPI_42_SHIFT                                                                        (10U)
2770 #define MPU_GICD_SPISR1_SPI_42_MASK                                                                         (0x00000400U)
2771
2772 #define MPU_GICD_SPISR1_SPI_43_SHIFT                                                                        (11U)
2773 #define MPU_GICD_SPISR1_SPI_43_MASK                                                                         (0x00000800U)
2774
2775 #define MPU_GICD_SPISR1_SPI_44_SHIFT                                                                        (12U)
2776 #define MPU_GICD_SPISR1_SPI_44_MASK                                                                         (0x00001000U)
2777
2778 #define MPU_GICD_SPISR1_SPI_45_SHIFT                                                                        (13U)
2779 #define MPU_GICD_SPISR1_SPI_45_MASK                                                                         (0x00002000U)
2780
2781 #define MPU_GICD_SPISR1_SPI_46_SHIFT                                                                        (14U)
2782 #define MPU_GICD_SPISR1_SPI_46_MASK                                                                         (0x00004000U)
2783
2784 #define MPU_GICD_SPISR1_SPI_47_SHIFT                                                                        (15U)
2785 #define MPU_GICD_SPISR1_SPI_47_MASK                                                                         (0x00008000U)
2786
2787 #define MPU_GICD_SPISR1_SPI_48_SHIFT                                                                        (16U)
2788 #define MPU_GICD_SPISR1_SPI_48_MASK                                                                         (0x00010000U)
2789
2790 #define MPU_GICD_SPISR1_SPI_49_SHIFT                                                                        (17U)
2791 #define MPU_GICD_SPISR1_SPI_49_MASK                                                                         (0x00020000U)
2792
2793 #define MPU_GICD_SPISR1_SPI_50_SHIFT                                                                        (18U)
2794 #define MPU_GICD_SPISR1_SPI_50_MASK                                                                         (0x00040000U)
2795
2796 #define MPU_GICD_SPISR1_SPI_51_SHIFT                                                                        (19U)
2797 #define MPU_GICD_SPISR1_SPI_51_MASK                                                                         (0x00080000U)
2798
2799 #define MPU_GICD_SPISR1_SPI_52_SHIFT                                                                        (20U)
2800 #define MPU_GICD_SPISR1_SPI_52_MASK                                                                         (0x00100000U)
2801
2802 #define MPU_GICD_SPISR1_SPI_53_SHIFT                                                                        (21U)
2803 #define MPU_GICD_SPISR1_SPI_53_MASK                                                                         (0x00200000U)
2804
2805 #define MPU_GICD_SPISR1_SPI_54_SHIFT                                                                        (22U)
2806 #define MPU_GICD_SPISR1_SPI_54_MASK                                                                         (0x00400000U)
2807
2808 #define MPU_GICD_SPISR1_SPI_55_SHIFT                                                                        (23U)
2809 #define MPU_GICD_SPISR1_SPI_55_MASK                                                                         (0x00800000U)
2810
2811 #define MPU_GICD_SPISR1_SPI_56_SHIFT                                                                        (24U)
2812 #define MPU_GICD_SPISR1_SPI_56_MASK                                                                         (0x01000000U)
2813
2814 #define MPU_GICD_SPISR1_SPI_57_SHIFT                                                                        (25U)
2815 #define MPU_GICD_SPISR1_SPI_57_MASK                                                                         (0x02000000U)
2816
2817 #define MPU_GICD_SPISR1_SPI_58_SHIFT                                                                        (26U)
2818 #define MPU_GICD_SPISR1_SPI_58_MASK                                                                         (0x04000000U)
2819
2820 #define MPU_GICD_SPISR1_SPI_59_SHIFT                                                                        (27U)
2821 #define MPU_GICD_SPISR1_SPI_59_MASK                                                                         (0x08000000U)
2822
2823 #define MPU_GICD_SPISR1_SPI_60_SHIFT                                                                        (28U)
2824 #define MPU_GICD_SPISR1_SPI_60_MASK                                                                         (0x10000000U)
2825
2826 #define MPU_GICD_SPISR1_SPI_61_SHIFT                                                                        (29U)
2827 #define MPU_GICD_SPISR1_SPI_61_MASK                                                                         (0x20000000U)
2828
2829 #define MPU_GICD_SPISR1_SPI_62_SHIFT                                                                        (30U)
2830 #define MPU_GICD_SPISR1_SPI_62_MASK                                                                         (0x40000000U)
2831
2832 #define MPU_GICD_SPISR1_SPI_63_SHIFT                                                                        (31U)
2833 #define MPU_GICD_SPISR1_SPI_63_MASK                                                                         (0x80000000U)
2834
2835 #define MPU_GICD_SPISR2_ID64_SHIFT                                                                          (0U)
2836 #define MPU_GICD_SPISR2_ID64_MASK                                                                           (0x00000001U)
2837
2838 #define MPU_GICD_SPISR2_ID65_SHIFT                                                                          (1U)
2839 #define MPU_GICD_SPISR2_ID65_MASK                                                                           (0x00000002U)
2840
2841 #define MPU_GICD_SPISR2_ID66_SHIFT                                                                          (2U)
2842 #define MPU_GICD_SPISR2_ID66_MASK                                                                           (0x00000004U)
2843
2844 #define MPU_GICD_SPISR2_ID67_SHIFT                                                                          (3U)
2845 #define MPU_GICD_SPISR2_ID67_MASK                                                                           (0x00000008U)
2846
2847 #define MPU_GICD_SPISR2_ID68_SHIFT                                                                          (4U)
2848 #define MPU_GICD_SPISR2_ID68_MASK                                                                           (0x00000010U)
2849
2850 #define MPU_GICD_SPISR2_ID69_SHIFT                                                                          (5U)
2851 #define MPU_GICD_SPISR2_ID69_MASK                                                                           (0x00000020U)
2852
2853 #define MPU_GICD_SPISR2_ID70_SHIFT                                                                          (6U)
2854 #define MPU_GICD_SPISR2_ID70_MASK                                                                           (0x00000040U)
2855
2856 #define MPU_GICD_SPISR2_ID71_SHIFT                                                                          (7U)
2857 #define MPU_GICD_SPISR2_ID71_MASK                                                                           (0x00000080U)
2858
2859 #define MPU_GICD_SPISR2_ID72_SHIFT                                                                          (8U)
2860 #define MPU_GICD_SPISR2_ID72_MASK                                                                           (0x00000100U)
2861
2862 #define MPU_GICD_SPISR2_ID73_SHIFT                                                                          (9U)
2863 #define MPU_GICD_SPISR2_ID73_MASK                                                                           (0x00000200U)
2864
2865 #define MPU_GICD_SPISR2_ID74_SHIFT                                                                          (10U)
2866 #define MPU_GICD_SPISR2_ID74_MASK                                                                           (0x00000400U)
2867
2868 #define MPU_GICD_SPISR2_ID75_SHIFT                                                                          (11U)
2869 #define MPU_GICD_SPISR2_ID75_MASK                                                                           (0x00000800U)
2870
2871 #define MPU_GICD_SPISR2_ID76_SHIFT                                                                          (12U)
2872 #define MPU_GICD_SPISR2_ID76_MASK                                                                           (0x00001000U)
2873
2874 #define MPU_GICD_SPISR2_ID77_SHIFT                                                                          (13U)
2875 #define MPU_GICD_SPISR2_ID77_MASK                                                                           (0x00002000U)
2876
2877 #define MPU_GICD_SPISR2_ID78_SHIFT                                                                          (14U)
2878 #define MPU_GICD_SPISR2_ID78_MASK                                                                           (0x00004000U)
2879
2880 #define MPU_GICD_SPISR2_ID79_SHIFT                                                                          (15U)
2881 #define MPU_GICD_SPISR2_ID79_MASK                                                                           (0x00008000U)
2882
2883 #define MPU_GICD_SPISR2_ID80_SHIFT                                                                          (16U)
2884 #define MPU_GICD_SPISR2_ID80_MASK                                                                           (0x00010000U)
2885
2886 #define MPU_GICD_SPISR2_ID81_SHIFT                                                                          (17U)
2887 #define MPU_GICD_SPISR2_ID81_MASK                                                                           (0x00020000U)
2888
2889 #define MPU_GICD_SPISR2_ID82_SHIFT                                                                          (18U)
2890 #define MPU_GICD_SPISR2_ID82_MASK                                                                           (0x00040000U)
2891
2892 #define MPU_GICD_SPISR2_ID83_SHIFT                                                                          (19U)
2893 #define MPU_GICD_SPISR2_ID83_MASK                                                                           (0x00080000U)
2894
2895 #define MPU_GICD_SPISR2_ID84_SHIFT                                                                          (20U)
2896 #define MPU_GICD_SPISR2_ID84_MASK                                                                           (0x00100000U)
2897
2898 #define MPU_GICD_SPISR2_ID85_SHIFT                                                                          (21U)
2899 #define MPU_GICD_SPISR2_ID85_MASK                                                                           (0x00200000U)
2900
2901 #define MPU_GICD_SPISR2_ID86_SHIFT                                                                          (22U)
2902 #define MPU_GICD_SPISR2_ID86_MASK                                                                           (0x00400000U)
2903
2904 #define MPU_GICD_SPISR2_ID87_SHIFT                                                                          (23U)
2905 #define MPU_GICD_SPISR2_ID87_MASK                                                                           (0x00800000U)
2906
2907 #define MPU_GICD_SPISR2_ID88_SHIFT                                                                          (24U)
2908 #define MPU_GICD_SPISR2_ID88_MASK                                                                           (0x01000000U)
2909
2910 #define MPU_GICD_SPISR2_ID89_SHIFT                                                                          (25U)
2911 #define MPU_GICD_SPISR2_ID89_MASK                                                                           (0x02000000U)
2912
2913 #define MPU_GICD_SPISR2_ID90_SHIFT                                                                          (26U)
2914 #define MPU_GICD_SPISR2_ID90_MASK                                                                           (0x04000000U)
2915
2916 #define MPU_GICD_SPISR2_ID91_SHIFT                                                                          (27U)
2917 #define MPU_GICD_SPISR2_ID91_MASK                                                                           (0x08000000U)
2918
2919 #define MPU_GICD_SPISR2_ID92_SHIFT                                                                          (28U)
2920 #define MPU_GICD_SPISR2_ID92_MASK                                                                           (0x10000000U)
2921
2922 #define MPU_GICD_SPISR2_ID93_SHIFT                                                                          (29U)
2923 #define MPU_GICD_SPISR2_ID93_MASK                                                                           (0x20000000U)
2924
2925 #define MPU_GICD_SPISR2_ID94_SHIFT                                                                          (30U)
2926 #define MPU_GICD_SPISR2_ID94_MASK                                                                           (0x40000000U)
2927
2928 #define MPU_GICD_SPISR2_ID95_SHIFT                                                                          (31U)
2929 #define MPU_GICD_SPISR2_ID95_MASK                                                                           (0x80000000U)
2930
2931 #define MPU_GICD_SPISR3_ID96_SHIFT                                                                          (0U)
2932 #define MPU_GICD_SPISR3_ID96_MASK                                                                           (0x00000001U)
2933
2934 #define MPU_GICD_SPISR3_ID97_SHIFT                                                                          (1U)
2935 #define MPU_GICD_SPISR3_ID97_MASK                                                                           (0x00000002U)
2936
2937 #define MPU_GICD_SPISR3_ID98_SHIFT                                                                          (2U)
2938 #define MPU_GICD_SPISR3_ID98_MASK                                                                           (0x00000004U)
2939
2940 #define MPU_GICD_SPISR3_ID99_SHIFT                                                                          (3U)
2941 #define MPU_GICD_SPISR3_ID99_MASK                                                                           (0x00000008U)
2942
2943 #define MPU_GICD_SPISR3_ID100_SHIFT                                                                         (4U)
2944 #define MPU_GICD_SPISR3_ID100_MASK                                                                          (0x00000010U)
2945
2946 #define MPU_GICD_SPISR3_ID101_SHIFT                                                                         (5U)
2947 #define MPU_GICD_SPISR3_ID101_MASK                                                                          (0x00000020U)
2948
2949 #define MPU_GICD_SPISR3_ID102_SHIFT                                                                         (6U)
2950 #define MPU_GICD_SPISR3_ID102_MASK                                                                          (0x00000040U)
2951
2952 #define MPU_GICD_SPISR3_ID103_SHIFT                                                                         (7U)
2953 #define MPU_GICD_SPISR3_ID103_MASK                                                                          (0x00000080U)
2954
2955 #define MPU_GICD_SPISR3_ID104_SHIFT                                                                         (8U)
2956 #define MPU_GICD_SPISR3_ID104_MASK                                                                          (0x00000100U)
2957
2958 #define MPU_GICD_SPISR3_ID105_SHIFT                                                                         (9U)
2959 #define MPU_GICD_SPISR3_ID105_MASK                                                                          (0x00000200U)
2960
2961 #define MPU_GICD_SPISR3_ID106_SHIFT                                                                         (10U)
2962 #define MPU_GICD_SPISR3_ID106_MASK                                                                          (0x00000400U)
2963
2964 #define MPU_GICD_SPISR3_ID107_SHIFT                                                                         (11U)
2965 #define MPU_GICD_SPISR3_ID107_MASK                                                                          (0x00000800U)
2966
2967 #define MPU_GICD_SPISR3_ID108_SHIFT                                                                         (12U)
2968 #define MPU_GICD_SPISR3_ID108_MASK                                                                          (0x00001000U)
2969
2970 #define MPU_GICD_SPISR3_ID109_SHIFT                                                                         (13U)
2971 #define MPU_GICD_SPISR3_ID109_MASK                                                                          (0x00002000U)
2972
2973 #define MPU_GICD_SPISR3_ID110_SHIFT                                                                         (14U)
2974 #define MPU_GICD_SPISR3_ID110_MASK                                                                          (0x00004000U)
2975
2976 #define MPU_GICD_SPISR3_ID111_SHIFT                                                                         (15U)
2977 #define MPU_GICD_SPISR3_ID111_MASK                                                                          (0x00008000U)
2978
2979 #define MPU_GICD_SPISR3_ID112_SHIFT                                                                         (16U)
2980 #define MPU_GICD_SPISR3_ID112_MASK                                                                          (0x00010000U)
2981
2982 #define MPU_GICD_SPISR3_ID113_SHIFT                                                                         (17U)
2983 #define MPU_GICD_SPISR3_ID113_MASK                                                                          (0x00020000U)
2984
2985 #define MPU_GICD_SPISR3_ID114_SHIFT                                                                         (18U)
2986 #define MPU_GICD_SPISR3_ID114_MASK                                                                          (0x00040000U)
2987
2988 #define MPU_GICD_SPISR3_ID115_SHIFT                                                                         (19U)
2989 #define MPU_GICD_SPISR3_ID115_MASK                                                                          (0x00080000U)
2990
2991 #define MPU_GICD_SPISR3_ID116_SHIFT                                                                         (20U)
2992 #define MPU_GICD_SPISR3_ID116_MASK                                                                          (0x00100000U)
2993
2994 #define MPU_GICD_SPISR3_ID117_SHIFT                                                                         (21U)
2995 #define MPU_GICD_SPISR3_ID117_MASK                                                                          (0x00200000U)
2996
2997 #define MPU_GICD_SPISR3_ID118_SHIFT                                                                         (22U)
2998 #define MPU_GICD_SPISR3_ID118_MASK                                                                          (0x00400000U)
2999
3000 #define MPU_GICD_SPISR3_ID119_SHIFT                                                                         (23U)
3001 #define MPU_GICD_SPISR3_ID119_MASK                                                                          (0x00800000U)
3002
3003 #define MPU_GICD_SPISR3_ID120_SHIFT                                                                         (24U)
3004 #define MPU_GICD_SPISR3_ID120_MASK                                                                          (0x01000000U)
3005
3006 #define MPU_GICD_SPISR3_ID121_SHIFT                                                                         (25U)
3007 #define MPU_GICD_SPISR3_ID121_MASK                                                                          (0x02000000U)
3008
3009 #define MPU_GICD_SPISR3_ID122_SHIFT                                                                         (26U)
3010 #define MPU_GICD_SPISR3_ID122_MASK                                                                          (0x04000000U)
3011
3012 #define MPU_GICD_SPISR3_ID123_SHIFT                                                                         (27U)
3013 #define MPU_GICD_SPISR3_ID123_MASK                                                                          (0x08000000U)
3014
3015 #define MPU_GICD_SPISR3_ID124_SHIFT                                                                         (28U)
3016 #define MPU_GICD_SPISR3_ID124_MASK                                                                          (0x10000000U)
3017
3018 #define MPU_GICD_SPISR3_ID125_SHIFT                                                                         (29U)
3019 #define MPU_GICD_SPISR3_ID125_MASK                                                                          (0x20000000U)
3020
3021 #define MPU_GICD_SPISR3_ID126_SHIFT                                                                         (30U)
3022 #define MPU_GICD_SPISR3_ID126_MASK                                                                          (0x40000000U)
3023
3024 #define MPU_GICD_SPISR3_ID127_SHIFT                                                                         (31U)
3025 #define MPU_GICD_SPISR3_ID127_MASK                                                                          (0x80000000U)
3026
3027 #define MPU_GICD_SPISR4_ID128_SHIFT                                                                         (0U)
3028 #define MPU_GICD_SPISR4_ID128_MASK                                                                          (0x00000001U)
3029
3030 #define MPU_GICD_SPISR4_ID129_SHIFT                                                                         (1U)
3031 #define MPU_GICD_SPISR4_ID129_MASK                                                                          (0x00000002U)
3032
3033 #define MPU_GICD_SPISR4_ID130_SHIFT                                                                         (2U)
3034 #define MPU_GICD_SPISR4_ID130_MASK                                                                          (0x00000004U)
3035
3036 #define MPU_GICD_SPISR4_ID131_SHIFT                                                                         (3U)
3037 #define MPU_GICD_SPISR4_ID131_MASK                                                                          (0x00000008U)
3038
3039 #define MPU_GICD_SPISR4_ID132_SHIFT                                                                         (4U)
3040 #define MPU_GICD_SPISR4_ID132_MASK                                                                          (0x00000010U)
3041
3042 #define MPU_GICD_SPISR4_ID133_SHIFT                                                                         (5U)
3043 #define MPU_GICD_SPISR4_ID133_MASK                                                                          (0x00000020U)
3044
3045 #define MPU_GICD_SPISR4_ID134_SHIFT                                                                         (6U)
3046 #define MPU_GICD_SPISR4_ID134_MASK                                                                          (0x00000040U)
3047
3048 #define MPU_GICD_SPISR4_ID135_SHIFT                                                                         (7U)
3049 #define MPU_GICD_SPISR4_ID135_MASK                                                                          (0x00000080U)
3050
3051 #define MPU_GICD_SPISR4_ID136_SHIFT                                                                         (8U)
3052 #define MPU_GICD_SPISR4_ID136_MASK                                                                          (0x00000100U)
3053
3054 #define MPU_GICD_SPISR4_ID137_SHIFT                                                                         (9U)
3055 #define MPU_GICD_SPISR4_ID137_MASK                                                                          (0x00000200U)
3056
3057 #define MPU_GICD_SPISR4_ID138_SHIFT                                                                         (10U)
3058 #define MPU_GICD_SPISR4_ID138_MASK                                                                          (0x00000400U)
3059
3060 #define MPU_GICD_SPISR4_ID139_SHIFT                                                                         (11U)
3061 #define MPU_GICD_SPISR4_ID139_MASK                                                                          (0x00000800U)
3062
3063 #define MPU_GICD_SPISR4_ID140_SHIFT                                                                         (12U)
3064 #define MPU_GICD_SPISR4_ID140_MASK                                                                          (0x00001000U)
3065
3066 #define MPU_GICD_SPISR4_ID141_SHIFT                                                                         (13U)
3067 #define MPU_GICD_SPISR4_ID141_MASK                                                                          (0x00002000U)
3068
3069 #define MPU_GICD_SPISR4_ID142_SHIFT                                                                         (14U)
3070 #define MPU_GICD_SPISR4_ID142_MASK                                                                          (0x00004000U)
3071
3072 #define MPU_GICD_SPISR4_ID143_SHIFT                                                                         (15U)
3073 #define MPU_GICD_SPISR4_ID143_MASK                                                                          (0x00008000U)
3074
3075 #define MPU_GICD_SPISR4_ID144_SHIFT                                                                         (16U)
3076 #define MPU_GICD_SPISR4_ID144_MASK                                                                          (0x00010000U)
3077
3078 #define MPU_GICD_SPISR4_ID145_SHIFT                                                                         (17U)
3079 #define MPU_GICD_SPISR4_ID145_MASK                                                                          (0x00020000U)
3080
3081 #define MPU_GICD_SPISR4_ID146_SHIFT                                                                         (18U)
3082 #define MPU_GICD_SPISR4_ID146_MASK                                                                          (0x00040000U)
3083
3084 #define MPU_GICD_SPISR4_ID147_SHIFT                                                                         (19U)
3085 #define MPU_GICD_SPISR4_ID147_MASK                                                                          (0x00080000U)
3086
3087 #define MPU_GICD_SPISR4_ID148_SHIFT                                                                         (20U)
3088 #define MPU_GICD_SPISR4_ID148_MASK                                                                          (0x00100000U)
3089
3090 #define MPU_GICD_SPISR4_ID149_SHIFT                                                                         (21U)
3091 #define MPU_GICD_SPISR4_ID149_MASK                                                                          (0x00200000U)
3092
3093 #define MPU_GICD_SPISR4_ID150_SHIFT                                                                         (22U)
3094 #define MPU_GICD_SPISR4_ID150_MASK                                                                          (0x00400000U)
3095
3096 #define MPU_GICD_SPISR4_ID151_SHIFT                                                                         (23U)
3097 #define MPU_GICD_SPISR4_ID151_MASK                                                                          (0x00800000U)
3098
3099 #define MPU_GICD_SPISR4_ID152_SHIFT                                                                         (24U)
3100 #define MPU_GICD_SPISR4_ID152_MASK                                                                          (0x01000000U)
3101
3102 #define MPU_GICD_SPISR4_ID153_SHIFT                                                                         (25U)
3103 #define MPU_GICD_SPISR4_ID153_MASK                                                                          (0x02000000U)
3104
3105 #define MPU_GICD_SPISR4_ID154_SHIFT                                                                         (26U)
3106 #define MPU_GICD_SPISR4_ID154_MASK                                                                          (0x04000000U)
3107
3108 #define MPU_GICD_SPISR4_ID155_SHIFT                                                                         (27U)
3109 #define MPU_GICD_SPISR4_ID155_MASK                                                                          (0x08000000U)
3110
3111 #define MPU_GICD_SPISR4_ID156_SHIFT                                                                         (28U)
3112 #define MPU_GICD_SPISR4_ID156_MASK                                                                          (0x10000000U)
3113
3114 #define MPU_GICD_SPISR4_ID157_SHIFT                                                                         (29U)
3115 #define MPU_GICD_SPISR4_ID157_MASK                                                                          (0x20000000U)
3116
3117 #define MPU_GICD_SPISR4_ID158_SHIFT                                                                         (30U)
3118 #define MPU_GICD_SPISR4_ID158_MASK                                                                          (0x40000000U)
3119
3120 #define MPU_GICD_SPISR4_ID159_SHIFT                                                                         (31U)
3121 #define MPU_GICD_SPISR4_ID159_MASK                                                                          (0x80000000U)
3122
3123 #define MPU_GICD_SGIR_SATT_SHIFT                                                                            (15U)
3124 #define MPU_GICD_SGIR_SATT_MASK                                                                             (0x00008000U)
3125
3126 #define MPU_GICD_SGIR_SGIINTID_SHIFT                                                                        (0U)
3127 #define MPU_GICD_SGIR_SGIINTID_MASK                                                                         (0x0000000fU)
3128
3129 #define MPU_GICD_SGIR_CPUTARGETLIST_SHIFT                                                                   (16U)
3130 #define MPU_GICD_SGIR_CPUTARGETLIST_MASK                                                                    (0x00ff0000U)
3131
3132 #define MPU_GICD_SGIR_TARGETLISTFILTER_SHIFT                                                                (24U)
3133 #define MPU_GICD_SGIR_TARGETLISTFILTER_MASK                                                                 (0x03000000U)
3134
3135 #define MPU_GICD_SGIR_RESERVED_SHIFT                                                                        (4U)
3136 #define MPU_GICD_SGIR_RESERVED_MASK                                                                         (0x00007ff0U)
3137
3138 #define MPU_GICD_SGIR_RESERVED2_SHIFT                                                                       (26U)
3139 #define MPU_GICD_SGIR_RESERVED2_MASK                                                                        (0xfc000000U)
3140
3141 #define MPU_GICD_CPENDSGIR0_SGI0_SHIFT                                                                      (0U)
3142 #define MPU_GICD_CPENDSGIR0_SGI0_MASK                                                                       (0x000000ffU)
3143
3144 #define MPU_GICD_CPENDSGIR0_SGI1_SHIFT                                                                      (8U)
3145 #define MPU_GICD_CPENDSGIR0_SGI1_MASK                                                                       (0x0000ff00U)
3146
3147 #define MPU_GICD_CPENDSGIR0_SGI2_SHIFT                                                                      (16U)
3148 #define MPU_GICD_CPENDSGIR0_SGI2_MASK                                                                       (0x00ff0000U)
3149
3150 #define MPU_GICD_CPENDSGIR0_SGI3_SHIFT                                                                      (24U)
3151 #define MPU_GICD_CPENDSGIR0_SGI3_MASK                                                                       (0xff000000U)
3152
3153 #define MPU_GICD_CPENDSGIR1_SGI4_SHIFT                                                                      (0U)
3154 #define MPU_GICD_CPENDSGIR1_SGI4_MASK                                                                       (0x000000ffU)
3155
3156 #define MPU_GICD_CPENDSGIR1_SGI5_SHIFT                                                                      (8U)
3157 #define MPU_GICD_CPENDSGIR1_SGI5_MASK                                                                       (0x0000ff00U)
3158
3159 #define MPU_GICD_CPENDSGIR1_SGI6_SHIFT                                                                      (16U)
3160 #define MPU_GICD_CPENDSGIR1_SGI6_MASK                                                                       (0x00ff0000U)
3161
3162 #define MPU_GICD_CPENDSGIR1_SGI7_SHIFT                                                                      (24U)
3163 #define MPU_GICD_CPENDSGIR1_SGI7_MASK                                                                       (0xff000000U)
3164
3165 #define MPU_GICD_CPENDSGIR2_SGI8_SHIFT                                                                      (0U)
3166 #define MPU_GICD_CPENDSGIR2_SGI8_MASK                                                                       (0x000000ffU)
3167
3168 #define MPU_GICD_CPENDSGIR2_SGI9_SHIFT                                                                      (8U)
3169 #define MPU_GICD_CPENDSGIR2_SGI9_MASK                                                                       (0x0000ff00U)
3170
3171 #define MPU_GICD_CPENDSGIR2_SGI10_SHIFT                                                                     (16U)
3172 #define MPU_GICD_CPENDSGIR2_SGI10_MASK                                                                      (0x00ff0000U)
3173
3174 #define MPU_GICD_CPENDSGIR2_SGI11_SHIFT                                                                     (24U)
3175 #define MPU_GICD_CPENDSGIR2_SGI11_MASK                                                                      (0xff000000U)
3176
3177 #define MPU_GICD_CPENDSGIR3_SGI12_SHIFT                                                                     (0U)
3178 #define MPU_GICD_CPENDSGIR3_SGI12_MASK                                                                      (0x000000ffU)
3179
3180 #define MPU_GICD_CPENDSGIR3_SGI13_SHIFT                                                                     (8U)
3181 #define MPU_GICD_CPENDSGIR3_SGI13_MASK                                                                      (0x0000ff00U)
3182
3183 #define MPU_GICD_CPENDSGIR3_SGI14_SHIFT                                                                     (16U)
3184 #define MPU_GICD_CPENDSGIR3_SGI14_MASK                                                                      (0x00ff0000U)
3185
3186 #define MPU_GICD_CPENDSGIR3_SGI15_SHIFT                                                                     (24U)
3187 #define MPU_GICD_CPENDSGIR3_SGI15_MASK                                                                      (0xff000000U)
3188
3189 #define MPU_GICD_SPENDSGIR0_SGI0_SHIFT                                                                      (0U)
3190 #define MPU_GICD_SPENDSGIR0_SGI0_MASK                                                                       (0x000000ffU)
3191
3192 #define MPU_GICD_SPENDSGIR0_SGI1_SHIFT                                                                      (8U)
3193 #define MPU_GICD_SPENDSGIR0_SGI1_MASK                                                                       (0x0000ff00U)
3194
3195 #define MPU_GICD_SPENDSGIR0_SGI2_SHIFT                                                                      (16U)
3196 #define MPU_GICD_SPENDSGIR0_SGI2_MASK                                                                       (0x00ff0000U)
3197
3198 #define MPU_GICD_SPENDSGIR0_SGI3_SHIFT                                                                      (24U)
3199 #define MPU_GICD_SPENDSGIR0_SGI3_MASK                                                                       (0xff000000U)
3200
3201 #define MPU_GICD_SPENDSGIR1_SGI4_SHIFT                                                                      (0U)
3202 #define MPU_GICD_SPENDSGIR1_SGI4_MASK                                                                       (0x000000ffU)
3203
3204 #define MPU_GICD_SPENDSGIR1_SGI5_SHIFT                                                                      (8U)
3205 #define MPU_GICD_SPENDSGIR1_SGI5_MASK                                                                       (0x0000ff00U)
3206
3207 #define MPU_GICD_SPENDSGIR1_SGI6_SHIFT                                                                      (16U)
3208 #define MPU_GICD_SPENDSGIR1_SGI6_MASK                                                                       (0x00ff0000U)
3209
3210 #define MPU_GICD_SPENDSGIR1_SGI7_SHIFT                                                                      (24U)
3211 #define MPU_GICD_SPENDSGIR1_SGI7_MASK                                                                       (0xff000000U)
3212
3213 #define MPU_GICD_SPENDSGIR2_SGI8_SHIFT                                                                      (0U)
3214 #define MPU_GICD_SPENDSGIR2_SGI8_MASK                                                                       (0x000000ffU)
3215
3216 #define MPU_GICD_SPENDSGIR2_SGI9_SHIFT                                                                      (8U)
3217 #define MPU_GICD_SPENDSGIR2_SGI9_MASK                                                                       (0x0000ff00U)
3218
3219 #define MPU_GICD_SPENDSGIR2_SGI10_SHIFT                                                                     (16U)
3220 #define MPU_GICD_SPENDSGIR2_SGI10_MASK                                                                      (0x00ff0000U)
3221
3222 #define MPU_GICD_SPENDSGIR2_SGI11_SHIFT                                                                     (24U)
3223 #define MPU_GICD_SPENDSGIR2_SGI11_MASK                                                                      (0xff000000U)
3224
3225 #define MPU_GICD_SPENDSGIR3_SGI12_SHIFT                                                                     (0U)
3226 #define MPU_GICD_SPENDSGIR3_SGI12_MASK                                                                      (0x000000ffU)
3227
3228 #define MPU_GICD_SPENDSGIR3_SGI13_SHIFT                                                                     (8U)
3229 #define MPU_GICD_SPENDSGIR3_SGI13_MASK                                                                      (0x0000ff00U)
3230
3231 #define MPU_GICD_SPENDSGIR3_SGI14_SHIFT                                                                     (16U)
3232 #define MPU_GICD_SPENDSGIR3_SGI14_MASK                                                                      (0x00ff0000U)
3233
3234 #define MPU_GICD_SPENDSGIR3_SGI15_SHIFT                                                                     (24U)
3235 #define MPU_GICD_SPENDSGIR3_SGI15_MASK                                                                      (0xff000000U)
3236
3237 #define MPU_GICD_PIDR4_CONTINUATION_CODE_SHIFT                                                              (0U)
3238 #define MPU_GICD_PIDR4_CONTINUATION_CODE_MASK                                                               (0x0000000fU)
3239
3240 #define MPU_GICD_PIDR4_RESERVED_SHIFT                                                                       (4U)
3241 #define MPU_GICD_PIDR4_RESERVED_MASK                                                                        (0xfffffff0U)
3242
3243 #define MPU_GICD_PIDR5_RESERVED_SHIFT                                                                       (0U)
3244 #define MPU_GICD_PIDR5_RESERVED_MASK                                                                        (0xffffffffU)
3245
3246 #define MPU_GICD_PIDR6_RESERVED_SHIFT                                                                       (0U)
3247 #define MPU_GICD_PIDR6_RESERVED_MASK                                                                        (0xffffffffU)
3248
3249 #define MPU_GICD_PIDR7_RESERVED_SHIFT                                                                       (0U)
3250 #define MPU_GICD_PIDR7_RESERVED_MASK                                                                        (0xffffffffU)
3251
3252 #define MPU_GICD_PIDR0_DEVID_FIELD_SHIFT                                                                    (0U)
3253 #define MPU_GICD_PIDR0_DEVID_FIELD_MASK                                                                     (0x000000ffU)
3254
3255 #define MPU_GICD_PIDR0_RESERVED_SHIFT                                                                       (8U)
3256 #define MPU_GICD_PIDR0_RESERVED_MASK                                                                        (0xffffff00U)
3257
3258 #define MPU_GICD_PIDR1_DEVID_SHIFT                                                                          (0U)
3259 #define MPU_GICD_PIDR1_DEVID_MASK                                                                           (0x0000000fU)
3260
3261 #define MPU_GICD_PIDR1_ARCHID_LOWER_FIELD_SHIFT                                                             (4U)
3262 #define MPU_GICD_PIDR1_ARCHID_LOWER_FIELD_MASK                                                              (0x000000f0U)
3263
3264 #define MPU_GICD_PIDR1_RESERVED_SHIFT                                                                       (8U)
3265 #define MPU_GICD_PIDR1_RESERVED_MASK                                                                        (0xffffff00U)
3266
3267 #define MPU_GICD_PIDR2_ARCHID_HIGHER_FIELD_SHIFT                                                            (0U)
3268 #define MPU_GICD_PIDR2_ARCHID_HIGHER_FIELD_MASK                                                             (0x00000007U)
3269
3270 #define MPU_GICD_PIDR2_USESJEP_CODE_FIELD_SHIFT                                                             (3U)
3271 #define MPU_GICD_PIDR2_USESJEP_CODE_FIELD_MASK                                                              (0x00000008U)
3272
3273 #define MPU_GICD_PIDR2_ARCHREV_FIELD_SHIFT                                                                  (4U)
3274 #define MPU_GICD_PIDR2_ARCHREV_FIELD_MASK                                                                   (0x000000f0U)
3275
3276 #define MPU_GICD_PIDR2_RESERVED_SHIFT                                                                       (8U)
3277 #define MPU_GICD_PIDR2_RESERVED_MASK                                                                        (0xffffff00U)
3278
3279 #define MPU_GICD_PIDR3_REVISION_FIELD_SHIFT                                                                 (4U)
3280 #define MPU_GICD_PIDR3_REVISION_FIELD_MASK                                                                  (0x000000f0U)
3281
3282 #define MPU_GICD_PIDR3_RESERVED_SHIFT                                                                       (0U)
3283 #define MPU_GICD_PIDR3_RESERVED_MASK                                                                        (0x0000000fU)
3284
3285 #define MPU_GICD_PIDR3_RESERVED1_SHIFT                                                                      (8U)
3286 #define MPU_GICD_PIDR3_RESERVED1_MASK                                                                       (0xffffff00U)
3287
3288 #define MPU_GICD_CIDR0_PREAMBLE_SHIFT                                                                       (0U)
3289 #define MPU_GICD_CIDR0_PREAMBLE_MASK                                                                        (0x000000ffU)
3290
3291 #define MPU_GICD_CIDR0_RESERVED_SHIFT                                                                       (8U)
3292 #define MPU_GICD_CIDR0_RESERVED_MASK                                                                        (0xffffff00U)
3293
3294 #define MPU_GICD_CIDR1_PREAMBLE_SHIFT                                                                       (0U)
3295 #define MPU_GICD_CIDR1_PREAMBLE_MASK                                                                        (0x000000ffU)
3296
3297 #define MPU_GICD_CIDR1_RESERVED_SHIFT                                                                       (8U)
3298 #define MPU_GICD_CIDR1_RESERVED_MASK                                                                        (0xffffff00U)
3299
3300 #define MPU_GICD_CIDR2_PREAMBLE_SHIFT                                                                       (0U)
3301 #define MPU_GICD_CIDR2_PREAMBLE_MASK                                                                        (0x000000ffU)
3302
3303 #define MPU_GICD_CIDR2_RESERVED_SHIFT                                                                       (8U)
3304 #define MPU_GICD_CIDR2_RESERVED_MASK                                                                        (0xffffff00U)
3305
3306 #define MPU_GICD_CIDR3_PREAMBLE_SHIFT                                                                       (0U)
3307 #define MPU_GICD_CIDR3_PREAMBLE_MASK                                                                        (0x000000ffU)
3308
3309 #define MPU_GICD_CIDR3_RESERVED_SHIFT                                                                       (8U)
3310 #define MPU_GICD_CIDR3_RESERVED_MASK                                                                        (0xffffff00U)
3311
3312 #ifdef __cplusplus
3313 }
3314 #endif
3315 #endif  /* _HW_MPU_INTC_DIST_H_ */