[processor-sdk/performance-audio-sr.git] / pdk_k2g_1_0_1_0_eng / packages / ti / csl / arch / a15 / src / csl_a15_startup.c
1 /**
2 * \file a15_startup.c
3 *
4 * \brief Interrupt vector is copied to the internal Ram. After that the
5 * control is given to the application.
6 *
7 * \copyright Copyright (C) 2013-2016 Texas Instruments Incorporated -
8 * http://www.ti.com/
9 */
11 /**
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
46 #include <ti/csl/tistdtypes.h>
47 #if 1
48 #include <ti/csl/csl_a15Aux.h>
49 #include <ti/csl/csl_armGicAux.h>
50 #endif
51 #include <ti/csl/arch/a15/csl_a15_startup.h>
53 /* ========================================================================== */
54 /* Internal Function Declarations */
55 /* ========================================================================== */
57 #define MMU_PAGETABLE_ALIGN_SIZE (16U * 1024U)
59 #define CSL_ENABLE_CACHE_MMU /* Enable MMU & CACHE */
61 #if defined(CSL_ENABLE_MMU)
62 #define CSL_MMU_DESC_TYPE_LONG /* MMU to use long descriptor */
63 #elif defined(CSL_ENABLE_CACHE_MMU)
64 #define CSL_MMU_DESC_TYPE_LONG /* MMU to use long descriptor */
65 #endif
67 static void CSL_A15_INIT_copyVectorTable(void);
69 void CSL_A15_INIT_startup(void);
71 extern Int32 main(void);
73 /* ========================================================================== */
74 /* Global Variables */
75 /* ========================================================================== */
77 /** \brief Vector table */
78 static Uint32 const vecTbl[14]=
79 {
80 0xE59FF018U, /* Opcode for loading PC with the contents of [PC + 0x18] */
81 0xE59FF018U, /* Opcode for loading PC with the contents of [PC + 0x18] */
82 0xE59FF018U, /* Opcode for loading PC with the contents of [PC + 0x18] */
83 0xE59FF018U, /* Opcode for loading PC with the contents of [PC + 0x18] */
84 0xE59FF014U, /* Opcode for loading PC with the contents of [PC + 0x14] */
85 0xE24FF008U, /* Opcode for loading PC with (PC - 8) (eq. to while(1)) */
86 0xE59FF010U, /* Opcode for loading PC with the contents of [PC + 0x10] */
87 0xE59FF010U, /* Opcode for loading PC with the contents of [PC + 0x10] */
88 (Uint32)(&Entry),
89 (Uint32)(&UndefInstHandler),
90 (Uint32)(&SVC_Handler),
91 (Uint32)(&AbortHandler),
92 (Uint32)(&IRQHandler),
93 (Uint32)(&FIQHandler)
94 };
96 #if 1
97 CSL_ArmGicDistIntrf distrIntrf;
98 CSL_ArmGicCpuIntrf gCpuIntrf;
99 #endif
101 /** \brief Page table configuration.*/
102 #if defined(CSL_ENABLE_MMU) || defined(CSL_ENABLE_CACHE_MMU)/* Enable MMU */
103 #if defined(CSL_MMU_DESC_TYPE_LONG) /* Enable to use long descriptor */
105 /** \brief Page tables to hold physical to virtual address mapping. The start
106 address of the page table must be aligned at 16K boundary */
107 CSL_A15MmuLongDescObj mmuObj
108 __attribute__((aligned(MMU_PAGETABLE_ALIGN_SIZE)));
110 CSL_A15MmuLongDescAttr mmuAttr0;
111 CSL_A15MmuLongDescAttr mmuAttr1;
112 CSL_A15MmuLongDescAttr mmuAttr2;
113 #else
115 /** \brief Page tables to hold physical to virtual address mapping. The start
116 address of the page table must be aligned at 16K boundary */
117 #pragma DATA_ALIGN(mmuobj, MMU_PAGETABLE_ALIGN_SIZE);
118 CSL_A15MmuShortDescObj mmuobj;
119 CSL_A15MmuShortDescObj mmuobj
120 __attribute__((aligned(MMU_PAGETABLE_ALIGN_SIZE)));
122 CSL_A15MmuShortDescAttr mmuAttr0;
123 CSL_A15MmuShortDescAttr mmuAttr1;
124 CSL_A15MmuShortDescAttr mmuAttr2;
125 CSL_A15MmuShortDescAttr mmuAttr3;
126 #endif
127 #endif
129 /* ========================================================================== */
130 /* Function Definitions */
131 /* ========================================================================== */
133 /**
134 * \brief This function does two operations:\n
135 * 1> Copies an array which contains vector table values to the
136 * processor's vector table space.\n
137 * 2> Then it calls the main() function.\n
138 *
139 * \param None.
140 *
141 * \retval None.
142 *
143 * \note This function is the first function that needs to be called in a
144 * system. This should be set as the entry point in the linker script
145 * file if the ELF executable is to loaded via a debugger on the
146 * target. This function never returns, but gives control to the
147 * application entry point.
148 **/
149 Uint32 start_boot(void); /*for misra warnings*/
150 Uint32 start_boot(void)
151 {
152 /* Copy the vector table to desired location. */
153 CSL_A15_INIT_copyVectorTable();
155 /* Configure system */
156 CSL_A15_INIT_startup();
158 /* Calling the main */
159 main();
161 while(1)
162 {}
163 }
165 /**
166 * \brief This function copies the vector table to a location in OCMC
167 * RAM and sets the vector base address register.
168 *
169 * \param None.
170 * \retval None.
171 *
172 * Note: The default vector table base is in OCMC RAM, but can be moved to
173 * other locations, to make some more space in OCMC RAM for relocating any
174 * other code, if desired. The vector table can be placed anywhere in the
175 * memory map. If the entire code is intended to be run from DDR, it can be
176 * placed in DDR also. In this case, only vector base address register need
177 * to be set with the base address of the vector table.
178 */
179 static void CSL_A15_INIT_copyVectorTable(void)
180 {
181 Uint32 vectorBase = 0x40300000U;
182 Uint32 ocmcRamSize = 512U * 1024U;
184 vectorBase = vectorBase + ocmcRamSize - 0x400U;
186 Uint32 *dest = (Uint32 *)vectorBase;
187 Uint32 *src = (Uint32 *)vecTbl;
188 Uint32 count;
190 CSL_a15SetVectorTable(vectorBase);
192 for(count = 0; count < sizeof(vecTbl)/sizeof(vecTbl[0]); count++)
193 {
194 dest[count] = src[count];
195 }
196 }
198 #if 1
199 void INTCCommonIntrHandler(void); /*for misra warnings*/
200 void INTCCommonIntrHandler(void)
201 {
202 CSL_armGicCommonIntrHandler(&gCpuIntrf);
203 }
204 #endif
206 void CSL_A15_INIT_startup(void)
207 {
208 uint32_t phyAddr = 0U;
210 #if defined(CSL_ENABLE_MMU) || defined(CSL_ENABLE_CACHE_MMU) /* Enable MMU */
211 #if defined(CSL_MMU_DESC_TYPE_LONG) /* Enable to use long descriptor */
212 mmuObj.numFirstLvlEntires = CSL_A15_MMU_LONG_DESC_LVL1_ENTIRES;
213 mmuObj.numSecondLvlEntires = CSL_A15_MMU_LONG_DESC_LVL2_ENTIRES;
214 mmuObj.mairEntires = CSL_A15_MMU_MAIR_LEN_BYTES;
215 mmuObj.mairAttr[0] = 0x44U;
216 mmuObj.mairAttr[1] = 0x0U;
217 mmuObj.mairAttr[2] = 0xFFU;
218 CSL_a15InitMmuLongDesc(&mmuObj);
220 CSL_a15InitMmuLongDescAttrs(&mmuAttr0);
221 CSL_a15InitMmuLongDescAttrs(&mmuAttr1);
222 CSL_a15InitMmuLongDescAttrs(&mmuAttr2);
224 mmuObj.mairAttr[0] = 0x44U;
225 mmuObj.mairAttr[1] = 0x0U;
226 mmuObj.mairAttr[2] = 0xFFU;
227 CSL_a15SetMmuMair(0, mmuObj.mairAttr[0]);
228 CSL_a15SetMmuMair(1, mmuObj.mairAttr[1]);
229 CSL_a15SetMmuMair(2, mmuObj.mairAttr[2]);
231 mmuAttr0.type = CSL_A15_MMU_LONG_DESC_TYPE_BLOCK;
232 mmuAttr0.accPerm = 0U;
233 mmuAttr0.shareable = 2U;
234 mmuAttr0.attrIndx = 1U;
236 for (phyAddr = 0x40000000U; phyAddr < 0x60000000U; phyAddr += 0x00200000U)
237 {
238 CSL_a15SetMmuSecondLevelLongDesc(&mmuObj, (void *)phyAddr, (void *)phyAddr, &mmuAttr0);
239 }
241 mmuAttr1.type = CSL_A15_MMU_LONG_DESC_TYPE_BLOCK;
242 mmuAttr1.accPerm = 0U;
243 mmuAttr1.shareable = 2U;
244 mmuAttr1.attrIndx = 2U;
246 for (phyAddr = 0x80000000U; phyAddr < 0xA0000000U; phyAddr += 0x00200000U)
247 {
248 CSL_a15SetMmuSecondLevelLongDesc(&mmuObj, (void *)phyAddr, (void *)phyAddr, &mmuAttr1);
249 }
251 mmuAttr2.type = CSL_A15_MMU_LONG_DESC_TYPE_BLOCK;
252 mmuAttr2.accPerm = 0U;
253 mmuAttr2.attrIndx = 0U;
255 for (mmuAttr2.phyAddr[0U] = 0xA0000000U; mmuAttr2.phyAddr[0U] < 0xB0000000U;
256 mmuAttr2.phyAddr[0U] += 0x00200000U)
257 {
258 CSL_a15SetMmuSecondLevelLongDesc(&mmuObj, (void *)phyAddr, (void *)phyAddr, &mmuAttr2);
259 }
261 CSL_a15EnableMmu();
262 #if defined(CSL_ENABLE_CACHE_MMU) /* Enable CACHE */
263 CSL_a15EnableCache();
264 #endif
265 #else
266 mmuobj.numFirstLvlEntires = CSL_A15_MMU_SHORT_DESC_LVL1_ENTIRES;
267 CSL_a15InitMmuShortDesc(&mmuobj);
269 CSL_a15InitMmuShortDescAttrs(&mmuAttr0);
270 CSL_a15InitMmuShortDescAttrs(&mmuAttr1);
271 CSL_a15InitMmuShortDescAttrs(&mmuAttr2);
272 CSL_a15InitMmuShortDescAttrs(&mmuAttr3);
274 mmuAttr0.type = CSL_A15_MMU_SHORT_DESC_TYPE_SECTION;
275 mmuAttr0.accPerm = 0U;
277 for (phyAddr = 0x00000000U; phyAddr < 0x80000000U; phyAddr += 0x00100000)
278 {
279 CSL_a15SetMmuFirstLevelShortDesc(&mmuobj, (void *)phyAddr, (void *)phyAddr, &mmuAttr0);
280 }
282 mmuAttr1.type = CSL_A15_MMU_SHORT_DESC_TYPE_SECTION;
283 mmuAttr1.bufferable = 1U;
284 mmuAttr1.accPerm = 3U;
285 mmuAttr1.tex = 5U;
286 mmuAttr1.nonSecure = 1U;
288 for (phyAddr = 0x80000000U; phyAddr < 0xA0000000U; phyAddr += 0x00100000)
289 {
290 CSL_a15SetMmuFirstLevelShortDesc(&mmuobj, (void *)phyAddr, (void *)phyAddr, &mmuAttr1);
291 }
293 mmuAttr2.type = CSL_A15_MMU_SHORT_DESC_TYPE_SECTION;
294 mmuAttr2.accPerm = 0U;
296 for (phyAddr = 0xA0000000U; phyAddr < 0xC0000000U; phyAddr += 0x00100000)
297 {
298 CSL_a15SetMmuFirstLevelShortDesc(&mmuobj, (void *)phyAddr, (void *)phyAddr, &mmuAttr2);
299 }
301 mmuAttr3.type = CSL_A15_MMU_SHORT_DESC_TYPE_SECTION;
302 mmuAttr3.accPerm = 0U;
304 for (phyAddr = 0xC0000000U; phyAddr < 0xE0000000U; phyAddr += 0x00100000)
305 {
306 CSL_a15SetMmuFirstLevelShortDesc(&mmuobj, (void *)phyAddr, (void *)phyAddr, &mmuAttr3);
307 }
309 #if defined(CSL_ENABLE_CACHE_MMU) /* Enable CACHE */
310 CSL_a15EnableCache();
311 CSL_a15InvAllDataCache();
312 CSL_a15InvAllInstrCache();
313 CSL_a15EnableCache();
314 #endif
315 CSL_a15EnableMmu();
316 #endif
317 #endif
319 #if 1
320 gCpuIntrf.gicDist = &distrIntrf;
321 gCpuIntrf.cpuIntfBasePtr = (void *)CSL_MPU_INTC_MPU_PHYS_CPU_IF_REGS;
322 distrIntrf.distBasePtr = (void *)CSL_MPU_INTC_MPU_DISTRIBUTOR_REGS;
323 gCpuIntrf.initStatus = (Uint32)FALSE;
324 gCpuIntrf.gicDist->initStatus = (Uint32)FALSE;
325 gCpuIntrf.pDefaultIntrHandlers = NULL;
326 gCpuIntrf.pDefaultUserParameter = NULL;
328 CSL_armGicInit(&gCpuIntrf);
329 #endif
330 }