1 /**
2 * @file csl_cache.h
3 *
4 * @brief
5 * This is the CACHE Auxilary Header File which exposes the various
6 * CSL Functional Layer API's to configure the CACHE Module.
7 *
8 * \par
9 * ============================================================================
10 * @n (C) Copyright 2002, 2003, 2004, 2005, 2008, 2009, Texas Instruments, Inc.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 /** @defgroup CSL_CACHE_API CACHE
43 *
44 * @section Introduction
45 *
46 * @subsection xxx Overview
47 * This page describes the Functions, Data Structures, Enumerations and Macros
48 * within CACHE module.
49 *
50 * This module uses three cache architectures, Level 1 Program (L1P), Level 1
51 * Data (L1D) and Level 2 CACHE architectures, The L1P and L1D can be
52 * configured as 0K, 4K, 8K, 16K, or 32K CACHE size. The L2 can be configured
53 * as 32KB, 64KB, 128KB, or 256KB CACHE size. This CACHE module supports the
54 * Block and Global Coherence Operations.
55 *
56 * @subsection References
57 * -# TMS320TCI6484 Data Sheet SPRS438 (Dec 2007)
58 *
59 */
61 #ifndef _CSL_CACHE_H_
62 #define _CSL_CACHE_H_
64 #ifdef __cplusplus
65 extern "C" {
66 #endif
68 #include <ti/csl/csl.h>
69 #include <ti/csl/cslr_cgem.h>
70 #include <ti/csl/soc.h>
72 /**
73 @defgroup CSL_CACHE_SYMBOL CACHE Symbols Defined
74 @ingroup CSL_CACHE_API
75 */
76 /**
77 @defgroup CSL_CACHE_ENUM CACHE Enumerated Data Types
78 @ingroup CSL_CACHE_API
79 */
80 /**
81 @defgroup CSL_CACHE_FUNCTION CACHE Functions
82 @ingroup CSL_CACHE_API
83 */
86 /**
87 @addtogroup CSL_CACHE_SYMBOL
88 @{
89 */
90 /** L2 Line Size */
91 #define CACHE_L2_LINESIZE 128
92 /** L1D Line Size */
93 #define CACHE_L1D_LINESIZE 64
94 /** L1P Line Size */
95 #define CACHE_L1P_LINESIZE 32
97 /** Handle to the CGEM Register Layer */
98 #define hCache ((CSL_CgemRegs *)CSL_C66X_COREPAC_REG_BASE_ADDRESS_REGS)
100 /** Cache Round to Line size */
101 #define CACHE_ROUND_TO_LINESIZE(CACHE,ELCNT,ELSIZE)\
102 ( ( ( ( (ELCNT) * (ELSIZE)\
103 + CACHE_##CACHE##_LINESIZE - 1\
104 ) / CACHE_##CACHE##_LINESIZE\
105 * CACHE_##CACHE##_LINESIZE\
106 ) + (ELSIZE) - 1\
107 ) / (ELSIZE)\
108 )
109 /**
110 @}
111 */
113 /******************************************************************************\
114 * global macro declarations
115 \******************************************************************************/
117 /** @addtogroup CSL_CACHE_ENUM
118 @{ */
119 /** @brief Enumeration for Cache wait flags
120 *
121 * This is used for specifying whether the cache operations should block till
122 * the desired operation is complete.
123 */
124 typedef enum
125 {
126 /** No blocking, the call exits after programmation of the
127 * control registers
128 */
129 CACHE_NOWAIT = 0,
131 /** Blocking Call, the call exits after the relevant cache
132 * status registers indicate completion. For block coherence
133 * this waits on the Word count register to be come 0 along
134 * with invalidating the prefetch buffer.
135 */
136 CACHE_WAIT = 1,
138 /** Blocking Call, For block coherence this uses the MFENCE to
139 * wait for completion, along with invalidating the prefetch
140 * buffer.
141 */
142 CACHE_FENCE_WAIT = 2,
144 /** Blocking Call, the call exits after the relevant cache
145 * status registers indicate completion. For block coherence
146 * this waits on the Word count register to be come 0.
147 */
148 CACHE_ONLY_WAIT = 3,
150 /** Blocking Call, For block coherence this uses the MFENCE only to
151 * wait for completion
152 */
153 CACHE_FENCE_ONLY_WAIT = 4
155 }CACHE_Wait;
157 /** @brief Enumeration for L1 (P or D) Sizes */
159 typedef enum {
160 /** No Cache */
161 CACHE_L1_0KCACHE = 0,
162 /** 4KB Cache */
163 CACHE_L1_4KCACHE = 1,
164 /** 8KB Cache */
165 CACHE_L1_8KCACHE = 2,
166 /** 16KB Cache */
167 CACHE_L1_16KCACHE = 3,
168 /** 32KB Cache */
169 CACHE_L1_32KCACHE = 4,
170 /** MAX Cache Size */
171 CACHE_L1_MAXIM1 = 5,
172 /** MAX Cache Size */
173 CACHE_L1_MAXIM2 = 6,
174 /** MAX Cache Size */
175 CACHE_L1_MAXIM3 = 7
176 } CACHE_L1Size;
178 /** @brief Enumeration for L2 Sizes */
180 /** For devices that have maximum caches less
181 * than the defined values, setting a higher value
182 * will map to maximum cache
183 */
184 typedef enum {
185 /** No Cache */
186 CACHE_0KCACHE = 0,
187 /** 32KB Cache */
188 CACHE_32KCACHE = 1,
189 /** 64KB Cache */
190 CACHE_64KCACHE = 2,
191 /** 128KB Cache */
192 CACHE_128KCACHE = 3,
193 /** 256KB Cache */
194 CACHE_256KCACHE = 4,
195 /** 512KB Cache */
196 CACHE_512KCACHE = 5,
197 /* 1024KB Cache */
198 CACHE_1024KCACHE = 6
199 } CACHE_L2Size;
201 /**
202 @}
203 */
205 #ifdef __cplusplus
206 }
207 #endif
209 #endif /*_CSL_CACHE_H_*/