[processor-sdk/performance-audio-sr.git] / pdk_k2g_1_0_1_0_eng / packages / ti / csl / cslr_cppidma_rx_channel_config.h
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2 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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32 */
33 #ifndef _CSLR_CPPIDMA_RX_CHANNEL_CONFIG_H_
34 #define _CSLR_CPPIDMA_RX_CHANNEL_CONFIG_H_
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40 #include <ti/csl/cslr.h>
41 #include <ti/csl/tistdtypes.h>
44 /**************************************************************************
45 * Register Overlay Structure for RX_CHANNEL_GLOBAL_CONFIG
46 **************************************************************************/
47 typedef struct {
48 volatile Uint32 RX_CHANNEL_GLOBAL_CONFIG_REG;
49 volatile Uint8 RSVD0[28];
50 } CSL_Cppidma_rx_channel_configRx_channel_global_configRegs;
53 /**************************************************************************
54 * Register Overlay Structure
55 **************************************************************************/
56 typedef struct {
57 CSL_Cppidma_rx_channel_configRx_channel_global_configRegs RX_CHANNEL_GLOBAL_CONFIG[129];
58 } CSL_Cppidma_rx_channel_configRegs;
63 /**************************************************************************
64 * Register Macros
65 **************************************************************************/
67 /* RX_CHANNEL_GLOBAL_CONFIG_REG */
68 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG(n) (0x0U + ((n) * (0x20U)))
71 /**************************************************************************
72 * Field Definition Macros
73 **************************************************************************/
75 /* RX_CHANNEL_GLOBAL_CONFIG_REG */
77 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_MASK (0x20000000U)
78 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_SHIFT (29U)
79 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_RESETVAL (0x00000000U)
80 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_MAX (0x00000001U)
82 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_MASK (0x40000000U)
83 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_SHIFT (30U)
84 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_RESETVAL (0x00000000U)
85 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_MAX (0x00000001U)
87 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_MASK (0x80000000U)
88 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_SHIFT (31U)
89 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_RESETVAL (0x00000000U)
90 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_MAX (0x00000001U)
92 #define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RESETVAL (0x00000000U)
94 #ifdef __cplusplus
95 }
96 #endif
97 #endif