[processor-sdk/performance-audio-sr.git] / processor_audio_sdk_1_00_00_00 / pasdk / test_dsp / sap / sap_d10.c
2 /*
3 Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/
4 All rights reserved.
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12 *
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21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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34 */
36 //
37 // I/O device configuration data structure definitions D10 (DA10x EVM).
40 // -----------------------------------------------------------------------------
41 // This file contains the necessary configurations and functions for
42 // using the DA10x Audio DC card in the PA environment. In particular, the
43 // SAP configurations are referenced in the pa(i/y)-evmda10x-io.c files
44 // for use in IOS (Input/Output Switching) shortcuts. Each configuration
45 // contains settings appropriate to the various devices on the DA10x-AudioDC;
46 // the DIR, DACs, ADCs, and DIT output. Also each configuration points to
47 // a common control function (D10_sapControl), which handles the various
48 // requests made by the PA framework.
50 // A note about clocking. There are two different master clocks
51 // available corresponding to the two primary input choices, DIR and ADC.
52 //
53 // DIR:
54 // . 512fs @ <= 48kHz
55 // . 256fs @ > 48kHz & <=96 kHz
56 // . 128fs @ > 96kHz
57 // ADC:
58 // . 768fs @ 32kHz
59 // . 512fs @ 48kHz
60 // . 256fs @ 96kHz
61 //
62 // This faciliates the logic used for the McASP transmit sections TX0 (DAC) and
63 // TX2 (DIT) which divide the master clock down to generate bit and frame clocks.
65 // -----------------------------------------------------------------------------
66 // Includes
68 #include <sap_d10.h>
69 #include <audio_dc_cfg.h>
73 // -----------------------------------------------------------------------------
74 // Local function declarations
76 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg);
77 static inline XDAS_Int32 initD10 (DEV2_Handle device) ;
78 static XDAS_Int32 clockMuxTx (int sel, int force);
79 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut);
80 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX);
82 void HSR4_readStatus (PAF_SIO_InputStatus *pStatus);
83 unsigned int HDMIGpioGetState (void);
84 // -----------------------------------------------------------------------------
85 // State machine variables and defines
87 // flag to facilitate one time initialization of DA10x Audio hardware
88 // 0 ==> not initialized, 1 ==> initialized
89 static char initDone = 0;
91 // input status
92 static PAF_SIO_InputStatus primaryStatus =
93 {
94 0, // lock
95 PAF_IEC_AUDIOMODE_UNKNOWN, // nonaudio
96 PAF_IEC_PREEMPHASIS_UNKNOWN, // emphasis
97 PAF_SAMPLERATE_UNKNOWN, // sampleRateMeasured
98 PAF_SAMPLERATE_UNKNOWN, // sampleRateData
99 0,0,0, // unused
100 };
103 // The McASP outputs (both for DAC and DIT) receive a high speed clock
104 // and in turn generate a bit and frame clock. The needed clock divider
105 // values are kept here for easy lookup.
106 unsigned char *pClkxDiv = NULL;
108 static const unsigned char clkxDivDIR[PAF_SAMPLERATE_N] =
109 {
110 0x2, //PAF_SAMPLERATE_UNKNOWN
111 0x8, //PAF_SAMPLERATE_NONE
112 0x8, //PAF_SAMPLERATE_32000HZ
113 0x2, //PAF_SAMPLERATE_44100HZ
114 0x2, //PAF_SAMPLERATE_48000HZ
115 0x4, //PAF_SAMPLERATE_88200HZ
116 0x2, //PAF_SAMPLERATE_96000HZ
117 0x2, //PAF_SAMPLERATE_192000HZ
118 0x4, //PAF_SAMPLERATE_64000HZ
119 0x2, //PAF_SAMPLERATE_128000HZ
120 0x2, //PAF_SAMPLERATE_176400HZ
121 0x8, //PAF_SAMPLERATE_8000HZ
122 0x8, //PAF_SAMPLERATE_11025HZ
123 0x8, //PAF_SAMPLERATE_12000HZ
124 0x8, //PAF_SAMPLERATE_16000HZ
125 0x8, //PAF_SAMPLERATE_22050HZ
126 0x8, //PAF_SAMPLERATE_24000HZ
127 };
130 static const unsigned char clkxDivADC[PAF_SAMPLERATE_N] =
131 {
132 0x8, //PAF_SAMPLERATE_UNKNOWN
133 0x8, //PAF_SAMPLERATE_NONE
134 0xC, //PAF_SAMPLERATE_32000HZ
135 0x8, //PAF_SAMPLERATE_44100HZ
136 0x8, //PAF_SAMPLERATE_48000HZ
137 0x4, //PAF_SAMPLERATE_88200HZ
138 0x4, //PAF_SAMPLERATE_96000HZ
139 0x2, //PAF_SAMPLERATE_192000HZ
140 0x4, //PAF_SAMPLERATE_64000HZ
141 0x2, //PAF_SAMPLERATE_128000HZ
142 0x2, //PAF_SAMPLERATE_176400HZ
143 0x8, //PAF_SAMPLERATE_8000HZ
144 0x8, //PAF_SAMPLERATE_11025HZ
145 0x8, //PAF_SAMPLERATE_12000HZ
146 0x8, //PAF_SAMPLERATE_16000HZ
147 0x8, //PAF_SAMPLERATE_22050HZ
148 0x8, //PAF_SAMPLERATE_24000HZ
149 };
151 static const unsigned char clkxDivHDMI[PAF_SAMPLERATE_N] =
152 {
153 0x8, //PAF_SAMPLERATE_UNKNOWN
154 0x8, //PAF_SAMPLERATE_NONE
155 0x8, //PAF_SAMPLERATE_32000HZ
156 0x2, //PAF_SAMPLERATE_44100HZ
157 0x2, //PAF_SAMPLERATE_48000HZ
158 0x4, //PAF_SAMPLERATE_88200HZ
159 0x4, //PAF_SAMPLERATE_96000HZ
160 0x2, //PAF_SAMPLERATE_192000HZ
161 0x4, //PAF_SAMPLERATE_64000HZ
162 0x2, //PAF_SAMPLERATE_128000HZ
163 0x2, //PAF_SAMPLERATE_176400HZ
164 0x8, //PAF_SAMPLERATE_8000HZ
165 0x8, //PAF_SAMPLERATE_11025HZ
166 0x8, //PAF_SAMPLERATE_12000HZ
167 0x8, //PAF_SAMPLERATE_16000HZ
168 0x8, //PAF_SAMPLERATE_22050HZ
169 0x8, //PAF_SAMPLERATE_24000HZ
170 };
172 // The ADCs, when operating as the master input, can only
173 // generate a limited set of audio sample rates since the clock
174 // is derived from AUXCLK which is the oscillator connected to the DSP.
175 // This table faciliates the access and definition of these rates.
176 static const Uint16 oscRateTable[8] =
177 {
178 PAF_SAMPLERATE_UNKNOWN, // 0
179 PAF_SAMPLERATE_32000HZ,
180 PAF_SAMPLERATE_44100HZ, // D10_RATE_44_1KHZ
181 PAF_SAMPLERATE_48000HZ,
182 PAF_SAMPLERATE_88200HZ, // D10_RATE_88_2KHZ
183 PAF_SAMPLERATE_96000HZ,
184 PAF_SAMPLERATE_176400HZ, // D10_RATE_176_4KHZ
185 PAF_SAMPLERATE_192000HZ
186 };
188 static const Uint16 RateTable_hdmi[8] =
189 {
190 PAF_SAMPLERATE_UNKNOWN, // HSDIO_AudioFreq_RESERVED
191 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
192 PAF_SAMPLERATE_44100HZ, // HSDIO_AudioFreq_44_1K
193 PAF_SAMPLERATE_48000HZ, // HSDIO_AudioFreq_48K
194 PAF_SAMPLERATE_88200HZ, // HSDIO_AudioFreq_88_2K
195 PAF_SAMPLERATE_96000HZ, // HSDIO_AudioFreq_96_4K
196 PAF_SAMPLERATE_176400HZ, // HSDIO_AudioFreq_176_4K
197 PAF_SAMPLERATE_192000HZ // HSDIO_AudioFreq_192K
198 };
200 static const Uint16 RateTable_spdif[4] =
201 {
202 PAF_SAMPLERATE_44100HZ, // AudioFreq_44_1K
203 PAF_SAMPLERATE_48000HZ, // AudioFreq_48K
204 PAF_SAMPLERATE_UNKNOWN, // AudioFreq_RESERVED
205 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
206 };
209 // base mcasp addresses for easy lookup
210 static volatile Uint32 * mcaspAddr[_MCASP_PORT_CNT] =
211 {
212 (volatile Uint32 *) _MCASP_BASE_PORT0,
213 (volatile Uint32 *) _MCASP_BASE_PORT1,
214 (volatile Uint32 *) _MCASP_BASE_PORT2
215 };
217 // The DA10x HW is configured for the DAC's mute lines to be operated based
218 // on McASP0's AMUTE (out) line. This is the hard mute.
219 static inline void dacHardMute (void) {
220 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
221 mcasp0[_MCASP_PDOUT_OFFSET] |= _MCASP_PDOUT_AMUTE_MASK;
222 }
223 static inline void dacHardUnMute (void) {
224 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
225 mcasp0[_MCASP_PDOUT_OFFSET] &= ~_MCASP_PDOUT_AMUTE_MASK;
226 mcasp0[_MCASP_AMUTE_OFFSET] |= MCASP_AMUTE_MUTEN_ERRLOW;
227 }
229 // How should the PCM18x DAC's soft mute functionality be used here?
230 // i.e, as different from the hard mute? need to review.
231 static inline void dacSoftMute (void) {
232 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
233 mcasp0[6] = 0x000 ;
234 mcasp0[6] = 0x400 ;
235 }
236 static inline void dacSoftUnMute (void) {
237 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
238 mcasp0[6] = 0x000 ;
239 mcasp0[6] = 0x400 ;
240 }
242 // -----------------------------------------------------------------------------
243 // McASP Input Configuration Definitions
245 static const MCASP_ConfigRcv rxConfigDIR =
246 {
247 MCASP_RMASK_OF(0xFFFFFFFF),
248 MCASP_RFMT_RMK(
249 MCASP_RFMT_RDATDLY_1BIT,
250 MCASP_RFMT_RRVRS_MSBFIRST,
251 MCASP_RFMT_RPAD_RPBIT,
252 MCASP_RFMT_RPBIT_OF(0),
253 MCASP_RFMT_RSSZ_32BITS,
254 MCASP_RFMT_RBUSEL_DAT,
255 MCASP_RFMT_RROT_NONE),
256 MCASP_AFSRCTL_RMK(
257 MCASP_AFSRCTL_RMOD_OF(2),
258 MCASP_AFSRCTL_FRWID_WORD,
259 MCASP_AFSRCTL_FSRM_EXTERNAL,
260 MCASP_AFSRCTL_FSRP_ACTIVELOW),
261 MCASP_ACLKRCTL_RMK(
262 MCASP_ACLKRCTL_CLKRP_RISING,
263 MCASP_ACLKRCTL_CLKRM_EXTERNAL,
264 MCASP_ACLKRCTL_CLKRDIV_DEFAULT),
265 MCASP_AHCLKRCTL_RMK(
266 MCASP_AHCLKRCTL_HCLKRM_EXTERNAL,
267 MCASP_AHCLKRCTL_HCLKRP_RISING,
268 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
269 MCASP_RTDM_OF(3),
270 MCASP_RINTCTL_DEFAULT,
271 MCASP_RCLKCHK_DEFAULT
272 };
274 static const MCASP_ConfigRcv rxConfigADC =
275 {
276 MCASP_RMASK_OF(0xFFFFFFFF),
277 MCASP_RFMT_RMK(
278 MCASP_RFMT_RDATDLY_1BIT,
279 MCASP_RFMT_RRVRS_MSBFIRST,
280 MCASP_RFMT_RPAD_RPBIT,
281 MCASP_RFMT_RPBIT_OF(0),
282 MCASP_RFMT_RSSZ_32BITS,
283 MCASP_RFMT_RBUSEL_DAT,
284 MCASP_RFMT_RROT_NONE),
285 MCASP_AFSRCTL_RMK(
286 MCASP_AFSRCTL_RMOD_OF(2),
287 MCASP_AFSRCTL_FRWID_WORD,
288 MCASP_AFSRCTL_FSRM_INTERNAL,
289 MCASP_AFSRCTL_FSRP_ACTIVEHIGH),
290 MCASP_ACLKRCTL_RMK(
291 MCASP_ACLKRCTL_CLKRP_RISING,
292 MCASP_ACLKRCTL_CLKRM_INTERNAL,
293 MCASP_ACLKXCTL_CLKXDIV_OF(7)),
294 MCASP_AHCLKRCTL_RMK(
295 MCASP_AHCLKRCTL_HCLKRM_INTERNAL,
296 MCASP_AHCLKRCTL_HCLKRP_RISING,
297 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
298 MCASP_RTDM_OF(3),
299 MCASP_RINTCTL_DEFAULT,
300 MCASP_RCLKCHK_DEFAULT
301 };
303 // -----------------------------------------------------------------------------
304 // McASP Output Configuration Definitions
306 static const MCASP_ConfigXmt txConfigDAC =
307 {
308 MCASP_XMASK_OF(0xFFFFFFFF),
309 MCASP_XFMT_RMK(
310 MCASP_XFMT_XDATDLY_1BIT,
311 MCASP_XFMT_XRVRS_MSBFIRST,
312 MCASP_XFMT_XPAD_ZERO,
313 MCASP_XFMT_XPBIT_DEFAULT,
314 MCASP_XFMT_XSSZ_32BITS,
315 MCASP_XFMT_XBUSEL_DAT,
316 MCASP_XFMT_XROT_NONE),
317 MCASP_AFSXCTL_RMK(
318 MCASP_AFSXCTL_XMOD_OF(2),
319 MCASP_AFSXCTL_FXWID_WORD,
320 MCASP_AFSXCTL_FSXM_INTERNAL,
321 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
322 MCASP_ACLKXCTL_RMK(
323 MCASP_ACLKXCTL_CLKXP_FALLING,
324 MCASP_ACLKXCTL_ASYNC_ASYNC,
325 MCASP_ACLKXCTL_CLKXM_INTERNAL,
326 MCASP_ACLKXCTL_CLKXDIV_OF(1)),
327 MCASP_AHCLKXCTL_RMK(
328 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
329 MCASP_AHCLKXCTL_HCLKXP_FALLING,
330 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
331 MCASP_XTDM_OF(3),
332 MCASP_XINTCTL_DEFAULT,
333 MCASP_XCLKCHK_DEFAULT
334 };
336 static const MCASP_ConfigXmt txConfigDACSlave =
337 {
338 MCASP_XMASK_OF(0xFFFFFFFF),
339 MCASP_XFMT_RMK(
340 MCASP_XFMT_XDATDLY_1BIT,
341 MCASP_XFMT_XRVRS_MSBFIRST,
342 MCASP_XFMT_XPAD_ZERO,
343 MCASP_XFMT_XPBIT_DEFAULT,
344 MCASP_XFMT_XSSZ_32BITS,
345 MCASP_XFMT_XBUSEL_DAT,
346 MCASP_XFMT_XROT_NONE),
347 MCASP_AFSXCTL_RMK(
348 MCASP_AFSXCTL_XMOD_OF(2),
349 MCASP_AFSXCTL_FXWID_WORD,
350 MCASP_AFSXCTL_FSXM_INTERNAL,
351 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
352 MCASP_ACLKXCTL_RMK(
353 MCASP_ACLKXCTL_CLKXP_FALLING,
354 MCASP_ACLKXCTL_ASYNC_ASYNC,
355 MCASP_ACLKXCTL_CLKXM_INTERNAL,
356 MCASP_ACLKXCTL_CLKXDIV_OF(1)),
357 MCASP_AHCLKXCTL_RMK(
358 MCASP_AHCLKXCTL_HCLKXM_INTERNAL,
359 MCASP_AHCLKXCTL_HCLKXP_FALLING,
360 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
361 MCASP_XTDM_OF(3),
362 MCASP_XINTCTL_DEFAULT,
363 MCASP_XCLKCHK_DEFAULT
364 };
366 static const MCASP_ConfigXmt txConfigDIT =
367 {
368 MCASP_XMASK_OF(0x00FFFFFF),
369 MCASP_XFMT_RMK(
370 MCASP_XFMT_XDATDLY_1BIT,
371 MCASP_XFMT_XRVRS_LSBFIRST,
372 MCASP_XFMT_XPAD_DEFAULT,
373 MCASP_XFMT_XPBIT_DEFAULT,
374 MCASP_XFMT_XSSZ_32BITS,
375 MCASP_XFMT_XBUSEL_DAT,
376 MCASP_XFMT_XROT_NONE),
377 MCASP_AFSXCTL_RMK(
378 MCASP_AFSXCTL_XMOD_OF(0x180),
379 MCASP_AFSXCTL_FXWID_BIT,
380 MCASP_AFSXCTL_FSXM_INTERNAL,
381 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
382 MCASP_ACLKXCTL_RMK(
383 MCASP_ACLKXCTL_CLKXP_FALLING,
384 MCASP_ACLKXCTL_ASYNC_ASYNC,
385 MCASP_ACLKXCTL_CLKXM_INTERNAL,
386 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
387 MCASP_AHCLKXCTL_RMK(
388 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
389 MCASP_AHCLKXCTL_HCLKXP_FALLING,
390 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
391 MCASP_XTDM_OF(0xFFFFFFFF),
392 MCASP_XINTCTL_DEFAULT,
393 MCASP_XCLKCHK_DEFAULT
394 };
396 static const MCASP_ConfigXmt txConfigDIT_16bit =
397 {
398 MCASP_XMASK_OF(0x0000FFFF),
399 MCASP_XFMT_RMK(
400 MCASP_XFMT_XDATDLY_1BIT,
401 MCASP_XFMT_XRVRS_LSBFIRST,
402 MCASP_XFMT_XPAD_DEFAULT,
403 MCASP_XFMT_XPBIT_DEFAULT,
404 MCASP_XFMT_XSSZ_32BITS,
405 MCASP_XFMT_XBUSEL_DAT,
406 MCASP_XFMT_XROT_24BITS),
407 MCASP_AFSXCTL_RMK(
408 MCASP_AFSXCTL_XMOD_OF(0x180),
409 MCASP_AFSXCTL_FXWID_BIT,
410 MCASP_AFSXCTL_FSXM_INTERNAL,
411 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
412 MCASP_ACLKXCTL_RMK(
413 MCASP_ACLKXCTL_CLKXP_FALLING,
414 MCASP_ACLKXCTL_ASYNC_ASYNC,
415 MCASP_ACLKXCTL_CLKXM_INTERNAL,
416 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
417 MCASP_AHCLKXCTL_RMK(
418 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
419 MCASP_AHCLKXCTL_HCLKXP_FALLING,
420 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
421 MCASP_XTDM_OF(0xFFFFFFFF),
422 MCASP_XINTCTL_DEFAULT,
423 MCASP_XCLKCHK_DEFAULT
424 };
426 // -----------------------------------------------------------------------------
427 // DAP Input Parameter Definitions
429 const SAP_D10_Rx_Params SAP_D10_RX_DIR =
430 {
431 sizeof (SAP_D10_Rx_Params), // size
432 "SAP", // name
433 MCASP_DEV2, // moduleNum --> mcasp #
434 (Void *)&rxConfigDIR, // pConfig
435 4, // wordSize (unused)
436 24, // precision (unused)
437 D10_sapControl, // control
438 0x00000020, // pinMask
439 (D10_MCLK_DIR << D10_MCLK_SHIFT), // mode
440 0,0 // unused[2]
441 };
443 const SAP_D10_Rx_Params SAP_D10_RX_ADC_44100HZ =
444 {
445 sizeof (SAP_D10_Rx_Params), // size
446 "SAP", // name
447 MCASP_DEV1, // moduleNum --> mcasp #
448 (Void *)&rxConfigADC, // pConfig
449 4, // wordSize (unused)
450 24, // precision (unused)
451 D10_sapControl, // control
452 0xE000000F, // pinMask
453 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
454 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
455 0,0 // unused[2]
456 };
458 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_44100HZ =
459 {
460 sizeof (SAP_D10_Rx_Params), // size
461 "SAP", // name
462 MCASP_DEV1, // moduleNum --> mcasp #
463 (Void *)&rxConfigADC, // pConfig
464 -1, // wordSize (unused)
465 -1, // precision (unused)
466 D10_sapControl, // control
467 0xE0000007, // pinMask
468 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
469 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
470 0,0 // unused[2]
471 };
473 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_44100HZ =
474 {
475 sizeof (SAP_D10_Rx_Params), // size
476 "SAP", // name
477 MCASP_DEV1, // moduleNum --> mcasp #
478 (Void *)&rxConfigADC, // pConfig
479 -1, // wordSize (unused)
480 -1, // precision (unused)
481 D10_sapControl, // control
482 0xE0000001, // pinMask
483 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
484 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
485 0,0 // unused[2]
486 };
488 const SAP_D10_Rx_Params SAP_D10_RX_ADC_88200HZ =
489 {
490 sizeof (SAP_D10_Rx_Params), // size
491 "SAP", // name
492 MCASP_DEV1, // moduleNum --> mcasp #
493 (Void *)&rxConfigADC, // pConfig
494 -1, // wordSize (unused)
495 -1, // precision (unused)
496 D10_sapControl, // control
497 0xE000000F, // pinMask
498 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
499 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
500 0,0 // unused[2]
501 };
503 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_88200HZ =
504 {
505 sizeof (SAP_D10_Rx_Params), // size
506 "SAP", // name
507 MCASP_DEV1, // moduleNum --> mcasp #
508 (Void *)&rxConfigADC, // pConfig
509 -1, // wordSize (unused)
510 -1, // precision (unused)
511 D10_sapControl, // control
512 0xE0000007, // pinMask
513 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
514 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
515 0,0 // unused[2]
516 };
518 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_88200HZ =
519 {
520 sizeof (SAP_D10_Rx_Params), // size
521 "SAP", // name
522 MCASP_DEV1, // moduleNum --> mcasp #
523 (Void *)&rxConfigADC, // pConfig
524 -1, // wordSize (unused)
525 -1, // precision (unused)
526 D10_sapControl, // control
527 0xE0000001, // pinMask
528 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
529 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
530 0,0 // unused[2]
531 };
534 const SAP_D10_Rx_Params SAP_D10_RX_HDMI_STEREO =
535 {
536 sizeof (SAP_D10_Rx_Params), // size
537 "SAP", // name
538 MCASP_DEV0, // moduleNum --> mcasp #
539 (Void *)&rxConfigDIR, // pConfig
540 4, // wordSize (unused)
541 -1, // precision (unused)
542 D10_sapControl, // control
543 0x00001000, // pinMask
544 (D10_MODE_HDMI << D10_MODE_SHIFT) |
545 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
546 0,0 // unused[2]
547 };
549 const SAP_D10_Rx_Params SAP_D10_RX_HDMI =
550 {
551 sizeof (SAP_D10_Rx_Params), // size
552 "SAP", // name
553 MCASP_DEV0, // moduleNum --> mcasp #
554 (Void *)&rxConfigDIR, // pConfig
555 4, // wordSize (unused)
556 -1, // precision (unused)
557 D10_sapControl, // control
558 0xE000F000, // pinMask
559 (D10_MODE_HDMI << D10_MODE_SHIFT) |
560 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
561 0,0 // unused[2]
562 };
564 // -----------------------------------------------------------------------------
565 // SAP Output Parameter Definitions
567 const SAP_D10_Tx_Params SAP_D10_TX_DAC =
568 {
569 sizeof (SAP_D10_Tx_Params), // size
570 "SAP", // name
571 MCASP_DEV0, // moduleNum --> mcasp #
572 (Void *)&txConfigDAC, // pConfig
573 4, // wordSize (in bytes)
574 24, // precision (in bits)
575 D10_sapControl, // control
576 0x1600000F, // pinMask
577 0, // mode
578 0,0,0 // unused[3]
579 };
581 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC =
582 {
583 sizeof (SAP_D10_Tx_Params), // size
584 "SAP", // name
585 MCASP_DEV0, // moduleNum --> mcasp #
586 (Void *)&txConfigDAC, // pConfig
587 4, // wordSize (in bytes)
588 24, // precision (in bits)
589 D10_sapControl, // control
590 0x16000001, // pinMask
591 0, // mode
592 0,0,0 // unused[3]
593 };
595 const SAP_D10_Tx_Params SAP_D10_TX_DIT =
596 {
597 sizeof (SAP_D10_Tx_Params), // size
598 "SAP", // name
599 MCASP_DEV2, // moduleNum --> mcasp #
600 (Void *) &txConfigDIT, // pConfig
601 3, // wordSize (in bytes)
602 24, // precision (in bits)
603 D10_sapControl, // control
604 0x1C000001, // pinMask
605 0, // mode
606 0,0,0 // unused[3]
607 };
609 const SAP_D10_Tx_Params SAP_D10_TX_DAC_SLAVE =
610 {
611 sizeof (SAP_D10_Tx_Params), // size
612 "SAP", // name
613 MCASP_DEV0, // moduleNum --> mcasp #
614 (Void *)&txConfigDACSlave, // pConfig
615 4, // wordSize (in bytes)
616 24, // precision (in bits)
617 D10_sapControl, // control
618 0x1E00000F, // pinMask
619 0, // mode
620 0,0,0 // unused[3]
621 };
623 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC_SLAVE =
624 {
625 sizeof (SAP_D10_Tx_Params), // size
626 "SAP", // name
627 MCASP_DEV0, // moduleNum --> mcasp #
628 (Void *)&txConfigDAC, // pConfig
629 4, // wordSize (in bytes)
630 24, // precision (in bits)
631 D10_sapControl, // control
632 0x16000001, // pinMask
633 0, // mode
634 0,0,0 // unused[3]
635 };
638 // -----------------------------------------------------------------------------
639 // One time initialization of the DA10x audio hardware.
641 /* DAC default configuration parameters */
642 DacConfig dacCfg =
643 {
644 DAC_AMUTE_CTRL_SCKI_LOST, /* Amute event */
645 0, /* Amute control */
646 DAC_SAMPLING_MODE_SINGLE_RATE, /* Sampling mode */
647 DAC_DATA_FORMAT_I2S, /* Data format */
648 0, /* Soft mute control */
649 DAC_ATTENUATION_WIDE_RANGE, /* Attenuation mode */
650 DAC_DEEMP_44KHZ, /* De-emph control */
651 100 /* Volume */
652 };
653 /* ADC default configuration parameters */
654 AdcConfig adcCfg =
655 {
656 90, /* ADC gain */
657 ADC_INL_SE_VINL1, /* Left input mux for ADC1L */
658 ADC_INL_SE_VINL2, /* Left input mux for ADC2L */
659 ADC_INR_SE_VINR1, /* Right input mux for ADC1R */
660 ADC_INR_SE_VINR2, /* Right input mux for ADC2R */
661 ADC_RX_WLEN_24BIT, /* ADC word length */
662 ADC_DATA_FORMAT_I2S, /* ADC data format */
663 0
664 };
666 Platform_STATUS setAudioDacConfig(void)
667 {
668 Platform_STATUS status;
670 /* Initialize Audio DAC module */
671 status = audioDacConfig(DAC_DEVICE_ALL, &dacCfg);
672 if (status)
673 Log_info0("SAP_D10: Audio DAC Configuration Failed!!!\n");
674 return status;
676 }
678 static inline XDAS_Int32 initD10 (DEV2_Handle device)
679 {
680 Platform_STATUS status = Platform_EOK;
682 /* Initialize common audio configurations */
683 status = platformAudioInit();
684 if(status != Platform_EOK)
685 {
686 System_printf("Audio Init Failed!\n");
687 return status;
688 }
690 /* Initialize Audio ADC module */
691 status = audioAdcConfig(ADC_DEVICE_ALL, &adcCfg);
692 if(status != Platform_EOK)
693 {
694 platform_write("Audio ADC Configuration Failed!\n");
695 return status;
696 }
698 /* Setup DIR 9001 for SPDIF input operation */
699 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
700 status = audioDirConfig();
701 if(status != Platform_EOK)
702 {
703 Log_info0("Audio DIR Init Failed!\n");
704 return status;
705 }
707 #if 1
708 /* Setup HSR41 for HDMI input operation */
709 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
710 /* Initialize the HDMI Card */
711 status = audioHDMIConfig();
712 if(status != Platform_EOK)
713 {
714 Log_info0("Audio HDMI Init Failed!\n");
715 return status;
716 }
717 #endif
719 // This is needed because DAC configuration needs some default clocking.
720 // We start with S/PDIF, because it's onboard the Audio DC & has its own crystal.
721 // HDMI is an add-on board & Audio OSC would need AUX clocking - both unfit for "default".
722 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
724 platform_delay(20000); // Without delay between these 2 calls system aborts.
726 status = setAudioDacConfig();
728 return status;
730 } //initD10
732 // -----------------------------------------------------------------------------
733 // The McASP TX section is *only* used as a master clock mux.
734 // Mux functionality is achieved by selecting either external high
735 // speed clocks (DIR/HDMI) or the internal AUXCLK (Audio_OSC). This is divided down
736 // output via ACLKX0 which is connected to the high speed input
737 // of TX0 (DAC) and TX2 (DIT).
739 static XDAS_Int32 clockMuxTx (int sel, int force)
740 {
741 Platform_STATUS status = 0;
742 // select clkxDiv table
743 if (sel == D10_MCLK_DIR)
744 {
745 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
746 pClkxDiv = (unsigned char *) clkxDivDIR;
747 }
748 else if (sel == D10_MCLK_HDMI)
749 {
750 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
751 pClkxDiv = (unsigned char *) clkxDivHDMI;
752 }
753 else if (sel == D10_MCLK_OSC)
754 {
755 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_OSC);
756 pClkxDiv = (unsigned char *) clkxDivADC;
757 }
759 platform_delay(20000);
761 return status;
762 } //clockMuxTx
765 // -----------------------------------------------------------------------------
766 // This function returns the input status of the specified device.
767 // This is called once when the device is opened
768 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter
769 // (PAF_SIO_CONTROL_GET_INPUT_STATUS).
771 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut)
772 {
773 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
774 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
775 volatile Uint32 *mcasp1 = (volatile Uint32 *) _MCASP_BASE_PORT1;
776 volatile Uint32 *mcasp2 = (volatile Uint32 *) _MCASP_BASE_PORT2;
778 Platform_STATUS status;
780 static int PrevSampRate = 0;
781 int Rate_spdif=0;
783 if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_DIR) &
784 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD))
785 {
786 pStatusIn->lock = !(platformAudioDirGetClkStatus());
787 pStatusIn->nonaudio = !(platformAudioDirGetAudioStatus());
788 pStatusIn->emphasis = platformAudioDirGetEmphStatus();
789 pStatusIn->sampleRateMeasured = RateTable_spdif[platformAudioDirGetFsOut()];
790 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
791 PrevSampRate = pStatusIn->sampleRateMeasured;
793 // GJ: Is this needed? Probably not.
794 mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
795 mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
797 }
798 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_OSC) &
799 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD)) {
800 int adcRate = (pParams->d10rx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
801 int regData;
803 pStatusIn->lock = 1;
804 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
805 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
806 pStatusIn->sampleRateMeasured = oscRateTable[adcRate];
807 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
809 }
810 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_HDMI) &
811 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_HDMI))
812 {
813 pStatusIn->lock = 1;
814 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
815 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
818 if(!HDMIGpioGetState()) {
819 HSR4_readStatus (pStatusIn);
820 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
821 PrevSampRate = pStatusIn->sampleRateMeasured;
822 }
823 else {
824 pStatusIn->sampleRateMeasured = PrevSampRate;
825 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
826 }
828 }
829 else
830 return -1;
832 // update another status if requested
833 if (pStatusOut)
834 *pStatusOut = *pStatusIn;
836 return 0;
837 } //manageInput
840 // -----------------------------------------------------------------------------
841 // This function configures the McASP TX clock dividers based on the
842 // master clock rate. This is called once when the device is opened
843 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter (PAF_SIO_CONTROL_SET_RATEX).
845 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX)
846 {
847 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
848 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
849 Uint32 divider;
852 if (!pClkxDiv)
853 return 1;
855 // set clock divider
856 if (rateX < .354)
857 rateX = 0.25;
858 else if (rateX < .707)
859 rateX = 0.50;
860 else if (rateX < 1.6)
861 rateX = 1.00;
862 else if (rateX < 2.828)
863 rateX = 2.00;
864 else
865 rateX = 4.00;
866 // if asynchronous then force clock change (assumes osc master)
867 if (pParams->d10tx.mode & D10_SYNC_MASK) {
868 int dacRate = (pParams->d10tx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
869 divider = pClkxDiv[oscRateTable[dacRate]];
870 }
871 else
872 divider = pClkxDiv[pStatusIn->sampleRateMeasured];
873 divider /= rateX;
875 Log_info2("SAP_D10: Inside manageOutput with divider = %d, rateX = %d", divider, rateX);
877 // DIT requires 2x clock
878 if ((mcasp[_MCASP_AFSXCTL_OFFSET] & _MCASP_AFSXCTL_XMOD_MASK) ==
879 (MCASP_AFSXCTL_XMOD_OF(0x180) << _MCASP_AFSXCTL_XMOD_SHIFT)) {
880 if (divider < 2)
881 return (SIO2_EINVAL);
882 divider >>= 1;
883 }
885 mcasp[_MCASP_ACLKXCTL_OFFSET] =
886 (mcasp[_MCASP_ACLKXCTL_OFFSET] & ~_MCASP_ACLKXCTL_CLKXDIV_MASK) |
887 (MCASP_ACLKXCTL_CLKXDIV_OF(divider-1) << _MCASP_ACLKXCTL_CLKXDIV_SHIFT);
888 return 0;
889 } //manageOutput
891 // -----------------------------------------------------------------------------
892 // This function is called by the peripheral driver (DAP) in response to
893 // various SIO_ctrl() calls made by the framework.
895 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg)
896 {
897 const SAP_D10_Rx_Params *pDapD10RxParams = (const SAP_D10_Rx_Params *)pParams;
898 const SAP_D10_Tx_Params *pDapD10TxParams = (const SAP_D10_Tx_Params *)pParams;
899 Platform_STATUS status;
901 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
902 XDAS_Int32 result = 0;
904 // perform one time hardware initialization
905 if (!initDone) {
906 result = initD10 (device);
907 if (result)
908 return result;
909 initDone = 1;
910 }
912 switch (code) {
914 // .............................................................................
915 // This case provides a regular entry point for managing the specified
916 // input device. Nominally, this is used to provide lock and sample rate
917 // status to the framework.
919 case PAF_SIO_CONTROL_GET_INPUT_STATUS:
920 if (device->mode != DEV2_INPUT)
921 return SIO2_EINVAL;
923 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
924 break;
926 // .............................................................................
927 // This case provides a regular entry point for managing the specified
928 // output device. Nominally this is used to change the output clock dividers
929 // in the case of double rate output (e.g. DTS 96/24).
931 case PAF_SIO_CONTROL_SET_RATEX:
932 // Support only output rate control, for now
933 if (device->mode != DEV2_OUTPUT)
934 return (SIO2_EINVAL);
936 // configure clock divider (bit and frame clocks)
937 manageOutput (device, pDapD10TxParams, *((float *) arg));
938 break;
940 // .............................................................................
941 // This case is called once when the device is opened/allocated by the framework.
942 // Here, for both input and output, this allows for configuring all needed
943 // clocks for proper operation.
945 case PAF_SIO_CONTROL_OPEN:
946 if (device->mode == DEV2_INPUT) {
948 // determine the master clock based on the mode element of the
949 // parameter configuration.
950 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
951 manageInput (device, pDapD10RxParams, NULL);
953 // select appropriate master clock (but dont force)
955 clockMuxTx (sel, -1);
957 }
958 else {
960 // Since DAC is a slave to the chosen input, operate the clksel switch appropriately
961 // Also, this is a create-time (i.e, CTRL_OPEN) only call & not appropriate under
962 // the periodic manage_(in/out)put calls
963 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
964 clockMuxTx (sel, -1);
965 platform_delay(20000); // Without delay between Tx McASP & DAC configs, system aborts.
966 setAudioDacConfig();
967 dacHardUnMute ();
969 // configure clock divider (bit and frame clocks)
970 manageOutput (device, pDapD10TxParams, 1.0);
971 }
972 break;
974 // .............................................................................
975 // This case is called once when the device is closed/freed by the framework.
977 case PAF_SIO_CONTROL_CLOSE:
978 // If TX0 then signal it is no longer in use by the DACs and
979 // configure manually to generate ADC clocks. Also hard mute
980 // the DACs since they are not in use.
981 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0)) {
983 dacHardMute ();
985 // if async then clear forced clock mux
986 // if asynchronous then force clock change
987 if (pDapD10TxParams->d10tx.mode & D10_SYNC_MASK)
988 clockMuxTx (0, 0);
989 }
990 break;
992 // .............................................................................
993 // These cases are called as appropriate by the framework when there is
994 // valid output data (UNMUTE) or no valid output (MUTE).
996 case PAF_SIO_CONTROL_MUTE:
997 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
998 dacSoftMute ();
999 break;
1001 case PAF_SIO_CONTROL_UNMUTE:
1002 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1003 dacSoftUnMute ();
1004 break;
1006 // .............................................................................
1007 // This case is called when the device is idled.
1008 // There is no specific handling -- but needed to avoid error return.
1010 case PAF_SIO_CONTROL_IDLE:
1011 break;
1013 // .............................................................................
1014 // Called from the IDL Loop to allow for clock management and the like
1015 // The call is protected by a TSK_disable and HWI_disable so it is safe
1016 // to read/write shared resources.
1018 case PAF_SIO_CONTROL_WATCHDOG:
1019 // call manageInput in case the sample rate has changed resulting
1020 // in no output clocks which may have blocked the audio processing
1021 // thread. This call will reconfigure the AK4588 and restart the clocks.
1022 if (device->mode == DEV2_INPUT)
1023 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1024 break;
1026 // .............................................................................
1027 // Called from DOB_issue to allow for different values of the channel status
1028 // fields of the SPDIF output.
1030 case PAF_SIO_CONTROL_SET_DITSTATUS:
1031 // No action necessary.
1032 break;
1034 case PAF_SIO_CONTROL_SET_WORDSIZE:
1035 if(((pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) != D10_MCLK_OSC)
1036 {
1037 if ((device->mode == DEV2_INPUT) && (arg == 2))
1038 {
1039 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=2");
1040 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_16BITS;
1041 }
1042 else if ((device->mode == DEV2_INPUT) && (arg == 4))
1043 {
1044 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=4");
1045 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_NONE;
1046 }
1047 }
1048 break;
1049 // .............................................................................
1050 // Any other cases are not handled and return an error.
1052 default:
1053 return SIO2_EINVAL;
1054 }
1056 return result;
1057 } //D10_sapControl
1059 // -----------------------------------------------------------------------------
1062 extern unsigned int read_hdmi_samprate();
1063 int RateHdmi=0;
1064 void HSR4_readStatus (PAF_SIO_InputStatus *pStatus)
1065 {
1066 //if(!RateHdmi)
1067 RateHdmi=read_hdmi_samprate();
1068 pStatus->sampleRateMeasured = RateTable_hdmi[RateHdmi];
1069 }
1071 unsigned int HDMIGpioGetState (void) {
1072 return(gpioReadInput(GPIO_PORT_0, PLATFORM_AUDIO_HSR_HMINTz_GPIO));
1073 }
1075 // EOF