[processor-sdk/performance-audio-sr.git] / processor_audio_sdk_1_00_00_00 / pasdk / test_dsp / sap / sap_d10.c
1 /*
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3 * All rights reserved.
4 *
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19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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33 */
34 //
35 // I/O device configuration data structure definitions D10 (DA10x EVM).
38 // -----------------------------------------------------------------------------
39 // This file contains the necessary configurations and functions for
40 // using the DA10x Audio DC card in the PA environment. In particular, the
41 // SAP configurations are referenced in the pa(i/y)-evmda10x-io.c files
42 // for use in IOS (Input/Output Switching) shortcuts. Each configuration
43 // contains settings appropriate to the various devices on the DA10x-AudioDC;
44 // the DIR, DACs, ADCs, and DIT output. Also each configuration points to
45 // a common control function (D10_sapControl), which handles the various
46 // requests made by the PA framework.
48 // A note about clocking. There are two different master clocks
49 // available corresponding to the two primary input choices, DIR and ADC.
50 //
51 // DIR:
52 // . 512fs @ <= 48kHz
53 // . 256fs @ > 48kHz & <=96 kHz
54 // . 128fs @ > 96kHz
55 // ADC:
56 // . 768fs @ 32kHz
57 // . 512fs @ 48kHz
58 // . 256fs @ 96kHz
59 //
60 // This faciliates the logic used for the McASP transmit sections TX0 (DAC) and
61 // TX2 (DIT) which divide the master clock down to generate bit and frame clocks.
63 // -----------------------------------------------------------------------------
64 // Includes
66 #include <sap_d10.h>
67 #include <audio_dc_cfg.h>
71 // -----------------------------------------------------------------------------
72 // Local function declarations
74 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg);
75 static inline XDAS_Int32 initD10 (DEV2_Handle device) ;
76 static XDAS_Int32 clockMuxTx (int sel, int force);
77 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut);
78 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX);
80 void HSR4_readStatus (PAF_SIO_InputStatus *pStatus);
81 unsigned int HDMIGpioGetState (void);
82 // -----------------------------------------------------------------------------
83 // State machine variables and defines
85 // flag to facilitate one time initialization of DA10x Audio hardware
86 // 0 ==> not initialized, 1 ==> initialized
87 static char initDone = 0;
89 // input status
90 static PAF_SIO_InputStatus primaryStatus =
91 {
92 0, // lock
93 PAF_IEC_AUDIOMODE_UNKNOWN, // nonaudio
94 PAF_IEC_PREEMPHASIS_UNKNOWN, // emphasis
95 PAF_SAMPLERATE_UNKNOWN, // sampleRateMeasured
96 PAF_SAMPLERATE_UNKNOWN, // sampleRateData
97 0,0,0, // unused
98 };
101 // The McASP outputs (both for DAC and DIT) receive a high speed clock
102 // and in turn generate a bit and frame clock. The needed clock divider
103 // values are kept here for easy lookup.
104 unsigned char *pClkxDiv = NULL;
106 static const unsigned char clkxDivDIR[PAF_SAMPLERATE_N] =
107 {
108 0x2, //PAF_SAMPLERATE_UNKNOWN
109 0x8, //PAF_SAMPLERATE_NONE
110 0x8, //PAF_SAMPLERATE_32000HZ
111 0x2, //PAF_SAMPLERATE_44100HZ
112 0x2, //PAF_SAMPLERATE_48000HZ
113 0x4, //PAF_SAMPLERATE_88200HZ
114 0x2, //PAF_SAMPLERATE_96000HZ
115 0x2, //PAF_SAMPLERATE_192000HZ
116 0x4, //PAF_SAMPLERATE_64000HZ
117 0x2, //PAF_SAMPLERATE_128000HZ
118 0x2, //PAF_SAMPLERATE_176400HZ
119 0x8, //PAF_SAMPLERATE_8000HZ
120 0x8, //PAF_SAMPLERATE_11025HZ
121 0x8, //PAF_SAMPLERATE_12000HZ
122 0x8, //PAF_SAMPLERATE_16000HZ
123 0x8, //PAF_SAMPLERATE_22050HZ
124 0x8, //PAF_SAMPLERATE_24000HZ
125 };
128 static const unsigned char clkxDivADC[PAF_SAMPLERATE_N] =
129 {
130 0x8, //PAF_SAMPLERATE_UNKNOWN
131 0x8, //PAF_SAMPLERATE_NONE
132 0xC, //PAF_SAMPLERATE_32000HZ
133 0x8, //PAF_SAMPLERATE_44100HZ
134 0x8, //PAF_SAMPLERATE_48000HZ
135 0x4, //PAF_SAMPLERATE_88200HZ
136 0x4, //PAF_SAMPLERATE_96000HZ
137 0x2, //PAF_SAMPLERATE_192000HZ
138 0x4, //PAF_SAMPLERATE_64000HZ
139 0x2, //PAF_SAMPLERATE_128000HZ
140 0x2, //PAF_SAMPLERATE_176400HZ
141 0x8, //PAF_SAMPLERATE_8000HZ
142 0x8, //PAF_SAMPLERATE_11025HZ
143 0x8, //PAF_SAMPLERATE_12000HZ
144 0x8, //PAF_SAMPLERATE_16000HZ
145 0x8, //PAF_SAMPLERATE_22050HZ
146 0x8, //PAF_SAMPLERATE_24000HZ
147 };
149 static const unsigned char clkxDivHDMI[PAF_SAMPLERATE_N] =
150 {
151 0x8, //PAF_SAMPLERATE_UNKNOWN
152 0x8, //PAF_SAMPLERATE_NONE
153 0x8, //PAF_SAMPLERATE_32000HZ
154 0x8, //PAF_SAMPLERATE_44100HZ
155 0x2, //PAF_SAMPLERATE_48000HZ
156 0x4, //PAF_SAMPLERATE_88200HZ
157 0x4, //PAF_SAMPLERATE_96000HZ
158 0x2, //PAF_SAMPLERATE_192000HZ
159 0x4, //PAF_SAMPLERATE_64000HZ
160 0x2, //PAF_SAMPLERATE_128000HZ
161 0x2, //PAF_SAMPLERATE_176400HZ
162 0x8, //PAF_SAMPLERATE_8000HZ
163 0x8, //PAF_SAMPLERATE_11025HZ
164 0x8, //PAF_SAMPLERATE_12000HZ
165 0x8, //PAF_SAMPLERATE_16000HZ
166 0x8, //PAF_SAMPLERATE_22050HZ
167 0x8, //PAF_SAMPLERATE_24000HZ
168 };
170 // The ADCs, when operating as the master input, can only
171 // generate a limited set of audio sample rates since the clock
172 // is derived from AUXCLK which is the oscillator connected to the DSP.
173 // This table faciliates the access and definition of these rates.
174 static const Uint16 oscRateTable[8] =
175 {
176 PAF_SAMPLERATE_UNKNOWN, // 0
177 PAF_SAMPLERATE_32000HZ,
178 PAF_SAMPLERATE_44100HZ, // D10_RATE_44_1KHZ
179 PAF_SAMPLERATE_48000HZ,
180 PAF_SAMPLERATE_88200HZ, // D10_RATE_88_2KHZ
181 PAF_SAMPLERATE_96000HZ,
182 PAF_SAMPLERATE_176400HZ, // D10_RATE_176_4KHZ
183 PAF_SAMPLERATE_192000HZ
184 };
186 static const Uint16 RateTable_hdmi[8] =
187 {
188 PAF_SAMPLERATE_UNKNOWN, // HSDIO_AudioFreq_RESERVED
189 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
190 PAF_SAMPLERATE_44100HZ, // HSDIO_AudioFreq_44_1K
191 PAF_SAMPLERATE_48000HZ, // HSDIO_AudioFreq_48K
192 PAF_SAMPLERATE_88200HZ, // HSDIO_AudioFreq_88_2K
193 PAF_SAMPLERATE_96000HZ, // HSDIO_AudioFreq_96_4K
194 PAF_SAMPLERATE_176400HZ, // HSDIO_AudioFreq_176_4K
195 PAF_SAMPLERATE_192000HZ // HSDIO_AudioFreq_192K
196 };
198 static const Uint16 RateTable_spdif[4] =
199 {
200 PAF_SAMPLERATE_44100HZ, // AudioFreq_44_1K
201 PAF_SAMPLERATE_48000HZ, // AudioFreq_48K
202 PAF_SAMPLERATE_UNKNOWN, // AudioFreq_RESERVED
203 PAF_SAMPLERATE_32000HZ, // HSDIO_AudioFreq_32K
204 };
207 // base mcasp addresses for easy lookup
208 static volatile Uint32 * mcaspAddr[_MCASP_PORT_CNT] =
209 {
210 (volatile Uint32 *) _MCASP_BASE_PORT0,
211 (volatile Uint32 *) _MCASP_BASE_PORT1,
212 (volatile Uint32 *) _MCASP_BASE_PORT2
213 };
215 // The DA10x HW is configured for the DAC's mute lines to be operated based
216 // on McASP0's AMUTE (out) line. This is the hard mute.
217 static inline void dacHardMute (void) {
218 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
219 mcasp0[_MCASP_PDOUT_OFFSET] |= _MCASP_PDOUT_AMUTE_MASK;
220 }
221 static inline void dacHardUnMute (void) {
222 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
223 mcasp0[_MCASP_PDOUT_OFFSET] &= ~_MCASP_PDOUT_AMUTE_MASK;
224 mcasp0[_MCASP_AMUTE_OFFSET] |= MCASP_AMUTE_MUTEN_ERRLOW;
225 }
227 // How should the PCM18x DAC's soft mute functionality be used here?
228 // i.e, as different from the hard mute? need to review.
229 static inline void dacSoftMute (void) {
230 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
231 mcasp0[6] = 0x000 ;
232 mcasp0[6] = 0x400 ;
233 }
234 static inline void dacSoftUnMute (void) {
235 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
236 mcasp0[6] = 0x000 ;
237 mcasp0[6] = 0x400 ;
238 }
240 // -----------------------------------------------------------------------------
241 // McASP Input Configuration Definitions
243 static const MCASP_ConfigRcv rxConfigDIR =
244 {
245 MCASP_RMASK_OF(0xFFFFFFFF),
246 MCASP_RFMT_RMK(
247 MCASP_RFMT_RDATDLY_1BIT,
248 MCASP_RFMT_RRVRS_MSBFIRST,
249 MCASP_RFMT_RPAD_RPBIT,
250 MCASP_RFMT_RPBIT_OF(0),
251 MCASP_RFMT_RSSZ_32BITS,
252 MCASP_RFMT_RBUSEL_DAT,
253 MCASP_RFMT_RROT_NONE),
254 MCASP_AFSRCTL_RMK(
255 MCASP_AFSRCTL_RMOD_OF(2),
256 MCASP_AFSRCTL_FRWID_WORD,
257 MCASP_AFSRCTL_FSRM_EXTERNAL,
258 MCASP_AFSRCTL_FSRP_ACTIVELOW),
259 MCASP_ACLKRCTL_RMK(
260 MCASP_ACLKRCTL_CLKRP_RISING,
261 MCASP_ACLKRCTL_CLKRM_EXTERNAL,
262 MCASP_ACLKRCTL_CLKRDIV_DEFAULT),
263 MCASP_AHCLKRCTL_RMK(
264 MCASP_AHCLKRCTL_HCLKRM_EXTERNAL,
265 MCASP_AHCLKRCTL_HCLKRP_RISING,
266 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
267 MCASP_RTDM_OF(3),
268 MCASP_RINTCTL_DEFAULT,
269 MCASP_RCLKCHK_DEFAULT
270 };
272 static const MCASP_ConfigRcv rxConfigADC =
273 {
274 MCASP_RMASK_OF(0xFFFFFFFF),
275 MCASP_RFMT_RMK(
276 MCASP_RFMT_RDATDLY_1BIT,
277 MCASP_RFMT_RRVRS_MSBFIRST,
278 MCASP_RFMT_RPAD_RPBIT,
279 MCASP_RFMT_RPBIT_OF(0),
280 MCASP_RFMT_RSSZ_32BITS,
281 MCASP_RFMT_RBUSEL_DAT,
282 MCASP_RFMT_RROT_NONE),
283 MCASP_AFSRCTL_RMK(
284 MCASP_AFSRCTL_RMOD_OF(2),
285 MCASP_AFSRCTL_FRWID_WORD,
286 MCASP_AFSRCTL_FSRM_INTERNAL,
287 MCASP_AFSRCTL_FSRP_ACTIVEHIGH),
288 MCASP_ACLKRCTL_RMK(
289 MCASP_ACLKRCTL_CLKRP_RISING,
290 MCASP_ACLKRCTL_CLKRM_INTERNAL,
291 MCASP_ACLKXCTL_CLKXDIV_OF(7)),
292 MCASP_AHCLKRCTL_RMK(
293 MCASP_AHCLKRCTL_HCLKRM_INTERNAL,
294 MCASP_AHCLKRCTL_HCLKRP_RISING,
295 MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
296 MCASP_RTDM_OF(3),
297 MCASP_RINTCTL_DEFAULT,
298 MCASP_RCLKCHK_DEFAULT
299 };
301 // -----------------------------------------------------------------------------
302 // McASP Output Configuration Definitions
304 static const MCASP_ConfigXmt txConfigDAC =
305 {
306 MCASP_XMASK_OF(0xFFFFFFFF),
307 MCASP_XFMT_RMK(
308 MCASP_XFMT_XDATDLY_1BIT,
309 MCASP_XFMT_XRVRS_MSBFIRST,
310 MCASP_XFMT_XPAD_ZERO,
311 MCASP_XFMT_XPBIT_DEFAULT,
312 MCASP_XFMT_XSSZ_32BITS,
313 MCASP_XFMT_XBUSEL_DAT,
314 MCASP_XFMT_XROT_NONE),
315 MCASP_AFSXCTL_RMK(
316 MCASP_AFSXCTL_XMOD_OF(2),
317 MCASP_AFSXCTL_FXWID_WORD,
318 MCASP_AFSXCTL_FSXM_INTERNAL,
319 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
320 MCASP_ACLKXCTL_RMK(
321 MCASP_ACLKXCTL_CLKXP_FALLING,
322 MCASP_ACLKXCTL_ASYNC_ASYNC,
323 MCASP_ACLKXCTL_CLKXM_INTERNAL,
324 MCASP_ACLKXCTL_CLKXDIV_OF(1)),
325 MCASP_AHCLKXCTL_RMK(
326 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
327 MCASP_AHCLKXCTL_HCLKXP_FALLING,
328 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
329 MCASP_XTDM_OF(3),
330 MCASP_XINTCTL_DEFAULT,
331 MCASP_XCLKCHK_DEFAULT
332 };
334 static const MCASP_ConfigXmt txConfigDACSlave =
335 {
336 MCASP_XMASK_OF(0xFFFFFFFF),
337 MCASP_XFMT_RMK(
338 MCASP_XFMT_XDATDLY_1BIT,
339 MCASP_XFMT_XRVRS_MSBFIRST,
340 MCASP_XFMT_XPAD_ZERO,
341 MCASP_XFMT_XPBIT_DEFAULT,
342 MCASP_XFMT_XSSZ_32BITS,
343 MCASP_XFMT_XBUSEL_DAT,
344 MCASP_XFMT_XROT_NONE),
345 MCASP_AFSXCTL_RMK(
346 MCASP_AFSXCTL_XMOD_OF(2),
347 MCASP_AFSXCTL_FXWID_WORD,
348 MCASP_AFSXCTL_FSXM_INTERNAL,
349 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
350 MCASP_ACLKXCTL_RMK(
351 MCASP_ACLKXCTL_CLKXP_FALLING,
352 MCASP_ACLKXCTL_ASYNC_ASYNC,
353 MCASP_ACLKXCTL_CLKXM_INTERNAL,
354 MCASP_ACLKXCTL_CLKXDIV_OF(1)),
355 MCASP_AHCLKXCTL_RMK(
356 MCASP_AHCLKXCTL_HCLKXM_INTERNAL,
357 MCASP_AHCLKXCTL_HCLKXP_FALLING,
358 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
359 MCASP_XTDM_OF(3),
360 MCASP_XINTCTL_DEFAULT,
361 MCASP_XCLKCHK_DEFAULT
362 };
364 static const MCASP_ConfigXmt txConfigDIT =
365 {
366 MCASP_XMASK_OF(0x00FFFFFF),
367 MCASP_XFMT_RMK(
368 MCASP_XFMT_XDATDLY_1BIT,
369 MCASP_XFMT_XRVRS_LSBFIRST,
370 MCASP_XFMT_XPAD_DEFAULT,
371 MCASP_XFMT_XPBIT_DEFAULT,
372 MCASP_XFMT_XSSZ_32BITS,
373 MCASP_XFMT_XBUSEL_DAT,
374 MCASP_XFMT_XROT_NONE),
375 MCASP_AFSXCTL_RMK(
376 MCASP_AFSXCTL_XMOD_OF(0x180),
377 MCASP_AFSXCTL_FXWID_BIT,
378 MCASP_AFSXCTL_FSXM_INTERNAL,
379 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
380 MCASP_ACLKXCTL_RMK(
381 MCASP_ACLKXCTL_CLKXP_FALLING,
382 MCASP_ACLKXCTL_ASYNC_ASYNC,
383 MCASP_ACLKXCTL_CLKXM_INTERNAL,
384 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
385 MCASP_AHCLKXCTL_RMK(
386 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
387 MCASP_AHCLKXCTL_HCLKXP_FALLING,
388 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
389 MCASP_XTDM_OF(0xFFFFFFFF),
390 MCASP_XINTCTL_DEFAULT,
391 MCASP_XCLKCHK_DEFAULT
392 };
394 static const MCASP_ConfigXmt txConfigDIT_16bit =
395 {
396 MCASP_XMASK_OF(0x0000FFFF),
397 MCASP_XFMT_RMK(
398 MCASP_XFMT_XDATDLY_1BIT,
399 MCASP_XFMT_XRVRS_LSBFIRST,
400 MCASP_XFMT_XPAD_DEFAULT,
401 MCASP_XFMT_XPBIT_DEFAULT,
402 MCASP_XFMT_XSSZ_32BITS,
403 MCASP_XFMT_XBUSEL_DAT,
404 MCASP_XFMT_XROT_24BITS),
405 MCASP_AFSXCTL_RMK(
406 MCASP_AFSXCTL_XMOD_OF(0x180),
407 MCASP_AFSXCTL_FXWID_BIT,
408 MCASP_AFSXCTL_FSXM_INTERNAL,
409 MCASP_AFSXCTL_FSXP_ACTIVEHIGH),
410 MCASP_ACLKXCTL_RMK(
411 MCASP_ACLKXCTL_CLKXP_FALLING,
412 MCASP_ACLKXCTL_ASYNC_ASYNC,
413 MCASP_ACLKXCTL_CLKXM_INTERNAL,
414 MCASP_ACLKXCTL_CLKXDIV_OF(0)),
415 MCASP_AHCLKXCTL_RMK(
416 MCASP_AHCLKXCTL_HCLKXM_EXTERNAL,
417 MCASP_AHCLKXCTL_HCLKXP_FALLING,
418 MCASP_AHCLKXCTL_HCLKXDIV_OF(0)),
419 MCASP_XTDM_OF(0xFFFFFFFF),
420 MCASP_XINTCTL_DEFAULT,
421 MCASP_XCLKCHK_DEFAULT
422 };
424 // -----------------------------------------------------------------------------
425 // DAP Input Parameter Definitions
427 const SAP_D10_Rx_Params SAP_D10_RX_DIR =
428 {
429 sizeof (SAP_D10_Rx_Params), // size
430 "SAP", // name
431 MCASP_DEV2, // moduleNum --> mcasp #
432 (Void *)&rxConfigDIR, // pConfig
433 4, // wordSize (unused)
434 24, // precision (unused)
435 D10_sapControl, // control
436 0x00000020, // pinMask
437 (D10_MCLK_DIR << D10_MCLK_SHIFT), // mode
438 0,0 // unused[2]
439 };
441 const SAP_D10_Rx_Params SAP_D10_RX_ADC_44100HZ =
442 {
443 sizeof (SAP_D10_Rx_Params), // size
444 "SAP", // name
445 MCASP_DEV1, // moduleNum --> mcasp #
446 (Void *)&rxConfigADC, // pConfig
447 4, // wordSize (unused)
448 24, // precision (unused)
449 D10_sapControl, // control
450 0xE000000F, // pinMask
451 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
452 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
453 0,0 // unused[2]
454 };
456 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_44100HZ =
457 {
458 sizeof (SAP_D10_Rx_Params), // size
459 "SAP", // name
460 MCASP_DEV1, // moduleNum --> mcasp #
461 (Void *)&rxConfigADC, // pConfig
462 -1, // wordSize (unused)
463 -1, // precision (unused)
464 D10_sapControl, // control
465 0xE0000007, // pinMask
466 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
467 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
468 0,0 // unused[2]
469 };
471 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_44100HZ =
472 {
473 sizeof (SAP_D10_Rx_Params), // size
474 "SAP", // name
475 MCASP_DEV1, // moduleNum --> mcasp #
476 (Void *)&rxConfigADC, // pConfig
477 -1, // wordSize (unused)
478 -1, // precision (unused)
479 D10_sapControl, // control
480 0xE0000001, // pinMask
481 (D10_RATE_44_1KHZ << D10_RATE_SHIFT) |
482 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
483 0,0 // unused[2]
484 };
486 const SAP_D10_Rx_Params SAP_D10_RX_ADC_88200HZ =
487 {
488 sizeof (SAP_D10_Rx_Params), // size
489 "SAP", // name
490 MCASP_DEV1, // moduleNum --> mcasp #
491 (Void *)&rxConfigADC, // pConfig
492 -1, // wordSize (unused)
493 -1, // precision (unused)
494 D10_sapControl, // control
495 0xE000000F, // pinMask
496 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
497 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
498 0,0 // unused[2]
499 };
501 const SAP_D10_Rx_Params SAP_D10_RX_ADC_6CH_88200HZ =
502 {
503 sizeof (SAP_D10_Rx_Params), // size
504 "SAP", // name
505 MCASP_DEV1, // moduleNum --> mcasp #
506 (Void *)&rxConfigADC, // pConfig
507 -1, // wordSize (unused)
508 -1, // precision (unused)
509 D10_sapControl, // control
510 0xE0000007, // pinMask
511 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
512 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
513 0,0 // unused[2]
514 };
516 const SAP_D10_Rx_Params SAP_D10_RX_ADC_STEREO_88200HZ =
517 {
518 sizeof (SAP_D10_Rx_Params), // size
519 "SAP", // name
520 MCASP_DEV1, // moduleNum --> mcasp #
521 (Void *)&rxConfigADC, // pConfig
522 -1, // wordSize (unused)
523 -1, // precision (unused)
524 D10_sapControl, // control
525 0xE0000001, // pinMask
526 (D10_RATE_88_2KHZ << D10_RATE_SHIFT) |
527 (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
528 0,0 // unused[2]
529 };
532 const SAP_D10_Rx_Params SAP_D10_RX_HDMI_STEREO =
533 {
534 sizeof (SAP_D10_Rx_Params), // size
535 "SAP", // name
536 MCASP_DEV0, // moduleNum --> mcasp #
537 (Void *)&rxConfigDIR, // pConfig
538 4, // wordSize (unused)
539 -1, // precision (unused)
540 D10_sapControl, // control
541 0x00001000, // pinMask
542 (D10_MODE_HDMI << D10_MODE_SHIFT) |
543 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
544 0,0 // unused[2]
545 };
547 const SAP_D10_Rx_Params SAP_D10_RX_HDMI =
548 {
549 sizeof (SAP_D10_Rx_Params), // size
550 "SAP", // name
551 MCASP_DEV0, // moduleNum --> mcasp #
552 (Void *)&rxConfigDIR, // pConfig
553 4, // wordSize (unused)
554 -1, // precision (unused)
555 D10_sapControl, // control
556 0xE000F000, // pinMask
557 (D10_MODE_HDMI << D10_MODE_SHIFT) |
558 (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
559 0,0 // unused[2]
560 };
562 // -----------------------------------------------------------------------------
563 // SAP Output Parameter Definitions
565 const SAP_D10_Tx_Params SAP_D10_TX_DAC =
566 {
567 sizeof (SAP_D10_Tx_Params), // size
568 "SAP", // name
569 MCASP_DEV0, // moduleNum --> mcasp #
570 (Void *)&txConfigDAC, // pConfig
571 4, // wordSize (in bytes)
572 24, // precision (in bits)
573 D10_sapControl, // control
574 0x1600000F, // pinMask
575 0, // mode
576 0,0,0 // unused[3]
577 };
579 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC =
580 {
581 sizeof (SAP_D10_Tx_Params), // size
582 "SAP", // name
583 MCASP_DEV0, // moduleNum --> mcasp #
584 (Void *)&txConfigDAC, // pConfig
585 4, // wordSize (in bytes)
586 24, // precision (in bits)
587 D10_sapControl, // control
588 0x16000001, // pinMask
589 0, // mode
590 0,0,0 // unused[3]
591 };
593 const SAP_D10_Tx_Params SAP_D10_TX_DIT =
594 {
595 sizeof (SAP_D10_Tx_Params), // size
596 "SAP", // name
597 MCASP_DEV2, // moduleNum --> mcasp #
598 (Void *) &txConfigDIT, // pConfig
599 3, // wordSize (in bytes)
600 24, // precision (in bits)
601 D10_sapControl, // control
602 0x1C000001, // pinMask
603 0, // mode
604 0,0,0 // unused[3]
605 };
607 const SAP_D10_Tx_Params SAP_D10_TX_DAC_SLAVE =
608 {
609 sizeof (SAP_D10_Tx_Params), // size
610 "SAP", // name
611 MCASP_DEV0, // moduleNum --> mcasp #
612 (Void *)&txConfigDACSlave, // pConfig
613 4, // wordSize (in bytes)
614 24, // precision (in bits)
615 D10_sapControl, // control
616 0x1E00000F, // pinMask
617 0, // mode
618 0,0,0 // unused[3]
619 };
621 const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC_SLAVE =
622 {
623 sizeof (SAP_D10_Tx_Params), // size
624 "SAP", // name
625 MCASP_DEV0, // moduleNum --> mcasp #
626 (Void *)&txConfigDAC, // pConfig
627 4, // wordSize (in bytes)
628 24, // precision (in bits)
629 D10_sapControl, // control
630 0x16000001, // pinMask
631 0, // mode
632 0,0,0 // unused[3]
633 };
636 // -----------------------------------------------------------------------------
637 // One time initialization of the DA10x audio hardware.
639 /* DAC default configuration parameters */
640 DacConfig dacCfg =
641 {
642 DAC_AMUTE_CTRL_SCKI_LOST, /* Amute event */
643 0, /* Amute control */
644 DAC_SAMPLING_MODE_SINGLE_RATE, /* Sampling mode */
645 DAC_DATA_FORMAT_I2S, /* Data format */
646 0, /* Soft mute control */
647 DAC_ATTENUATION_WIDE_RANGE, /* Attenuation mode */
648 DAC_DEEMP_44KHZ, /* De-emph control */
649 100 /* Volume */
650 };
651 /* ADC default configuration parameters */
652 AdcConfig adcCfg =
653 {
654 90, /* ADC gain */
655 ADC_INL_SE_VINL1, /* Left input mux for ADC1L */
656 ADC_INL_SE_VINL2, /* Left input mux for ADC2L */
657 ADC_INR_SE_VINR1, /* Right input mux for ADC1R */
658 ADC_INR_SE_VINR2, /* Right input mux for ADC2R */
659 ADC_RX_WLEN_24BIT, /* ADC word length */
660 ADC_DATA_FORMAT_I2S, /* ADC data format */
661 0
662 };
664 Platform_STATUS setAudioDacConfig(void)
665 {
666 Platform_STATUS status;
668 /* Initialize Audio DAC module */
669 status = audioDacConfig(DAC_DEVICE_ALL, &dacCfg);
670 if (status)
671 Log_info0("SAP_D10: Audio DAC Configuration Failed!!!\n");
672 return status;
674 }
676 static inline XDAS_Int32 initD10 (DEV2_Handle device)
677 {
678 Platform_STATUS status = Platform_EOK;
680 /* Initialize common audio configurations */
681 status = platformAudioInit();
682 if(status != Platform_EOK)
683 {
684 System_printf("Audio Init Failed!\n");
685 return status;
686 }
688 /* Initialize Audio ADC module */
689 status = audioAdcConfig(ADC_DEVICE_ALL, &adcCfg);
690 if(status != Platform_EOK)
691 {
692 platform_write("Audio ADC Configuration Failed!\n");
693 return status;
694 }
696 /* Setup DIR 9001 for SPDIF input operation */
697 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
698 status = audioDirConfig();
699 if(status != Platform_EOK)
700 {
701 Log_info0("Audio DIR Init Failed!\n");
702 return status;
703 }
705 #if 0
706 /* Setup HSR41 for HDMI input operation */
707 //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
708 /* Initialize the HDMI Card */
709 status = audioHDMIConfig();
710 if(status != Platform_EOK)
711 {
712 Log_info0("Audio HDMI Init Failed!\n");
713 return status;
714 }
715 #endif
717 // This is needed because DAC configuration needs some default clocking.
718 // We start with S/PDIF, because it's onboard the Audio DC & has its own crystal.
719 // HDMI is an add-on board & Audio OSC would need AUX clocking - both unfit for "default".
720 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
722 platform_delay(20000); // Without delay between these 2 calls system aborts.
724 status = setAudioDacConfig();
726 return status;
728 } //initD10
730 // -----------------------------------------------------------------------------
731 // The McASP TX section is *only* used as a master clock mux.
732 // Mux functionality is achieved by selecting either external high
733 // speed clocks (DIR/HDMI) or the internal AUXCLK (Audio_OSC). This is divided down
734 // output via ACLKX0 which is connected to the high speed input
735 // of TX0 (DAC) and TX2 (DIT).
737 static XDAS_Int32 clockMuxTx (int sel, int force)
738 {
739 Platform_STATUS status = 0;
740 // select clkxDiv table
741 if (sel == D10_MCLK_DIR)
742 {
743 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
744 pClkxDiv = (unsigned char *) clkxDivDIR;
745 }
746 else if (sel == D10_MCLK_HDMI)
747 {
748 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
749 pClkxDiv = (unsigned char *) clkxDivHDMI;
750 }
751 else if (sel == D10_MCLK_OSC)
752 {
753 status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_OSC);
754 pClkxDiv = (unsigned char *) clkxDivADC;
755 }
757 platform_delay(20000);
759 return status;
760 } //clockMuxTx
763 // -----------------------------------------------------------------------------
764 // This function returns the input status of the specified device.
765 // This is called once when the device is opened
766 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter
767 // (PAF_SIO_CONTROL_GET_INPUT_STATUS).
769 static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PAF_SIO_InputStatus *pStatusOut)
770 {
771 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
772 volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
773 volatile Uint32 *mcasp1 = (volatile Uint32 *) _MCASP_BASE_PORT1;
774 volatile Uint32 *mcasp2 = (volatile Uint32 *) _MCASP_BASE_PORT2;
776 Platform_STATUS status;
778 static int PrevSampRate = 0;
779 int Rate_spdif=0;
781 if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_DIR) &
782 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD))
783 {
784 pStatusIn->lock = !(platformAudioDirGetClkStatus());
785 pStatusIn->nonaudio = !(platformAudioDirGetAudioStatus());
786 pStatusIn->emphasis = platformAudioDirGetEmphStatus();
787 pStatusIn->sampleRateMeasured = RateTable_spdif[platformAudioDirGetFsOut()];
788 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
789 PrevSampRate = pStatusIn->sampleRateMeasured;
791 // GJ: Is this needed? Probably not.
792 mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
793 mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
795 }
796 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_OSC) &
797 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD)) {
798 int adcRate = (pParams->d10rx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
799 int regData;
801 pStatusIn->lock = 1;
802 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
803 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
804 pStatusIn->sampleRateMeasured = oscRateTable[adcRate];
805 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
807 }
808 else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_HDMI) &
809 (((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_HDMI))
810 {
811 pStatusIn->lock = 1;
812 pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
813 pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
816 if(!HDMIGpioGetState()) {
817 HSR4_readStatus (pStatusIn);
818 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
819 PrevSampRate = pStatusIn->sampleRateMeasured;
820 }
821 else {
822 pStatusIn->sampleRateMeasured = PrevSampRate;
823 pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
824 }
826 }
827 else
828 return -1;
830 // update another status if requested
831 if (pStatusOut)
832 *pStatusOut = *pStatusIn;
834 return 0;
835 } //manageInput
838 // -----------------------------------------------------------------------------
839 // This function configures the McASP TX clock dividers based on the
840 // master clock rate. This is called once when the device is opened
841 // (PAF_SIO_CONTROL_OPEN) and periodically thereafter (PAF_SIO_CONTROL_SET_RATEX).
843 static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX)
844 {
845 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
846 PAF_SIO_InputStatus *pStatusIn = &primaryStatus;
847 Uint32 divider;
850 if (!pClkxDiv)
851 return 1;
853 // set clock divider
854 if (rateX < .354)
855 rateX = 0.25;
856 else if (rateX < .707)
857 rateX = 0.50;
858 else if (rateX < 1.6)
859 rateX = 1.00;
860 else if (rateX < 2.828)
861 rateX = 2.00;
862 else
863 rateX = 4.00;
864 // if asynchronous then force clock change (assumes osc master)
865 if (pParams->d10tx.mode & D10_SYNC_MASK) {
866 int dacRate = (pParams->d10tx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
867 divider = pClkxDiv[oscRateTable[dacRate]];
868 }
869 else
870 divider = pClkxDiv[pStatusIn->sampleRateMeasured];
871 divider /= rateX;
873 Log_info2("SAP_D10: Inside manageOutput with divider = %d, rateX = %d", divider, rateX);
875 // DIT requires 2x clock
876 if ((mcasp[_MCASP_AFSXCTL_OFFSET] & _MCASP_AFSXCTL_XMOD_MASK) ==
877 (MCASP_AFSXCTL_XMOD_OF(0x180) << _MCASP_AFSXCTL_XMOD_SHIFT)) {
878 if (divider < 2)
879 return (SIO2_EINVAL);
880 divider >>= 1;
881 }
883 mcasp[_MCASP_ACLKXCTL_OFFSET] =
884 (mcasp[_MCASP_ACLKXCTL_OFFSET] & ~_MCASP_ACLKXCTL_CLKXDIV_MASK) |
885 (MCASP_ACLKXCTL_CLKXDIV_OF(divider-1) << _MCASP_ACLKXCTL_CLKXDIV_SHIFT);
886 return 0;
887 } //manageOutput
889 // -----------------------------------------------------------------------------
890 // This function is called by the peripheral driver (DAP) in response to
891 // various SIO_ctrl() calls made by the framework.
893 XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XDAS_Int32 code, XDAS_Int32 arg)
894 {
895 const SAP_D10_Rx_Params *pDapD10RxParams = (const SAP_D10_Rx_Params *)pParams;
896 const SAP_D10_Tx_Params *pDapD10TxParams = (const SAP_D10_Tx_Params *)pParams;
897 Platform_STATUS status;
899 volatile Uint32 *mcasp = mcaspAddr[pParams->sio.moduleNum];
900 XDAS_Int32 result = 0;
902 // perform one time hardware initialization
903 if (!initDone) {
904 result = initD10 (device);
905 if (result)
906 return result;
907 initDone = 1;
908 }
910 switch (code) {
912 // .............................................................................
913 // This case provides a regular entry point for managing the specified
914 // input device. Nominally, this is used to provide lock and sample rate
915 // status to the framework.
917 case PAF_SIO_CONTROL_GET_INPUT_STATUS:
918 if (device->mode != DEV2_INPUT)
919 return SIO2_EINVAL;
921 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
922 break;
924 // .............................................................................
925 // This case provides a regular entry point for managing the specified
926 // output device. Nominally this is used to change the output clock dividers
927 // in the case of double rate output (e.g. DTS 96/24).
929 case PAF_SIO_CONTROL_SET_RATEX:
930 // Support only output rate control, for now
931 if (device->mode != DEV2_OUTPUT)
932 return (SIO2_EINVAL);
934 // configure clock divider (bit and frame clocks)
935 manageOutput (device, pDapD10TxParams, *((float *) arg));
936 break;
938 // .............................................................................
939 // This case is called once when the device is opened/allocated by the framework.
940 // Here, for both input and output, this allows for configuring all needed
941 // clocks for proper operation.
943 case PAF_SIO_CONTROL_OPEN:
944 if (device->mode == DEV2_INPUT) {
946 // determine the master clock based on the mode element of the
947 // parameter configuration.
948 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
949 manageInput (device, pDapD10RxParams, NULL);
951 // select appropriate master clock (but dont force)
953 clockMuxTx (sel, -1);
955 }
956 else {
958 // Since DAC is a slave to the chosen input, operate the clksel switch appropriately
959 // Also, this is a create-time (i.e, CTRL_OPEN) only call & not appropriate under
960 // the periodic manage_(in/out)put calls
961 int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
962 clockMuxTx (sel, -1);
963 platform_delay(20000); // Without delay between Tx McASP & DAC configs, system aborts.
964 setAudioDacConfig();
965 dacHardUnMute ();
967 // configure clock divider (bit and frame clocks)
968 manageOutput (device, pDapD10TxParams, 1.0);
969 }
970 break;
972 // .............................................................................
973 // This case is called once when the device is closed/freed by the framework.
975 case PAF_SIO_CONTROL_CLOSE:
976 // If TX0 then signal it is no longer in use by the DACs and
977 // configure manually to generate ADC clocks. Also hard mute
978 // the DACs since they are not in use.
979 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0)) {
981 dacHardMute ();
983 // if async then clear forced clock mux
984 // if asynchronous then force clock change
985 if (pDapD10TxParams->d10tx.mode & D10_SYNC_MASK)
986 clockMuxTx (0, 0);
987 }
988 break;
990 // .............................................................................
991 // These cases are called as appropriate by the framework when there is
992 // valid output data (UNMUTE) or no valid output (MUTE).
994 case PAF_SIO_CONTROL_MUTE:
995 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
996 dacSoftMute ();
997 break;
999 case PAF_SIO_CONTROL_UNMUTE:
1000 if ((device->mode == DEV2_OUTPUT) && (pParams->sio.moduleNum == MCASP_DEV0))
1001 dacSoftUnMute ();
1002 break;
1004 // .............................................................................
1005 // This case is called when the device is idled.
1006 // There is no specific handling -- but needed to avoid error return.
1008 case PAF_SIO_CONTROL_IDLE:
1009 break;
1011 // .............................................................................
1012 // Called from the IDL Loop to allow for clock management and the like
1013 // The call is protected by a TSK_disable and HWI_disable so it is safe
1014 // to read/write shared resources.
1016 case PAF_SIO_CONTROL_WATCHDOG:
1017 // call manageInput in case the sample rate has changed resulting
1018 // in no output clocks which may have blocked the audio processing
1019 // thread. This call will reconfigure the AK4588 and restart the clocks.
1020 if (device->mode == DEV2_INPUT)
1021 manageInput (device, pDapD10RxParams, (PAF_SIO_InputStatus *) arg);
1022 break;
1024 // .............................................................................
1025 // Called from DOB_issue to allow for different values of the channel status
1026 // fields of the SPDIF output.
1028 case PAF_SIO_CONTROL_SET_DITSTATUS:
1029 // No action necessary.
1030 break;
1032 case PAF_SIO_CONTROL_SET_WORDSIZE:
1033 if(((pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) != D10_MCLK_OSC)
1034 {
1035 if ((device->mode == DEV2_INPUT) && (arg == 2))
1036 {
1037 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=2");
1038 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_16BITS;
1039 }
1040 else if ((device->mode == DEV2_INPUT) && (arg == 4))
1041 {
1042 Log_info0("Inside SAP_D10Control PAF_SIO_CONTROL_SET_WORDSIZE for arg=4");
1043 mcasp[_MCASP_RFMT_OFFSET] = (mcasp[_MCASP_RFMT_OFFSET] & ~_MCASP_RFMT_RROT_MASK) | MCASP_RFMT_RROT_NONE;
1044 }
1045 }
1046 break;
1047 // .............................................................................
1048 // Any other cases are not handled and return an error.
1050 default:
1051 return SIO2_EINVAL;
1052 }
1054 return result;
1055 } //D10_sapControl
1057 // -----------------------------------------------------------------------------
1060 extern unsigned int read_hdmi_samprate();
1061 int RateHdmi=0;
1062 void HSR4_readStatus (PAF_SIO_InputStatus *pStatus)
1063 {
1064 //if(!RateHdmi)
1065 RateHdmi=read_hdmi_samprate();
1066 pStatus->sampleRateMeasured = RateTable_hdmi[RateHdmi];
1067 }
1069 unsigned int HDMIGpioGetState (void) {
1070 return(gpioReadInput(GPIO_PORT_0, PLATFORM_AUDIO_HSR_HMINTz_GPIO));
1071 }
1073 // EOF