1 /*
2 * Copyright (c) 2012-2014 Texas Instruments Incorporated - http://www.ti.com
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * ======== config.bld ========
35 *
36 */
37 var Build = xdc.useModule('xdc.bld.BuildEnvironment');
39 /* Memory Map for ti.platforms.evmTCI66AK2G02
40 *
41 * Address Size Comment
42 * -------------------------------------------------------------
43 * 0C00_0000 0008_0000 ( 512 KB) SR_MSMC (ipc:data)
44 * 0C08_0000 0004_0000 ( 256 KB) HOST_MSMC (code, data)
45 * 0C0C_0000 0004_0000 ( 256 KB) CORE_MSMC (code, data)
46 * 8000_0000 0020_0000 ( 2 MB) SR_0 (ipc)
47 * 8020_0000 0080_0000 ( 8 MB) SR_DDR3 (ipc:data)
48 * 80A0_0000 0080_0000 ( 8 MB) COMMON_DDR3 (data)
49 * 8120_0000 0400_0000 ( 64 MB) HOST_DDR3 (code, data)
50 * 8520_0000 0400_0000 ( 64 MB) CORE0_DDR3 (code, data)
51 * 8920_0000 76E0_0000 (1902 MB) DDR3 (code, data)
52 */
54 var SR_MSMC = {
55 name: "SR_MSMC", space: "data", access: "RW",
56 base: 0x0C000000, len: 0x00080000,
57 comment: "SR MSMC Memory (512 KB)"
58 };
60 var SR_0 = {
61 name: "SR_0", space: "data", access: "RW",
62 base: 0x80000000, len: 0x00200000,
63 comment: "SR#0 Memory"
64 };
66 var SR_DDR3 = {
67 name: "SR_DDR3", space: "data", access: "RW",
68 base: 0x80200000, len: 0x00800000,
69 comment: "SR DDR3 Memory"
70 };
72 var COMMON_DDR3 = {
73 name: "COMMON_DDR3", space: "data", access: "RW",
74 base: 0x80A00000, len: 0x00800000,
75 comment: "COMMON DDR3 Memory"
76 };
78 var DDR3 = {
79 name: "DDR3", space: "code/data", access: "RW",
80 base: 0x89200000, len: 0x76E00000,
81 comment: "DDR3 Memory"
82 };
84 // This is ARM
85 Build.platformTable["ti.platforms.evmTCI66AK2G02:host"] = {
86 customMemoryMap: [
87 ["SR_MSMC", SR_MSMC],
89 [ "HOST_MSMC", {
90 name: "HOST_MSMC", space: "code/data", access: "RWX",
91 base: 0x0C080000, len: 0x00040000,
92 comment: "HOST MSMC SRAM"
93 }],
95 ["SR_0", SR_0],
97 ["SR_DDR3", SR_DDR3],
99 ["COMMON_DDR3", COMMON_DDR3],
101 [ "HOST_DDR3", {
102 name: "HOST_DDR3", space: "code/data", access: "RWX",
103 base: 0x81200000, len: 0x04000000,
104 comment: "HOST DDR3"
105 }],
107 ["DDR3", DDR3]
108 ],
110 codeMemory: "HOST_DDR3",
111 dataMemory: "HOST_DDR3",
112 stackMemory: "HOST_DDR3"
113 };
115 // This is DSP
116 Build.platformTable["ti.platforms.evmTCI66AK2G02:core0"] = {
117 customMemoryMap: [
118 ["L2SRAM", {
119 comment: "1MB L2 SRAM/CACHE",
120 name: "L2SRAM",
121 base: 0x00800000,
122 len: 0x00100000,
123 space: "code/data",
124 access: "RWX"
125 }],
127 ["L1PSRAM", {
128 comment: "32KB RAM/CACHE L1 program memory",
129 name: "L1PSRAM",
130 base: 0x00E00000,
131 len: 0x00008000,
132 space: "code",
133 access: "RWX"
134 }],
136 ["L1DSRAM", {
137 comment: "32KB RAM/CACHE L1 data memory",
138 name: "L1DSRAM",
139 base: 0x00F00000,
140 len: 0x00008000,
141 space: "data",
142 access: "RW"
143 }],
145 ["SR_MSMC", SR_MSMC],
147 [ "CORE0_MSMC", {
148 name: "CORE0_MSMC", space: "code/data", access: "RWX",
149 base: 0x0C0C0000, len: 0x00040000,
150 comment: "CORE0 MSMC SRAM"
151 }],
153 ["SR_0", SR_0],
155 ["SR_DDR3", SR_DDR3],
157 ["COMMON_DDR3", COMMON_DDR3],
159 [ "CORE0_DDR3", {
160 name: "CORE0_DDR3", space: "code/data", access: "RWX",
161 base: 0x85200000, len: 0x04000000,
162 comment: "CORE0 DDR3"
163 }],
165 ["DDR3", DDR3]
166 ],
168 codeMemory: "CORE0_DDR3",
169 dataMemory: "CORE0_DDR3",
170 stackMemory: "CORE0_DDR3",
172 l1DMode: "32k",
173 l1PMode: "32k",
174 l2Mode: "256k"
175 };