2 /*
3 * Copyright {C} 2016 Texas Instruments Incorporated - http://www.ti.com/
4 * ALL RIGHTS RESERVED
5 *
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the
17 * distribution.
18 *
19 * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 */
37 //
38 //
39 // PCM Encoder alpha codes
40 //
41 //
42 //
44 #ifndef _PCE_A
45 #define _PCE_A
47 #include <paftyp_a.h>
48 #include <acpbeta.h>
50 // The PCE_VERSION build control should be used to distinguish PCE1
51 // from PCE2.
53 #ifndef PCE_VERSION
54 #define PCE_VERSION 2
55 #endif /* PCE_VERSION */
57 #define readPCEMode 0xc200+STD_BETA_PCE,0x0400
58 /* Note: this should not be disabled */
59 #define writePCEModeEnable 0xca00+STD_BETA_PCE,0x0401
61 #define PCE_PHASE_BASE 0x06
62 #define PCE_PHASE_LENGTH 0x0c
64 #define readPCEModePhase0Mode 0xc200+STD_BETA_PCE,(PCE_PHASE_BASE << 8)+0x00
65 #define writePCEModePhase0ModeDisable 0xca00+STD_BETA_PCE,(PCE_PHASE_BASE << 8)+0x00
66 #define writePCEModePhase0ModeEnable 0xca00+STD_BETA_PCE,(PCE_PHASE_BASE << 8)+0x01
68 #define readPCEModePhase0Type 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+1) << 8)+0x00
69 #define writePCEModePhase0TypeUnused 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+1) << 8)+0x00
71 #define readPCEModePhase1Mode 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+2) << 8)+0x00
72 #define writePCEModePhase1ModeDisable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+2) << 8)+0x00
73 #define writePCEModePhase1ModeEnable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+2) << 8)+0x01
75 #define readPCEModePhase1Type 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+3) << 8)+0x00
76 #define writePCEModePhase1TypeUnused 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+3) << 8)+0x00
78 #define readPCEModePhase2Mode 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+4) << 8)+0x00
79 #define writePCEModePhase2ModeDisable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+4) << 8)+0x00
80 #define writePCEModePhase2ModeEnable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+4) << 8)+0x01
82 #define readPCEModePhase2Type 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+5) << 8)+0x00
83 #define writePCEModePhase2TypeUnused 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+5) << 8)+0x00
85 #define readPCEModePhase3Mode 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+6) << 8)+0x00
86 #define writePCEModePhase3ModeDisable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+6) << 8)+0x00
87 #define writePCEModePhase3ModeEnable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+6) << 8)+0x01
89 #define readPCEModePhase3Type 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+7) << 8)+0x00
90 #define writePCEModePhase3TypeUnused 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+7) << 8)+0x00
92 #if PCE_VERSION == 2
94 #define readPCEModePhase4Mode 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+8) << 8)+0x00
95 #define writePCEModePhase4ModeDisable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+8) << 8)+0x00
96 #define writePCEModePhase4ModeEnable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+8) << 8)+0x01
98 #define readPCEModePhase4Type 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+9) << 8)+0x00
99 #define writePCEModePhase4TypeUnused 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+9) << 8)+0x00
101 #define readPCEModePhase5Mode 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+10) << 8)+0x00
102 #define writePCEModePhase5ModeDisable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+10) << 8)+0x00
103 #define writePCEModePhase5ModeEnable 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+10) << 8)+0x01
105 #define readPCEModePhase5Type 0xc200+STD_BETA_PCE,((PCE_PHASE_BASE+11) << 8)+0x00
106 #define writePCEModePhase5TypeUnused 0xca00+STD_BETA_PCE,((PCE_PHASE_BASE+11) << 8)+0x00
108 #define readPCEVOLMode readPCEModePhase0Mode
109 #define writePCEVOLModeDisable writePCEModePhase0ModeDisable
110 #define writePCEVOLModeEnable writePCEModePhase0ModeEnable
112 #define readPCEVOLType readPCEModePhase0Type
113 #define writePCEVOLTypeUnused writePCEModePhase0TypeUnused
115 #define readPCEDELMode readPCEModePhase1Mode
116 #define writePCEDELModeDisable writePCEModePhase1ModeDisable
117 #define writePCEDELModeEnable writePCEModePhase1ModeEnable
119 #define readPCEDELType readPCEModePhase1Type
120 #define writePCEDELTypeUnused writePCEModePhase1TypeUnused
122 #define readPCEOUTMode readPCEModePhase2Mode
123 #define writePCEOUTModeDisable writePCEModePhase2ModeDisable
124 #define writePCEOUTModeEnable writePCEModePhase2ModeEnable
126 #define readPCEOUTType readPCEModePhase2Type
127 #define writePCEOUTTypeUnused writePCEModePhase2TypeUnused
129 // PCE SLD Alpha codes
130 #define PCE_PHASE_DELAY_BASE PCE_PHASE_BASE+PCE_PHASE_LENGTH
131 #define PCE_PHASE_DELAY_LENGTH 0x04
133 #define readPCEDELUnit 0xc200+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x00
134 #define writePCEDELUnitTimeSamples 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x00
135 #define writePCEDELUnitTimeMillisecondsQ0 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x01
136 #define writePCEDELUnitTimeMillisecondsQ1 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x02
137 #define writePCEDELUnitTimeCentimeters 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x03
138 #define writePCEDELUnitTimeFeet 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x04
139 #define writePCEDELUnitTimeYards 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x05
140 #define writePCEDELUnitTimeMeters 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x06
141 #define writePCEDELUnitTimeDecimilliseconds 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x07
142 #define writePCEDELUnitLocationSamples 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x80
143 #define writePCEDELUnitLocationMillisecondsQ0 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x81
144 #define writePCEDELUnitLocationMillisecondsQ1 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x82
145 #define writePCEDELUnitLocationCentimeters 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x83
146 #define writePCEDELUnitLocationFeet 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x84
147 #define writePCEDELUnitLocationYards 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x85
148 #define writePCEDELUnitLocationMeters 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x86
149 #define writePCEDELUnitLocationDecimilliseconds 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+1) << 8)+0x87
151 #define writePCEDELUnitTimeMilliseconds writePCEDELUnitTimeMillisecondsQ0
152 #define writePCEDELUnitTimeMilliseconds2 writePCEDELUnitTimeMillisecondsQ1
153 #define writePCEDELUnitLocationMilliseconds writePCEDELUnitLocationMillisecondsQ0
154 #define writePCEDELUnitLocationMilliseconds2 writePCEDELUnitLocationMillisecondsQ1
156 #define readPCEDELNumb 0xc200+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+2) << 8)+0x00
157 #define writePCEDELNumbXX(XX) 0xca00+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+2) << 8)+0x##XX
159 #define readPCEDELUnused 0xc200+STD_BETA_PCE,((PCE_PHASE_DELAY_BASE+3) << 8)+0x00
161 #define PCE_PHASE_DELAY_CHAN_BASE PCE_PHASE_DELAY_BASE+PCE_PHASE_DELAY_LENGTH
162 #define PCE_PHASE_DELAY_CHAN_LENGTH PAF_MAXNUMCHAN_AF*2
164 #if 0 < PAF_MAXNUMCHAN_AF
165 #define readPCEDELDelayLeft 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE
166 #define writePCEDELDelayLeftN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE,NN
167 #define readPCEDELDelayRght 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+2
168 #define writePCEDELDelayRghtN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+2,NN
170 #endif /* 0 < PAF_MAXNUMCHAN_AF */
171 #if PAF_MAXNUMCHAN_AF == 4
172 #define readPCEDELDelayCntr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4
173 #define writePCEDELDelayCntrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4,NN
174 #define readPCEDELDelaySurr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6
175 #define writePCEDELDelaySurrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6,NN
177 #define readPCEDELDelayMaster 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8
178 #define writePCEDELDelayMasterN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8,NN
180 #elif PAF_MAXNUMCHAN_AF == 6
181 #define readPCEDELDelayCntr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4
182 #define writePCEDELDelayCntrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4,NN
183 #define readPCEDELDelaySurr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6
184 #define writePCEDELDelaySurrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6,NN
185 #define readPCEDELDelayLSur 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6
186 #define writePCEDELDelayLSurN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6,NN
187 #define readPCEDELDelayRSur 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8
188 #define writePCEDELDelayRSurN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8,NN
189 #define readPCEDELDelaySubw 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+10
190 #define writePCEDELDelaySubwN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+10,NN
192 #define readPCEDELDelayMaster 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
193 #define writePCEDELDelayMasterN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
195 #elif PAF_MAXNUMCHAN_AF == 8
196 #define readPCEDELDelayCntr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4
197 #define writePCEDELDelayCntrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4,NN
198 #define readPCEDELDelaySurr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6
199 #define writePCEDELDelaySurrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6,NN
200 #define readPCEDELDelayLSur 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6
201 #define writePCEDELDelayLSurN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6,NN
202 #define readPCEDELDelayRSur 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8
203 #define writePCEDELDelayRSurN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8,NN
204 #define readPCEDELDelaySubw 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+10
205 #define writePCEDELDelaySubwN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+10,NN
206 #define readPCEDELDelayBack 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
207 #define writePCEDELDelayBackN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
208 #define readPCEDELDelayLBak 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
209 #define writePCEDELDelayLBakN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
210 #define readPCEDELDelayRBak 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14
211 #define writePCEDELDelayRBakN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14,NN
213 #define readPCEDELDelayMaster 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16
214 #define writePCEDELDelayMasterN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16,NN
216 #elif PAF_MAXNUMCHAN_AF == 16
218 #define readPCEDELDelayCntr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4
219 #define writePCEDELDelayCntrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4,NN
220 #define readPCEDELDelayLCtr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4
221 #define writePCEDELDelayLCtrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4,NN
222 #define readPCEDELDelayRCtr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6
223 #define writePCEDELDelayRCtrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6,NN
224 #define readPCEDELDelayWide 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8
225 #define writePCEDELDelayWideN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8,NN
226 #define readPCEDELDelayLWid 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8
227 #define writePCEDELDelayLWidN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8,NN
228 #define readPCEDELDelayRWid 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+10
229 #define writePCEDELDelayRWidN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+10,NN
230 #define readPCEDELDelayOver 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
231 #define writePCEDELDelayOverN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
232 #define readPCEDELDelayLOvr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
233 #define writePCEDELDelayLOvrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
234 #define readPCEDELDelayROvr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14
235 #define writePCEDELDelayROvrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14,NN
236 #define readPCEDELDelaySurr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16
237 #define writePCEDELDelaySurrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16,NN
238 #define readPCEDELDelayLSur 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16
239 #define writePCEDELDelayLSurN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16,NN
240 #define readPCEDELDelayRSur 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+18
241 #define writePCEDELDelayRSurN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+18,NN
242 #define readPCEDELDelayBack 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+20
243 #define writePCEDELDelayBackN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+20,NN
244 #define readPCEDELDelayLBak 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+20
245 #define writePCEDELDelayLBakN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+20,NN
246 #define readPCEDELDelayRBak 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+22
247 #define writePCEDELDelayRBakN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+22,NN
248 #define readPCEDELDelaySubw 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+24
249 #define writePCEDELDelaySubwN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+24,NN
250 #define readPCEDELDelayLSub 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+24
251 #define writePCEDELDelayLSubN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+24,NN
252 #define readPCEDELDelayRSub 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+26
253 #define writePCEDELDelayRSubN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+26,NN
254 #define readPCEDELDelayLHed 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28
255 #define writePCEDELDelayLHedN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28,NN
256 #define readPCEDELDelayRHed 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30
257 #define writePCEDELDelayRHedN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30,NN
259 #define readPCEDELDelayMaster 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+32
260 #define writePCEDELDelayMasterN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+32,NN
262 //ATMOS
263 #define readPCEDELDelayLtrr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
264 #define writePCEDELDelayLtrrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
265 #define readPCEDELDelayRtrr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14
266 #define writePCEDELDelayRtrrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14,NN
267 #define readPCEDELDelayLtrh 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
268 #define writePCEDELDelayLtrhN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
269 #define readPCEDELDelayRtrh 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14
270 #define writePCEDELDelayRtrhN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14,NN
271 #define readPCEDELDelayLtmd 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28
272 #define writePCEDELDelayLtmdN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28,NN
273 #define readPCEDELDelayRtmd 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30
274 #define writePCEDELDelayRtmd(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30,NN
275 #define readPCEDELDelayLtft 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28
276 #define writePCEDELDelayLtftN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28,NN
277 #define readPCEDELDelayRtft 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30
278 #define writePCEDELDelayRtftN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30,NN
279 #define readPCEDELDelayLtfh 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28
280 #define writePCEDELDelayLtfhN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28,NN
281 #define readPCEDELDelayRtfh 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30
282 #define writePCEDELDelayRtfh(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30,NN
285 #elif PAF_MAXNUMCHAN_AF == 32
288 #define readPCEDELDelayCntr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4
289 #define writePCEDELDelayCntrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4,NN
290 #define readPCEDELDelayLCtr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4
291 #define writePCEDELDelayLCtrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+4,NN
292 #define readPCEDELDelayRCtr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6
293 #define writePCEDELDelayRCtrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+6,NN
294 #define readPCEDELDelayWide 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8
295 #define writePCEDELDelayWideN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8,NN
296 #define readPCEDELDelayLWid 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8
297 #define writePCEDELDelayLWidN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+8,NN
298 #define readPCEDELDelayRWid 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+10
299 #define writePCEDELDelayRWidN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+10,NN
300 #define readPCEDELDelayOver 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
301 #define writePCEDELDelayOverN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
302 #define readPCEDELDelayLOvr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
303 #define writePCEDELDelayLOvrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
304 #define readPCEDELDelayROvr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14
305 #define writePCEDELDelayROvrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14,NN
306 #define readPCEDELDelayLtmd 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12
307 #define writePCEDELDelayLtmdN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+12,NN
308 #define readPCEDELDelayRtmd 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14
309 #define writePCEDELDelayRtmdN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+14,NN
310 #define readPCEDELDelaySurr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16
311 #define writePCEDELDelaySurrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16,NN
312 #define readPCEDELDelayLSur 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16
313 #define writePCEDELDelayLSurN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+16,NN
314 #define readPCEDELDelayRSur 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+18
315 #define writePCEDELDelayRSurN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+18,NN
316 #define readPCEDELDelayBack 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+20
317 #define writePCEDELDelayBackN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+20,NN
318 #define readPCEDELDelayLBak 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+20
319 #define writePCEDELDelayLBakN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+20,NN
320 #define readPCEDELDelayRBak 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+22
321 #define writePCEDELDelayRBakN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+22,NN
322 #define readPCEDELDelaySubw 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+24
323 #define writePCEDELDelaySubwN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+24,NN
324 #define readPCEDELDelayLSub 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+24
325 #define writePCEDELDelayLSubN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+24,NN
326 #define readPCEDELDelayRSub 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+26
327 #define writePCEDELDelayRSubN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+26,NN
328 #define readPCEDELDelayLHed 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28
329 #define writePCEDELDelayLHedN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+28,NN
330 #define readPCEDELDelayRHed 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30
331 #define writePCEDELDelayRHedN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+30,NN
332 //
333 #define readPCEDELDelayCHed 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+32
334 #define writePCEDELDelayCHedN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+32,NN
335 #define readPCEDELDelayTOvr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+34
336 #define writePCEDELDelayTOvrN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+34,NN
337 #define readPCEDELDelayLHSide 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+36
338 #define writePCEDELDelayLHSideN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+36,NN
339 #define readPCEDELDelayRHSide 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+38
340 #define writePCEDELDelayRHSideN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+38,NN
341 #define readPCEDELDelayLHRear 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+40
342 #define writePCEDELDelayLHRearN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+40,NN
343 #define readPCEDELDelayRHRear 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+42
344 #define writePCEDELDelayRHRearN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+42,NN
345 #define readPCEDELDelayCHRear 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+44
346 #define writePCEDELDelayCHRearN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+44,NN
347 //..
348 // Three channels -unassigned
349 //..
350 #define readPCEDELDelayLCtrInr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+52
351 #define writePCEDELDelayLCtrInrN(NN)0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+52,NN
352 #define readPCEDELDelayRCtrInr 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+54
353 #define writePCEDELDelayRCtrInrN(NN)0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+54,NN
354 //..
355 // Four channels -unassigned ie till PCE_PHASE_DELAY_CHAN_BASE+60
356 //..
358 #define readPCEDELDelayMaster 0xc300+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+PAF_MAXNUMCHAN_AF*2
359 #define writePCEDELDelayMasterN(NN) 0xcb00+STD_BETA_PCE,PCE_PHASE_DELAY_CHAN_BASE+PAF_MAXNUMCHAN_AF*2,NN
362 /* PAF_MAXNUMCHAN_AF == 32 */
364 #else /* PAF_MAXNUMCHAN */
365 #error unsupported option
366 #endif /* PAF_MAXNUMCHAN */
371 //
372 //---
373 //PCE OUTPUT PHASE Alpha codes
374 #define PCE_PHASE_OUTPUT_BASE PCE_PHASE_DELAY_CHAN_BASE+PCE_PHASE_DELAY_CHAN_LENGTH+2
375 //+2 is for DelayMaster
376 #define PCE_PHASE_OUTPUT_BASE_LENGTH 3 //4 - byte elements added
377 //Eg:-
378 //#define readPCEDELDelayMaster 0xc32e,0x0036
379 //#define readPCEExceptionDetectMode 0xc22e,0x3800
381 #define readPCEExceptionDetectMode 0xc200+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE)<<8)+0x00
382 #define writePCEExceptionDetectDisable 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE)<<8)+0x00
383 #define writePCEExceptionDetectEnable 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE)<<8)+0x01
385 #define readPCEExceptionDetectFlag 0xc200+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+1)<<8)+0x00
386 #define writePCEExceptionDetectFlagOff 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+1)<<8)+0x00
387 #define writePCEExceptionDetectFlagOn 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+1)<<8)+0x01
389 #define readPCEExceptionDetectMute 0xc200+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+2)<<8)+0x00
390 #define writePCEExceptionDetectUnmute 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+2)<<8)+0x00
391 #define writePCEExceptionDetectMute 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+2)<<8)+0x01
393 #define readPCEClipDetectFlag 0xc200+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+3)<<8)+0x00
394 #define writePCEClipDetectFlagOff 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+3)<<8)+0x00
395 #define writePCEClipDetectFlagOn 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+3)<<8)+0x01
397 #define readPCEBsMetadataType 0xc200+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+4)<<8)+0x00
399 #define readPCEMdInsert 0xc200+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+5)<<8)+0x00
400 #define writePCEMdInsertDisable 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+5)<<8)+0x00
401 #define writePCEMdInsertEnable 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+5)<<8)+0x01
403 #define readPCEMaxNumChMd 0xc200+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+6)<<8)+0x00
404 #define writePCEMaxNumChMd(N) 0xca00+STD_BETA_PCE,((PCE_PHASE_OUTPUT_BASE+6)<<8)+((N)&0xff)
407 #endif /* PCE_VERSION */
409 #define readPCEStatus 0xc508,STD_BETA_PCE
411 #if PCE_VERSION == 1
412 #define readPCEControl \
413 readPCEMode, \
414 readPCEModePhase0Mode, \
415 readPCEModePhase0Type, \
416 readPCEModePhase1Mode, \
417 readPCEModePhase1Type, \
418 readPCEModePhase2Mode, \
419 readPCEModePhase2Type, \
420 readPCEModePhase3Mode, \
421 readPCEModePhase3Type
422 #elif PCE_VERSION == 2
423 #define readPCEControl \
424 readPCEMode, \
425 readPCEModePhase0Mode, \
426 readPCEModePhase0Type, \
427 readPCEModePhase1Mode, \
428 readPCEModePhase1Type, \
429 readPCEModePhase2Mode, \
430 readPCEModePhase2Type, \
431 readPCEModePhase3Mode, \
432 readPCEModePhase3Type, \
433 readPCEModePhase4Mode, \
434 readPCEModePhase4Type, \
435 readPCEModePhase5Mode, \
436 readPCEModePhase5Type, \
437 readPCEDELUnit, \
438 readPCEDELNumb, \
439 readPCEDELDelayLeft, \
440 readPCEDELDelayRght, \
441 readPCEDELDelayCntr, \
442 readPCEDELDelayLCtr, \
443 readPCEDELDelayRCtr, \
444 readPCEDELDelayWide, \
445 readPCEDELDelayLWid, \
446 readPCEDELDelayRWid, \
447 readPCEDELDelayOver, \
448 readPCEDELDelayLOvr, \
449 readPCEDELDelayROvr, \
450 readPCEDELDelaySurr, \
451 readPCEDELDelayLSur, \
452 readPCEDELDelayRSur, \
453 readPCEDELDelayBack, \
454 readPCEDELDelayLBak, \
455 readPCEDELDelayRBak, \
456 readPCEDELDelaySubw, \
457 readPCEDELDelayLSub, \
458 readPCEDELDelayRSub, \
459 readPCEDELDelayLHed, \
460 readPCEDELDelayRHed
461 // readPCEDELDelayMaster
463 /* in support of inverse compilation only */
464 #define writePCEDELNumbXX__10__ writePCEDELNumbXX(10)
465 #define wrotePCEDELDelayLeft 0x0800+readPCEDELDelayLeft
466 #define wrotePCEDELDelayRght 0x0800+readPCEDELDelayRght
467 #define wrotePCEDELDelayCtr 0x0800+readPCEDELDelayCntr
468 #define wrotePCEDELDelayLCtr 0x0800+readPCEDELDelayLCtr
469 #define wrotePCEDELDelayRCtr 0x0800+readPCEDELDelayRCtr
470 #define wrotePCEDELDelayWide 0x0800+readPCEDELDelayWide
471 #define wrotePCEDELDelayLWid 0x0800+readPCEDELDelayLWid
472 #define wrotePCEDELDelayRWid 0x0800+readPCEDELDelayRWid
473 #define wrotePCEDELDelayOver 0x0800+readPCEDELDelayOver
474 #define wrotePCEDELDelayLOvr 0x0800+readPCEDELDelayLOvr
475 #define wrotePCEDELDelayROvr 0x0800+readPCEDELDelayROvr
476 #define wrotePCEDELDelaySurr 0x0800+readPCEDELDelaySurr
477 #define wrotePCEDELDelayLSur 0x0800+readPCEDELDelayLSur
478 #define wrotePCEDELDelayRSur 0x0800+readPCEDELDelayRSur
479 #define wrotePCEDELDelayBack 0x0800+readPCEDELDelayBack
480 #define wrotePCEDELDelayLBak 0x0800+readPCEDELDelayLBak
481 #define wrotePCEDELDelayRBak 0x0800+readPCEDELDelayRBak
482 #define wrotePCEDELDelaySubw 0x0800+readPCEDELDelaySubw
483 #define wrotePCEDELDelayLSub 0x0800+readPCEDELDelayLSub
484 #define wrotePCEDELDelayRSub 0x0800+readPCEDELDelayRSub
485 #define wrotePCEDELDelayLHed 0x0800+readPCEDELDelayLHed
486 #define wrotePCEDELDelayRHed 0x0800+readPCEDELDelayRHed
488 #endif /* PCE_VERSION */
490 #endif /* _PCE_A */