[processor-sdk/performance-audio-sr.git] / psdk_cust / ipc_3_43_00_00_eng / docs / cdoc / ti / sdo / ipc / family / vayu / InterruptIpu-src.html
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8 1 <span class="comment">/*
9 </span> 2 <span class="comment"> * Copyright (c) 2012-2014 Texas Instruments Incorporated - http://www.ti.com
10 </span> 3 <span class="comment"> * All rights reserved.
11 </span> 4 <span class="comment"> *
12 </span> 5 <span class="comment"> * Redistribution and use in source and binary forms, with or without
13 </span> 6 <span class="comment"> * modification, are permitted provided that the following conditions
14 </span> 7 <span class="comment"> * are met:
15 </span> 8 <span class="comment"> *
16 </span> 9 <span class="comment"> * * Redistributions of source code must retain the above copyright
17 </span> 10 <span class="comment"> * notice, this list of conditions and the following disclaimer.
18 </span> 11 <span class="comment"> *
19 </span> 12 <span class="comment"> * * Redistributions in binary form must reproduce the above copyright
20 </span> 13 <span class="comment"> * notice, this list of conditions and the following disclaimer in the
21 </span> 14 <span class="comment"> * documentation and/or other materials provided with the distribution.
22 </span> 15 <span class="comment"> *
23 </span> 16 <span class="comment"> * * Neither the name of Texas Instruments Incorporated nor the names of
24 </span> 17 <span class="comment"> * its contributors may be used to endorse or promote products derived
25 </span> 18 <span class="comment"> * from this software without specific prior written permission.
26 </span> 19 <span class="comment"> *
27 </span> 20 <span class="comment"> * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28 </span> 21 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 </span> 22 <span class="comment"> * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 </span> 23 <span class="comment"> * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 </span> 24 <span class="comment"> * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 </span> 25 <span class="comment"> * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 </span> 26 <span class="comment"> * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
34 </span> 27 <span class="comment"> * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
35 </span> 28 <span class="comment"> * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
36 </span> 29 <span class="comment"> * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
37 </span> 30 <span class="comment"> * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 </span> 31 <span class="comment"> */</span>
39 32 <span class="comment">/*
40 </span> 33 <span class="comment"> * ======== InterruptIpu.xdc ========
41 </span> 34 <span class="comment"> *
42 </span> 35 <span class="comment"> */</span>
43 36
44 37 import ti.sdo.utils.MultiProc;
45 38
46 39 <span class="xdoc">/*!
47 </span> 40 <span class="xdoc"> * ======== InterruptIpu ========
48 </span> 41 <span class="xdoc"> * IPU interrupt manager
49 </span> 42 <span class="xdoc"> */</span>
50 43 <span class=key>module</span> InterruptIpu <span class=key>inherits</span> ti.sdo.ipc.notifyDrivers.IInterrupt
51 44 {
52 45 <span class="xdoc">/*!
53 </span> 46 <span class="xdoc"> * Maximum number of cores
54 </span> 47 <span class="xdoc"> *
55 </span> 48 <span class="xdoc"> * <b>@_nodoc</b>
56 </span> 49 <span class="xdoc"> */</span>
57 50 <span class=key>const</span> UInt8 NUM_CORES = 11;
58 51
59 52 <span class="xdoc">/*!
60 </span> 53 <span class="xdoc"> * Maximum number of EVE cores
61 </span> 54 <span class="xdoc"> *
62 </span> 55 <span class="xdoc"> * Although your device may have fewer EVE cores, `NUM_EVES` represents
63 </span> 56 <span class="xdoc"> * the maximum number of EVEs that may be present on a Vayu system.
64 </span> 57 <span class="xdoc"> */</span>
65 58 <span class=key>const</span> UInt8 NUM_EVES = 4;
66 59
67 60 <span class="xdoc">/*!
68 </span> 61 <span class="xdoc"> * Maximum number of IPU cores
69 </span> 62 <span class="xdoc"> *
70 </span> 63 <span class="xdoc"> * <b>@_nodoc</b>
71 </span> 64 <span class="xdoc"> */</span>
72 65 <span class=key>const</span> UInt8 NUM_Ipu_CORES = 2;
73 66
74 67 <span class="xdoc">/*!
75 </span> 68 <span class="xdoc"> * Number of internal EVE mailboxes
76 </span> 69 <span class="xdoc"> *
77 </span> 70 <span class="xdoc"> * Each EVE core has 3 mailboxes.
78 </span> 71 <span class="xdoc"> *
79 </span> 72 <span class="xdoc"> * Although your device may have fewer EVE cores, `NUM_EVE_MBX` represents
80 </span> 73 <span class="xdoc"> * the maximum number of EVE mailboxes (including all EVE cores) that may
81 </span> 74 <span class="xdoc"> * be present.
82 </span> 75 <span class="xdoc"> */</span>
83 76 <span class=key>const</span> UInt8 NUM_EVE_MBX = NUM_EVES * 3;
84 77
85 78 <span class="xdoc">/*!
86 </span> 79 <span class="xdoc"> * Number of System mailboxes used by IPC
87 </span> 80 <span class="xdoc"> *
88 </span> 81 <span class="xdoc"> * This represents the number of System mailboxes used by IPC. IPC
89 </span> 82 <span class="xdoc"> * currently uses system mailboxes 5, 6, 7 and 8.
90 </span> 83 <span class="xdoc"> */</span>
91 84 <span class=key>const</span> UInt8 NUM_SYS_MBX = 4;
92 85
93 86 <span class="xdoc">/*!
94 </span> 87 <span class="xdoc"> * Base address for the mailbox subsystems
95 </span> 88 <span class="xdoc"> *
96 </span> 89 <span class="xdoc"> * The `mailboxBaseAddr` array indicates the virtual addresses through
97 </span> 90 <span class="xdoc"> * which IPC will access various mailboxes. The specific mailbox addresses
98 </span> 91 <span class="xdoc"> * each array index maps to follows:
99 </span> 92 <span class="xdoc"> * <b>@p(blist)</b>
100 </span> 93 <span class="xdoc"> * - 0 - EVE1 MBX0
101 </span> 94 <span class="xdoc"> * - 1 - EVE1 MBX1
102 </span> 95 <span class="xdoc"> * - 2 - EVE1 MBX2 (unused, do not assign)
103 </span> 96 <span class="xdoc"> * - 3 - EVE2 MBX0
104 </span> 97 <span class="xdoc"> * - 4 - EVE2 MBX1
105 </span> 98 <span class="xdoc"> * - 5 - EVE2 MBX2 (unused, do not assign)
106 </span> 99 <span class="xdoc"> * - 6 - EVE3 MBX0
107 </span> 100 <span class="xdoc"> * - 7 - EVE3 MBX1
108 </span> 101 <span class="xdoc"> * - 8 - EVE1 MBX2 (unused, do not assign)
109 </span> 102 <span class="xdoc"> * - 9 - EVE4 MBX0
110 </span> 103 <span class="xdoc"> * - 10 - EVE4 MBX1
111 </span> 104 <span class="xdoc"> * - 11 - EVE1 MBX2 (unused, do not assign)
112 </span> 105 <span class="xdoc"> * - 12 - System Mailbox 5
113 </span> 106 <span class="xdoc"> * - 13 - System Mailbox 6
114 </span> 107 <span class="xdoc"> * - 14 - System Mailbox 7
115 </span> 108 <span class="xdoc"> * - 15 - System Mailbox 8
116 </span> 109 <span class="xdoc"> * <b>@p</b>
117 </span> 110 <span class="xdoc"> *
118 </span> 111 <span class="xdoc"> * Note that these mailboxes are not accessible at their physical
119 </span> 112 <span class="xdoc"> * addresses (in the 0x4XXX_XXXX range). So default virtual addresses
120 </span> 113 <span class="xdoc"> * through which these mailboxes will be accessed are assigned in the
121 </span> 114 <span class="xdoc"> * 0x6XXX_XXXX range. Users must ensure these virtual addresses are
122 </span> 115 <span class="xdoc"> * correctly mapped to the 0x4XXX_XXXX-based phys addrs in each IPUs AMMU.
123 </span> 116 <span class="xdoc"> */</span>
124 117 <span class=key>config</span> UInt32 mailboxBaseAddr[NUM_EVE_MBX + NUM_SYS_MBX];
125 118
126 119 <span class="xdoc">/*!
127 </span> 120 <span class="xdoc"> * Mailbox table for storing encoded Base Address, mailbox user Id,
128 </span> 121 <span class="xdoc"> * and sub-mailbox index.
129 </span> 122 <span class="xdoc"> *
130 </span> 123 <span class="xdoc"> * <b>@_nodoc</b>
131 </span> 124 <span class="xdoc"> */</span>
132 125 <span class=key>config</span> UInt32 mailboxTable[NUM_CORES * NUM_CORES];
133 126
134 127 <span class="xdoc">/*!
135 </span> 128 <span class="xdoc"> * Base address for the Ducati CTRL register
136 </span> 129 <span class="xdoc"> */</span>
137 130 <span class=key>config</span> UInt32 ducatiCtrlBaseAddr = 0x40001000;
138 131
139 132 <span class="xdoc">/*!
140 </span> 133 <span class="xdoc"> * Processor Id table
141 </span> 134 <span class="xdoc"> *
142 </span> 135 <span class="xdoc"> * <b>@_nodoc</b>
143 </span> 136 <span class="xdoc"> */</span>
144 137 <span class=key>config</span> UInt32 procIdTable[NUM_CORES];
145 138
146 139 <span class=key>internal</span>:
147 140
148 141 <span class="xdoc">/*! Statically retrieve procIds to avoid doing this at runtime */</span>
149 142 <span class=key>config</span> UInt eve1ProcId = MultiProc.INVALIDID;
150 143 <span class=key>config</span> UInt eve2ProcId = MultiProc.INVALIDID;
151 144 <span class=key>config</span> UInt eve3ProcId = MultiProc.INVALIDID;
152 145 <span class=key>config</span> UInt eve4ProcId = MultiProc.INVALIDID;
153 146 <span class=key>config</span> UInt dsp1ProcId = MultiProc.INVALIDID;
154 147 <span class=key>config</span> UInt dsp2ProcId = MultiProc.INVALIDID;
155 148 <span class=key>config</span> UInt ipu1_0ProcId = MultiProc.INVALIDID;
156 149 <span class=key>config</span> UInt ipu2_0ProcId = MultiProc.INVALIDID;
157 150 <span class=key>config</span> UInt hostProcId = MultiProc.INVALIDID;
158 151 <span class=key>config</span> UInt ipu1_1ProcId = MultiProc.INVALIDID;
159 152 <span class=key>config</span> UInt ipu2_1ProcId = MultiProc.INVALIDID;
160 153
161 154 <span class="xdoc">/*! Function table */</span>
162 155 <span class=key>struct</span> FxnTable {
163 156 Fxn func;
164 157 UArg arg;
165 158 }
166 159
167 160 <span class="xdoc">/*! Stub to be plugged for inter-ducati interrupts */</span>
168 161 Void intShmDucatiStub(UArg arg);
169 162
170 163 <span class="xdoc">/*! Stub to be plugged for intra-ducati interrupts */</span>
171 164 Void intShmMbxStub(UInt16 idx);
172 165
173 166 <span class=key>struct</span> Module_State {
174 167 <span class="comment">/*
175 </span> 168 <span class="comment"> * Create a function table of length 8 (Total number of cores in the
176 </span> 169 <span class="comment"> * System) for each M4 core.
177 </span> 170 <span class="comment"> */</span>
178 171 FxnTable fxnTable[NUM_CORES];
179 172 };
180 173 }
181 </pre>
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