[processor-sdk/performance-audio-sr.git] / psdk_cust / libarch_k2g_1_0_1_0 / examples / dsponly / k2g / src / k2g_edma3_region.c
1 /*
2 * k2g_edma3_region.c
3 *
4 * Sample file showing the initialization of EDMA3 regions.
5 *
6 * Copyright (C) 2009-2017 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sdo/edma3/drv/edma3_drv.h>
40 #include <ti/sdo/edma3/rm/edma3_rm.h>
42 /* Number of EDMA3 controllers present in the system */
43 #define NUM_EDMA3_INSTANCES 2u
45 /* Driver Object Initialization Configuration */
46 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
47 {
48 {
49 /* EDMA3 INSTANCE# 0 */
50 /** Total number of DMA Channels supported by the EDMA3 Controller */
51 64u,
52 /** Total number of QDMA Channels supported by the EDMA3 Controller */
53 8u,
54 /** Total number of TCCs supported by the EDMA3 Controller */
55 64u,
56 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
57 512u,
58 /** Total number of Event Queues in the EDMA3 Controller */
59 2u,
60 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
61 2u,
62 /** Number of Regions on this EDMA3 controller */
63 8u,
65 /**
66 * \brief Channel mapping existence
67 * A value of 0 (No channel mapping) implies that there is fixed association
68 * for a channel number to a parameter entry number or, in other words,
69 * PaRAM entry n corresponds to channel n.
70 */
71 1u,
73 /** Existence of memory protection feature */
74 1u,
76 /** Global Register Region of CC Registers */
77 (void *)0x02700000u,
78 /** Transfer Controller (TC) Registers */
79 {
80 (void *)0x02760000u,
81 (void *)0x02768000u,
82 (void *)NULL,
83 (void *)NULL,
84 (void *)NULL,
85 (void *)NULL,
86 (void *)NULL,
87 (void *)NULL
88 },
89 /** Interrupt no. for Transfer Completion */
90 0x88,
91 /** Interrupt no. for CC Error */
92 0x99,
93 /** Interrupt no. for TCs Error */
94 {
95 0xA0,
96 0xA1,
97 0u,
98 0u,
99 0u,
100 0u,
101 0u,
102 0u,
103 },
105 /**
106 * \brief EDMA3 TC priority setting
107 *
108 * User can program the priority of the Event Queues
109 * at a system-wide level. This means that the user can set the
110 * priority of an IO initiated by either of the TCs (Transfer Controllers)
111 * relative to IO initiated by the other bus masters on the
112 * device (ARM, DSP, USB, etc)
113 */
114 {
115 0u,
116 1u,
117 0u,
118 0u,
119 0u,
120 0u,
121 0u,
122 0u
123 },
124 /**
125 * \brief To Configure the Threshold level of number of events
126 * that can be queued up in the Event queues. EDMA3CC error register
127 * (CCERR) will indicate whether or not at any instant of time the
128 * number of events queued up in any of the event queues exceeds
129 * or equals the threshold/watermark value that is set
130 * in the queue watermark threshold register (QWMTHRA).
131 */
132 {
133 16u,
134 16u,
135 0u,
136 0u,
137 0u,
138 0u,
139 0u,
140 0u
141 },
143 /**
144 * \brief To Configure the Default Burst Size (DBS) of TCs.
145 * An optimally-sized command is defined by the transfer controller
146 * default burst size (DBS). Different TCs can have different
147 * DBS values. It is defined in Bytes.
148 */
149 {
150 256u,
151 256u,
152 0u,
153 0u,
154 0u,
155 0u,
156 0u,
157 0u
158 },
160 /**
161 * \brief Mapping from each DMA channel to a Parameter RAM set,
162 * if it exists, otherwise of no use.
163 */
164 {
165 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
166 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
167 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
168 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
169 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
170 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
171 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
172 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
173 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
174 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
175 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
176 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
177 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
178 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
179 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
180 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
181 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
182 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
183 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
184 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
185 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
186 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
187 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
188 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
189 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
190 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
191 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
192 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
193 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
194 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
195 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
196 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
197 },
199 /**
200 * \brief Mapping from each DMA channel to a TCC. This specific
201 * TCC code will be returned when the transfer is completed
202 * on the mapped channel.
203 */
204 {
205 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
206 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
207 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
208 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
209 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
210 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
211 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
212 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
213 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
214 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
215 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
216 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
217 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
218 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
219 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
220 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
221 },
223 /**
224 * \brief Mapping of DMA channels to Hardware Events from
225 * various peripherals, which use EDMA for data transfer.
226 * All channels need not be mapped, some can be free also.
227 */
228 {
229 0xFFFFFFFFu,
230 0x00000000u
231 }
232 },
234 {
235 /* EDMA3 INSTANCE# 1 */
236 /** Total number of DMA Channels supported by the EDMA3 Controller */
237 64u,
238 /** Total number of QDMA Channels supported by the EDMA3 Controller */
239 8u,
240 /** Total number of TCCs supported by the EDMA3 Controller */
241 64u,
242 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
243 512u,
244 /** Total number of Event Queues in the EDMA3 Controller */
245 2u,
246 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
247 2u,
248 /** Number of Regions on this EDMA3 controller */
249 8u,
251 /**
252 * \brief Channel mapping existence
253 * A value of 0 (No channel mapping) implies that there is fixed association
254 * for a channel number to a parameter entry number or, in other words,
255 * PaRAM entry n corresponds to channel n.
256 */
257 1u,
259 /** Existence of memory protection feature */
260 1u,
262 /** Global Register Region of CC Registers */
263 (void *)0x02728000u,
264 /** Transfer Controller (TC) Registers */
265 {
266 (void *)0x027B0000u,
267 (void *)0x027B8000u,
268 (void *)NULL,
269 (void *)NULL,
270 (void *)NULL,
271 (void *)NULL,
272 (void *)NULL,
273 (void *)NULL
274 },
275 /** Interrupt no. for Transfer Completion */
276 0x90,
277 /** Interrupt no. for CC Error */
278 0x9C,
279 /** Interrupt no. for TCs Error */
280 {
281 0xA4,
282 0xA5,
283 0u,
284 0u,
285 0u,
286 0u,
287 0u,
288 0u,
289 },
291 /**
292 * \brief EDMA3 TC priority setting
293 *
294 * User can program the priority of the Event Queues
295 * at a system-wide level. This means that the user can set the
296 * priority of an IO initiated by either of the TCs (Transfer Controllers)
297 * relative to IO initiated by the other bus masters on the
298 * device (ARM, DSP, USB, etc)
299 */
300 {
301 0u,
302 1u,
303 2u,
304 3u,
305 0u,
306 0u,
307 0u,
308 0u
309 },
310 /**
311 * \brief To Configure the Threshold level of number of events
312 * that can be queued up in the Event queues. EDMA3CC error register
313 * (CCERR) will indicate whether or not at any instant of time the
314 * number of events queued up in any of the event queues exceeds
315 * or equals the threshold/watermark value that is set
316 * in the queue watermark threshold register (QWMTHRA).
317 */
318 {
319 16u,
320 16u,
321 16u,
322 16u,
323 0u,
324 0u,
325 0u,
326 0u
327 },
329 /**
330 * \brief To Configure the Default Burst Size (DBS) of TCs.
331 * An optimally-sized command is defined by the transfer controller
332 * default burst size (DBS). Different TCs can have different
333 * DBS values. It is defined in Bytes.
334 */
335 {
336 128u,
337 128u,
338 128u,
339 128u,
340 0u,
341 0u,
342 0u,
343 0u
344 },
346 /**
347 * \brief Mapping from each DMA channel to a Parameter RAM set,
348 * if it exists, otherwise of no use.
349 */
350 {
351 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
352 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
353 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
354 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
355 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
356 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
357 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
358 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
359 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
360 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
361 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
362 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
363 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
364 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
365 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
366 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
367 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
368 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
369 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
370 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
371 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
372 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
373 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
374 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
375 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
376 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
377 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
378 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
379 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
380 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
381 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
382 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
383 },
385 /**
386 * \brief Mapping from each DMA channel to a TCC. This specific
387 * TCC code will be returned when the transfer is completed
388 * on the mapped channel.
389 */
390 {
391 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
392 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
393 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
394 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
395 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
396 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
397 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
398 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
399 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
400 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
401 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
402 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
403 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
404 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
405 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
406 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
407 },
409 /**
410 * \brief Mapping of DMA channels to Hardware Events from
411 * various peripherals, which use EDMA for data transfer.
412 * All channels need not be mapped, some can be free also.
413 */
414 {
415 0xFFFFFFFFu,
416 0x00000000u
417 }
418 },
419 }; /* sampleEdma3GblCfgParams */
421 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
422 {
423 /* EDMA3 INSTANCE# 0 */
424 {
425 /* Resources owned/reserved by region 0 */
426 {
427 /* ownPaRAMSets */
428 /* 31 0 63 32 95 64 127 96 */
429 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
430 /* 159 128 191 160 223 192 255 224 */
431 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
432 /* 287 256 319 288 351 320 383 352 */
433 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
434 /* 415 384 447 416 479 448 511 480 */
435 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
437 /* ownDmaChannels */
438 /* 31 0 63 32 */
439 {0x000000FFu, 0x00000000u},
441 /* ownQdmaChannels */
442 /* 31 0 */
443 {0x00000001u},
445 /* ownTccs */
446 /* 31 0 63 32 */
447 {0x000000FFu, 0x00000000u},
449 /* resvdPaRAMSets */
450 /* 31 0 63 32 95 64 127 96 */
451 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
452 /* 159 128 191 160 223 192 255 224 */
453 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
454 /* 287 256 319 288 351 320 383 352 */
455 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
456 /* 415 384 447 416 479 448 511 480 */
457 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
459 /* resvdDmaChannels */
460 /* 31 0 63 32 */
461 {0x00000000u, 0x00000000u},
463 /* resvdQdmaChannels */
464 /* 31 0 */
465 {0x00000000u},
467 /* resvdTccs */
468 /* 31 0 63 32 */
469 {0x00000000u, 0x00000000u},
470 },
472 /* Resources owned/reserved by region 1 */
473 {
474 /* ownPaRAMSets */
475 /* 31 0 63 32 95 64 127 96 */
476 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
477 /* 159 128 191 160 223 192 255 224 */
478 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
479 /* 287 256 319 288 351 320 383 352 */
480 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
481 /* 415 384 447 416 479 448 511 480 */
482 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
484 /* ownDmaChannels */
485 /* 31 0 63 32 */
486 {0x0000FF00u, 0x00000000u},
488 /* ownQdmaChannels */
489 /* 31 0 */
490 {0x00000002u},
492 /* ownTccs */
493 /* 31 0 63 32 */
494 {0x0000FF00u, 0x00000000u},
496 /* resvdPaRAMSets */
497 /* 31 0 63 32 95 64 127 96 */
498 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
499 /* 159 128 191 160 223 192 255 224 */
500 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
501 /* 287 256 319 288 351 320 383 352 */
502 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
503 /* 415 384 447 416 479 448 511 480 */
504 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
506 /* resvdDmaChannels */
507 /* 31 0 63 32 */
508 {0x00000000u, 0x00000000u},
510 /* resvdQdmaChannels */
511 /* 31 0 */
512 {0x00000000u},
514 /* resvdTccs */
515 /* 31 0 63 32 */
516 {0x00000000u, 0x00000000u},
517 },
519 /* Resources owned/reserved by region 2 */
520 {
521 /* ownPaRAMSets */
522 /* 31 0 63 32 95 64 127 96 */
523 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
524 /* 159 128 191 160 223 192 255 224 */
525 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
526 /* 287 256 319 288 351 320 383 352 */
527 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
528 /* 415 384 447 416 479 448 511 480 */
529 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
531 /* ownDmaChannels */
532 /* 31 0 63 32 */
533 {0x00FF0000u, 0x0000000u},
535 /* ownQdmaChannels */
536 /* 31 0 */
537 {0x00000004u},
539 /* ownTccs */
540 /* 31 0 63 32 */
541 {0x00FF0000u, 0x00000000u},
543 /* resvdPaRAMSets */
544 /* 31 0 63 32 95 64 127 96 */
545 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
546 /* 159 128 191 160 223 192 255 224 */
547 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
548 /* 287 256 319 288 351 320 383 352 */
549 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
550 /* 415 384 447 416 479 448 511 480 */
551 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
553 /* resvdDmaChannels */
554 /* 31 0 63 32 */
555 {0x00000000u, 0x00000000u},
557 /* resvdQdmaChannels */
558 /* 31 0 */
559 {0x00000000u},
561 /* resvdTccs */
562 /* 31 0 63 32 */
563 {0x00000000u, 0x00000000u},
564 },
566 /* Resources owned/reserved by region 3 */
567 {
568 /* ownPaRAMSets */
569 /* 31 0 63 32 95 64 127 96 */
570 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
571 /* 159 128 191 160 223 192 255 224 */
572 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
573 /* 287 256 319 288 351 320 383 352 */
574 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
575 /* 415 384 447 416 479 448 511 480 */
576 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
578 /* ownDmaChannels */
579 /* 31 0 63 32 */
580 {0xFF000000u, 0x00000000u},
582 /* ownQdmaChannels */
583 /* 31 0 */
584 {0x00000008u},
586 /* ownTccs */
587 /* 31 0 63 32 */
588 {0xFF000000u, 0x00000000u},
590 /* resvdPaRAMSets */
591 /* 31 0 63 32 95 64 127 96 */
592 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
593 /* 159 128 191 160 223 192 255 224 */
594 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
595 /* 287 256 319 288 351 320 383 352 */
596 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
597 /* 415 384 447 416 479 448 511 480 */
598 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
600 /* resvdDmaChannels */
601 /* 31 0 63 32 */
602 {0x00000000u, 0x00000000u},
604 /* resvdQdmaChannels */
605 /* 31 0 */
606 {0x00000000u},
608 /* resvdTccs */
609 /* 31 0 63 32 */
610 {0x00000000u, 0x00000000u},
611 },
613 /* Resources owned/reserved by region 4 */
614 {
615 /* ownPaRAMSets */
616 /* 31 0 63 32 95 64 127 96 */
617 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
618 /* 159 128 191 160 223 192 255 224 */
619 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
620 /* 287 256 319 288 351 320 383 352 */
621 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
622 /* 415 384 447 416 479 448 511 480 */
623 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
625 /* ownDmaChannels */
626 /* 31 0 63 32 */
627 {0x00000000u, 0x000000FFu},
629 /* ownQdmaChannels */
630 /* 31 0 */
631 {0x00000010u},
633 /* ownTccs */
634 /* 31 0 63 32 */
635 {0x00000000u, 0x000000FFu},
637 /* resvdPaRAMSets */
638 /* 31 0 63 32 95 64 127 96 */
639 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
640 /* 159 128 191 160 223 192 255 224 */
641 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
642 /* 287 256 319 288 351 320 383 352 */
643 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
644 /* 415 384 447 416 479 448 511 480 */
645 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
647 /* resvdDmaChannels */
648 /* 31 0 63 32 */
649 {0x00000000u, 0x00000000u},
651 /* resvdQdmaChannels */
652 /* 31 0 */
653 {0x00000000u},
655 /* resvdTccs */
656 /* 31 0 63 32 */
657 {0x00000000u, 0x00000000u},
658 },
660 /* Resources owned/reserved by region 5 */
661 {
662 /* ownPaRAMSets */
663 /* 31 0 63 32 95 64 127 96 */
664 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
665 /* 159 128 191 160 223 192 255 224 */
666 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
667 /* 287 256 319 288 351 320 383 352 */
668 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
669 /* 415 384 447 416 479 448 511 480 */
670 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
672 /* ownDmaChannels */
673 /* 31 0 63 32 */
674 {0x00000000u, 0x0000FF00u},
676 /* ownQdmaChannels */
677 /* 31 0 */
678 {0x00000020u},
680 /* ownTccs */
681 /* 31 0 63 32 */
682 {0x00000000u, 0x0000FF00u},
684 /* resvdPaRAMSets */
685 /* 31 0 63 32 95 64 127 96 */
686 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
687 /* 159 128 191 160 223 192 255 224 */
688 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
689 /* 287 256 319 288 351 320 383 352 */
690 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
691 /* 415 384 447 416 479 448 511 480 */
692 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
694 /* resvdDmaChannels */
695 /* 31 0 63 32 */
696 {0x00000000u, 0x00000000u},
698 /* resvdQdmaChannels */
699 /* 31 0 */
700 {0x00000000u},
702 /* resvdTccs */
703 /* 31 0 63 32 */
704 {0x00000000u, 0x00000000u},
705 },
707 /* Resources owned/reserved by region 6 */
708 {
709 /* ownPaRAMSets */
710 /* 31 0 63 32 95 64 127 96 */
711 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
712 /* 159 128 191 160 223 192 255 224 */
713 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
714 /* 287 256 319 288 351 320 383 352 */
715 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
716 /* 415 384 447 416 479 448 511 480 */
717 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
719 /* ownDmaChannels */
720 /* 31 0 63 32 */
721 {0x00000000u, 0x00FF0000u},
723 /* ownQdmaChannels */
724 /* 31 0 */
725 {0x00000040u},
727 /* ownTccs */
728 /* 31 0 63 32 */
729 {0x00000000u, 0x00FF0000u},
731 /* resvdPaRAMSets */
732 /* 31 0 63 32 95 64 127 96 */
733 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
734 /* 159 128 191 160 223 192 255 224 */
735 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
736 /* 287 256 319 288 351 320 383 352 */
737 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
738 /* 415 384 447 416 479 448 511 480 */
739 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
741 /* resvdDmaChannels */
742 /* 31 0 63 32 */
743 {0x00000000u, 0x00000000u},
745 /* resvdQdmaChannels */
746 /* 31 0 */
747 {0x00000000u},
749 /* resvdTccs */
750 /* 31 0 63 32 */
751 {0x00000000u, 0x00000000u},
752 },
754 /* Resources owned/reserved by region 7 */
755 {
756 /* ownPaRAMSets */
757 /* 31 0 63 32 95 64 127 96 */
758 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
759 /* 159 128 191 160 223 192 255 224 */
760 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
761 /* 287 256 319 288 351 320 383 352 */
762 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
763 /* 415 384 447 416 479 448 511 480 */
764 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
766 /* ownDmaChannels */
767 /* 31 0 63 32 */
768 {0x00000000u, 0xFF000000u},
770 /* ownQdmaChannels */
771 /* 31 0 */
772 {0x00000080u},
774 /* ownTccs */
775 /* 31 0 63 32 */
776 {0x00000000u, 0xFF000000u},
778 /* resvdPaRAMSets */
779 /* 31 0 63 32 95 64 127 96 */
780 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
781 /* 159 128 191 160 223 192 255 224 */
782 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
783 /* 287 256 319 288 351 320 383 352 */
784 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
785 /* 415 384 447 416 479 448 511 480 */
786 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
788 /* resvdDmaChannels */
789 /* 31 0 63 32 */
790 {0x00000000u, 0x00000000u},
792 /* resvdQdmaChannels */
793 /* 31 0 */
794 {0x00000000u},
796 /* resvdTccs */
797 /* 31 0 63 32 */
798 {0x00000000u, 0x00000000u},
799 },
800 },
802 /* EDMA3 INSTANCE# 1 */
803 {
804 /* Resources owned/reserved by region 0 */
805 {
806 /* ownPaRAMSets */
807 /* 31 0 63 32 95 64 127 96 */
808 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
809 /* 159 128 191 160 223 192 255 224 */
810 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
811 /* 287 256 319 288 351 320 383 352 */
812 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
813 /* 415 384 447 416 479 448 511 480 */
814 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
816 /* ownDmaChannels */
817 /* 31 0 63 32 */
818 {0xFFFFFFFFu, 0xFFFFFFFFu},
820 /* ownQdmaChannels */
821 /* 31 0 */
822 {0x00000001u},
824 /* ownTccs */
825 /* 31 0 63 32 */
826 {0xFFFFFFFFu, 0xFFFFFFFFu},
828 /* resvdPaRAMSets */
829 /* 31 0 63 32 95 64 127 96 */
830 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
831 /* 159 128 191 160 223 192 255 224 */
832 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
833 /* 287 256 319 288 351 320 383 352 */
834 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
835 /* 415 384 447 416 479 448 511 480 */
836 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
838 /* resvdDmaChannels */
839 /* 31 0 63 32 */
840 {0x00000000u, 0x00000000u},
842 /* resvdQdmaChannels */
843 /* 31 0 */
844 {0x00000000u},
846 /* resvdTccs */
847 /* 31 0 63 32 */
848 {0x00000000u, 0x00000000u},
849 },
851 /* Resources owned/reserved by region 1 */
852 {
853 /* ownPaRAMSets */
854 /* 31 0 63 32 95 64 127 96 */
855 {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
856 /* 159 128 191 160 223 192 255 224 */
857 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
858 /* 287 256 319 288 351 320 383 352 */
859 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
860 /* 415 384 447 416 479 448 511 480 */
861 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
863 /* ownDmaChannels */
864 /* 31 0 63 32 */
865 {0x0000FF00u, 0x00000000u},
867 /* ownQdmaChannels */
868 /* 31 0 */
869 {0x00000002u},
871 /* ownTccs */
872 /* 31 0 63 32 */
873 {0x0000FF00u, 0x00000000u},
875 /* resvdPaRAMSets */
876 /* 31 0 63 32 95 64 127 96 */
877 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
878 /* 159 128 191 160 223 192 255 224 */
879 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
880 /* 287 256 319 288 351 320 383 352 */
881 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
882 /* 415 384 447 416 479 448 511 480 */
883 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
885 /* resvdDmaChannels */
886 /* 31 0 63 32 */
887 {0x00000000u, 0x00000000u},
889 /* resvdQdmaChannels */
890 /* 31 0 */
891 {0x00000000u},
893 /* resvdTccs */
894 /* 31 0 63 32 */
895 {0x00000000u, 0x00000000u},
896 },
898 /* Resources owned/reserved by region 2 */
899 {
900 /* ownPaRAMSets */
901 /* 31 0 63 32 95 64 127 96 */
902 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
903 /* 159 128 191 160 223 192 255 224 */
904 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
905 /* 287 256 319 288 351 320 383 352 */
906 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
907 /* 415 384 447 416 479 448 511 480 */
908 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
910 /* ownDmaChannels */
911 /* 31 0 63 32 */
912 {0x00FF0000u, 0x0000000u},
914 /* ownQdmaChannels */
915 /* 31 0 */
916 {0x00000004u},
918 /* ownTccs */
919 /* 31 0 63 32 */
920 {0x00FF0000u, 0x00000000u},
922 /* resvdPaRAMSets */
923 /* 31 0 63 32 95 64 127 96 */
924 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
925 /* 159 128 191 160 223 192 255 224 */
926 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
927 /* 287 256 319 288 351 320 383 352 */
928 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
929 /* 415 384 447 416 479 448 511 480 */
930 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
932 /* resvdDmaChannels */
933 /* 31 0 63 32 */
934 {0x00000000u, 0x00000000u},
936 /* resvdQdmaChannels */
937 /* 31 0 */
938 {0x00000000u},
940 /* resvdTccs */
941 /* 31 0 63 32 */
942 {0x00000000u, 0x00000000u},
943 },
945 /* Resources owned/reserved by region 3 */
946 {
947 /* ownPaRAMSets */
948 /* 31 0 63 32 95 64 127 96 */
949 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
950 /* 159 128 191 160 223 192 255 224 */
951 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
952 /* 287 256 319 288 351 320 383 352 */
953 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
954 /* 415 384 447 416 479 448 511 480 */
955 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
957 /* ownDmaChannels */
958 /* 31 0 63 32 */
959 {0xFF000000u, 0x00000000u},
961 /* ownQdmaChannels */
962 /* 31 0 */
963 {0x00000008u},
965 /* ownTccs */
966 /* 31 0 63 32 */
967 {0xFF000000u, 0x00000000u},
969 /* resvdPaRAMSets */
970 /* 31 0 63 32 95 64 127 96 */
971 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
972 /* 159 128 191 160 223 192 255 224 */
973 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
974 /* 287 256 319 288 351 320 383 352 */
975 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
976 /* 415 384 447 416 479 448 511 480 */
977 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
979 /* resvdDmaChannels */
980 /* 31 0 63 32 */
981 {0x00000000u, 0x00000000u},
983 /* resvdQdmaChannels */
984 /* 31 0 */
985 {0x00000000u},
987 /* resvdTccs */
988 /* 31 0 63 32 */
989 {0x00000000u, 0x00000000u},
990 },
992 /* Resources owned/reserved by region 4 */
993 {
994 /* ownPaRAMSets */
995 /* 31 0 63 32 95 64 127 96 */
996 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
997 /* 159 128 191 160 223 192 255 224 */
998 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
999 /* 287 256 319 288 351 320 383 352 */
1000 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
1001 /* 415 384 447 416 479 448 511 480 */
1002 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1004 /* ownDmaChannels */
1005 /* 31 0 63 32 */
1006 {0x00000000u, 0x000000FFu},
1008 /* ownQdmaChannels */
1009 /* 31 0 */
1010 {0x00000010u},
1012 /* ownTccs */
1013 /* 31 0 63 32 */
1014 {0x00000000u, 0x000000FFu},
1016 /* resvdPaRAMSets */
1017 /* 31 0 63 32 95 64 127 96 */
1018 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1019 /* 159 128 191 160 223 192 255 224 */
1020 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1021 /* 287 256 319 288 351 320 383 352 */
1022 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1023 /* 415 384 447 416 479 448 511 480 */
1024 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1026 /* resvdDmaChannels */
1027 /* 31 0 63 32 */
1028 {0x00000000u, 0x00000000u},
1030 /* resvdQdmaChannels */
1031 /* 31 0 */
1032 {0x00000000u},
1034 /* resvdTccs */
1035 /* 31 0 63 32 */
1036 {0x00000000u, 0x00000000u},
1037 },
1039 /* Resources owned/reserved by region 5 */
1040 {
1041 /* ownPaRAMSets */
1042 /* 31 0 63 32 95 64 127 96 */
1043 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1044 /* 159 128 191 160 223 192 255 224 */
1045 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1046 /* 287 256 319 288 351 320 383 352 */
1047 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
1048 /* 415 384 447 416 479 448 511 480 */
1049 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
1051 /* ownDmaChannels */
1052 /* 31 0 63 32 */
1053 {0x00000000u, 0x0000FF00u},
1055 /* ownQdmaChannels */
1056 /* 31 0 */
1057 {0x00000020u},
1059 /* ownTccs */
1060 /* 31 0 63 32 */
1061 {0x00000000u, 0x0000FF00u},
1063 /* resvdPaRAMSets */
1064 /* 31 0 63 32 95 64 127 96 */
1065 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1066 /* 159 128 191 160 223 192 255 224 */
1067 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1068 /* 287 256 319 288 351 320 383 352 */
1069 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1070 /* 415 384 447 416 479 448 511 480 */
1071 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1073 /* resvdDmaChannels */
1074 /* 31 0 63 32 */
1075 {0x00000000u, 0x00000000u},
1077 /* resvdQdmaChannels */
1078 /* 31 0 */
1079 {0x00000000u},
1081 /* resvdTccs */
1082 /* 31 0 63 32 */
1083 {0x00000000u, 0x00000000u},
1084 },
1086 /* Resources owned/reserved by region 6 */
1087 {
1088 /* ownPaRAMSets */
1089 /* 31 0 63 32 95 64 127 96 */
1090 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1091 /* 159 128 191 160 223 192 255 224 */
1092 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1093 /* 287 256 319 288 351 320 383 352 */
1094 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1095 /* 415 384 447 416 479 448 511 480 */
1096 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1098 /* ownDmaChannels */
1099 /* 31 0 63 32 */
1100 {0x00000000u, 0x00FF0000u},
1102 /* ownQdmaChannels */
1103 /* 31 0 */
1104 {0x00000040u},
1106 /* ownTccs */
1107 /* 31 0 63 32 */
1108 {0x00000000u, 0x00FF0000u},
1110 /* resvdPaRAMSets */
1111 /* 31 0 63 32 95 64 127 96 */
1112 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1113 /* 159 128 191 160 223 192 255 224 */
1114 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1115 /* 287 256 319 288 351 320 383 352 */
1116 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1117 /* 415 384 447 416 479 448 511 480 */
1118 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1120 /* resvdDmaChannels */
1121 /* 31 0 63 32 */
1122 {0x00000000u, 0x00000000u},
1124 /* resvdQdmaChannels */
1125 /* 31 0 */
1126 {0x00000000u},
1128 /* resvdTccs */
1129 /* 31 0 63 32 */
1130 {0x00000000u, 0x00000000u},
1131 },
1133 /* Resources owned/reserved by region 7 */
1134 {
1135 /* ownPaRAMSets */
1136 /* 31 0 63 32 95 64 127 96 */
1137 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1138 /* 159 128 191 160 223 192 255 224 */
1139 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1140 /* 287 256 319 288 351 320 383 352 */
1141 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1142 /* 415 384 447 416 479 448 511 480 */
1143 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1145 /* ownDmaChannels */
1146 /* 31 0 63 32 */
1147 {0x00000000u, 0xFF000000u},
1149 /* ownQdmaChannels */
1150 /* 31 0 */
1151 {0x00000080u},
1153 /* ownTccs */
1154 /* 31 0 63 32 */
1155 {0x00000000u, 0xFF000000u},
1157 /* resvdPaRAMSets */
1158 /* 31 0 63 32 95 64 127 96 */
1159 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1160 /* 159 128 191 160 223 192 255 224 */
1161 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1162 /* 287 256 319 288 351 320 383 352 */
1163 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1164 /* 415 384 447 416 479 448 511 480 */
1165 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1167 /* resvdDmaChannels */
1168 /* 31 0 63 32 */
1169 {0x00000000u, 0x00000000u},
1171 /* resvdQdmaChannels */
1172 /* 31 0 */
1173 {0x00000000u},
1175 /* resvdTccs */
1176 /* 31 0 63 32 */
1177 {0x00000000u, 0x00000000u},
1178 },
1179 },
1180 }; /* sampleInstInitConfig */
1183 EDMA3_RM_GblConfigParams *libEdma3GblCfgParams = &sampleEdma3GblCfgParams[0];
1184 EDMA3_RM_InstanceInitConfig *libInstInitConfig = &sampleInstInitConfig[0][0];