[processor-sdk/performance-audio-sr.git] / psdk_cust / libarch_k2g_1_0_1_0 / examples / dsponly / libarch_c6678_config.c
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39 #include <xdc/std.h>
40 #include <ti/sdo/edma3/rm/edma3_rm.h>
41 #include <ti/sdo/fc/edma3/edma3_config.h>
43 #define EDMA_MGR_NUM_EDMA_INSTANCES 3
45 /* In the arrays below, each bit of a 32-bit word corresponds to a single */
46 /* PaRAMSet/EDMAChannel/QDMAChannel/TCC owned by the corresponding region, */
47 /* i.e., can be used for general purpose EDMA tranfers, or reserved for */
48 /* EDMA transfers by hardware peripherals (cannot be used for general */
49 /* purpose EDMA tranfers) */
51 #define DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x00000000u)
52 #define DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x00000000u)
54 /* EDMA3_InstanceInitConfig sample0 with region neither owning nor */
55 /* reserving any EDMA resources */
56 #define regionSample0 \
57 { \
58 /* Resources owned by Region */ \
59 /* ownPaRAMSets */ \
60 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
61 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
62 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
63 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
64 \
65 /* ownDmaChannels */ \
66 {0x00000000u, 0x00000000u}, \
67 \
68 /* ownQdmaChannels */ \
69 {0x00000000u}, \
70 \
71 /* ownTccs */ \
72 {0x00000000u, 0x00000000u}, \
73 \
74 /* Resources reserved by Region */ \
75 /* resvdPaRAMSets */ \
76 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
77 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
78 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
79 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
80 \
81 /* resvdDmaChannels */ \
82 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
83 \
84 /* resvdQdmaChannels */ \
85 {0x00000000u}, \
86 \
87 /* resvdTccs */ \
88 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
89 }
91 /* EDMA3_InstanceInitConfig sample1 with region owning PaRAM sets 64-105, */
92 /* and EDMA channel 0-7, but not reserving any EDMA resources */
93 /* Note that the first N PaRAM sets (N=number of EDMA channels available */
94 /* on an EDMA instance) are reserved in EDMA3 LLD ). */
95 #define regionSample1 \
96 { \
97 /* Resources owned by Region */ \
98 /* ownPaRAMSets */ \
99 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, \
100 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, \
101 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
102 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
103 \
104 /* ownDmaChannels */ \
105 {0x0000FFFFu, 0x00000000u}, \
106 \
107 /* ownQdmaChannels */ \
108 {0x00000000u}, \
109 \
110 /* ownTccs */ \
111 {0x0000FFFFu, 0x00000000u}, \
112 \
113 /* Resources reserved by Region */ \
114 /* resvdPaRAMSets */ \
115 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
116 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
117 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
118 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
119 \
120 /* resvdDmaChannels */ \
121 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
122 \
123 /* resvdQdmaChannels */ \
124 {0x00000000u}, \
125 \
126 /* resvdTccs */ \
127 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
128 }
131 /* EDMA3_InstanceInitConfig sample2 with region owning PaRAM sets 106-147, */
132 /* and EDMA channel 8-15, but not reserving any EDMA resources */
133 #define regionSample2 \
134 { \
135 /* Resources owned by Region */ \
136 /* ownPaRAMSets */ \
137 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
138 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, \
139 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
140 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
141 \
142 /* ownDmaChannels */ \
143 {0xFFFF0000u, 0x00000000u}, \
144 \
145 /* ownQdmaChannels */ \
146 {0x00000000u}, \
147 \
148 /* ownTccs */ \
149 {0xFFFF0000u, 0x00000000u}, \
150 \
151 /* Resources reserved by Region */ \
152 /* resvdPaRAMSets */ \
153 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
154 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
155 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
156 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
157 \
158 /* resvdDmaChannels */ \
159 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
160 \
161 /* resvdQdmaChannels */ \
162 {0x00000000u}, \
163 \
164 /* resvdTccs */ \
165 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
166 }
168 /* EDMA3_InstanceInitConfig sample3 with region owning PaRAM sets 148-189, */
169 /* and EDMA channel 16-23, but not reserving any EDMA resources */
170 #define regionSample3 \
171 { \
172 /* Resources owned by Region */ \
173 /* ownPaRAMSets */ \
174 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
175 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
176 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, \
177 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
178 \
179 /* ownDmaChannels */ \
180 {0x00000000u, 0x0000FFFFu}, \
181 \
182 /* ownQdmaChannels */ \
183 {0x00000000u}, \
184 \
185 /* ownTccs */ \
186 {0x00000000u, 0x0000FFFFu}, \
187 \
188 /* Resources reserved by Region */ \
189 /* resvdPaRAMSets */ \
190 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
191 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
192 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
193 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
194 \
195 /* resvdDmaChannels */ \
196 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
197 \
198 /* resvdQdmaChannels */ \
199 {0x00000000u}, \
200 \
201 /* resvdTccs */ \
202 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
203 }
205 /* EDMA3_InstanceInitConfig sample4 with region owning PaRAM sets 190-231, */
206 /* and EDMA channel 24-31, but not reserving any EDMA resources */
207 #define regionSample4 \
208 { \
209 /* Resources owned by Region */ \
210 /* ownPaRAMSets */ \
211 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
212 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
213 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu, \
214 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u}, \
215 \
216 /* ownDmaChannels */ \
217 {0x00000000u, 0xFFFF0000u}, \
218 \
219 /* ownQdmaChannels */ \
220 {0x00000000u}, \
221 \
222 /* ownTccs */ \
223 {0x00000000u, 0xFFFF0000u}, \
224 \
225 /* Resources reserved by Region */ \
226 /* resvdPaRAMSets */ \
227 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
228 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
229 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
230 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
231 \
232 /* resvdDmaChannels */ \
233 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
234 \
235 /* resvdQdmaChannels */ \
236 {0x00000000u}, \
237 \
238 /* resvdTccs */ \
239 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
240 }
242 #define NUM_EDMA_INSTANCES 3
243 const EDMA3_InstanceInitConfig C6678_config[NUM_EDMA_INSTANCES][EDMA3_MAX_REGIONS] =
244 {
245 /* EDMA3 INSTANCE# 0 */
246 { regionSample0, regionSample0, regionSample0, regionSample0,
247 regionSample0, regionSample0, regionSample0, regionSample0
248 },
249 /* EDMA3 INSTANCE# 1 */
250 { regionSample1, regionSample2, regionSample3, regionSample4,
251 regionSample0, regionSample0, regionSample0, regionSample0
252 },
253 /* EDMA3 INSTANCE# 2 */
254 { regionSample0, regionSample0, regionSample0, regionSample0,
255 regionSample1, regionSample2, regionSample3, regionSample4
256 }
257 };
259 const EDMA3_InstanceInitConfig edmaMgrInstanceInitConfig[EDMA_MGR_NUM_EDMA_INSTANCES][EDMA3_MAX_REGIONS] =
260 {
261 /* EDMA3 INSTANCE# 0 */
262 { regionSample0, regionSample0, regionSample0, regionSample0,
263 regionSample0, regionSample0, regionSample0, regionSample0
264 },
265 /* EDMA3 INSTANCE# 1 */
266 { regionSample1, regionSample2, regionSample3, regionSample4,
267 regionSample0, regionSample0, regionSample0, regionSample0
268 },
269 /* EDMA3 INSTANCE# 2 */
270 { regionSample0, regionSample0, regionSample0, regionSample0,
271 regionSample1, regionSample2, regionSample3, regionSample4
272 }
273 };
275 int32_t edmaMgrRegion2Instance[EDMA3_MAX_REGIONS] = {1,1,1,1,2,2,2,2};
277 /* Driver Object Initialization Configuration */
278 EDMA3_GblConfigParams edmaMgrGblConfigParams [EDMA_MGR_NUM_EDMA_INSTANCES] =
279 {
280 {
281 /* EDMA3 INSTANCE# 0 */
282 /** Total number of DMA Channels supported by the EDMA3 Controller */
283 16u,
284 /** Total number of QDMA Channels supported by the EDMA3 Controller */
285 8u,
286 /** Total number of TCCs supported by the EDMA3 Controller */
287 16u,
288 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
289 128u,
290 /** Total number of Event Queues in the EDMA3 Controller */
291 2u,
292 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
293 2u,
294 /** Number of Regions on this EDMA3 controller */
295 8u,
297 /**
298 * \brief Channel mapping existence
299 * A value of 0 (No channel mapping) implies that there is fixed association
300 * for a channel number to a parameter entry number or, in other words,
301 * PaRAM entry n corresponds to channel n.
302 */
303 1u,
305 /** Existence of memory protection feature */
306 1u,
308 /** Global Register Region of CC Registers */
309 (void *)0x02700000u,
310 /** Transfer Controller (TC) Registers */
311 {
312 (void *)0x02760000u,
313 (void *)0x02768000u,
314 (void *)NULL,
315 (void *)NULL,
316 (void *)NULL,
317 (void *)NULL,
318 (void *)NULL,
319 (void *)NULL
320 },
321 /** Interrupt no. for Transfer Completion */
322 38u,
323 /** Interrupt no. for CC Error */
324 32u,
325 /** Interrupt no. for TCs Error */
326 {
327 34u,
328 35u,
329 0u,
330 0u,
331 0u,
332 0u,
333 0u,
334 0u,
335 },
337 /**
338 * \brief EDMA3 TC priority setting
339 *
340 * User can program the priority of the Event Queues
341 * at a system-wide level. This means that the user can set the
342 * priority of an IO initiated by either of the TCs (Transfer Controllers)
343 * relative to IO initiated by the other bus masters on the
344 * device (ARM, DSP, USB, etc)
345 */
346 {
347 0u,
348 1u,
349 0u,
350 0u,
351 0u,
352 0u,
353 0u,
354 0u
355 },
356 /**
357 * \brief To Configure the Threshold level of number of events
358 * that can be queued up in the Event queues. EDMA3CC error register
359 * (CCERR) will indicate whether or not at any instant of time the
360 * number of events queued up in any of the event queues exceeds
361 * or equals the threshold/watermark value that is set
362 * in the queue watermark threshold register (QWMTHRA).
363 */
364 {
365 16u,
366 16u,
367 0u,
368 0u,
369 0u,
370 0u,
371 0u,
372 0u
373 },
375 /**
376 * \brief To Configure the Default Burst Size (DBS) of TCs.
377 * An optimally-sized command is defined by the transfer controller
378 * default burst size (DBS). Different TCs can have different
379 * DBS values. It is defined in Bytes.
380 */
381 {
382 128u,
383 128u,
384 0u,
385 0u,
386 0u,
387 0u,
388 0u,
389 0u
390 },
392 /**
393 * \brief Mapping from each DMA channel to a Parameter RAM set,
394 * if it exists, otherwise of no use.
395 */
396 {
397 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
398 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
399 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
400 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
401 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
402 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
403 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
404 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
405 /* DMA channels 16-63 DOES NOT exist */
406 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
407 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
408 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
409 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
410 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
411 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
412 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
413 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
414 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
415 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
416 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
417 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
418 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
419 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
420 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
421 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
422 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
423 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
424 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
425 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
426 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
427 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
428 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
429 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
430 },
432 /**
433 * \brief Mapping from each DMA channel to a TCC. This specific
434 * TCC code will be returned when the transfer is completed
435 * on the mapped channel.
436 */
437 {
438 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
439 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
440 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
441 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
442 /* DMA channels 16-63 DOES NOT exist */
443 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
444 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
445 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
446 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
447 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
448 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
449 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
450 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
451 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
452 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
453 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
454 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
455 },
457 /**
458 * \brief Mapping of DMA channels to Hardware Events from
459 * various peripherals, which use EDMA for data transfer.
460 * All channels need not be mapped, some can be free also.
461 */
462 {
463 0x00000000u,
464 0x00000000u
465 }
466 },
468 {
469 /* EDMA3 INSTANCE# 1 */
470 /** Total number of DMA Channels supported by the EDMA3 Controller */
471 64u,
472 /** Total number of QDMA Channels supported by the EDMA3 Controller */
473 8u,
474 /** Total number of TCCs supported by the EDMA3 Controller */
475 64u,
476 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
477 512u,
478 /** Total number of Event Queues in the EDMA3 Controller */
479 4u,
480 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
481 4u,
482 /** Number of Regions on this EDMA3 controller */
483 8u,
485 /**
486 * \brief Channel mapping existence
487 * A value of 0 (No channel mapping) implies that there is fixed association
488 * for a channel number to a parameter entry number or, in other words,
489 * PaRAM entry n corresponds to channel n.
490 */
491 1u,
493 /** Existence of memory protection feature */
494 1u,
496 /** Global Register Region of CC Registers */
497 (void *)0x02720000u,
498 /** Transfer Controller (TC) Registers */
499 {
500 (void *)0x02770000u,
501 (void *)0x02778000u,
502 (void *)0x02780000u,
503 (void *)0x02788000u,
504 (void *)NULL,
505 (void *)NULL,
506 (void *)NULL,
507 (void *)NULL
508 },
509 /** Interrupt no. for Transfer Completion */
510 8u,
511 /** Interrupt no. for CC Error */
512 0u,
513 /** Interrupt no. for TCs Error */
514 {
515 2u,
516 3u,
517 4u,
518 5u,
519 0u,
520 0u,
521 0u,
522 0u,
523 },
525 /**
526 * \brief EDMA3 TC priority setting
527 *
528 * User can program the priority of the Event Queues
529 * at a system-wide level. This means that the user can set the
530 * priority of an IO initiated by either of the TCs (Transfer Controllers)
531 * relative to IO initiated by the other bus masters on the
532 * device (ARM, DSP, USB, etc)
533 */
534 {
535 0u,
536 1u,
537 2u,
538 3u,
539 0u,
540 0u,
541 0u,
542 0u
543 },
544 /**
545 * \brief To Configure the Threshold level of number of events
546 * that can be queued up in the Event queues. EDMA3CC error register
547 * (CCERR) will indicate whether or not at any instant of time the
548 * number of events queued up in any of the event queues exceeds
549 * or equals the threshold/watermark value that is set
550 * in the queue watermark threshold register (QWMTHRA).
551 */
552 {
553 16u,
554 16u,
555 16u,
556 16u,
557 0u,
558 0u,
559 0u,
560 0u
561 },
563 /**
564 * \brief To Configure the Default Burst Size (DBS) of TCs.
565 * An optimally-sized command is defined by the transfer controller
566 * default burst size (DBS). Different TCs can have different
567 * DBS values. It is defined in Bytes.
568 */
569 {
570 128u,
571 64u,
572 128u,
573 64u,
574 0u,
575 0u,
576 0u,
577 0u
578 },
580 /**
581 * \brief Mapping from each DMA channel to a Parameter RAM set,
582 * if it exists, otherwise of no use.
583 */
584 {
585 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
586 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
587 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
588 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
589 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
590 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
591 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
592 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
593 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
594 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
595 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
596 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
597 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
598 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
599 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
600 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
601 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
602 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
603 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
604 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
605 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
606 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
607 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
608 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
609 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
610 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
611 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
612 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
613 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
614 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
615 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
616 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
617 },
619 /**
620 * \brief Mapping from each DMA channel to a TCC. This specific
621 * TCC code will be returned when the transfer is completed
622 * on the mapped channel.
623 */
624 {
625 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
626 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
627 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
628 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
629 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
630 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
631 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
632 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
633 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
634 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
635 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
636 },
638 /**
639 * \brief Mapping of DMA channels to Hardware Events from
640 * various peripherals, which use EDMA for data transfer.
641 * All channels need not be mapped, some can be free also.
642 */
643 {
644 0xFFFFFFFFu,
645 0xFF000000u
646 }
647 },
649 {
650 /* EDMA3 INSTANCE# 2 */
651 /** Total number of DMA Channels supported by the EDMA3 Controller */
652 64u,
653 /** Total number of QDMA Channels supported by the EDMA3 Controller */
654 8u,
655 /** Total number of TCCs supported by the EDMA3 Controller */
656 64u,
657 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
658 512u,
659 /** Total number of Event Queues in the EDMA3 Controller */
660 4u,
661 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
662 4u,
663 /** Number of Regions on this EDMA3 controller */
664 8u,
666 /**
667 * \brief Channel mapping existence
668 * A value of 0 (No channel mapping) implies that there is fixed association
669 * for a channel number to a parameter entry number or, in other words,
670 * PaRAM entry n corresponds to channel n.
671 */
672 1u,
674 /** Existence of memory protection feature */
675 1u,
677 /** Global Register Region of CC Registers */
678 (void *)0x02740000u,
679 /** Transfer Controller (TC) Registers */
680 {
681 (void *)0x02790000u,
682 (void *)0x02798000u,
683 (void *)0x027A0000u,
684 (void *)0x027A8000u,
685 (void *)NULL,
686 (void *)NULL,
687 (void *)NULL,
688 (void *)NULL
689 },
690 /** Interrupt no. for Transfer Completion */
691 24u,
692 /** Interrupt no. for CC Error */
693 16u,
694 /** Interrupt no. for TCs Error */
695 {
696 18u,
697 19u,
698 20u,
699 21u,
700 0u,
701 0u,
702 0u,
703 0u,
704 },
706 /**
707 * \brief EDMA3 TC priority setting
708 *
709 * User can program the priority of the Event Queues
710 * at a system-wide level. This means that the user can set the
711 * priority of an IO initiated by either of the TCs (Transfer Controllers)
712 * relative to IO initiated by the other bus masters on the
713 * device (ARM, DSP, USB, etc)
714 */
715 {
716 0u,
717 1u,
718 2u,
719 3u,
720 0u,
721 0u,
722 0u,
723 0u
724 },
725 /**
726 * \brief To Configure the Threshold level of number of events
727 * that can be queued up in the Event queues. EDMA3CC error register
728 * (CCERR) will indicate whether or not at any instant of time the
729 * number of events queued up in any of the event queues exceeds
730 * or equals the threshold/watermark value that is set
731 * in the queue watermark threshold register (QWMTHRA).
732 */
733 {
734 16u,
735 16u,
736 16u,
737 16u,
738 0u,
739 0u,
740 0u,
741 0u
742 },
744 /**
745 * \brief To Configure the Default Burst Size (DBS) of TCs.
746 * An optimally-sized command is defined by the transfer controller
747 * default burst size (DBS). Different TCs can have different
748 * DBS values. It is defined in Bytes.
749 */
750 {
751 128u,
752 64u,
753 64u,
754 128u,
755 0u,
756 0u,
757 0u,
758 0u
759 },
761 /**
762 * \brief Mapping from each DMA channel to a Parameter RAM set,
763 * if it exists, otherwise of no use.
764 */
765 {
766 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
767 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
768 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
769 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
770 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
771 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
772 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
773 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
774 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
775 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
776 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
777 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
778 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
779 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
780 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
781 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
782 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
783 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
784 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
785 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
786 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
787 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
788 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
789 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
790 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
791 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
792 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
793 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
794 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
795 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
796 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
797 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
798 },
800 /**
801 * \brief Mapping from each DMA channel to a TCC. This specific
802 * TCC code will be returned when the transfer is completed
803 * on the mapped channel.
804 */
805 {
806 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
807 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
808 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
809 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
810 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
811 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
812 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
813 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
814 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
815 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
816 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
817 },
819 /**
820 * \brief Mapping of DMA channels to Hardware Events from
821 * various peripherals, which use EDMA for data transfer.
822 * All channels need not be mapped, some can be free also.
823 */
824 {
825 0xFFFFFFFFu,
826 0xFF000000u
827 }
828 },
829 };
832 int32_t *ti_sdo_fc_edmamgr_region2Instance = (int32_t*)&edmaMgrRegion2Instance[0];
833 EDMA3_GblConfigParams *ti_sdo_fc_edmamgr_edma3GblConfigParams = (EDMA3_GblConfigParams*)&edmaMgrGblConfigParams[0];
834 EDMA3_InstanceInitConfig *ti_sdo_fc_edmamgr_edma3RegionConfig = (EDMA3_InstanceInitConfig*)&edmaMgrInstanceInitConfig[0][0];